[deliverable/binutils-gdb.git] / sim / v850 / sim-main.h

#ifndef SIM_MAIN_H
#define SIM_MAIN_H

/* General config options */

#define WITH_CORE
#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1


/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */

#define WITH_TARGET_WORD_MSB 31


#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-fpu.h"

typedef address_word sim_cia;

#include "sim-base.h"

#include "simops.h"
#include "bfd.h"


typedef signed8 int8;
typedef unsigned8 uint8;
typedef signed16 int16;
typedef unsigned16 uint16;
typedef signed32 int32;
typedef unsigned32 uint32;
typedef unsigned32 reg_t;


/* The current state of the processor; registers, memory, etc.  */

typedef struct _v850_regs {
  reg_t regs[32];		/* general-purpose registers */
  reg_t sregs[32];		/* system registers, including psw */
  reg_t pc;
  int dummy_mem;                /* where invalid accesses go */
  reg_t mpu0_sregs[28];         /* mpu0 system registers */
  reg_t mpu1_sregs[28];         /* mpu1 system registers */
  reg_t fpu_sregs[28];          /* fpu system registers */
} v850_regs;

struct _sim_cpu
{
  /* ... simulator specific members ... */
  v850_regs reg;
  reg_t psw_mask;               /* only allow non-reserved bits to be set */
  sim_event *pending_nmi;
  /* ... base type ... */
  sim_cpu_base base;
};

#define CIA_GET(CPU) ((CPU)->reg.pc + 0)
#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))

struct sim_state {
  sim_cpu cpu[MAX_NR_PROCESSORS];
#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif
#if 0
  SIM_ADDR rom_size;
  SIM_ADDR low_end;
  SIM_ADDR high_start;
  SIM_ADDR high_base;
  void *mem;
#endif
  sim_state_base base;
};

/* For compatibility, until all functions converted to passing
   SIM_DESC as an argument */
extern SIM_DESC simulator;


#define V850_ROM_SIZE 0x8000
#define V850_LOW_END 0x200000
#define V850_HIGH_START 0xffe000


/* Because we are still using the old semantic table, provide compat
   macro's that store the instruction where the old simops expects
   it. */

extern uint32 OP[4];
#if 0
OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
OP[3] = inst;
#endif

#define SAVE_1 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = 0; \
OP[3] = instruction_0

#define COMPAT_1(CALL) \
SAVE_1; \
PC += (CALL); \
nia = PC

#define SAVE_2 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = instruction_1; \
OP[3] = (instruction_1 << 16) | instruction_0

#define COMPAT_2(CALL) \
SAVE_2; \
PC += (CALL); \
nia = PC


/* new */
#define GR  ((CPU)->reg.regs)
#define SR  ((CPU)->reg.sregs)
#define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
#define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
#define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)

/* old */
#define State    (STATE_CPU (simulator, 0)->reg)
#define PC	(State.pc)
#define SP_REGNO        3
#define SP      (State.regs[SP_REGNO])
#define EP	(State.regs[30])

#define EIPC  (State.sregs[0])
#define EIPSW (State.sregs[1])
#define FEPC  (State.sregs[2])
#define FEPSW (State.sregs[3])
#define ECR   (State.sregs[4])
#define PSW   (State.sregs[5])
#define PSW_REGNO   5
#define EIIC  (State.sregs[13])
#define FEIC  (State.sregs[14])
#define DBIC  (SR[15])
#define CTPC  (SR[16])
#define CTPSW (SR[17])
#define DBPC  (State.sregs[18])
#define DBPSW (State.sregs[19])
#define CTBP  (State.sregs[20])
#define DIR   (SR[21])
#define EIWR  (SR[28])
#define FEWR  (SR[29])
#define DBWR  (SR[30])
#define BSEL  (SR[31])

#define PSW_US BIT32 (8)
#define PSW_NP 0x80
#define PSW_EP 0x40
#define PSW_ID 0x20
#define PSW_SAT 0x10
#define PSW_CY 0x8
#define PSW_OV 0x4
#define PSW_S 0x2
#define PSW_Z 0x1

#define PSW_NPV	(1<<18)
#define PSW_DMP	(1<<17)
#define PSW_IMP	(1<<16)

#define ECR_EICC 0x0000ffff
#define ECR_FECC 0xffff0000

/* FPU */

#define FPSR  (FPU_SR[6])
#define FPSR_REGNO 6
#define FPEPC (FPU_SR[7])
#define FPST  (FPU_SR[8])
#define FPST_REGNO 8
#define FPCC  (FPU_SR[9])
#define FPCFG (FPU_SR[10])
#define FPCFG_REGNO 10

#define FPSR_DEM  0x00200000
#define FPSR_SEM  0x00100000
#define FPSR_RM   0x000c0000
#define FPSR_RN   0x00000000
#define FPSR_FS   0x00020000
#define FPSR_PR   0x00010000

#define FPSR_XC   0x0000fc00
#define FPSR_XCE  0x00008000
#define FPSR_XCV  0x00004000
#define FPSR_XCZ  0x00002000
#define FPSR_XCO  0x00001000
#define FPSR_XCU  0x00000800
#define FPSR_XCI  0x00000400

#define FPSR_XE   0x000003e0
#define FPSR_XEV  0x00000200
#define FPSR_XEZ  0x00000100
#define FPSR_XEO  0x00000080
#define FPSR_XEU  0x00000040
#define FPSR_XEI  0x00000020

#define FPSR_XP   0x0000001f
#define FPSR_XPV  0x00000010
#define FPSR_XPZ  0x00000008
#define FPSR_XPO  0x00000004
#define FPSR_XPU  0x00000002
#define FPSR_XPI  0x00000001

#define FPST_PR   0x00008000 
#define FPST_XCE  0x00002000 
#define FPST_XCV  0x00001000 
#define FPST_XCZ  0x00000800 
#define FPST_XCO  0x00000400 
#define FPST_XCU  0x00000200 
#define FPST_XCI  0x00000100 

#define FPST_XPV  0x00000010 
#define FPST_XPZ  0x00000008 
#define FPST_XPO  0x00000004 
#define FPST_XPU  0x00000002 
#define FPST_XPI  0x00000001 

#define FPCFG_RM   0x00000180 
#define FPCFG_XEV  0x00000010 
#define FPCFG_XEZ  0x00000008 
#define FPCFG_XEO  0x00000004 
#define FPCFG_XEU  0x00000002 
#define FPCFG_XEI  0x00000001 

#define GET_FPCC()\
 ((FPSR >> 24) &0xf)

#define CLEAR_FPCC(bbb)\
  (FPSR &= ~(1 << (bbb+24)))

#define SET_FPCC(bbb)\
 (FPSR |= 1 << (bbb+24))

#define TEST_FPCC(bbb)\
  ((FPSR & (1 << (bbb+24))) != 0)

#define FPSR_GET_ROUND()					\
  (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near		\
   : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up	\
   : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down	\
   : sim_fpu_round_zero)


enum FPU_COMPARE {
  FPU_CMP_F = 0,
  FPU_CMP_UN,
  FPU_CMP_EQ,
  FPU_CMP_UEQ,
  FPU_CMP_OLT,
  FPU_CMP_ULT,
  FPU_CMP_OLE,
  FPU_CMP_ULE,
  FPU_CMP_SF,
  FPU_CMP_NGLE,
  FPU_CMP_SEQ,
  FPU_CMP_NGL,
  FPU_CMP_LT,
  FPU_CMP_NGE,
  FPU_CMP_LE,
  FPU_CMP_NGT
};


/* MPU */
#define MPM	(MPU1_SR[0])
#define MPC	(MPU1_SR[1])
#define MPC_REGNO 1
#define TID	(MPU1_SR[2])
#define PPA	(MPU1_SR[3])
#define PPM	(MPU1_SR[4])
#define PPC	(MPU1_SR[5])
#define DCC	(MPU1_SR[6])
#define DCV0	(MPU1_SR[7])
#define DCV1	(MPU1_SR[8])
#define SPAL	(MPU1_SR[10])
#define SPAU	(MPU1_SR[11])
#define IPA0L	(MPU1_SR[12])
#define IPA0U	(MPU1_SR[13])
#define IPA1L	(MPU1_SR[14])
#define IPA1U	(MPU1_SR[15])
#define IPA2L	(MPU1_SR[16])
#define IPA2U	(MPU1_SR[17])
#define IPA3L	(MPU1_SR[18])
#define IPA3U	(MPU1_SR[19])
#define DPA0L	(MPU1_SR[20])
#define DPA0U	(MPU1_SR[21])
#define DPA1L	(MPU1_SR[22])
#define DPA1U	(MPU1_SR[23])
#define DPA2L	(MPU1_SR[24])
#define DPA2U	(MPU1_SR[25])
#define DPA3L	(MPU1_SR[26])
#define DPA3U	(MPU1_SR[27])

#define PPC_PPE 0x1
#define SPAL_SPE 0x1
#define SPAL_SPS 0x10

#define VIP	(MPU0_SR[0])
#define VMECR	(MPU0_SR[4])
#define VMTID	(MPU0_SR[5])
#define VMADR	(MPU0_SR[6])
#define VPECR	(MPU0_SR[8])
#define VPTID	(MPU0_SR[9])
#define VPADR	(MPU0_SR[10])
#define VDECR	(MPU0_SR[12])
#define VDTID	(MPU0_SR[13])

#define MPM_AUE	0x2
#define MPM_MPE	0x1

#define VMECR_VMX   0x2
#define VMECR_VMR   0x4
#define VMECR_VMW   0x8
#define VMECR_VMS   0x10
#define VMECR_VMRMW 0x20
#define VMECR_VMMS  0x40

#define IPA2ADDR(IPA)	((IPA) & 0x1fffff80)
#define IPA_IPE	0x1 
#define IPA_IPX	0x2 
#define IPA_IPR	0x4 
#define IPE0	(IPA0L & IPA_IPE)
#define IPE1	(IPA1L & IPA_IPE)
#define IPE2	(IPA2L & IPA_IPE)
#define IPE3	(IPA3L & IPA_IPE)
#define IPX0	(IPA0L & IPA_IPX)
#define IPX1	(IPA1L & IPA_IPX)
#define IPX2	(IPA2L & IPA_IPX)
#define IPX3	(IPA3L & IPA_IPX)
#define IPR0	(IPA0L & IPA_IPR)
#define IPR1	(IPA1L & IPA_IPR)
#define IPR2	(IPA2L & IPA_IPR)
#define IPR3	(IPA3L & IPA_IPR)

#define DPA2ADDR(DPA)	((DPA) & 0x1fffff80)
#define DPA_DPE 0x1	
#define DPA_DPR 0x4	
#define DPA_DPW 0x8	
#define DPE0	(DPA0L & DPA_DPE)
#define DPE1	(DPA1L & DPA_DPE)
#define DPE2	(DPA2L & DPA_DPE)
#define DPE3	(DPA3L & DPA_DPE)
#define DPR0	(DPA0L & DPA_DPR)
#define DPR1	(DPA1L & DPA_DPR)
#define DPR2	(DPA2L & DPA_DPR)
#define DPR3	(DPA3L & DPA_DPR)
#define DPW0	(DPA0L & DPA_DPW)
#define DPW1	(DPA1L & DPA_DPW)
#define DPW2	(DPA2L & DPA_DPW)
#define DPW3	(DPA3L & DPA_DPW)

#define DCC_DCE0 0x1
#define DCC_DCE1 0x10000

#define PPA2ADDR(PPA)	((PPA) & 0x1fffff80) 
#define PPC_PPC 0xfffffffe
#define PPC_PPE 0x1
#define PPC_PPM 0x0000fff8


#define SEXT3(x)	((((x)&0x7)^(~0x3))+0x4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~0x7))+0x8)	

/* sign-extend a 5-bit number */
#define SEXT5(x)	((((x)&0x1f)^(~0xf))+0x10)	

/* sign-extend a 9-bit number */
#define SEXT9(x)	((((x)&0x1ff)^(~0xff))+0x100)

/* sign-extend a 22-bit number */
#define SEXT22(x)	((((x)&0x3fffff)^(~0x1fffff))+0x200000)

/* sign extend a 40 bit number */
#define SEXT40(x)	((((x) & UNSIGNED64 (0xffffffffff)) \
			  ^ (~UNSIGNED64 (0x7fffffffff))) \
			 + UNSIGNED64 (0x8000000000))

/* sign extend a 44 bit number */
#define SEXT44(x)	((((x) & UNSIGNED64 (0xfffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffff))) \
			 + UNSIGNED64 (0x80000000000))

/* sign extend a 60 bit number */
#define SEXT60(x)	((((x) & UNSIGNED64 (0xfffffffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
			 + UNSIGNED64 (0x800000000000000))

/* No sign extension */
#define NOP(x)		(x)

#define INC_ADDR(x,i)	x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))

#define RLW(x) load_mem (x, 4)

/* Function declarations.  */

#define IMEM16(EA) \
sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))

#define IMEM16_IMMED(EA,N) \
sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
			 PC, exec_map, (EA) + (N) * 2)

#define load_mem(ADDR,LEN) \
sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
			       PC, read_map, (ADDR))

#define store_mem(ADDR,LEN,DATA) \
sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
				PC, write_map, (ADDR), (DATA))


/* compare cccc field against PSW */
int condition_met (unsigned code);


/* Debug/tracing calls */

enum op_types
{
  OP_UNKNOWN,
  OP_NONE,
  OP_TRAP,
  OP_REG,
  OP_REG_REG,
  OP_REG_REG_CMP,
  OP_REG_REG_MOVE,
  OP_IMM_REG,
  OP_IMM_REG_CMP,
  OP_IMM_REG_MOVE,
  OP_COND_BR,
  OP_LOAD16,
  OP_STORE16,
  OP_LOAD32,
  OP_STORE32,
  OP_JUMP,
  OP_IMM_REG_REG,
  OP_UIMM_REG_REG,
  OP_IMM16_REG_REG,
  OP_UIMM16_REG_REG,
  OP_BIT,
  OP_EX1,
  OP_EX2,
  OP_LDSR,
  OP_STSR,
  OP_BIT_CHANGE,
  OP_REG_REG_REG,
  OP_REG_REG3,
  OP_IMM_REG_REG_REG,
  OP_PUSHPOP1,
  OP_PUSHPOP2,
  OP_PUSHPOP3,
};

#ifdef DEBUG
void trace_input (char *name, enum op_types type, int size);
void trace_output (enum op_types result);
void trace_result (int has_result, unsigned32 result);

extern int trace_num_values;
extern unsigned32 trace_values[];
extern unsigned32 trace_pc;
extern const char *trace_name;
extern int trace_module;

#define TRACE_BRANCH0() \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_num_values = 0; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH1(IN1) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_num_values = 1; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH2(IN1, IN2) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_num_values = 2; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH3(IN1, IN2, IN3) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_values[2] = (IN3); \
    trace_num_values = 3; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_LD(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = (NAME); \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_ST(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_FP_INPUT_FPU1(V0)	\
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0; \
      sim_fpu_to64 (&f0, (V0)); \
      trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
    } \
} while (0)

#define TRACE_FP_INPUT_FPU2(V0, V1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0, f1; \
      sim_fpu_to64 (&f0, (V0)); \
      sim_fpu_to64 (&f1, (V1)); \
      trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1);	\
    } \
} while (0)

#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0, f1, f2; \
      sim_fpu_to64 (&f0, (V0)); \
      sim_fpu_to64 (&f1, (V1)); \
      sim_fpu_to64 (&f2, (V2)); \
      trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
    } \
} while (0)

#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      int d0 = (V0); \
      unsigned64 f1, f2; \
      TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
      TRACE_IDX (data) = TRACE_FPU_IDX;	\
      sim_fpu_to64 (&f1, (V1)); \
      sim_fpu_to64 (&f2, (V2)); \
      save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
      save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
      save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
    } \
} while (0)

#define TRACE_FP_INPUT_WORD2(V0, V1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
} while (0)

#define TRACE_FP_RESULT_FPU1(R0) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0; \
      sim_fpu_to64 (&f0, (R0));	\
      trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
    } \
} while (0)

#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)

#define TRACE_FP_RESULT_WORD2(R0, R1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
} while (0)

#else
#define trace_input(NAME, IN1, IN2)
#define trace_output(RESULT)
#define trace_result(HAS_RESULT, RESULT)

#define TRACE_ALU_INPUT0()
#define TRACE_ALU_INPUT1(IN0)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
#define TRACE_ALU_RESULT(RESULT)

#define TRACE_BRANCH0()
#define TRACE_BRANCH1(IN1)
#define TRACE_BRANCH2(IN1, IN2)
#define TRACE_BRANCH2(IN1, IN2, IN3)

#define TRACE_LD(ADDR,RESULT)
#define TRACE_ST(ADDR,RESULT)

#endif

#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
#define GPR_CLEAR(N)    (State.regs[(N)] = 0)

extern void divun ( unsigned int       N,
		    unsigned long int  als,
		    unsigned long int  sfi,
		    unsigned32 /*unsigned long int*/ *  quotient_ptr,
		    unsigned32 /*unsigned long int*/ *  remainder_ptr,
		    int *overflow_ptr
		    );
extern void divn ( unsigned int       N,
		   unsigned long int  als,
		   unsigned long int  sfi,
		   signed32 /*signed long int*/ *  quotient_ptr,
		   signed32 /*signed long int*/ *  remainder_ptr,
		   int *overflow_ptr
		   );
extern int type1_regs[];
extern int type2_regs[];
extern int type3_regs[];

#endif
Commit	Line	Data
c906108c SS	1	#ifndef SIM_MAIN_H
	2	#define SIM_MAIN_H
	3
	4	/* General config options */
	5
	6	#define WITH_CORE
	7	#define WITH_MODULO_MEMORY 1
	8	#define WITH_WATCHPOINTS 1
	9
	10
	11	/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
	12
	13	#define WITH_TARGET_WORD_MSB 31
	14
	15
	16	#include "sim-basics.h"
	17	#include "sim-signal.h"
2aaed979	18	#include "sim-fpu.h"
c906108c SS	19
	20	typedef address_word sim_cia;
	21
	22	#include "sim-base.h"
	23
	24	#include "simops.h"
	25	#include "bfd.h"
	26
	27
	28	typedef signed8 int8;
	29	typedef unsigned8 uint8;
	30	typedef signed16 int16;
	31	typedef unsigned16 uint16;
	32	typedef signed32 int32;
	33	typedef unsigned32 uint32;
	34	typedef unsigned32 reg_t;
	35
	36
	37	/* The current state of the processor; registers, memory, etc. */
	38
	39	typedef struct _v850_regs {
	40	reg_t regs[32]; /* general-purpose registers */
	41	reg_t sregs[32]; /* system registers, including psw */
	42	reg_t pc;
2aaed979 KB	43	int dummy_mem; /* where invalid accesses go */
	44	reg_t mpu0_sregs[28]; /* mpu0 system registers */
	45	reg_t mpu1_sregs[28]; /* mpu1 system registers */
	46	reg_t fpu_sregs[28]; /* fpu system registers */
c906108c SS	47	} v850_regs;
	48
	49	struct _sim_cpu
	50	{
	51	/* ... simulator specific members ... */
	52	v850_regs reg;
	53	reg_t psw_mask; /* only allow non-reserved bits to be set */
	54	sim_event *pending_nmi;
	55	/* ... base type ... */
	56	sim_cpu_base base;
	57	};
	58
	59	#define CIA_GET(CPU) ((CPU)->reg.pc + 0)
	60	#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
	61
	62	struct sim_state {
	63	sim_cpu cpu[MAX_NR_PROCESSORS];
	64	#if (WITH_SMP)
	65	#define STATE_CPU(sd,n) (&(sd)->cpu[n])
	66	#else
	67	#define STATE_CPU(sd,n) (&(sd)->cpu[0])
	68	#endif
	69	#if 0
	70	SIM_ADDR rom_size;
	71	SIM_ADDR low_end;
	72	SIM_ADDR high_start;
	73	SIM_ADDR high_base;
	74	void *mem;
	75	#endif
	76	sim_state_base base;
	77	};
	78
	79	/* For compatibility, until all functions converted to passing
	80	SIM_DESC as an argument */
	81	extern SIM_DESC simulator;
	82
	83
	84	#define V850_ROM_SIZE 0x8000
	85	#define V850_LOW_END 0x200000
	86	#define V850_HIGH_START 0xffe000
	87
	88
	89	/* Because we are still using the old semantic table, provide compat
	90	macro's that store the instruction where the old simops expects
	91	it. */
	92
	93	extern uint32 OP[4];
	94	#if 0
	95	OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
	96	OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
	97	OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
	98	OP[3] = inst;
	99	#endif
	100
	101	#define SAVE_1 \
	102	PC = cia; \
	103	OP[0] = instruction_0 & 0x1f; \
	104	OP[1] = (instruction_0 >> 11) & 0x1f; \
	105	OP[2] = 0; \
	106	OP[3] = instruction_0
	107
	108	#define COMPAT_1(CALL) \
	109	SAVE_1; \
	110	PC += (CALL); \
111	nia = PC
112
113	#define SAVE_2 \
114	PC = cia; \
115	OP[0] = instruction_0 & 0x1f; \
116	OP[1] = (instruction_0 >> 11) & 0x1f; \
117	OP[2] = instruction_1; \
118	OP[3] = (instruction_1 << 16) \| instruction_0
119
120	#define COMPAT_2(CALL) \
121	SAVE_2; \
122	PC += (CALL); \
123	nia = PC
124
125
126	/* new */
127	#define GR ((CPU)->reg.regs)
128	#define SR ((CPU)->reg.sregs)
2aaed979 KB	129	#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
	130	#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
	131	#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
c906108c SS	132
	133	/* old */
	134	#define State (STATE_CPU (simulator, 0)->reg)
	135	#define PC (State.pc)
2aaed979 KB	136	#define SP_REGNO 3
2aaed979 KB	137	#define SP (State.regs[SP_REGNO])
c906108c SS	138	#define EP (State.regs[30])
	139
	140	#define EIPC (State.sregs[0])
	141	#define EIPSW (State.sregs[1])
	142	#define FEPC (State.sregs[2])
	143	#define FEPSW (State.sregs[3])
	144	#define ECR (State.sregs[4])
	145	#define PSW (State.sregs[5])
2aaed979 KB	146	#define PSW_REGNO 5
	147	#define EIIC (State.sregs[13])
	148	#define FEIC (State.sregs[14])
	149	#define DBIC (SR[15])
c906108c SS	150	#define CTPC (SR[16])
	151	#define CTPSW (SR[17])
	152	#define DBPC (State.sregs[18])
	153	#define DBPSW (State.sregs[19])
	154	#define CTBP (State.sregs[20])
2aaed979 KB	155	#define DIR (SR[21])
	156	#define EIWR (SR[28])
	157	#define FEWR (SR[29])
	158	#define DBWR (SR[30])
	159	#define BSEL (SR[31])
c906108c SS	160
	161	#define PSW_US BIT32 (8)
	162	#define PSW_NP 0x80
	163	#define PSW_EP 0x40
	164	#define PSW_ID 0x20
	165	#define PSW_SAT 0x10
	166	#define PSW_CY 0x8
	167	#define PSW_OV 0x4
	168	#define PSW_S 0x2
	169	#define PSW_Z 0x1
	170
2aaed979 KB	171	#define PSW_NPV (1<<18)
	172	#define PSW_DMP (1<<17)
	173	#define PSW_IMP (1<<16)
	174
	175	#define ECR_EICC 0x0000ffff
	176	#define ECR_FECC 0xffff0000
	177
	178	/* FPU */
	179
	180	#define FPSR (FPU_SR[6])
	181	#define FPSR_REGNO 6
	182	#define FPEPC (FPU_SR[7])
	183	#define FPST (FPU_SR[8])
	184	#define FPST_REGNO 8
	185	#define FPCC (FPU_SR[9])
	186	#define FPCFG (FPU_SR[10])
	187	#define FPCFG_REGNO 10
	188
	189	#define FPSR_DEM 0x00200000
	190	#define FPSR_SEM 0x00100000
	191	#define FPSR_RM 0x000c0000
	192	#define FPSR_RN 0x00000000
	193	#define FPSR_FS 0x00020000
	194	#define FPSR_PR 0x00010000
	195
	196	#define FPSR_XC 0x0000fc00
	197	#define FPSR_XCE 0x00008000
	198	#define FPSR_XCV 0x00004000
	199	#define FPSR_XCZ 0x00002000
	200	#define FPSR_XCO 0x00001000
	201	#define FPSR_XCU 0x00000800
	202	#define FPSR_XCI 0x00000400
	203
	204	#define FPSR_XE 0x000003e0
	205	#define FPSR_XEV 0x00000200
	206	#define FPSR_XEZ 0x00000100
	207	#define FPSR_XEO 0x00000080
	208	#define FPSR_XEU 0x00000040
	209	#define FPSR_XEI 0x00000020
	210
	211	#define FPSR_XP 0x0000001f
	212	#define FPSR_XPV 0x00000010
	213	#define FPSR_XPZ 0x00000008
	214	#define FPSR_XPO 0x00000004
	215	#define FPSR_XPU 0x00000002
	216	#define FPSR_XPI 0x00000001
	217
	218	#define FPST_PR 0x00008000
	219	#define FPST_XCE 0x00002000
	220	#define FPST_XCV 0x00001000
	221	#define FPST_XCZ 0x00000800
	222	#define FPST_XCO 0x00000400
	223	#define FPST_XCU 0x00000200
	224	#define FPST_XCI 0x00000100
	225
	226	#define FPST_XPV 0x00000010
	227	#define FPST_XPZ 0x00000008
	228	#define FPST_XPO 0x00000004
	229	#define FPST_XPU 0x00000002
	230	#define FPST_XPI 0x00000001
	231
	232	#define FPCFG_RM 0x00000180
	233	#define FPCFG_XEV 0x00000010
	234	#define FPCFG_XEZ 0x00000008
235	#define FPCFG_XEO 0x00000004
236	#define FPCFG_XEU 0x00000002
237	#define FPCFG_XEI 0x00000001
238
239	#define GET_FPCC()\
240	((FPSR >> 24) &0xf)
241
242	#define CLEAR_FPCC(bbb)\
243	(FPSR &= ~(1 << (bbb+24)))
244
245	#define SET_FPCC(bbb)\
246	(FPSR \|= 1 << (bbb+24))
247
248	#define TEST_FPCC(bbb)\
249	((FPSR & (1 << (bbb+24))) != 0)
250
251	#define FPSR_GET_ROUND() \
252	(((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
253	: ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
254	: ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
255	: sim_fpu_round_zero)
256
257
258	enum FPU_COMPARE {
259	FPU_CMP_F = 0,
260	FPU_CMP_UN,
261	FPU_CMP_EQ,
262	FPU_CMP_UEQ,
263	FPU_CMP_OLT,
264	FPU_CMP_ULT,
265	FPU_CMP_OLE,
266	FPU_CMP_ULE,
267	FPU_CMP_SF,
268	FPU_CMP_NGLE,
269	FPU_CMP_SEQ,
270	FPU_CMP_NGL,
271	FPU_CMP_LT,
272	FPU_CMP_NGE,
273	FPU_CMP_LE,
274	FPU_CMP_NGT
275	};
276
277
278	/* MPU */
279	#define MPM (MPU1_SR[0])
280	#define MPC (MPU1_SR[1])
281	#define MPC_REGNO 1
282	#define TID (MPU1_SR[2])
283	#define PPA (MPU1_SR[3])
284	#define PPM (MPU1_SR[4])
285	#define PPC (MPU1_SR[5])
286	#define DCC (MPU1_SR[6])
287	#define DCV0 (MPU1_SR[7])
288	#define DCV1 (MPU1_SR[8])
289	#define SPAL (MPU1_SR[10])
290	#define SPAU (MPU1_SR[11])
291	#define IPA0L (MPU1_SR[12])
292	#define IPA0U (MPU1_SR[13])
293	#define IPA1L (MPU1_SR[14])
294	#define IPA1U (MPU1_SR[15])
295	#define IPA2L (MPU1_SR[16])
296	#define IPA2U (MPU1_SR[17])
297	#define IPA3L (MPU1_SR[18])
298	#define IPA3U (MPU1_SR[19])
299	#define DPA0L (MPU1_SR[20])
300	#define DPA0U (MPU1_SR[21])
301	#define DPA1L (MPU1_SR[22])
302	#define DPA1U (MPU1_SR[23])
303	#define DPA2L (MPU1_SR[24])
304	#define DPA2U (MPU1_SR[25])
305	#define DPA3L (MPU1_SR[26])
306	#define DPA3U (MPU1_SR[27])
307
308	#define PPC_PPE 0x1
309	#define SPAL_SPE 0x1
310	#define SPAL_SPS 0x10
311
312	#define VIP (MPU0_SR[0])
313	#define VMECR (MPU0_SR[4])
314	#define VMTID (MPU0_SR[5])
315	#define VMADR (MPU0_SR[6])
316	#define VPECR (MPU0_SR[8])
317	#define VPTID (MPU0_SR[9])
318	#define VPADR (MPU0_SR[10])
319	#define VDECR (MPU0_SR[12])
320	#define VDTID (MPU0_SR[13])
321
322	#define MPM_AUE 0x2
323	#define MPM_MPE 0x1
324
325	#define VMECR_VMX 0x2
326	#define VMECR_VMR 0x4
327	#define VMECR_VMW 0x8
328	#define VMECR_VMS 0x10
329	#define VMECR_VMRMW 0x20
330	#define VMECR_VMMS 0x40
331
332	#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
333	#define IPA_IPE 0x1
334	#define IPA_IPX 0x2
335	#define IPA_IPR 0x4
336	#define IPE0 (IPA0L & IPA_IPE)
337	#define IPE1 (IPA1L & IPA_IPE)
338	#define IPE2 (IPA2L & IPA_IPE)
339	#define IPE3 (IPA3L & IPA_IPE)
340	#define IPX0 (IPA0L & IPA_IPX)
341	#define IPX1 (IPA1L & IPA_IPX)
342	#define IPX2 (IPA2L & IPA_IPX)
343	#define IPX3 (IPA3L & IPA_IPX)
344	#define IPR0 (IPA0L & IPA_IPR)
345	#define IPR1 (IPA1L & IPA_IPR)
346	#define IPR2 (IPA2L & IPA_IPR)
347	#define IPR3 (IPA3L & IPA_IPR)
348
349	#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
350	#define DPA_DPE 0x1
351	#define DPA_DPR 0x4
352	#define DPA_DPW 0x8
353	#define DPE0 (DPA0L & DPA_DPE)
354	#define DPE1 (DPA1L & DPA_DPE)
355	#define DPE2 (DPA2L & DPA_DPE)
356	#define DPE3 (DPA3L & DPA_DPE)
357	#define DPR0 (DPA0L & DPA_DPR)
358	#define DPR1 (DPA1L & DPA_DPR)
359	#define DPR2 (DPA2L & DPA_DPR)
360	#define DPR3 (DPA3L & DPA_DPR)
361	#define DPW0 (DPA0L & DPA_DPW)
362	#define DPW1 (DPA1L & DPA_DPW)
363	#define DPW2 (DPA2L & DPA_DPW)
364	#define DPW3 (DPA3L & DPA_DPW)
365
366	#define DCC_DCE0 0x1
367	#define DCC_DCE1 0x10000
368
369	#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
370	#define PPC_PPC 0xfffffffe
371	#define PPC_PPE 0x1
372	#define PPC_PPM 0x0000fff8
373
374
c906108c SS	375	#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
	376
	377	/* sign-extend a 4-bit number */
	378	#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
	379
	380	/* sign-extend a 5-bit number */
	381	#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
	382
	383	/* sign-extend a 9-bit number */
	384	#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
	385
	386	/* sign-extend a 22-bit number */
	387	#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
	388
	389	/* sign extend a 40 bit number */
	390	#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
	391	^ (~UNSIGNED64 (0x7fffffffff))) \
	392	+ UNSIGNED64 (0x8000000000))
	393
	394	/* sign extend a 44 bit number */
	395	#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
	396	^ (~ UNSIGNED64 (0x7ffffffffff))) \
	397	+ UNSIGNED64 (0x80000000000))
	398
	399	/* sign extend a 60 bit number */
	400	#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
	401	^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
	402	+ UNSIGNED64 (0x800000000000000))
	403
	404	/* No sign extension */
	405	#define NOP(x) (x)
	406
	407	#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
	408
	409	#define RLW(x) load_mem (x, 4)
	410
	411	/* Function declarations. */
	412
	413	#define IMEM16(EA) \
	414	sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
	415
	416	#define IMEM16_IMMED(EA,N) \
	417	sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
	418	PC, exec_map, (EA) + (N) * 2)
	419
	420	#define load_mem(ADDR,LEN) \
	421	sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
	422	PC, read_map, (ADDR))
	423
	424	#define store_mem(ADDR,LEN,DATA) \
	425	sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
	426	PC, write_map, (ADDR), (DATA))
	427
	428
	429	/* compare cccc field against PSW */
	430	int condition_met (unsigned code);
	431
	432
	433	/* Debug/tracing calls */
	434
	435	enum op_types
	436	{
	437	OP_UNKNOWN,
	438	OP_NONE,
439	OP_TRAP,
440	OP_REG,
441	OP_REG_REG,
442	OP_REG_REG_CMP,
443	OP_REG_REG_MOVE,
444	OP_IMM_REG,
445	OP_IMM_REG_CMP,
446	OP_IMM_REG_MOVE,
447	OP_COND_BR,
448	OP_LOAD16,
449	OP_STORE16,
450	OP_LOAD32,
451	OP_STORE32,
452	OP_JUMP,
453	OP_IMM_REG_REG,
454	OP_UIMM_REG_REG,
455	OP_IMM16_REG_REG,
456	OP_UIMM16_REG_REG,
457	OP_BIT,
458	OP_EX1,
459	OP_EX2,
460	OP_LDSR,
461	OP_STSR,
462	OP_BIT_CHANGE,
463	OP_REG_REG_REG,
464	OP_REG_REG3,
465	OP_IMM_REG_REG_REG,
466	OP_PUSHPOP1,
467	OP_PUSHPOP2,
468	OP_PUSHPOP3,
469	};
470
471	#ifdef DEBUG
bdca5ee4 TT	472	void trace_input (char *name, enum op_types type, int size);
	473	void trace_output (enum op_types result);
	474	void trace_result (int has_result, unsigned32 result);
c906108c SS	475
	476	extern int trace_num_values;
	477	extern unsigned32 trace_values[];
	478	extern unsigned32 trace_pc;
	479	extern const char *trace_name;
	480	extern int trace_module;
	481
	482	#define TRACE_BRANCH0() \
	483	do { \
	484	if (TRACE_BRANCH_P (CPU)) { \
	485	trace_module = TRACE_BRANCH_IDX; \
	486	trace_pc = cia; \
	487	trace_name = itable[MY_INDEX].name; \
	488	trace_num_values = 0; \
	489	trace_result (1, (nia)); \
	490	} \
	491	} while (0)
	492
	493	#define TRACE_BRANCH1(IN1) \
	494	do { \
	495	if (TRACE_BRANCH_P (CPU)) { \
	496	trace_module = TRACE_BRANCH_IDX; \
	497	trace_pc = cia; \
	498	trace_name = itable[MY_INDEX].name; \
	499	trace_values[0] = (IN1); \
	500	trace_num_values = 1; \
	501	trace_result (1, (nia)); \
	502	} \
	503	} while (0)
	504
	505	#define TRACE_BRANCH2(IN1, IN2) \
	506	do { \
	507	if (TRACE_BRANCH_P (CPU)) { \
	508	trace_module = TRACE_BRANCH_IDX; \
	509	trace_pc = cia; \
	510	trace_name = itable[MY_INDEX].name; \
	511	trace_values[0] = (IN1); \
	512	trace_values[1] = (IN2); \
	513	trace_num_values = 2; \
	514	trace_result (1, (nia)); \
	515	} \
	516	} while (0)
	517
	518	#define TRACE_BRANCH3(IN1, IN2, IN3) \
	519	do { \
	520	if (TRACE_BRANCH_P (CPU)) { \
	521	trace_module = TRACE_BRANCH_IDX; \
	522	trace_pc = cia; \
	523	trace_name = itable[MY_INDEX].name; \
	524	trace_values[0] = (IN1); \
	525	trace_values[1] = (IN2); \
	526	trace_values[2] = (IN3); \
	527	trace_num_values = 3; \
	528	trace_result (1, (nia)); \
	529	} \
	530	} while (0)
	531
	532	#define TRACE_LD(ADDR,RESULT) \
	533	do { \
	534	if (TRACE_MEMORY_P (CPU)) { \
	535	trace_module = TRACE_MEMORY_IDX; \
	536	trace_pc = cia; \
	537	trace_name = itable[MY_INDEX].name; \
	538	trace_values[0] = (ADDR); \
539	trace_num_values = 1; \
540	trace_result (1, (RESULT)); \
541	} \
542	} while (0)
543
544	#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
545	do { \
546	if (TRACE_MEMORY_P (CPU)) { \
547	trace_module = TRACE_MEMORY_IDX; \
548	trace_pc = cia; \
549	trace_name = (NAME); \
550	trace_values[0] = (ADDR); \
551	trace_num_values = 1; \
552	trace_result (1, (RESULT)); \
553	} \
554	} while (0)
555
556	#define TRACE_ST(ADDR,RESULT) \
557	do { \
558	if (TRACE_MEMORY_P (CPU)) { \
559	trace_module = TRACE_MEMORY_IDX; \
560	trace_pc = cia; \
561	trace_name = itable[MY_INDEX].name; \
562	trace_values[0] = (ADDR); \
563	trace_num_values = 1; \
564	trace_result (1, (RESULT)); \
565	} \
566	} while (0)
567
2aaed979 KB	568	#define TRACE_FP_INPUT_FPU1(V0) \
	569	do { \
	570	if (TRACE_FPU_P (CPU)) \
	571	{ \
	572	unsigned64 f0; \
	573	sim_fpu_to64 (&f0, (V0)); \
	574	trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
	575	} \
	576	} while (0)
	577
	578	#define TRACE_FP_INPUT_FPU2(V0, V1) \
	579	do { \
	580	if (TRACE_FPU_P (CPU)) \
	581	{ \
	582	unsigned64 f0, f1; \
	583	sim_fpu_to64 (&f0, (V0)); \
	584	sim_fpu_to64 (&f1, (V1)); \
	585	trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
	586	} \
	587	} while (0)
	588
	589	#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
	590	do { \
	591	if (TRACE_FPU_P (CPU)) \
	592	{ \
	593	unsigned64 f0, f1, f2; \
	594	sim_fpu_to64 (&f0, (V0)); \
	595	sim_fpu_to64 (&f1, (V1)); \
	596	sim_fpu_to64 (&f2, (V2)); \
	597	trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
	598	} \
	599	} while (0)
	600
	601	#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
	602	do { \
	603	if (TRACE_FPU_P (CPU)) \
	604	{ \
	605	int d0 = (V0); \
	606	unsigned64 f1, f2; \
	607	TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
	608	TRACE_IDX (data) = TRACE_FPU_IDX; \
	609	sim_fpu_to64 (&f1, (V1)); \
	610	sim_fpu_to64 (&f2, (V2)); \
	611	save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
	612	save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
	613	save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
	614	} \
	615	} while (0)
	616
	617	#define TRACE_FP_INPUT_WORD2(V0, V1) \
	618	do { \
	619	if (TRACE_FPU_P (CPU)) \
	620	trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
	621	} while (0)
	622
	623	#define TRACE_FP_RESULT_FPU1(R0) \
	624	do { \
	625	if (TRACE_FPU_P (CPU)) \
	626	{ \
	627	unsigned64 f0; \
	628	sim_fpu_to64 (&f0, (R0)); \
	629	trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
	630	} \
	631	} while (0)
632
633	#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
634
635	#define TRACE_FP_RESULT_WORD2(R0, R1) \
636	do { \
637	if (TRACE_FPU_P (CPU)) \
638	trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
639	} while (0)
640
c906108c SS	641	#else
	642	#define trace_input(NAME, IN1, IN2)
	643	#define trace_output(RESULT)
	644	#define trace_result(HAS_RESULT, RESULT)
	645
	646	#define TRACE_ALU_INPUT0()
	647	#define TRACE_ALU_INPUT1(IN0)
	648	#define TRACE_ALU_INPUT2(IN0, IN1)
	649	#define TRACE_ALU_INPUT2(IN0, IN1)
	650	#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
	651	#define TRACE_ALU_RESULT(RESULT)
	652
	653	#define TRACE_BRANCH0()
	654	#define TRACE_BRANCH1(IN1)
	655	#define TRACE_BRANCH2(IN1, IN2)
	656	#define TRACE_BRANCH2(IN1, IN2, IN3)
	657
	658	#define TRACE_LD(ADDR,RESULT)
	659	#define TRACE_ST(ADDR,RESULT)
	660
	661	#endif
	662
e551c257 NC	663	#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
e551c257 NC	664	#define GPR_CLEAR(N) (State.regs[(N)] = 0)
c906108c SS	665
	666	extern void divun ( unsigned int N,
	667	unsigned long int als,
	668	unsigned long int sfi,
	669	unsigned32 /unsigned long int/ * quotient_ptr,
	670	unsigned32 /unsigned long int/ * remainder_ptr,
0da2b665	671	int *overflow_ptr
c906108c SS	672	);
	673	extern void divn ( unsigned int N,
	674	unsigned long int als,
	675	unsigned long int sfi,
	676	signed32 /signed long int/ * quotient_ptr,
	677	signed32 /signed long int/ * remainder_ptr,
0da2b665	678	int *overflow_ptr
c906108c SS	679	);
	680	extern int type1_regs[];
	681	extern int type2_regs[];
	682	extern int type3_regs[];
	683
	684	#endif