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* gx prototype: simulator I/O bug fix
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
CommitLineData
22c1c7dd 1#include <signal.h>
9cdd2c6d 2#include "sim-main.h"
22c1c7dd
JL		 3#include "v850_sim.h"
4#include "simops.h"
9cdd2c6d
AC		 5
6#ifdef HAVE_UTIME_H
7#include <utime.h>
b5e935ae
AC		 8#endif
9
10#ifdef HAVE_TIME_H
11#include <time.h>
da3a66e5
AC		 12#endif
13
14#ifdef HAVE_UNISTD_H
15#include <unistd.h>
9cdd2c6d
AC		 16#endif
17
5d37a07b
AC		 18#ifdef HAVE_STRING_H
19#include <string.h>
20#else
21#ifdef HAVE_STRINGS_H
22#include <strings.h>
23#endif
24#endif
25
26
27
28
29
0ffba68f
AC		 30 /* FIXME - should be including a version of syscall.h that does not
31 pollute the name space */
32#include "../../libgloss/v850/sys/syscall.h"
9cdd2c6d 33
da3a66e5
AC		 34#include "libiberty.h"
35
96851909 36#include <errno.h>
87e43259 37#if !defined(__GO32__) && !defined(_WIN32)
c500c074 38#include <sys/stat.h>
8824fb45 39#include <sys/times.h>
7fc45edb 40#include <sys/time.h>
87e43259 41#endif
22c1c7dd 42
70caad98 43/* start-sanitize-v850e */
bda61639
AC		 44/* This is an array of the bit positions of registers r20 .. r31 in
45 that order in a prepare/dispose instruction. */
46int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
70caad98
NC		 47/* end-sanitize-v850e */
48/* start-sanitize-v850eq */
bda61639
AC		 49/* This is an array of the bit positions of registers r16 .. r31 in
50 that order in a push/pop instruction. */
51int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
52/* This is an array of the bit positions of registers r1 .. r15 in
53 that order in a push/pop instruction. */
54int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
70caad98
NC		 55/* end-sanitize-v850eq */
56
ead4a3f1 57#ifdef DEBUG
ead4a3f1 58#ifndef SIZE_INSTRUCTION
3f33acd0 59#define SIZE_INSTRUCTION 18
ead4a3f1
MM		 60#endif
61
62#ifndef SIZE_VALUES
63#define SIZE_VALUES 11
64#endif
65
3f33acd0 66
fb1fd475
AC		 67unsigned32 trace_values[3];
68int trace_num_values;
69unsigned32 trace_pc;
70const char *trace_name;
6aead89a 71const char *trace_module;
1d00ce83 72
70caad98 73
658303f7 74void
ead4a3f1
MM		 75trace_input (name, type, size)
76 char *name;
77 enum op_types type;
78 int size;
79{
ead4a3f1 80
02508bb1 81 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
ead4a3f1
MM		 82 return;
83
3f33acd0
AC		 84 trace_pc = PC;
85 trace_name = name;
6aead89a 86 trace_module = "alu";
ead4a3f1
MM		 87
88 switch (type)
89 {
90 default:
91 case OP_UNKNOWN:
92 case OP_NONE:
ead4a3f1 93 case OP_TRAP:
3f33acd0 94 trace_num_values = 0;
ead4a3f1 95 break;
658303f7 96
ead4a3f1 97 case OP_REG:
658303f7 98 case OP_REG_REG_MOVE:
3f33acd0
AC		 99 trace_values[0] = State.regs[OP[0]];
100 trace_num_values = 1;
ead4a3f1 101 break;
658303f7
AC		 102
103 /* start-sanitize-v850e */
104 case OP_BIT_CHANGE:
105 /* end-sanitize-v850e */
ead4a3f1
MM		 106 case OP_REG_REG:
107 case OP_REG_REG_CMP:
3f33acd0
AC		 108 trace_values[0] = State.regs[OP[1]];
109 trace_values[1] = State.regs[OP[0]];
110 trace_num_values = 2;
ead4a3f1 111 break;
658303f7 112
ead4a3f1
MM		 113 case OP_IMM_REG:
114 case OP_IMM_REG_CMP:
3f33acd0
AC		 115 trace_values[0] = SEXT5 (OP[0]);
116 trace_values[1] = OP[1];
117 trace_num_values = 2;
658303f7
AC		 118 break;
119
ead4a3f1 120 case OP_IMM_REG_MOVE:
3f33acd0
AC		 121 trace_values[0] = SEXT5 (OP[0]);
122 trace_num_values = 1;
ead4a3f1 123 break;
658303f7 124
ead4a3f1 125 case OP_COND_BR:
3f33acd0
AC		 126 trace_values[0] = State.pc;
127 trace_values[1] = SEXT9 (OP[0]);
128 trace_values[2] = PSW;
129 trace_num_values = 3;
ead4a3f1 130 break;
658303f7 131
ead4a3f1 132 case OP_LOAD16:
3f33acd0
AC		 133 trace_values[0] = OP[1] * size;
134 trace_values[1] = State.regs[30];
135 trace_num_values = 2;
ead4a3f1 136 break;
658303f7 137
ead4a3f1 138 case OP_STORE16:
3f33acd0
AC		 139 trace_values[0] = State.regs[OP[0]];
140 trace_values[1] = OP[1] * size;
141 trace_values[2] = State.regs[30];
142 trace_num_values = 3;
ead4a3f1 143 break;
658303f7 144
ead4a3f1 145 case OP_LOAD32:
3f33acd0
AC		 146 trace_values[0] = EXTEND16 (OP[2]);
147 trace_values[1] = State.regs[OP[0]];
148 trace_num_values = 2;
ead4a3f1 149 break;
658303f7 150
ead4a3f1 151 case OP_STORE32:
3f33acd0
AC		 152 trace_values[0] = State.regs[OP[1]];
153 trace_values[1] = EXTEND16 (OP[2]);
154 trace_values[2] = State.regs[OP[0]];
155 trace_num_values = 3;
ead4a3f1 156 break;
658303f7 157
ead4a3f1 158 case OP_JUMP:
3f33acd0
AC		 159 trace_values[0] = SEXT22 (OP[0]);
160 trace_values[1] = State.pc;
161 trace_num_values = 2;
ead4a3f1 162 break;
658303f7 163
ead4a3f1 164 case OP_IMM_REG_REG:
3f33acd0
AC		 165 trace_values[0] = EXTEND16 (OP[0]) << size;
166 trace_values[1] = State.regs[OP[1]];
167 trace_num_values = 2;
ead4a3f1 168 break;
658303f7 169
fb1fd475
AC		 170 case OP_IMM16_REG_REG:
171 trace_values[0] = EXTEND16 (OP[2]) << size;
172 trace_values[1] = State.regs[OP[1]];
173 trace_num_values = 2;
174 break;
175
ead4a3f1 176 case OP_UIMM_REG_REG:
3f33acd0
AC		 177 trace_values[0] = (OP[0] & 0xffff) << size;
178 trace_values[1] = State.regs[OP[1]];
179 trace_num_values = 2;
ead4a3f1 180 break;
658303f7 181
fb1fd475
AC		 182 case OP_UIMM16_REG_REG:
183 trace_values[0] = (OP[2]) << size;
184 trace_values[1] = State.regs[OP[1]];
185 trace_num_values = 2;
186 break;
187
ead4a3f1 188 case OP_BIT:
3f33acd0 189 trace_num_values = 0;
ead4a3f1 190 break;
658303f7 191
ead4a3f1 192 case OP_EX1:
3f33acd0
AC		 193 trace_values[0] = PSW;
194 trace_num_values = 1;
658303f7
AC		 195 break;
196
ead4a3f1 197 case OP_EX2:
3f33acd0 198 trace_num_values = 0;
ead4a3f1 199 break;
658303f7 200
ead4a3f1 201 case OP_LDSR:
3f33acd0
AC		 202 trace_values[0] = State.regs[OP[0]];
203 trace_num_values = 1;
70caad98 204 break;
658303f7
AC		 205
206 case OP_STSR:
3f33acd0
AC		 207 trace_values[0] = State.sregs[OP[1]];
208 trace_num_values = 1;
ead4a3f1 209 }
658303f7 210
ead4a3f1
MM		 211}
212
658303f7 213void
fb1fd475 214trace_result (int has_result, unsigned32 result)
ead4a3f1 215{
3f33acd0
AC		 216 char buf[1000];
217 char *chp;
ead4a3f1 218
3f33acd0
AC		 219 buf[0] = '\0';
220 chp = buf;
221
222 /* write out the values saved during the trace_input call */
223 {
224 int i;
225 for (i = 0; i < trace_num_values; i++)
226 {
227 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", trace_values[i]);
228 chp = strchr (chp, '\0');
229 }
230 while (i++ < 3)
231 {
232 sprintf (chp, "%*s", SIZE_VALUES, "");
233 chp = strchr (chp, '\0');
234 }
235 }
236
fb1fd475
AC		 237 /* append any result to the end of the buffer */
238 if (has_result)
239 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
240
241 trace_one_insn (simulator, STATE_CPU (simulator, 0), trace_pc,
242 TRACE_LINENUM_P (STATE_CPU (simulator, 0)),
6aead89a 243 "simops", __LINE__, trace_module,
fb1fd475
AC		 244 "%-*s -%s", SIZE_INSTRUCTION, trace_name, buf);
245}
246
247void
248trace_output (result)
249 enum op_types result;
250{
251 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
252 return;
253
3f33acd0
AC		 254 switch (result)
255 {
256 default:
257 case OP_UNKNOWN:
258 case OP_NONE:
259 case OP_TRAP:
260 case OP_REG:
261 case OP_REG_REG_CMP:
262 case OP_IMM_REG_CMP:
263 case OP_COND_BR:
264 case OP_STORE16:
265 case OP_STORE32:
266 case OP_BIT:
267 case OP_EX2:
fb1fd475 268 trace_result (0, 0);
3f33acd0
AC		 269 break;
270
271 case OP_LOAD16:
272 case OP_STSR:
fb1fd475 273 trace_result (1, State.regs[OP[0]]);
3f33acd0
AC		 274 break;
275
276 case OP_REG_REG:
277 case OP_REG_REG_MOVE:
278 case OP_IMM_REG:
279 case OP_IMM_REG_MOVE:
280 case OP_LOAD32:
281 case OP_EX1:
fb1fd475 282 trace_result (1, State.regs[OP[1]]);
3f33acd0
AC		 283 break;
284
285 case OP_IMM_REG_REG:
286 case OP_UIMM_REG_REG:
fb1fd475
AC		 287 case OP_IMM16_REG_REG:
288 case OP_UIMM16_REG_REG:
289 trace_result (1, State.regs[OP[1]]);
3f33acd0
AC		 290 break;
291
292 case OP_JUMP:
293 if (OP[1] != 0)
fb1fd475
AC		 294 trace_result (1, State.regs[OP[1]]);
295 else
296 trace_result (0, 0);
3f33acd0
AC		 297 break;
298
299 case OP_LDSR:
fb1fd475 300 trace_result (1, State.sregs[OP[1]]);
3f33acd0 301 break;
ead4a3f1 302 }
3f33acd0 303}
ead4a3f1
MM		 304#endif
305
70caad98
NC		 306\f
307/* Returns 1 if the specific condition is met, returns 0 otherwise. */
bd4c35cc 308int
70caad98
NC		 309condition_met (unsigned code)
310{
311 unsigned int psw = PSW;
312
313 switch (code & 0xf)
314 {
315 case 0x0: return ((psw & PSW_OV) != 0);
316 case 0x1: return ((psw & PSW_CY) != 0);
317 case 0x2: return ((psw & PSW_Z) != 0);
318 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
319 case 0x4: return ((psw & PSW_S) != 0);
320 /*case 0x5: return 1;*/
321 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
322 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
323 case 0x8: return ((psw & PSW_OV) == 0);
324 case 0x9: return ((psw & PSW_CY) == 0);
325 case 0xa: return ((psw & PSW_Z) == 0);
326 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
327 case 0xc: return ((psw & PSW_S) == 0);
328 case 0xd: return ((psw & PSW_SAT) != 0);
329 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
330 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
331 }
332
333 return 1;
334}
658303f7 335/* start-sanitize-v850e */
70caad98 336
70caad98
NC		 337static unsigned long
338Add32 (unsigned long a1, unsigned long a2, int * carry)
339{
340 unsigned long result = (a1 + a2);
341
342 * carry = (result < a1);
343
344 return result;
345}
346
347static void
348Multiply64 (boolean sign, unsigned long op0)
349{
350 unsigned long op1;
351 unsigned long lo;
352 unsigned long mid1;
353 unsigned long mid2;
354 unsigned long hi;
355 unsigned long RdLo;
356 unsigned long RdHi;
357 int carry;
358
359 op1 = State.regs[ OP[1] ];
360
361 if (sign)
362 {
363 /* Compute sign of result and adjust operands if necessary. */
364
365 sign = (op0 ^ op1) & 0x80000000;
366
367 if (((signed long) op0) < 0)
368 op0 = - op0;
369
370 if (((signed long) op1) < 0)
371 op1 = - op1;
372 }
373
374 /* We can split the 32x32 into four 16x16 operations. This ensures
375 that we do not lose precision on 32bit only hosts: */
376 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
377 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
378 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
379 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
380
381 /* We now need to add all of these results together, taking care
382 to propogate the carries from the additions: */
383 RdLo = Add32 (lo, (mid1 << 16), & carry);
384 RdHi = carry;
385 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
386 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
387
388 if (sign)
389 {
390 /* Negate result if necessary. */
391
392 RdLo = ~ RdLo;
393 RdHi = ~ RdHi;
394 if (RdLo == 0xFFFFFFFF)
395 {
396 RdLo = 0;
397 RdHi += 1;
398 }
399 else
400 RdLo += 1;
401 }
402
5262de21
JW		 403 /* Don't store into register 0. */
404 if (OP[1])
405 State.regs[ OP[1] ] = RdLo;
406 if (OP[2] >> 11)
407 State.regs[ OP[2] >> 11 ] = RdHi;
70caad98
NC		 408
409 return;
410}
70caad98 411
658303f7 412/* end-sanitize-v850e */
da3a66e5
AC		 413\f
414/* Read a null terminated string from memory, return in a buffer */
415static char *
416fetch_str (sd, addr)
417 SIM_DESC sd;
418 address_word addr;
419{
420 char *buf;
421 int nr = 0;
422 while (sim_core_read_1 (STATE_CPU (sd, 0),
423 PC, sim_core_read_map, addr + nr) != 0)
424 nr++;
425 buf = NZALLOC (char, nr + 1);
426 sim_read (simulator, addr, buf, nr);
427 return buf;
428}
429
430/* Read a null terminated argument vector from memory, return in a
431 buffer */
432static char **
433fetch_argv (sd, addr)
434 SIM_DESC sd;
435 address_word addr;
436{
437 int max_nr = 64;
438 int nr = 0;
439 char **buf = xmalloc (max_nr * sizeof (char*));
440 while (1)
441 {
442 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
443 PC, sim_core_read_map, addr + nr * 4);
444 if (a == 0) break;
445 buf[nr] = fetch_str (sd, a);
446 nr ++;
447 if (nr == max_nr - 1)
448 {
449 max_nr += 50;
450 buf = xrealloc (buf, max_nr * sizeof (char*));
451 }
452 }
453 buf[nr] = 0;
454 return buf;
455}
456
ead4a3f1 457\f
28647e4c 458/* sst.b */
70caad98 459int
28647e4c
JL		 460OP_380 ()
461{
ead4a3f1 462 trace_input ("sst.b", OP_STORE16, 1);
70caad98
NC		 463
464 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
465
ead4a3f1 466 trace_output (OP_STORE16);
70caad98
NC		 467
468 return 2;
28647e4c
JL		 469}
470
471/* sst.h */
70caad98 472int
28647e4c
JL		 473OP_480 ()
474{
ead4a3f1 475 trace_input ("sst.h", OP_STORE16, 2);
70caad98
NC		 476
477 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
478
ead4a3f1 479 trace_output (OP_STORE16);
70caad98
NC		 480
481 return 2;
28647e4c
JL		 482}
483
484/* sst.w */
70caad98 485int
28647e4c
JL		 486OP_501 ()
487{
ead4a3f1 488 trace_input ("sst.w", OP_STORE16, 4);
70caad98
NC		 489
490 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
491
ead4a3f1 492 trace_output (OP_STORE16);
70caad98
NC		 493
494 return 2;
28647e4c
JL		 495}
496
497/* ld.b */
70caad98 498int
28647e4c
JL		 499OP_700 ()
500{
70caad98 501 int adr;
28647e4c 502
ead4a3f1 503 trace_input ("ld.b", OP_LOAD32, 1);
70caad98 504
5d37a07b 505 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
70caad98 506
5d37a07b 507 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
70caad98 508
ead4a3f1 509 trace_output (OP_LOAD32);
70caad98
NC		 510
511 return 4;
28647e4c
JL		 512}
513
514/* ld.h */
70caad98 515int
28647e4c
JL		 516OP_720 ()
517{
70caad98 518 int adr;
28647e4c 519
ead4a3f1 520 trace_input ("ld.h", OP_LOAD32, 2);
70caad98 521
5d37a07b 522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
70caad98
NC		 523 adr &= ~0x1;
524
5d37a07b 525 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
70caad98 526
ead4a3f1 527 trace_output (OP_LOAD32);
70caad98
NC		 528
529 return 4;
28647e4c
JL		 530}
531
532/* ld.w */
70caad98 533int
28647e4c
JL		 534OP_10720 ()
535{
70caad98 536 int adr;
28647e4c 537
ead4a3f1 538 trace_input ("ld.w", OP_LOAD32, 4);
70caad98 539
5d37a07b 540 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
70caad98
NC		 541 adr &= ~0x3;
542
543 State.regs[ OP[1] ] = load_mem (adr, 4);
544
ead4a3f1 545 trace_output (OP_LOAD32);
70caad98
NC		 546
547 return 4;
28647e4c
JL		 548}
549
550/* st.b */
70caad98 551int
28647e4c
JL		 552OP_740 ()
553{
ead4a3f1 554 trace_input ("st.b", OP_STORE32, 1);
70caad98 555
5d37a07b 556 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
70caad98 557
ead4a3f1 558 trace_output (OP_STORE32);
70caad98
NC		 559
560 return 4;
28647e4c
JL		 561}
562
563/* st.h */
70caad98 564int
22c1c7dd
JL		 565OP_760 ()
566{
70caad98
NC		 567 int adr;
568
ead4a3f1 569 trace_input ("st.h", OP_STORE32, 2);
70caad98 570
5d37a07b 571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
70caad98
NC		 572 adr &= ~1;
573
574 store_mem (adr, 2, State.regs[ OP[1] ]);
575
ead4a3f1 576 trace_output (OP_STORE32);
70caad98
NC		 577
578 return 4;
28647e4c
JL		 579}
580
581/* st.w */
70caad98 582int
28647e4c
JL		 583OP_10760 ()
584{
70caad98
NC		 585 int adr;
586
ead4a3f1 587 trace_input ("st.w", OP_STORE32, 4);
70caad98 588
5d37a07b 589 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
70caad98
NC		 590 adr &= ~3;
591
592 store_mem (adr, 4, State.regs[ OP[1] ]);
593
ead4a3f1 594 trace_output (OP_STORE32);
70caad98
NC		 595
596 return 4;
22c1c7dd
JL		 597}
598
0ef0eba5 599/* add reg, reg */
70caad98 600int
1fe983dc 601OP_1C0 ()
22c1c7dd 602{
0ef0eba5 603 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 604
ead4a3f1 605 trace_input ("add", OP_REG_REG, 0);
70caad98 606
0ef0eba5 607 /* Compute the result. */
70caad98
NC		 608
609 op0 = State.regs[ OP[0] ];
610 op1 = State.regs[ OP[1] ];
611
0ef0eba5 612 result = op0 + op1;
1fe983dc 613
0ef0eba5
JL		 614 /* Compute the condition codes. */
615 z = (result == 0);
616 s = (result & 0x80000000);
617 cy = (result < op0 || result < op1);
618 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
619 && (op0 & 0x80000000) != (result & 0x80000000));
620
621 /* Store the result and condition codes. */
622 State.regs[OP[1]] = result;
ee3f2d4f
MM		 623 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
624 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
614f1c68 625 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 626 trace_output (OP_REG_REG);
70caad98
NC		 627
628 return 2;
0ef0eba5
JL		 629}
630
631/* add sign_extend(imm5), reg */
70caad98 632int
1fe983dc 633OP_240 ()
22c1c7dd 634{
0ef0eba5
JL		 635 unsigned int op0, op1, result, z, s, cy, ov;
636 int temp;
1fe983dc 637
ead4a3f1
MM		 638 trace_input ("add", OP_IMM_REG, 0);
639
0ef0eba5 640 /* Compute the result. */
ead4a3f1 641 temp = SEXT5 (OP[0]);
0ef0eba5
JL		 642 op0 = temp;
643 op1 = State.regs[OP[1]];
644 result = op0 + op1;
645
646 /* Compute the condition codes. */
647 z = (result == 0);
648 s = (result & 0x80000000);
649 cy = (result < op0 || result < op1);
650 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
651 && (op0 & 0x80000000) != (result & 0x80000000));
22c1c7dd 652
0ef0eba5
JL		 653 /* Store the result and condition codes. */
654 State.regs[OP[1]] = result;
ee3f2d4f
MM		 655 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
656 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5 657 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 658 trace_output (OP_IMM_REG);
70caad98
NC		 659
660 return 2;
0ef0eba5 661}
1fe983dc 662
0ef0eba5 663/* addi sign_extend(imm16), reg, reg */
70caad98 664int
1fe983dc 665OP_600 ()
22c1c7dd 666{
0ef0eba5 667 unsigned int op0, op1, result, z, s, cy, ov;
0ef0eba5 668
fb1fd475 669 trace_input ("addi", OP_IMM16_REG_REG, 0);
ead4a3f1 670
0ef0eba5 671 /* Compute the result. */
70caad98 672
5d37a07b 673 op0 = EXTEND16 (OP[2]);
70caad98 674 op1 = State.regs[ OP[0] ];
0ef0eba5
JL		 675 result = op0 + op1;
676
677 /* Compute the condition codes. */
678 z = (result == 0);
679 s = (result & 0x80000000);
680 cy = (result < op0 || result < op1);
681 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
682 && (op0 & 0x80000000) != (result & 0x80000000));
683
684 /* Store the result and condition codes. */
70caad98 685 State.regs[OP[1]] = result;
ee3f2d4f
MM		 686 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
687 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5 688 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
fb1fd475 689 trace_output (OP_IMM16_REG_REG);
70caad98
NC		 690
691 return 4;
22c1c7dd
JL		 692}
693
aabce0f4 694/* sub reg1, reg2 */
70caad98 695int
1fe983dc 696OP_1A0 ()
22c1c7dd 697{
aabce0f4
JL		 698 unsigned int op0, op1, result, z, s, cy, ov;
699
ead4a3f1 700 trace_input ("sub", OP_REG_REG, 0);
aabce0f4 701 /* Compute the result. */
70caad98
NC		 702 op0 = State.regs[ OP[0] ];
703 op1 = State.regs[ OP[1] ];
aabce0f4 704 result = op1 - op0;
22c1c7dd 705
aabce0f4
JL		 706 /* Compute the condition codes. */
707 z = (result == 0);
708 s = (result & 0x80000000);
d81352b8 709 cy = (op1 < op0);
aabce0f4
JL		 710 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
711 && (op1 & 0x80000000) != (result & 0x80000000));
1fe983dc 712
aabce0f4
JL		 713 /* Store the result and condition codes. */
714 State.regs[OP[1]] = result;
ee3f2d4f
MM		 715 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
716 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 717 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 718 trace_output (OP_REG_REG);
70caad98
NC		 719
720 return 2;
aabce0f4
JL		 721}
722
723/* subr reg1, reg2 */
70caad98 724int
1fe983dc 725OP_180 ()
22c1c7dd 726{
aabce0f4 727 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 728
ead4a3f1 729 trace_input ("subr", OP_REG_REG, 0);
aabce0f4 730 /* Compute the result. */
70caad98
NC		 731 op0 = State.regs[ OP[0] ];
732 op1 = State.regs[ OP[1] ];
aabce0f4 733 result = op0 - op1;
e98e3b2c 734
aabce0f4
JL		 735 /* Compute the condition codes. */
736 z = (result == 0);
737 s = (result & 0x80000000);
d81352b8 738 cy = (op0 < op1);
aabce0f4
JL		 739 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
740 && (op0 & 0x80000000) != (result & 0x80000000));
741
742 /* Store the result and condition codes. */
743 State.regs[OP[1]] = result;
ee3f2d4f
MM		 744 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
745 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 746 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 747 trace_output (OP_REG_REG);
70caad98
NC		 748
749 return 2;
aabce0f4
JL		 750}
751
70caad98 752/* sxh reg1 */
70caad98 753int
e98e3b2c 754OP_E0 ()
22c1c7dd 755{
fb1fd475 756 trace_input ("mulh", OP_REG_REG, 0);
70caad98 757
fb1fd475 758 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
70caad98 759
fb1fd475 760 trace_output (OP_REG_REG);
70caad98
NC		 761
762 return 2;
763}
764
765/* mulh sign_extend(imm5), reg2 */
766int
767OP_2E0 ()
22c1c7dd 768{
ead4a3f1 769 trace_input ("mulh", OP_IMM_REG, 0);
70caad98 770
5d37a07b 771 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
70caad98 772
ead4a3f1 773 trace_output (OP_IMM_REG);
70caad98
NC		 774
775 return 2;
22c1c7dd
JL		 776}
777
aabce0f4 778/* mulhi imm16, reg1, reg2 */
70caad98 779int
e98e3b2c
JL		 780OP_6E0 ()
781{
fb1fd475 782 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
70caad98 783
bda61639 784 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
70caad98 785
fb1fd475 786 trace_output (OP_IMM16_REG_REG);
70caad98
NC		 787
788 return 4;
e98e3b2c
JL		 789}
790
aabce0f4 791/* divh reg1, reg2 */
70caad98 792int
e98e3b2c 793OP_40 ()
22c1c7dd 794{
fb1fd475
AC		 795 unsigned int op0, op1, result, ov, s, z;
796 int temp;
ead4a3f1 797
fb1fd475 798 trace_input ("divh", OP_REG_REG, 0);
aabce0f4 799
fb1fd475
AC		 800 /* Compute the result. */
801 temp = EXTEND16 (State.regs[ OP[0] ]);
802 op0 = temp;
803 op1 = State.regs[OP[1]];
804
805 if (op0 == 0xffffffff && op1 == 0x80000000)
806 {
807 result = 0x80000000;
808 ov = 1;
809 }
810 else if (op0 != 0)
811 {
812 result = op1 / op0;
813 ov = 0;
aabce0f4
JL		 814 }
815 else
9fca2fd3 816 {
fb1fd475
AC		 817 result = 0x0;
818 ov = 1;
70caad98 819 }
fb1fd475
AC		 820
821 /* Compute the condition codes. */
822 z = (result == 0);
823 s = (result & 0x80000000);
824
825 /* Store the result and condition codes. */
826 State.regs[OP[1]] = result;
827 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
828 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
829 | (ov ? PSW_OV : 0));
830 trace_output (OP_REG_REG);
70caad98
NC		 831
832 return 2;
22c1c7dd
JL		 833}
834
3095b8df 835/* cmp reg, reg */
70caad98 836int
3095b8df
JL		 837OP_1E0 ()
838{
839 unsigned int op0, op1, result, z, s, cy, ov;
840
ead4a3f1 841 trace_input ("cmp", OP_REG_REG_CMP, 0);
3095b8df 842 /* Compute the result. */
70caad98
NC		 843 op0 = State.regs[ OP[0] ];
844 op1 = State.regs[ OP[1] ];
3095b8df
JL		 845 result = op1 - op0;
846
847 /* Compute the condition codes. */
848 z = (result == 0);
849 s = (result & 0x80000000);
d81352b8 850 cy = (op1 < op0);
3095b8df
JL		 851 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
852 && (op1 & 0x80000000) != (result & 0x80000000));
853
854 /* Set condition codes. */
ee3f2d4f
MM		 855 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
856 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df 857 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 858 trace_output (OP_REG_REG_CMP);
70caad98
NC		 859
860 return 2;
3095b8df
JL		 861}
862
863/* cmp sign_extend(imm5), reg */
70caad98 864int
3095b8df
JL		 865OP_260 ()
866{
867 unsigned int op0, op1, result, z, s, cy, ov;
868 int temp;
869
870 /* Compute the result. */
ead4a3f1
MM		 871 trace_input ("cmp", OP_IMM_REG_CMP, 0);
872 temp = SEXT5 (OP[0]);
3095b8df
JL		 873 op0 = temp;
874 op1 = State.regs[OP[1]];
875 result = op1 - op0;
876
877 /* Compute the condition codes. */
878 z = (result == 0);
879 s = (result & 0x80000000);
d81352b8 880 cy = (op1 < op0);
3095b8df
JL		 881 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
882 && (op1 & 0x80000000) != (result & 0x80000000));
883
884 /* Set condition codes. */
ee3f2d4f
MM		 885 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
886 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df 887 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 888 trace_output (OP_IMM_REG_CMP);
70caad98
NC		 889
890 return 2;
3095b8df
JL		 891}
892
893/* setf cccc,reg2 */
70caad98 894int
3095b8df
JL		 895OP_7E0 ()
896{
ead4a3f1 897 trace_input ("setf", OP_EX1, 0);
3095b8df 898
70caad98 899 State.regs[ OP[1] ] = condition_met (OP[0]);
3095b8df 900
ead4a3f1 901 trace_output (OP_EX1);
70caad98
NC		 902
903 return 4;
3095b8df
JL		 904}
905
dca41ba7 906/* satadd reg,reg */
70caad98 907int
dca41ba7
JL		 908OP_C0 ()
909{
bda61639
AC		 910 unsigned int op0, op1, result, z, s, cy, ov, sat;
911
912 trace_input ("satadd", OP_REG_REG, 0);
913 /* Compute the result. */
914 op0 = State.regs[ OP[0] ];
915 op1 = State.regs[ OP[1] ];
916 result = op0 + op1;
917
918 /* Compute the condition codes. */
919 z = (result == 0);
920 s = (result & 0x80000000);
921 cy = (result < op0 || result < op1);
922 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
923 && (op0 & 0x80000000) != (result & 0x80000000));
924 sat = ov;
925
926 /* Store the result and condition codes. */
927 State.regs[OP[1]] = result;
928 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
929 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
930 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
931 | (sat ? PSW_SAT : 0));
932
933 /* Handle saturated results. */
934 if (sat && s)
935 State.regs[OP[1]] = 0x80000000;
936 else if (sat)
937 State.regs[OP[1]] = 0x7fffffff;
938 trace_output (OP_REG_REG);
dca41ba7 939
70caad98 940 return 2;
dca41ba7
JL		 941}
942
943/* satadd sign_extend(imm5), reg */
70caad98 944int
dca41ba7
JL		 945OP_220 ()
946{
947 unsigned int op0, op1, result, z, s, cy, ov, sat;
948
949 int temp;
950
ead4a3f1
MM		 951 trace_input ("satadd", OP_IMM_REG, 0);
952
dca41ba7 953 /* Compute the result. */
ead4a3f1 954 temp = SEXT5 (OP[0]);
dca41ba7
JL		 955 op0 = temp;
956 op1 = State.regs[OP[1]];
957 result = op0 + op1;
958
959 /* Compute the condition codes. */
960 z = (result == 0);
961 s = (result & 0x80000000);
962 cy = (result < op0 || result < op1);
963 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
964 && (op0 & 0x80000000) != (result & 0x80000000));
965 sat = ov;
966
967 /* Store the result and condition codes. */
968 State.regs[OP[1]] = result;
ee3f2d4f
MM		 969 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
970 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 971 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
972 | (sat ? PSW_SAT : 0));
973
974 /* Handle saturated results. */
0e4ccc58 975 if (sat && s)
dca41ba7
JL		 976 State.regs[OP[1]] = 0x80000000;
977 else if (sat)
978 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 979 trace_output (OP_IMM_REG);
70caad98
NC		 980
981 return 2;
dca41ba7
JL		 982}
983
984/* satsub reg1, reg2 */
70caad98 985int
dca41ba7
JL		 986OP_A0 ()
987{
fb1fd475
AC		 988 unsigned int op0, op1, result, z, s, cy, ov, sat;
989
990 trace_input ("satsub", OP_REG_REG, 0);
991
992 /* Compute the result. */
993 op0 = State.regs[ OP[0] ];
994 op1 = State.regs[ OP[1] ];
995 result = op1 - op0;
996
997 /* Compute the condition codes. */
998 z = (result == 0);
999 s = (result & 0x80000000);
1000 cy = (op1 < op0);
1001 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1002 && (op1 & 0x80000000) != (result & 0x80000000));
1003 sat = ov;
1004
1005 /* Store the result and condition codes. */
1006 State.regs[OP[1]] = result;
1007 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1008 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1009 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1010 | (sat ? PSW_SAT : 0));
1011
1012 /* Handle saturated results. */
1013 if (sat && s)
1014 State.regs[OP[1]] = 0x80000000;
1015 else if (sat)
1016 State.regs[OP[1]] = 0x7fffffff;
1017 trace_output (OP_REG_REG);
70caad98 1018 return 2;
dca41ba7
JL		 1019}
1020
1021/* satsubi sign_extend(imm16), reg */
70caad98 1022int
dca41ba7
JL		 1023OP_660 ()
1024{
1025 unsigned int op0, op1, result, z, s, cy, ov, sat;
1026 int temp;
1027
ead4a3f1
MM		 1028 trace_input ("satsubi", OP_IMM_REG, 0);
1029
dca41ba7 1030 /* Compute the result. */
5d37a07b 1031 temp = EXTEND16 (OP[2]);
dca41ba7 1032 op0 = temp;
70caad98 1033 op1 = State.regs[ OP[0] ];
dca41ba7
JL		 1034 result = op1 - op0;
1035
1036 /* Compute the condition codes. */
1037 z = (result == 0);
1038 s = (result & 0x80000000);
d81352b8 1039 cy = (op1 < op0);
dca41ba7
JL		 1040 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1041 && (op1 & 0x80000000) != (result & 0x80000000));
1042 sat = ov;
1043
1044 /* Store the result and condition codes. */
1045 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1046 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1047 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1048 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1049 | (sat ? PSW_SAT : 0));
1050
1051 /* Handle saturated results. */
0e4ccc58 1052 if (sat && s)
dca41ba7
JL		 1053 State.regs[OP[1]] = 0x80000000;
1054 else if (sat)
1055 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1056 trace_output (OP_IMM_REG);
70caad98
NC		 1057
1058 return 4;
dca41ba7
JL		 1059}
1060
ead4a3f1 1061/* satsubr reg,reg */
70caad98 1062int
dca41ba7
JL		 1063OP_80 ()
1064{
bda61639
AC		 1065 unsigned int op0, op1, result, z, s, cy, ov, sat;
1066
1067 trace_input ("satsubr", OP_REG_REG, 0);
1068
1069 /* Compute the result. */
1070 op0 = State.regs[ OP[0] ];
1071 op1 = State.regs[ OP[1] ];
1072 result = op0 - op1;
1073
1074 /* Compute the condition codes. */
1075 z = (result == 0);
1076 s = (result & 0x80000000);
1077 cy = (result < op0);
1078 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1079 && (op1 & 0x80000000) != (result & 0x80000000));
1080 sat = ov;
1081
1082 /* Store the result and condition codes. */
1083 State.regs[OP[1]] = result;
1084 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1085 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1086 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1087 | (sat ? PSW_SAT : 0));
1088
1089 /* Handle saturated results. */
1090 if (sat && s)
1091 State.regs[OP[1]] = 0x80000000;
1092 else if (sat)
1093 State.regs[OP[1]] = 0x7fffffff;
1094 trace_output (OP_REG_REG);
dca41ba7 1095
70caad98 1096 return 2;
dca41ba7
JL		 1097}
1098
3095b8df 1099/* tst reg,reg */
70caad98 1100int
3095b8df
JL		 1101OP_160 ()
1102{
9fca2fd3 1103 unsigned int op0, op1, result, z, s;
3095b8df 1104
ead4a3f1
MM		 1105 trace_input ("tst", OP_REG_REG_CMP, 0);
1106
3095b8df 1107 /* Compute the result. */
70caad98
NC		 1108 op0 = State.regs[ OP[0] ];
1109 op1 = State.regs[ OP[1] ];
3095b8df
JL		 1110 result = op0 & op1;
1111
1112 /* Compute the condition codes. */
1113 z = (result == 0);
1114 s = (result & 0x80000000);
1115
1116 /* Store the condition codes. */
ee3f2d4f
MM		 1117 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1118 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1119 trace_output (OP_REG_REG_CMP);
70caad98
NC		 1120
1121 return 2;
3095b8df
JL		 1122}
1123
1fe983dc 1124/* mov sign_extend(imm5), reg */
70caad98 1125int
1fe983dc 1126OP_200 ()
22c1c7dd 1127{
fb1fd475 1128 int value = SEXT5 (OP[0]);
70caad98 1129
fb1fd475 1130 trace_input ("mov", OP_IMM_REG_MOVE, 0);
70caad98 1131
fb1fd475
AC		 1132 State.regs[ OP[1] ] = value;
1133
1134 trace_output (OP_IMM_REG_MOVE);
1135
1136 return 2;
22c1c7dd
JL		 1137}
1138
1fe983dc 1139/* movhi imm16, reg, reg */
70caad98 1140int
1fe983dc 1141OP_640 ()
22c1c7dd 1142{
fb1fd475 1143 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
70caad98 1144
fb1fd475 1145 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
70caad98 1146
fb1fd475 1147 trace_output (OP_UIMM16_REG_REG);
70caad98
NC		 1148
1149 return 4;
22c1c7dd
JL		 1150}
1151
35404c7d 1152/* sar zero_extend(imm5),reg1 */
70caad98 1153int
77553374 1154OP_2A0 ()
22c1c7dd 1155{
9fca2fd3 1156 unsigned int op0, op1, result, z, s, cy;
77553374 1157
ead4a3f1 1158 trace_input ("sar", OP_IMM_REG, 0);
70caad98
NC		 1159 op0 = OP[0];
1160 op1 = State.regs[ OP[1] ];
35404c7d 1161 result = (signed)op1 >> op0;
77553374 1162
35404c7d
JL		 1163 /* Compute the condition codes. */
1164 z = (result == 0);
1165 s = (result & 0x80000000);
1166 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 1167
35404c7d 1168 /* Store the result and condition codes. */
70caad98 1169 State.regs[ OP[1] ] = result;
ee3f2d4f
MM		 1170 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1171 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
9fca2fd3 1172 | (cy ? PSW_CY : 0));
ead4a3f1 1173 trace_output (OP_IMM_REG);
70caad98
NC		 1174
1175 return 2;
35404c7d 1176}
77553374 1177
35404c7d 1178/* sar reg1, reg2 */
70caad98 1179int
77553374 1180OP_A007E0 ()
22c1c7dd 1181{
9fca2fd3 1182 unsigned int op0, op1, result, z, s, cy;
77553374 1183
ead4a3f1 1184 trace_input ("sar", OP_REG_REG, 0);
70caad98
NC		 1185
1186 op0 = State.regs[ OP[0] ] & 0x1f;
1187 op1 = State.regs[ OP[1] ];
35404c7d 1188 result = (signed)op1 >> op0;
77553374 1189
35404c7d
JL		 1190 /* Compute the condition codes. */
1191 z = (result == 0);
1192 s = (result & 0x80000000);
1193 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 1194
35404c7d
JL		 1195 /* Store the result and condition codes. */
1196 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1197 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1198 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1199 | (cy ? PSW_CY : 0));
ead4a3f1 1200 trace_output (OP_REG_REG);
70caad98
NC		 1201
1202 return 4;
35404c7d 1203}
77553374 1204
35404c7d 1205/* shl zero_extend(imm5),reg1 */
70caad98 1206int
22c1c7dd 1207OP_2C0 ()
77553374 1208{
9fca2fd3 1209 unsigned int op0, op1, result, z, s, cy;
35404c7d 1210
ead4a3f1 1211 trace_input ("shl", OP_IMM_REG, 0);
70caad98
NC		 1212 op0 = OP[0];
1213 op1 = State.regs[ OP[1] ];
35404c7d
JL		 1214 result = op1 << op0;
1215
1216 /* Compute the condition codes. */
1217 z = (result == 0);
1218 s = (result & 0x80000000);
1219 cy = (op1 & (1 << (32 - op0)));
77553374 1220
35404c7d
JL		 1221 /* Store the result and condition codes. */
1222 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1223 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1224 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1225 | (cy ? PSW_CY : 0));
ead4a3f1 1226 trace_output (OP_IMM_REG);
70caad98
NC		 1227
1228 return 2;
35404c7d 1229}
77553374 1230
35404c7d 1231/* shl reg1, reg2 */
70caad98 1232int
77553374
JL		 1233OP_C007E0 ()
1234{
9fca2fd3 1235 unsigned int op0, op1, result, z, s, cy;
77553374 1236
ead4a3f1 1237 trace_input ("shl", OP_REG_REG, 0);
70caad98
NC		 1238 op0 = State.regs[ OP[0] ] & 0x1f;
1239 op1 = State.regs[ OP[1] ];
35404c7d
JL		 1240 result = op1 << op0;
1241
1242 /* Compute the condition codes. */
1243 z = (result == 0);
1244 s = (result & 0x80000000);
1245 cy = (op1 & (1 << (32 - op0)));
1246
1247 /* Store the result and condition codes. */
1248 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1249 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1250 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1251 | (cy ? PSW_CY : 0));
ead4a3f1 1252 trace_output (OP_REG_REG);
70caad98
NC		 1253
1254 return 4;
35404c7d 1255}
77553374 1256
35404c7d 1257/* shr zero_extend(imm5),reg1 */
70caad98 1258int
77553374
JL		 1259OP_280 ()
1260{
9fca2fd3 1261 unsigned int op0, op1, result, z, s, cy;
77553374 1262
ead4a3f1 1263 trace_input ("shr", OP_IMM_REG, 0);
70caad98
NC		 1264 op0 = OP[0];
1265 op1 = State.regs[ OP[1] ];
35404c7d 1266 result = op1 >> op0;
77553374 1267
35404c7d
JL		 1268 /* Compute the condition codes. */
1269 z = (result == 0);
1270 s = (result & 0x80000000);
1271 cy = (op1 & (1 << (op0 - 1)));
1272
1273 /* Store the result and condition codes. */
1274 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1275 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1276 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1277 | (cy ? PSW_CY : 0));
ead4a3f1 1278 trace_output (OP_IMM_REG);
70caad98
NC		 1279
1280 return 2;
35404c7d
JL		 1281}
1282
1283/* shr reg1, reg2 */
70caad98 1284int
77553374
JL		 1285OP_8007E0 ()
1286{
9fca2fd3 1287 unsigned int op0, op1, result, z, s, cy;
35404c7d 1288
ead4a3f1 1289 trace_input ("shr", OP_REG_REG, 0);
70caad98
NC		 1290 op0 = State.regs[ OP[0] ] & 0x1f;
1291 op1 = State.regs[ OP[1] ];
35404c7d
JL		 1292 result = op1 >> op0;
1293
1294 /* Compute the condition codes. */
1295 z = (result == 0);
1296 s = (result & 0x80000000);
1297 cy = (op1 & (1 << (op0 - 1)));
1298
1299 /* Store the result and condition codes. */
1300 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1301 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1302 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1303 | (cy ? PSW_CY : 0));
ead4a3f1 1304 trace_output (OP_REG_REG);
70caad98
NC		 1305
1306 return 4;
77553374
JL		 1307}
1308
0ef0eba5 1309/* or reg, reg */
70caad98 1310int
1fe983dc
JL		 1311OP_100 ()
1312{
9fca2fd3 1313 unsigned int op0, op1, result, z, s;
1fe983dc 1314
ead4a3f1
MM		 1315 trace_input ("or", OP_REG_REG, 0);
1316
0ef0eba5 1317 /* Compute the result. */
70caad98
NC		 1318 op0 = State.regs[ OP[0] ];
1319 op1 = State.regs[ OP[1] ];
0ef0eba5 1320 result = op0 | op1;
1fe983dc 1321
0ef0eba5
JL		 1322 /* Compute the condition codes. */
1323 z = (result == 0);
1324 s = (result & 0x80000000);
1325
1326 /* Store the result and condition codes. */
1327 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1328 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1329 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1330 trace_output (OP_REG_REG);
70caad98
NC		 1331
1332 return 2;
0ef0eba5
JL		 1333}
1334
1335/* ori zero_extend(imm16), reg, reg */
70caad98 1336int
1fe983dc
JL		 1337OP_680 ()
1338{
9fca2fd3 1339 unsigned int op0, op1, result, z, s;
1fe983dc 1340
fb1fd475 1341 trace_input ("ori", OP_UIMM16_REG_REG, 0);
70caad98
NC		 1342 op0 = OP[2];
1343 op1 = State.regs[ OP[0] ];
0ef0eba5 1344 result = op0 | op1;
1fe983dc 1345
0ef0eba5
JL		 1346 /* Compute the condition codes. */
1347 z = (result == 0);
1348 s = (result & 0x80000000);
1fe983dc 1349
0ef0eba5 1350 /* Store the result and condition codes. */
70caad98 1351 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1352 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1353 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
fb1fd475 1354 trace_output (OP_UIMM16_REG_REG);
70caad98
NC		 1355
1356 return 4;
0ef0eba5
JL		 1357}
1358
1359/* and reg, reg */
70caad98 1360int
22c1c7dd
JL		 1361OP_140 ()
1362{
9fca2fd3 1363 unsigned int op0, op1, result, z, s;
22c1c7dd 1364
ead4a3f1
MM		 1365 trace_input ("and", OP_REG_REG, 0);
1366
0ef0eba5 1367 /* Compute the result. */
70caad98
NC		 1368 op0 = State.regs[ OP[0] ];
1369 op1 = State.regs[ OP[1] ];
0ef0eba5 1370 result = op0 & op1;
1fe983dc 1371
0ef0eba5
JL		 1372 /* Compute the condition codes. */
1373 z = (result == 0);
1374 s = (result & 0x80000000);
1375
1376 /* Store the result and condition codes. */
1377 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1378 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1379 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1380 trace_output (OP_REG_REG);
70caad98
NC		 1381
1382 return 2;
0ef0eba5
JL		 1383}
1384
1385/* andi zero_extend(imm16), reg, reg */
70caad98 1386int
1fe983dc
JL		 1387OP_6C0 ()
1388{
70caad98 1389 unsigned int result, z;
1fe983dc 1390
fb1fd475 1391 trace_input ("andi", OP_UIMM16_REG_REG, 0);
70caad98
NC		 1392
1393 result = OP[2] & State.regs[ OP[0] ];
1fe983dc 1394
0ef0eba5
JL		 1395 /* Compute the condition codes. */
1396 z = (result == 0);
1fe983dc 1397
0ef0eba5 1398 /* Store the result and condition codes. */
70caad98
NC		 1399 State.regs[ OP[1] ] = result;
1400
ee3f2d4f
MM		 1401 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1402 PSW |= (z ? PSW_Z : 0);
70caad98 1403
fb1fd475 1404 trace_output (OP_UIMM16_REG_REG);
70caad98
NC		 1405
1406 return 4;
0ef0eba5
JL		 1407}
1408
1409/* xor reg, reg */
70caad98 1410int
1fe983dc 1411OP_120 ()
22c1c7dd 1412{
9fca2fd3 1413 unsigned int op0, op1, result, z, s;
1fe983dc 1414
ead4a3f1
MM		 1415 trace_input ("xor", OP_REG_REG, 0);
1416
0ef0eba5 1417 /* Compute the result. */
70caad98
NC		 1418 op0 = State.regs[ OP[0] ];
1419 op1 = State.regs[ OP[1] ];
0ef0eba5 1420 result = op0 ^ op1;
1fe983dc 1421
0ef0eba5
JL		 1422 /* Compute the condition codes. */
1423 z = (result == 0);
1424 s = (result & 0x80000000);
1425
1426 /* Store the result and condition codes. */
1427 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1428 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1429 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1430 trace_output (OP_REG_REG);
70caad98
NC		 1431
1432 return 2;
0ef0eba5
JL		 1433}
1434
1435/* xori zero_extend(imm16), reg, reg */
70caad98 1436int
1fe983dc
JL		 1437OP_6A0 ()
1438{
9fca2fd3 1439 unsigned int op0, op1, result, z, s;
0ef0eba5 1440
fb1fd475 1441 trace_input ("xori", OP_UIMM16_REG_REG, 0);
70caad98
NC		 1442 op0 = OP[2];
1443 op1 = State.regs[ OP[0] ];
0ef0eba5
JL		 1444 result = op0 ^ op1;
1445
1446 /* Compute the condition codes. */
1447 z = (result == 0);
1448 s = (result & 0x80000000);
1449
1450 /* Store the result and condition codes. */
70caad98 1451 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1452 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1453 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
fb1fd475 1454 trace_output (OP_UIMM16_REG_REG);
70caad98
NC		 1455
1456 return 4;
0ef0eba5
JL		 1457}
1458
1459/* not reg1, reg2 */
70caad98 1460int
0ef0eba5
JL		 1461OP_20 ()
1462{
9fca2fd3 1463 unsigned int op0, result, z, s;
0ef0eba5 1464
ead4a3f1 1465 trace_input ("not", OP_REG_REG_MOVE, 0);
0ef0eba5 1466 /* Compute the result. */
70caad98 1467 op0 = State.regs[ OP[0] ];
0ef0eba5
JL		 1468 result = ~op0;
1469
1470 /* Compute the condition codes. */
1471 z = (result == 0);
1472 s = (result & 0x80000000);
1fe983dc 1473
0ef0eba5
JL		 1474 /* Store the result and condition codes. */
1475 State.regs[OP[1]] = result;
ee3f2d4f
MM		 1476 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1477 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1478 trace_output (OP_REG_REG_MOVE);
70caad98
NC		 1479
1480 return 2;
22c1c7dd
JL		 1481}
1482
28647e4c 1483/* set1 */
70caad98 1484int
28647e4c 1485OP_7C0 ()
1fe983dc 1486{
83fc3bac 1487 unsigned int op0, op1, op2;
9fca2fd3 1488 int temp;
83fc3bac 1489
ead4a3f1 1490 trace_input ("set1", OP_BIT, 0);
70caad98 1491 op0 = State.regs[ OP[0] ];
83fc3bac 1492 op1 = OP[1] & 0x7;
5d37a07b 1493 temp = EXTEND16 (OP[2]);
83fc3bac 1494 op2 = temp;
96851909 1495 temp = load_mem (op0 + op2, 1);
ee3f2d4f 1496 PSW &= ~PSW_Z;
83fc3bac 1497 if ((temp & (1 << op1)) == 0)
ee3f2d4f 1498 PSW |= PSW_Z;
787d66bb 1499 temp |= (1 << op1);
96851909 1500 store_mem (op0 + op2, 1, temp);
ead4a3f1 1501 trace_output (OP_BIT);
70caad98
NC		 1502
1503 return 4;
1fe983dc
JL		 1504}
1505
28647e4c 1506/* not1 */
70caad98 1507int
28647e4c 1508OP_47C0 ()
1fe983dc 1509{
83fc3bac 1510 unsigned int op0, op1, op2;
9fca2fd3 1511 int temp;
83fc3bac 1512
ead4a3f1 1513 trace_input ("not1", OP_BIT, 0);
70caad98 1514 op0 = State.regs[ OP[0] ];
83fc3bac 1515 op1 = OP[1] & 0x7;
5d37a07b 1516 temp = EXTEND16 (OP[2]);
83fc3bac 1517 op2 = temp;
96851909 1518 temp = load_mem (op0 + op2, 1);
ee3f2d4f 1519 PSW &= ~PSW_Z;
83fc3bac 1520 if ((temp & (1 << op1)) == 0)
ee3f2d4f 1521 PSW |= PSW_Z;
787d66bb 1522 temp ^= (1 << op1);
96851909 1523 store_mem (op0 + op2, 1, temp);
ead4a3f1 1524 trace_output (OP_BIT);
70caad98
NC		 1525
1526 return 4;
1fe983dc
JL		 1527}
1528
28647e4c 1529/* clr1 */
70caad98 1530int
28647e4c
JL		 1531OP_87C0 ()
1532{
83fc3bac 1533 unsigned int op0, op1, op2;
9fca2fd3 1534 int temp;
83fc3bac 1535
ead4a3f1 1536 trace_input ("clr1", OP_BIT, 0);
70caad98 1537 op0 = State.regs[ OP[0] ];
83fc3bac 1538 op1 = OP[1] & 0x7;
5d37a07b 1539 temp = EXTEND16 (OP[2]);
83fc3bac 1540 op2 = temp;
96851909 1541 temp = load_mem (op0 + op2, 1);
ee3f2d4f 1542 PSW &= ~PSW_Z;
83fc3bac 1543 if ((temp & (1 << op1)) == 0)
ee3f2d4f 1544 PSW |= PSW_Z;
83fc3bac 1545 temp &= ~(1 << op1);
96851909 1546 store_mem (op0 + op2, 1, temp);
ead4a3f1 1547 trace_output (OP_BIT);
70caad98
NC		 1548
1549 return 4;
28647e4c
JL		 1550}
1551
1552/* tst1 */
70caad98 1553int
28647e4c 1554OP_C7C0 ()
1fe983dc 1555{
83fc3bac 1556 unsigned int op0, op1, op2;
9fca2fd3 1557 int temp;
83fc3bac 1558
ead4a3f1 1559 trace_input ("tst1", OP_BIT, 0);
70caad98 1560 op0 = State.regs[ OP[0] ];
83fc3bac 1561 op1 = OP[1] & 0x7;
5d37a07b 1562 temp = EXTEND16 (OP[2]);
83fc3bac 1563 op2 = temp;
96851909 1564 temp = load_mem (op0 + op2, 1);
ee3f2d4f 1565 PSW &= ~PSW_Z;
83fc3bac 1566 if ((temp & (1 << op1)) == 0)
ee3f2d4f 1567 PSW |= PSW_Z;
ead4a3f1 1568 trace_output (OP_BIT);
70caad98
NC		 1569
1570 return 4;
1fe983dc 1571}
e98e3b2c 1572
3095b8df 1573/* di */
70caad98 1574int
e98e3b2c
JL		 1575OP_16007E0 ()
1576{
ead4a3f1 1577 trace_input ("di", OP_NONE, 0);
ee3f2d4f 1578 PSW |= PSW_ID;
ead4a3f1 1579 trace_output (OP_NONE);
70caad98
NC		 1580
1581 return 4;
e98e3b2c
JL		 1582}
1583
3095b8df 1584/* ei */
70caad98 1585int
e98e3b2c
JL		 1586OP_16087E0 ()
1587{
ead4a3f1 1588 trace_input ("ei", OP_NONE, 0);
ee3f2d4f 1589 PSW &= ~PSW_ID;
ead4a3f1 1590 trace_output (OP_NONE);
70caad98
NC		 1591
1592 return 4;
e98e3b2c
JL		 1593}
1594
ee3f2d4f 1595/* halt */
70caad98 1596int
e98e3b2c
JL		 1597OP_12007E0 ()
1598{
ead4a3f1 1599 trace_input ("halt", OP_NONE, 0);
ee3f2d4f 1600 /* FIXME this should put processor into a mode where NMI still handled */
ead4a3f1 1601 trace_output (OP_NONE);
5d37a07b
AC		 1602 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1603 sim_stopped, SIGTRAP);
1604 return 0;
e98e3b2c
JL		 1605}
1606
ee3f2d4f 1607/* trap */
70caad98 1608int
e98e3b2c
JL		 1609OP_10007E0 ()
1610{
ead4a3f1
MM		 1611 trace_input ("trap", OP_TRAP, 0);
1612 trace_output (OP_TRAP);
1613
96851909 1614 /* Trap 31 is used for simulating OS I/O functions */
d81352b8 1615
96851909 1616 if (OP[0] == 31)
d81352b8 1617 {
d81352b8
JL		 1618 int save_errno = errno;
1619 errno = 0;
1620
1621/* Registers passed to trap 0 */
1622
1623#define FUNC State.regs[6] /* function number, return value */
1624#define PARM1 State.regs[7] /* optional parm 1 */
1625#define PARM2 State.regs[8] /* optional parm 2 */
1626#define PARM3 State.regs[9] /* optional parm 3 */
1627
1628/* Registers set by trap 0 */
1629
1630#define RETVAL State.regs[10] /* return value */
1631#define RETERR State.regs[11] /* return error code */
1632
1633/* Turn a pointer in a register into a pointer into real memory. */
1634
96851909 1635#define MEMPTR(x) (map (x))
d81352b8
JL		 1636
1637 switch (FUNC)
1638 {
0ffba68f 1639
da3a66e5 1640#ifdef HAVE_FORK
0ffba68f 1641#ifdef SYS_fork
d81352b8
JL		 1642 case SYS_fork:
1643 RETVAL = fork ();
1644 break;
0ffba68f
AC		 1645#endif
1646#endif
1647
da3a66e5 1648#ifdef HAVE_EXECVE
0ffba68f 1649#ifdef SYS_execv
d81352b8 1650 case SYS_execve:
da3a66e5
AC		 1651 {
1652 char *path = fetch_str (simulator, PARM1);
1653 char **argv = fetch_argv (simulator, PARM2);
1654 char **envp = fetch_argv (simulator, PARM3);
1655 RETVAL = execve (path, argv, envp);
1656 zfree (path);
1657 freeargv (argv);
1658 freeargv (envp);
1659 break;
1660 }
0ffba68f
AC		 1661#endif
1662#endif
1663
da3a66e5 1664#if HAVE_EXECV
87e43259 1665#ifdef SYS_execv
d81352b8 1666 case SYS_execv:
da3a66e5
AC		 1667 {
1668 char *path = fetch_str (simulator, PARM1);
1669 char **argv = fetch_argv (simulator, PARM2);
1670 RETVAL = execv (path, argv);
1671 zfree (path);
1672 freeargv (argv);
1673 break;
1674 }
87e43259 1675#endif
0ffba68f
AC		 1676#endif
1677
9909e232 1678#if 0
0ffba68f 1679#ifdef SYS_pipe
d81352b8
JL		 1680 case SYS_pipe:
1681 {
1682 reg_t buf;
1683 int host_fd[2];
1684
1685 buf = PARM1;
1686 RETVAL = pipe (host_fd);
1687 SW (buf, host_fd[0]);
1688 buf += sizeof(uint16);
1689 SW (buf, host_fd[1]);
1690 }
1691 break;
0ffba68f
AC		 1692#endif
1693#endif
d81352b8 1694
0ffba68f
AC		 1695#if 0
1696#ifdef SYS_wait
d81352b8
JL		 1697 case SYS_wait:
1698 {
1699 int status;
1700
1701 RETVAL = wait (&status);
1702 SW (PARM1, status);
1703 }
1704 break;
9909e232 1705#endif
d81352b8
JL		 1706#endif
1707
0ffba68f 1708#ifdef SYS_read
d81352b8 1709 case SYS_read:
da3a66e5
AC		 1710 {
1711 char *buf = zalloc (PARM3);
1712 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1713 sim_write (simulator, PARM2, buf, PARM3);
1714 zfree (buf);
1715 break;
1716 }
0ffba68f
AC		 1717#endif
1718
1719#ifdef SYS_write
d81352b8 1720 case SYS_write:
da3a66e5
AC		 1721 {
1722 char *buf = zalloc (PARM3);
1723 sim_read (simulator, PARM2, buf, PARM3);
1724 if (PARM1 == 1)
1725 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1726 else
1727 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1728 zfree (buf);
1729 break;
1730 }
0ffba68f
AC		 1731#endif
1732
1733#ifdef SYS_lseek
d81352b8 1734 case SYS_lseek:
9cdd2c6d 1735 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
d81352b8 1736 break;
0ffba68f
AC		 1737#endif
1738
1739#ifdef SYS_close
d81352b8 1740 case SYS_close:
9cdd2c6d 1741 RETVAL = sim_io_close (simulator, PARM1);
d81352b8 1742 break;
0ffba68f
AC		 1743#endif
1744
1745#ifdef SYS_open
d81352b8 1746 case SYS_open:
da3a66e5
AC		 1747 {
1748 char *buf = fetch_str (simulator, PARM1);
1749 RETVAL = sim_io_open (simulator, buf, PARM2);
1750 zfree (buf);
1751 break;
1752 }
0ffba68f
AC		 1753#endif
1754
1755#ifdef SYS_exit
d81352b8 1756 case SYS_exit:
6ec96a02 1757 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
5d37a07b
AC		 1758 /* get signal encoded by kill */
1759 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1760 sim_signalled, PARM1 & 0xffff);
6ec96a02 1761 else if (PARM1 == 0xdead)
5d37a07b
AC		 1762 /* old libraries */
1763 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1764 sim_exited, SIGABRT);
6ec96a02 1765 else
5d37a07b
AC		 1766 /* PARM1 has exit status */
1767 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1768 sim_exited, PARM1);
d81352b8 1769 break;
0ffba68f 1770#endif
d81352b8 1771
87e43259 1772#if !defined(__GO32__) && !defined(_WIN32)
0ffba68f 1773#ifdef SYS_stat
d81352b8
JL		 1774 case SYS_stat: /* added at hmsi */
1775 /* stat system call */
1776 {
1777 struct stat host_stat;
1778 reg_t buf;
da3a66e5 1779 char *path = fetch_str (simulator, PARM1);
d81352b8 1780
da3a66e5 1781 RETVAL = stat (path, &host_stat);
d81352b8 1782
da3a66e5 1783 zfree (path);
d81352b8
JL		 1784 buf = PARM2;
1785
c500c074
JL		 1786 /* Just wild-assed guesses. */
1787 store_mem (buf, 2, host_stat.st_dev);
1788 store_mem (buf + 2, 2, host_stat.st_ino);
1789 store_mem (buf + 4, 4, host_stat.st_mode);
1790 store_mem (buf + 8, 2, host_stat.st_nlink);
1791 store_mem (buf + 10, 2, host_stat.st_uid);
1792 store_mem (buf + 12, 2, host_stat.st_gid);
1793 store_mem (buf + 14, 2, host_stat.st_rdev);
1794 store_mem (buf + 16, 4, host_stat.st_size);
1795 store_mem (buf + 20, 4, host_stat.st_atime);
1796 store_mem (buf + 28, 4, host_stat.st_mtime);
1797 store_mem (buf + 36, 4, host_stat.st_ctime);
d81352b8
JL		 1798 }
1799 break;
0ffba68f
AC		 1800#endif
1801#endif
d81352b8 1802
da3a66e5 1803#ifdef HAVE_CHOWN
0ffba68f 1804#ifdef SYS_chown
d81352b8 1805 case SYS_chown:
da3a66e5
AC		 1806 {
1807 char *path = fetch_str (simulator, PARM1);
1808 RETVAL = chown (path, PARM2, PARM3);
1809 zfree (path);
1810 }
d81352b8 1811 break;
0ffba68f
AC		 1812#endif
1813#endif
1814
0ffba68f 1815#if HAVE_CHMOD
da3a66e5 1816#ifdef SYS_chmod
d81352b8 1817 case SYS_chmod:
da3a66e5
AC		 1818 {
1819 char *path = fetch_str (simulator, PARM1);
1820 RETVAL = chmod (path, PARM2);
1821 zfree (path);
1822 }
d81352b8 1823 break;
0ffba68f
AC		 1824#endif
1825#endif
1826
87e43259 1827#ifdef SYS_time
0ffba68f 1828#if HAVE_TIME
6803f89b 1829 case SYS_time:
ee3f2d4f
MM		 1830 {
1831 time_t now;
1832 RETVAL = time (&now);
1833 store_mem (PARM1, 4, now);
1834 }
6803f89b 1835 break;
87e43259 1836#endif
0ffba68f
AC		 1837#endif
1838
1839#if !defined(__GO32__) && !defined(_WIN32)
87e43259 1840#ifdef SYS_times
8824fb45
JL		 1841 case SYS_times:
1842 {
1843 struct tms tms;
1844 RETVAL = times (&tms);
1845 store_mem (PARM1, 4, tms.tms_utime);
1846 store_mem (PARM1 + 4, 4, tms.tms_stime);
1847 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1848 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1849 break;
1850 }
87e43259 1851#endif
0ffba68f
AC		 1852#endif
1853
1854#ifdef SYS_gettimeofday
1855#if !defined(__GO32__) && !defined(_WIN32)
8824fb45
JL		 1856 case SYS_gettimeofday:
1857 {
1858 struct timeval t;
1859 struct timezone tz;
1860 RETVAL = gettimeofday (&t, &tz);
1861 store_mem (PARM1, 4, t.tv_sec);
1862 store_mem (PARM1 + 4, 4, t.tv_usec);
1863 store_mem (PARM2, 4, tz.tz_minuteswest);
1864 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1865 break;
1866 }
0ffba68f
AC		 1867#endif
1868#endif
1869
87e43259 1870#ifdef SYS_utime
9cdd2c6d 1871#if HAVE_UTIME
d81352b8 1872 case SYS_utime:
da3a66e5
AC		 1873 {
1874 /* Cast the second argument to void *, to avoid type mismatch
1875 if a prototype is present. */
1876 sim_io_error (simulator, "Utime not supported");
1877 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1878 }
d81352b8 1879 break;
87e43259
AC		 1880#endif
1881#endif
0ffba68f 1882
d81352b8
JL		 1883 default:
1884 abort ();
1885 }
1886 RETERR = errno;
1887 errno = save_errno;
70caad98
NC		 1888
1889 return 4;
d81352b8 1890 }
96851909
SG		 1891 else
1892 { /* Trap 0 -> 30 */
ee3f2d4f
MM		 1893 EIPC = PC + 4;
1894 EIPSW = PSW;
1895 /* Mask out EICC */
1896 ECR &= 0xffff0000;
1897 ECR |= 0x40 + OP[0];
1898 /* Flag that we are now doing exception processing. */
1899 PSW |= PSW_EP | PSW_ID;
96851909 1900 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
70caad98
NC		 1901
1902 return 0;
d81352b8 1903 }
e98e3b2c
JL		 1904}
1905
658303f7 1906/* start-sanitize-v850e */
70caad98
NC		 1907/* tst1 reg2, [reg1] */
1908int
1909OP_E607E0 (void)
1910{
1911 int temp;
1912
5d37a07b 1913 trace_input ("tst1", OP_BIT, 1);
70caad98
NC		 1914
1915 temp = load_mem (State.regs[ OP[0] ], 1);
1916
1917 PSW &= ~PSW_Z;
1918 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
1919 PSW |= PSW_Z;
1920
5d37a07b 1921 trace_output (OP_BIT);
70caad98
NC		 1922
1923 return 4;
1924}
1925
658303f7
AC		 1926/* end-sanitize-v850e */
1927/* start-sanitize-v850e */
64ad9cec
NC		 1928/* mulu reg1, reg2, reg3 */
1929int
1930OP_22207E0 (void)
1931{
1932 trace_input ("mulu", OP_REG_REG_REG, 0);
1933
1934 Multiply64 (false, State.regs[ OP[0] ]);
1935
1936 trace_output (OP_REG_REG_REG);
1937
1938 return 4;
1939}
1940
658303f7 1941/* end-sanitize-v850e */
70caad98
NC		 1942/* start-sanitize-v850e */
1943
1944#define BIT_CHANGE_OP( name, binop ) \
1945 unsigned int bit; \
1946 unsigned int temp; \
1947 \
1948 trace_input (name, OP_BIT_CHANGE, 0); \
1949 \
1950 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
1951 temp = load_mem (State.regs[ OP[0] ], 1); \
1952 \
1953 PSW &= ~PSW_Z; \
1954 if ((temp & bit) == 0) \
1955 PSW |= PSW_Z; \
1956 temp binop bit; \
1957 \
1958 store_mem (State.regs[ OP[0] ], 1, temp); \
1959 \
1960 trace_output (OP_BIT_CHANGE); \
1961 \
1962 return 4;
1963
1964/* clr1 reg2, [reg1] */
1965int
1966OP_E407E0 (void)
1967{
1968 BIT_CHANGE_OP ("clr1", &= ~ );
1969}
1970
1971/* not1 reg2, [reg1] */
1972int
1973OP_E207E0 (void)
1974{
1975 BIT_CHANGE_OP ("not1", ^= );
e98e3b2c 1976}
70caad98
NC		 1977
1978/* set1 */
1979int
1980OP_E007E0 (void)
1981{
1982 BIT_CHANGE_OP ("set1", |= );
1983}
1984
1985/* sasf */
1986int
1987OP_20007E0 (void)
1988{
1989 trace_input ("sasf", OP_EX1, 0);
1990
1991 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1992
1993 trace_output (OP_EX1);
1994
1995 return 4;
1996}
1997/* end-sanitize-v850e */
70caad98 1998/* start-sanitize-v850eq */
64ad9cec 1999/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
bda61639 2000void
64ad9cec
NC		 2001divun
2002(
2003 unsigned int N,
2004 unsigned long int als,
2005 unsigned long int sfi,
2006 unsigned long int * quotient_ptr,
2007 unsigned long int * remainder_ptr,
2008 boolean * overflow_ptr
2009)
2010{
9cdd2c6d 2011 unsigned long ald = sfi >> (N - 1);
64ad9cec
NC		 2012 unsigned long alo = als;
2013 unsigned int Q = 1;
2014 unsigned int C;
2015 unsigned int S = 0;
2016 unsigned int i;
2017 unsigned int R1 = 1;
64ad9cec
NC		 2018 unsigned int DBZ = (als == 0) ? 1 : 0;
2019 unsigned long alt = Q ? ~als : als;
2020
2021 /* 1st Loop */
2022 alo = ald + alt + Q;
9cdd2c6d
AC		 2023 C = (((alt >> 31) & (ald >> 31))
2024 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2025 C = C ^ Q;
2026 Q = ~(C ^ S) & 1;
2027 R1 = (alo == 0) ? 0 : (R1 & Q);
2028 if ((S ^ (alo>>31)) && !C)
2029 {
2030 DBZ = 1;
2031 }
2032 S = alo >> 31;
2033 sfi = (sfi << (32-N+1)) | Q;
2034 ald = (alo << 1) | (sfi >> 31);
2035
2036 /* 2nd - N-1th Loop */
2037 for (i = 2; i < N; i++)
2038 {
2039 alt = Q ? ~als : als;
2040 alo = ald + alt + Q;
9cdd2c6d
AC		 2041 C = (((alt >> 31) & (ald >> 31))
2042 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2043 C = C ^ Q;
2044 Q = ~(C ^ S) & 1;
2045 R1 = (alo == 0) ? 0 : (R1 & Q);
2046 if ((S ^ (alo>>31)) && !C && !DBZ)
2047 {
2048 DBZ = 1;
2049 }
2050 S = alo >> 31;
2051 sfi = (sfi << 1) | Q;
2052 ald = (alo << 1) | (sfi >> 31);
2053 }
2054
2055 /* Nth Loop */
2056 alt = Q ? ~als : als;
2057 alo = ald + alt + Q;
9cdd2c6d
AC		 2058 C = (((alt >> 31) & (ald >> 31))
2059 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2060 C = C ^ Q;
2061 Q = ~(C ^ S) & 1;
2062 R1 = (alo == 0) ? 0 : (R1 & Q);
2063 if ((S ^ (alo>>31)) && !C)
2064 {
2065 DBZ = 1;
2066 }
2067
2068 * quotient_ptr = (sfi << 1) | Q;
2069 * remainder_ptr = Q ? alo : (alo + als);
2070 * overflow_ptr = DBZ | R1;
2071}
2072
2073/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
bda61639 2074void
64ad9cec
NC		 2075divn
2076(
2077 unsigned int N,
2078 unsigned long int als,
2079 unsigned long int sfi,
2080 signed long int * quotient_ptr,
2081 signed long int * remainder_ptr,
2082 boolean * overflow_ptr
2083)
2084{
2085 unsigned long ald = (signed long) sfi >> (N - 1);
2086 unsigned long alo = als;
2087 unsigned int SS = als >> 31;
2088 unsigned int SD = sfi >> 31;
2089 unsigned int R1 = 1;
2090 unsigned int OV;
2091 unsigned int DBZ = als == 0 ? 1 : 0;
2092 unsigned int Q = ~(SS ^ SD) & 1;
2093 unsigned int C;
2094 unsigned int S;
2095 unsigned int i;
2096 unsigned long alt = Q ? ~als : als;
2097
2098
2099 /* 1st Loop */
2100
2101 alo = ald + alt + Q;
9cdd2c6d
AC		 2102 C = (((alt >> 31) & (ald >> 31))
2103 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2104 Q = C ^ SS;
2105 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2106 S = alo >> 31;
2107 sfi = (sfi << (32-N+1)) | Q;
2108 ald = (alo << 1) | (sfi >> 31);
2109 if ((alo >> 31) ^ (ald >> 31))
2110 {
2111 DBZ = 1;
2112 }
2113
2114 /* 2nd - N-1th Loop */
2115
2116 for (i = 2; i < N; i++)
2117 {
2118 alt = Q ? ~als : als;
2119 alo = ald + alt + Q;
9cdd2c6d
AC		 2120 C = (((alt >> 31) & (ald >> 31))
2121 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2122 Q = C ^ SS;
2123 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2124 S = alo >> 31;
2125 sfi = (sfi << 1) | Q;
2126 ald = (alo << 1) | (sfi >> 31);
2127 if ((alo >> 31) ^ (ald >> 31))
2128 {
2129 DBZ = 1;
2130 }
2131 }
2132
2133 /* Nth Loop */
2134 alt = Q ? ~als : als;
2135 alo = ald + alt + Q;
9cdd2c6d
AC		 2136 C = (((alt >> 31) & (ald >> 31))
2137 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
64ad9cec
NC		 2138 Q = C ^ SS;
2139 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2140 sfi = (sfi << (32-N+1));
2141 ald = alo;
2142
2143 /* End */
2144 if (alo != 0)
2145 {
2146 alt = Q ? ~als : als;
2147 alo = ald + alt + Q;
2148 }
2149 R1 = R1 & ((~alo >> 31) ^ SD);
2150 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2151 if (N != 32)
2152 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2153 else
2154 ald = sfi = sfi | Q;
2155
2156 OV = DBZ | ((alo == 0) ? 0 : R1);
2157
2158 * remainder_ptr = alo;
2159
2160 /* Adj */
9cdd2c6d
AC		 2161 if (((alo != 0) && ((SS ^ SD) ^ R1))
2162 || ((alo == 0) && (SS ^ R1)))
64ad9cec
NC		 2163 alo = ald + 1;
2164 else
2165 alo = ald;
2166
2167 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2168
2169 * quotient_ptr = alo;
2170 * overflow_ptr = OV;
2171}
2172
70caad98
NC		 2173/* sdivun imm5, reg1, reg2, reg3 */
2174int
2175OP_1C207E0 (void)
2176{
64ad9cec
NC		 2177 unsigned long int quotient;
2178 unsigned long int remainder;
2179 unsigned long int divide_by;
2180 unsigned long int divide_this;
2181 boolean overflow = false;
2182 unsigned int imm5;
70caad98
NC		 2183
2184 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2185
2186 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2187
64ad9cec
NC		 2188 divide_by = State.regs[ OP[0] ];
2189 divide_this = State.regs[ OP[1] ] << imm5;
70caad98 2190
64ad9cec 2191 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
70caad98 2192
64ad9cec
NC		 2193 State.regs[ OP[1] ] = quotient;
2194 State.regs[ OP[2] >> 11 ] = remainder;
70caad98
NC		 2195
2196 /* Set condition codes. */
2197 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2198
2199 if (overflow) PSW |= PSW_OV;
2200 if (quotient == 0) PSW |= PSW_Z;
60616228 2201 if (quotient & 0x80000000) PSW |= PSW_S;
70caad98
NC		 2202
2203 trace_output (OP_IMM_REG_REG_REG);
2204
2205 return 4;
2206}
2207
2208/* sdivn imm5, reg1, reg2, reg3 */
2209int
2210OP_1C007E0 (void)
2211{
64ad9cec
NC		 2212 signed long int quotient;
2213 signed long int remainder;
2214 signed long int divide_by;
2215 signed long int divide_this;
2216 boolean overflow = false;
2217 unsigned int imm5;
70caad98
NC		 2218
2219 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2220
2221 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2222
64ad9cec
NC		 2223 divide_by = State.regs[ OP[0] ];
2224 divide_this = State.regs[ OP[1] ] << imm5;
70caad98 2225
64ad9cec 2226 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
70caad98 2227
64ad9cec
NC		 2228 State.regs[ OP[1] ] = quotient;
2229 State.regs[ OP[2] >> 11 ] = remainder;
70caad98
NC		 2230
2231 /* Set condition codes. */
2232 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2233
2234 if (overflow) PSW |= PSW_OV;
2235 if (quotient == 0) PSW |= PSW_Z;
2236 if (quotient < 0) PSW |= PSW_S;
2237
2238 trace_output (OP_IMM_REG_REG_REG);
2239
2240 return 4;
2241}
2242
2243/* sdivhun imm5, reg1, reg2, reg3 */
2244int
2245OP_18207E0 (void)
2246{
64ad9cec
NC		 2247 unsigned long int quotient;
2248 unsigned long int remainder;
2249 unsigned long int divide_by;
2250 unsigned long int divide_this;
2251 boolean overflow = false;
2252 unsigned int imm5;
70caad98
NC		 2253
2254 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2255
2256 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2257
64ad9cec
NC		 2258 divide_by = State.regs[ OP[0] ] & 0xffff;
2259 divide_this = State.regs[ OP[1] ] << imm5;
70caad98 2260
64ad9cec 2261 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
70caad98 2262
64ad9cec
NC		 2263 State.regs[ OP[1] ] = quotient;
2264 State.regs[ OP[2] >> 11 ] = remainder;
70caad98
NC		 2265
2266 /* Set condition codes. */
2267 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2268
2269 if (overflow) PSW |= PSW_OV;
2270 if (quotient == 0) PSW |= PSW_Z;
60616228 2271 if (quotient & 0x80000000) PSW |= PSW_S;
70caad98
NC		 2272
2273 trace_output (OP_IMM_REG_REG_REG);
2274
2275 return 4;
2276}
2277
2278/* sdivhn imm5, reg1, reg2, reg3 */
2279int
2280OP_18007E0 (void)
2281{
64ad9cec
NC		 2282 signed long int quotient;
2283 signed long int remainder;
2284 signed long int divide_by;
2285 signed long int divide_this;
2286 boolean overflow = false;
2287 unsigned int imm5;
70caad98
NC		 2288
2289 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2290
2291 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2292
5d37a07b 2293 divide_by = EXTEND16 (State.regs[ OP[0] ]);
64ad9cec 2294 divide_this = State.regs[ OP[1] ] << imm5;
70caad98 2295
64ad9cec 2296 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
70caad98 2297
64ad9cec
NC		 2298 State.regs[ OP[1] ] = quotient;
2299 State.regs[ OP[2] >> 11 ] = remainder;
70caad98
NC		 2300
2301 /* Set condition codes. */
2302 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2303
2304 if (overflow) PSW |= PSW_OV;
2305 if (quotient == 0) PSW |= PSW_Z;
2306 if (quotient < 0) PSW |= PSW_S;
2307
2308 trace_output (OP_IMM_REG_REG_REG);
2309
2310 return 4;
2311}
70caad98 2312
658303f7 2313/* end-sanitize-v850eq */
70caad98
NC		 2314/* start-sanitize-v850e */
2315/* divu reg1, reg2, reg3 */
70caad98
NC		 2316int
2317OP_2C207E0 (void)
2318{
2319 unsigned long int quotient;
2320 unsigned long int remainder;
64ad9cec
NC		 2321 unsigned long int divide_by;
2322 unsigned long int divide_this;
70caad98
NC		 2323 boolean overflow = false;
2324
bda61639
AC		 2325 trace_input ("divu", OP_REG_REG_REG, 0);
2326
2327 /* Compute the result. */
2328
2329 divide_by = State.regs[ OP[0] ];
2330 divide_this = State.regs[ OP[1] ];
2331
2332 if (divide_by == 0)
70caad98 2333 {
bda61639
AC		 2334 overflow = true;
2335 divide_by = 1;
70caad98 2336 }
bda61639
AC		 2337
2338 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2339 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2340
2341 /* Set condition codes. */
2342 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2343
2344 if (overflow) PSW |= PSW_OV;
2345 if (quotient == 0) PSW |= PSW_Z;
2346 if (quotient & 0x80000000) PSW |= PSW_S;
2347
2348 trace_output (OP_REG_REG_REG);
70caad98
NC		 2349
2350 return 4;
2351}
2352
658303f7
AC		 2353/* end-sanitize-v850e */
2354/* start-sanitize-v850e */
70caad98 2355/* div reg1, reg2, reg3 */
70caad98
NC		 2356int
2357OP_2C007E0 (void)
2358{
2359 signed long int quotient;
2360 signed long int remainder;
64ad9cec
NC		 2361 signed long int divide_by;
2362 signed long int divide_this;
70caad98
NC		 2363 boolean overflow = false;
2364
bda61639
AC		 2365 trace_input ("div", OP_REG_REG_REG, 0);
2366
2367 /* Compute the result. */
2368
2369 divide_by = State.regs[ OP[0] ];
2370 divide_this = State.regs[ OP[1] ];
2371
2372 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
70caad98 2373 {
bda61639
AC		 2374 overflow = true;
2375 divide_by = 1;
70caad98 2376 }
bda61639
AC		 2377
2378 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2379 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2380
2381 /* Set condition codes. */
2382 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2383
2384 if (overflow) PSW |= PSW_OV;
2385 if (quotient == 0) PSW |= PSW_Z;
2386 if (quotient < 0) PSW |= PSW_S;
2387
2388 trace_output (OP_REG_REG_REG);
70caad98
NC		 2389
2390 return 4;
2391}
2392
658303f7
AC		 2393/* end-sanitize-v850e */
2394/* start-sanitize-v850e */
70caad98 2395/* divhu reg1, reg2, reg3 */
70caad98
NC		 2396int
2397OP_28207E0 (void)
2398{
2399 unsigned long int quotient;
2400 unsigned long int remainder;
64ad9cec
NC		 2401 unsigned long int divide_by;
2402 unsigned long int divide_this;
70caad98
NC		 2403 boolean overflow = false;
2404
bda61639
AC		 2405 trace_input ("divhu", OP_REG_REG_REG, 0);
2406
2407 /* Compute the result. */
2408
2409 divide_by = State.regs[ OP[0] ] & 0xffff;
2410 divide_this = State.regs[ OP[1] ];
2411
2412 if (divide_by == 0)
70caad98 2413 {
bda61639
AC		 2414 overflow = true;
2415 divide_by = 1;
70caad98 2416 }
bda61639
AC		 2417
2418 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2419 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2420
2421 /* Set condition codes. */
2422 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2423
2424 if (overflow) PSW |= PSW_OV;
2425 if (quotient == 0) PSW |= PSW_Z;
2426 if (quotient & 0x80000000) PSW |= PSW_S;
2427
2428 trace_output (OP_REG_REG_REG);
70caad98
NC		 2429
2430 return 4;
2431}
2432
658303f7
AC		 2433/* end-sanitize-v850e */
2434/* start-sanitize-v850e */
70caad98 2435/* divh reg1, reg2, reg3 */
70caad98
NC		 2436int
2437OP_28007E0 (void)
2438{
2439 signed long int quotient;
2440 signed long int remainder;
64ad9cec
NC		 2441 signed long int divide_by;
2442 signed long int divide_this;
70caad98
NC		 2443 boolean overflow = false;
2444
bda61639
AC		 2445 trace_input ("divh", OP_REG_REG_REG, 0);
2446
2447 /* Compute the result. */
2448
2449 divide_by = State.regs[ OP[0] ];
2450 divide_this = EXTEND16 (State.regs[ OP[1] ]);
2451
2452 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
70caad98 2453 {
bda61639
AC		 2454 overflow = true;
2455 divide_by = 1;
70caad98 2456 }
bda61639
AC		 2457
2458 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2459 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2460
2461 /* Set condition codes. */
2462 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2463
2464 if (overflow) PSW |= PSW_OV;
2465 if (quotient == 0) PSW |= PSW_Z;
2466 if (quotient < 0) PSW |= PSW_S;
2467
2468 trace_output (OP_REG_REG_REG);
70caad98
NC		 2469
2470 return 4;
2471}
2472
658303f7
AC		 2473/* end-sanitize-v850e */
2474/* start-sanitize-v850e */
70caad98
NC		 2475/* mulu imm9, reg2, reg3 */
2476int
2477OP_24207E0 (void)
2478{
2479 trace_input ("mulu", OP_IMM_REG_REG, 0);
2480
2481 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2482
2483 trace_output (OP_IMM_REG_REG);
2484
2485 return 4;
2486}
2487
658303f7
AC		 2488/* end-sanitize-v850e */
2489/* start-sanitize-v850e */
70caad98
NC		 2490/* mul imm9, reg2, reg3 */
2491int
2492OP_24007E0 (void)
2493{
2494 trace_input ("mul", OP_IMM_REG_REG, 0);
2495
2496 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2497
2498 trace_output (OP_IMM_REG_REG);
2499
2500 return 4;
2501}
2502
658303f7
AC		 2503/* end-sanitize-v850e */
2504/* start-sanitize-v850e */
70caad98
NC		 2505/* ld.hu */
2506int
2507OP_107E0 (void)
2508{
bda61639 2509 int adr;
70caad98 2510
bda61639 2511 trace_input ("ld.hu", OP_LOAD32, 2);
70caad98 2512
bda61639
AC		 2513 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2514 adr &= ~0x1;
70caad98 2515
bda61639 2516 State.regs[ OP[1] ] = load_mem (adr, 2);
70caad98 2517
bda61639 2518 trace_output (OP_LOAD32);
70caad98
NC		 2519
2520 return 4;
2521}
2522
658303f7
AC		 2523/* end-sanitize-v850e */
2524/* start-sanitize-v850e */
70caad98
NC		 2525/* ld.bu */
2526int
2527OP_10780 (void)
2528{
bda61639 2529 int adr;
70caad98 2530
bda61639 2531 trace_input ("ld.bu", OP_LOAD32, 1);
70caad98 2532
bda61639
AC		 2533 adr = (State.regs[ OP[0] ]
2534 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
70caad98 2535
bda61639 2536 State.regs[ OP[1] ] = load_mem (adr, 1);
70caad98 2537
bda61639 2538 trace_output (OP_LOAD32);
70caad98
NC		 2539
2540 return 4;
2541}
2542
2543/* prepare list12, imm5, imm32 */
2544int
2545OP_1B0780 (void)
2546{
2547 int i;
2548
2549 trace_input ("prepare", OP_PUSHPOP1, 0);
2550
60616228
NC		 2551 /* Store the registers with lower number registers being placed at higher addresses. */
2552 for (i = 0; i < 12; i++)
70caad98
NC		 2553 if ((OP[3] & (1 << type1_regs[ i ])))
2554 {
2555 SP -= 4;
2556 store_mem (SP, 4, State.regs[ 20 + i ]);
2557 }
2558
2559 SP -= (OP[3] & 0x3e) << 1;
2560
2561 EP = load_mem (PC + 4, 4);
2562
2563 trace_output (OP_PUSHPOP1);
2564
2565 return 8;
2566}
2567
2568/* prepare list12, imm5, imm16-32 */
2569int
2570OP_130780 (void)
2571{
2572 int i;
2573
2574 trace_input ("prepare", OP_PUSHPOP1, 0);
2575
60616228
NC		 2576 /* Store the registers with lower number registers being placed at higher addresses. */
2577 for (i = 0; i < 12; i++)
70caad98
NC		 2578 if ((OP[3] & (1 << type1_regs[ i ])))
2579 {
2580 SP -= 4;
2581 store_mem (SP, 4, State.regs[ 20 + i ]);
2582 }
2583
2584 SP -= (OP[3] & 0x3e) << 1;
2585
2586 EP = load_mem (PC + 4, 2) << 16;
2587
2588 trace_output (OP_PUSHPOP1);
2589
2590 return 6;
2591}
2592
2593/* prepare list12, imm5, imm16 */
2594int
2595OP_B0780 (void)
2596{
2597 int i;
2598
2599 trace_input ("prepare", OP_PUSHPOP1, 0);
2600
60616228
NC		 2601 /* Store the registers with lower number registers being placed at higher addresses. */
2602 for (i = 0; i < 12; i++)
70caad98
NC		 2603 if ((OP[3] & (1 << type1_regs[ i ])))
2604 {
2605 SP -= 4;
2606 store_mem (SP, 4, State.regs[ 20 + i ]);
2607 }
2608
2609 SP -= (OP[3] & 0x3e) << 1;
2610
5d37a07b 2611 EP = EXTEND16 (load_mem (PC + 4, 2));
70caad98
NC		 2612
2613 trace_output (OP_PUSHPOP1);
2614
2615 return 6;
2616}
2617
2618/* prepare list12, imm5, sp */
2619int
2620OP_30780 (void)
2621{
2622 int i;
2623
2624 trace_input ("prepare", OP_PUSHPOP1, 0);
2625
60616228
NC		 2626 /* Store the registers with lower number registers being placed at higher addresses. */
2627 for (i = 0; i < 12; i++)
70caad98
NC		 2628 if ((OP[3] & (1 << type1_regs[ i ])))
2629 {
2630 SP -= 4;
2631 store_mem (SP, 4, State.regs[ 20 + i ]);
2632 }
2633
2634 SP -= (OP[3] & 0x3e) << 1;
2635
2636 EP = SP;
2637
2638 trace_output (OP_PUSHPOP1);
2639
2640 return 4;
2641}
2642
658303f7
AC		 2643/* end-sanitize-v850e */
2644/* start-sanitize-v850e */
64ad9cec
NC		 2645/* mul reg1, reg2, reg3 */
2646int
2647OP_22007E0 (void)
2648{
2649 trace_input ("mul", OP_REG_REG_REG, 0);
2650
2651 Multiply64 (true, State.regs[ OP[0] ]);
2652
2653 trace_output (OP_REG_REG_REG);
2654
2655 return 4;
2656}
2657
70caad98
NC		 2658/* end-sanitize-v850e */
2659/* start-sanitize-v850eq */
2660
2661/* popmh list18 */
2662int
2663OP_307F0 (void)
2664{
2665 int i;
2666
2667 trace_input ("popmh", OP_PUSHPOP2, 0);
2668
70caad98
NC		 2669 if (OP[3] & (1 << 19))
2670 {
2671 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2672 {
2673 FEPSW = load_mem ( SP & ~ 3, 4);
2674 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2675 }
2676 else
2677 {
2678 EIPSW = load_mem ( SP & ~ 3, 4);
2679 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2680 }
2681
2682 SP += 8;
2683 }
2684
60616228
NC		 2685 /* Load the registers with lower number registers being retrieved from higher addresses. */
2686 for (i = 16; i--;)
2687 if ((OP[3] & (1 << type2_regs[ i ])))
2688 {
2689 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2690 SP += 4;
2691 }
2692
70caad98
NC		 2693 trace_output (OP_PUSHPOP2);
2694
2695 return 4;
2696}
2697
2698/* popml lsit18 */
2699int
2700OP_107F0 (void)
2701{
2702 int i;
2703
2704 trace_input ("popml", OP_PUSHPOP3, 0);
2705
70caad98
NC		 2706 if (OP[3] & (1 << 19))
2707 {
2708 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2709 {
2710 FEPSW = load_mem ( SP & ~ 3, 4);
2711 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2712 }
2713 else
2714 {
2715 EIPSW = load_mem ( SP & ~ 3, 4);
2716 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2717 }
2718
2719 SP += 8;
2720 }
2721
60616228
NC		 2722 if (OP[3] & (1 << 3))
2723 {
2724 PSW = load_mem (SP & ~ 3, 4);
2725 SP += 4;
2726 }
2727
2728 /* Load the registers with lower number registers being retrieved from higher addresses. */
2729 for (i = 15; i--;)
2730 if ((OP[3] & (1 << type3_regs[ i ])))
2731 {
2732 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2733 SP += 4;
2734 }
2735
70caad98 2736 trace_output (OP_PUSHPOP2);
9cdd2c6d
AC		 2737
2738 return 4;
70caad98
NC		 2739}
2740
2741/* pushmh list18 */
2742int
2743OP_307E0 (void)
2744{
2745 int i;
2746
2747 trace_input ("pushmh", OP_PUSHPOP2, 0);
2748
60616228
NC		 2749 /* Store the registers with lower number registers being placed at higher addresses. */
2750 for (i = 0; i < 16; i++)
2751 if ((OP[3] & (1 << type2_regs[ i ])))
2752 {
2753 SP -= 4;
2754 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2755 }
2756
70caad98
NC		 2757 if (OP[3] & (1 << 19))
2758 {
2759 SP -= 8;
2760
2761 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2762 {
2763 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2764 store_mem ( SP & ~ 3, 4, FEPSW);
2765 }
2766 else
2767 {
2768 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2769 store_mem ( SP & ~ 3, 4, EIPSW);
2770 }
2771 }
2772
70caad98
NC		 2773 trace_output (OP_PUSHPOP2);
2774
2775 return 4;
2776}
2777
2778/* end-sanitize-v850eq */
GDB Binutils - Deliverables
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