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c906108c SS |
1 | #include "sim-main.h" |
2 | #include "v850_sim.h" | |
3 | #include "simops.h" | |
4 | ||
4389ce38 MK |
5 | #include <sys/types.h> |
6 | ||
c906108c SS |
7 | #ifdef HAVE_UTIME_H |
8 | #include <utime.h> | |
9 | #endif | |
10 | ||
11 | #ifdef HAVE_TIME_H | |
12 | #include <time.h> | |
13 | #endif | |
14 | ||
15 | #ifdef HAVE_UNISTD_H | |
16 | #include <unistd.h> | |
17 | #endif | |
18 | ||
19 | #ifdef HAVE_STRING_H | |
20 | #include <string.h> | |
21 | #else | |
22 | #ifdef HAVE_STRINGS_H | |
23 | #include <strings.h> | |
24 | #endif | |
25 | #endif | |
26 | ||
27 | #include "targ-vals.h" | |
28 | ||
29 | #include "libiberty.h" | |
30 | ||
31 | #include <errno.h> | |
32 | #if !defined(__GO32__) && !defined(_WIN32) | |
33 | #include <sys/stat.h> | |
34 | #include <sys/times.h> | |
35 | #include <sys/time.h> | |
36 | #endif | |
37 | ||
38 | /* This is an array of the bit positions of registers r20 .. r31 in | |
39 | that order in a prepare/dispose instruction. */ | |
40 | int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 }; | |
41 | /* This is an array of the bit positions of registers r16 .. r31 in | |
42 | that order in a push/pop instruction. */ | |
43 | int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; | |
44 | /* This is an array of the bit positions of registers r1 .. r15 in | |
45 | that order in a push/pop instruction. */ | |
46 | int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; | |
47 | ||
48 | #ifdef DEBUG | |
49 | #ifndef SIZE_INSTRUCTION | |
50 | #define SIZE_INSTRUCTION 18 | |
51 | #endif | |
52 | ||
53 | #ifndef SIZE_VALUES | |
54 | #define SIZE_VALUES 11 | |
55 | #endif | |
56 | ||
57 | ||
58 | unsigned32 trace_values[3]; | |
59 | int trace_num_values; | |
60 | unsigned32 trace_pc; | |
61 | const char *trace_name; | |
62 | int trace_module; | |
63 | ||
64 | ||
65 | void | |
66 | trace_input (name, type, size) | |
67 | char *name; | |
68 | enum op_types type; | |
69 | int size; | |
70 | { | |
71 | ||
72 | if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) | |
73 | return; | |
74 | ||
75 | trace_pc = PC; | |
76 | trace_name = name; | |
77 | trace_module = TRACE_ALU_IDX; | |
78 | ||
79 | switch (type) | |
80 | { | |
81 | default: | |
82 | case OP_UNKNOWN: | |
83 | case OP_NONE: | |
84 | case OP_TRAP: | |
85 | trace_num_values = 0; | |
86 | break; | |
87 | ||
88 | case OP_REG: | |
89 | case OP_REG_REG_MOVE: | |
90 | trace_values[0] = State.regs[OP[0]]; | |
91 | trace_num_values = 1; | |
92 | break; | |
93 | ||
94 | case OP_BIT_CHANGE: | |
95 | case OP_REG_REG: | |
96 | case OP_REG_REG_CMP: | |
97 | trace_values[0] = State.regs[OP[1]]; | |
98 | trace_values[1] = State.regs[OP[0]]; | |
99 | trace_num_values = 2; | |
100 | break; | |
101 | ||
102 | case OP_IMM_REG: | |
103 | case OP_IMM_REG_CMP: | |
104 | trace_values[0] = SEXT5 (OP[0]); | |
105 | trace_values[1] = OP[1]; | |
106 | trace_num_values = 2; | |
107 | break; | |
108 | ||
109 | case OP_IMM_REG_MOVE: | |
110 | trace_values[0] = SEXT5 (OP[0]); | |
111 | trace_num_values = 1; | |
112 | break; | |
113 | ||
114 | case OP_COND_BR: | |
115 | trace_values[0] = State.pc; | |
116 | trace_values[1] = SEXT9 (OP[0]); | |
117 | trace_values[2] = PSW; | |
118 | trace_num_values = 3; | |
119 | break; | |
120 | ||
121 | case OP_LOAD16: | |
122 | trace_values[0] = OP[1] * size; | |
123 | trace_values[1] = State.regs[30]; | |
124 | trace_num_values = 2; | |
125 | break; | |
126 | ||
127 | case OP_STORE16: | |
128 | trace_values[0] = State.regs[OP[0]]; | |
129 | trace_values[1] = OP[1] * size; | |
130 | trace_values[2] = State.regs[30]; | |
131 | trace_num_values = 3; | |
132 | break; | |
133 | ||
134 | case OP_LOAD32: | |
135 | trace_values[0] = EXTEND16 (OP[2]); | |
136 | trace_values[1] = State.regs[OP[0]]; | |
137 | trace_num_values = 2; | |
138 | break; | |
139 | ||
140 | case OP_STORE32: | |
141 | trace_values[0] = State.regs[OP[1]]; | |
142 | trace_values[1] = EXTEND16 (OP[2]); | |
143 | trace_values[2] = State.regs[OP[0]]; | |
144 | trace_num_values = 3; | |
145 | break; | |
146 | ||
147 | case OP_JUMP: | |
148 | trace_values[0] = SEXT22 (OP[0]); | |
149 | trace_values[1] = State.pc; | |
150 | trace_num_values = 2; | |
151 | break; | |
152 | ||
153 | case OP_IMM_REG_REG: | |
154 | trace_values[0] = EXTEND16 (OP[0]) << size; | |
155 | trace_values[1] = State.regs[OP[1]]; | |
156 | trace_num_values = 2; | |
157 | break; | |
158 | ||
159 | case OP_IMM16_REG_REG: | |
160 | trace_values[0] = EXTEND16 (OP[2]) << size; | |
161 | trace_values[1] = State.regs[OP[1]]; | |
162 | trace_num_values = 2; | |
163 | break; | |
164 | ||
165 | case OP_UIMM_REG_REG: | |
166 | trace_values[0] = (OP[0] & 0xffff) << size; | |
167 | trace_values[1] = State.regs[OP[1]]; | |
168 | trace_num_values = 2; | |
169 | break; | |
170 | ||
171 | case OP_UIMM16_REG_REG: | |
172 | trace_values[0] = (OP[2]) << size; | |
173 | trace_values[1] = State.regs[OP[1]]; | |
174 | trace_num_values = 2; | |
175 | break; | |
176 | ||
177 | case OP_BIT: | |
178 | trace_num_values = 0; | |
179 | break; | |
180 | ||
181 | case OP_EX1: | |
182 | trace_values[0] = PSW; | |
183 | trace_num_values = 1; | |
184 | break; | |
185 | ||
186 | case OP_EX2: | |
187 | trace_num_values = 0; | |
188 | break; | |
189 | ||
190 | case OP_LDSR: | |
191 | trace_values[0] = State.regs[OP[0]]; | |
192 | trace_num_values = 1; | |
193 | break; | |
194 | ||
195 | case OP_STSR: | |
196 | trace_values[0] = State.sregs[OP[1]]; | |
197 | trace_num_values = 1; | |
198 | } | |
199 | ||
200 | } | |
201 | ||
202 | void | |
203 | trace_result (int has_result, unsigned32 result) | |
204 | { | |
205 | char buf[1000]; | |
206 | char *chp; | |
207 | ||
208 | buf[0] = '\0'; | |
209 | chp = buf; | |
210 | ||
211 | /* write out the values saved during the trace_input call */ | |
212 | { | |
213 | int i; | |
214 | for (i = 0; i < trace_num_values; i++) | |
215 | { | |
d62274a3 AC |
216 | sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", |
217 | (long) trace_values[i]); | |
c906108c SS |
218 | chp = strchr (chp, '\0'); |
219 | } | |
220 | while (i++ < 3) | |
221 | { | |
222 | sprintf (chp, "%*s", SIZE_VALUES, ""); | |
223 | chp = strchr (chp, '\0'); | |
224 | } | |
225 | } | |
226 | ||
227 | /* append any result to the end of the buffer */ | |
228 | if (has_result) | |
229 | sprintf (chp, " :: 0x%.8lx", (unsigned long)result); | |
230 | ||
231 | trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf); | |
232 | } | |
233 | ||
234 | void | |
235 | trace_output (result) | |
236 | enum op_types result; | |
237 | { | |
238 | if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) | |
239 | return; | |
240 | ||
241 | switch (result) | |
242 | { | |
243 | default: | |
244 | case OP_UNKNOWN: | |
245 | case OP_NONE: | |
246 | case OP_TRAP: | |
247 | case OP_REG: | |
248 | case OP_REG_REG_CMP: | |
249 | case OP_IMM_REG_CMP: | |
250 | case OP_COND_BR: | |
251 | case OP_STORE16: | |
252 | case OP_STORE32: | |
253 | case OP_BIT: | |
254 | case OP_EX2: | |
255 | trace_result (0, 0); | |
256 | break; | |
257 | ||
258 | case OP_LOAD16: | |
259 | case OP_STSR: | |
260 | trace_result (1, State.regs[OP[0]]); | |
261 | break; | |
262 | ||
263 | case OP_REG_REG: | |
264 | case OP_REG_REG_MOVE: | |
265 | case OP_IMM_REG: | |
266 | case OP_IMM_REG_MOVE: | |
267 | case OP_LOAD32: | |
268 | case OP_EX1: | |
269 | trace_result (1, State.regs[OP[1]]); | |
270 | break; | |
271 | ||
272 | case OP_IMM_REG_REG: | |
273 | case OP_UIMM_REG_REG: | |
274 | case OP_IMM16_REG_REG: | |
275 | case OP_UIMM16_REG_REG: | |
276 | trace_result (1, State.regs[OP[1]]); | |
277 | break; | |
278 | ||
279 | case OP_JUMP: | |
280 | if (OP[1] != 0) | |
281 | trace_result (1, State.regs[OP[1]]); | |
282 | else | |
283 | trace_result (0, 0); | |
284 | break; | |
285 | ||
286 | case OP_LDSR: | |
287 | trace_result (1, State.sregs[OP[1]]); | |
288 | break; | |
289 | } | |
290 | } | |
291 | #endif | |
292 | ||
293 | \f | |
294 | /* Returns 1 if the specific condition is met, returns 0 otherwise. */ | |
295 | int | |
296 | condition_met (unsigned code) | |
297 | { | |
298 | unsigned int psw = PSW; | |
299 | ||
300 | switch (code & 0xf) | |
301 | { | |
302 | case 0x0: return ((psw & PSW_OV) != 0); | |
303 | case 0x1: return ((psw & PSW_CY) != 0); | |
304 | case 0x2: return ((psw & PSW_Z) != 0); | |
305 | case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0); | |
306 | case 0x4: return ((psw & PSW_S) != 0); | |
307 | /*case 0x5: return 1;*/ | |
308 | case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0); | |
309 | case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0); | |
310 | case 0x8: return ((psw & PSW_OV) == 0); | |
311 | case 0x9: return ((psw & PSW_CY) == 0); | |
312 | case 0xa: return ((psw & PSW_Z) == 0); | |
313 | case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0); | |
314 | case 0xc: return ((psw & PSW_S) == 0); | |
315 | case 0xd: return ((psw & PSW_SAT) != 0); | |
316 | case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0); | |
317 | case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0); | |
318 | } | |
319 | ||
320 | return 1; | |
321 | } | |
322 | ||
2aaed979 | 323 | unsigned long |
c906108c SS |
324 | Add32 (unsigned long a1, unsigned long a2, int * carry) |
325 | { | |
326 | unsigned long result = (a1 + a2); | |
327 | ||
328 | * carry = (result < a1); | |
329 | ||
330 | return result; | |
331 | } | |
332 | ||
333 | static void | |
0da2b665 | 334 | Multiply64 (int sign, unsigned long op0) |
c906108c SS |
335 | { |
336 | unsigned long op1; | |
337 | unsigned long lo; | |
338 | unsigned long mid1; | |
339 | unsigned long mid2; | |
340 | unsigned long hi; | |
341 | unsigned long RdLo; | |
342 | unsigned long RdHi; | |
343 | int carry; | |
344 | ||
345 | op1 = State.regs[ OP[1] ]; | |
346 | ||
347 | if (sign) | |
348 | { | |
349 | /* Compute sign of result and adjust operands if necessary. */ | |
350 | ||
351 | sign = (op0 ^ op1) & 0x80000000; | |
352 | ||
353 | if (((signed long) op0) < 0) | |
354 | op0 = - op0; | |
355 | ||
356 | if (((signed long) op1) < 0) | |
357 | op1 = - op1; | |
358 | } | |
359 | ||
360 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
361 | that we do not lose precision on 32bit only hosts: */ | |
362 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
363 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
364 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
365 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
366 | ||
367 | /* We now need to add all of these results together, taking care | |
368 | to propogate the carries from the additions: */ | |
369 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
370 | RdHi = carry; | |
371 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
372 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
373 | ||
374 | if (sign) | |
375 | { | |
376 | /* Negate result if necessary. */ | |
377 | ||
378 | RdLo = ~ RdLo; | |
379 | RdHi = ~ RdHi; | |
380 | if (RdLo == 0xFFFFFFFF) | |
381 | { | |
382 | RdLo = 0; | |
383 | RdHi += 1; | |
384 | } | |
385 | else | |
386 | RdLo += 1; | |
387 | } | |
388 | ||
389 | /* Don't store into register 0. */ | |
390 | if (OP[1]) | |
391 | State.regs[ OP[1] ] = RdLo; | |
392 | if (OP[2] >> 11) | |
393 | State.regs[ OP[2] >> 11 ] = RdHi; | |
394 | ||
395 | return; | |
396 | } | |
397 | ||
398 | \f | |
399 | /* Read a null terminated string from memory, return in a buffer */ | |
400 | static char * | |
401 | fetch_str (sd, addr) | |
402 | SIM_DESC sd; | |
403 | address_word addr; | |
404 | { | |
405 | char *buf; | |
406 | int nr = 0; | |
407 | while (sim_core_read_1 (STATE_CPU (sd, 0), | |
408 | PC, read_map, addr + nr) != 0) | |
409 | nr++; | |
410 | buf = NZALLOC (char, nr + 1); | |
411 | sim_read (simulator, addr, buf, nr); | |
412 | return buf; | |
413 | } | |
414 | ||
415 | /* Read a null terminated argument vector from memory, return in a | |
416 | buffer */ | |
417 | static char ** | |
418 | fetch_argv (sd, addr) | |
419 | SIM_DESC sd; | |
420 | address_word addr; | |
421 | { | |
422 | int max_nr = 64; | |
423 | int nr = 0; | |
424 | char **buf = xmalloc (max_nr * sizeof (char*)); | |
425 | while (1) | |
426 | { | |
427 | unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0), | |
428 | PC, read_map, addr + nr * 4); | |
429 | if (a == 0) break; | |
430 | buf[nr] = fetch_str (sd, a); | |
431 | nr ++; | |
432 | if (nr == max_nr - 1) | |
433 | { | |
434 | max_nr += 50; | |
435 | buf = xrealloc (buf, max_nr * sizeof (char*)); | |
436 | } | |
437 | } | |
438 | buf[nr] = 0; | |
439 | return buf; | |
440 | } | |
441 | ||
442 | \f | |
443 | /* sst.b */ | |
444 | int | |
445 | OP_380 () | |
446 | { | |
447 | trace_input ("sst.b", OP_STORE16, 1); | |
448 | ||
449 | store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]); | |
450 | ||
451 | trace_output (OP_STORE16); | |
452 | ||
453 | return 2; | |
454 | } | |
455 | ||
456 | /* sst.h */ | |
457 | int | |
458 | OP_480 () | |
459 | { | |
460 | trace_input ("sst.h", OP_STORE16, 2); | |
461 | ||
462 | store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]); | |
463 | ||
464 | trace_output (OP_STORE16); | |
465 | ||
466 | return 2; | |
467 | } | |
468 | ||
469 | /* sst.w */ | |
470 | int | |
471 | OP_501 () | |
472 | { | |
473 | trace_input ("sst.w", OP_STORE16, 4); | |
474 | ||
475 | store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]); | |
476 | ||
477 | trace_output (OP_STORE16); | |
478 | ||
479 | return 2; | |
480 | } | |
481 | ||
482 | /* ld.b */ | |
483 | int | |
484 | OP_700 () | |
485 | { | |
486 | int adr; | |
487 | ||
488 | trace_input ("ld.b", OP_LOAD32, 1); | |
489 | ||
490 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
491 | ||
492 | State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1)); | |
493 | ||
494 | trace_output (OP_LOAD32); | |
495 | ||
496 | return 4; | |
497 | } | |
498 | ||
499 | /* ld.h */ | |
500 | int | |
501 | OP_720 () | |
502 | { | |
503 | int adr; | |
504 | ||
505 | trace_input ("ld.h", OP_LOAD32, 2); | |
506 | ||
507 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
508 | adr &= ~0x1; | |
509 | ||
510 | State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2)); | |
511 | ||
512 | trace_output (OP_LOAD32); | |
513 | ||
514 | return 4; | |
515 | } | |
516 | ||
517 | /* ld.w */ | |
518 | int | |
519 | OP_10720 () | |
520 | { | |
521 | int adr; | |
522 | ||
523 | trace_input ("ld.w", OP_LOAD32, 4); | |
524 | ||
525 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
526 | adr &= ~0x3; | |
527 | ||
528 | State.regs[ OP[1] ] = load_mem (adr, 4); | |
529 | ||
530 | trace_output (OP_LOAD32); | |
531 | ||
532 | return 4; | |
533 | } | |
534 | ||
535 | /* st.b */ | |
536 | int | |
537 | OP_740 () | |
538 | { | |
539 | trace_input ("st.b", OP_STORE32, 1); | |
540 | ||
541 | store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]); | |
542 | ||
543 | trace_output (OP_STORE32); | |
544 | ||
545 | return 4; | |
546 | } | |
547 | ||
548 | /* st.h */ | |
549 | int | |
550 | OP_760 () | |
551 | { | |
552 | int adr; | |
553 | ||
554 | trace_input ("st.h", OP_STORE32, 2); | |
555 | ||
556 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
557 | adr &= ~1; | |
558 | ||
559 | store_mem (adr, 2, State.regs[ OP[1] ]); | |
560 | ||
561 | trace_output (OP_STORE32); | |
562 | ||
563 | return 4; | |
564 | } | |
565 | ||
566 | /* st.w */ | |
567 | int | |
568 | OP_10760 () | |
569 | { | |
570 | int adr; | |
571 | ||
572 | trace_input ("st.w", OP_STORE32, 4); | |
573 | ||
574 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
575 | adr &= ~3; | |
576 | ||
577 | store_mem (adr, 4, State.regs[ OP[1] ]); | |
578 | ||
579 | trace_output (OP_STORE32); | |
580 | ||
581 | return 4; | |
582 | } | |
583 | ||
584 | /* add reg, reg */ | |
585 | int | |
586 | OP_1C0 () | |
587 | { | |
588 | unsigned int op0, op1, result, z, s, cy, ov; | |
589 | ||
590 | trace_input ("add", OP_REG_REG, 0); | |
591 | ||
592 | /* Compute the result. */ | |
593 | ||
594 | op0 = State.regs[ OP[0] ]; | |
595 | op1 = State.regs[ OP[1] ]; | |
596 | ||
597 | result = op0 + op1; | |
598 | ||
599 | /* Compute the condition codes. */ | |
600 | z = (result == 0); | |
601 | s = (result & 0x80000000); | |
602 | cy = (result < op0 || result < op1); | |
603 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
604 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
605 | ||
606 | /* Store the result and condition codes. */ | |
607 | State.regs[OP[1]] = result; | |
608 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
609 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
610 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
611 | trace_output (OP_REG_REG); | |
612 | ||
613 | return 2; | |
614 | } | |
615 | ||
616 | /* add sign_extend(imm5), reg */ | |
617 | int | |
618 | OP_240 () | |
619 | { | |
620 | unsigned int op0, op1, result, z, s, cy, ov; | |
621 | int temp; | |
622 | ||
623 | trace_input ("add", OP_IMM_REG, 0); | |
624 | ||
625 | /* Compute the result. */ | |
626 | temp = SEXT5 (OP[0]); | |
627 | op0 = temp; | |
628 | op1 = State.regs[OP[1]]; | |
629 | result = op0 + op1; | |
630 | ||
631 | /* Compute the condition codes. */ | |
632 | z = (result == 0); | |
633 | s = (result & 0x80000000); | |
634 | cy = (result < op0 || result < op1); | |
635 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
636 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
637 | ||
638 | /* Store the result and condition codes. */ | |
639 | State.regs[OP[1]] = result; | |
640 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
641 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
642 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
643 | trace_output (OP_IMM_REG); | |
644 | ||
645 | return 2; | |
646 | } | |
647 | ||
648 | /* addi sign_extend(imm16), reg, reg */ | |
649 | int | |
650 | OP_600 () | |
651 | { | |
652 | unsigned int op0, op1, result, z, s, cy, ov; | |
653 | ||
654 | trace_input ("addi", OP_IMM16_REG_REG, 0); | |
655 | ||
656 | /* Compute the result. */ | |
657 | ||
658 | op0 = EXTEND16 (OP[2]); | |
659 | op1 = State.regs[ OP[0] ]; | |
660 | result = op0 + op1; | |
661 | ||
662 | /* Compute the condition codes. */ | |
663 | z = (result == 0); | |
664 | s = (result & 0x80000000); | |
665 | cy = (result < op0 || result < op1); | |
666 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
667 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
668 | ||
669 | /* Store the result and condition codes. */ | |
670 | State.regs[OP[1]] = result; | |
671 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
672 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
673 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
674 | trace_output (OP_IMM16_REG_REG); | |
675 | ||
676 | return 4; | |
677 | } | |
678 | ||
679 | /* sub reg1, reg2 */ | |
680 | int | |
681 | OP_1A0 () | |
682 | { | |
683 | unsigned int op0, op1, result, z, s, cy, ov; | |
684 | ||
685 | trace_input ("sub", OP_REG_REG, 0); | |
686 | /* Compute the result. */ | |
687 | op0 = State.regs[ OP[0] ]; | |
688 | op1 = State.regs[ OP[1] ]; | |
689 | result = op1 - op0; | |
690 | ||
691 | /* Compute the condition codes. */ | |
692 | z = (result == 0); | |
693 | s = (result & 0x80000000); | |
694 | cy = (op1 < op0); | |
695 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
696 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
697 | ||
698 | /* Store the result and condition codes. */ | |
699 | State.regs[OP[1]] = result; | |
700 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
701 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
702 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
703 | trace_output (OP_REG_REG); | |
704 | ||
705 | return 2; | |
706 | } | |
707 | ||
708 | /* subr reg1, reg2 */ | |
709 | int | |
710 | OP_180 () | |
711 | { | |
712 | unsigned int op0, op1, result, z, s, cy, ov; | |
713 | ||
714 | trace_input ("subr", OP_REG_REG, 0); | |
715 | /* Compute the result. */ | |
716 | op0 = State.regs[ OP[0] ]; | |
717 | op1 = State.regs[ OP[1] ]; | |
718 | result = op0 - op1; | |
719 | ||
720 | /* Compute the condition codes. */ | |
721 | z = (result == 0); | |
722 | s = (result & 0x80000000); | |
723 | cy = (op0 < op1); | |
724 | ov = ((op0 & 0x80000000) != (op1 & 0x80000000) | |
725 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
726 | ||
727 | /* Store the result and condition codes. */ | |
728 | State.regs[OP[1]] = result; | |
729 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
730 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
731 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
732 | trace_output (OP_REG_REG); | |
733 | ||
734 | return 2; | |
735 | } | |
736 | ||
737 | /* sxh reg1 */ | |
738 | int | |
739 | OP_E0 () | |
740 | { | |
741 | trace_input ("mulh", OP_REG_REG, 0); | |
742 | ||
743 | State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ])); | |
744 | ||
745 | trace_output (OP_REG_REG); | |
746 | ||
747 | return 2; | |
748 | } | |
749 | ||
750 | /* mulh sign_extend(imm5), reg2 */ | |
751 | int | |
752 | OP_2E0 () | |
753 | { | |
754 | trace_input ("mulh", OP_IMM_REG, 0); | |
755 | ||
756 | State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]); | |
757 | ||
758 | trace_output (OP_IMM_REG); | |
759 | ||
760 | return 2; | |
761 | } | |
762 | ||
763 | /* mulhi imm16, reg1, reg2 */ | |
764 | int | |
765 | OP_6E0 () | |
766 | { | |
767 | trace_input ("mulhi", OP_IMM16_REG_REG, 0); | |
768 | ||
769 | State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]); | |
770 | ||
771 | trace_output (OP_IMM16_REG_REG); | |
772 | ||
773 | return 4; | |
774 | } | |
775 | ||
c906108c SS |
776 | /* cmp reg, reg */ |
777 | int | |
778 | OP_1E0 () | |
779 | { | |
780 | unsigned int op0, op1, result, z, s, cy, ov; | |
781 | ||
782 | trace_input ("cmp", OP_REG_REG_CMP, 0); | |
783 | /* Compute the result. */ | |
784 | op0 = State.regs[ OP[0] ]; | |
785 | op1 = State.regs[ OP[1] ]; | |
786 | result = op1 - op0; | |
787 | ||
788 | /* Compute the condition codes. */ | |
789 | z = (result == 0); | |
790 | s = (result & 0x80000000); | |
791 | cy = (op1 < op0); | |
792 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
793 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
794 | ||
795 | /* Set condition codes. */ | |
796 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
797 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
798 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
799 | trace_output (OP_REG_REG_CMP); | |
800 | ||
801 | return 2; | |
802 | } | |
803 | ||
804 | /* cmp sign_extend(imm5), reg */ | |
805 | int | |
806 | OP_260 () | |
807 | { | |
808 | unsigned int op0, op1, result, z, s, cy, ov; | |
809 | int temp; | |
810 | ||
811 | /* Compute the result. */ | |
812 | trace_input ("cmp", OP_IMM_REG_CMP, 0); | |
813 | temp = SEXT5 (OP[0]); | |
814 | op0 = temp; | |
815 | op1 = State.regs[OP[1]]; | |
816 | result = op1 - op0; | |
817 | ||
818 | /* Compute the condition codes. */ | |
819 | z = (result == 0); | |
820 | s = (result & 0x80000000); | |
821 | cy = (op1 < op0); | |
822 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
823 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
824 | ||
825 | /* Set condition codes. */ | |
826 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
827 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
828 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
829 | trace_output (OP_IMM_REG_CMP); | |
830 | ||
831 | return 2; | |
832 | } | |
833 | ||
834 | /* setf cccc,reg2 */ | |
835 | int | |
836 | OP_7E0 () | |
837 | { | |
838 | trace_input ("setf", OP_EX1, 0); | |
839 | ||
840 | State.regs[ OP[1] ] = condition_met (OP[0]); | |
841 | ||
842 | trace_output (OP_EX1); | |
843 | ||
844 | return 4; | |
845 | } | |
846 | ||
847 | /* satadd reg,reg */ | |
848 | int | |
849 | OP_C0 () | |
850 | { | |
851 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
852 | ||
853 | trace_input ("satadd", OP_REG_REG, 0); | |
854 | /* Compute the result. */ | |
855 | op0 = State.regs[ OP[0] ]; | |
856 | op1 = State.regs[ OP[1] ]; | |
857 | result = op0 + op1; | |
858 | ||
859 | /* Compute the condition codes. */ | |
860 | z = (result == 0); | |
861 | s = (result & 0x80000000); | |
862 | cy = (result < op0 || result < op1); | |
863 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
864 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
865 | sat = ov; | |
866 | ||
c5fbc25b DD |
867 | /* Handle saturated results. */ |
868 | if (sat && s) | |
869 | { | |
870 | /* An overflow that results in a negative result implies that we | |
871 | became too positive. */ | |
872 | result = 0x7fffffff; | |
873 | s = 0; | |
874 | } | |
875 | else if (sat) | |
876 | { | |
877 | /* Any other overflow must have thus been too negative. */ | |
878 | result = 0x80000000; | |
879 | s = 1; | |
880 | z = 0; | |
881 | } | |
882 | ||
c906108c SS |
883 | /* Store the result and condition codes. */ |
884 | State.regs[OP[1]] = result; | |
885 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
886 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
887 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
888 | | (sat ? PSW_SAT : 0)); | |
c5fbc25b | 889 | |
c906108c SS |
890 | trace_output (OP_REG_REG); |
891 | ||
892 | return 2; | |
893 | } | |
894 | ||
895 | /* satadd sign_extend(imm5), reg */ | |
896 | int | |
897 | OP_220 () | |
898 | { | |
899 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
900 | ||
901 | int temp; | |
902 | ||
903 | trace_input ("satadd", OP_IMM_REG, 0); | |
904 | ||
905 | /* Compute the result. */ | |
906 | temp = SEXT5 (OP[0]); | |
907 | op0 = temp; | |
908 | op1 = State.regs[OP[1]]; | |
909 | result = op0 + op1; | |
910 | ||
911 | /* Compute the condition codes. */ | |
912 | z = (result == 0); | |
913 | s = (result & 0x80000000); | |
914 | cy = (result < op0 || result < op1); | |
915 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
916 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
917 | sat = ov; | |
918 | ||
c5fbc25b DD |
919 | /* Handle saturated results. */ |
920 | if (sat && s) | |
921 | { | |
922 | /* An overflow that results in a negative result implies that we | |
923 | became too positive. */ | |
924 | result = 0x7fffffff; | |
925 | s = 0; | |
926 | } | |
927 | else if (sat) | |
928 | { | |
929 | /* Any other overflow must have thus been too negative. */ | |
930 | result = 0x80000000; | |
931 | s = 1; | |
932 | z = 0; | |
933 | } | |
934 | ||
c906108c SS |
935 | /* Store the result and condition codes. */ |
936 | State.regs[OP[1]] = result; | |
937 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
938 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
939 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
940 | | (sat ? PSW_SAT : 0)); | |
c906108c SS |
941 | trace_output (OP_IMM_REG); |
942 | ||
943 | return 2; | |
944 | } | |
945 | ||
946 | /* satsub reg1, reg2 */ | |
947 | int | |
948 | OP_A0 () | |
949 | { | |
950 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
951 | ||
952 | trace_input ("satsub", OP_REG_REG, 0); | |
953 | ||
954 | /* Compute the result. */ | |
955 | op0 = State.regs[ OP[0] ]; | |
956 | op1 = State.regs[ OP[1] ]; | |
957 | result = op1 - op0; | |
958 | ||
959 | /* Compute the condition codes. */ | |
960 | z = (result == 0); | |
961 | s = (result & 0x80000000); | |
962 | cy = (op1 < op0); | |
963 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
964 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
965 | sat = ov; | |
c5fbc25b DD |
966 | |
967 | /* Handle saturated results. */ | |
968 | if (sat && s) | |
969 | { | |
970 | /* An overflow that results in a negative result implies that we | |
971 | became too positive. */ | |
972 | result = 0x7fffffff; | |
973 | s = 0; | |
974 | } | |
975 | else if (sat) | |
976 | { | |
977 | /* Any other overflow must have thus been too negative. */ | |
978 | result = 0x80000000; | |
979 | s = 1; | |
980 | z = 0; | |
981 | } | |
982 | ||
c906108c SS |
983 | /* Store the result and condition codes. */ |
984 | State.regs[OP[1]] = result; | |
985 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
986 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
987 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
988 | | (sat ? PSW_SAT : 0)); | |
989 | ||
c906108c SS |
990 | trace_output (OP_REG_REG); |
991 | return 2; | |
992 | } | |
993 | ||
994 | /* satsubi sign_extend(imm16), reg */ | |
995 | int | |
996 | OP_660 () | |
997 | { | |
998 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
999 | int temp; | |
1000 | ||
1001 | trace_input ("satsubi", OP_IMM_REG, 0); | |
1002 | ||
1003 | /* Compute the result. */ | |
1004 | temp = EXTEND16 (OP[2]); | |
1005 | op0 = temp; | |
1006 | op1 = State.regs[ OP[0] ]; | |
1007 | result = op1 - op0; | |
1008 | ||
1009 | /* Compute the condition codes. */ | |
1010 | z = (result == 0); | |
1011 | s = (result & 0x80000000); | |
1012 | cy = (op1 < op0); | |
1013 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
1014 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
1015 | sat = ov; | |
1016 | ||
c5fbc25b DD |
1017 | /* Handle saturated results. */ |
1018 | if (sat && s) | |
1019 | { | |
1020 | /* An overflow that results in a negative result implies that we | |
1021 | became too positive. */ | |
1022 | result = 0x7fffffff; | |
1023 | s = 0; | |
1024 | } | |
1025 | else if (sat) | |
1026 | { | |
1027 | /* Any other overflow must have thus been too negative. */ | |
1028 | result = 0x80000000; | |
1029 | s = 1; | |
1030 | z = 0; | |
1031 | } | |
1032 | ||
c906108c SS |
1033 | /* Store the result and condition codes. */ |
1034 | State.regs[OP[1]] = result; | |
1035 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
1036 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1037 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
1038 | | (sat ? PSW_SAT : 0)); | |
1039 | ||
c906108c SS |
1040 | trace_output (OP_IMM_REG); |
1041 | ||
1042 | return 4; | |
1043 | } | |
1044 | ||
1045 | /* satsubr reg,reg */ | |
1046 | int | |
1047 | OP_80 () | |
1048 | { | |
1049 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
1050 | ||
1051 | trace_input ("satsubr", OP_REG_REG, 0); | |
1052 | ||
1053 | /* Compute the result. */ | |
1054 | op0 = State.regs[ OP[0] ]; | |
1055 | op1 = State.regs[ OP[1] ]; | |
1056 | result = op0 - op1; | |
1057 | ||
1058 | /* Compute the condition codes. */ | |
1059 | z = (result == 0); | |
1060 | s = (result & 0x80000000); | |
c5fbc25b DD |
1061 | cy = (op0 < op1); |
1062 | ov = ((op0 & 0x80000000) != (op1 & 0x80000000) | |
1063 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
c906108c | 1064 | sat = ov; |
c5fbc25b DD |
1065 | |
1066 | /* Handle saturated results. */ | |
1067 | if (sat && s) | |
1068 | { | |
1069 | /* An overflow that results in a negative result implies that we | |
1070 | became too positive. */ | |
1071 | result = 0x7fffffff; | |
1072 | s = 0; | |
1073 | } | |
1074 | else if (sat) | |
1075 | { | |
1076 | /* Any other overflow must have thus been too negative. */ | |
1077 | result = 0x80000000; | |
1078 | s = 1; | |
1079 | z = 0; | |
1080 | } | |
c906108c SS |
1081 | |
1082 | /* Store the result and condition codes. */ | |
1083 | State.regs[OP[1]] = result; | |
1084 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
1085 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1086 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
1087 | | (sat ? PSW_SAT : 0)); | |
1088 | ||
c906108c SS |
1089 | trace_output (OP_REG_REG); |
1090 | ||
1091 | return 2; | |
1092 | } | |
1093 | ||
1094 | /* tst reg,reg */ | |
1095 | int | |
1096 | OP_160 () | |
1097 | { | |
1098 | unsigned int op0, op1, result, z, s; | |
1099 | ||
1100 | trace_input ("tst", OP_REG_REG_CMP, 0); | |
1101 | ||
1102 | /* Compute the result. */ | |
1103 | op0 = State.regs[ OP[0] ]; | |
1104 | op1 = State.regs[ OP[1] ]; | |
1105 | result = op0 & op1; | |
1106 | ||
1107 | /* Compute the condition codes. */ | |
1108 | z = (result == 0); | |
1109 | s = (result & 0x80000000); | |
1110 | ||
1111 | /* Store the condition codes. */ | |
1112 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1113 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1114 | trace_output (OP_REG_REG_CMP); | |
1115 | ||
1116 | return 2; | |
1117 | } | |
1118 | ||
1119 | /* mov sign_extend(imm5), reg */ | |
1120 | int | |
1121 | OP_200 () | |
1122 | { | |
1123 | int value = SEXT5 (OP[0]); | |
1124 | ||
1125 | trace_input ("mov", OP_IMM_REG_MOVE, 0); | |
1126 | ||
1127 | State.regs[ OP[1] ] = value; | |
1128 | ||
1129 | trace_output (OP_IMM_REG_MOVE); | |
1130 | ||
1131 | return 2; | |
1132 | } | |
1133 | ||
1134 | /* movhi imm16, reg, reg */ | |
1135 | int | |
1136 | OP_640 () | |
1137 | { | |
1138 | trace_input ("movhi", OP_UIMM16_REG_REG, 16); | |
1139 | ||
1140 | State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16); | |
1141 | ||
1142 | trace_output (OP_UIMM16_REG_REG); | |
1143 | ||
1144 | return 4; | |
1145 | } | |
1146 | ||
1147 | /* sar zero_extend(imm5),reg1 */ | |
1148 | int | |
1149 | OP_2A0 () | |
1150 | { | |
1151 | unsigned int op0, op1, result, z, s, cy; | |
1152 | ||
1153 | trace_input ("sar", OP_IMM_REG, 0); | |
1154 | op0 = OP[0]; | |
1155 | op1 = State.regs[ OP[1] ]; | |
1156 | result = (signed)op1 >> op0; | |
1157 | ||
1158 | /* Compute the condition codes. */ | |
1159 | z = (result == 0); | |
1160 | s = (result & 0x80000000); | |
c5fbc25b | 1161 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1162 | |
1163 | /* Store the result and condition codes. */ | |
1164 | State.regs[ OP[1] ] = result; | |
1165 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1166 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1167 | | (cy ? PSW_CY : 0)); | |
1168 | trace_output (OP_IMM_REG); | |
1169 | ||
1170 | return 2; | |
1171 | } | |
1172 | ||
1173 | /* sar reg1, reg2 */ | |
1174 | int | |
1175 | OP_A007E0 () | |
1176 | { | |
1177 | unsigned int op0, op1, result, z, s, cy; | |
1178 | ||
1179 | trace_input ("sar", OP_REG_REG, 0); | |
1180 | ||
1181 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1182 | op1 = State.regs[ OP[1] ]; | |
1183 | result = (signed)op1 >> op0; | |
1184 | ||
1185 | /* Compute the condition codes. */ | |
1186 | z = (result == 0); | |
1187 | s = (result & 0x80000000); | |
c5fbc25b | 1188 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1189 | |
1190 | /* Store the result and condition codes. */ | |
1191 | State.regs[OP[1]] = result; | |
1192 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1193 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1194 | | (cy ? PSW_CY : 0)); | |
1195 | trace_output (OP_REG_REG); | |
1196 | ||
1197 | return 4; | |
1198 | } | |
1199 | ||
1200 | /* shl zero_extend(imm5),reg1 */ | |
1201 | int | |
1202 | OP_2C0 () | |
1203 | { | |
1204 | unsigned int op0, op1, result, z, s, cy; | |
1205 | ||
1206 | trace_input ("shl", OP_IMM_REG, 0); | |
1207 | op0 = OP[0]; | |
1208 | op1 = State.regs[ OP[1] ]; | |
1209 | result = op1 << op0; | |
1210 | ||
1211 | /* Compute the condition codes. */ | |
1212 | z = (result == 0); | |
1213 | s = (result & 0x80000000); | |
c5fbc25b | 1214 | cy = op0 ? (op1 & (1 << (32 - op0))) : 0; |
c906108c SS |
1215 | |
1216 | /* Store the result and condition codes. */ | |
1217 | State.regs[OP[1]] = result; | |
1218 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1219 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1220 | | (cy ? PSW_CY : 0)); | |
1221 | trace_output (OP_IMM_REG); | |
1222 | ||
1223 | return 2; | |
1224 | } | |
1225 | ||
1226 | /* shl reg1, reg2 */ | |
1227 | int | |
1228 | OP_C007E0 () | |
1229 | { | |
1230 | unsigned int op0, op1, result, z, s, cy; | |
1231 | ||
1232 | trace_input ("shl", OP_REG_REG, 0); | |
1233 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1234 | op1 = State.regs[ OP[1] ]; | |
1235 | result = op1 << op0; | |
1236 | ||
1237 | /* Compute the condition codes. */ | |
1238 | z = (result == 0); | |
1239 | s = (result & 0x80000000); | |
c5fbc25b | 1240 | cy = op0 ? (op1 & (1 << (32 - op0))) : 0; |
c906108c SS |
1241 | |
1242 | /* Store the result and condition codes. */ | |
1243 | State.regs[OP[1]] = result; | |
1244 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1245 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1246 | | (cy ? PSW_CY : 0)); | |
1247 | trace_output (OP_REG_REG); | |
1248 | ||
1249 | return 4; | |
1250 | } | |
1251 | ||
1252 | /* shr zero_extend(imm5),reg1 */ | |
1253 | int | |
1254 | OP_280 () | |
1255 | { | |
1256 | unsigned int op0, op1, result, z, s, cy; | |
1257 | ||
1258 | trace_input ("shr", OP_IMM_REG, 0); | |
1259 | op0 = OP[0]; | |
1260 | op1 = State.regs[ OP[1] ]; | |
1261 | result = op1 >> op0; | |
1262 | ||
1263 | /* Compute the condition codes. */ | |
1264 | z = (result == 0); | |
1265 | s = (result & 0x80000000); | |
c5fbc25b | 1266 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1267 | |
1268 | /* Store the result and condition codes. */ | |
1269 | State.regs[OP[1]] = result; | |
1270 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1271 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1272 | | (cy ? PSW_CY : 0)); | |
1273 | trace_output (OP_IMM_REG); | |
1274 | ||
1275 | return 2; | |
1276 | } | |
1277 | ||
1278 | /* shr reg1, reg2 */ | |
1279 | int | |
1280 | OP_8007E0 () | |
1281 | { | |
1282 | unsigned int op0, op1, result, z, s, cy; | |
1283 | ||
1284 | trace_input ("shr", OP_REG_REG, 0); | |
1285 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1286 | op1 = State.regs[ OP[1] ]; | |
1287 | result = op1 >> op0; | |
1288 | ||
1289 | /* Compute the condition codes. */ | |
1290 | z = (result == 0); | |
1291 | s = (result & 0x80000000); | |
c5fbc25b | 1292 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1293 | |
1294 | /* Store the result and condition codes. */ | |
1295 | State.regs[OP[1]] = result; | |
1296 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1297 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1298 | | (cy ? PSW_CY : 0)); | |
1299 | trace_output (OP_REG_REG); | |
1300 | ||
1301 | return 4; | |
1302 | } | |
1303 | ||
1304 | /* or reg, reg */ | |
1305 | int | |
1306 | OP_100 () | |
1307 | { | |
1308 | unsigned int op0, op1, result, z, s; | |
1309 | ||
1310 | trace_input ("or", OP_REG_REG, 0); | |
1311 | ||
1312 | /* Compute the result. */ | |
1313 | op0 = State.regs[ OP[0] ]; | |
1314 | op1 = State.regs[ OP[1] ]; | |
1315 | result = op0 | op1; | |
1316 | ||
1317 | /* Compute the condition codes. */ | |
1318 | z = (result == 0); | |
1319 | s = (result & 0x80000000); | |
1320 | ||
1321 | /* Store the result and condition codes. */ | |
1322 | State.regs[OP[1]] = result; | |
1323 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1324 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1325 | trace_output (OP_REG_REG); | |
1326 | ||
1327 | return 2; | |
1328 | } | |
1329 | ||
1330 | /* ori zero_extend(imm16), reg, reg */ | |
1331 | int | |
1332 | OP_680 () | |
1333 | { | |
1334 | unsigned int op0, op1, result, z, s; | |
1335 | ||
1336 | trace_input ("ori", OP_UIMM16_REG_REG, 0); | |
1337 | op0 = OP[2]; | |
1338 | op1 = State.regs[ OP[0] ]; | |
1339 | result = op0 | op1; | |
1340 | ||
1341 | /* Compute the condition codes. */ | |
1342 | z = (result == 0); | |
1343 | s = (result & 0x80000000); | |
1344 | ||
1345 | /* Store the result and condition codes. */ | |
1346 | State.regs[OP[1]] = result; | |
1347 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1348 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1349 | trace_output (OP_UIMM16_REG_REG); | |
1350 | ||
1351 | return 4; | |
1352 | } | |
1353 | ||
1354 | /* and reg, reg */ | |
1355 | int | |
1356 | OP_140 () | |
1357 | { | |
1358 | unsigned int op0, op1, result, z, s; | |
1359 | ||
1360 | trace_input ("and", OP_REG_REG, 0); | |
1361 | ||
1362 | /* Compute the result. */ | |
1363 | op0 = State.regs[ OP[0] ]; | |
1364 | op1 = State.regs[ OP[1] ]; | |
1365 | result = op0 & op1; | |
1366 | ||
1367 | /* Compute the condition codes. */ | |
1368 | z = (result == 0); | |
1369 | s = (result & 0x80000000); | |
1370 | ||
1371 | /* Store the result and condition codes. */ | |
1372 | State.regs[OP[1]] = result; | |
1373 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1374 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1375 | trace_output (OP_REG_REG); | |
1376 | ||
1377 | return 2; | |
1378 | } | |
1379 | ||
1380 | /* andi zero_extend(imm16), reg, reg */ | |
1381 | int | |
1382 | OP_6C0 () | |
1383 | { | |
1384 | unsigned int result, z; | |
1385 | ||
1386 | trace_input ("andi", OP_UIMM16_REG_REG, 0); | |
1387 | ||
1388 | result = OP[2] & State.regs[ OP[0] ]; | |
1389 | ||
1390 | /* Compute the condition codes. */ | |
1391 | z = (result == 0); | |
1392 | ||
1393 | /* Store the result and condition codes. */ | |
1394 | State.regs[ OP[1] ] = result; | |
1395 | ||
1396 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1397 | PSW |= (z ? PSW_Z : 0); | |
1398 | ||
1399 | trace_output (OP_UIMM16_REG_REG); | |
1400 | ||
1401 | return 4; | |
1402 | } | |
1403 | ||
1404 | /* xor reg, reg */ | |
1405 | int | |
1406 | OP_120 () | |
1407 | { | |
1408 | unsigned int op0, op1, result, z, s; | |
1409 | ||
1410 | trace_input ("xor", OP_REG_REG, 0); | |
1411 | ||
1412 | /* Compute the result. */ | |
1413 | op0 = State.regs[ OP[0] ]; | |
1414 | op1 = State.regs[ OP[1] ]; | |
1415 | result = op0 ^ op1; | |
1416 | ||
1417 | /* Compute the condition codes. */ | |
1418 | z = (result == 0); | |
1419 | s = (result & 0x80000000); | |
1420 | ||
1421 | /* Store the result and condition codes. */ | |
1422 | State.regs[OP[1]] = result; | |
1423 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1424 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1425 | trace_output (OP_REG_REG); | |
1426 | ||
1427 | return 2; | |
1428 | } | |
1429 | ||
1430 | /* xori zero_extend(imm16), reg, reg */ | |
1431 | int | |
1432 | OP_6A0 () | |
1433 | { | |
1434 | unsigned int op0, op1, result, z, s; | |
1435 | ||
1436 | trace_input ("xori", OP_UIMM16_REG_REG, 0); | |
1437 | op0 = OP[2]; | |
1438 | op1 = State.regs[ OP[0] ]; | |
1439 | result = op0 ^ op1; | |
1440 | ||
1441 | /* Compute the condition codes. */ | |
1442 | z = (result == 0); | |
1443 | s = (result & 0x80000000); | |
1444 | ||
1445 | /* Store the result and condition codes. */ | |
1446 | State.regs[OP[1]] = result; | |
1447 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1448 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1449 | trace_output (OP_UIMM16_REG_REG); | |
1450 | ||
1451 | return 4; | |
1452 | } | |
1453 | ||
1454 | /* not reg1, reg2 */ | |
1455 | int | |
1456 | OP_20 () | |
1457 | { | |
1458 | unsigned int op0, result, z, s; | |
1459 | ||
1460 | trace_input ("not", OP_REG_REG_MOVE, 0); | |
1461 | /* Compute the result. */ | |
1462 | op0 = State.regs[ OP[0] ]; | |
1463 | result = ~op0; | |
1464 | ||
1465 | /* Compute the condition codes. */ | |
1466 | z = (result == 0); | |
1467 | s = (result & 0x80000000); | |
1468 | ||
1469 | /* Store the result and condition codes. */ | |
1470 | State.regs[OP[1]] = result; | |
1471 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1472 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1473 | trace_output (OP_REG_REG_MOVE); | |
1474 | ||
1475 | return 2; | |
1476 | } | |
1477 | ||
1478 | /* set1 */ | |
1479 | int | |
1480 | OP_7C0 () | |
1481 | { | |
1482 | unsigned int op0, op1, op2; | |
1483 | int temp; | |
1484 | ||
1485 | trace_input ("set1", OP_BIT, 0); | |
1486 | op0 = State.regs[ OP[0] ]; | |
1487 | op1 = OP[1] & 0x7; | |
1488 | temp = EXTEND16 (OP[2]); | |
1489 | op2 = temp; | |
1490 | temp = load_mem (op0 + op2, 1); | |
1491 | PSW &= ~PSW_Z; | |
1492 | if ((temp & (1 << op1)) == 0) | |
1493 | PSW |= PSW_Z; | |
1494 | temp |= (1 << op1); | |
1495 | store_mem (op0 + op2, 1, temp); | |
1496 | trace_output (OP_BIT); | |
1497 | ||
1498 | return 4; | |
1499 | } | |
1500 | ||
1501 | /* not1 */ | |
1502 | int | |
1503 | OP_47C0 () | |
1504 | { | |
1505 | unsigned int op0, op1, op2; | |
1506 | int temp; | |
1507 | ||
1508 | trace_input ("not1", OP_BIT, 0); | |
1509 | op0 = State.regs[ OP[0] ]; | |
1510 | op1 = OP[1] & 0x7; | |
1511 | temp = EXTEND16 (OP[2]); | |
1512 | op2 = temp; | |
1513 | temp = load_mem (op0 + op2, 1); | |
1514 | PSW &= ~PSW_Z; | |
1515 | if ((temp & (1 << op1)) == 0) | |
1516 | PSW |= PSW_Z; | |
1517 | temp ^= (1 << op1); | |
1518 | store_mem (op0 + op2, 1, temp); | |
1519 | trace_output (OP_BIT); | |
1520 | ||
1521 | return 4; | |
1522 | } | |
1523 | ||
1524 | /* clr1 */ | |
1525 | int | |
1526 | OP_87C0 () | |
1527 | { | |
1528 | unsigned int op0, op1, op2; | |
1529 | int temp; | |
1530 | ||
1531 | trace_input ("clr1", OP_BIT, 0); | |
1532 | op0 = State.regs[ OP[0] ]; | |
1533 | op1 = OP[1] & 0x7; | |
1534 | temp = EXTEND16 (OP[2]); | |
1535 | op2 = temp; | |
1536 | temp = load_mem (op0 + op2, 1); | |
1537 | PSW &= ~PSW_Z; | |
1538 | if ((temp & (1 << op1)) == 0) | |
1539 | PSW |= PSW_Z; | |
1540 | temp &= ~(1 << op1); | |
1541 | store_mem (op0 + op2, 1, temp); | |
1542 | trace_output (OP_BIT); | |
1543 | ||
1544 | return 4; | |
1545 | } | |
1546 | ||
1547 | /* tst1 */ | |
1548 | int | |
1549 | OP_C7C0 () | |
1550 | { | |
1551 | unsigned int op0, op1, op2; | |
1552 | int temp; | |
1553 | ||
1554 | trace_input ("tst1", OP_BIT, 0); | |
1555 | op0 = State.regs[ OP[0] ]; | |
1556 | op1 = OP[1] & 0x7; | |
1557 | temp = EXTEND16 (OP[2]); | |
1558 | op2 = temp; | |
1559 | temp = load_mem (op0 + op2, 1); | |
1560 | PSW &= ~PSW_Z; | |
1561 | if ((temp & (1 << op1)) == 0) | |
1562 | PSW |= PSW_Z; | |
1563 | trace_output (OP_BIT); | |
1564 | ||
1565 | return 4; | |
1566 | } | |
1567 | ||
1568 | /* di */ | |
1569 | int | |
1570 | OP_16007E0 () | |
1571 | { | |
1572 | trace_input ("di", OP_NONE, 0); | |
1573 | PSW |= PSW_ID; | |
1574 | trace_output (OP_NONE); | |
1575 | ||
1576 | return 4; | |
1577 | } | |
1578 | ||
1579 | /* ei */ | |
1580 | int | |
1581 | OP_16087E0 () | |
1582 | { | |
1583 | trace_input ("ei", OP_NONE, 0); | |
1584 | PSW &= ~PSW_ID; | |
1585 | trace_output (OP_NONE); | |
1586 | ||
1587 | return 4; | |
1588 | } | |
1589 | ||
1590 | /* halt */ | |
1591 | int | |
1592 | OP_12007E0 () | |
1593 | { | |
1594 | trace_input ("halt", OP_NONE, 0); | |
1595 | /* FIXME this should put processor into a mode where NMI still handled */ | |
1596 | trace_output (OP_NONE); | |
1597 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1598 | sim_stopped, SIM_SIGTRAP); | |
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | /* trap */ | |
1603 | int | |
1604 | OP_10007E0 () | |
1605 | { | |
1606 | trace_input ("trap", OP_TRAP, 0); | |
1607 | trace_output (OP_TRAP); | |
1608 | ||
1609 | /* Trap 31 is used for simulating OS I/O functions */ | |
1610 | ||
1611 | if (OP[0] == 31) | |
1612 | { | |
1613 | int save_errno = errno; | |
1614 | errno = 0; | |
1615 | ||
1616 | /* Registers passed to trap 0 */ | |
1617 | ||
1618 | #define FUNC State.regs[6] /* function number, return value */ | |
1619 | #define PARM1 State.regs[7] /* optional parm 1 */ | |
1620 | #define PARM2 State.regs[8] /* optional parm 2 */ | |
1621 | #define PARM3 State.regs[9] /* optional parm 3 */ | |
1622 | ||
1623 | /* Registers set by trap 0 */ | |
1624 | ||
1625 | #define RETVAL State.regs[10] /* return value */ | |
1626 | #define RETERR State.regs[11] /* return error code */ | |
1627 | ||
1628 | /* Turn a pointer in a register into a pointer into real memory. */ | |
1629 | ||
1630 | #define MEMPTR(x) (map (x)) | |
1631 | ||
d0f0baa2 KB |
1632 | RETERR = 0; |
1633 | ||
c906108c SS |
1634 | switch (FUNC) |
1635 | { | |
1636 | ||
1637 | #ifdef HAVE_FORK | |
1638 | #ifdef TARGET_SYS_fork | |
1639 | case TARGET_SYS_fork: | |
1640 | RETVAL = fork (); | |
d0f0baa2 | 1641 | RETERR = errno; |
c906108c SS |
1642 | break; |
1643 | #endif | |
1644 | #endif | |
1645 | ||
1646 | #ifdef HAVE_EXECVE | |
1647 | #ifdef TARGET_SYS_execv | |
1648 | case TARGET_SYS_execve: | |
1649 | { | |
1650 | char *path = fetch_str (simulator, PARM1); | |
1651 | char **argv = fetch_argv (simulator, PARM2); | |
1652 | char **envp = fetch_argv (simulator, PARM3); | |
1653 | RETVAL = execve (path, argv, envp); | |
d79fe0d6 | 1654 | free (path); |
c906108c SS |
1655 | freeargv (argv); |
1656 | freeargv (envp); | |
d0f0baa2 | 1657 | RETERR = errno; |
c906108c SS |
1658 | break; |
1659 | } | |
1660 | #endif | |
1661 | #endif | |
1662 | ||
1663 | #if HAVE_EXECV | |
1664 | #ifdef TARGET_SYS_execv | |
1665 | case TARGET_SYS_execv: | |
1666 | { | |
1667 | char *path = fetch_str (simulator, PARM1); | |
1668 | char **argv = fetch_argv (simulator, PARM2); | |
1669 | RETVAL = execv (path, argv); | |
d79fe0d6 | 1670 | free (path); |
c906108c | 1671 | freeargv (argv); |
d0f0baa2 | 1672 | RETERR = errno; |
c906108c SS |
1673 | break; |
1674 | } | |
1675 | #endif | |
1676 | #endif | |
1677 | ||
1678 | #if 0 | |
1679 | #ifdef TARGET_SYS_pipe | |
1680 | case TARGET_SYS_pipe: | |
1681 | { | |
1682 | reg_t buf; | |
1683 | int host_fd[2]; | |
1684 | ||
1685 | buf = PARM1; | |
1686 | RETVAL = pipe (host_fd); | |
1687 | SW (buf, host_fd[0]); | |
1688 | buf += sizeof(uint16); | |
1689 | SW (buf, host_fd[1]); | |
d0f0baa2 | 1690 | RETERR = errno; |
c906108c SS |
1691 | } |
1692 | break; | |
1693 | #endif | |
1694 | #endif | |
1695 | ||
1696 | #if 0 | |
1697 | #ifdef TARGET_SYS_wait | |
1698 | case TARGET_SYS_wait: | |
1699 | { | |
1700 | int status; | |
1701 | ||
1702 | RETVAL = wait (&status); | |
1703 | SW (PARM1, status); | |
d0f0baa2 | 1704 | RETERR = errno; |
c906108c SS |
1705 | } |
1706 | break; | |
1707 | #endif | |
1708 | #endif | |
1709 | ||
1710 | #ifdef TARGET_SYS_read | |
1711 | case TARGET_SYS_read: | |
1712 | { | |
1713 | char *buf = zalloc (PARM3); | |
1714 | RETVAL = sim_io_read (simulator, PARM1, buf, PARM3); | |
1715 | sim_write (simulator, PARM2, buf, PARM3); | |
d79fe0d6 | 1716 | free (buf); |
d0f0baa2 KB |
1717 | if ((int) RETVAL < 0) |
1718 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1719 | break; |
1720 | } | |
1721 | #endif | |
1722 | ||
1723 | #ifdef TARGET_SYS_write | |
1724 | case TARGET_SYS_write: | |
1725 | { | |
1726 | char *buf = zalloc (PARM3); | |
1727 | sim_read (simulator, PARM2, buf, PARM3); | |
1728 | if (PARM1 == 1) | |
1729 | RETVAL = sim_io_write_stdout (simulator, buf, PARM3); | |
1730 | else | |
1731 | RETVAL = sim_io_write (simulator, PARM1, buf, PARM3); | |
d79fe0d6 | 1732 | free (buf); |
d0f0baa2 KB |
1733 | if ((int) RETVAL < 0) |
1734 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1735 | break; |
1736 | } | |
1737 | #endif | |
1738 | ||
1739 | #ifdef TARGET_SYS_lseek | |
1740 | case TARGET_SYS_lseek: | |
1741 | RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3); | |
d0f0baa2 KB |
1742 | if ((int) RETVAL < 0) |
1743 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1744 | break; |
1745 | #endif | |
1746 | ||
1747 | #ifdef TARGET_SYS_close | |
1748 | case TARGET_SYS_close: | |
1749 | RETVAL = sim_io_close (simulator, PARM1); | |
d0f0baa2 KB |
1750 | if ((int) RETVAL < 0) |
1751 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1752 | break; |
1753 | #endif | |
1754 | ||
1755 | #ifdef TARGET_SYS_open | |
1756 | case TARGET_SYS_open: | |
1757 | { | |
1758 | char *buf = fetch_str (simulator, PARM1); | |
1759 | RETVAL = sim_io_open (simulator, buf, PARM2); | |
d79fe0d6 | 1760 | free (buf); |
d0f0baa2 KB |
1761 | if ((int) RETVAL < 0) |
1762 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1763 | break; |
1764 | } | |
1765 | #endif | |
1766 | ||
1767 | #ifdef TARGET_SYS_exit | |
1768 | case TARGET_SYS_exit: | |
1769 | if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0) | |
1770 | /* get signal encoded by kill */ | |
1771 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1772 | sim_signalled, PARM1 & 0xffff); | |
1773 | else if (PARM1 == 0xdead) | |
1774 | /* old libraries */ | |
1775 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1776 | sim_stopped, SIM_SIGABRT); | |
1777 | else | |
1778 | /* PARM1 has exit status */ | |
1779 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1780 | sim_exited, PARM1); | |
1781 | break; | |
1782 | #endif | |
1783 | ||
c906108c SS |
1784 | #ifdef TARGET_SYS_stat |
1785 | case TARGET_SYS_stat: /* added at hmsi */ | |
1786 | /* stat system call */ | |
1787 | { | |
1788 | struct stat host_stat; | |
1789 | reg_t buf; | |
1790 | char *path = fetch_str (simulator, PARM1); | |
1791 | ||
d0f0baa2 | 1792 | RETVAL = sim_io_stat (simulator, path, &host_stat); |
c906108c | 1793 | |
d79fe0d6 | 1794 | free (path); |
c906108c SS |
1795 | buf = PARM2; |
1796 | ||
1797 | /* Just wild-assed guesses. */ | |
1798 | store_mem (buf, 2, host_stat.st_dev); | |
1799 | store_mem (buf + 2, 2, host_stat.st_ino); | |
1800 | store_mem (buf + 4, 4, host_stat.st_mode); | |
1801 | store_mem (buf + 8, 2, host_stat.st_nlink); | |
1802 | store_mem (buf + 10, 2, host_stat.st_uid); | |
1803 | store_mem (buf + 12, 2, host_stat.st_gid); | |
1804 | store_mem (buf + 14, 2, host_stat.st_rdev); | |
1805 | store_mem (buf + 16, 4, host_stat.st_size); | |
1806 | store_mem (buf + 20, 4, host_stat.st_atime); | |
1807 | store_mem (buf + 28, 4, host_stat.st_mtime); | |
1808 | store_mem (buf + 36, 4, host_stat.st_ctime); | |
d0f0baa2 KB |
1809 | |
1810 | if ((int) RETVAL < 0) | |
1811 | RETERR = sim_io_get_errno (simulator); | |
1812 | } | |
1813 | break; | |
1814 | #endif | |
1815 | ||
1816 | #ifdef TARGET_SYS_fstat | |
1817 | case TARGET_SYS_fstat: | |
1818 | /* fstat system call */ | |
1819 | { | |
1820 | struct stat host_stat; | |
1821 | reg_t buf; | |
1822 | ||
1823 | RETVAL = sim_io_fstat (simulator, PARM1, &host_stat); | |
1824 | ||
1825 | buf = PARM2; | |
1826 | ||
1827 | /* Just wild-assed guesses. */ | |
1828 | store_mem (buf, 2, host_stat.st_dev); | |
1829 | store_mem (buf + 2, 2, host_stat.st_ino); | |
1830 | store_mem (buf + 4, 4, host_stat.st_mode); | |
1831 | store_mem (buf + 8, 2, host_stat.st_nlink); | |
1832 | store_mem (buf + 10, 2, host_stat.st_uid); | |
1833 | store_mem (buf + 12, 2, host_stat.st_gid); | |
1834 | store_mem (buf + 14, 2, host_stat.st_rdev); | |
1835 | store_mem (buf + 16, 4, host_stat.st_size); | |
1836 | store_mem (buf + 20, 4, host_stat.st_atime); | |
1837 | store_mem (buf + 28, 4, host_stat.st_mtime); | |
1838 | store_mem (buf + 36, 4, host_stat.st_ctime); | |
1839 | ||
1840 | if ((int) RETVAL < 0) | |
1841 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1842 | } |
1843 | break; | |
1844 | #endif | |
d0f0baa2 KB |
1845 | |
1846 | #ifdef TARGET_SYS_rename | |
1847 | case TARGET_SYS_rename: | |
1848 | { | |
1849 | char *oldpath = fetch_str (simulator, PARM1); | |
1850 | char *newpath = fetch_str (simulator, PARM2); | |
1851 | RETVAL = sim_io_rename (simulator, oldpath, newpath); | |
1852 | free (oldpath); | |
1853 | free (newpath); | |
1854 | if ((int) RETVAL < 0) | |
1855 | RETERR = sim_io_get_errno (simulator); | |
1856 | } | |
1857 | break; | |
1858 | #endif | |
1859 | ||
1860 | #ifdef TARGET_SYS_unlink | |
1861 | case TARGET_SYS_unlink: | |
1862 | { | |
1863 | char *path = fetch_str (simulator, PARM1); | |
1864 | RETVAL = sim_io_unlink (simulator, path); | |
1865 | free (path); | |
1866 | if ((int) RETVAL < 0) | |
1867 | RETERR = sim_io_get_errno (simulator); | |
1868 | } | |
1869 | break; | |
c906108c SS |
1870 | #endif |
1871 | ||
1872 | #ifdef HAVE_CHOWN | |
1873 | #ifdef TARGET_SYS_chown | |
1874 | case TARGET_SYS_chown: | |
1875 | { | |
1876 | char *path = fetch_str (simulator, PARM1); | |
1877 | RETVAL = chown (path, PARM2, PARM3); | |
d79fe0d6 | 1878 | free (path); |
d0f0baa2 | 1879 | RETERR = errno; |
c906108c SS |
1880 | } |
1881 | break; | |
1882 | #endif | |
1883 | #endif | |
1884 | ||
1885 | #if HAVE_CHMOD | |
1886 | #ifdef TARGET_SYS_chmod | |
1887 | case TARGET_SYS_chmod: | |
1888 | { | |
1889 | char *path = fetch_str (simulator, PARM1); | |
1890 | RETVAL = chmod (path, PARM2); | |
d79fe0d6 | 1891 | free (path); |
d0f0baa2 | 1892 | RETERR = errno; |
c906108c SS |
1893 | } |
1894 | break; | |
1895 | #endif | |
1896 | #endif | |
1897 | ||
1898 | #ifdef TARGET_SYS_time | |
1899 | #if HAVE_TIME | |
1900 | case TARGET_SYS_time: | |
1901 | { | |
1902 | time_t now; | |
1903 | RETVAL = time (&now); | |
1904 | store_mem (PARM1, 4, now); | |
d0f0baa2 | 1905 | RETERR = errno; |
c906108c SS |
1906 | } |
1907 | break; | |
1908 | #endif | |
1909 | #endif | |
1910 | ||
1911 | #if !defined(__GO32__) && !defined(_WIN32) | |
1912 | #ifdef TARGET_SYS_times | |
1913 | case TARGET_SYS_times: | |
1914 | { | |
1915 | struct tms tms; | |
1916 | RETVAL = times (&tms); | |
1917 | store_mem (PARM1, 4, tms.tms_utime); | |
1918 | store_mem (PARM1 + 4, 4, tms.tms_stime); | |
1919 | store_mem (PARM1 + 8, 4, tms.tms_cutime); | |
1920 | store_mem (PARM1 + 12, 4, tms.tms_cstime); | |
d0f0baa2 | 1921 | reterr = errno; |
c906108c SS |
1922 | break; |
1923 | } | |
1924 | #endif | |
1925 | #endif | |
1926 | ||
1927 | #ifdef TARGET_SYS_gettimeofday | |
1928 | #if !defined(__GO32__) && !defined(_WIN32) | |
1929 | case TARGET_SYS_gettimeofday: | |
1930 | { | |
1931 | struct timeval t; | |
1932 | struct timezone tz; | |
1933 | RETVAL = gettimeofday (&t, &tz); | |
1934 | store_mem (PARM1, 4, t.tv_sec); | |
1935 | store_mem (PARM1 + 4, 4, t.tv_usec); | |
1936 | store_mem (PARM2, 4, tz.tz_minuteswest); | |
1937 | store_mem (PARM2 + 4, 4, tz.tz_dsttime); | |
d0f0baa2 | 1938 | RETERR = errno; |
c906108c SS |
1939 | break; |
1940 | } | |
1941 | #endif | |
1942 | #endif | |
1943 | ||
1944 | #ifdef TARGET_SYS_utime | |
1945 | #if HAVE_UTIME | |
1946 | case TARGET_SYS_utime: | |
1947 | { | |
1948 | /* Cast the second argument to void *, to avoid type mismatch | |
1949 | if a prototype is present. */ | |
1950 | sim_io_error (simulator, "Utime not supported"); | |
1951 | /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */ | |
1952 | } | |
1953 | break; | |
1954 | #endif | |
1955 | #endif | |
1956 | ||
1957 | default: | |
1958 | abort (); | |
1959 | } | |
c906108c SS |
1960 | errno = save_errno; |
1961 | ||
1962 | return 4; | |
1963 | } | |
1964 | else | |
1965 | { /* Trap 0 -> 30 */ | |
1966 | EIPC = PC + 4; | |
1967 | EIPSW = PSW; | |
1968 | /* Mask out EICC */ | |
1969 | ECR &= 0xffff0000; | |
1970 | ECR |= 0x40 + OP[0]; | |
1971 | /* Flag that we are now doing exception processing. */ | |
1972 | PSW |= PSW_EP | PSW_ID; | |
2e8162ce | 1973 | PC = (OP[0] < 0x10) ? 0x40 : 0x50; |
c906108c SS |
1974 | |
1975 | return 0; | |
1976 | } | |
1977 | } | |
1978 | ||
1979 | /* tst1 reg2, [reg1] */ | |
1980 | int | |
1981 | OP_E607E0 (void) | |
1982 | { | |
1983 | int temp; | |
1984 | ||
1985 | trace_input ("tst1", OP_BIT, 1); | |
1986 | ||
1987 | temp = load_mem (State.regs[ OP[0] ], 1); | |
1988 | ||
1989 | PSW &= ~PSW_Z; | |
30458d39 | 1990 | if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0) |
c906108c SS |
1991 | PSW |= PSW_Z; |
1992 | ||
1993 | trace_output (OP_BIT); | |
1994 | ||
1995 | return 4; | |
1996 | } | |
1997 | ||
1998 | /* mulu reg1, reg2, reg3 */ | |
1999 | int | |
2000 | OP_22207E0 (void) | |
2001 | { | |
2002 | trace_input ("mulu", OP_REG_REG_REG, 0); | |
2003 | ||
0da2b665 | 2004 | Multiply64 (0, State.regs[ OP[0] ]); |
c906108c SS |
2005 | |
2006 | trace_output (OP_REG_REG_REG); | |
2007 | ||
2008 | return 4; | |
2009 | } | |
2010 | ||
2011 | #define BIT_CHANGE_OP( name, binop ) \ | |
2012 | unsigned int bit; \ | |
2013 | unsigned int temp; \ | |
2014 | \ | |
2015 | trace_input (name, OP_BIT_CHANGE, 0); \ | |
2016 | \ | |
30458d39 | 2017 | bit = 1 << (State.regs[ OP[1] ] & 0x7); \ |
c906108c SS |
2018 | temp = load_mem (State.regs[ OP[0] ], 1); \ |
2019 | \ | |
2020 | PSW &= ~PSW_Z; \ | |
2021 | if ((temp & bit) == 0) \ | |
2022 | PSW |= PSW_Z; \ | |
2023 | temp binop bit; \ | |
2024 | \ | |
2025 | store_mem (State.regs[ OP[0] ], 1, temp); \ | |
2026 | \ | |
2027 | trace_output (OP_BIT_CHANGE); \ | |
2028 | \ | |
2029 | return 4; | |
2030 | ||
2031 | /* clr1 reg2, [reg1] */ | |
2032 | int | |
2033 | OP_E407E0 (void) | |
2034 | { | |
2035 | BIT_CHANGE_OP ("clr1", &= ~ ); | |
2036 | } | |
2037 | ||
2038 | /* not1 reg2, [reg1] */ | |
2039 | int | |
2040 | OP_E207E0 (void) | |
2041 | { | |
2042 | BIT_CHANGE_OP ("not1", ^= ); | |
2043 | } | |
2044 | ||
2045 | /* set1 */ | |
2046 | int | |
2047 | OP_E007E0 (void) | |
2048 | { | |
2049 | BIT_CHANGE_OP ("set1", |= ); | |
2050 | } | |
2051 | ||
2052 | /* sasf */ | |
2053 | int | |
2054 | OP_20007E0 (void) | |
2055 | { | |
2056 | trace_input ("sasf", OP_EX1, 0); | |
2057 | ||
2058 | State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]); | |
2059 | ||
2060 | trace_output (OP_EX1); | |
2061 | ||
2062 | return 4; | |
2063 | } | |
2064 | ||
2065 | /* This function is courtesy of Sugimoto at NEC, via Seow Tan | |
2066 | (Soew_Tan@el.nec.com) */ | |
2067 | void | |
2068 | divun | |
2069 | ( | |
2070 | unsigned int N, | |
2071 | unsigned long int als, | |
2072 | unsigned long int sfi, | |
2073 | unsigned32 /*unsigned long int*/ * quotient_ptr, | |
2074 | unsigned32 /*unsigned long int*/ * remainder_ptr, | |
0da2b665 | 2075 | int * overflow_ptr |
c906108c SS |
2076 | ) |
2077 | { | |
2078 | unsigned long ald = sfi >> (N - 1); | |
2079 | unsigned long alo = als; | |
2080 | unsigned int Q = 1; | |
2081 | unsigned int C; | |
2082 | unsigned int S = 0; | |
2083 | unsigned int i; | |
2084 | unsigned int R1 = 1; | |
2085 | unsigned int DBZ = (als == 0) ? 1 : 0; | |
2086 | unsigned long alt = Q ? ~als : als; | |
2087 | ||
2088 | /* 1st Loop */ | |
2089 | alo = ald + alt + Q; | |
2090 | C = (((alt >> 31) & (ald >> 31)) | |
2091 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2092 | C = C ^ Q; | |
2093 | Q = ~(C ^ S) & 1; | |
2094 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2095 | if ((S ^ (alo>>31)) && !C) | |
2096 | { | |
2097 | DBZ = 1; | |
2098 | } | |
2099 | S = alo >> 31; | |
2100 | sfi = (sfi << (32-N+1)) | Q; | |
2101 | ald = (alo << 1) | (sfi >> 31); | |
2102 | ||
2103 | /* 2nd - N-1th Loop */ | |
2104 | for (i = 2; i < N; i++) | |
2105 | { | |
2106 | alt = Q ? ~als : als; | |
2107 | alo = ald + alt + Q; | |
2108 | C = (((alt >> 31) & (ald >> 31)) | |
2109 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2110 | C = C ^ Q; | |
2111 | Q = ~(C ^ S) & 1; | |
2112 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2113 | if ((S ^ (alo>>31)) && !C && !DBZ) | |
2114 | { | |
2115 | DBZ = 1; | |
2116 | } | |
2117 | S = alo >> 31; | |
2118 | sfi = (sfi << 1) | Q; | |
2119 | ald = (alo << 1) | (sfi >> 31); | |
2120 | } | |
2121 | ||
2122 | /* Nth Loop */ | |
2123 | alt = Q ? ~als : als; | |
2124 | alo = ald + alt + Q; | |
2125 | C = (((alt >> 31) & (ald >> 31)) | |
2126 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2127 | C = C ^ Q; | |
2128 | Q = ~(C ^ S) & 1; | |
2129 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2130 | if ((S ^ (alo>>31)) && !C) | |
2131 | { | |
2132 | DBZ = 1; | |
2133 | } | |
2134 | ||
2135 | * quotient_ptr = (sfi << 1) | Q; | |
2136 | * remainder_ptr = Q ? alo : (alo + als); | |
2137 | * overflow_ptr = DBZ | R1; | |
2138 | } | |
2139 | ||
2140 | /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */ | |
2141 | void | |
2142 | divn | |
2143 | ( | |
2144 | unsigned int N, | |
2145 | unsigned long int als, | |
2146 | unsigned long int sfi, | |
2147 | signed32 /*signed long int*/ * quotient_ptr, | |
2148 | signed32 /*signed long int*/ * remainder_ptr, | |
0da2b665 | 2149 | int * overflow_ptr |
c906108c SS |
2150 | ) |
2151 | { | |
2152 | unsigned long ald = (signed long) sfi >> (N - 1); | |
2153 | unsigned long alo = als; | |
2154 | unsigned int SS = als >> 31; | |
2155 | unsigned int SD = sfi >> 31; | |
2156 | unsigned int R1 = 1; | |
2157 | unsigned int OV; | |
2158 | unsigned int DBZ = als == 0 ? 1 : 0; | |
2159 | unsigned int Q = ~(SS ^ SD) & 1; | |
2160 | unsigned int C; | |
2161 | unsigned int S; | |
2162 | unsigned int i; | |
2163 | unsigned long alt = Q ? ~als : als; | |
2164 | ||
2165 | ||
2166 | /* 1st Loop */ | |
2167 | ||
2168 | alo = ald + alt + Q; | |
2169 | C = (((alt >> 31) & (ald >> 31)) | |
2170 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2171 | Q = C ^ SS; | |
2172 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2173 | S = alo >> 31; | |
2174 | sfi = (sfi << (32-N+1)) | Q; | |
2175 | ald = (alo << 1) | (sfi >> 31); | |
2176 | if ((alo >> 31) ^ (ald >> 31)) | |
2177 | { | |
2178 | DBZ = 1; | |
2179 | } | |
2180 | ||
2181 | /* 2nd - N-1th Loop */ | |
2182 | ||
2183 | for (i = 2; i < N; i++) | |
2184 | { | |
2185 | alt = Q ? ~als : als; | |
2186 | alo = ald + alt + Q; | |
2187 | C = (((alt >> 31) & (ald >> 31)) | |
2188 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2189 | Q = C ^ SS; | |
2190 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2191 | S = alo >> 31; | |
2192 | sfi = (sfi << 1) | Q; | |
2193 | ald = (alo << 1) | (sfi >> 31); | |
2194 | if ((alo >> 31) ^ (ald >> 31)) | |
2195 | { | |
2196 | DBZ = 1; | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | /* Nth Loop */ | |
2201 | alt = Q ? ~als : als; | |
2202 | alo = ald + alt + Q; | |
2203 | C = (((alt >> 31) & (ald >> 31)) | |
2204 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2205 | Q = C ^ SS; | |
2206 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2207 | sfi = (sfi << (32-N+1)); | |
2208 | ald = alo; | |
2209 | ||
2210 | /* End */ | |
2211 | if (alo != 0) | |
2212 | { | |
2213 | alt = Q ? ~als : als; | |
2214 | alo = ald + alt + Q; | |
2215 | } | |
2216 | R1 = R1 & ((~alo >> 31) ^ SD); | |
2217 | if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald; | |
2218 | if (N != 32) | |
2219 | ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q; | |
2220 | else | |
2221 | ald = sfi = sfi | Q; | |
2222 | ||
2223 | OV = DBZ | ((alo == 0) ? 0 : R1); | |
2224 | ||
2225 | * remainder_ptr = alo; | |
2226 | ||
2227 | /* Adj */ | |
2228 | if (((alo != 0) && ((SS ^ SD) ^ R1)) | |
2229 | || ((alo == 0) && (SS ^ R1))) | |
2230 | alo = ald + 1; | |
2231 | else | |
2232 | alo = ald; | |
2233 | ||
2234 | OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31)); | |
2235 | ||
2236 | * quotient_ptr = alo; | |
2237 | * overflow_ptr = OV; | |
2238 | } | |
2239 | ||
2240 | /* sdivun imm5, reg1, reg2, reg3 */ | |
2241 | int | |
2242 | OP_1C207E0 (void) | |
2243 | { | |
2244 | unsigned32 /*unsigned long int*/ quotient; | |
2245 | unsigned32 /*unsigned long int*/ remainder; | |
2246 | unsigned long int divide_by; | |
2247 | unsigned long int divide_this; | |
0da2b665 | 2248 | int overflow = 0; |
c906108c SS |
2249 | unsigned int imm5; |
2250 | ||
2251 | trace_input ("sdivun", OP_IMM_REG_REG_REG, 0); | |
2252 | ||
2253 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2254 | ||
2255 | divide_by = State.regs[ OP[0] ]; | |
2256 | divide_this = State.regs[ OP[1] ] << imm5; | |
2257 | ||
2258 | divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2259 | ||
2260 | State.regs[ OP[1] ] = quotient; | |
2261 | State.regs[ OP[2] >> 11 ] = remainder; | |
2262 | ||
2263 | /* Set condition codes. */ | |
2264 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2265 | ||
2266 | if (overflow) PSW |= PSW_OV; | |
2267 | if (quotient == 0) PSW |= PSW_Z; | |
2268 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2269 | ||
2270 | trace_output (OP_IMM_REG_REG_REG); | |
2271 | ||
2272 | return 4; | |
2273 | } | |
2274 | ||
2275 | /* sdivn imm5, reg1, reg2, reg3 */ | |
2276 | int | |
2277 | OP_1C007E0 (void) | |
2278 | { | |
2279 | signed32 /*signed long int*/ quotient; | |
2280 | signed32 /*signed long int*/ remainder; | |
2281 | signed long int divide_by; | |
2282 | signed long int divide_this; | |
0da2b665 | 2283 | int overflow = 0; |
c906108c SS |
2284 | unsigned int imm5; |
2285 | ||
2286 | trace_input ("sdivn", OP_IMM_REG_REG_REG, 0); | |
2287 | ||
2288 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2289 | ||
98e460c3 DD |
2290 | divide_by = (signed32) State.regs[ OP[0] ]; |
2291 | divide_this = (signed32) (State.regs[ OP[1] ] << imm5); | |
c906108c SS |
2292 | |
2293 | divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2294 | ||
2295 | State.regs[ OP[1] ] = quotient; | |
2296 | State.regs[ OP[2] >> 11 ] = remainder; | |
2297 | ||
2298 | /* Set condition codes. */ | |
2299 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2300 | ||
2301 | if (overflow) PSW |= PSW_OV; | |
2302 | if (quotient == 0) PSW |= PSW_Z; | |
2303 | if (quotient < 0) PSW |= PSW_S; | |
2304 | ||
2305 | trace_output (OP_IMM_REG_REG_REG); | |
2306 | ||
2307 | return 4; | |
2308 | } | |
2309 | ||
2310 | /* sdivhun imm5, reg1, reg2, reg3 */ | |
2311 | int | |
2312 | OP_18207E0 (void) | |
2313 | { | |
2314 | unsigned32 /*unsigned long int*/ quotient; | |
2315 | unsigned32 /*unsigned long int*/ remainder; | |
2316 | unsigned long int divide_by; | |
2317 | unsigned long int divide_this; | |
0da2b665 | 2318 | int overflow = 0; |
c906108c SS |
2319 | unsigned int imm5; |
2320 | ||
2321 | trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0); | |
2322 | ||
2323 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2324 | ||
2325 | divide_by = State.regs[ OP[0] ] & 0xffff; | |
2326 | divide_this = State.regs[ OP[1] ] << imm5; | |
2327 | ||
2328 | divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2329 | ||
2330 | State.regs[ OP[1] ] = quotient; | |
2331 | State.regs[ OP[2] >> 11 ] = remainder; | |
2332 | ||
2333 | /* Set condition codes. */ | |
2334 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2335 | ||
2336 | if (overflow) PSW |= PSW_OV; | |
2337 | if (quotient == 0) PSW |= PSW_Z; | |
2338 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2339 | ||
2340 | trace_output (OP_IMM_REG_REG_REG); | |
2341 | ||
2342 | return 4; | |
2343 | } | |
2344 | ||
2345 | /* sdivhn imm5, reg1, reg2, reg3 */ | |
2346 | int | |
2347 | OP_18007E0 (void) | |
2348 | { | |
2349 | signed32 /*signed long int*/ quotient; | |
2350 | signed32 /*signed long int*/ remainder; | |
2351 | signed long int divide_by; | |
2352 | signed long int divide_this; | |
0da2b665 | 2353 | int overflow = 0; |
c906108c SS |
2354 | unsigned int imm5; |
2355 | ||
2356 | trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0); | |
2357 | ||
2358 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2359 | ||
2360 | divide_by = EXTEND16 (State.regs[ OP[0] ]); | |
98e460c3 | 2361 | divide_this = (signed32) (State.regs[ OP[1] ] << imm5); |
c906108c SS |
2362 | |
2363 | divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2364 | ||
2365 | State.regs[ OP[1] ] = quotient; | |
2366 | State.regs[ OP[2] >> 11 ] = remainder; | |
2367 | ||
2368 | /* Set condition codes. */ | |
2369 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2370 | ||
2371 | if (overflow) PSW |= PSW_OV; | |
2372 | if (quotient == 0) PSW |= PSW_Z; | |
2373 | if (quotient < 0) PSW |= PSW_S; | |
2374 | ||
2375 | trace_output (OP_IMM_REG_REG_REG); | |
2376 | ||
2377 | return 4; | |
2378 | } | |
2379 | ||
2380 | /* divu reg1, reg2, reg3 */ | |
2381 | int | |
2382 | OP_2C207E0 (void) | |
2383 | { | |
2384 | unsigned long int quotient; | |
2385 | unsigned long int remainder; | |
2386 | unsigned long int divide_by; | |
2387 | unsigned long int divide_this; | |
0da2b665 | 2388 | int overflow = 0; |
c906108c SS |
2389 | |
2390 | trace_input ("divu", OP_REG_REG_REG, 0); | |
2391 | ||
2392 | /* Compute the result. */ | |
2393 | ||
2394 | divide_by = State.regs[ OP[0] ]; | |
2395 | divide_this = State.regs[ OP[1] ]; | |
2396 | ||
2397 | if (divide_by == 0) | |
2398 | { | |
c5fbc25b | 2399 | PSW |= PSW_OV; |
c906108c | 2400 | } |
c5fbc25b DD |
2401 | else |
2402 | { | |
2403 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; | |
2404 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2405 | |
c5fbc25b DD |
2406 | /* Set condition codes. */ |
2407 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2408 | |
c5fbc25b DD |
2409 | if (overflow) PSW |= PSW_OV; |
2410 | if (quotient == 0) PSW |= PSW_Z; | |
2411 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2412 | } | |
c906108c SS |
2413 | |
2414 | trace_output (OP_REG_REG_REG); | |
2415 | ||
2416 | return 4; | |
2417 | } | |
2418 | ||
2419 | /* div reg1, reg2, reg3 */ | |
2420 | int | |
2421 | OP_2C007E0 (void) | |
2422 | { | |
2423 | signed long int quotient; | |
2424 | signed long int remainder; | |
2425 | signed long int divide_by; | |
2426 | signed long int divide_this; | |
c906108c SS |
2427 | |
2428 | trace_input ("div", OP_REG_REG_REG, 0); | |
2429 | ||
2430 | /* Compute the result. */ | |
2431 | ||
98e460c3 | 2432 | divide_by = (signed32) State.regs[ OP[0] ]; |
c906108c SS |
2433 | divide_this = State.regs[ OP[1] ]; |
2434 | ||
c5fbc25b | 2435 | if (divide_by == 0) |
c906108c | 2436 | { |
c5fbc25b | 2437 | PSW |= PSW_OV; |
c906108c | 2438 | } |
98e460c3 | 2439 | else if (divide_by == -1 && divide_this == (1L << 31)) |
c5fbc25b DD |
2440 | { |
2441 | PSW &= ~PSW_Z; | |
2442 | PSW |= PSW_OV | PSW_S; | |
2443 | State.regs[ OP[1] ] = (1 << 31); | |
2444 | State.regs[ OP[2] >> 11 ] = 0; | |
2445 | } | |
2446 | else | |
2447 | { | |
98e460c3 | 2448 | divide_this = (signed32) divide_this; |
c5fbc25b DD |
2449 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; |
2450 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
98e460c3 | 2451 | |
c5fbc25b DD |
2452 | /* Set condition codes. */ |
2453 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2454 | |
c5fbc25b DD |
2455 | if (quotient == 0) PSW |= PSW_Z; |
2456 | if (quotient < 0) PSW |= PSW_S; | |
2457 | } | |
c906108c SS |
2458 | |
2459 | trace_output (OP_REG_REG_REG); | |
2460 | ||
2461 | return 4; | |
2462 | } | |
2463 | ||
2464 | /* divhu reg1, reg2, reg3 */ | |
2465 | int | |
2466 | OP_28207E0 (void) | |
2467 | { | |
2468 | unsigned long int quotient; | |
2469 | unsigned long int remainder; | |
2470 | unsigned long int divide_by; | |
2471 | unsigned long int divide_this; | |
0da2b665 | 2472 | int overflow = 0; |
c906108c SS |
2473 | |
2474 | trace_input ("divhu", OP_REG_REG_REG, 0); | |
2475 | ||
2476 | /* Compute the result. */ | |
2477 | ||
2478 | divide_by = State.regs[ OP[0] ] & 0xffff; | |
2479 | divide_this = State.regs[ OP[1] ]; | |
2480 | ||
2481 | if (divide_by == 0) | |
2482 | { | |
c5fbc25b | 2483 | PSW |= PSW_OV; |
c906108c | 2484 | } |
c5fbc25b DD |
2485 | else |
2486 | { | |
2487 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; | |
2488 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2489 | |
c5fbc25b DD |
2490 | /* Set condition codes. */ |
2491 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2492 | |
c5fbc25b DD |
2493 | if (overflow) PSW |= PSW_OV; |
2494 | if (quotient == 0) PSW |= PSW_Z; | |
2495 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2496 | } | |
c906108c SS |
2497 | |
2498 | trace_output (OP_REG_REG_REG); | |
2499 | ||
2500 | return 4; | |
2501 | } | |
2502 | ||
2503 | /* divh reg1, reg2, reg3 */ | |
2504 | int | |
2505 | OP_28007E0 (void) | |
2506 | { | |
2507 | signed long int quotient; | |
2508 | signed long int remainder; | |
2509 | signed long int divide_by; | |
2510 | signed long int divide_this; | |
0da2b665 | 2511 | int overflow = 0; |
c906108c SS |
2512 | |
2513 | trace_input ("divh", OP_REG_REG_REG, 0); | |
2514 | ||
2515 | /* Compute the result. */ | |
2516 | ||
c5fbc25b DD |
2517 | divide_by = EXTEND16 (State.regs[ OP[0] ]); |
2518 | divide_this = State.regs[ OP[1] ]; | |
c906108c | 2519 | |
c5fbc25b DD |
2520 | if (divide_by == 0) |
2521 | { | |
2522 | PSW |= PSW_OV; | |
2523 | } | |
98e460c3 | 2524 | else if (divide_by == -1 && divide_this == (1L << 31)) |
c906108c | 2525 | { |
c5fbc25b DD |
2526 | PSW &= ~PSW_Z; |
2527 | PSW |= PSW_OV | PSW_S; | |
2528 | State.regs[ OP[1] ] = (1 << 31); | |
2529 | State.regs[ OP[2] >> 11 ] = 0; | |
c906108c | 2530 | } |
c5fbc25b DD |
2531 | else |
2532 | { | |
98e460c3 | 2533 | divide_this = (signed32) divide_this; |
c5fbc25b DD |
2534 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; |
2535 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2536 | |
c5fbc25b DD |
2537 | /* Set condition codes. */ |
2538 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2539 | |
c5fbc25b DD |
2540 | if (quotient == 0) PSW |= PSW_Z; |
2541 | if (quotient < 0) PSW |= PSW_S; | |
2542 | } | |
c906108c SS |
2543 | |
2544 | trace_output (OP_REG_REG_REG); | |
2545 | ||
2546 | return 4; | |
2547 | } | |
2548 | ||
2549 | /* mulu imm9, reg2, reg3 */ | |
2550 | int | |
2551 | OP_24207E0 (void) | |
2552 | { | |
2553 | trace_input ("mulu", OP_IMM_REG_REG, 0); | |
2554 | ||
0da2b665 | 2555 | Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); |
c906108c SS |
2556 | |
2557 | trace_output (OP_IMM_REG_REG); | |
2558 | ||
2559 | return 4; | |
2560 | } | |
2561 | ||
2562 | /* mul imm9, reg2, reg3 */ | |
2563 | int | |
2564 | OP_24007E0 (void) | |
2565 | { | |
2566 | trace_input ("mul", OP_IMM_REG_REG, 0); | |
2567 | ||
0da2b665 | 2568 | Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0))); |
c906108c SS |
2569 | |
2570 | trace_output (OP_IMM_REG_REG); | |
2571 | ||
2572 | return 4; | |
2573 | } | |
2574 | ||
2575 | /* ld.hu */ | |
2576 | int | |
2577 | OP_107E0 (void) | |
2578 | { | |
2579 | int adr; | |
2580 | ||
2581 | trace_input ("ld.hu", OP_LOAD32, 2); | |
2582 | ||
2583 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
2584 | adr &= ~0x1; | |
2585 | ||
2586 | State.regs[ OP[1] ] = load_mem (adr, 2); | |
2587 | ||
2588 | trace_output (OP_LOAD32); | |
2589 | ||
2590 | return 4; | |
2591 | } | |
2592 | ||
2593 | ||
2594 | /* ld.bu */ | |
2595 | int | |
2596 | OP_10780 (void) | |
2597 | { | |
2598 | int adr; | |
2599 | ||
2600 | trace_input ("ld.bu", OP_LOAD32, 1); | |
2601 | ||
2602 | adr = (State.regs[ OP[0] ] | |
2603 | + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1))); | |
2604 | ||
2605 | State.regs[ OP[1] ] = load_mem (adr, 1); | |
2606 | ||
2607 | trace_output (OP_LOAD32); | |
2608 | ||
2609 | return 4; | |
2610 | } | |
2611 | ||
2612 | /* prepare list12, imm5, imm32 */ | |
2613 | int | |
2614 | OP_1B0780 (void) | |
2615 | { | |
2616 | int i; | |
2617 | ||
2618 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2619 | ||
2620 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2621 | for (i = 0; i < 12; i++) | |
2622 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2623 | { | |
2624 | SP -= 4; | |
2625 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2626 | } | |
2627 | ||
2628 | SP -= (OP[3] & 0x3e) << 1; | |
2629 | ||
2630 | EP = load_mem (PC + 4, 4); | |
2631 | ||
2632 | trace_output (OP_PUSHPOP1); | |
2633 | ||
2634 | return 8; | |
2635 | } | |
2636 | ||
2637 | /* prepare list12, imm5, imm16-32 */ | |
2638 | int | |
2639 | OP_130780 (void) | |
2640 | { | |
2641 | int i; | |
2642 | ||
2643 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2644 | ||
2645 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2646 | for (i = 0; i < 12; i++) | |
2647 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2648 | { | |
2649 | SP -= 4; | |
2650 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2651 | } | |
2652 | ||
2653 | SP -= (OP[3] & 0x3e) << 1; | |
2654 | ||
2655 | EP = load_mem (PC + 4, 2) << 16; | |
2656 | ||
2657 | trace_output (OP_PUSHPOP1); | |
2658 | ||
2659 | return 6; | |
2660 | } | |
2661 | ||
2662 | /* prepare list12, imm5, imm16 */ | |
2663 | int | |
2664 | OP_B0780 (void) | |
2665 | { | |
2666 | int i; | |
2667 | ||
2668 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2669 | ||
2670 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2671 | for (i = 0; i < 12; i++) | |
2672 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2673 | { | |
2674 | SP -= 4; | |
2675 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2676 | } | |
2677 | ||
2678 | SP -= (OP[3] & 0x3e) << 1; | |
2679 | ||
2680 | EP = EXTEND16 (load_mem (PC + 4, 2)); | |
2681 | ||
2682 | trace_output (OP_PUSHPOP1); | |
2683 | ||
2684 | return 6; | |
2685 | } | |
2686 | ||
2687 | /* prepare list12, imm5, sp */ | |
2688 | int | |
2689 | OP_30780 (void) | |
2690 | { | |
2691 | int i; | |
2692 | ||
2693 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2694 | ||
2695 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2696 | for (i = 0; i < 12; i++) | |
2697 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2698 | { | |
2699 | SP -= 4; | |
2700 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2701 | } | |
2702 | ||
2703 | SP -= (OP[3] & 0x3e) << 1; | |
2704 | ||
2705 | EP = SP; | |
2706 | ||
2707 | trace_output (OP_PUSHPOP1); | |
2708 | ||
2709 | return 4; | |
2710 | } | |
2711 | ||
2712 | /* mul reg1, reg2, reg3 */ | |
2713 | int | |
2714 | OP_22007E0 (void) | |
2715 | { | |
2716 | trace_input ("mul", OP_REG_REG_REG, 0); | |
2717 | ||
0da2b665 | 2718 | Multiply64 (1, State.regs[ OP[0] ]); |
c906108c SS |
2719 | |
2720 | trace_output (OP_REG_REG_REG); | |
2721 | ||
2722 | return 4; | |
2723 | } | |
2724 | ||
2725 | /* popmh list18 */ | |
2726 | int | |
2727 | OP_307F0 (void) | |
2728 | { | |
2729 | int i; | |
2730 | ||
2731 | trace_input ("popmh", OP_PUSHPOP2, 0); | |
2732 | ||
2733 | if (OP[3] & (1 << 19)) | |
2734 | { | |
2735 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2736 | { | |
2737 | FEPSW = load_mem ( SP & ~ 3, 4); | |
2738 | FEPC = load_mem ((SP + 4) & ~ 3, 4); | |
2739 | } | |
2740 | else | |
2741 | { | |
2742 | EIPSW = load_mem ( SP & ~ 3, 4); | |
2743 | EIPC = load_mem ((SP + 4) & ~ 3, 4); | |
2744 | } | |
2745 | ||
2746 | SP += 8; | |
2747 | } | |
2748 | ||
2749 | /* Load the registers with lower number registers being retrieved from higher addresses. */ | |
2750 | for (i = 16; i--;) | |
2751 | if ((OP[3] & (1 << type2_regs[ i ]))) | |
2752 | { | |
2753 | State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4); | |
2754 | SP += 4; | |
2755 | } | |
2756 | ||
2757 | trace_output (OP_PUSHPOP2); | |
2758 | ||
2759 | return 4; | |
2760 | } | |
2761 | ||
2762 | /* popml lsit18 */ | |
2763 | int | |
2764 | OP_107F0 (void) | |
2765 | { | |
2766 | int i; | |
2767 | ||
2768 | trace_input ("popml", OP_PUSHPOP3, 0); | |
2769 | ||
2770 | if (OP[3] & (1 << 19)) | |
2771 | { | |
2772 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2773 | { | |
2774 | FEPSW = load_mem ( SP & ~ 3, 4); | |
2775 | FEPC = load_mem ((SP + 4) & ~ 3, 4); | |
2776 | } | |
2777 | else | |
2778 | { | |
2779 | EIPSW = load_mem ( SP & ~ 3, 4); | |
2780 | EIPC = load_mem ((SP + 4) & ~ 3, 4); | |
2781 | } | |
2782 | ||
2783 | SP += 8; | |
2784 | } | |
2785 | ||
2786 | if (OP[3] & (1 << 3)) | |
2787 | { | |
2788 | PSW = load_mem (SP & ~ 3, 4); | |
2789 | SP += 4; | |
2790 | } | |
2791 | ||
2792 | /* Load the registers with lower number registers being retrieved from higher addresses. */ | |
2793 | for (i = 15; i--;) | |
2794 | if ((OP[3] & (1 << type3_regs[ i ]))) | |
2795 | { | |
2796 | State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4); | |
2797 | SP += 4; | |
2798 | } | |
2799 | ||
2800 | trace_output (OP_PUSHPOP2); | |
2801 | ||
2802 | return 4; | |
2803 | } | |
2804 | ||
2805 | /* pushmh list18 */ | |
2806 | int | |
2807 | OP_307E0 (void) | |
2808 | { | |
2809 | int i; | |
2810 | ||
2811 | trace_input ("pushmh", OP_PUSHPOP2, 0); | |
2812 | ||
2813 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2814 | for (i = 0; i < 16; i++) | |
2815 | if ((OP[3] & (1 << type2_regs[ i ]))) | |
2816 | { | |
2817 | SP -= 4; | |
2818 | store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]); | |
2819 | } | |
2820 | ||
2821 | if (OP[3] & (1 << 19)) | |
2822 | { | |
2823 | SP -= 8; | |
2824 | ||
2825 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2826 | { | |
2827 | store_mem ((SP + 4) & ~ 3, 4, FEPC); | |
2828 | store_mem ( SP & ~ 3, 4, FEPSW); | |
2829 | } | |
2830 | else | |
2831 | { | |
2832 | store_mem ((SP + 4) & ~ 3, 4, EIPC); | |
2833 | store_mem ( SP & ~ 3, 4, EIPSW); | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | trace_output (OP_PUSHPOP2); | |
2838 | ||
2839 | return 4; | |
2840 | } | |
2841 | ||
2aaed979 KB |
2842 | /* V850E2R FPU functions */ |
2843 | /* | |
2844 | sim_fpu_status_invalid_snan = 1, -V--- (sim spec.) | |
2845 | sim_fpu_status_invalid_qnan = 2, ----- (sim spec.) | |
2846 | sim_fpu_status_invalid_isi = 4, (inf - inf) -V--- | |
2847 | sim_fpu_status_invalid_idi = 8, (inf / inf) -V--- | |
2848 | sim_fpu_status_invalid_zdz = 16, (0 / 0) -V--- | |
2849 | sim_fpu_status_invalid_imz = 32, (inf * 0) -V--- | |
2850 | sim_fpu_status_invalid_cvi = 64, convert to integer -V--- | |
2851 | sim_fpu_status_invalid_div0 = 128, (X / 0) --Z-- | |
2852 | sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.) | |
2853 | sim_fpu_status_invalid_sqrt = 512, -V--- | |
2854 | sim_fpu_status_rounded = 1024, I---- | |
2855 | sim_fpu_status_inexact = 2048, I---- (sim spec.) | |
2856 | sim_fpu_status_overflow = 4096, I--O- | |
2857 | sim_fpu_status_underflow = 8192, I---U | |
2858 | sim_fpu_status_denorm = 16384, ----U (sim spec.) | |
2859 | */ | |
2860 | ||
2861 | void update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p) | |
2862 | { | |
2863 | unsigned int fpsr = FPSR & mask; | |
2864 | ||
2865 | unsigned int flags = 0; | |
2866 | ||
2867 | if (fpsr & FPSR_XEI | |
2868 | && ((status & (sim_fpu_status_rounded | |
2869 | | sim_fpu_status_overflow | |
2870 | | sim_fpu_status_inexact)) | |
2871 | || (status & sim_fpu_status_underflow | |
2872 | && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0 | |
2873 | && fpsr & FPSR_FS))) | |
2874 | { | |
2875 | flags |= FPSR_XCI | FPSR_XPI; | |
2876 | } | |
2877 | ||
2878 | if (fpsr & FPSR_XEV | |
2879 | && (status & (sim_fpu_status_invalid_isi | |
2880 | | sim_fpu_status_invalid_imz | |
2881 | | sim_fpu_status_invalid_zdz | |
2882 | | sim_fpu_status_invalid_idi | |
2883 | | sim_fpu_status_invalid_cvi | |
2884 | | sim_fpu_status_invalid_sqrt | |
2885 | | sim_fpu_status_invalid_snan))) | |
2886 | { | |
2887 | flags |= FPSR_XCV | FPSR_XPV; | |
2888 | } | |
2889 | ||
2890 | if (fpsr & FPSR_XEZ | |
2891 | && (status & sim_fpu_status_invalid_div0)) | |
2892 | { | |
2893 | flags |= FPSR_XCV | FPSR_XPV; | |
2894 | } | |
2895 | ||
2896 | if (fpsr & FPSR_XEO | |
2897 | && (status & sim_fpu_status_overflow)) | |
2898 | { | |
2899 | flags |= FPSR_XCO | FPSR_XPO; | |
2900 | } | |
2901 | ||
2902 | if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0) | |
2903 | && (status & (sim_fpu_status_underflow | |
2904 | | sim_fpu_status_denorm))) | |
2905 | { | |
2906 | flags |= FPSR_XCU | FPSR_XPU; | |
2907 | } | |
2908 | ||
2909 | if (flags) | |
2910 | { | |
2911 | FPSR &= ~FPSR_XC; | |
2912 | FPSR |= flags; | |
2913 | ||
2914 | SignalExceptionFPE(sd, double_op_p); | |
2915 | } | |
2916 | } | |
2917 | ||
2918 | /* | |
2919 | exception | |
2920 | */ | |
2921 | ||
2922 | void SignalException(SIM_DESC sd) | |
2923 | { | |
2924 | if (MPM & MPM_AUE) | |
2925 | { | |
2926 | PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP); | |
2927 | } | |
2928 | } | |
2929 | ||
2930 | void SignalExceptionFPE(SIM_DESC sd, unsigned int double_op_p) | |
2931 | { | |
2932 | if (((PSW & (PSW_NP|PSW_ID)) == 0) | |
2933 | || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))) | |
2934 | { | |
2935 | EIPC = PC; | |
2936 | EIPSW = PSW; | |
2937 | EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)) | |
2938 | ? 0x71 : 0x72; | |
2939 | PSW |= (PSW_EP | PSW_ID); | |
2940 | PC = 0x70; | |
2941 | ||
2942 | SignalException(sd); | |
2943 | } | |
2944 | } | |
2945 | ||
2946 | ||
2947 | void check_invalid_snan(SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p) | |
2948 | { | |
2949 | if ((FPSR & FPSR_XEI) | |
2950 | && (status & sim_fpu_status_invalid_snan)) | |
2951 | { | |
2952 | FPSR &= ~FPSR_XC; | |
2953 | FPSR |= FPSR_XCV; | |
2954 | FPSR |= FPSR_XPV; | |
2955 | SignalExceptionFPE(sd, double_op_p); | |
2956 | } | |
2957 | } | |
2958 | ||
2959 | int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p) | |
2960 | { | |
2961 | int result = -1; | |
2962 | ||
2963 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2964 | { | |
2965 | if (cmp & 0x8) | |
2966 | { | |
2967 | if (FPSR & FPSR_XEV) | |
2968 | { | |
2969 | FPSR |= FPSR_XCV | FPSR_XPV; | |
2970 | SignalExceptionFPE(sd, double_op_p); | |
2971 | } | |
2972 | } | |
2973 | ||
2974 | switch (cmp) | |
2975 | { | |
2976 | case FPU_CMP_F: | |
2977 | result = 0; | |
2978 | break; | |
2979 | case FPU_CMP_UN: | |
2980 | result = 1; | |
2981 | break; | |
2982 | case FPU_CMP_EQ: | |
2983 | result = 0; | |
2984 | break; | |
2985 | case FPU_CMP_UEQ: | |
2986 | result = 1; | |
2987 | break; | |
2988 | case FPU_CMP_OLT: | |
2989 | result = 0; | |
2990 | break; | |
2991 | case FPU_CMP_ULT: | |
2992 | result = 1; | |
2993 | break; | |
2994 | case FPU_CMP_OLE: | |
2995 | result = 0; | |
2996 | break; | |
2997 | case FPU_CMP_ULE: | |
2998 | result = 1; | |
2999 | break; | |
3000 | case FPU_CMP_SF: | |
3001 | result = 0; | |
3002 | break; | |
3003 | case FPU_CMP_NGLE: | |
3004 | result = 1; | |
3005 | break; | |
3006 | case FPU_CMP_SEQ: | |
3007 | result = 0; | |
3008 | break; | |
3009 | case FPU_CMP_NGL: | |
3010 | result = 1; | |
3011 | break; | |
3012 | case FPU_CMP_LT: | |
3013 | result = 0; | |
3014 | break; | |
3015 | case FPU_CMP_NGE: | |
3016 | result = 1; | |
3017 | break; | |
3018 | case FPU_CMP_LE: | |
3019 | result = 0; | |
3020 | break; | |
3021 | case FPU_CMP_NGT: | |
3022 | result = 1; | |
3023 | break; | |
3024 | default: | |
3025 | abort(); | |
3026 | } | |
3027 | } | |
3028 | else if (sim_fpu_is_infinity(&wop1) && sim_fpu_is_infinity(&wop2) | |
3029 | && sim_fpu_sign(&wop1) == sim_fpu_sign(&wop2)) | |
3030 | { | |
3031 | switch (cmp) | |
3032 | { | |
3033 | case FPU_CMP_F: | |
3034 | result = 0; | |
3035 | break; | |
3036 | case FPU_CMP_UN: | |
3037 | result = 0; | |
3038 | break; | |
3039 | case FPU_CMP_EQ: | |
3040 | result = 1; | |
3041 | break; | |
3042 | case FPU_CMP_UEQ: | |
3043 | result = 1; | |
3044 | break; | |
3045 | case FPU_CMP_OLT: | |
3046 | result = 0; | |
3047 | break; | |
3048 | case FPU_CMP_ULT: | |
3049 | result = 0; | |
3050 | break; | |
3051 | case FPU_CMP_OLE: | |
3052 | result = 1; | |
3053 | break; | |
3054 | case FPU_CMP_ULE: | |
3055 | result = 1; | |
3056 | break; | |
3057 | case FPU_CMP_SF: | |
3058 | result = 0; | |
3059 | break; | |
3060 | case FPU_CMP_NGLE: | |
3061 | result = 0; | |
3062 | break; | |
3063 | case FPU_CMP_SEQ: | |
3064 | result = 1; | |
3065 | break; | |
3066 | case FPU_CMP_NGL: | |
3067 | result = 1; | |
3068 | break; | |
3069 | case FPU_CMP_LT: | |
3070 | result = 0; | |
3071 | break; | |
3072 | case FPU_CMP_NGE: | |
3073 | result = 0; | |
3074 | break; | |
3075 | case FPU_CMP_LE: | |
3076 | result = 1; | |
3077 | break; | |
3078 | case FPU_CMP_NGT: | |
3079 | result = 1; | |
3080 | break; | |
3081 | default: | |
3082 | abort(); | |
3083 | } | |
3084 | } | |
3085 | else | |
3086 | { | |
3087 | int gt = 0,lt = 0,eq = 0, status; | |
3088 | ||
3089 | status = sim_fpu_cmp( &wop1, &wop2 ); | |
3090 | ||
3091 | switch (status) { | |
3092 | case SIM_FPU_IS_SNAN: | |
3093 | case SIM_FPU_IS_QNAN: | |
3094 | abort(); | |
3095 | break; | |
3096 | ||
3097 | case SIM_FPU_IS_NINF: | |
3098 | lt = 1; | |
3099 | break; | |
3100 | case SIM_FPU_IS_PINF: | |
3101 | gt = 1; | |
3102 | break; | |
3103 | case SIM_FPU_IS_NNUMBER: | |
3104 | lt = 1; | |
3105 | break; | |
3106 | case SIM_FPU_IS_PNUMBER: | |
3107 | gt = 1; | |
3108 | break; | |
3109 | case SIM_FPU_IS_NDENORM: | |
3110 | lt = 1; | |
3111 | break; | |
3112 | case SIM_FPU_IS_PDENORM: | |
3113 | gt = 1; | |
3114 | break; | |
3115 | case SIM_FPU_IS_NZERO: | |
3116 | case SIM_FPU_IS_PZERO: | |
3117 | eq = 1; | |
3118 | break; | |
3119 | } | |
3120 | ||
3121 | switch (cmp) | |
3122 | { | |
3123 | case FPU_CMP_F: | |
3124 | result = 0; | |
3125 | break; | |
3126 | case FPU_CMP_UN: | |
3127 | result = 0; | |
3128 | break; | |
3129 | case FPU_CMP_EQ: | |
3130 | result = eq; | |
3131 | break; | |
3132 | case FPU_CMP_UEQ: | |
3133 | result = eq; | |
3134 | break; | |
3135 | case FPU_CMP_OLT: | |
3136 | result = lt; | |
3137 | break; | |
3138 | case FPU_CMP_ULT: | |
3139 | result = lt; | |
3140 | break; | |
3141 | case FPU_CMP_OLE: | |
3142 | result = lt || eq; | |
3143 | break; | |
3144 | case FPU_CMP_ULE: | |
3145 | result = lt || eq; | |
3146 | break; | |
3147 | case FPU_CMP_SF: | |
3148 | result = 0; | |
3149 | break; | |
3150 | case FPU_CMP_NGLE: | |
3151 | result = 0; | |
3152 | break; | |
3153 | case FPU_CMP_SEQ: | |
3154 | result = eq; | |
3155 | break; | |
3156 | case FPU_CMP_NGL: | |
3157 | result = eq; | |
3158 | break; | |
3159 | case FPU_CMP_LT: | |
3160 | result = lt; | |
3161 | break; | |
3162 | case FPU_CMP_NGE: | |
3163 | result = lt; | |
3164 | break; | |
3165 | case FPU_CMP_LE: | |
3166 | result = lt || eq; | |
3167 | break; | |
3168 | case FPU_CMP_NGT: | |
3169 | result = lt || eq; | |
3170 | break; | |
3171 | } | |
3172 | } | |
3173 | ||
3174 | ASSERT(result != -1); | |
3175 | return result; | |
3176 | } | |
3177 | ||
3178 | void v850_div(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) | |
3179 | { | |
3180 | signed long int quotient; | |
3181 | signed long int remainder; | |
3182 | signed long int divide_by; | |
3183 | signed long int divide_this; | |
3184 | bfd_boolean overflow = FALSE; | |
3185 | ||
3186 | /* Compute the result. */ | |
3187 | divide_by = op0; | |
3188 | divide_this = op1; | |
3189 | ||
3190 | if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) | |
3191 | { | |
3192 | overflow = TRUE; | |
3193 | divide_by = 1; | |
3194 | } | |
3195 | ||
3196 | quotient = divide_this / divide_by; | |
3197 | remainder = divide_this % divide_by; | |
3198 | ||
3199 | /* Set condition codes. */ | |
3200 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
3201 | ||
3202 | if (overflow) PSW |= PSW_OV; | |
3203 | if (quotient == 0) PSW |= PSW_Z; | |
3204 | if (quotient < 0) PSW |= PSW_S; | |
3205 | ||
3206 | *op2p = quotient; | |
3207 | *op3p = remainder; | |
3208 | } | |
3209 | ||
3210 | void v850_divu(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) | |
3211 | { | |
3212 | unsigned long int quotient; | |
3213 | unsigned long int remainder; | |
3214 | unsigned long int divide_by; | |
3215 | unsigned long int divide_this; | |
3216 | bfd_boolean overflow = FALSE; | |
3217 | ||
3218 | /* Compute the result. */ | |
3219 | ||
3220 | divide_by = op0; | |
3221 | divide_this = op1; | |
3222 | ||
3223 | if (divide_by == 0) | |
3224 | { | |
3225 | overflow = TRUE; | |
3226 | divide_by = 1; | |
3227 | } | |
3228 | ||
3229 | quotient = divide_this / divide_by; | |
3230 | remainder = divide_this % divide_by; | |
3231 | ||
3232 | /* Set condition codes. */ | |
3233 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
3234 | ||
3235 | if (overflow) PSW |= PSW_OV; | |
3236 | if (quotient == 0) PSW |= PSW_Z; | |
3237 | if (quotient & 0x80000000) PSW |= PSW_S; | |
3238 | ||
3239 | *op2p = quotient; | |
3240 | *op3p = remainder; | |
3241 | } | |
3242 | ||
3243 | ||
3244 | void v850_sar(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
3245 | { | |
3246 | unsigned int result, z, s, cy; | |
3247 | ||
3248 | op0 &= 0x1f; | |
3249 | result = (signed)op1 >> op0; | |
3250 | ||
3251 | /* Compute the condition codes. */ | |
3252 | z = (result == 0); | |
3253 | s = (result & 0x80000000); | |
3254 | cy = (op1 & (1 << (op0 - 1))); | |
3255 | ||
3256 | /* Store the result and condition codes. */ | |
3257 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3258 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3259 | | (cy ? PSW_CY : 0)); | |
3260 | ||
3261 | *op2p = result; | |
3262 | } | |
3263 | ||
3264 | void v850_shl(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
3265 | { | |
3266 | unsigned int result, z, s, cy; | |
3267 | ||
3268 | op0 &= 0x1f; | |
3269 | result = op1 << op0; | |
3270 | ||
3271 | /* Compute the condition codes. */ | |
3272 | z = (result == 0); | |
3273 | s = (result & 0x80000000); | |
3274 | cy = (op1 & (1 << (32 - op0))); | |
3275 | ||
3276 | /* Store the result and condition codes. */ | |
3277 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3278 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3279 | | (cy ? PSW_CY : 0)); | |
3280 | ||
3281 | *op2p = result; | |
3282 | } | |
3283 | ||
67d7515b NC |
3284 | void |
3285 | v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest) | |
3286 | { | |
3287 | unsigned int result, z, s, cy; | |
3288 | ||
3289 | amount &= 0x1f; | |
3290 | result = src << amount; | |
3291 | result |= src >> (32 - amount); | |
3292 | ||
3293 | /* Compute the condition codes. */ | |
3294 | z = (result == 0); | |
3295 | s = (result & 0x80000000); | |
3296 | cy = ! (result & 1); | |
3297 | ||
3298 | /* Store the result and condition codes. */ | |
3299 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3300 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3301 | | (cy ? PSW_CY : 0)); | |
3302 | ||
3303 | * dest = result; | |
3304 | } | |
3305 | ||
3306 | void | |
3307 | v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb, | |
3308 | unsigned int * dest) | |
3309 | { | |
3310 | unsigned int mask; | |
3311 | unsigned int result, pos, width; | |
3312 | unsigned int z, s; | |
3313 | ||
3314 | pos = lsb; | |
3315 | width = (msb - lsb) + 1; | |
3316 | ||
3317 | mask = ~ (-1 << width); | |
3318 | source &= mask; | |
3319 | mask <<= pos; | |
3320 | result = (* dest) & ~ mask; | |
3321 | result |= source << pos; | |
3322 | ||
3323 | /* Compute the condition codes. */ | |
3324 | z = (result == 0); | |
3325 | s = result & 0x80000000; | |
3326 | ||
3327 | /* Store the result and condition codes. */ | |
3328 | PSW &= ~(PSW_Z | PSW_S | PSW_OV ); | |
3329 | PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0); | |
3330 | ||
3331 | * dest = result; | |
3332 | } | |
3333 | ||
2aaed979 KB |
3334 | void v850_shr(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) |
3335 | { | |
3336 | unsigned int result, z, s, cy; | |
3337 | ||
3338 | op0 &= 0x1f; | |
3339 | result = op1 >> op0; | |
3340 | ||
3341 | /* Compute the condition codes. */ | |
3342 | z = (result == 0); | |
3343 | s = (result & 0x80000000); | |
3344 | cy = (op1 & (1 << (op0 - 1))); | |
3345 | ||
3346 | /* Store the result and condition codes. */ | |
3347 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3348 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3349 | | (cy ? PSW_CY : 0)); | |
3350 | ||
3351 | *op2p = result; | |
3352 | } | |
3353 | ||
3354 | void v850_satadd(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
3355 | { | |
3356 | unsigned int result, z, s, cy, ov, sat; | |
3357 | ||
3358 | result = op0 + op1; | |
3359 | ||
3360 | /* Compute the condition codes. */ | |
3361 | z = (result == 0); | |
3362 | s = (result & 0x80000000); | |
3363 | cy = (result < op0 || result < op1); | |
3364 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
3365 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
3366 | sat = ov; | |
3367 | ||
3368 | /* Store the result and condition codes. */ | |
3369 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
3370 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3371 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
3372 | | (sat ? PSW_SAT : 0)); | |
3373 | ||
3374 | /* Handle saturated results. */ | |
3375 | if (sat && s) | |
3376 | { | |
3377 | result = 0x7fffffff; | |
3378 | PSW &= ~PSW_S; | |
3379 | } | |
3380 | else if (sat) | |
3381 | { | |
3382 | result = 0x80000000; | |
3383 | PSW |= PSW_S; | |
3384 | } | |
3385 | ||
3386 | *op2p = result; | |
3387 | } | |
3388 | ||
3389 | void v850_satsub(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
3390 | { | |
3391 | unsigned int result, z, s, cy, ov, sat; | |
3392 | ||
3393 | /* Compute the result. */ | |
3394 | result = op1 - op0; | |
3395 | ||
3396 | /* Compute the condition codes. */ | |
3397 | z = (result == 0); | |
3398 | s = (result & 0x80000000); | |
3399 | cy = (op1 < op0); | |
3400 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
3401 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
3402 | sat = ov; | |
3403 | ||
3404 | /* Store the result and condition codes. */ | |
3405 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
3406 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3407 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
3408 | | (sat ? PSW_SAT : 0)); | |
3409 | ||
3410 | /* Handle saturated results. */ | |
3411 | if (sat && s) | |
3412 | { | |
3413 | result = 0x7fffffff; | |
3414 | PSW &= ~PSW_S; | |
3415 | } | |
3416 | else if (sat) | |
3417 | { | |
3418 | result = 0x80000000; | |
3419 | PSW |= PSW_S; | |
3420 | } | |
3421 | ||
3422 | *op2p = result; | |
3423 | } | |
3424 | ||
3425 | unsigned32 | |
3426 | load_data_mem(sd, addr, len) | |
3427 | SIM_DESC sd; | |
3428 | SIM_ADDR addr; | |
3429 | int len; | |
3430 | { | |
3431 | uint32 data; | |
3432 | ||
3433 | switch (len) | |
3434 | { | |
3435 | case 1: | |
3436 | data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0), | |
3437 | PC, read_map, addr); | |
3438 | break; | |
3439 | case 2: | |
3440 | data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0), | |
3441 | PC, read_map, addr); | |
3442 | break; | |
3443 | case 4: | |
3444 | data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0), | |
3445 | PC, read_map, addr); | |
3446 | break; | |
3447 | default: | |
3448 | abort (); | |
3449 | } | |
3450 | return data; | |
3451 | } | |
3452 | ||
3453 | void | |
3454 | store_data_mem(sd, addr, len, data) | |
3455 | SIM_DESC sd; | |
3456 | SIM_ADDR addr; | |
3457 | int len; | |
3458 | unsigned32 data; | |
3459 | { | |
3460 | switch (len) | |
3461 | { | |
3462 | case 1: | |
3463 | store_mem(addr, 1, data); | |
3464 | break; | |
3465 | case 2: | |
3466 | store_mem(addr, 2, data); | |
3467 | break; | |
3468 | case 4: | |
3469 | store_mem(addr, 4, data); | |
3470 | break; | |
3471 | default: | |
3472 | abort (); | |
3473 | } | |
3474 | } | |
3475 | ||
3476 | int mpu_load_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg) | |
3477 | { | |
3478 | int result = 1; | |
3479 | ||
3480 | if (PSW & PSW_DMP) | |
3481 | { | |
3482 | if (IPE0 && addr >= IPA2ADDR(IPA0L) && addr <= IPA2ADDR(IPA0L) && IPR0) | |
3483 | { | |
3484 | /* text area */ | |
3485 | } | |
3486 | else if (IPE1 && addr >= IPA2ADDR(IPA1L) && addr <= IPA2ADDR(IPA1L) && IPR1) | |
3487 | { | |
3488 | /* text area */ | |
3489 | } | |
3490 | else if (IPE2 && addr >= IPA2ADDR(IPA2L) && addr <= IPA2ADDR(IPA2L) && IPR2) | |
3491 | { | |
3492 | /* text area */ | |
3493 | } | |
3494 | else if (IPE3 && addr >= IPA2ADDR(IPA3L) && addr <= IPA2ADDR(IPA3L) && IPR3) | |
3495 | { | |
3496 | /* text area */ | |
3497 | } | |
3498 | else if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM)) | |
3499 | { | |
3500 | /* preifarallel area */ | |
3501 | } | |
3502 | else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU)) | |
3503 | { | |
3504 | /* stack area */ | |
3505 | } | |
3506 | else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPR0 | |
3507 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3508 | { | |
3509 | /* data area */ | |
3510 | } | |
3511 | else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPR1 | |
3512 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3513 | { | |
3514 | /* data area */ | |
3515 | } | |
3516 | else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPR2 | |
3517 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3518 | { | |
3519 | /* data area */ | |
3520 | } | |
3521 | else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPR3 | |
3522 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3523 | { | |
3524 | /* data area */ | |
3525 | } | |
3526 | else | |
3527 | { | |
3528 | VMECR &= ~(VMECR_VMW | VMECR_VMX); | |
3529 | VMECR |= VMECR_VMR; | |
3530 | VMADR = addr; | |
3531 | VMTID = TID; | |
3532 | FEIC = 0x431; | |
3533 | ||
3534 | PC = 0x30; | |
3535 | ||
3536 | SignalException(sd); | |
3537 | result = 0; | |
3538 | } | |
3539 | } | |
3540 | ||
3541 | return result; | |
3542 | } | |
3543 | ||
3544 | int mpu_store_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg) | |
3545 | { | |
3546 | int result = 1; | |
3547 | ||
3548 | if (PSW & PSW_DMP) | |
3549 | { | |
3550 | if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM)) | |
3551 | { | |
3552 | /* preifarallel area */ | |
3553 | } | |
3554 | else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU)) | |
3555 | { | |
3556 | /* stack area */ | |
3557 | } | |
3558 | else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPW0 | |
3559 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3560 | { | |
3561 | /* data area */ | |
3562 | } | |
3563 | else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPW1 | |
3564 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3565 | { | |
3566 | /* data area */ | |
3567 | } | |
3568 | else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPW2 | |
3569 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3570 | { | |
3571 | /* data area */ | |
3572 | } | |
3573 | else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPW3 | |
3574 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) | |
3575 | { | |
3576 | /* data area */ | |
3577 | } | |
3578 | else | |
3579 | { | |
3580 | if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM)) | |
3581 | { | |
3582 | FEIC = 0x432; | |
3583 | VPTID = TID; | |
3584 | VPADR = PC; | |
3585 | #ifdef NOT_YET | |
3586 | VIP_PP; | |
3587 | VPECR; | |
3588 | #endif | |
3589 | } | |
3590 | else | |
3591 | { | |
3592 | FEIC = 0x431; | |
3593 | VMTID = TID; | |
3594 | VMADR = VMECR; | |
3595 | VMECR &= ~(VMECR_VMW | VMECR_VMX); | |
3596 | VMECR |= VMECR_VMR; | |
3597 | PC = 0x30; | |
3598 | } | |
3599 | result = 0; | |
3600 | } | |
3601 | } | |
3602 | ||
3603 | return result; | |
3604 | } | |
3605 |