[deliverable/binutils-gdb.git] / sim / v850 / simops.c

#include <signal.h>
#include "v850_sim.h"
#include "simops.h"

void
OP_220 ()
{
}

void
OP_10760 ()
{
}

void
OP_C7C0 ()
{
}

void
OP_760 ()
{
}

void
OP_580 ()
{
}

void
OP_700 ()
{
}

void
OP_581 ()
{
}

void
OP_582 ()
{
}

void
OP_583 ()
{
}

void
OP_584 ()
{
}

void
OP_585 ()
{
}

void
OP_586 ()
{
}

void
OP_587 ()
{
}

void
OP_588 ()
{
}

void
OP_589 ()
{
}

void
OP_58A ()
{
}

void
OP_58B ()
{
}

void
OP_58C ()
{
}

void
OP_400 ()
{
}

void
OP_160 ()
{
}

void
OP_58D ()
{
}

void
OP_58E ()
{
}

void
OP_58F ()
{
}

void
OP_660 ()
{
}


/* add reg, reg */
void
OP_1C0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 + op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* add sign_extend(imm5), reg */
void
OP_240 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;
  int temp;

  /* Compute the result.  */
  temp = (OP[0] & 0x1f);
  temp = (temp << 27) >> 27;
  op0 = temp;
  op1 = State.regs[OP[1]];
  result = op0 + op1;
  
  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* addi sign_extend(imm16), reg, reg */
void
OP_600 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;
  int temp;

  /* Compute the result.  */
  temp = (OP[0] & 0xffff);
  temp = (temp << 16) >> 16;
  op0 = temp;
  op1 = State.regs[OP[1]];
  result = op0 + op1;
  
  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* sub reg1, reg2

   XXX condition codes  */
void
OP_1A0 ()
{
  State.regs[OP[1]] -= State.regs[OP[0]];
}

/* subr reg1, reg2

   XXX condition codes */
void
OP_180 ()
{
  State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
}

/* mulh reg1, reg2

   XXX condition codes */
void
OP_E0 ()
{
  State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
		       * (State.regs[OP[0]] & 0xffff));
}

/* mulh sign_extend(imm5), reg2

   Condition codes */
void
OP_2E0 ()
{
  int value = OP[0];
 
  value = (value << 27) >> 27;

  State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
}

/* mulhi imm16, reg1, reg2

   XXX condition codes */
void
OP_6E0 ()
{
  int value = OP[0];
 
  value = value & 0xffff;

  State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
}

/* divh reg1, reg2

   XXX condition codes.
   XXX Is this signed or unsigned?  */
void
OP_40 ()
{
  State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
}

void
OP_10720 ()
{
}

void
OP_780 ()
{
}

void
OP_720 ()
{
}

void
OP_60 ()
{
}

void
OP_87C0 ()
{
}

void
OP_300 ()
{
}

/* mov reg, reg */
void
OP_0 ()
{
  State.regs[OP[1]] = State.regs[OP[0]];
}

/* mov sign_extend(imm5), reg */
void
OP_200 ()
{
  int value = OP[0];
 
  value = (value << 27) >> 27;
  State.regs[OP[1]] = value;
}

/* movea sign_extend(imm16), reg, reg  */

void
OP_620 ()
{
  int value = OP[0];
 
  value = (value << 16) >> 16;

  State.regs[OP[2]] = State.regs[OP[1]] + value;
}

/* movhi imm16, reg, reg */
void
OP_640 ()
{
  int value = OP[0];
 
  value = (value & 0xffff) << 16; 

  State.regs[OP[2]] = State.regs[OP[1]] + value;
}

void
OP_7C0 ()
{
}

void
OP_1687E0 ()
{
}

void
OP_1E0 ()
{
}

void
OP_A0 ()
{
}

void
OP_260 ()
{
}

void
OP_740 ()
{
}

void
OP_80 ()
{
}

/* sar zero_extend(imm5),reg1

   XXX condition codes.  */
void
OP_2A0 ()
{
  int temp = State.regs[OP[1]];

  temp >>= (OP[0] & 0x1f);

  State.regs[OP[1]] = temp;
}

/* sar reg1, reg2

   XXX condition codes.  */
void
OP_A007E0 ()
{
  int temp = State.regs[OP[1]];

  temp >>= (State.regs[OP[0]] & 0x1f);

  State.regs[OP[1]] = temp;
}

/* shl zero_extend(imm5),reg1

   XXX condition codes.  */
void
OP_2C0 ()
{
  State.regs[OP[1]] <<= (OP[0] & 0x1f);
}

/* shl reg1, reg2

   XXX condition codes.  */
void
OP_C007E0 ()
{
  State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
}

/* shr zero_extend(imm5),reg1

   XXX condition codes.  */
void
OP_280 ()
{
  State.regs[OP[1]] >>= (OP[0] & 0x1f);
}

/* shr reg1, reg2

   XXX condition codes.  */
void
OP_8007E0 ()
{
  State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
}

void
OP_500 ()
{
}

void
OP_47C0 ()
{
}

void
OP_7E0 ()
{
}

/* or reg, reg */
void
OP_100 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 | op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* ori zero_extend(imm16), reg, reg */
void
OP_680 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 | op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
  State.psw |= (z ? PSW_Z : 0);
}

/* and reg, reg */
void
OP_140 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 & op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* andi zero_extend(imm16), reg, reg */
void
OP_6C0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 & op1;

  /* Compute the condition codes.  */
  z = (result == 0);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= (z ? PSW_Z : 0);
}

/* xor reg, reg */
void
OP_120 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 ^ op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* xori zero_extend(imm16), reg, reg */
void
OP_6A0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 ^ op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
  State.psw |= (z ? PSW_Z : 0);
}

/* not reg1, reg2 */
void
OP_20 ()
{
  unsigned int op0, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  result = ~op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

void
OP_C0 ()
{
}

void
OP_480 ()
{
}

void
OP_380 ()
{
}

void
OP_501 ()
{
}

/* di, not supported */
void
OP_16007E0 ()
{
  abort ();
}

/* ei, not supported */
void
OP_16087E0 ()
{
  abort ();
}

/* halt, not supported */
void
OP_12007E0 ()
{
  abort ();
}

/* reti, not supported */
void
OP_14007E0 ()
{
  abort ();
}

/* trap, not supportd */
void
OP_10007E0 ()
{
  abort ();
}

/* ldsr, not supported */
void
OP_2007E0 ()
{
  abort ();
}

/* stsr, not supported */
void
OP_4007E0 ()
{
  abort ();
}
Commit	Line	Data
22c1c7dd JL	1	#include <signal.h>
	2	#include "v850_sim.h"
	3	#include "simops.h"
	4
22c1c7dd JL	5	void
	6	OP_220 ()
	7	{
	8	}
	9
	10	void
	11	OP_10760 ()
	12	{
	13	}
	14
	15	void
	16	OP_C7C0 ()
	17	{
	18	}
	19
	20	void
	21	OP_760 ()
	22	{
	23	}
	24
22c1c7dd JL	25	void
	26	OP_580 ()
	27	{
	28	}
	29
	30	void
	31	OP_700 ()
	32	{
	33	}
	34
	35	void
	36	OP_581 ()
	37	{
	38	}
	39
22c1c7dd JL	40	void
	41	OP_582 ()
	42	{
	43	}
	44
	45	void
	46	OP_583 ()
	47	{
	48	}
	49
	50	void
	51	OP_584 ()
	52	{
	53	}
	54
	55	void
	56	OP_585 ()
	57	{
	58	}
	59
	60	void
	61	OP_586 ()
	62	{
	63	}
	64
	65	void
	66	OP_587 ()
	67	{
	68	}
	69
	70	void
	71	OP_588 ()
	72	{
	73	}
	74
	75	void
	76	OP_589 ()
	77	{
	78	}
	79
	80	void
	81	OP_58A ()
	82	{
	83	}
	84
	85	void
	86	OP_58B ()
	87	{
	88	}
	89
	90	void
	91	OP_58C ()
	92	{
	93	}
	94
	95	void
	96	OP_400 ()
	97	{
	98	}
	99
22c1c7dd JL	100	void
	101	OP_160 ()
	102	{
	103	}
	104
	105	void
	106	OP_58D ()
	107	{
	108	}
	109
	110	void
	111	OP_58E ()
	112	{
	113	}
	114
	115	void
	116	OP_58F ()
	117	{
	118	}
	119
	120	void
	121	OP_660 ()
	122	{
	123	}
	124
22c1c7dd	125
0ef0eba5	126	/* add reg, reg */
22c1c7dd	127	void
1fe983dc	128	OP_1C0 ()
22c1c7dd	129	{
0ef0eba5	130	unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd	131
0ef0eba5 JL	132	/* Compute the result. */
	133	op0 = State.regs[OP[0]];
	134	op1 = State.regs[OP[1]];
	135	result = op0 + op1;
1fe983dc	136
0ef0eba5 JL	137	/* Compute the condition codes. */
	138	z = (result == 0);
	139	s = (result & 0x80000000);
	140	cy = (result < op0 \|\| result < op1);
	141	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	142	&& (op0 & 0x80000000) != (result & 0x80000000));
	143
	144	/* Store the result and condition codes. */
	145	State.regs[OP[1]] = result;
	146	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	147	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	148	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	149	}
	150
	151	/* add sign_extend(imm5), reg */
22c1c7dd	152	void
1fe983dc	153	OP_240 ()
22c1c7dd	154	{
0ef0eba5 JL	155	unsigned int op0, op1, result, z, s, cy, ov;
0ef0eba5 JL	156	int temp;
1fe983dc	157
0ef0eba5 JL	158	/* Compute the result. */
	159	temp = (OP[0] & 0x1f);
	160	temp = (temp << 27) >> 27;
	161	op0 = temp;
	162	op1 = State.regs[OP[1]];
	163	result = op0 + op1;
	164
	165	/* Compute the condition codes. */
	166	z = (result == 0);
	167	s = (result & 0x80000000);
	168	cy = (result < op0 \|\| result < op1);
	169	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	170	&& (op0 & 0x80000000) != (result & 0x80000000));
22c1c7dd	171
0ef0eba5 JL	172	/* Store the result and condition codes. */
	173	State.regs[OP[1]] = result;
	174	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	175	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	176	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	177	}
1fe983dc	178
0ef0eba5	179	/* addi sign_extend(imm16), reg, reg */
22c1c7dd	180	void
1fe983dc	181	OP_600 ()
22c1c7dd	182	{
0ef0eba5 JL	183	unsigned int op0, op1, result, z, s, cy, ov;
	184	int temp;
	185
	186	/* Compute the result. */
	187	temp = (OP[0] & 0xffff);
	188	temp = (temp << 16) >> 16;
	189	op0 = temp;
	190	op1 = State.regs[OP[1]];
	191	result = op0 + op1;
	192
	193	/* Compute the condition codes. */
	194	z = (result == 0);
	195	s = (result & 0x80000000);
	196	cy = (result < op0 \|\| result < op1);
	197	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	198	&& (op0 & 0x80000000) != (result & 0x80000000));
	199
	200	/* Store the result and condition codes. */
	201	State.regs[OP[2]] = result;
	202	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	203	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	204	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
22c1c7dd JL	205	}
22c1c7dd JL	206
1fe983dc JL	207	/* sub reg1, reg2
	208
	209	XXX condition codes */
22c1c7dd	210	void
1fe983dc	211	OP_1A0 ()
22c1c7dd	212	{
1fe983dc	213	State.regs[OP[1]] -= State.regs[OP[0]];
22c1c7dd JL	214	}
22c1c7dd JL	215
1fe983dc JL	216	/* subr reg1, reg2
	217
	218	XXX condition codes */
22c1c7dd	219	void
1fe983dc	220	OP_180 ()
22c1c7dd	221	{
1fe983dc	222	State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
22c1c7dd JL	223	}
22c1c7dd JL	224
e98e3b2c JL	225	/* mulh reg1, reg2
	226
	227	XXX condition codes */
22c1c7dd	228	void
e98e3b2c	229	OP_E0 ()
22c1c7dd	230	{
e98e3b2c	231	State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
fb8eb42b	232	* (State.regs[OP[0]] & 0xffff));
22c1c7dd JL	233	}
22c1c7dd JL	234
e98e3b2c JL	235	/* mulh sign_extend(imm5), reg2
	236
	237	Condition codes */
22c1c7dd	238	void
e98e3b2c	239	OP_2E0 ()
22c1c7dd	240	{
e98e3b2c JL	241	int value = OP[0];
	242
	243	value = (value << 27) >> 27;
	244
	245	State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
22c1c7dd JL	246	}
22c1c7dd JL	247
e98e3b2c JL	248	/* mulhi imm16, reg1, reg2
	249
	250	XXX condition codes */
22c1c7dd	251	void
e98e3b2c JL	252	OP_6E0 ()
	253	{
	254	int value = OP[0];
	255
	256	value = value & 0xffff;
	257
fb8eb42b	258	State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
e98e3b2c JL	259	}
	260
	261	/* divh reg1, reg2
	262
	263	XXX condition codes.
	264	XXX Is this signed or unsigned? */
	265	void
	266	OP_40 ()
22c1c7dd	267	{
fb8eb42b	268	State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
22c1c7dd JL	269	}
22c1c7dd JL	270
22c1c7dd	271	void
1fe983dc	272	OP_10720 ()
22c1c7dd JL	273	{
	274	}
	275
	276	void
1fe983dc	277	OP_780 ()
22c1c7dd JL	278	{
	279	}
	280
	281	void
	282	OP_720 ()
	283	{
	284	}
	285
	286	void
	287	OP_60 ()
	288	{
	289	}
	290
22c1c7dd JL	291	void
	292	OP_87C0 ()
	293	{
	294	}
	295
22c1c7dd JL	296	void
	297	OP_300 ()
	298	{
	299	}
	300
1fe983dc	301	/* mov reg, reg */
22c1c7dd JL	302	void
	303	OP_0 ()
	304	{
1fe983dc	305	State.regs[OP[1]] = State.regs[OP[0]];
22c1c7dd JL	306	}
22c1c7dd JL	307
1fe983dc	308	/* mov sign_extend(imm5), reg */
22c1c7dd	309	void
1fe983dc	310	OP_200 ()
22c1c7dd	311	{
1fe983dc JL	312	int value = OP[0];
	313
	314	value = (value << 27) >> 27;
	315	State.regs[OP[1]] = value;
22c1c7dd JL	316	}
22c1c7dd JL	317
1fe983dc JL	318	/* movea sign_extend(imm16), reg, reg */
1fe983dc JL	319
22c1c7dd	320	void
1fe983dc	321	OP_620 ()
22c1c7dd	322	{
1fe983dc JL	323	int value = OP[0];
	324
	325	value = (value << 16) >> 16;
	326
	327	State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd JL	328	}
22c1c7dd JL	329
1fe983dc	330	/* movhi imm16, reg, reg */
22c1c7dd	331	void
1fe983dc	332	OP_640 ()
22c1c7dd	333	{
1fe983dc JL	334	int value = OP[0];
	335
	336	value = (value & 0xffff) << 16;
	337
	338	State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd JL	339	}
	340
	341	void
1fe983dc	342	OP_7C0 ()
22c1c7dd JL	343	{
	344	}
	345
	346	void
1fe983dc	347	OP_1687E0 ()
22c1c7dd JL	348	{
	349	}
	350
	351	void
	352	OP_1E0 ()
	353	{
	354	}
	355
	356	void
	357	OP_A0 ()
	358	{
	359	}
	360
	361	void
	362	OP_260 ()
	363	{
	364	}
	365
22c1c7dd JL	366	void
	367	OP_740 ()
	368	{
	369	}
	370
	371	void
	372	OP_80 ()
	373	{
	374	}
	375
77553374 JL	376	/* sar zero_extend(imm5),reg1
	377
	378	XXX condition codes. */
22c1c7dd	379	void
77553374	380	OP_2A0 ()
22c1c7dd	381	{
77553374 JL	382	int temp = State.regs[OP[1]];
	383
	384	temp >>= (OP[0] & 0x1f);
	385
	386	State.regs[OP[1]] = temp;
22c1c7dd JL	387	}
22c1c7dd JL	388
77553374 JL	389	/* sar reg1, reg2
	390
	391	XXX condition codes. */
22c1c7dd	392	void
77553374	393	OP_A007E0 ()
22c1c7dd	394	{
77553374 JL	395	int temp = State.regs[OP[1]];
	396
	397	temp >>= (State.regs[OP[0]] & 0x1f);
	398
	399	State.regs[OP[1]] = temp;
22c1c7dd JL	400	}
22c1c7dd JL	401
77553374 JL	402	/* shl zero_extend(imm5),reg1
	403
	404	XXX condition codes. */
22c1c7dd JL	405	void
22c1c7dd JL	406	OP_2C0 ()
77553374 JL	407	{
	408	State.regs[OP[1]] <<= (OP[0] & 0x1f);
	409	}
	410
	411	/* shl reg1, reg2
	412
	413	XXX condition codes. */
	414	void
	415	OP_C007E0 ()
	416	{
	417	State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
	418	}
	419
	420	/* shr zero_extend(imm5),reg1
	421
	422	XXX condition codes. */
	423	void
	424	OP_280 ()
	425	{
	426	State.regs[OP[1]] >>= (OP[0] & 0x1f);
	427	}
	428
	429	/* shr reg1, reg2
	430
	431	XXX condition codes. */
	432	void
	433	OP_8007E0 ()
	434	{
	435	State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
	436	}
	437
	438	void
	439	OP_500 ()
22c1c7dd JL	440	{
	441	}
	442
22c1c7dd JL	443	void
	444	OP_47C0 ()
	445	{
	446	}
	447
22c1c7dd JL	448	void
	449	OP_7E0 ()
	450	{
	451	}
	452
0ef0eba5	453	/* or reg, reg */
1fe983dc JL	454	void
	455	OP_100 ()
	456	{
0ef0eba5	457	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	458
0ef0eba5 JL	459	/* Compute the result. */
	460	op0 = State.regs[OP[0]];
	461	op1 = State.regs[OP[1]];
	462	result = op0 \| op1;
1fe983dc	463
0ef0eba5 JL	464	/* Compute the condition codes. */
	465	z = (result == 0);
	466	s = (result & 0x80000000);
	467
	468	/* Store the result and condition codes. */
	469	State.regs[OP[1]] = result;
	470	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	471	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	472	}
	473
	474	/* ori zero_extend(imm16), reg, reg */
1fe983dc JL	475	void
	476	OP_680 ()
	477	{
0ef0eba5	478	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	479
0ef0eba5 JL	480	op0 = OP[0] & 0xffff;
	481	op1 = State.regs[OP[1]];
	482	result = op0 \| op1;
1fe983dc	483
0ef0eba5 JL	484	/* Compute the condition codes. */
	485	z = (result == 0);
	486	s = (result & 0x80000000);
1fe983dc	487
0ef0eba5 JL	488	/* Store the result and condition codes. */
	489	State.regs[OP[2]] = result;
	490	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	491	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	492	State.psw \|= (z ? PSW_Z : 0);
	493	}
	494
	495	/* and reg, reg */
22c1c7dd JL	496	void
	497	OP_140 ()
	498	{
0ef0eba5	499	unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd	500
0ef0eba5 JL	501	/* Compute the result. */
	502	op0 = State.regs[OP[0]];
	503	op1 = State.regs[OP[1]];
	504	result = op0 & op1;
1fe983dc	505
0ef0eba5 JL	506	/* Compute the condition codes. */
	507	z = (result == 0);
	508	s = (result & 0x80000000);
	509
	510	/* Store the result and condition codes. */
	511	State.regs[OP[1]] = result;
	512	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	513	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	514	}
	515
	516	/* andi zero_extend(imm16), reg, reg */
22c1c7dd	517	void
1fe983dc JL	518	OP_6C0 ()
1fe983dc JL	519	{
0ef0eba5	520	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	521
0ef0eba5 JL	522	op0 = OP[0] & 0xffff;
	523	op1 = State.regs[OP[1]];
	524	result = op0 & op1;
1fe983dc	525
0ef0eba5 JL	526	/* Compute the condition codes. */
0ef0eba5 JL	527	z = (result == 0);
1fe983dc	528
0ef0eba5 JL	529	/* Store the result and condition codes. */
	530	State.regs[OP[2]] = result;
	531	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	532	State.psw \|= (z ? PSW_Z : 0);
	533	}
	534
	535	/* xor reg, reg */
1fe983dc JL	536	void
1fe983dc JL	537	OP_120 ()
22c1c7dd	538	{
0ef0eba5	539	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	540
0ef0eba5 JL	541	/* Compute the result. */
	542	op0 = State.regs[OP[0]];
	543	op1 = State.regs[OP[1]];
	544	result = op0 ^ op1;
1fe983dc	545
0ef0eba5 JL	546	/* Compute the condition codes. */
	547	z = (result == 0);
	548	s = (result & 0x80000000);
	549
	550	/* Store the result and condition codes. */
	551	State.regs[OP[1]] = result;
	552	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	553	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	554	}
	555
	556	/* xori zero_extend(imm16), reg, reg */
1fe983dc JL	557	void
	558	OP_6A0 ()
	559	{
0ef0eba5 JL	560	unsigned int op0, op1, result, z, s, cy, ov;
	561
	562	op0 = OP[0] & 0xffff;
	563	op1 = State.regs[OP[1]];
	564	result = op0 ^ op1;
	565
	566	/* Compute the condition codes. */
	567	z = (result == 0);
	568	s = (result & 0x80000000);
	569
	570	/* Store the result and condition codes. */
	571	State.regs[OP[2]] = result;
	572	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	573	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	574	State.psw \|= (z ? PSW_Z : 0);
	575	}
	576
	577	/* not reg1, reg2 */
	578	void
	579	OP_20 ()
	580	{
	581	unsigned int op0, result, z, s, cy, ov;
	582
	583	/* Compute the result. */
	584	op0 = State.regs[OP[0]];
	585	result = ~op0;
	586
	587	/* Compute the condition codes. */
	588	z = (result == 0);
	589	s = (result & 0x80000000);
1fe983dc	590
0ef0eba5 JL	591	/* Store the result and condition codes. */
	592	State.regs[OP[1]] = result;
	593	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	594	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
22c1c7dd JL	595	}
	596
	597	void
	598	OP_C0 ()
	599	{
	600	}
	601
1fe983dc JL	602	void
	603	OP_480 ()
	604	{
	605	}
	606
	607	void
	608	OP_380 ()
	609	{
	610	}
	611
	612	void
	613	OP_501 ()
	614	{
	615	}
e98e3b2c JL	616
	617	/* di, not supported */
	618	void
	619	OP_16007E0 ()
	620	{
	621	abort ();
	622	}
	623
	624	/* ei, not supported */
	625	void
	626	OP_16087E0 ()
	627	{
	628	abort ();
	629	}
	630
	631	/* halt, not supported */
	632	void
	633	OP_12007E0 ()
	634	{
	635	abort ();
	636	}
	637
	638	/* reti, not supported */
	639	void
	640	OP_14007E0 ()
	641	{
	642	abort ();
	643	}
	644
	645	/* trap, not supportd */
	646	void
	647	OP_10007E0 ()
	648	{
	649	abort ();
	650	}
	651
	652	/* ldsr, not supported */
	653	void
	654	OP_2007E0 ()
	655	{
	656	abort ();
	657	}
	658
	659	/* stsr, not supported */
	660	void
	661	OP_4007E0 ()
	662	{
	663	abort ();
	664	}
	665