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* v850_sim.h: The V850 doesn't have split I&D spaces. Change
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
CommitLineData
22c1c7dd
JL		 1#include <signal.h>
2#include "v850_sim.h"
3#include "simops.h"
4
28647e4c 5/* sld.b */
22c1c7dd 6void
28647e4c 7OP_300 ()
22c1c7dd
JL		 8{
9}
10
28647e4c 11/* sld.h */
22c1c7dd 12void
28647e4c
JL		 13OP_400 ()
14{
15}
16
17/* sld.w */
18void
19OP_500 ()
22c1c7dd
JL		 20{
21}
22
28647e4c
JL		 23/* sst.b */
24void
25OP_380 ()
26{
27}
28
29/* sst.h */
30void
31OP_480 ()
32{
33}
34
35/* sst.w */
36void
37OP_501 ()
38{
39}
40
41/* ld.b */
42void
43OP_700 ()
44{
45 unsigned int op0, op1, op2;
46 int result, temp;
47
48 op0 = State.regs[OP[0]];
49 temp = OP[2];
50 temp = (temp << 16) >> 16;
51 op2 = temp;
52 result = get_byte (State.mem + op0 + op2);
53 result = (result << 24) >> 24;
54 State.regs[OP[1]] = result;
55}
56
57/* ld.h */
58void
59OP_720 ()
60{
61 unsigned int op0, op1, op2;
62 int result, temp;
63
64 op0 = State.regs[OP[0]];
65 temp = (temp << 16) >> 16;
66 temp &= ~0x1;
67 op2 = temp;
68 result = get_half (State.mem + op0 + op2);
69 result = (result << 16) >> 16;
70 State.regs[OP[1]] = result;
71}
72
73/* ld.w */
74void
75OP_10720 ()
76{
77 unsigned int op0, op1, op2;
78 int result, temp;
79
80 op0 = State.regs[OP[0]];
81 temp = (temp << 16) >> 16;
82 temp &= ~0x1;
83 op2 = temp;
84 result = get_word (State.mem + op0 + op2);
85 State.regs[OP[1]] = result;
86}
87
88/* st.b */
89void
90OP_740 ()
91{
92 unsigned int op0, op1, op2;
93 int result, temp;
94
95 op0 = State.regs[OP[0]];
96 op1 = State.regs[OP[1]];
97 temp = OP[2];
98 temp = (temp << 16) >> 16;
99 op2 = temp;
100 put_byte (State.mem + op0 + op2, op1);
101}
102
103/* st.h */
22c1c7dd
JL		 104void
105OP_760 ()
106{
28647e4c
JL		 107 unsigned int op0, op1, op2;
108 int result, temp;
109
110 op0 = State.regs[OP[0]];
111 op1 = State.regs[OP[1]];
112 temp = OP[2];
113 temp &= ~0x1;
114 temp = (temp << 16) >> 16;
115 op2 = temp;
116 put_half (State.mem + op0 + op2, op1);
117}
118
119/* st.w */
120void
121OP_10760 ()
122{
123 unsigned int op0, op1, op2;
124 int result, temp;
125
126 op0 = State.regs[OP[0]];
127 op1 = State.regs[OP[1]];
128 temp = OP[2];
129 temp &= ~0x1;
130 temp = (temp << 16) >> 16;
131 op2 = temp;
132 put_word (State.mem + op0 + op2, op1);
22c1c7dd
JL		 133}
134
2108e864 135/* bv disp9 */
22c1c7dd
JL		 136void
137OP_580 ()
138{
2108e864
JL		 139 unsigned int op0, psw;
140 int temp;
22c1c7dd 141
2108e864
JL		 142 temp = (State.regs[OP[0]] << 23) >> 23;
143 op0 = temp;
614f1c68 144 psw = State.sregs[5];
2108e864
JL		 145
146 if ((psw & PSW_OV) != 0)
147 State.pc += op0;
148 else
149 State.pc += 2;
22c1c7dd
JL		 150}
151
2108e864 152/* bl disp9 */
22c1c7dd
JL		 153void
154OP_581 ()
155{
2108e864
JL		 156 unsigned int op0, psw;
157 int temp;
158
159 temp = (State.regs[OP[0]] << 23) >> 23;
160 op0 = temp;
614f1c68 161 psw = State.sregs[5];
2108e864
JL		 162
163 if ((psw & PSW_CY) != 0)
164 State.pc += op0;
165 else
166 State.pc += 2;
22c1c7dd
JL		 167}
168
2108e864 169/* be disp9 */
22c1c7dd
JL		 170void
171OP_582 ()
172{
2108e864
JL		 173 unsigned int op0, psw;
174 int temp;
175
176 temp = (State.regs[OP[0]] << 23) >> 23;
177 op0 = temp;
614f1c68 178 psw = State.sregs[5];
2108e864
JL		 179
180 if ((psw & PSW_Z) != 0)
181 State.pc += op0;
182 else
183 State.pc += 2;
22c1c7dd
JL		 184}
185
2108e864 186/* bnh disp 9*/
22c1c7dd
JL		 187void
188OP_583 ()
189{
2108e864
JL		 190 unsigned int op0, psw;
191 int temp;
192
193 temp = (State.regs[OP[0]] << 23) >> 23;
194 op0 = temp;
614f1c68 195 psw = State.sregs[5];
2108e864
JL		 196
197 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
198 State.pc += op0;
199 else
200 State.pc += 2;
22c1c7dd
JL		 201}
202
2108e864 203/* bn disp9 */
22c1c7dd
JL		 204void
205OP_584 ()
206{
2108e864
JL		 207 unsigned int op0, psw;
208 int temp;
209
210 temp = (State.regs[OP[0]] << 23) >> 23;
211 op0 = temp;
614f1c68 212 psw = State.sregs[5];
2108e864
JL		 213
214 if ((psw & PSW_S) != 0)
215 State.pc += op0;
216 else
217 State.pc += 2;
22c1c7dd
JL		 218}
219
2108e864 220/* br disp9 */
22c1c7dd
JL		 221void
222OP_585 ()
223{
2108e864
JL		 224 unsigned int op0;
225 int temp;
226
227 temp = (State.regs[OP[0]] << 23) >> 23;
228 op0 = temp;
229 State.pc += op0;
22c1c7dd
JL		 230}
231
2108e864 232/* blt disp9 */
22c1c7dd
JL		 233void
234OP_586 ()
235{
2108e864
JL		 236 unsigned int op0, psw;
237 int temp;
238
239 temp = (State.regs[OP[0]] << 23) >> 23;
240 op0 = temp;
614f1c68 241 psw = State.sregs[5];
2108e864
JL		 242
243 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
244 State.pc += op0;
245 else
246 State.pc += 2;
22c1c7dd
JL		 247}
248
2108e864 249/* ble disp9 */
22c1c7dd
JL		 250void
251OP_587 ()
252{
2108e864
JL		 253 unsigned int op0, psw;
254 int temp;
255
256 temp = (State.regs[OP[0]] << 23) >> 23;
257 op0 = temp;
614f1c68 258 psw = State.sregs[5];
2108e864
JL		 259
260 if ((((psw & PSW_Z) != 0)
261 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
262 State.pc += op0;
263 else
264 State.pc += 2;
22c1c7dd
JL		 265}
266
2108e864 267/* bnv disp9 */
22c1c7dd
JL		 268void
269OP_588 ()
270{
2108e864
JL		 271 unsigned int op0, psw;
272 int temp;
273
274 temp = (State.regs[OP[0]] << 23) >> 23;
275 op0 = temp;
614f1c68 276 psw = State.sregs[5];
2108e864
JL		 277
278 if ((psw & PSW_OV) == 0)
279 State.pc += op0;
280 else
281 State.pc += 2;
22c1c7dd
JL		 282}
283
2108e864 284/* bnl disp9 */
22c1c7dd
JL		 285void
286OP_589 ()
287{
2108e864
JL		 288 unsigned int op0, psw;
289 int temp;
290
291 temp = (State.regs[OP[0]] << 23) >> 23;
292 op0 = temp;
614f1c68 293 psw = State.sregs[5];
2108e864
JL		 294
295 if ((psw & PSW_CY) == 0)
296 State.pc += op0;
297 else
298 State.pc += 2;
22c1c7dd
JL		 299}
300
2108e864 301/* bne disp9 */
22c1c7dd
JL		 302void
303OP_58A ()
304{
2108e864
JL		 305 unsigned int op0, psw;
306 int temp;
307
308 temp = (State.regs[OP[0]] << 23) >> 23;
309 op0 = temp;
614f1c68 310 psw = State.sregs[5];
2108e864
JL		 311
312 if ((psw & PSW_Z) == 0)
313 State.pc += op0;
314 else
315 State.pc += 2;
22c1c7dd
JL		 316}
317
2108e864 318/* bh disp9 */
22c1c7dd
JL		 319void
320OP_58B ()
321{
2108e864
JL		 322 unsigned int op0, psw;
323 int temp;
22c1c7dd 324
2108e864
JL		 325 temp = (State.regs[OP[0]] << 23) >> 23;
326 op0 = temp;
614f1c68 327 psw = State.sregs[5];
2108e864
JL		 328
329 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
330 State.pc += op0;
331 else
332 State.pc += 2;
22c1c7dd
JL		 333}
334
2108e864 335/* bp disp9 */
22c1c7dd 336void
2108e864 337OP_58C ()
22c1c7dd 338{
2108e864
JL		 339 unsigned int op0, psw;
340 int temp;
22c1c7dd 341
2108e864
JL		 342 temp = (State.regs[OP[0]] << 23) >> 23;
343 op0 = temp;
614f1c68 344 psw = State.sregs[5];
2108e864
JL		 345
346 if ((psw & PSW_S) == 0)
347 State.pc += op0;
348 else
349 State.pc += 2;
22c1c7dd
JL		 350}
351
2108e864 352/* bsa disp9 */
22c1c7dd
JL		 353void
354OP_58D ()
355{
2108e864
JL		 356 unsigned int op0, psw;
357 int temp;
358
359 temp = (State.regs[OP[0]] << 23) >> 23;
360 op0 = temp;
614f1c68 361 psw = State.sregs[5];
2108e864
JL		 362
363 if ((psw & PSW_SAT) != 0)
364 State.pc += op0;
365 else
366 State.pc += 2;
22c1c7dd
JL		 367}
368
2108e864 369/* bge disp9 */
22c1c7dd
JL		 370void
371OP_58E ()
372{
2108e864
JL		 373 unsigned int op0, psw;
374 int temp;
375
376 temp = (State.regs[OP[0]] << 23) >> 23;
377 op0 = temp;
614f1c68 378 psw = State.sregs[5];
2108e864
JL		 379
380 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
381 State.pc += op0;
382 else
383 State.pc += 2;
22c1c7dd
JL		 384}
385
2108e864 386/* bgt disp9 */
22c1c7dd
JL		 387void
388OP_58F ()
389{
2108e864
JL		 390 unsigned int op0, psw;
391 int temp;
392
393 temp = (State.regs[OP[0]] << 23) >> 23;
394 op0 = temp;
614f1c68 395 psw = State.sregs[5];
2108e864
JL		 396
397 if ((((psw & PSW_Z) != 0)
398 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
399 State.pc += op0;
400 else
401 State.pc += 2;
22c1c7dd
JL		 402}
403
e9b6cbac 404/* jmp [reg1] */
22c1c7dd 405void
e9b6cbac 406OP_60 ()
22c1c7dd 407{
e9b6cbac
JL		 408 /* interp.c will bump this by +2, so correct for it here. */
409 State.pc = State.regs[OP[0]] - 2;
22c1c7dd
JL		 410}
411
e9b6cbac
JL		 412/* jarl disp22, reg */
413void
414OP_780 ()
415{
416 unsigned int op0, opc;
417 int temp;
418
419 temp = OP[0];
420 temp = (temp << 10) >> 10;
421 op0 = temp;
422 opc = State.pc;
423
424 State.pc += temp;
425
426 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
427 if (OP[1] != 0)
428 State.regs[OP[1]] = opc + 4;
429}
22c1c7dd 430
0ef0eba5 431/* add reg, reg */
22c1c7dd 432void
1fe983dc 433OP_1C0 ()
22c1c7dd 434{
0ef0eba5 435 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 436
0ef0eba5
JL		 437 /* Compute the result. */
438 op0 = State.regs[OP[0]];
439 op1 = State.regs[OP[1]];
440 result = op0 + op1;
1fe983dc 441
0ef0eba5
JL		 442 /* Compute the condition codes. */
443 z = (result == 0);
444 s = (result & 0x80000000);
445 cy = (result < op0 || result < op1);
446 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
447 && (op0 & 0x80000000) != (result & 0x80000000));
448
449 /* Store the result and condition codes. */
450 State.regs[OP[1]] = result;
614f1c68
JL		 451 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
452 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
453 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
0ef0eba5
JL		 454}
455
456/* add sign_extend(imm5), reg */
22c1c7dd 457void
1fe983dc 458OP_240 ()
22c1c7dd 459{
0ef0eba5
JL		 460 unsigned int op0, op1, result, z, s, cy, ov;
461 int temp;
1fe983dc 462
0ef0eba5
JL		 463 /* Compute the result. */
464 temp = (OP[0] & 0x1f);
465 temp = (temp << 27) >> 27;
466 op0 = temp;
467 op1 = State.regs[OP[1]];
468 result = op0 + op1;
469
470 /* Compute the condition codes. */
471 z = (result == 0);
472 s = (result & 0x80000000);
473 cy = (result < op0 || result < op1);
474 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
475 && (op0 & 0x80000000) != (result & 0x80000000));
22c1c7dd 476
0ef0eba5
JL		 477 /* Store the result and condition codes. */
478 State.regs[OP[1]] = result;
614f1c68
JL		 479 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
480 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5
JL		 481 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
482}
1fe983dc 483
0ef0eba5 484/* addi sign_extend(imm16), reg, reg */
22c1c7dd 485void
1fe983dc 486OP_600 ()
22c1c7dd 487{
0ef0eba5
JL		 488 unsigned int op0, op1, result, z, s, cy, ov;
489 int temp;
490
491 /* Compute the result. */
492 temp = (OP[0] & 0xffff);
493 temp = (temp << 16) >> 16;
494 op0 = temp;
495 op1 = State.regs[OP[1]];
496 result = op0 + op1;
497
498 /* Compute the condition codes. */
499 z = (result == 0);
500 s = (result & 0x80000000);
501 cy = (result < op0 || result < op1);
502 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
503 && (op0 & 0x80000000) != (result & 0x80000000));
504
505 /* Store the result and condition codes. */
506 State.regs[OP[2]] = result;
614f1c68
JL		 507 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
508 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5 509 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
22c1c7dd
JL		 510}
511
aabce0f4 512/* sub reg1, reg2 */
22c1c7dd 513void
1fe983dc 514OP_1A0 ()
22c1c7dd 515{
aabce0f4
JL		 516 unsigned int op0, op1, result, z, s, cy, ov;
517
518 /* Compute the result. */
519 op0 = State.regs[OP[0]];
520 op1 = State.regs[OP[1]];
521 result = op1 - op0;
22c1c7dd 522
aabce0f4
JL		 523 /* Compute the condition codes. */
524 z = (result == 0);
525 s = (result & 0x80000000);
526 cy = (result < -op0);
527 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
528 && (op1 & 0x80000000) != (result & 0x80000000));
1fe983dc 529
aabce0f4
JL		 530 /* Store the result and condition codes. */
531 State.regs[OP[1]] = result;
614f1c68
JL		 532 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
533 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 534 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
aabce0f4
JL		 535}
536
537/* subr reg1, reg2 */
22c1c7dd 538void
1fe983dc 539OP_180 ()
22c1c7dd 540{
aabce0f4 541 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 542
aabce0f4
JL		 543 /* Compute the result. */
544 op0 = State.regs[OP[0]];
545 op1 = State.regs[OP[1]];
546 result = op0 - op1;
e98e3b2c 547
aabce0f4
JL		 548 /* Compute the condition codes. */
549 z = (result == 0);
550 s = (result & 0x80000000);
551 cy = (result < -op1);
552 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
553 && (op0 & 0x80000000) != (result & 0x80000000));
554
555 /* Store the result and condition codes. */
556 State.regs[OP[1]] = result;
614f1c68
JL		 557 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
558 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4
JL		 559 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
560}
561
562/* mulh reg1, reg2 */
22c1c7dd 563void
e98e3b2c 564OP_E0 ()
22c1c7dd 565{
e98e3b2c 566 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
fb8eb42b 567 * (State.regs[OP[0]] & 0xffff));
22c1c7dd
JL		 568}
569
e98e3b2c
JL		 570/* mulh sign_extend(imm5), reg2
571
572 Condition codes */
22c1c7dd 573void
e98e3b2c 574OP_2E0 ()
22c1c7dd 575{
e98e3b2c
JL		 576 int value = OP[0];
577
578 value = (value << 27) >> 27;
579
580 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
22c1c7dd
JL		 581}
582
aabce0f4 583/* mulhi imm16, reg1, reg2 */
22c1c7dd 584void
e98e3b2c
JL		 585OP_6E0 ()
586{
587 int value = OP[0];
588
589 value = value & 0xffff;
590
fb8eb42b 591 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
e98e3b2c
JL		 592}
593
aabce0f4 594/* divh reg1, reg2 */
e98e3b2c
JL		 595void
596OP_40 ()
22c1c7dd 597{
aabce0f4
JL		 598 unsigned int op0, op1, result, z, s, cy, ov;
599 int temp;
600
601 /* Compute the result. */
602 temp = State.regs[OP[0]] & 0xffff;
603 temp = (temp << 16) >> 16;
604 op0 = temp;
605 op1 = State.regs[OP[1]];
606
607 if (op0 == 0xffffffff && op1 == 0x80000000)
608 {
609 result = 0x80000000;
610 ov = 1;
611 }
612 else if (op0 != 0)
613 {
614 result = op1 / op0;
615 ov = 0;
616 }
617 else
618 ov = 1;
619
620 /* Compute the condition codes. */
621 z = (result == 0);
622 s = (result & 0x80000000);
623
624 /* Store the result and condition codes. */
625 State.regs[OP[1]] = result;
614f1c68
JL		 626 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
627 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 628 | (ov ? PSW_OV : 0));
22c1c7dd
JL		 629}
630
3095b8df
JL		 631/* cmp reg, reg */
632void
633OP_1E0 ()
634{
635 unsigned int op0, op1, result, z, s, cy, ov;
636
637 /* Compute the result. */
638 op0 = State.regs[OP[0]];
639 op1 = State.regs[OP[1]];
640 result = op1 - op0;
641
642 /* Compute the condition codes. */
643 z = (result == 0);
644 s = (result & 0x80000000);
645 cy = (result < -op0);
646 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
647 && (op1 & 0x80000000) != (result & 0x80000000));
648
649 /* Set condition codes. */
614f1c68
JL		 650 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
651 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df
JL		 652 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
653}
654
655/* cmp sign_extend(imm5), reg */
656void
657OP_260 ()
658{
659 unsigned int op0, op1, result, z, s, cy, ov;
660 int temp;
661
662 /* Compute the result. */
663 temp = OP[0];
664 temp = (temp << 27) >> 27;
665 op0 = temp;
666 op1 = State.regs[OP[1]];
667 result = op1 - op0;
668
669 /* Compute the condition codes. */
670 z = (result == 0);
671 s = (result & 0x80000000);
672 cy = (result < -op0);
673 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
674 && (op1 & 0x80000000) != (result & 0x80000000));
675
676 /* Set condition codes. */
614f1c68
JL		 677 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
678 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df
JL		 679 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
680}
681
682/* setf cccc,reg2 */
683void
684OP_7E0 ()
685{
686 /* Hack alert. We turn off a bit in op0 since we really only
687 wanted 4 bits. */
688 unsigned int op0, psw, result;
689
690 op0 = OP[0] & 0xf;
614f1c68 691 psw = State.sregs[5];
3095b8df
JL		 692
693 switch (op0)
694 {
695 case 0x0:
696 result = ((psw & PSW_OV) != 0);
697 break;
698 case 0x1:
699 result = ((psw & PSW_CY) != 0);
700 break;
701 case 0x2:
702 result = ((psw & PSW_Z) != 0);
703 break;
704 case 0x3:
705 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
706 break;
707 case 0x4:
708 result = ((psw & PSW_S) != 0);
709 break;
710 case 0x5:
711 result = 1;
712 break;
713 case 0x6:
714 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
715 break;
716 case 0x7:
717 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
718 || ((psw & PSW_Z) != 0)) != 0);
719 break;
720 case 0x8:
721 result = ((psw & PSW_OV) == 0);
722 break;
723 case 0x9:
724 result = ((psw & PSW_CY) == 0);
725 break;
726 case 0xa:
727 result = ((psw & PSW_Z) == 0);
728 break;
729 case 0xb:
730 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
731 break;
732 case 0xc:
733 result = ((psw & PSW_S) == 0);
734 break;
735 case 0xd:
736 result = ((psw & PSW_SAT) != 0);
737 break;
738 case 0xe:
739 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
740 break;
741 case 0xf:
742 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
743 || ((psw & PSW_Z) != 0)) == 0);
744 break;
745 }
746
747 State.regs[OP[1]] = result;
748}
749
dca41ba7
JL		 750/* satadd reg,reg */
751void
752OP_C0 ()
753{
754 unsigned int op0, op1, result, z, s, cy, ov, sat;
755
756 /* Compute the result. */
757 op0 = State.regs[OP[0]];
758 op1 = State.regs[OP[1]];
759 result = op0 + op1;
760
761 /* Compute the condition codes. */
762 z = (result == 0);
763 s = (result & 0x80000000);
764 cy = (result < op0 || result < op1);
765 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
766 && (op0 & 0x80000000) != (result & 0x80000000));
767 sat = ov;
768
769 /* Store the result and condition codes. */
770 State.regs[OP[1]] = result;
614f1c68
JL		 771 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
772 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 773 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
774 | (sat ? PSW_SAT : 0));
775
776 /* Handle saturated results. */
777 if (sat && (op0 & 0x80000000))
778 State.regs[OP[1]] = 0x80000000;
779 else if (sat)
780 State.regs[OP[1]] = 0x7fffffff;
781}
782
783/* satadd sign_extend(imm5), reg */
784void
785OP_220 ()
786{
787 unsigned int op0, op1, result, z, s, cy, ov, sat;
788
789 int temp;
790
791 /* Compute the result. */
792 temp = (OP[0] & 0x1f);
793 temp = (temp << 27) >> 27;
794 op0 = temp;
795 op1 = State.regs[OP[1]];
796 result = op0 + op1;
797
798 /* Compute the condition codes. */
799 z = (result == 0);
800 s = (result & 0x80000000);
801 cy = (result < op0 || result < op1);
802 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
803 && (op0 & 0x80000000) != (result & 0x80000000));
804 sat = ov;
805
806 /* Store the result and condition codes. */
807 State.regs[OP[1]] = result;
614f1c68
JL		 808 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
809 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 810 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
811 | (sat ? PSW_SAT : 0));
812
813 /* Handle saturated results. */
814 if (sat && (op0 & 0x80000000))
815 State.regs[OP[1]] = 0x80000000;
816 else if (sat)
817 State.regs[OP[1]] = 0x7fffffff;
818}
819
820/* satsub reg1, reg2 */
821void
822OP_A0 ()
823{
824 unsigned int op0, op1, result, z, s, cy, ov, sat;
825
826 /* Compute the result. */
827 op0 = State.regs[OP[0]];
828 op1 = State.regs[OP[1]];
829 result = op1 - op0;
830
831 /* Compute the condition codes. */
832 z = (result == 0);
833 s = (result & 0x80000000);
834 cy = (result < -op0);
835 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
836 && (op1 & 0x80000000) != (result & 0x80000000));
837 sat = ov;
838
839 /* Store the result and condition codes. */
840 State.regs[OP[1]] = result;
614f1c68
JL		 841 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
842 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 843 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
844 | (sat ? PSW_SAT : 0));
845
846 /* Handle saturated results. */
847 if (sat && (op1 & 0x80000000))
848 State.regs[OP[1]] = 0x80000000;
849 else if (sat)
850 State.regs[OP[1]] = 0x7fffffff;
851}
852
853/* satsubi sign_extend(imm16), reg */
854void
855OP_660 ()
856{
857 unsigned int op0, op1, result, z, s, cy, ov, sat;
858 int temp;
859
860 /* Compute the result. */
861 temp = (OP[0] & 0xffff);
862 temp = (temp << 16) >> 16;
863 op0 = temp;
864 op1 = State.regs[OP[1]];
865 result = op1 - op0;
866
867 /* Compute the condition codes. */
868 z = (result == 0);
869 s = (result & 0x80000000);
870 cy = (result < -op0);
871 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
872 && (op1 & 0x80000000) != (result & 0x80000000));
873 sat = ov;
874
875 /* Store the result and condition codes. */
876 State.regs[OP[1]] = result;
614f1c68
JL		 877 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
878 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 879 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
880 | (sat ? PSW_SAT : 0));
881
882 /* Handle saturated results. */
883 if (sat && (op1 & 0x80000000))
884 State.regs[OP[1]] = 0x80000000;
885 else if (sat)
886 State.regs[OP[1]] = 0x7fffffff;
887}
888
889void
890OP_80 ()
891{
892 unsigned int op0, op1, result, z, s, cy, ov, sat;
893
894 /* Compute the result. */
895 op0 = State.regs[OP[0]];
896 op1 = State.regs[OP[1]];
897 result = op0 - op1;
898
899 /* Compute the condition codes. */
900 z = (result == 0);
901 s = (result & 0x80000000);
902 cy = (result < -op0);
903 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
904 && (op1 & 0x80000000) != (result & 0x80000000));
905 sat = ov;
906
907 /* Store the result and condition codes. */
908 State.regs[OP[1]] = result;
614f1c68
JL		 909 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
910 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 911 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
912 | (sat ? PSW_SAT : 0));
913
914 /* Handle saturated results. */
915 if (sat && (op0 & 0x80000000))
916 State.regs[OP[1]] = 0x80000000;
917 else if (sat)
918 State.regs[OP[1]] = 0x7fffffff;
919}
920
3095b8df
JL		 921/* tst reg,reg */
922void
923OP_160 ()
924{
925 unsigned int op0, op1, result, z, s, cy, ov;
926
927 /* Compute the result. */
928 op0 = State.regs[OP[0]];
929 op1 = State.regs[OP[1]];
930 result = op0 & op1;
931
932 /* Compute the condition codes. */
933 z = (result == 0);
934 s = (result & 0x80000000);
935
936 /* Store the condition codes. */
614f1c68
JL		 937 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
938 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
3095b8df
JL		 939}
940
1fe983dc 941/* mov reg, reg */
22c1c7dd
JL		 942void
943OP_0 ()
944{
1fe983dc 945 State.regs[OP[1]] = State.regs[OP[0]];
22c1c7dd
JL		 946}
947
1fe983dc 948/* mov sign_extend(imm5), reg */
22c1c7dd 949void
1fe983dc 950OP_200 ()
22c1c7dd 951{
1fe983dc
JL		 952 int value = OP[0];
953
954 value = (value << 27) >> 27;
955 State.regs[OP[1]] = value;
22c1c7dd
JL		 956}
957
1fe983dc
JL		 958/* movea sign_extend(imm16), reg, reg */
959
22c1c7dd 960void
1fe983dc 961OP_620 ()
22c1c7dd 962{
1fe983dc
JL		 963 int value = OP[0];
964
965 value = (value << 16) >> 16;
966
967 State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd
JL		 968}
969
1fe983dc 970/* movhi imm16, reg, reg */
22c1c7dd 971void
1fe983dc 972OP_640 ()
22c1c7dd 973{
1fe983dc
JL		 974 int value = OP[0];
975
976 value = (value & 0xffff) << 16;
977
978 State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd
JL		 979}
980
35404c7d 981/* sar zero_extend(imm5),reg1 */
22c1c7dd 982void
77553374 983OP_2A0 ()
22c1c7dd 984{
35404c7d 985 unsigned int op0, op1, result, z, s, cy, ov;
77553374 986
35404c7d
JL		 987 op0 = OP[0] & 0x1f;
988 op1 = State.regs[OP[1]];
989 result = (signed)op1 >> op0;
77553374 990
35404c7d
JL		 991 /* Compute the condition codes. */
992 z = (result == 0);
993 s = (result & 0x80000000);
994 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 995
35404c7d
JL		 996 /* Store the result and condition codes. */
997 State.regs[OP[1]] = result;
614f1c68
JL		 998 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
999 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d
JL		 1000 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1001}
77553374 1002
35404c7d 1003/* sar reg1, reg2 */
22c1c7dd 1004void
77553374 1005OP_A007E0 ()
22c1c7dd 1006{
35404c7d 1007 unsigned int op0, op1, result, z, s, cy, ov;
77553374 1008
35404c7d
JL		 1009 op0 = State.regs[OP[0]] & 0x1f;
1010 op1 = State.regs[OP[1]];
1011 result = (signed)op1 >> op0;
77553374 1012
35404c7d
JL		 1013 /* Compute the condition codes. */
1014 z = (result == 0);
1015 s = (result & 0x80000000);
1016 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 1017
35404c7d
JL		 1018 /* Store the result and condition codes. */
1019 State.regs[OP[1]] = result;
614f1c68
JL		 1020 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1021 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d
JL		 1022 | (cy ? PSW_CY : 0));
1023}
77553374 1024
35404c7d 1025/* shl zero_extend(imm5),reg1 */
22c1c7dd
JL		 1026void
1027OP_2C0 ()
77553374 1028{
35404c7d
JL		 1029 unsigned int op0, op1, result, z, s, cy, ov;
1030
1031 op0 = OP[0] & 0x1f;
1032 op1 = State.regs[OP[1]];
1033 result = op1 << op0;
1034
1035 /* Compute the condition codes. */
1036 z = (result == 0);
1037 s = (result & 0x80000000);
1038 cy = (op1 & (1 << (32 - op0)));
77553374 1039
35404c7d
JL		 1040 /* Store the result and condition codes. */
1041 State.regs[OP[1]] = result;
614f1c68
JL		 1042 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1043 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d
JL		 1044 | (cy ? PSW_CY : 0));
1045}
77553374 1046
35404c7d 1047/* shl reg1, reg2 */
77553374
JL		 1048void
1049OP_C007E0 ()
1050{
35404c7d 1051 unsigned int op0, op1, result, z, s, cy, ov;
77553374 1052
35404c7d
JL		 1053 op0 = State.regs[OP[0]] & 0x1f;
1054 op1 = State.regs[OP[1]];
1055 result = op1 << op0;
1056
1057 /* Compute the condition codes. */
1058 z = (result == 0);
1059 s = (result & 0x80000000);
1060 cy = (op1 & (1 << (32 - op0)));
1061
1062 /* Store the result and condition codes. */
1063 State.regs[OP[1]] = result;
614f1c68
JL		 1064 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1065 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d
JL		 1066 | (cy ? PSW_CY : 0));
1067}
77553374 1068
35404c7d 1069/* shr zero_extend(imm5),reg1 */
77553374
JL		 1070void
1071OP_280 ()
1072{
35404c7d 1073 unsigned int op0, op1, result, z, s, cy, ov;
77553374 1074
35404c7d
JL		 1075 op0 = OP[0] & 0x1f;
1076 op1 = State.regs[OP[1]];
1077 result = op1 >> op0;
77553374 1078
35404c7d
JL		 1079 /* Compute the condition codes. */
1080 z = (result == 0);
1081 s = (result & 0x80000000);
1082 cy = (op1 & (1 << (op0 - 1)));
1083
1084 /* Store the result and condition codes. */
1085 State.regs[OP[1]] = result;
614f1c68
JL		 1086 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1087 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d
JL		 1088 | (cy ? PSW_CY : 0));
1089}
1090
1091/* shr reg1, reg2 */
77553374
JL		 1092void
1093OP_8007E0 ()
1094{
35404c7d
JL		 1095 unsigned int op0, op1, result, z, s, cy, ov;
1096
1097 op0 = State.regs[OP[0]] & 0x1f;
1098 op1 = State.regs[OP[1]];
1099 result = op1 >> op0;
1100
1101 /* Compute the condition codes. */
1102 z = (result == 0);
1103 s = (result & 0x80000000);
1104 cy = (op1 & (1 << (op0 - 1)));
1105
1106 /* Store the result and condition codes. */
1107 State.regs[OP[1]] = result;
614f1c68
JL		 1108 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1109 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1110 | (cy ? PSW_CY : 0));
77553374
JL		 1111}
1112
0ef0eba5 1113/* or reg, reg */
1fe983dc
JL		 1114void
1115OP_100 ()
1116{
0ef0eba5 1117 unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc 1118
0ef0eba5
JL		 1119 /* Compute the result. */
1120 op0 = State.regs[OP[0]];
1121 op1 = State.regs[OP[1]];
1122 result = op0 | op1;
1fe983dc 1123
0ef0eba5
JL		 1124 /* Compute the condition codes. */
1125 z = (result == 0);
1126 s = (result & 0x80000000);
1127
1128 /* Store the result and condition codes. */
1129 State.regs[OP[1]] = result;
614f1c68
JL		 1130 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1131 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
0ef0eba5
JL		 1132}
1133
1134/* ori zero_extend(imm16), reg, reg */
1fe983dc
JL		 1135void
1136OP_680 ()
1137{
0ef0eba5 1138 unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc 1139
0ef0eba5
JL		 1140 op0 = OP[0] & 0xffff;
1141 op1 = State.regs[OP[1]];
1142 result = op0 | op1;
1fe983dc 1143
0ef0eba5
JL		 1144 /* Compute the condition codes. */
1145 z = (result == 0);
1146 s = (result & 0x80000000);
1fe983dc 1147
0ef0eba5
JL		 1148 /* Store the result and condition codes. */
1149 State.regs[OP[2]] = result;
614f1c68
JL		 1150 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1151 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
0ef0eba5
JL		 1152}
1153
1154/* and reg, reg */
22c1c7dd
JL		 1155void
1156OP_140 ()
1157{
0ef0eba5 1158 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 1159
0ef0eba5
JL		 1160 /* Compute the result. */
1161 op0 = State.regs[OP[0]];
1162 op1 = State.regs[OP[1]];
1163 result = op0 & op1;
1fe983dc 1164
0ef0eba5
JL		 1165 /* Compute the condition codes. */
1166 z = (result == 0);
1167 s = (result & 0x80000000);
1168
1169 /* Store the result and condition codes. */
1170 State.regs[OP[1]] = result;
614f1c68
JL		 1171 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1172 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
0ef0eba5
JL		 1173}
1174
1175/* andi zero_extend(imm16), reg, reg */
22c1c7dd 1176void
1fe983dc
JL		 1177OP_6C0 ()
1178{
0ef0eba5 1179 unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc 1180
0ef0eba5
JL		 1181 op0 = OP[0] & 0xffff;
1182 op1 = State.regs[OP[1]];
1183 result = op0 & op1;
1fe983dc 1184
0ef0eba5
JL		 1185 /* Compute the condition codes. */
1186 z = (result == 0);
1fe983dc 1187
0ef0eba5
JL		 1188 /* Store the result and condition codes. */
1189 State.regs[OP[2]] = result;
614f1c68
JL		 1190 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1191 State.sregs[5] |= (z ? PSW_Z : 0);
0ef0eba5
JL		 1192}
1193
1194/* xor reg, reg */
1fe983dc
JL		 1195void
1196OP_120 ()
22c1c7dd 1197{
0ef0eba5 1198 unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc 1199
0ef0eba5
JL		 1200 /* Compute the result. */
1201 op0 = State.regs[OP[0]];
1202 op1 = State.regs[OP[1]];
1203 result = op0 ^ op1;
1fe983dc 1204
0ef0eba5
JL		 1205 /* Compute the condition codes. */
1206 z = (result == 0);
1207 s = (result & 0x80000000);
1208
1209 /* Store the result and condition codes. */
1210 State.regs[OP[1]] = result;
614f1c68
JL		 1211 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1212 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
0ef0eba5
JL		 1213}
1214
1215/* xori zero_extend(imm16), reg, reg */
1fe983dc
JL		 1216void
1217OP_6A0 ()
1218{
0ef0eba5
JL		 1219 unsigned int op0, op1, result, z, s, cy, ov;
1220
1221 op0 = OP[0] & 0xffff;
1222 op1 = State.regs[OP[1]];
1223 result = op0 ^ op1;
1224
1225 /* Compute the condition codes. */
1226 z = (result == 0);
1227 s = (result & 0x80000000);
1228
1229 /* Store the result and condition codes. */
1230 State.regs[OP[2]] = result;
614f1c68
JL		 1231 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1232 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
0ef0eba5
JL		 1233}
1234
1235/* not reg1, reg2 */
1236void
1237OP_20 ()
1238{
1239 unsigned int op0, result, z, s, cy, ov;
1240
1241 /* Compute the result. */
1242 op0 = State.regs[OP[0]];
1243 result = ~op0;
1244
1245 /* Compute the condition codes. */
1246 z = (result == 0);
1247 s = (result & 0x80000000);
1fe983dc 1248
0ef0eba5
JL		 1249 /* Store the result and condition codes. */
1250 State.regs[OP[1]] = result;
614f1c68
JL		 1251 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1252 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
22c1c7dd
JL		 1253}
1254
28647e4c 1255/* set1 */
1fe983dc 1256void
28647e4c 1257OP_7C0 ()
1fe983dc
JL		 1258{
1259}
1260
28647e4c 1261/* not1 */
1fe983dc 1262void
28647e4c 1263OP_47C0 ()
1fe983dc
JL		 1264{
1265}
1266
28647e4c 1267/* clr1 */
1fe983dc 1268void
28647e4c
JL		 1269OP_87C0 ()
1270{
1271}
1272
1273/* tst1 */
1274void
1275OP_C7C0 ()
1fe983dc
JL		 1276{
1277}
e98e3b2c 1278
3095b8df 1279/* di */
e98e3b2c
JL		 1280void
1281OP_16007E0 ()
1282{
614f1c68 1283 State.sregs[5] |= PSW_ID;
e98e3b2c
JL		 1284}
1285
3095b8df 1286/* ei */
e98e3b2c
JL		 1287void
1288OP_16087E0 ()
1289{
614f1c68 1290 State.sregs[5] &= ~PSW_ID;
e98e3b2c
JL		 1291}
1292
1293/* halt, not supported */
1294void
1295OP_12007E0 ()
1296{
1297 abort ();
1298}
1299
1300/* reti, not supported */
1301void
1302OP_14007E0 ()
1303{
1304 abort ();
1305}
1306
1307/* trap, not supportd */
1308void
1309OP_10007E0 ()
1310{
1311 abort ();
1312}
1313
614f1c68 1314/* ldsr, reg,reg */
e98e3b2c
JL		 1315void
1316OP_2007E0 ()
1317{
614f1c68
JL		 1318 unsigned int op0;
1319
1320 op0 = State.regs[OP[0]];
1321 State.sregs[OP[1]] = op0;
e98e3b2c
JL		 1322}
1323
1324/* stsr, not supported */
1325void
1326OP_4007E0 ()
1327{
614f1c68
JL		 1328 unsigned int op0;
1329
1330 op0 = State.sregs[OP[1]];
1331 State.regs[OP[0]] = op0;
e98e3b2c
JL		 1332}
1333
GDB Binutils - Deliverables
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