[deliverable/binutils-gdb.git] / sim / v850 / simops.c

#include <signal.h>
#include "v850_sim.h"
#include "simops.h"

void
OP_220 ()
{
}

void
OP_10760 ()
{
}

void
OP_C7C0 ()
{
}

void
OP_760 ()
{
}

void
OP_580 ()
{
}

void
OP_700 ()
{
}

void
OP_581 ()
{
}

void
OP_582 ()
{
}

void
OP_583 ()
{
}

void
OP_584 ()
{
}

void
OP_585 ()
{
}

void
OP_586 ()
{
}

void
OP_587 ()
{
}

void
OP_588 ()
{
}

void
OP_589 ()
{
}

void
OP_58A ()
{
}

void
OP_58B ()
{
}

void
OP_58C ()
{
}

void
OP_400 ()
{
}

void
OP_160 ()
{
}

void
OP_58D ()
{
}

void
OP_58E ()
{
}

void
OP_58F ()
{
}

void
OP_660 ()
{
}


/* add reg, reg */
void
OP_1C0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 + op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* add sign_extend(imm5), reg */
void
OP_240 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;
  int temp;

  /* Compute the result.  */
  temp = (OP[0] & 0x1f);
  temp = (temp << 27) >> 27;
  op0 = temp;
  op1 = State.regs[OP[1]];
  result = op0 + op1;
  
  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* addi sign_extend(imm16), reg, reg */
void
OP_600 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;
  int temp;

  /* Compute the result.  */
  temp = (OP[0] & 0xffff);
  temp = (temp << 16) >> 16;
  op0 = temp;
  op1 = State.regs[OP[1]];
  result = op0 + op1;
  
  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < op0 || result < op1);
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* sub reg1, reg2 */
void
OP_1A0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op1 - op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < -op0);
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
	&& (op1 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
  State.regs[OP[1]] = State.regs[OP[0]];
}

/* subr reg1, reg2 */
void
OP_180 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 - op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (result < -op1);
  ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
	&& (op0 & 0x80000000) != (result & 0x80000000));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* mulh reg1, reg2 */
void
OP_E0 ()
{
  State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
		       * (State.regs[OP[0]] & 0xffff));
}

/* mulh sign_extend(imm5), reg2

   Condition codes */
void
OP_2E0 ()
{
  int value = OP[0];
 
  value = (value << 27) >> 27;

  State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
}

/* mulhi imm16, reg1, reg2 */
void
OP_6E0 ()
{
  int value = OP[0];
 
  value = value & 0xffff;

  State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
}

/* divh reg1, reg2 */
void
OP_40 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;
  int temp;

  /* Compute the result.  */
  temp = State.regs[OP[0]] & 0xffff;
  temp = (temp << 16) >> 16;
  op0 = temp;
  op1 = State.regs[OP[1]];

  if (op0 == 0xffffffff && op1 == 0x80000000)
    {
      result = 0x80000000;
      ov = 1;
    }
  else if (op0 != 0)
    {
      result = op1 / op0;
      ov = 0;
    }
  else
    ov = 1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (ov ? PSW_OV : 0));
}

void
OP_10720 ()
{
}

void
OP_780 ()
{
}

void
OP_720 ()
{
}

void
OP_60 ()
{
}

void
OP_87C0 ()
{
}

void
OP_300 ()
{
}

/* mov reg, reg */
void
OP_0 ()
{
  State.regs[OP[1]] = State.regs[OP[0]];
}

/* mov sign_extend(imm5), reg */
void
OP_200 ()
{
  int value = OP[0];
 
  value = (value << 27) >> 27;
  State.regs[OP[1]] = value;
}

/* movea sign_extend(imm16), reg, reg  */

void
OP_620 ()
{
  int value = OP[0];
 
  value = (value << 16) >> 16;

  State.regs[OP[2]] = State.regs[OP[1]] + value;
}

/* movhi imm16, reg, reg */
void
OP_640 ()
{
  int value = OP[0];
 
  value = (value & 0xffff) << 16; 

  State.regs[OP[2]] = State.regs[OP[1]] + value;
}

void
OP_7C0 ()
{
}

void
OP_1687E0 ()
{
}

void
OP_1E0 ()
{
}

void
OP_A0 ()
{
}

void
OP_260 ()
{
}

void
OP_740 ()
{
}

void
OP_80 ()
{
}

/* sar zero_extend(imm5),reg1 */
void
OP_2A0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0x1f;
  op1 = State.regs[OP[1]];
  result = (signed)op1 >> op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (op0 - 1)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
}

/* sar reg1, reg2 */
void
OP_A007E0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = State.regs[OP[0]] & 0x1f;
  op1 = State.regs[OP[1]];
  result = (signed)op1 >> op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (op0 - 1)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0));
}

/* shl zero_extend(imm5),reg1 */
void
OP_2C0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0x1f;
  op1 = State.regs[OP[1]];
  result = op1 << op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (32 - op0)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0));
}

/* shl reg1, reg2 */
void
OP_C007E0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = State.regs[OP[0]] & 0x1f;
  op1 = State.regs[OP[1]];
  result = op1 << op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (32 - op0)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0));
}

/* shr zero_extend(imm5),reg1 */
void
OP_280 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0x1f;
  op1 = State.regs[OP[1]];
  result = op1 >> op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (op0 - 1)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0));
}

/* shr reg1, reg2 */
void
OP_8007E0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = State.regs[OP[0]] & 0x1f;
  op1 = State.regs[OP[1]];
  result = op1 >> op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  cy = (op1 & (1 << (op0 - 1)));

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
		| (cy ? PSW_CY : 0));
}

void
OP_500 ()
{
}

void
OP_47C0 ()
{
}

void
OP_7E0 ()
{
}

/* or reg, reg */
void
OP_100 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 | op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* ori zero_extend(imm16), reg, reg */
void
OP_680 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 | op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* and reg, reg */
void
OP_140 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 & op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* andi zero_extend(imm16), reg, reg */
void
OP_6C0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 & op1;

  /* Compute the condition codes.  */
  z = (result == 0);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= (z ? PSW_Z : 0);
}

/* xor reg, reg */
void
OP_120 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  op1 = State.regs[OP[1]];
  result = op0 ^ op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* xori zero_extend(imm16), reg, reg */
void
OP_6A0 ()
{
  unsigned int op0, op1, result, z, s, cy, ov;

  op0 = OP[0] & 0xffff;
  op1 = State.regs[OP[1]];
  result = op0 ^ op1;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[2]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

/* not reg1, reg2 */
void
OP_20 ()
{
  unsigned int op0, result, z, s, cy, ov;

  /* Compute the result.  */
  op0 = State.regs[OP[0]];
  result = ~op0;

  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);

  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
  State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
}

void
OP_C0 ()
{
}

void
OP_480 ()
{
}

void
OP_380 ()
{
}

void
OP_501 ()
{
}

/* di, not supported */
void
OP_16007E0 ()
{
  abort ();
}

/* ei, not supported */
void
OP_16087E0 ()
{
  abort ();
}

/* halt, not supported */
void
OP_12007E0 ()
{
  abort ();
}

/* reti, not supported */
void
OP_14007E0 ()
{
  abort ();
}

/* trap, not supportd */
void
OP_10007E0 ()
{
  abort ();
}

/* ldsr, not supported */
void
OP_2007E0 ()
{
  abort ();
}

/* stsr, not supported */
void
OP_4007E0 ()
{
  abort ();
}
Commit	Line	Data
22c1c7dd JL	1	#include <signal.h>
	2	#include "v850_sim.h"
	3	#include "simops.h"
	4
22c1c7dd JL	5	void
	6	OP_220 ()
	7	{
	8	}
	9
	10	void
	11	OP_10760 ()
	12	{
	13	}
	14
	15	void
	16	OP_C7C0 ()
	17	{
	18	}
	19
	20	void
	21	OP_760 ()
	22	{
	23	}
	24
22c1c7dd JL	25	void
	26	OP_580 ()
	27	{
	28	}
	29
	30	void
	31	OP_700 ()
	32	{
	33	}
	34
	35	void
	36	OP_581 ()
	37	{
	38	}
	39
22c1c7dd JL	40	void
	41	OP_582 ()
	42	{
	43	}
	44
	45	void
	46	OP_583 ()
	47	{
	48	}
	49
	50	void
	51	OP_584 ()
	52	{
	53	}
	54
	55	void
	56	OP_585 ()
	57	{
	58	}
	59
	60	void
	61	OP_586 ()
	62	{
	63	}
	64
	65	void
	66	OP_587 ()
	67	{
	68	}
	69
	70	void
	71	OP_588 ()
	72	{
	73	}
	74
	75	void
	76	OP_589 ()
	77	{
	78	}
	79
	80	void
	81	OP_58A ()
	82	{
	83	}
	84
	85	void
	86	OP_58B ()
	87	{
	88	}
	89
	90	void
	91	OP_58C ()
	92	{
	93	}
	94
	95	void
	96	OP_400 ()
	97	{
	98	}
	99
22c1c7dd JL	100	void
	101	OP_160 ()
	102	{
	103	}
	104
	105	void
	106	OP_58D ()
	107	{
	108	}
	109
	110	void
	111	OP_58E ()
	112	{
	113	}
	114
	115	void
	116	OP_58F ()
	117	{
	118	}
	119
	120	void
	121	OP_660 ()
	122	{
	123	}
	124
22c1c7dd	125
0ef0eba5	126	/* add reg, reg */
22c1c7dd	127	void
1fe983dc	128	OP_1C0 ()
22c1c7dd	129	{
0ef0eba5	130	unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd	131
0ef0eba5 JL	132	/* Compute the result. */
	133	op0 = State.regs[OP[0]];
	134	op1 = State.regs[OP[1]];
	135	result = op0 + op1;
1fe983dc	136
0ef0eba5 JL	137	/* Compute the condition codes. */
	138	z = (result == 0);
	139	s = (result & 0x80000000);
	140	cy = (result < op0 \|\| result < op1);
	141	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	142	&& (op0 & 0x80000000) != (result & 0x80000000));
	143
	144	/* Store the result and condition codes. */
	145	State.regs[OP[1]] = result;
	146	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	147	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	148	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	149	}
	150
	151	/* add sign_extend(imm5), reg */
22c1c7dd	152	void
1fe983dc	153	OP_240 ()
22c1c7dd	154	{
0ef0eba5 JL	155	unsigned int op0, op1, result, z, s, cy, ov;
0ef0eba5 JL	156	int temp;
1fe983dc	157
0ef0eba5 JL	158	/* Compute the result. */
	159	temp = (OP[0] & 0x1f);
	160	temp = (temp << 27) >> 27;
	161	op0 = temp;
	162	op1 = State.regs[OP[1]];
	163	result = op0 + op1;
	164
	165	/* Compute the condition codes. */
	166	z = (result == 0);
	167	s = (result & 0x80000000);
	168	cy = (result < op0 \|\| result < op1);
	169	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	170	&& (op0 & 0x80000000) != (result & 0x80000000));
22c1c7dd	171
0ef0eba5 JL	172	/* Store the result and condition codes. */
	173	State.regs[OP[1]] = result;
	174	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	175	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	176	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	177	}
1fe983dc	178
0ef0eba5	179	/* addi sign_extend(imm16), reg, reg */
22c1c7dd	180	void
1fe983dc	181	OP_600 ()
22c1c7dd	182	{
0ef0eba5 JL	183	unsigned int op0, op1, result, z, s, cy, ov;
	184	int temp;
	185
	186	/* Compute the result. */
	187	temp = (OP[0] & 0xffff);
	188	temp = (temp << 16) >> 16;
	189	op0 = temp;
	190	op1 = State.regs[OP[1]];
	191	result = op0 + op1;
	192
	193	/* Compute the condition codes. */
	194	z = (result == 0);
	195	s = (result & 0x80000000);
	196	cy = (result < op0 \|\| result < op1);
	197	ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
	198	&& (op0 & 0x80000000) != (result & 0x80000000));
	199
	200	/* Store the result and condition codes. */
	201	State.regs[OP[2]] = result;
	202	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	203	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	204	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
22c1c7dd JL	205	}
22c1c7dd JL	206
aabce0f4	207	/* sub reg1, reg2 */
22c1c7dd	208	void
1fe983dc	209	OP_1A0 ()
22c1c7dd	210	{
aabce0f4 JL	211	unsigned int op0, op1, result, z, s, cy, ov;
	212
	213	/* Compute the result. */
	214	op0 = State.regs[OP[0]];
	215	op1 = State.regs[OP[1]];
	216	result = op1 - op0;
22c1c7dd	217
aabce0f4 JL	218	/* Compute the condition codes. */
	219	z = (result == 0);
	220	s = (result & 0x80000000);
	221	cy = (result < -op0);
	222	ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
	223	&& (op1 & 0x80000000) != (result & 0x80000000));
1fe983dc	224
aabce0f4 JL	225	/* Store the result and condition codes. */
	226	State.regs[OP[1]] = result;
	227	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	228	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	229	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	230	State.regs[OP[1]] = State.regs[OP[0]];
	231	}
	232
	233	/* subr reg1, reg2 */
22c1c7dd	234	void
1fe983dc	235	OP_180 ()
22c1c7dd	236	{
aabce0f4	237	unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd	238
aabce0f4 JL	239	/* Compute the result. */
	240	op0 = State.regs[OP[0]];
	241	op1 = State.regs[OP[1]];
	242	result = op0 - op1;
e98e3b2c	243
aabce0f4 JL	244	/* Compute the condition codes. */
	245	z = (result == 0);
	246	s = (result & 0x80000000);
	247	cy = (result < -op1);
	248	ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
	249	&& (op0 & 0x80000000) != (result & 0x80000000));
	250
	251	/* Store the result and condition codes. */
	252	State.regs[OP[1]] = result;
	253	State.psw &= ~(PSW_Z \| PSW_S \| PSW_CY \| PSW_OV);
	254	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	255	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	256	}
	257
	258	/* mulh reg1, reg2 */
22c1c7dd	259	void
e98e3b2c	260	OP_E0 ()
22c1c7dd	261	{
e98e3b2c	262	State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
fb8eb42b	263	* (State.regs[OP[0]] & 0xffff));
22c1c7dd JL	264	}
22c1c7dd JL	265
e98e3b2c JL	266	/* mulh sign_extend(imm5), reg2
	267
	268	Condition codes */
22c1c7dd	269	void
e98e3b2c	270	OP_2E0 ()
22c1c7dd	271	{
e98e3b2c JL	272	int value = OP[0];
	273
	274	value = (value << 27) >> 27;
	275
	276	State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
22c1c7dd JL	277	}
22c1c7dd JL	278
aabce0f4	279	/* mulhi imm16, reg1, reg2 */
22c1c7dd	280	void
e98e3b2c JL	281	OP_6E0 ()
	282	{
	283	int value = OP[0];
	284
	285	value = value & 0xffff;
	286
fb8eb42b	287	State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
e98e3b2c JL	288	}
e98e3b2c JL	289
aabce0f4	290	/* divh reg1, reg2 */
e98e3b2c JL	291	void
e98e3b2c JL	292	OP_40 ()
22c1c7dd	293	{
aabce0f4 JL	294	unsigned int op0, op1, result, z, s, cy, ov;
	295	int temp;
	296
	297	/* Compute the result. */
	298	temp = State.regs[OP[0]] & 0xffff;
	299	temp = (temp << 16) >> 16;
	300	op0 = temp;
	301	op1 = State.regs[OP[1]];
	302
	303	if (op0 == 0xffffffff && op1 == 0x80000000)
	304	{
	305	result = 0x80000000;
	306	ov = 1;
	307	}
	308	else if (op0 != 0)
	309	{
	310	result = op1 / op0;
	311	ov = 0;
	312	}
	313	else
	314	ov = 1;
	315
	316	/* Compute the condition codes. */
	317	z = (result == 0);
	318	s = (result & 0x80000000);
	319
	320	/* Store the result and condition codes. */
	321	State.regs[OP[1]] = result;
	322	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	323	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	324	\| (ov ? PSW_OV : 0));
22c1c7dd JL	325	}
22c1c7dd JL	326
22c1c7dd	327	void
1fe983dc	328	OP_10720 ()
22c1c7dd JL	329	{
	330	}
	331
	332	void
1fe983dc	333	OP_780 ()
22c1c7dd JL	334	{
	335	}
	336
	337	void
	338	OP_720 ()
	339	{
	340	}
	341
	342	void
	343	OP_60 ()
	344	{
	345	}
	346
22c1c7dd JL	347	void
	348	OP_87C0 ()
	349	{
	350	}
	351
22c1c7dd JL	352	void
	353	OP_300 ()
	354	{
	355	}
	356
1fe983dc	357	/* mov reg, reg */
22c1c7dd JL	358	void
	359	OP_0 ()
	360	{
1fe983dc	361	State.regs[OP[1]] = State.regs[OP[0]];
22c1c7dd JL	362	}
22c1c7dd JL	363
1fe983dc	364	/* mov sign_extend(imm5), reg */
22c1c7dd	365	void
1fe983dc	366	OP_200 ()
22c1c7dd	367	{
1fe983dc JL	368	int value = OP[0];
	369
	370	value = (value << 27) >> 27;
	371	State.regs[OP[1]] = value;
22c1c7dd JL	372	}
22c1c7dd JL	373
1fe983dc JL	374	/* movea sign_extend(imm16), reg, reg */
1fe983dc JL	375
22c1c7dd	376	void
1fe983dc	377	OP_620 ()
22c1c7dd	378	{
1fe983dc JL	379	int value = OP[0];
	380
	381	value = (value << 16) >> 16;
	382
	383	State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd JL	384	}
22c1c7dd JL	385
1fe983dc	386	/* movhi imm16, reg, reg */
22c1c7dd	387	void
1fe983dc	388	OP_640 ()
22c1c7dd	389	{
1fe983dc JL	390	int value = OP[0];
	391
	392	value = (value & 0xffff) << 16;
	393
	394	State.regs[OP[2]] = State.regs[OP[1]] + value;
22c1c7dd JL	395	}
	396
	397	void
1fe983dc	398	OP_7C0 ()
22c1c7dd JL	399	{
	400	}
	401
	402	void
1fe983dc	403	OP_1687E0 ()
22c1c7dd JL	404	{
	405	}
	406
	407	void
	408	OP_1E0 ()
	409	{
	410	}
	411
	412	void
	413	OP_A0 ()
	414	{
	415	}
	416
	417	void
	418	OP_260 ()
	419	{
	420	}
	421
22c1c7dd JL	422	void
	423	OP_740 ()
	424	{
	425	}
	426
	427	void
	428	OP_80 ()
	429	{
	430	}
	431
35404c7d	432	/* sar zero_extend(imm5),reg1 */
22c1c7dd	433	void
77553374	434	OP_2A0 ()
22c1c7dd	435	{
35404c7d	436	unsigned int op0, op1, result, z, s, cy, ov;
77553374	437
35404c7d JL	438	op0 = OP[0] & 0x1f;
	439	op1 = State.regs[OP[1]];
	440	result = (signed)op1 >> op0;
77553374	441
35404c7d JL	442	/* Compute the condition codes. */
	443	z = (result == 0);
	444	s = (result & 0x80000000);
	445	cy = (op1 & (1 << (op0 - 1)));
22c1c7dd	446
35404c7d JL	447	/* Store the result and condition codes. */
	448	State.regs[OP[1]] = result;
	449	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	450	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	451	\| (cy ? PSW_CY : 0) \| (ov ? PSW_OV : 0));
	452	}
77553374	453
35404c7d	454	/* sar reg1, reg2 */
22c1c7dd	455	void
77553374	456	OP_A007E0 ()
22c1c7dd	457	{
35404c7d	458	unsigned int op0, op1, result, z, s, cy, ov;
77553374	459
35404c7d JL	460	op0 = State.regs[OP[0]] & 0x1f;
	461	op1 = State.regs[OP[1]];
	462	result = (signed)op1 >> op0;
77553374	463
35404c7d JL	464	/* Compute the condition codes. */
	465	z = (result == 0);
	466	s = (result & 0x80000000);
	467	cy = (op1 & (1 << (op0 - 1)));
22c1c7dd	468
35404c7d JL	469	/* Store the result and condition codes. */
	470	State.regs[OP[1]] = result;
	471	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	472	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	473	\| (cy ? PSW_CY : 0));
	474	}
77553374	475
35404c7d	476	/* shl zero_extend(imm5),reg1 */
22c1c7dd JL	477	void
22c1c7dd JL	478	OP_2C0 ()
77553374	479	{
35404c7d JL	480	unsigned int op0, op1, result, z, s, cy, ov;
	481
	482	op0 = OP[0] & 0x1f;
	483	op1 = State.regs[OP[1]];
	484	result = op1 << op0;
	485
	486	/* Compute the condition codes. */
	487	z = (result == 0);
	488	s = (result & 0x80000000);
	489	cy = (op1 & (1 << (32 - op0)));
77553374	490
35404c7d JL	491	/* Store the result and condition codes. */
	492	State.regs[OP[1]] = result;
	493	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	494	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	495	\| (cy ? PSW_CY : 0));
	496	}
77553374	497
35404c7d	498	/* shl reg1, reg2 */
77553374 JL	499	void
	500	OP_C007E0 ()
	501	{
35404c7d	502	unsigned int op0, op1, result, z, s, cy, ov;
77553374	503
35404c7d JL	504	op0 = State.regs[OP[0]] & 0x1f;
	505	op1 = State.regs[OP[1]];
	506	result = op1 << op0;
	507
	508	/* Compute the condition codes. */
	509	z = (result == 0);
	510	s = (result & 0x80000000);
	511	cy = (op1 & (1 << (32 - op0)));
	512
	513	/* Store the result and condition codes. */
	514	State.regs[OP[1]] = result;
	515	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	516	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	517	\| (cy ? PSW_CY : 0));
	518	}
77553374	519
35404c7d	520	/* shr zero_extend(imm5),reg1 */
77553374 JL	521	void
	522	OP_280 ()
	523	{
35404c7d	524	unsigned int op0, op1, result, z, s, cy, ov;
77553374	525
35404c7d JL	526	op0 = OP[0] & 0x1f;
	527	op1 = State.regs[OP[1]];
	528	result = op1 >> op0;
77553374	529
35404c7d JL	530	/* Compute the condition codes. */
	531	z = (result == 0);
	532	s = (result & 0x80000000);
	533	cy = (op1 & (1 << (op0 - 1)));
	534
	535	/* Store the result and condition codes. */
	536	State.regs[OP[1]] = result;
	537	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	538	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	539	\| (cy ? PSW_CY : 0));
	540	}
	541
	542	/* shr reg1, reg2 */
77553374 JL	543	void
	544	OP_8007E0 ()
	545	{
35404c7d JL	546	unsigned int op0, op1, result, z, s, cy, ov;
	547
	548	op0 = State.regs[OP[0]] & 0x1f;
	549	op1 = State.regs[OP[1]];
	550	result = op1 >> op0;
	551
	552	/* Compute the condition codes. */
	553	z = (result == 0);
	554	s = (result & 0x80000000);
	555	cy = (op1 & (1 << (op0 - 1)));
	556
	557	/* Store the result and condition codes. */
	558	State.regs[OP[1]] = result;
	559	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV \| PSW_CY);
	560	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0)
	561	\| (cy ? PSW_CY : 0));
77553374 JL	562	}
	563
	564	void
	565	OP_500 ()
22c1c7dd JL	566	{
	567	}
	568
22c1c7dd JL	569	void
	570	OP_47C0 ()
	571	{
	572	}
	573
22c1c7dd JL	574	void
	575	OP_7E0 ()
	576	{
	577	}
	578
0ef0eba5	579	/* or reg, reg */
1fe983dc JL	580	void
	581	OP_100 ()
	582	{
0ef0eba5	583	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	584
0ef0eba5 JL	585	/* Compute the result. */
	586	op0 = State.regs[OP[0]];
	587	op1 = State.regs[OP[1]];
	588	result = op0 \| op1;
1fe983dc	589
0ef0eba5 JL	590	/* Compute the condition codes. */
	591	z = (result == 0);
	592	s = (result & 0x80000000);
	593
	594	/* Store the result and condition codes. */
	595	State.regs[OP[1]] = result;
	596	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	597	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	598	}
	599
	600	/* ori zero_extend(imm16), reg, reg */
1fe983dc JL	601	void
	602	OP_680 ()
	603	{
0ef0eba5	604	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	605
0ef0eba5 JL	606	op0 = OP[0] & 0xffff;
	607	op1 = State.regs[OP[1]];
	608	result = op0 \| op1;
1fe983dc	609
0ef0eba5 JL	610	/* Compute the condition codes. */
	611	z = (result == 0);
	612	s = (result & 0x80000000);
1fe983dc	613
0ef0eba5 JL	614	/* Store the result and condition codes. */
	615	State.regs[OP[2]] = result;
	616	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	617	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
0ef0eba5 JL	618	}
	619
	620	/* and reg, reg */
22c1c7dd JL	621	void
	622	OP_140 ()
	623	{
0ef0eba5	624	unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd	625
0ef0eba5 JL	626	/* Compute the result. */
	627	op0 = State.regs[OP[0]];
	628	op1 = State.regs[OP[1]];
	629	result = op0 & op1;
1fe983dc	630
0ef0eba5 JL	631	/* Compute the condition codes. */
	632	z = (result == 0);
	633	s = (result & 0x80000000);
	634
	635	/* Store the result and condition codes. */
	636	State.regs[OP[1]] = result;
	637	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	638	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	639	}
	640
	641	/* andi zero_extend(imm16), reg, reg */
22c1c7dd	642	void
1fe983dc JL	643	OP_6C0 ()
1fe983dc JL	644	{
0ef0eba5	645	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	646
0ef0eba5 JL	647	op0 = OP[0] & 0xffff;
	648	op1 = State.regs[OP[1]];
	649	result = op0 & op1;
1fe983dc	650
0ef0eba5 JL	651	/* Compute the condition codes. */
0ef0eba5 JL	652	z = (result == 0);
1fe983dc	653
0ef0eba5 JL	654	/* Store the result and condition codes. */
	655	State.regs[OP[2]] = result;
	656	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	657	State.psw \|= (z ? PSW_Z : 0);
	658	}
	659
	660	/* xor reg, reg */
1fe983dc JL	661	void
1fe983dc JL	662	OP_120 ()
22c1c7dd	663	{
0ef0eba5	664	unsigned int op0, op1, result, z, s, cy, ov;
1fe983dc	665
0ef0eba5 JL	666	/* Compute the result. */
	667	op0 = State.regs[OP[0]];
	668	op1 = State.regs[OP[1]];
	669	result = op0 ^ op1;
1fe983dc	670
0ef0eba5 JL	671	/* Compute the condition codes. */
	672	z = (result == 0);
	673	s = (result & 0x80000000);
	674
	675	/* Store the result and condition codes. */
	676	State.regs[OP[1]] = result;
	677	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	678	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
	679	}
	680
	681	/* xori zero_extend(imm16), reg, reg */
1fe983dc JL	682	void
	683	OP_6A0 ()
	684	{
0ef0eba5 JL	685	unsigned int op0, op1, result, z, s, cy, ov;
	686
	687	op0 = OP[0] & 0xffff;
	688	op1 = State.regs[OP[1]];
	689	result = op0 ^ op1;
	690
	691	/* Compute the condition codes. */
	692	z = (result == 0);
	693	s = (result & 0x80000000);
	694
	695	/* Store the result and condition codes. */
	696	State.regs[OP[2]] = result;
	697	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	698	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
0ef0eba5 JL	699	}
	700
	701	/* not reg1, reg2 */
	702	void
	703	OP_20 ()
	704	{
	705	unsigned int op0, result, z, s, cy, ov;
	706
	707	/* Compute the result. */
	708	op0 = State.regs[OP[0]];
	709	result = ~op0;
	710
	711	/* Compute the condition codes. */
	712	z = (result == 0);
	713	s = (result & 0x80000000);
1fe983dc	714
0ef0eba5 JL	715	/* Store the result and condition codes. */
	716	State.regs[OP[1]] = result;
	717	State.psw &= ~(PSW_Z \| PSW_S \| PSW_OV);
	718	State.psw \|= ((z ? PSW_Z : 0) \| (s ? PSW_S : 0));
22c1c7dd JL	719	}
	720
	721	void
	722	OP_C0 ()
	723	{
	724	}
	725
1fe983dc JL	726	void
	727	OP_480 ()
	728	{
	729	}
	730
	731	void
	732	OP_380 ()
	733	{
	734	}
	735
	736	void
	737	OP_501 ()
	738	{
	739	}
e98e3b2c JL	740
	741	/* di, not supported */
	742	void
	743	OP_16007E0 ()
	744	{
	745	abort ();
	746	}
	747
	748	/* ei, not supported */
	749	void
	750	OP_16087E0 ()
	751	{
	752	abort ();
	753	}
	754
	755	/* halt, not supported */
	756	void
	757	OP_12007E0 ()
	758	{
	759	abort ();
	760	}
	761
	762	/* reti, not supported */
	763	void
	764	OP_14007E0 ()
	765	{
	766	abort ();
	767	}
	768
	769	/* trap, not supportd */
	770	void
	771	OP_10007E0 ()
	772	{
	773	abort ();
	774	}
	775
	776	/* ldsr, not supported */
	777	void
	778	OP_2007E0 ()
	779	{
	780	abort ();
	781	}
	782
	783	/* stsr, not supported */
	784	void
	785	OP_4007E0 ()
	786	{
	787	abort ();
	788	}
	789