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Store bfd pointer in a global variable
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
CommitLineData
22c1c7dd
JL		 1#include <signal.h>
2#include "v850_sim.h"
3#include "simops.h"
9909e232 4#include "sys/syscall.h"
22c1c7dd 5
ead4a3f1
MM		 6enum op_types {
7 OP_UNKNOWN,
8 OP_NONE,
9 OP_TRAP,
10 OP_REG,
11 OP_REG_REG,
12 OP_REG_REG_CMP,
13 OP_REG_REG_MOVE,
14 OP_IMM_REG,
15 OP_IMM_REG_CMP,
16 OP_IMM_REG_MOVE,
17 OP_COND_BR,
18 OP_LOAD16,
19 OP_STORE16,
20 OP_LOAD32,
21 OP_STORE32,
22 OP_JUMP,
23 OP_IMM_REG_REG,
24 OP_UIMM_REG_REG,
25 OP_BIT,
26 OP_EX1,
27 OP_EX2,
28 OP_LDSR,
29 OP_STSR
30};
31
32#ifdef DEBUG
33static void trace_input PARAMS ((char *name, enum op_types type, int size));
34static void trace_output PARAMS ((enum op_types result));
35
36#ifndef SIZE_INSTRUCTION
37#define SIZE_INSTRUCTION 6
38#endif
39
40#ifndef SIZE_OPERANDS
41#define SIZE_OPERANDS 16
42#endif
43
44#ifndef SIZE_VALUES
45#define SIZE_VALUES 11
46#endif
47
48static void
49trace_input (name, type, size)
50 char *name;
51 enum op_types type;
52 int size;
53{
54 char buf[80];
55 uint32 values[3];
56 int num_values, i;
57 char *cond;
58
59 if ((v850_debug & DEBUG_TRACE) == 0)
60 return;
61
62 (*v850_callback->printf_filtered) (v850_callback,
63 "0x%.8x: %-*s",
64 (unsigned)PC,
65 SIZE_INSTRUCTION, name);
66
67 switch (type)
68 {
69 default:
70 case OP_UNKNOWN:
71 case OP_NONE:
72 strcpy (buf, "unknown");
73 break;
74
75 case OP_TRAP:
76 sprintf (buf, "%d", OP[0]);
77 break;
78
79 case OP_REG:
80 sprintf (buf, "r%d", OP[0]);
81 break;
82
83 case OP_REG_REG:
84 case OP_REG_REG_CMP:
85 case OP_REG_REG_MOVE:
86 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
87 break;
88
89 case OP_IMM_REG:
90 case OP_IMM_REG_CMP:
91 case OP_IMM_REG_MOVE:
92 sprintf (buf, "%d,r%d", OP[1], OP[0]);
93 break;
94
95 case OP_COND_BR:
96 sprintf (buf, "%d", SEXT9 (OP[0]));
97 break;
98
99 case OP_LOAD16:
100 sprintf (buf, "%d[r30],r%d", SEXT7 (OP[1]) * size, OP[0]);
101 break;
102
103 case OP_STORE16:
104 sprintf (buf, "r%d,%d[r30]", OP[0], SEXT7 (OP[1]) * size);
105 break;
106
107 case OP_LOAD32:
108 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]), OP[0], OP[1]);
109 break;
110
111 case OP_STORE32:
112 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2]), OP[0]);
113 break;
114
115 case OP_JUMP:
116 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
117 break;
118
119 case OP_IMM_REG_REG:
120 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
121 break;
122
123 case OP_UIMM_REG_REG:
124 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
125 break;
126
127 case OP_BIT:
128 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
129 break;
130
131 case OP_EX1:
132 switch (OP[0] & 0xf)
133 {
134 default: cond = "?"; break;
135 case 0x0: cond = "v"; break;
136 case 0x1: cond = "c"; break;
137 case 0x2: cond = "z"; break;
138 case 0x3: cond = "nh"; break;
139 case 0x4: cond = "s"; break;
140 case 0x5: cond = "t"; break;
141 case 0x6: cond = "lt"; break;
142 case 0x7: cond = "le"; break;
143 case 0x8: cond = "nv"; break;
144 case 0x9: cond = "nc"; break;
145 case 0xa: cond = "nz"; break;
146 case 0xb: cond = "h"; break;
147 case 0xc: cond = "ns"; break;
148 case 0xd: cond = "sa"; break;
149 case 0xe: cond = "ge"; break;
150 case 0xf: cond = "gt"; break;
151 }
152
153 sprintf (buf, "%s,r%d", cond, OP[1]);
154 break;
155
156 case OP_EX2:
157 strcpy (buf, "EX2");
158 break;
159
160 case OP_LDSR:
161 case OP_STSR:
162 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
163 break;
164 }
165
166 if ((v850_debug & DEBUG_VALUES) == 0)
167 {
168 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
169 }
170 else
171 {
172 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
173 switch (type)
174 {
175 default:
176 case OP_UNKNOWN:
177 case OP_NONE:
178 case OP_TRAP:
179 num_values = 0;
180 break;
181
182 case OP_REG:
183 case OP_REG_REG_MOVE:
184 values[0] = State.regs[OP[0]];
185 num_values = 1;
186 break;
187
188 case OP_REG_REG:
189 case OP_REG_REG_CMP:
190 values[0] = State.regs[OP[1]];
191 values[1] = State.regs[OP[0]];
192 num_values = 2;
193 break;
194
195 case OP_IMM_REG:
196 case OP_IMM_REG_CMP:
197 values[0] = SEXT5 (OP[0]);
198 values[1] = OP[1];
199 num_values = 2;
200 break;
201
202 case OP_IMM_REG_MOVE:
203 values[0] = SEXT5 (OP[0]);
204 num_values = 1;
205 break;
206
207 case OP_COND_BR:
208 values[0] = State.pc;
209 values[1] = SEXT9 (OP[0]);
210 values[2] = State.sregs[5];
211 num_values = 3;
212 break;
213
214 case OP_LOAD16:
215 values[0] = SEXT7 (OP[1]) * size;
216 values[1] = State.regs[30];
217 num_values = 2;
218 break;
219
220 case OP_STORE16:
221 values[0] = State.regs[OP[0]];
222 values[1] = SEXT7 (OP[1]) * size;
223 values[2] = State.regs[30];
224 num_values = 3;
225 break;
226
227 case OP_LOAD32:
228 values[0] = SEXT16 (OP[2]);
229 values[1] = State.regs[OP[0]];
230 num_values = 2;
231 break;
232
233 case OP_STORE32:
234 values[0] = State.regs[OP[1]];
235 values[1] = SEXT16 (OP[2]);
236 values[2] = State.regs[OP[0]];
237 num_values = 3;
238 break;
239
240 case OP_JUMP:
241 values[0] = SEXT22 (OP[0]);
242 values[1] = State.pc;
243 num_values = 2;
244 break;
245
246 case OP_IMM_REG_REG:
247 values[0] = SEXT16 (OP[0]) << size;
248 values[1] = State.regs[OP[1]];
249 num_values = 2;
250 break;
251
252 case OP_UIMM_REG_REG:
253 values[0] = (OP[0] & 0xffff) << size;
254 values[1] = State.regs[OP[1]];
255 num_values = 2;
256 break;
257
258 case OP_BIT:
259 num_values = 0;
260 break;
261
262 case OP_EX1:
263 values[0] = State.sregs[5];
264 num_values = 1;
265 break;
266
267 case OP_EX2:
268 num_values = 0;
269 break;
270
271 case OP_LDSR:
272 values[0] = State.regs[OP[0]];
273 num_values = 1;
274 break;
275
276 case OP_STSR:
277 values[0] = State.sregs[OP[1]];
278 num_values = 1;
279 }
280
281 for (i = 0; i < num_values; i++)
282 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
283
284 while (i++ < 3)
285 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
286 }
287}
288
289static void
290trace_output (result)
291 enum op_types result;
292{
293 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
294 {
295 switch (result)
296 {
297 default:
298 case OP_UNKNOWN:
299 case OP_NONE:
300 case OP_TRAP:
301 case OP_REG:
302 case OP_REG_REG_CMP:
303 case OP_IMM_REG_CMP:
304 case OP_COND_BR:
305 case OP_STORE16:
306 case OP_STORE32:
307 case OP_BIT:
308 case OP_EX2:
309 break;
310
311 case OP_LOAD16:
312 case OP_STSR:
313 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
314 (unsigned long)State.regs[OP[0]]);
315 break;
316
317 case OP_REG_REG:
318 case OP_REG_REG_MOVE:
319 case OP_IMM_REG:
320 case OP_IMM_REG_MOVE:
321 case OP_LOAD32:
322 case OP_EX1:
323 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
324 (unsigned long)State.regs[OP[1]]);
325 break;
326
327 case OP_IMM_REG_REG:
328 case OP_UIMM_REG_REG:
329 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
330 (unsigned long)State.regs[OP[2]]);
331 break;
332
333 case OP_JUMP:
334 if (OP[1] != 0)
335 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
336 (unsigned long)State.regs[OP[1]]);
337 break;
338
339 case OP_LDSR:
340 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
341 (unsigned long)State.sregs[OP[1]]);
342 break;
343 }
344
345 (*v850_callback->printf_filtered) (v850_callback, "\n");
346 }
347}
348
349#else
350#define trace_input(NAME, IN1, IN2, IN3)
351#define trace_output(RESULT)
352#endif
353
354\f
28647e4c 355/* sld.b */
22c1c7dd 356void
28647e4c 357OP_300 ()
22c1c7dd 358{
9fca2fd3 359 unsigned int op2;
3cb6bf78
JL		 360 int result, temp;
361
ead4a3f1 362 trace_input ("sld.b", OP_LOAD16, 1);
3cb6bf78 363 temp = OP[1];
ead4a3f1 364 temp = SEXT7 (temp);
3cb6bf78
JL		 365 op2 = temp;
366 result = get_byte (State.mem + State.regs[30] + op2);
ead4a3f1
MM		 367 State.regs[OP[0]] = SEXT8 (result);
368 trace_output (OP_LOAD16);
22c1c7dd
JL		 369}
370
28647e4c 371/* sld.h */
22c1c7dd 372void
28647e4c
JL		 373OP_400 ()
374{
9fca2fd3 375 unsigned int op2;
3cb6bf78
JL		 376 int result, temp;
377
ead4a3f1 378 trace_input ("sld.h", OP_LOAD16, 2);
3cb6bf78 379 temp = OP[1];
ead4a3f1 380 temp = SEXT7 (temp);
3cb6bf78
JL		 381 op2 = temp << 1;
382 result = get_half (State.mem + State.regs[30] + op2);
ead4a3f1
MM		 383 State.regs[OP[0]] = SEXT16 (result);
384 trace_output (OP_LOAD16);
28647e4c
JL		 385}
386
387/* sld.w */
388void
389OP_500 ()
22c1c7dd 390{
9fca2fd3 391 unsigned int op2;
3cb6bf78
JL		 392 int result, temp;
393
ead4a3f1 394 trace_input ("sld.w", OP_LOAD16, 4);
3cb6bf78 395 temp = OP[1];
ead4a3f1 396 temp = SEXT7 (temp);
3cb6bf78
JL		 397 op2 = temp << 2;
398 result = get_word (State.mem + State.regs[30] + op2);
399 State.regs[OP[0]] = result;
ead4a3f1 400 trace_output (OP_LOAD16);
22c1c7dd
JL		 401}
402
28647e4c
JL		 403/* sst.b */
404void
405OP_380 ()
406{
9fca2fd3
JL		 407 unsigned int op0, op1;
408 int temp;
3cb6bf78 409
ead4a3f1 410 trace_input ("sst.b", OP_STORE16, 1);
3cb6bf78
JL		 411 op0 = State.regs[OP[0]];
412 temp = OP[1];
ead4a3f1 413 temp = SEXT7 (temp);
3cb6bf78
JL		 414 op1 = temp;
415 put_byte (State.mem + State.regs[30] + op1, op0);
ead4a3f1 416 trace_output (OP_STORE16);
28647e4c
JL		 417}
418
419/* sst.h */
420void
421OP_480 ()
422{
9fca2fd3
JL		 423 unsigned int op0, op1;
424 int temp;
3cb6bf78 425
ead4a3f1 426 trace_input ("sst.h", OP_STORE16, 2);
3cb6bf78
JL		 427 op0 = State.regs[OP[0]];
428 temp = OP[1];
ead4a3f1 429 temp = SEXT7 (temp);
3cb6bf78
JL		 430 op1 = temp << 1;
431 put_half (State.mem + State.regs[30] + op1, op0);
ead4a3f1 432 trace_output (OP_STORE16);
28647e4c
JL		 433}
434
435/* sst.w */
436void
437OP_501 ()
438{
9fca2fd3
JL		 439 unsigned int op0, op1;
440 int temp;
3cb6bf78 441
ead4a3f1 442 trace_input ("sst.w", OP_STORE16, 4);
3cb6bf78
JL		 443 op0 = State.regs[OP[0]];
444 temp = OP[1];
ead4a3f1 445 temp = SEXT7 (temp);
3cb6bf78
JL		 446 op1 = temp << 2;
447 put_word (State.mem + State.regs[30] + op1, op0);
ead4a3f1 448 trace_output (OP_STORE16);
28647e4c
JL		 449}
450
451/* ld.b */
452void
453OP_700 ()
454{
9fca2fd3 455 unsigned int op0, op2;
28647e4c
JL		 456 int result, temp;
457
ead4a3f1 458 trace_input ("ld.b", OP_LOAD32, 1);
28647e4c 459 op0 = State.regs[OP[0]];
ead4a3f1 460 temp = SEXT16 (OP[2]);
28647e4c
JL		 461 op2 = temp;
462 result = get_byte (State.mem + op0 + op2);
ead4a3f1
MM		 463 State.regs[OP[1]] = SEXT8 (result);
464 trace_output (OP_LOAD32);
28647e4c
JL		 465}
466
467/* ld.h */
468void
469OP_720 ()
470{
9fca2fd3 471 unsigned int op0, op2;
28647e4c
JL		 472 int result, temp;
473
ead4a3f1 474 trace_input ("ld.h", OP_LOAD32, 2);
28647e4c 475 op0 = State.regs[OP[0]];
ead4a3f1 476 temp = SEXT16 (OP[2]);
28647e4c
JL		 477 temp &= ~0x1;
478 op2 = temp;
479 result = get_half (State.mem + op0 + op2);
ead4a3f1
MM		 480 State.regs[OP[1]] = SEXT16 (result);
481 trace_output (OP_LOAD32);
28647e4c
JL		 482}
483
484/* ld.w */
485void
486OP_10720 ()
487{
9fca2fd3 488 unsigned int op0, op2;
28647e4c
JL		 489 int result, temp;
490
ead4a3f1 491 trace_input ("ld.w", OP_LOAD32, 4);
28647e4c 492 op0 = State.regs[OP[0]];
ead4a3f1 493 temp = SEXT16 (OP[2]);
28647e4c
JL		 494 temp &= ~0x1;
495 op2 = temp;
496 result = get_word (State.mem + op0 + op2);
497 State.regs[OP[1]] = result;
ead4a3f1 498 trace_output (OP_LOAD32);
28647e4c
JL		 499}
500
501/* st.b */
502void
503OP_740 ()
504{
505 unsigned int op0, op1, op2;
9fca2fd3 506 int temp;
28647e4c 507
ead4a3f1 508 trace_input ("st.b", OP_STORE32, 1);
28647e4c
JL		 509 op0 = State.regs[OP[0]];
510 op1 = State.regs[OP[1]];
ead4a3f1 511 temp = SEXT16 (OP[2]);
28647e4c
JL		 512 op2 = temp;
513 put_byte (State.mem + op0 + op2, op1);
ead4a3f1 514 trace_output (OP_STORE32);
28647e4c
JL		 515}
516
517/* st.h */
22c1c7dd
JL		 518void
519OP_760 ()
520{
28647e4c 521 unsigned int op0, op1, op2;
9fca2fd3 522 int temp;
28647e4c 523
ead4a3f1 524 trace_input ("st.h", OP_STORE32, 2);
28647e4c
JL		 525 op0 = State.regs[OP[0]];
526 op1 = State.regs[OP[1]];
ead4a3f1 527 temp = SEXT16 (OP[2] & ~0x1);
28647e4c
JL		 528 op2 = temp;
529 put_half (State.mem + op0 + op2, op1);
ead4a3f1 530 trace_output (OP_STORE32);
28647e4c
JL		 531}
532
533/* st.w */
534void
535OP_10760 ()
536{
537 unsigned int op0, op1, op2;
9fca2fd3 538 int temp;
28647e4c 539
ead4a3f1 540 trace_input ("st.w", OP_STORE32, 4);
28647e4c
JL		 541 op0 = State.regs[OP[0]];
542 op1 = State.regs[OP[1]];
ead4a3f1 543 temp = SEXT16 (OP[2] & ~0x1);
28647e4c
JL		 544 op2 = temp;
545 put_word (State.mem + op0 + op2, op1);
ead4a3f1 546 trace_output (OP_STORE32);
22c1c7dd
JL		 547}
548
2108e864 549/* bv disp9 */
22c1c7dd
JL		 550void
551OP_580 ()
552{
ead4a3f1
MM		 553 unsigned int psw;
554 int op0;
22c1c7dd 555
ead4a3f1
MM		 556 trace_input ("bv", OP_COND_BR, 0);
557 op0 = SEXT9 (OP[0]);
614f1c68 558 psw = State.sregs[5];
2108e864
JL		 559
560 if ((psw & PSW_OV) != 0)
561 State.pc += op0;
562 else
563 State.pc += 2;
ead4a3f1 564 trace_output (OP_COND_BR);
22c1c7dd
JL		 565}
566
2108e864 567/* bl disp9 */
22c1c7dd
JL		 568void
569OP_581 ()
570{
ead4a3f1
MM		 571 unsigned int psw;
572 int op0;
2108e864 573
ead4a3f1
MM		 574 trace_input ("bl", OP_COND_BR, 0);
575 op0 = SEXT9 (OP[0]);
614f1c68 576 psw = State.sregs[5];
2108e864
JL		 577
578 if ((psw & PSW_CY) != 0)
579 State.pc += op0;
580 else
581 State.pc += 2;
ead4a3f1 582 trace_output (OP_COND_BR);
22c1c7dd
JL		 583}
584
2108e864 585/* be disp9 */
22c1c7dd
JL		 586void
587OP_582 ()
588{
ead4a3f1
MM		 589 unsigned int psw;
590 int op0;
2108e864 591
ead4a3f1
MM		 592 trace_input ("be", OP_COND_BR, 0);
593 op0 = SEXT9 (OP[0]);
614f1c68 594 psw = State.sregs[5];
2108e864
JL		 595
596 if ((psw & PSW_Z) != 0)
597 State.pc += op0;
598 else
599 State.pc += 2;
ead4a3f1 600 trace_output (OP_COND_BR);
22c1c7dd
JL		 601}
602
2108e864 603/* bnh disp 9*/
22c1c7dd
JL		 604void
605OP_583 ()
606{
ead4a3f1
MM		 607 unsigned int psw;
608 int op0;
2108e864 609
ead4a3f1
MM		 610 trace_input ("bnh", OP_COND_BR, 0);
611 op0 = SEXT9 (OP[0]);
614f1c68 612 psw = State.sregs[5];
2108e864
JL		 613
614 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
615 State.pc += op0;
616 else
617 State.pc += 2;
ead4a3f1 618 trace_output (OP_COND_BR);
22c1c7dd
JL		 619}
620
2108e864 621/* bn disp9 */
22c1c7dd
JL		 622void
623OP_584 ()
624{
ead4a3f1
MM		 625 unsigned int psw;
626 int op0;
2108e864 627
ead4a3f1
MM		 628 trace_input ("bn", OP_COND_BR, 0);
629 op0 = SEXT9 (OP[0]);
614f1c68 630 psw = State.sregs[5];
2108e864
JL		 631
632 if ((psw & PSW_S) != 0)
633 State.pc += op0;
634 else
635 State.pc += 2;
ead4a3f1 636 trace_output (OP_COND_BR);
22c1c7dd
JL		 637}
638
2108e864 639/* br disp9 */
22c1c7dd
JL		 640void
641OP_585 ()
642{
ead4a3f1
MM		 643 unsigned int psw;
644 int op0;
2108e864 645
ead4a3f1
MM		 646 trace_input ("br", OP_COND_BR, 0);
647 op0 = SEXT9 (OP[0]);
2108e864 648 State.pc += op0;
ead4a3f1 649 trace_output (OP_COND_BR);
22c1c7dd
JL		 650}
651
2108e864 652/* blt disp9 */
22c1c7dd
JL		 653void
654OP_586 ()
655{
ead4a3f1
MM		 656 unsigned int psw;
657 int op0;
2108e864 658
ead4a3f1
MM		 659 trace_input ("blt", OP_COND_BR, 0);
660 op0 = SEXT9 (OP[0]);
614f1c68 661 psw = State.sregs[5];
2108e864
JL		 662
663 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
664 State.pc += op0;
665 else
666 State.pc += 2;
ead4a3f1 667 trace_output (OP_COND_BR);
22c1c7dd
JL		 668}
669
2108e864 670/* ble disp9 */
22c1c7dd
JL		 671void
672OP_587 ()
673{
ead4a3f1
MM		 674 unsigned int psw;
675 int op0;
2108e864 676
ead4a3f1
MM		 677 trace_input ("ble", OP_COND_BR, 0);
678 op0 = SEXT9 (OP[0]);
614f1c68 679 psw = State.sregs[5];
2108e864
JL		 680
681 if ((((psw & PSW_Z) != 0)
682 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
683 State.pc += op0;
684 else
685 State.pc += 2;
ead4a3f1 686 trace_output (OP_COND_BR);
22c1c7dd
JL		 687}
688
2108e864 689/* bnv disp9 */
22c1c7dd
JL		 690void
691OP_588 ()
692{
ead4a3f1
MM		 693 unsigned int psw;
694 int op0;
2108e864 695
ead4a3f1
MM		 696 trace_input ("bnv", OP_COND_BR, 0);
697 op0 = SEXT9 (OP[0]);
614f1c68 698 psw = State.sregs[5];
2108e864
JL		 699
700 if ((psw & PSW_OV) == 0)
701 State.pc += op0;
702 else
703 State.pc += 2;
ead4a3f1 704 trace_output (OP_COND_BR);
22c1c7dd
JL		 705}
706
2108e864 707/* bnl disp9 */
22c1c7dd
JL		 708void
709OP_589 ()
710{
ead4a3f1
MM		 711 unsigned int psw;
712 int op0;
2108e864 713
ead4a3f1
MM		 714 trace_input ("bnl", OP_COND_BR, 0);
715 op0 = SEXT9 (OP[0]);
614f1c68 716 psw = State.sregs[5];
2108e864
JL		 717
718 if ((psw & PSW_CY) == 0)
719 State.pc += op0;
720 else
721 State.pc += 2;
ead4a3f1 722 trace_output (OP_COND_BR);
22c1c7dd
JL		 723}
724
2108e864 725/* bne disp9 */
22c1c7dd
JL		 726void
727OP_58A ()
728{
ead4a3f1
MM		 729 unsigned int psw;
730 int op0;
2108e864 731
ead4a3f1
MM		 732 trace_input ("bne", OP_COND_BR, 0);
733 op0 = SEXT9 (OP[0]);
614f1c68 734 psw = State.sregs[5];
2108e864
JL		 735
736 if ((psw & PSW_Z) == 0)
737 State.pc += op0;
738 else
739 State.pc += 2;
ead4a3f1 740 trace_output (OP_COND_BR);
22c1c7dd
JL		 741}
742
2108e864 743/* bh disp9 */
22c1c7dd
JL		 744void
745OP_58B ()
746{
ead4a3f1
MM		 747 unsigned int psw;
748 int op0;
22c1c7dd 749
ead4a3f1
MM		 750 trace_input ("bh", OP_COND_BR, 0);
751 op0 = SEXT9 (OP[0]);
614f1c68 752 psw = State.sregs[5];
2108e864
JL		 753
754 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
755 State.pc += op0;
756 else
757 State.pc += 2;
ead4a3f1 758 trace_output (OP_COND_BR);
22c1c7dd
JL		 759}
760
2108e864 761/* bp disp9 */
22c1c7dd 762void
2108e864 763OP_58C ()
22c1c7dd 764{
ead4a3f1
MM		 765 unsigned int psw;
766 int op0;
22c1c7dd 767
ead4a3f1
MM		 768 trace_input ("bp", OP_COND_BR, 0);
769 op0 = SEXT9 (OP[0]);
614f1c68 770 psw = State.sregs[5];
2108e864
JL		 771
772 if ((psw & PSW_S) == 0)
773 State.pc += op0;
774 else
775 State.pc += 2;
ead4a3f1 776 trace_output (OP_COND_BR);
22c1c7dd
JL		 777}
778
2108e864 779/* bsa disp9 */
22c1c7dd
JL		 780void
781OP_58D ()
782{
ead4a3f1
MM		 783 unsigned int psw;
784 int op0;
2108e864 785
ead4a3f1
MM		 786 trace_input ("bsa", OP_COND_BR, 0);
787 op0 = SEXT9 (OP[0]);
614f1c68 788 psw = State.sregs[5];
2108e864
JL		 789
790 if ((psw & PSW_SAT) != 0)
791 State.pc += op0;
792 else
793 State.pc += 2;
ead4a3f1 794 trace_output (OP_COND_BR);
22c1c7dd
JL		 795}
796
2108e864 797/* bge disp9 */
22c1c7dd
JL		 798void
799OP_58E ()
800{
ead4a3f1
MM		 801 unsigned int psw;
802 int op0;
2108e864 803
ead4a3f1
MM		 804 trace_input ("bge", OP_COND_BR, 0);
805 op0 = SEXT9 (OP[0]);
614f1c68 806 psw = State.sregs[5];
2108e864
JL		 807
808 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
809 State.pc += op0;
810 else
811 State.pc += 2;
ead4a3f1 812 trace_output (OP_COND_BR);
22c1c7dd
JL		 813}
814
2108e864 815/* bgt disp9 */
22c1c7dd
JL		 816void
817OP_58F ()
818{
ead4a3f1
MM		 819 unsigned int psw;
820 int op0;
2108e864 821
ead4a3f1
MM		 822 trace_input ("bgt", OP_COND_BR, 0);
823 op0 = SEXT9 (OP[0]);
614f1c68 824 psw = State.sregs[5];
2108e864
JL		 825
826 if ((((psw & PSW_Z) != 0)
827 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
828 State.pc += op0;
829 else
830 State.pc += 2;
ead4a3f1 831 trace_output (OP_COND_BR);
22c1c7dd
JL		 832}
833
e9b6cbac 834/* jmp [reg1] */
22c1c7dd 835void
e9b6cbac 836OP_60 ()
22c1c7dd 837{
e9b6cbac 838 /* interp.c will bump this by +2, so correct for it here. */
ead4a3f1 839 trace_input ("jmp", OP_REG, 0);
e9b6cbac 840 State.pc = State.regs[OP[0]] - 2;
ead4a3f1 841 trace_output (OP_REG);
22c1c7dd
JL		 842}
843
e9b6cbac
JL		 844/* jarl disp22, reg */
845void
846OP_780 ()
847{
848 unsigned int op0, opc;
849 int temp;
850
ead4a3f1
MM		 851 trace_input ("jarl", OP_JUMP, 0);
852 temp = SEXT22 (OP[0]);
e9b6cbac
JL		 853 op0 = temp;
854 opc = State.pc;
855
856 State.pc += temp;
857
858 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
859 if (OP[1] != 0)
860 State.regs[OP[1]] = opc + 4;
ead4a3f1 861 trace_output (OP_JUMP);
e9b6cbac 862}
22c1c7dd 863
0ef0eba5 864/* add reg, reg */
22c1c7dd 865void
1fe983dc 866OP_1C0 ()
22c1c7dd 867{
0ef0eba5 868 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 869
ead4a3f1 870 trace_input ("add", OP_REG_REG, 0);
0ef0eba5
JL		 871 /* Compute the result. */
872 op0 = State.regs[OP[0]];
873 op1 = State.regs[OP[1]];
874 result = op0 + op1;
1fe983dc 875
0ef0eba5
JL		 876 /* Compute the condition codes. */
877 z = (result == 0);
878 s = (result & 0x80000000);
879 cy = (result < op0 || result < op1);
880 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
881 && (op0 & 0x80000000) != (result & 0x80000000));
882
883 /* Store the result and condition codes. */
884 State.regs[OP[1]] = result;
614f1c68
JL		 885 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
886 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
887 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 888 trace_output (OP_REG_REG);
0ef0eba5
JL		 889}
890
891/* add sign_extend(imm5), reg */
22c1c7dd 892void
1fe983dc 893OP_240 ()
22c1c7dd 894{
0ef0eba5
JL		 895 unsigned int op0, op1, result, z, s, cy, ov;
896 int temp;
1fe983dc 897
ead4a3f1
MM		 898 trace_input ("add", OP_IMM_REG, 0);
899
0ef0eba5 900 /* Compute the result. */
ead4a3f1 901 temp = SEXT5 (OP[0]);
0ef0eba5
JL		 902 op0 = temp;
903 op1 = State.regs[OP[1]];
904 result = op0 + op1;
905
906 /* Compute the condition codes. */
907 z = (result == 0);
908 s = (result & 0x80000000);
909 cy = (result < op0 || result < op1);
910 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
911 && (op0 & 0x80000000) != (result & 0x80000000));
22c1c7dd 912
0ef0eba5
JL		 913 /* Store the result and condition codes. */
914 State.regs[OP[1]] = result;
614f1c68
JL		 915 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
916 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5 917 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 918 trace_output (OP_IMM_REG);
0ef0eba5 919}
1fe983dc 920
0ef0eba5 921/* addi sign_extend(imm16), reg, reg */
22c1c7dd 922void
1fe983dc 923OP_600 ()
22c1c7dd 924{
0ef0eba5
JL		 925 unsigned int op0, op1, result, z, s, cy, ov;
926 int temp;
927
ead4a3f1
MM		 928 trace_input ("addi", OP_IMM_REG_REG, 0);
929
0ef0eba5 930 /* Compute the result. */
ead4a3f1 931 temp = SEXT16 (OP[0]);
0ef0eba5
JL		 932 op0 = temp;
933 op1 = State.regs[OP[1]];
934 result = op0 + op1;
935
936 /* Compute the condition codes. */
937 z = (result == 0);
938 s = (result & 0x80000000);
939 cy = (result < op0 || result < op1);
940 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
941 && (op0 & 0x80000000) != (result & 0x80000000));
942
943 /* Store the result and condition codes. */
944 State.regs[OP[2]] = result;
614f1c68
JL		 945 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
946 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
0ef0eba5 947 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 948 trace_output (OP_IMM_REG_REG);
22c1c7dd
JL		 949}
950
aabce0f4 951/* sub reg1, reg2 */
22c1c7dd 952void
1fe983dc 953OP_1A0 ()
22c1c7dd 954{
aabce0f4
JL		 955 unsigned int op0, op1, result, z, s, cy, ov;
956
ead4a3f1 957 trace_input ("sub", OP_REG_REG, 0);
aabce0f4
JL		 958 /* Compute the result. */
959 op0 = State.regs[OP[0]];
960 op1 = State.regs[OP[1]];
961 result = op1 - op0;
22c1c7dd 962
aabce0f4
JL		 963 /* Compute the condition codes. */
964 z = (result == 0);
965 s = (result & 0x80000000);
d81352b8 966 cy = (op1 < op0);
aabce0f4
JL		 967 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
968 && (op1 & 0x80000000) != (result & 0x80000000));
1fe983dc 969
aabce0f4
JL		 970 /* Store the result and condition codes. */
971 State.regs[OP[1]] = result;
614f1c68
JL		 972 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
973 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 974 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 975 trace_output (OP_REG_REG);
aabce0f4
JL		 976}
977
978/* subr reg1, reg2 */
22c1c7dd 979void
1fe983dc 980OP_180 ()
22c1c7dd 981{
aabce0f4 982 unsigned int op0, op1, result, z, s, cy, ov;
22c1c7dd 983
ead4a3f1 984 trace_input ("subr", OP_REG_REG, 0);
aabce0f4
JL		 985 /* Compute the result. */
986 op0 = State.regs[OP[0]];
987 op1 = State.regs[OP[1]];
988 result = op0 - op1;
e98e3b2c 989
aabce0f4
JL		 990 /* Compute the condition codes. */
991 z = (result == 0);
992 s = (result & 0x80000000);
d81352b8 993 cy = (op0 < op1);
aabce0f4
JL		 994 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
995 && (op0 & 0x80000000) != (result & 0x80000000));
996
997 /* Store the result and condition codes. */
998 State.regs[OP[1]] = result;
614f1c68
JL		 999 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1000 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 1001 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 1002 trace_output (OP_REG_REG);
aabce0f4
JL		 1003}
1004
1005/* mulh reg1, reg2 */
22c1c7dd 1006void
e98e3b2c 1007OP_E0 ()
22c1c7dd 1008{
ead4a3f1 1009 trace_input ("mulh", OP_REG_REG, 0);
e98e3b2c 1010 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
fb8eb42b 1011 * (State.regs[OP[0]] & 0xffff));
ead4a3f1 1012 trace_output (OP_REG_REG);
22c1c7dd
JL		 1013}
1014
e98e3b2c
JL		 1015/* mulh sign_extend(imm5), reg2
1016
1017 Condition codes */
22c1c7dd 1018void
e98e3b2c 1019OP_2E0 ()
22c1c7dd 1020{
ead4a3f1 1021 int value = SEXT5 (OP[0]);
e98e3b2c 1022
ead4a3f1 1023 trace_input ("mulh", OP_IMM_REG, 0);
e98e3b2c 1024 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
ead4a3f1 1025 trace_output (OP_IMM_REG);
22c1c7dd
JL		 1026}
1027
aabce0f4 1028/* mulhi imm16, reg1, reg2 */
22c1c7dd 1029void
e98e3b2c
JL		 1030OP_6E0 ()
1031{
ead4a3f1 1032 int value = OP[0] & 0xffff;
e98e3b2c 1033
ead4a3f1 1034 trace_input ("mulhi", OP_IMM_REG_REG, 0);
fb8eb42b 1035 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
ead4a3f1 1036 trace_output (OP_IMM_REG_REG);
e98e3b2c
JL		 1037}
1038
aabce0f4 1039/* divh reg1, reg2 */
e98e3b2c
JL		 1040void
1041OP_40 ()
22c1c7dd 1042{
9fca2fd3 1043 unsigned int op0, op1, result, ov, s, z;
aabce0f4
JL		 1044 int temp;
1045
ead4a3f1
MM		 1046 trace_input ("divh", OP_REG_REG, 0);
1047
aabce0f4 1048 /* Compute the result. */
ead4a3f1 1049 temp = SEXT16 (State.regs[OP[0]]);
aabce0f4
JL		 1050 op0 = temp;
1051 op1 = State.regs[OP[1]];
1052
1053 if (op0 == 0xffffffff && op1 == 0x80000000)
1054 {
1055 result = 0x80000000;
1056 ov = 1;
1057 }
1058 else if (op0 != 0)
1059 {
1060 result = op1 / op0;
1061 ov = 0;
1062 }
1063 else
9fca2fd3
JL		 1064 {
1065 result = 0x0;
1066 ov = 1;
1067 }
aabce0f4
JL		 1068
1069 /* Compute the condition codes. */
1070 z = (result == 0);
1071 s = (result & 0x80000000);
1072
1073 /* Store the result and condition codes. */
1074 State.regs[OP[1]] = result;
614f1c68
JL		 1075 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1076 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
aabce0f4 1077 | (ov ? PSW_OV : 0));
ead4a3f1 1078 trace_output (OP_REG_REG);
22c1c7dd
JL		 1079}
1080
3095b8df
JL		 1081/* cmp reg, reg */
1082void
1083OP_1E0 ()
1084{
1085 unsigned int op0, op1, result, z, s, cy, ov;
1086
ead4a3f1 1087 trace_input ("cmp", OP_REG_REG_CMP, 0);
3095b8df
JL		 1088 /* Compute the result. */
1089 op0 = State.regs[OP[0]];
1090 op1 = State.regs[OP[1]];
1091 result = op1 - op0;
1092
1093 /* Compute the condition codes. */
1094 z = (result == 0);
1095 s = (result & 0x80000000);
d81352b8 1096 cy = (op1 < op0);
3095b8df
JL		 1097 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1098 && (op1 & 0x80000000) != (result & 0x80000000));
1099
1100 /* Set condition codes. */
614f1c68
JL		 1101 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1102 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df 1103 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 1104 trace_output (OP_REG_REG_CMP);
3095b8df
JL		 1105}
1106
1107/* cmp sign_extend(imm5), reg */
1108void
1109OP_260 ()
1110{
1111 unsigned int op0, op1, result, z, s, cy, ov;
1112 int temp;
1113
1114 /* Compute the result. */
ead4a3f1
MM		 1115 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1116 temp = SEXT5 (OP[0]);
3095b8df
JL		 1117 op0 = temp;
1118 op1 = State.regs[OP[1]];
1119 result = op1 - op0;
1120
1121 /* Compute the condition codes. */
1122 z = (result == 0);
1123 s = (result & 0x80000000);
d81352b8 1124 cy = (op1 < op0);
3095b8df
JL		 1125 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1126 && (op1 & 0x80000000) != (result & 0x80000000));
1127
1128 /* Set condition codes. */
614f1c68
JL		 1129 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1130 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3095b8df 1131 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
ead4a3f1 1132 trace_output (OP_IMM_REG_CMP);
3095b8df
JL		 1133}
1134
1135/* setf cccc,reg2 */
1136void
1137OP_7E0 ()
1138{
1139 /* Hack alert. We turn off a bit in op0 since we really only
1140 wanted 4 bits. */
9fca2fd3 1141 unsigned int op0, psw, result = 0;
3095b8df 1142
ead4a3f1 1143 trace_input ("setf", OP_EX1, 0);
3095b8df 1144 op0 = OP[0] & 0xf;
614f1c68 1145 psw = State.sregs[5];
3095b8df
JL		 1146
1147 switch (op0)
1148 {
1149 case 0x0:
1150 result = ((psw & PSW_OV) != 0);
1151 break;
1152 case 0x1:
1153 result = ((psw & PSW_CY) != 0);
1154 break;
1155 case 0x2:
1156 result = ((psw & PSW_Z) != 0);
1157 break;
1158 case 0x3:
1159 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1160 break;
1161 case 0x4:
1162 result = ((psw & PSW_S) != 0);
1163 break;
1164 case 0x5:
1165 result = 1;
1166 break;
1167 case 0x6:
1168 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1169 break;
1170 case 0x7:
1171 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1172 || ((psw & PSW_Z) != 0)) != 0);
1173 break;
1174 case 0x8:
1175 result = ((psw & PSW_OV) == 0);
1176 break;
1177 case 0x9:
1178 result = ((psw & PSW_CY) == 0);
1179 break;
1180 case 0xa:
1181 result = ((psw & PSW_Z) == 0);
1182 break;
1183 case 0xb:
1184 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1185 break;
1186 case 0xc:
1187 result = ((psw & PSW_S) == 0);
1188 break;
1189 case 0xd:
1190 result = ((psw & PSW_SAT) != 0);
1191 break;
1192 case 0xe:
1193 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1194 break;
1195 case 0xf:
1196 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1197 || ((psw & PSW_Z) != 0)) == 0);
1198 break;
1199 }
1200
1201 State.regs[OP[1]] = result;
ead4a3f1 1202 trace_output (OP_EX1);
3095b8df
JL		 1203}
1204
dca41ba7
JL		 1205/* satadd reg,reg */
1206void
1207OP_C0 ()
1208{
1209 unsigned int op0, op1, result, z, s, cy, ov, sat;
1210
ead4a3f1 1211 trace_input ("satadd", OP_REG_REG, 0);
dca41ba7
JL		 1212 /* Compute the result. */
1213 op0 = State.regs[OP[0]];
1214 op1 = State.regs[OP[1]];
1215 result = op0 + op1;
1216
1217 /* Compute the condition codes. */
1218 z = (result == 0);
1219 s = (result & 0x80000000);
1220 cy = (result < op0 || result < op1);
1221 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1222 && (op0 & 0x80000000) != (result & 0x80000000));
1223 sat = ov;
1224
1225 /* Store the result and condition codes. */
1226 State.regs[OP[1]] = result;
614f1c68
JL		 1227 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1228 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1229 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1230 | (sat ? PSW_SAT : 0));
1231
1232 /* Handle saturated results. */
0e4ccc58 1233 if (sat && s)
dca41ba7
JL		 1234 State.regs[OP[1]] = 0x80000000;
1235 else if (sat)
1236 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1237 trace_output (OP_REG_REG);
dca41ba7
JL		 1238}
1239
1240/* satadd sign_extend(imm5), reg */
1241void
1242OP_220 ()
1243{
1244 unsigned int op0, op1, result, z, s, cy, ov, sat;
1245
1246 int temp;
1247
ead4a3f1
MM		 1248 trace_input ("satadd", OP_IMM_REG, 0);
1249
dca41ba7 1250 /* Compute the result. */
ead4a3f1 1251 temp = SEXT5 (OP[0]);
dca41ba7
JL		 1252 op0 = temp;
1253 op1 = State.regs[OP[1]];
1254 result = op0 + op1;
1255
1256 /* Compute the condition codes. */
1257 z = (result == 0);
1258 s = (result & 0x80000000);
1259 cy = (result < op0 || result < op1);
1260 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1261 && (op0 & 0x80000000) != (result & 0x80000000));
1262 sat = ov;
1263
1264 /* Store the result and condition codes. */
1265 State.regs[OP[1]] = result;
614f1c68
JL		 1266 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1267 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1268 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1269 | (sat ? PSW_SAT : 0));
1270
1271 /* Handle saturated results. */
0e4ccc58 1272 if (sat && s)
dca41ba7
JL		 1273 State.regs[OP[1]] = 0x80000000;
1274 else if (sat)
1275 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1276 trace_output (OP_IMM_REG);
dca41ba7
JL		 1277}
1278
1279/* satsub reg1, reg2 */
1280void
1281OP_A0 ()
1282{
1283 unsigned int op0, op1, result, z, s, cy, ov, sat;
1284
ead4a3f1
MM		 1285 trace_input ("satsub", OP_REG_REG, 0);
1286
dca41ba7
JL		 1287 /* Compute the result. */
1288 op0 = State.regs[OP[0]];
1289 op1 = State.regs[OP[1]];
1290 result = op1 - op0;
1291
1292 /* Compute the condition codes. */
1293 z = (result == 0);
1294 s = (result & 0x80000000);
d81352b8 1295 cy = (op1 < op0);
dca41ba7
JL		 1296 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1297 && (op1 & 0x80000000) != (result & 0x80000000));
1298 sat = ov;
1299
1300 /* Store the result and condition codes. */
1301 State.regs[OP[1]] = result;
614f1c68
JL		 1302 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1303 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1304 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1305 | (sat ? PSW_SAT : 0));
1306
1307 /* Handle saturated results. */
0e4ccc58 1308 if (sat && s)
dca41ba7
JL		 1309 State.regs[OP[1]] = 0x80000000;
1310 else if (sat)
1311 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1312 trace_output (OP_REG_REG);
dca41ba7
JL		 1313}
1314
1315/* satsubi sign_extend(imm16), reg */
1316void
1317OP_660 ()
1318{
1319 unsigned int op0, op1, result, z, s, cy, ov, sat;
1320 int temp;
1321
ead4a3f1
MM		 1322 trace_input ("satsubi", OP_IMM_REG, 0);
1323
dca41ba7 1324 /* Compute the result. */
ead4a3f1 1325 temp = SEXT16 (OP[0]);
dca41ba7
JL		 1326 op0 = temp;
1327 op1 = State.regs[OP[1]];
1328 result = op1 - op0;
1329
1330 /* Compute the condition codes. */
1331 z = (result == 0);
1332 s = (result & 0x80000000);
d81352b8 1333 cy = (op1 < op0);
dca41ba7
JL		 1334 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1335 && (op1 & 0x80000000) != (result & 0x80000000));
1336 sat = ov;
1337
1338 /* Store the result and condition codes. */
1339 State.regs[OP[1]] = result;
614f1c68
JL		 1340 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1341 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1342 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1343 | (sat ? PSW_SAT : 0));
1344
1345 /* Handle saturated results. */
0e4ccc58 1346 if (sat && s)
dca41ba7
JL		 1347 State.regs[OP[1]] = 0x80000000;
1348 else if (sat)
1349 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1350 trace_output (OP_IMM_REG);
dca41ba7
JL		 1351}
1352
ead4a3f1 1353/* satsubr reg,reg */
dca41ba7
JL		 1354void
1355OP_80 ()
1356{
1357 unsigned int op0, op1, result, z, s, cy, ov, sat;
1358
ead4a3f1
MM		 1359 trace_input ("satsubr", OP_REG_REG, 0);
1360
dca41ba7
JL		 1361 /* Compute the result. */
1362 op0 = State.regs[OP[0]];
1363 op1 = State.regs[OP[1]];
1364 result = op0 - op1;
1365
1366 /* Compute the condition codes. */
1367 z = (result == 0);
1368 s = (result & 0x80000000);
d81352b8 1369 cy = (result < op0);
dca41ba7
JL		 1370 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1371 && (op1 & 0x80000000) != (result & 0x80000000));
1372 sat = ov;
1373
1374 /* Store the result and condition codes. */
1375 State.regs[OP[1]] = result;
614f1c68
JL		 1376 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1377 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
dca41ba7
JL		 1378 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1379 | (sat ? PSW_SAT : 0));
1380
1381 /* Handle saturated results. */
0e4ccc58 1382 if (sat && s)
dca41ba7
JL		 1383 State.regs[OP[1]] = 0x80000000;
1384 else if (sat)
1385 State.regs[OP[1]] = 0x7fffffff;
ead4a3f1 1386 trace_output (OP_REG_REG);
dca41ba7
JL		 1387}
1388
3095b8df
JL		 1389/* tst reg,reg */
1390void
1391OP_160 ()
1392{
9fca2fd3 1393 unsigned int op0, op1, result, z, s;
3095b8df 1394
ead4a3f1
MM		 1395 trace_input ("tst", OP_REG_REG_CMP, 0);
1396
3095b8df
JL		 1397 /* Compute the result. */
1398 op0 = State.regs[OP[0]];
1399 op1 = State.regs[OP[1]];
1400 result = op0 & op1;
1401
1402 /* Compute the condition codes. */
1403 z = (result == 0);
1404 s = (result & 0x80000000);
1405
1406 /* Store the condition codes. */
614f1c68
JL		 1407 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1408 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1409 trace_output (OP_REG_REG_CMP);
3095b8df
JL		 1410}
1411
1fe983dc 1412/* mov reg, reg */
22c1c7dd
JL		 1413void
1414OP_0 ()
1415{
ead4a3f1 1416 trace_input ("mov", OP_REG_REG_MOVE, 0);
1fe983dc 1417 State.regs[OP[1]] = State.regs[OP[0]];
ead4a3f1 1418 trace_output (OP_REG_REG_MOVE);
22c1c7dd
JL		 1419}
1420
1fe983dc 1421/* mov sign_extend(imm5), reg */
22c1c7dd 1422void
1fe983dc 1423OP_200 ()
22c1c7dd 1424{
ead4a3f1 1425 int value = SEXT5 (OP[0]);
1fe983dc 1426
ead4a3f1 1427 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1fe983dc 1428 State.regs[OP[1]] = value;
ead4a3f1 1429 trace_output (OP_IMM_REG_MOVE);
22c1c7dd
JL		 1430}
1431
1fe983dc
JL		 1432/* movea sign_extend(imm16), reg, reg */
1433
22c1c7dd 1434void
1fe983dc 1435OP_620 ()
22c1c7dd 1436{
ead4a3f1 1437 int value = SEXT16 (OP[0]);
1fe983dc 1438
ead4a3f1 1439 trace_input ("movea", OP_IMM_REG_REG, 0);
1fe983dc 1440 State.regs[OP[2]] = State.regs[OP[1]] + value;
ead4a3f1 1441 trace_output (OP_IMM_REG_REG);
22c1c7dd
JL		 1442}
1443
1fe983dc 1444/* movhi imm16, reg, reg */
22c1c7dd 1445void
1fe983dc 1446OP_640 ()
22c1c7dd 1447{
ead4a3f1 1448 uint32 value = (OP[0] & 0xffff) << 16;
1fe983dc 1449
ead4a3f1 1450 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1fe983dc 1451 State.regs[OP[2]] = State.regs[OP[1]] + value;
ead4a3f1 1452 trace_output (OP_UIMM_REG_REG);
22c1c7dd
JL		 1453}
1454
35404c7d 1455/* sar zero_extend(imm5),reg1 */
22c1c7dd 1456void
77553374 1457OP_2A0 ()
22c1c7dd 1458{
9fca2fd3 1459 unsigned int op0, op1, result, z, s, cy;
77553374 1460
ead4a3f1 1461 trace_input ("sar", OP_IMM_REG, 0);
35404c7d
JL		 1462 op0 = OP[0] & 0x1f;
1463 op1 = State.regs[OP[1]];
1464 result = (signed)op1 >> op0;
77553374 1465
35404c7d
JL		 1466 /* Compute the condition codes. */
1467 z = (result == 0);
1468 s = (result & 0x80000000);
1469 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 1470
35404c7d
JL		 1471 /* Store the result and condition codes. */
1472 State.regs[OP[1]] = result;
614f1c68
JL		 1473 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1474 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
9fca2fd3 1475 | (cy ? PSW_CY : 0));
ead4a3f1 1476 trace_output (OP_IMM_REG);
35404c7d 1477}
77553374 1478
35404c7d 1479/* sar reg1, reg2 */
22c1c7dd 1480void
77553374 1481OP_A007E0 ()
22c1c7dd 1482{
9fca2fd3 1483 unsigned int op0, op1, result, z, s, cy;
77553374 1484
ead4a3f1 1485 trace_input ("sar", OP_REG_REG, 0);
35404c7d
JL		 1486 op0 = State.regs[OP[0]] & 0x1f;
1487 op1 = State.regs[OP[1]];
1488 result = (signed)op1 >> op0;
77553374 1489
35404c7d
JL		 1490 /* Compute the condition codes. */
1491 z = (result == 0);
1492 s = (result & 0x80000000);
1493 cy = (op1 & (1 << (op0 - 1)));
22c1c7dd 1494
35404c7d
JL		 1495 /* Store the result and condition codes. */
1496 State.regs[OP[1]] = result;
614f1c68
JL		 1497 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1498 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1499 | (cy ? PSW_CY : 0));
ead4a3f1 1500 trace_output (OP_REG_REG);
35404c7d 1501}
77553374 1502
35404c7d 1503/* shl zero_extend(imm5),reg1 */
22c1c7dd
JL		 1504void
1505OP_2C0 ()
77553374 1506{
9fca2fd3 1507 unsigned int op0, op1, result, z, s, cy;
35404c7d 1508
ead4a3f1 1509 trace_input ("shl", OP_IMM_REG, 0);
35404c7d
JL		 1510 op0 = OP[0] & 0x1f;
1511 op1 = State.regs[OP[1]];
1512 result = op1 << op0;
1513
1514 /* Compute the condition codes. */
1515 z = (result == 0);
1516 s = (result & 0x80000000);
1517 cy = (op1 & (1 << (32 - op0)));
77553374 1518
35404c7d
JL		 1519 /* Store the result and condition codes. */
1520 State.regs[OP[1]] = result;
614f1c68
JL		 1521 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1522 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1523 | (cy ? PSW_CY : 0));
ead4a3f1 1524 trace_output (OP_IMM_REG);
35404c7d 1525}
77553374 1526
35404c7d 1527/* shl reg1, reg2 */
77553374
JL		 1528void
1529OP_C007E0 ()
1530{
9fca2fd3 1531 unsigned int op0, op1, result, z, s, cy;
77553374 1532
ead4a3f1 1533 trace_input ("shl", OP_REG_REG, 0);
35404c7d
JL		 1534 op0 = State.regs[OP[0]] & 0x1f;
1535 op1 = State.regs[OP[1]];
1536 result = op1 << op0;
1537
1538 /* Compute the condition codes. */
1539 z = (result == 0);
1540 s = (result & 0x80000000);
1541 cy = (op1 & (1 << (32 - op0)));
1542
1543 /* Store the result and condition codes. */
1544 State.regs[OP[1]] = result;
614f1c68
JL		 1545 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1546 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1547 | (cy ? PSW_CY : 0));
ead4a3f1 1548 trace_output (OP_REG_REG);
35404c7d 1549}
77553374 1550
35404c7d 1551/* shr zero_extend(imm5),reg1 */
77553374
JL		 1552void
1553OP_280 ()
1554{
9fca2fd3 1555 unsigned int op0, op1, result, z, s, cy;
77553374 1556
ead4a3f1 1557 trace_input ("shr", OP_IMM_REG, 0);
35404c7d
JL		 1558 op0 = OP[0] & 0x1f;
1559 op1 = State.regs[OP[1]];
1560 result = op1 >> op0;
77553374 1561
35404c7d
JL		 1562 /* Compute the condition codes. */
1563 z = (result == 0);
1564 s = (result & 0x80000000);
1565 cy = (op1 & (1 << (op0 - 1)));
1566
1567 /* Store the result and condition codes. */
1568 State.regs[OP[1]] = result;
614f1c68
JL		 1569 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1570 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1571 | (cy ? PSW_CY : 0));
ead4a3f1 1572 trace_output (OP_IMM_REG);
35404c7d
JL		 1573}
1574
1575/* shr reg1, reg2 */
77553374
JL		 1576void
1577OP_8007E0 ()
1578{
9fca2fd3 1579 unsigned int op0, op1, result, z, s, cy;
35404c7d 1580
ead4a3f1 1581 trace_input ("shr", OP_REG_REG, 0);
35404c7d
JL		 1582 op0 = State.regs[OP[0]] & 0x1f;
1583 op1 = State.regs[OP[1]];
1584 result = op1 >> op0;
1585
1586 /* Compute the condition codes. */
1587 z = (result == 0);
1588 s = (result & 0x80000000);
1589 cy = (op1 & (1 << (op0 - 1)));
1590
1591 /* Store the result and condition codes. */
1592 State.regs[OP[1]] = result;
614f1c68
JL		 1593 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1594 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
35404c7d 1595 | (cy ? PSW_CY : 0));
ead4a3f1 1596 trace_output (OP_REG_REG);
77553374
JL		 1597}
1598
0ef0eba5 1599/* or reg, reg */
1fe983dc
JL		 1600void
1601OP_100 ()
1602{
9fca2fd3 1603 unsigned int op0, op1, result, z, s;
1fe983dc 1604
ead4a3f1
MM		 1605 trace_input ("or", OP_REG_REG, 0);
1606
0ef0eba5
JL		 1607 /* Compute the result. */
1608 op0 = State.regs[OP[0]];
1609 op1 = State.regs[OP[1]];
1610 result = op0 | op1;
1fe983dc 1611
0ef0eba5
JL		 1612 /* Compute the condition codes. */
1613 z = (result == 0);
1614 s = (result & 0x80000000);
1615
1616 /* Store the result and condition codes. */
1617 State.regs[OP[1]] = result;
614f1c68
JL		 1618 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1619 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1620 trace_output (OP_REG_REG);
0ef0eba5
JL		 1621}
1622
1623/* ori zero_extend(imm16), reg, reg */
1fe983dc
JL		 1624void
1625OP_680 ()
1626{
9fca2fd3 1627 unsigned int op0, op1, result, z, s;
1fe983dc 1628
ead4a3f1 1629 trace_input ("ori", OP_UIMM_REG_REG, 0);
0ef0eba5
JL		 1630 op0 = OP[0] & 0xffff;
1631 op1 = State.regs[OP[1]];
1632 result = op0 | op1;
1fe983dc 1633
0ef0eba5
JL		 1634 /* Compute the condition codes. */
1635 z = (result == 0);
1636 s = (result & 0x80000000);
1fe983dc 1637
0ef0eba5
JL		 1638 /* Store the result and condition codes. */
1639 State.regs[OP[2]] = result;
614f1c68
JL		 1640 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1641 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1642 trace_output (OP_UIMM_REG_REG);
0ef0eba5
JL		 1643}
1644
1645/* and reg, reg */
22c1c7dd
JL		 1646void
1647OP_140 ()
1648{
9fca2fd3 1649 unsigned int op0, op1, result, z, s;
22c1c7dd 1650
ead4a3f1
MM		 1651 trace_input ("and", OP_REG_REG, 0);
1652
0ef0eba5
JL		 1653 /* Compute the result. */
1654 op0 = State.regs[OP[0]];
1655 op1 = State.regs[OP[1]];
1656 result = op0 & op1;
1fe983dc 1657
0ef0eba5
JL		 1658 /* Compute the condition codes. */
1659 z = (result == 0);
1660 s = (result & 0x80000000);
1661
1662 /* Store the result and condition codes. */
1663 State.regs[OP[1]] = result;
614f1c68
JL		 1664 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1665 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1666 trace_output (OP_REG_REG);
0ef0eba5
JL		 1667}
1668
1669/* andi zero_extend(imm16), reg, reg */
22c1c7dd 1670void
1fe983dc
JL		 1671OP_6C0 ()
1672{
9fca2fd3 1673 unsigned int op0, op1, result, z;
1fe983dc 1674
ead4a3f1 1675 trace_input ("andi", OP_UIMM_REG_REG, 0);
0ef0eba5
JL		 1676 op0 = OP[0] & 0xffff;
1677 op1 = State.regs[OP[1]];
1678 result = op0 & op1;
1fe983dc 1679
0ef0eba5
JL		 1680 /* Compute the condition codes. */
1681 z = (result == 0);
1fe983dc 1682
0ef0eba5
JL		 1683 /* Store the result and condition codes. */
1684 State.regs[OP[2]] = result;
614f1c68
JL		 1685 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1686 State.sregs[5] |= (z ? PSW_Z : 0);
ead4a3f1 1687 trace_output (OP_UIMM_REG_REG);
0ef0eba5
JL		 1688}
1689
1690/* xor reg, reg */
1fe983dc
JL		 1691void
1692OP_120 ()
22c1c7dd 1693{
9fca2fd3 1694 unsigned int op0, op1, result, z, s;
1fe983dc 1695
ead4a3f1
MM		 1696 trace_input ("xor", OP_REG_REG, 0);
1697
0ef0eba5
JL		 1698 /* Compute the result. */
1699 op0 = State.regs[OP[0]];
1700 op1 = State.regs[OP[1]];
1701 result = op0 ^ op1;
1fe983dc 1702
0ef0eba5
JL		 1703 /* Compute the condition codes. */
1704 z = (result == 0);
1705 s = (result & 0x80000000);
1706
1707 /* Store the result and condition codes. */
1708 State.regs[OP[1]] = result;
614f1c68
JL		 1709 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1710 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1711 trace_output (OP_REG_REG);
0ef0eba5
JL		 1712}
1713
1714/* xori zero_extend(imm16), reg, reg */
1fe983dc
JL		 1715void
1716OP_6A0 ()
1717{
9fca2fd3 1718 unsigned int op0, op1, result, z, s;
0ef0eba5 1719
ead4a3f1 1720 trace_input ("xori", OP_UIMM_REG_REG, 0);
0ef0eba5
JL		 1721 op0 = OP[0] & 0xffff;
1722 op1 = State.regs[OP[1]];
1723 result = op0 ^ op1;
1724
1725 /* Compute the condition codes. */
1726 z = (result == 0);
1727 s = (result & 0x80000000);
1728
1729 /* Store the result and condition codes. */
1730 State.regs[OP[2]] = result;
614f1c68
JL		 1731 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1732 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1733 trace_output (OP_UIMM_REG_REG);
0ef0eba5
JL		 1734}
1735
1736/* not reg1, reg2 */
1737void
1738OP_20 ()
1739{
9fca2fd3 1740 unsigned int op0, result, z, s;
0ef0eba5 1741
ead4a3f1 1742 trace_input ("not", OP_REG_REG_MOVE, 0);
0ef0eba5
JL		 1743 /* Compute the result. */
1744 op0 = State.regs[OP[0]];
1745 result = ~op0;
1746
1747 /* Compute the condition codes. */
1748 z = (result == 0);
1749 s = (result & 0x80000000);
1fe983dc 1750
0ef0eba5
JL		 1751 /* Store the result and condition codes. */
1752 State.regs[OP[1]] = result;
614f1c68
JL		 1753 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1754 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
ead4a3f1 1755 trace_output (OP_REG_REG_MOVE);
22c1c7dd
JL		 1756}
1757
28647e4c 1758/* set1 */
1fe983dc 1759void
28647e4c 1760OP_7C0 ()
1fe983dc 1761{
83fc3bac 1762 unsigned int op0, op1, op2;
9fca2fd3 1763 int temp;
83fc3bac 1764
ead4a3f1 1765 trace_input ("set1", OP_BIT, 0);
83fc3bac
JL		 1766 op0 = State.regs[OP[0]];
1767 op1 = OP[1] & 0x7;
ead4a3f1 1768 temp = SEXT16 (OP[2]);
83fc3bac
JL		 1769 op2 = temp;
1770 temp = get_byte (State.mem + op0 + op2);
1771 State.sregs[5] &= ~PSW_Z;
1772 if ((temp & (1 << op1)) == 0)
1773 State.sregs[5] |= PSW_Z;
787d66bb 1774 temp |= (1 << op1);
83fc3bac 1775 put_byte (State.mem + op0 + op2, temp);
ead4a3f1 1776 trace_output (OP_BIT);
1fe983dc
JL		 1777}
1778
28647e4c 1779/* not1 */
1fe983dc 1780void
28647e4c 1781OP_47C0 ()
1fe983dc 1782{
83fc3bac 1783 unsigned int op0, op1, op2;
9fca2fd3 1784 int temp;
83fc3bac 1785
ead4a3f1 1786 trace_input ("not1", OP_BIT, 0);
83fc3bac
JL		 1787 op0 = State.regs[OP[0]];
1788 op1 = OP[1] & 0x7;
ead4a3f1 1789 temp = SEXT16 (OP[2]);
83fc3bac
JL		 1790 op2 = temp;
1791 temp = get_byte (State.mem + op0 + op2);
1792 State.sregs[5] &= ~PSW_Z;
1793 if ((temp & (1 << op1)) == 0)
1794 State.sregs[5] |= PSW_Z;
787d66bb 1795 temp ^= (1 << op1);
83fc3bac 1796 put_byte (State.mem + op0 + op2, temp);
ead4a3f1 1797 trace_output (OP_BIT);
1fe983dc
JL		 1798}
1799
28647e4c 1800/* clr1 */
1fe983dc 1801void
28647e4c
JL		 1802OP_87C0 ()
1803{
83fc3bac 1804 unsigned int op0, op1, op2;
9fca2fd3 1805 int temp;
83fc3bac 1806
ead4a3f1 1807 trace_input ("clr1", OP_BIT, 0);
83fc3bac
JL		 1808 op0 = State.regs[OP[0]];
1809 op1 = OP[1] & 0x7;
ead4a3f1 1810 temp = SEXT16 (OP[2]);
83fc3bac
JL		 1811 op2 = temp;
1812 temp = get_byte (State.mem + op0 + op2);
1813 State.sregs[5] &= ~PSW_Z;
1814 if ((temp & (1 << op1)) == 0)
1815 State.sregs[5] |= PSW_Z;
1816 temp &= ~(1 << op1);
1817 put_byte (State.mem + op0 + op2, temp);
ead4a3f1 1818 trace_output (OP_BIT);
28647e4c
JL		 1819}
1820
1821/* tst1 */
1822void
1823OP_C7C0 ()
1fe983dc 1824{
83fc3bac 1825 unsigned int op0, op1, op2;
9fca2fd3 1826 int temp;
83fc3bac 1827
ead4a3f1 1828 trace_input ("tst1", OP_BIT, 0);
83fc3bac
JL		 1829 op0 = State.regs[OP[0]];
1830 op1 = OP[1] & 0x7;
ead4a3f1 1831 temp = SEXT16 (OP[2]);
83fc3bac
JL		 1832 op2 = temp;
1833 temp = get_byte (State.mem + op0 + op2);
1834 State.sregs[5] &= ~PSW_Z;
1835 if ((temp & (1 << op1)) == 0)
1836 State.sregs[5] |= PSW_Z;
ead4a3f1 1837 trace_output (OP_BIT);
1fe983dc 1838}
e98e3b2c 1839
3095b8df 1840/* di */
e98e3b2c
JL		 1841void
1842OP_16007E0 ()
1843{
ead4a3f1 1844 trace_input ("di", OP_NONE, 0);
614f1c68 1845 State.sregs[5] |= PSW_ID;
ead4a3f1 1846 trace_output (OP_NONE);
e98e3b2c
JL		 1847}
1848
3095b8df 1849/* ei */
e98e3b2c
JL		 1850void
1851OP_16087E0 ()
1852{
ead4a3f1 1853 trace_input ("ei", OP_NONE, 0);
614f1c68 1854 State.sregs[5] &= ~PSW_ID;
ead4a3f1 1855 trace_output (OP_NONE);
e98e3b2c
JL		 1856}
1857
1858/* halt, not supported */
1859void
1860OP_12007E0 ()
1861{
ead4a3f1 1862 trace_input ("halt", OP_NONE, 0);
d81352b8 1863 State.exception = SIGQUIT;
ead4a3f1 1864 trace_output (OP_NONE);
e98e3b2c
JL		 1865}
1866
1867/* reti, not supported */
1868void
1869OP_14007E0 ()
1870{
ead4a3f1
MM		 1871 trace_input ("reti", OP_NONE, 0);
1872 trace_output (OP_NONE);
e98e3b2c
JL		 1873 abort ();
1874}
1875
1876/* trap, not supportd */
1877void
1878OP_10007E0 ()
1879{
d81352b8
JL		 1880 extern int errno;
1881
ead4a3f1
MM		 1882 trace_input ("trap", OP_TRAP, 0);
1883 trace_output (OP_TRAP);
1884
d81352b8
JL		 1885 /* Trap 0 is used for simulating low-level I/O */
1886
1887 if (OP[0] == 0)
1888 {
d81352b8
JL		 1889 int save_errno = errno;
1890 errno = 0;
1891
1892/* Registers passed to trap 0 */
1893
1894#define FUNC State.regs[6] /* function number, return value */
1895#define PARM1 State.regs[7] /* optional parm 1 */
1896#define PARM2 State.regs[8] /* optional parm 2 */
1897#define PARM3 State.regs[9] /* optional parm 3 */
1898
1899/* Registers set by trap 0 */
1900
1901#define RETVAL State.regs[10] /* return value */
1902#define RETERR State.regs[11] /* return error code */
1903
1904/* Turn a pointer in a register into a pointer into real memory. */
1905
1906#define MEMPTR(x) ((char *)((x) + State.mem))
1907
1908
1909 switch (FUNC)
1910 {
d81352b8
JL		 1911#if !defined(__GO32__) && !defined(_WIN32)
1912 case SYS_fork:
1913 RETVAL = fork ();
1914 break;
1915 case SYS_execve:
1916 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1917 (char **)MEMPTR (PARM3));
1918 break;
1919 case SYS_execv:
1920 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
1921 break;
9909e232 1922#if 0
d81352b8
JL		 1923 case SYS_pipe:
1924 {
1925 reg_t buf;
1926 int host_fd[2];
1927
1928 buf = PARM1;
1929 RETVAL = pipe (host_fd);
1930 SW (buf, host_fd[0]);
1931 buf += sizeof(uint16);
1932 SW (buf, host_fd[1]);
1933 }
1934 break;
1935
1936 case SYS_wait:
1937 {
1938 int status;
1939
1940 RETVAL = wait (&status);
1941 SW (PARM1, status);
1942 }
1943 break;
9909e232 1944#endif
d81352b8
JL		 1945#endif
1946
1947 case SYS_read:
1948 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
1949 PARM3);
1950 break;
d81352b8
JL		 1951 case SYS_write:
1952 if (PARM1 == 1)
1953 RETVAL = (int)v850_callback->write_stdout (v850_callback,
1954 MEMPTR (PARM2), PARM3);
1955 else
1956 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
1957 MEMPTR (PARM2), PARM3);
1958 break;
d81352b8
JL		 1959 case SYS_lseek:
1960 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
1961 break;
1962 case SYS_close:
1963 RETVAL = v850_callback->close (v850_callback, PARM1);
1964 break;
1965 case SYS_open:
1966 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
1967 break;
d81352b8
JL		 1968 case SYS_exit:
1969 /* EXIT - caller can look in PARM1 to work out the
1970 reason */
1971 if (PARM1 == 0xdead || PARM1 == 0x1)
1972 State.exception = SIGABRT;
1973 else
1974 State.exception = SIGQUIT;
1975 break;
1976
1977#if 0
1978 case SYS_stat: /* added at hmsi */
1979 /* stat system call */
1980 {
1981 struct stat host_stat;
1982 reg_t buf;
1983
1984 RETVAL = stat (MEMPTR (PARM1), &host_stat);
1985
1986 buf = PARM2;
1987
1988 /* The hard-coded offsets and sizes were determined by using
1989 * the D10V compiler on a test program that used struct stat.
1990 */
1991 SW (buf, host_stat.st_dev);
1992 SW (buf+2, host_stat.st_ino);
1993 SW (buf+4, host_stat.st_mode);
1994 SW (buf+6, host_stat.st_nlink);
1995 SW (buf+8, host_stat.st_uid);
1996 SW (buf+10, host_stat.st_gid);
1997 SW (buf+12, host_stat.st_rdev);
1998 SLW (buf+16, host_stat.st_size);
1999 SLW (buf+20, host_stat.st_atime);
2000 SLW (buf+28, host_stat.st_mtime);
2001 SLW (buf+36, host_stat.st_ctime);
2002 }
9909e232 2003#endif
d81352b8
JL		 2004 break;
2005
2006 case SYS_chown:
2007 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2008 break;
2009 case SYS_chmod:
2010 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2011 break;
2012 case SYS_utime:
2013 /* Cast the second argument to void *, to avoid type mismatch
2014 if a prototype is present. */
2015 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2016 break;
d81352b8
JL		 2017 default:
2018 abort ();
2019 }
2020 RETERR = errno;
2021 errno = save_errno;
d81352b8
JL		 2022 }
2023 else if (OP[0] == 1 )
2024 {
2025 char *fstr = State.regs[2] + State.mem;
2026 puts (fstr);
2027 }
e98e3b2c
JL		 2028}
2029
614f1c68 2030/* ldsr, reg,reg */
e98e3b2c
JL		 2031void
2032OP_2007E0 ()
2033{
614f1c68
JL		 2034 unsigned int op0;
2035
ead4a3f1 2036 trace_input ("ldsr", OP_LDSR, 0);
614f1c68
JL		 2037 op0 = State.regs[OP[0]];
2038 State.sregs[OP[1]] = op0;
ead4a3f1 2039 trace_output (OP_LDSR);
e98e3b2c
JL		 2040}
2041
2042/* stsr, not supported */
2043void
2044OP_4007E0 ()
2045{
614f1c68
JL		 2046 unsigned int op0;
2047
ead4a3f1 2048 trace_input ("stsr", OP_STSR, 0);
614f1c68
JL		 2049 op0 = State.sregs[OP[1]];
2050 State.regs[OP[0]] = op0;
ead4a3f1 2051 trace_output (OP_STSR);
e98e3b2c 2052}
GDB Binutils - Deliverables
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