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NUMBERS_WITH_SUFFIX *doesn't* want to handle 'x', since that is valid
[deliverable/binutils-gdb.git] / sim / v850 / v850.igen
CommitLineData
c906108c
SS		 1:option:::insn-bit-size:16
2:option:::hi-bit-nr:15
3
4
5:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6:option:::format-names:XI,XII,XIII
7:option:::format-names:XIV,XV
8:option:::format-names:Z
9
10
11:model:::v850:v850:
12
13:option:::multi-sim:true
14:model:::v850e:v850e:
15
16:option:::multi-sim:true
17:model:::v850ea:v850ea:
18
19
20
21// Cache macros
22
23:cache:::unsigned:reg1:RRRRR:(RRRRR)
24:cache:::unsigned:reg2:rrrrr:(rrrrr)
25:cache:::unsigned:reg3:wwwww:(wwwww)
26
27:cache:::unsigned:disp4:dddd:(dddd)
28:cache:::unsigned:disp5:dddd:(dddd << 1)
29:cache:::unsigned:disp7:ddddddd:ddddddd
30:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
31:cache:::unsigned:disp8:dddddd:(dddddd << 2)
32:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
33:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
34:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
35:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
36
37:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
38:cache:::unsigned:imm6:iiiiii:iiiiii
39:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
40:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
41:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
42:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
43:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
44:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
45
46:cache:::unsigned:vector:iiiii:iiiii
47
48:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
49:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
50
51:cache:::unsigned:bit3:bbb:bbb
52
53
54// What do we do with an illegal instruction?
55:internal::::illegal:
56{
57 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
58 (unsigned long) cia);
59 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
60}
61
62
63
64// Add
65
66rrrrr,001110,RRRRR:I:::add
67"add r<reg1>, r<reg2>"
68{
69 COMPAT_1 (OP_1C0 ());
70}
71
72rrrrr,010010,iiiii:II:::add
73"add <imm5>,r<reg2>"
74{
75 COMPAT_1 (OP_240 ());
76}
77
78
79
80// ADDI
81rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
82"addi <simm16>, r<reg1>, r<reg2>"
83{
84 COMPAT_2 (OP_600 ());
85}
86
87
88
89// AND
90rrrrr,001010,RRRRR:I:::and
91"and r<reg1>, r<reg2>"
92{
93 COMPAT_1 (OP_140 ());
94}
95
96
97
98// ANDI
99rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
100"andi <uimm16>, r<reg1>, r<reg2>"
101{
102 COMPAT_2 (OP_6C0 ());
103}
104
105
106
107// Map condition code to a string
108:%s::::cccc:int cccc
109{
110 switch (cccc)
111 {
112 case 0xf: return "gt";
113 case 0xe: return "ge";
114 case 0x6: return "lt";
115
116 case 0x7: return "le";
117
118 case 0xb: return "h";
119 case 0x9: return "nl";
120 case 0x1: return "l";
121
122 case 0x3: return "nh";
123
124 case 0x2: return "e";
125
126 case 0xa: return "ne";
127
128 case 0x0: return "v";
129 case 0x8: return "nv";
130 case 0x4: return "n";
131 case 0xc: return "p";
132 /* case 0x1: return "c"; */
133 /* case 0x9: return "nc"; */
134 /* case 0x2: return "z"; */
135 /* case 0xa: return "nz"; */
136 case 0x5: return "r"; /* always */
137 case 0xd: return "sa";
138 }
139 return "(null)";
140}
141
142
143// Bcond
144ddddd,1011,ddd,cccc:III:::Bcond
145"b%s<cccc> <disp9>"
146{
147 int cond = condition_met (cccc);
148 if (cond)
149 nia = cia + disp9;
150 TRACE_BRANCH1 (cond);
151}
152
153
154
155// BSH
156rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
157*v850e
158*v850ea
159"bsh r<reg2>, r<reg3>"
160{
161 unsigned32 value;
162 TRACE_ALU_INPUT1 (GR[reg2]);
163
164 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
165 | MOVED32 (GR[reg2], 31, 24, 23, 16)
166 | MOVED32 (GR[reg2], 7, 0, 15, 8)
167 | MOVED32 (GR[reg2], 15, 8, 7, 0));
168
169 GR[reg3] = value;
170 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
171 if (value == 0) PSW |= PSW_Z;
172 if (value & 0x80000000) PSW |= PSW_S;
173 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
174
175 TRACE_ALU_RESULT (GR[reg3]);
176}
177
178// BSW
179rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
180*v850e
181*v850ea
182"bsw r<reg2>, r<reg3>"
183{
184#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
185 unsigned32 value;
186 TRACE_ALU_INPUT1 (GR[reg2]);
187
188 value = GR[reg2];
189 value >>= 24;
190 value |= (GR[reg2] << 24);
191 value |= ((GR[reg2] << 8) & 0x00ff0000);
192 value |= ((GR[reg2] >> 8) & 0x0000ff00);
193 GR[reg3] = value;
194
195 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
196
197 if (value == 0) PSW |= PSW_Z;
198 if (value & 0x80000000) PSW |= PSW_S;
199 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
200
201 TRACE_ALU_RESULT (GR[reg3]);
202}
203
204// CALLT
2050000001000,iiiiii:II:::callt
206*v850e
207*v850ea
208"callt <imm6>"
209{
210 unsigned32 adr;
211 unsigned32 off;
212 CTPC = cia + 2;
213 CTPSW = PSW;
214 adr = (CTBP & ~1) + (imm6 << 1);
215 off = load_mem (adr, 2) & ~1; /* Force alignment */
216 nia = (CTBP & ~1) + off;
217 TRACE_BRANCH3 (adr, CTBP, off);
218}
219
220
221// CLR1
22210,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
223"clr1 <bit3>, <disp16>[r<reg1>]"
224{
225 COMPAT_2 (OP_87C0 ());
226}
227
228rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
229*v850e
230*v850ea
231"clr1 r<reg2>, [r<reg1>]"
232{
233 COMPAT_2 (OP_E407E0 ());
234}
235
236
237// CTRET
2380000011111100000 + 0000000101000100:X:::ctret
239*v850e
240*v850ea
241"ctret"
242{
243 nia = (CTPC & ~1);
244 PSW = (CTPSW & (CPU)->psw_mask);
245 TRACE_BRANCH1 (PSW);
246}
247
248// CMOV
249rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
250*v850e
251*v850ea
252"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
253{
254 int cond = condition_met (cccc);
255 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
256 GR[reg3] = cond ? GR[reg1] : GR[reg2];
257 TRACE_ALU_RESULT (GR[reg3]);
258}
259
260rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
261*v850e
262*v850ea
263"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
264{
265 int cond = condition_met (cccc);
266 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
267 GR[reg3] = cond ? imm5 : GR[reg2];
268 TRACE_ALU_RESULT (GR[reg3]);
269}
270
271// CMP
272rrrrr,001111,RRRRR:I:::cmp
273"cmp r<reg1>, r<reg2>"
274{
275 COMPAT_1 (OP_1E0 ());
276}
277
278rrrrr,010011,iiiii:II:::cmp
279"cmp <imm5>, r<reg2>"
280{
281 COMPAT_1 (OP_260 ());
282}
283
284
285
286// DI
2870000011111100000 + 0000000101100000:X:::di
288"di"
289{
290 COMPAT_2 (OP_16007E0 ());
291}
292
293
294
295// DISPOSE
296// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
297// "dispose <imm5>, <list12>"
2980000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
299*v850e
300*v850ea
301"dispose <imm5>, <list12>":RRRRR == 0
302"dispose <imm5>, <list12>, [reg1]"
303{
304 int i;
305 SAVE_2;
306
307 trace_input ("dispose", OP_PUSHPOP1, 0);
308
309 SP += (OP[3] & 0x3e) << 1;
310
311 /* Load the registers with lower number registers being retrieved
312 from higher addresses. */
313 for (i = 12; i--;)
314 if ((OP[3] & (1 << type1_regs[ i ])))
315 {
316 State.regs[ 20 + i ] = load_mem (SP, 4);
317 SP += 4;
318 }
319
320 if ((OP[3] & 0x1f0000) != 0)
321 {
322 nia = State.regs[ (OP[3] >> 16) & 0x1f];
323 }
324
325 trace_output (OP_PUSHPOP1);
326}
327
328
329// DIV
330rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
331*v850e
332"div r<reg1>, r<reg2>, r<reg3>"
333{
334 COMPAT_2 (OP_2C007E0 ());
335}
336
337
338// DIVH
339rrrrr!0,000010,RRRRR!0:I:::divh
340"divh r<reg1>, r<reg2>"
341{
342 COMPAT_1 (OP_40 ());
343}
344
345rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
346*v850e
347"divh r<reg1>, r<reg2>, r<reg3>"
348{
349 COMPAT_2 (OP_28007E0 ());
350}
351
352
353// DIVHU
354rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
355*v850e
356"divhu r<reg1>, r<reg2>, r<reg3>"
357{
358 COMPAT_2 (OP_28207E0 ());
359}
360
361
362// DIVU
363rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
364*v850e
365"divu r<reg1>, r<reg2>, r<reg3>"
366{
367 COMPAT_2 (OP_2C207E0 ());
368}
369
370
371// EI
3721000011111100000 + 0000000101100000:X:::ei
373"ei"
374{
375 COMPAT_2 (OP_16087E0 ());
376}
377
378
379
380// HALT
3810000011111100000 + 0000000100100000:X:::halt
382"halt"
383{
384 COMPAT_2 (OP_12007E0 ());
385}
386
387
388
389// HSW
390rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
391*v850e
392*v850ea
393"hsw r<reg2>, r<reg3>"
394{
395 unsigned32 value;
396 TRACE_ALU_INPUT1 (GR[reg2]);
397
398 value = GR[reg2];
399 value >>= 16;
400 value |= (GR[reg2] << 16);
401
402 GR[reg3] = value;
403
404 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
405
406 if (value == 0) PSW |= PSW_Z;
407 if (value & 0x80000000) PSW |= PSW_S;
408 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
409
410 TRACE_ALU_RESULT (GR[reg3]);
411}
412
413
414
415// JARL
416rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
417"jarl <disp22>, r<reg2>"
418{
419 GR[reg2] = nia;
420 nia = cia + disp22;
421 TRACE_BRANCH1 (GR[reg2]);
422}
423
424
425
426// JMP
42700000000011,RRRRR:I:::jmp
428"jmp [r<reg1>]"
429{
430 nia = GR[reg1] & ~1;
431 TRACE_BRANCH0 ();
432}
433
434
435
436// JR
4370000011110,dddddd + ddddddddddddddd,0:V:::jr
438"jr <disp22>"
439{
440 nia = cia + disp22;
441 TRACE_BRANCH0 ();
442}
443
444
445
446// LD
447rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
448"ld.b <disp16>[r<reg1>], r<reg2>"
449{
450 COMPAT_2 (OP_700 ());
451}
452
453rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
454"ld.h <disp16>[r<reg1>], r<reg2>"
455{
456 COMPAT_2 (OP_720 ());
457}
458
459rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
460"ld.w <disp16>[r<reg1>], r<reg2>"
461{
462 COMPAT_2 (OP_10720 ());
463}
464
465rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
466*v850e
467*v850ea
468"ld.bu <disp16>[r<reg1>], r<reg2>"
469{
470 COMPAT_2 (OP_10780 ());
471}
472
473rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
474*v850e
475*v850ea
476"ld.hu <disp16>[r<reg1>], r<reg2>"
477{
478 COMPAT_2 (OP_107E0 ());
479}
480
481
482// LDSR
483regID,111111,RRRRR + 0000000000100000:IX:::ldsr
484"ldsr r<reg1>, s<regID>"
485{
486 TRACE_ALU_INPUT1 (GR[reg1]);
487
488 if (&PSW == &SR[regID])
489 PSW = (GR[reg1] & (CPU)->psw_mask);
490 else
491 SR[regID] = GR[reg1];
492
493 TRACE_ALU_RESULT (SR[regID]);
494}
495
496
497
498// MOV
499rrrrr!0,000000,RRRRR:I:::mov
500"mov r<reg1>, r<reg2>"
501{
502 TRACE_ALU_INPUT0 ();
503 GR[reg2] = GR[reg1];
504 TRACE_ALU_RESULT (GR[reg2]);
505}
506
507
508rrrrr!0,010000,iiiii:II:::mov
509"mov <imm5>, r<reg2>"
510{
511 COMPAT_1 (OP_200 ());
512}
513
51400000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
515*v850e
516*v850ea
517"mov <imm32>, r<reg1>"
518{
519 SAVE_2;
520 trace_input ("mov", OP_IMM_REG, 4);
521 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
522 trace_output (OP_IMM_REG);
523}
524
525
526
527// MOVEA
528rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
529"movea <simm16>, r<reg1>, r<reg2>"
530{
531 TRACE_ALU_INPUT2 (GR[reg1], simm16);
532 GR[reg2] = GR[reg1] + simm16;
533 TRACE_ALU_RESULT (GR[reg2]);
534}
535
536
537
538// MOVHI
539rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
540"movhi <uimm16>, r<reg1>, r<reg2>"
541{
542 COMPAT_2 (OP_640 ());
543}
544
545
546
547// MUL
548rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
549*v850e
550*v850ea
551"mul r<reg1>, r<reg2>, r<reg3>"
552{
553 COMPAT_2 (OP_22007E0 ());
554}
555
556rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
557*v850e
558*v850ea
559"mul <imm9>, r<reg2>, r<reg3>"
560{
561 COMPAT_2 (OP_24007E0 ());
562}
563
564
565// MULH
566rrrrr!0,000111,RRRRR:I:::mulh
567"mulh r<reg1>, r<reg2>"
568{
569 COMPAT_1 (OP_E0 ());
570}
571
572rrrrr!0,010111,iiiii:II:::mulh
573"mulh <imm5>, r<reg2>"
574{
575 COMPAT_1 (OP_2E0 ());
576}
577
578
579
580// MULHI
581rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
582"mulhi <uimm16>, r<reg1>, r<reg2>"
583{
584 COMPAT_2 (OP_6E0 ());
585}
586
587
588
589// MULU
590rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
591*v850e
592*v850ea
593"mulu r<reg1>, r<reg2>, r<reg3>"
594{
595 COMPAT_2 (OP_22207E0 ());
596}
597
598rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
599*v850e
600*v850ea
601"mulu <imm9>, r<reg2>, r<reg3>"
602{
603 COMPAT_2 (OP_24207E0 ());
604}
605
606
607
608// NOP
6090000000000000000:I:::nop
610"nop"
611{
612 /* do nothing, trace nothing */
613}
614
615
616
617// NOT
618rrrrr,000001,RRRRR:I:::not
619"not r<reg1>, r<reg2>"
620{
621 COMPAT_1 (OP_20 ());
622}
623
624
625
626// NOT1
62701,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
628"not1 <bit3>, <disp16>[r<reg1>]"
629{
630 COMPAT_2 (OP_47C0 ());
631}
632
633rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
634*v850e
635*v850ea
636"not1 r<reg2>, r<reg1>"
637{
638 COMPAT_2 (OP_E207E0 ());
639}
640
641
642
643// OR
644rrrrr,001000,RRRRR:I:::or
645"or r<reg1>, r<reg2>"
646{
647 COMPAT_1 (OP_100 ());
648}
649
650
651
652// ORI
653rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
654"ori <uimm16>, r<reg1>, r<reg2>"
655{
656 COMPAT_2 (OP_680 ());
657}
658
659
660
661// PREPARE
6620000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
663*v850e
664*v850ea
665"prepare <list12>, <imm5>"
666{
667 int i;
668 SAVE_2;
669
670 trace_input ("prepare", OP_PUSHPOP1, 0);
671
672 /* Store the registers with lower number registers being placed at
673 higher addresses. */
674 for (i = 0; i < 12; i++)
675 if ((OP[3] & (1 << type1_regs[ i ])))
676 {
677 SP -= 4;
678 store_mem (SP, 4, State.regs[ 20 + i ]);
679 }
680
681 SP -= (OP[3] & 0x3e) << 1;
682
683 trace_output (OP_PUSHPOP1);
684}
685
686
6870000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
688*v850e
689*v850ea
690"prepare <list12>, <imm5>, sp"
691{
692 COMPAT_2 (OP_30780 ());
693}
694
6950000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
696*v850e
697*v850ea
698"prepare <list12>, <imm5>, <uimm16>"
699{
700 COMPAT_2 (OP_B0780 ());
701}
702
7030000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
704*v850e
705*v850ea
706"prepare <list12>, <imm5>, <uimm16>"
707{
708 COMPAT_2 (OP_130780 ());
709}
710
7110000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
712*v850e
713*v850ea
714"prepare <list12>, <imm5>, <uimm32>"
715{
716 COMPAT_2 (OP_1B0780 ());
717}
718
719
720
721// RETI
7220000011111100000 + 0000000101000000:X:::reti
723"reti"
724{
725 if ((PSW & PSW_EP))
726 {
727 nia = (EIPC & ~1);
728 PSW = EIPSW;
729 }
730 else if ((PSW & PSW_NP))
731 {
732 nia = (FEPC & ~1);
733 PSW = FEPSW;
734 }
735 else
736 {
737 nia = (EIPC & ~1);
738 PSW = EIPSW;
739 }
740 TRACE_BRANCH1 (PSW);
741}
742
743
744
745// SAR
746rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
747"sar r<reg1>, r<reg2>"
748{
749 COMPAT_2 (OP_A007E0 ());
750}
751
752rrrrr,010101,iiiii:II:::sar
753"sar <imm5>, r<reg2>"
754{
755 COMPAT_1 (OP_2A0 ());
756}
757
758
759
760// SASF
761rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
762*v850e
763*v850ea
764"sasf %s<cccc>, r<reg2>"
765{
766 COMPAT_2 (OP_20007E0 ());
767}
768
769
770
771
772// SATADD
773rrrrr!0,000110,RRRRR:I:::satadd
774"satadd r<reg1>, r<reg2>"
775{
776 COMPAT_1 (OP_C0 ());
777}
778
779rrrrr!0,010001,iiiii:II:::satadd
780"satadd <imm5>, r<reg2>"
781{
782 COMPAT_1 (OP_220 ());
783}
784
785
786
787// SATSUB
788rrrrr!0,000101,RRRRR:I:::satsub
789"satsub r<reg1>, r<reg2>"
790{
791 COMPAT_1 (OP_A0 ());
792}
793
794
795
796// SATSUBI
797rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
798"satsubi <simm16>, r<reg1>, r<reg2>"
799{
800 COMPAT_2 (OP_660 ());
801}
802
803
804
805// SATSUBR
806rrrrr!0,000100,RRRRR:I:::satsubr
807"satsubr r<reg1>, r<reg2>"
808{
809 COMPAT_1 (OP_80 ());
810}
811
812
813
814// SETF
815rrrrr,1111110,cccc + 0000000000000000:IX:::setf
816"setf %s<cccc>, r<reg2>"
817{
818 COMPAT_2 (OP_7E0 ());
819}
820
821
822
823// SET1
82400,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
825"set1 <bit3>, <disp16>[r<reg1>]"
826{
827 COMPAT_2 (OP_7C0 ());
828}
829
830rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
831*v850e
832*v850ea
833"set1 r<reg2>, [r<reg1>]"
834{
835 COMPAT_2 (OP_E007E0 ());
836}
837
838
839
840// SHL
841rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
842"shl r<reg1>, r<reg2>"
843{
844 COMPAT_2 (OP_C007E0 ());
845}
846
847rrrrr,010110,iiiii:II:::shl
848"shl <imm5>, r<reg2>"
849{
850 COMPAT_1 (OP_2C0 ());
851}
852
853
854
855// SHR
856rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
857"shr r<reg1>, r<reg2>"
858{
859 COMPAT_2 (OP_8007E0 ());
860}
861
862rrrrr,010100,iiiii:II:::shr
863"shr <imm5>, r<reg2>"
864{
865 COMPAT_1 (OP_280 ());
866}
867
868
869
870// SLD
871rrrrr,0110,ddddddd:IV:::sld.b
872"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
873"sld.b <disp7>[ep], r<reg2>"
874{
875 unsigned32 addr = EP + disp7;
876 unsigned32 result = load_mem (addr, 1);
877 if (PSW & PSW_US)
878 {
879 GR[reg2] = result;
880 TRACE_LD_NAME ("sld.bu", addr, result);
881 }
882 else
883 {
884 result = EXTEND8 (result);
885 GR[reg2] = result;
886 TRACE_LD (addr, result);
887 }
888}
889
890rrrrr,1000,ddddddd:IV:::sld.h
891"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
892"sld.h <disp8>[ep], r<reg2>"
893{
894 unsigned32 addr = EP + disp8;
895 unsigned32 result = load_mem (addr, 2);
896 if (PSW & PSW_US)
897 {
898 GR[reg2] = result;
899 TRACE_LD_NAME ("sld.hu", addr, result);
900 }
901 else
902 {
903 result = EXTEND16 (result);
904 GR[reg2] = result;
905 TRACE_LD (addr, result);
906 }
907}
908
909rrrrr,1010,dddddd,0:IV:::sld.w
910"sld.w <disp8>[ep], r<reg2>"
911{
912 unsigned32 addr = EP + disp8;
913 unsigned32 result = load_mem (addr, 4);
914 GR[reg2] = result;
915 TRACE_LD (addr, result);
916}
917
918rrrrr!0,0000110,dddd:IV:::sld.bu
919*v850e
920*v850ea
921"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
922"sld.bu <disp4>[ep], r<reg2>"
923{
924 unsigned32 addr = EP + disp4;
925 unsigned32 result = load_mem (addr, 1);
926 if (PSW & PSW_US)
927 {
928 result = EXTEND8 (result);
929 GR[reg2] = result;
930 TRACE_LD_NAME ("sld.b", addr, result);
931 }
932 else
933 {
934 GR[reg2] = result;
935 TRACE_LD (addr, result);
936 }
937}
938
939rrrrr!0,0000111,dddd:IV:::sld.hu
940*v850e
941*v850ea
942"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
943"sld.hu <disp5>[ep], r<reg2>"
944{
945 unsigned32 addr = EP + disp5;
946 unsigned32 result = load_mem (addr, 2);
947 if (PSW & PSW_US)
948 {
949 result = EXTEND16 (result);
950 GR[reg2] = result;
951 TRACE_LD_NAME ("sld.h", addr, result);
952 }
953 else
954 {
955 GR[reg2] = result;
956 TRACE_LD (addr, result);
957 }
958}
959
960
961// SST
962rrrrr,0111,ddddddd:IV:::sst.b
963"sst.b r<reg2>, <disp7>[ep]"
964{
965 COMPAT_1 (OP_380 ());
966}
967
968rrrrr,1001,ddddddd:IV:::sst.h
969"sst.h r<reg2>, <disp8>[ep]"
970{
971 COMPAT_1 (OP_480 ());
972}
973
974rrrrr,1010,dddddd,1:IV:::sst.w
975"sst.w r<reg2>, <disp8>[ep]"
976{
977 COMPAT_1 (OP_501 ());
978}
979
980
981
982// ST
983rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
984"st.b r<reg2>, <disp16>[r<reg1>]"
985{
986 COMPAT_2 (OP_740 ());
987}
988
989rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
990"st.h r<reg2>, <disp16>[r<reg1>]"
991{
992 COMPAT_2 (OP_760 ());
993}
994
995rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
996"st.w r<reg2>, <disp16>[r<reg1>]"
997{
998 COMPAT_2 (OP_10760 ());
999}
1000
1001
1002
1003// STSR
1004rrrrr,111111,regID + 0000000001000000:IX:::stsr
1005"stsr s<regID>, r<reg2>"
1006{
1007 TRACE_ALU_INPUT1 (SR[regID]);
1008 GR[reg2] = SR[regID];
1009 TRACE_ALU_RESULT (GR[reg2]);
1010}
1011
1012
1013
1014// SUB
1015rrrrr,001101,RRRRR:I:::sub
1016"sub r<reg1>, r<reg2>"
1017{
1018 COMPAT_1 (OP_1A0 ());
1019}
1020
1021
1022
1023// SUBR
1024rrrrr,001100,RRRRR:I:::subr
1025"subr r<reg1>, r<reg2>"
1026{
1027 COMPAT_1 (OP_180 ());
1028}
1029
1030
1031
1032// SWITCH
103300000000010,RRRRR:I:::switch
1034*v850e
1035*v850ea
1036"switch r<reg1>"
1037{
1038 unsigned long adr;
1039 SAVE_1;
1040 trace_input ("switch", OP_REG, 0);
1041 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1042 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1043 trace_output (OP_REG);
1044}
1045
1046
1047// SXB
104800000000101,RRRRR:I:::sxb
1049*v850e
1050*v850ea
1051"sxb r<reg1>"
1052{
1053 TRACE_ALU_INPUT1 (GR[reg1]);
1054 GR[reg1] = EXTEND8 (GR[reg1]);
1055 TRACE_ALU_RESULT (GR[reg1]);
1056}
1057
1058// SXH
105900000000111,RRRRR:I:::sxh
1060*v850e
1061*v850ea
1062"sxh r<reg1>"
1063{
1064 TRACE_ALU_INPUT1 (GR[reg1]);
1065 GR[reg1] = EXTEND16 (GR[reg1]);
1066 TRACE_ALU_RESULT (GR[reg1]);
1067}
1068
1069
1070
1071// TRAP
107200000111111,iiiii + 0000000100000000:X:::trap
1073"trap <vector>"
1074{
1075 COMPAT_2 (OP_10007E0 ());
1076}
1077
1078
1079
1080// TST
1081rrrrr,001011,RRRRR:I:::tst
1082"tst r<reg1>, r<reg2>"
1083{
1084 COMPAT_1 (OP_160 ());
1085}
1086
1087
1088
1089// TST1
109011,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1091"tst1 <bit3>, <disp16>[r<reg1>]"
1092{
1093 COMPAT_2 (OP_C7C0 ());
1094}
1095
1096rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1097*v850e
1098*v850ea
1099"tst1 r<reg2>, [r<reg1>]"
1100{
1101 COMPAT_2 (OP_E607E0 ());
1102}
1103
1104
1105
1106// XOR
1107rrrrr,001001,RRRRR:I:::xor
1108"xor r<reg1>, r<reg2>"
1109{
1110 COMPAT_1 (OP_120 ());
1111}
1112
1113
1114
1115// XORI
1116rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1117"xori <uimm16>, r<reg1>, r<reg2>"
1118{
1119 COMPAT_2 (OP_6A0 ());
1120}
1121
1122
1123
1124// ZXB
112500000000100,RRRRR:I:::zxb
1126*v850e
1127*v850ea
1128"zxb r<reg1>"
1129{
1130 TRACE_ALU_INPUT1 (GR[reg1]);
1131 GR[reg1] = GR[reg1] & 0xff;
1132 TRACE_ALU_RESULT (GR[reg1]);
1133}
1134
1135// ZXH
113600000000110,RRRRR:I:::zxh
1137*v850e
1138*v850ea
1139"zxh r<reg1>"
1140{
1141 TRACE_ALU_INPUT1 (GR[reg1]);
1142 GR[reg1] = GR[reg1] & 0xffff;
1143 TRACE_ALU_RESULT (GR[reg1]);
1144}
1145
1146
1147// Right field must be zero so that it doesn't clash with DIVH
1148// Left field must be non-zero so that it doesn't clash with SWITCH
114911111,000010,00000:I:::break
1150{
1151 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1152}
1153
1154
1155
1156// DIVHN
1157rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1158*v850ea
1159"divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1160{
1161 signed32 quotient;
1162 signed32 remainder;
1163 signed32 divide_by;
1164 signed32 divide_this;
1165 boolean overflow = false;
1166 SAVE_2;
1167
1168 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1169
1170 divide_by = EXTEND16 (State.regs[ reg1 ]);
1171 divide_this = State.regs[ reg2 ];
1172
1173 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1174
1175 State.regs[ reg2 ] = quotient;
1176 State.regs[ reg3 ] = remainder;
1177
1178 /* Set condition codes. */
1179 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1180
1181 if (overflow) PSW |= PSW_OV;
1182 if (quotient == 0) PSW |= PSW_Z;
1183 if (quotient < 0) PSW |= PSW_S;
1184
1185 trace_output (OP_IMM_REG_REG_REG);
1186}
1187
1188
1189
1190// DIVHUN
1191rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1192*v850ea
1193"divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1194{
1195 signed32 quotient;
1196 signed32 remainder;
1197 signed32 divide_by;
1198 signed32 divide_this;
1199 boolean overflow = false;
1200 SAVE_2;
1201
1202 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1203
1204 divide_by = State.regs[ reg1 ] & 0xffff;
1205 divide_this = State.regs[ reg2 ];
1206
1207 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1208
1209 State.regs[ reg2 ] = quotient;
1210 State.regs[ reg3 ] = remainder;
1211
1212 /* Set condition codes. */
1213 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1214
1215 if (overflow) PSW |= PSW_OV;
1216 if (quotient == 0) PSW |= PSW_Z;
1217 if (quotient & 0x80000000) PSW |= PSW_S;
1218
1219 trace_output (OP_IMM_REG_REG_REG);
1220}
1221
1222
1223
1224// DIVN
1225rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1226*v850ea
1227"divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1228{
1229 signed32 quotient;
1230 signed32 remainder;
1231 signed32 divide_by;
1232 signed32 divide_this;
1233 boolean overflow = false;
1234 SAVE_2;
1235
1236 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1237
1238 divide_by = State.regs[ reg1 ];
1239 divide_this = State.regs[ reg2 ];
1240
1241 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1242
1243 State.regs[ reg2 ] = quotient;
1244 State.regs[ reg3 ] = remainder;
1245
1246 /* Set condition codes. */
1247 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1248
1249 if (overflow) PSW |= PSW_OV;
1250 if (quotient == 0) PSW |= PSW_Z;
1251 if (quotient < 0) PSW |= PSW_S;
1252
1253 trace_output (OP_IMM_REG_REG_REG);
1254}
1255
1256
1257
1258// DIVUN
1259rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1260*v850ea
1261"divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1262{
1263 signed32 quotient;
1264 signed32 remainder;
1265 signed32 divide_by;
1266 signed32 divide_this;
1267 boolean overflow = false;
1268 SAVE_2;
1269
1270 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1271
1272 divide_by = State.regs[ reg1 ];
1273 divide_this = State.regs[ reg2 ];
1274
1275 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1276
1277 State.regs[ reg2 ] = quotient;
1278 State.regs[ reg3 ] = remainder;
1279
1280 /* Set condition codes. */
1281 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1282
1283 if (overflow) PSW |= PSW_OV;
1284 if (quotient == 0) PSW |= PSW_Z;
1285 if (quotient & 0x80000000) PSW |= PSW_S;
1286
1287 trace_output (OP_IMM_REG_REG_REG);
1288}
1289
1290
1291
1292// SDIVHN
1293rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1294*v850ea
1295"sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1296{
1297 COMPAT_2 (OP_18007E0 ());
1298}
1299
1300
1301
1302// SDIVHUN
1303rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1304*v850ea
1305"sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1306{
1307 COMPAT_2 (OP_18207E0 ());
1308}
1309
1310
1311
1312// SDIVN
1313rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1314*v850ea
1315"sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1316{
1317 COMPAT_2 (OP_1C007E0 ());
1318}
1319
1320
1321
1322// SDIVUN
1323rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1324*v850ea
1325"sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1326{
1327 COMPAT_2 (OP_1C207E0 ());
1328}
1329
1330
1331
1332// PUSHML
1333000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1334*v850ea
1335"pushml <list18>"
1336{
1337 int i;
1338 SAVE_2;
1339
1340 trace_input ("pushml", OP_PUSHPOP3, 0);
1341
1342 /* Store the registers with lower number registers being placed at
1343 higher addresses. */
1344
1345 for (i = 0; i < 15; i++)
1346 if ((OP[3] & (1 << type3_regs[ i ])))
1347 {
1348 SP -= 4;
1349 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1350 }
1351
1352 if (OP[3] & (1 << 3))
1353 {
1354 SP -= 4;
1355
1356 store_mem (SP & ~ 3, 4, PSW);
1357 }
1358
1359 if (OP[3] & (1 << 19))
1360 {
1361 SP -= 8;
1362
1363 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1364 {
1365 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1366 store_mem ( SP & ~ 3, 4, FEPSW);
1367 }
1368 else
1369 {
1370 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1371 store_mem ( SP & ~ 3, 4, EIPSW);
1372 }
1373 }
1374
1375 trace_output (OP_PUSHPOP2);
1376}
1377
1378
1379
1380// PUSHHML
1381000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1382*v850ea
1383"pushhml <list18>"
1384{
1385 COMPAT_2 (OP_307E0 ());
1386}
1387
1388
1389
1390// POPML
1391000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1392*v850ea
1393"popml <list18>"
1394{
1395 COMPAT_2 (OP_107F0 ());
1396}
1397
1398
1399
1400// POPMH
1401000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1402*v850ea
1403"popmh <list18>"
1404{
1405 COMPAT_2 (OP_307F0 ());
1406}
1407
GDB Binutils - Deliverables
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