Commit | Line | Data |
---|---|---|
c906108c SS |
1 | :option:::insn-bit-size:16 |
2 | :option:::hi-bit-nr:15 | |
3 | ||
4 | ||
5 | :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X | |
6 | :option:::format-names:XI,XII,XIII | |
7 | :option:::format-names:XIV,XV | |
8 | :option:::format-names:Z | |
2aaed979 | 9 | :option:::format-names:F_I |
c906108c SS |
10 | |
11 | ||
12 | :model:::v850:v850: | |
13 | ||
14 | :option:::multi-sim:true | |
15 | :model:::v850e:v850e: | |
c5ea1d53 NC |
16 | :option:::multi-sim:true |
17 | :model:::v850e1:v850e1: | |
2aaed979 KB |
18 | :option:::multi-sim:true |
19 | :model:::v850e2:v850e2: | |
20 | :option:::multi-sim:true | |
21 | :model:::v850e2v3:v850e2v3: | |
67d7515b NC |
22 | :option:::multi-sim:true |
23 | :model:::v850e3v5:v850e3v5: | |
c906108c | 24 | |
c906108c SS |
25 | // Cache macros |
26 | ||
27 | :cache:::unsigned:reg1:RRRRR:(RRRRR) | |
28 | :cache:::unsigned:reg2:rrrrr:(rrrrr) | |
29 | :cache:::unsigned:reg3:wwwww:(wwwww) | |
d99ff40f | 30 | :cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1)) |
2aaed979 KB |
31 | |
32 | :cache:::unsigned:reg1e:RRRR:(RRRR << 1) | |
33 | :cache:::unsigned:reg2e:rrrr:(rrrr << 1) | |
34 | :cache:::unsigned:reg3e:wwww:(wwww << 1) | |
35 | :cache:::unsigned:reg4e:mmmm:(mmmm << 1) | |
c906108c SS |
36 | |
37 | :cache:::unsigned:disp4:dddd:(dddd) | |
38 | :cache:::unsigned:disp5:dddd:(dddd << 1) | |
39 | :cache:::unsigned:disp7:ddddddd:ddddddd | |
40 | :cache:::unsigned:disp8:ddddddd:(ddddddd << 1) | |
41 | :cache:::unsigned:disp8:dddddd:(dddddd << 2) | |
42 | :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) | |
43 | :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd) | |
44 | :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1) | |
2aaed979 | 45 | :cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1) |
c906108c | 46 | :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1) |
2aaed979 KB |
47 | :cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 - 1) |
48 | :cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), 23 - 1) | |
c906108c SS |
49 | |
50 | :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4) | |
51 | :cache:::unsigned:imm6:iiiiii:iiiiii | |
52 | :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1) | |
53 | :cache:::unsigned:imm5:iiii:(32 - (iiii << 1)) | |
54 | :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii) | |
55 | :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii | |
56 | :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII) | |
57 | :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd) | |
58 | ||
59 | :cache:::unsigned:vector:iiiii:iiiii | |
60 | ||
61 | :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL) | |
62 | :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL) | |
63 | ||
64 | :cache:::unsigned:bit3:bbb:bbb | |
2aaed979 | 65 | :cache:::unsigned:bit4:bbbb:bbbb |
67d7515b | 66 | :cache:::unsigned:bit13:B,BBB:((B << 3) + BBB) |
c906108c SS |
67 | |
68 | ||
69 | // What do we do with an illegal instruction? | |
70 | :internal::::illegal: | |
71 | { | |
72 | sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", | |
73 | (unsigned long) cia); | |
74 | sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); | |
75 | } | |
76 | ||
77 | ||
78 | ||
2aaed979 | 79 | // ADD |
c906108c SS |
80 | rrrrr,001110,RRRRR:I:::add |
81 | "add r<reg1>, r<reg2>" | |
82 | { | |
83 | COMPAT_1 (OP_1C0 ()); | |
84 | } | |
85 | ||
86 | rrrrr,010010,iiiii:II:::add | |
87 | "add <imm5>,r<reg2>" | |
88 | { | |
89 | COMPAT_1 (OP_240 ()); | |
90 | } | |
91 | ||
92 | ||
93 | ||
94 | // ADDI | |
95 | rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi | |
96 | "addi <simm16>, r<reg1>, r<reg2>" | |
97 | { | |
98 | COMPAT_2 (OP_600 ()); | |
99 | } | |
100 | ||
101 | ||
102 | ||
2aaed979 KB |
103 | // ADF |
104 | rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf | |
105 | *v850e2 | |
106 | *v850e2v3 | |
67d7515b | 107 | *v850e3v5 |
2aaed979 KB |
108 | "adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" |
109 | { | |
110 | int cond = condition_met (cccc); | |
111 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
112 | GR[reg3] = GR[reg1] + GR[reg2] + (cond ? 1 : 0); | |
113 | TRACE_ALU_RESULT1 (GR[reg3]); | |
114 | } | |
115 | ||
116 | ||
117 | ||
c906108c SS |
118 | // AND |
119 | rrrrr,001010,RRRRR:I:::and | |
120 | "and r<reg1>, r<reg2>" | |
121 | { | |
122 | COMPAT_1 (OP_140 ()); | |
123 | } | |
124 | ||
125 | ||
126 | ||
127 | // ANDI | |
128 | rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi | |
129 | "andi <uimm16>, r<reg1>, r<reg2>" | |
130 | { | |
131 | COMPAT_2 (OP_6C0 ()); | |
132 | } | |
133 | ||
134 | ||
135 | ||
136 | // Map condition code to a string | |
137 | :%s::::cccc:int cccc | |
138 | { | |
139 | switch (cccc) | |
140 | { | |
141 | case 0xf: return "gt"; | |
142 | case 0xe: return "ge"; | |
143 | case 0x6: return "lt"; | |
144 | ||
145 | case 0x7: return "le"; | |
146 | ||
147 | case 0xb: return "h"; | |
148 | case 0x9: return "nl"; | |
149 | case 0x1: return "l"; | |
150 | ||
151 | case 0x3: return "nh"; | |
152 | ||
153 | case 0x2: return "e"; | |
154 | ||
155 | case 0xa: return "ne"; | |
156 | ||
157 | case 0x0: return "v"; | |
158 | case 0x8: return "nv"; | |
159 | case 0x4: return "n"; | |
160 | case 0xc: return "p"; | |
161 | /* case 0x1: return "c"; */ | |
162 | /* case 0x9: return "nc"; */ | |
163 | /* case 0x2: return "z"; */ | |
164 | /* case 0xa: return "nz"; */ | |
165 | case 0x5: return "r"; /* always */ | |
166 | case 0xd: return "sa"; | |
167 | } | |
168 | return "(null)"; | |
169 | } | |
170 | ||
171 | ||
172 | // Bcond | |
173 | ddddd,1011,ddd,cccc:III:::Bcond | |
174 | "b%s<cccc> <disp9>" | |
175 | { | |
b9791fcd FCE |
176 | int cond; |
177 | if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) { | |
178 | // Special case - treat "br *" like illegal instruction | |
179 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
180 | } else { | |
181 | cond = condition_met (cccc); | |
182 | if (cond) | |
183 | nia = cia + disp9; | |
184 | TRACE_BRANCH1 (cond); | |
185 | } | |
c906108c SS |
186 | } |
187 | ||
2aaed979 KB |
188 | 00000111111,d,cccc + ddddddddddddddd,1:VII:::Bcond |
189 | "breakpoint":((disp17 == 0) && (cccc == 0x05)) | |
190 | "b%s<cccc> <disp17>" | |
191 | *v850e2v3 | |
67d7515b | 192 | *v850e3v5 |
2aaed979 KB |
193 | { |
194 | int cond; | |
195 | cond = condition_met (cccc); | |
196 | if (cond) | |
197 | nia = cia + disp17; | |
198 | TRACE_BRANCH_INPUT1 (cond); | |
199 | TRACE_BRANCH_RESULT (nia); | |
200 | } | |
201 | ||
c906108c SS |
202 | |
203 | ||
204 | // BSH | |
205 | rrrrr,11111100000 + wwwww,01101000010:XII:::bsh | |
206 | *v850e | |
c5ea1d53 | 207 | *v850e1 |
2aaed979 KB |
208 | *v850e2 |
209 | *v850e2v3 | |
67d7515b | 210 | *v850e3v5 |
c906108c SS |
211 | "bsh r<reg2>, r<reg3>" |
212 | { | |
213 | unsigned32 value; | |
214 | TRACE_ALU_INPUT1 (GR[reg2]); | |
215 | ||
216 | value = (MOVED32 (GR[reg2], 23, 16, 31, 24) | |
217 | | MOVED32 (GR[reg2], 31, 24, 23, 16) | |
218 | | MOVED32 (GR[reg2], 7, 0, 15, 8) | |
219 | | MOVED32 (GR[reg2], 15, 8, 7, 0)); | |
220 | ||
221 | GR[reg3] = value; | |
222 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
c5fbc25b | 223 | if ((value & 0xffff) == 0) PSW |= PSW_Z; |
c906108c | 224 | if (value & 0x80000000) PSW |= PSW_S; |
c5fbc25b | 225 | if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY; |
c906108c SS |
226 | |
227 | TRACE_ALU_RESULT (GR[reg3]); | |
228 | } | |
229 | ||
2aaed979 KB |
230 | |
231 | ||
c906108c SS |
232 | // BSW |
233 | rrrrr,11111100000 + wwwww,01101000000:XII:::bsw | |
234 | *v850e | |
c5ea1d53 | 235 | *v850e1 |
2aaed979 KB |
236 | *v850e2 |
237 | *v850e2v3 | |
67d7515b | 238 | *v850e3v5 |
c906108c SS |
239 | "bsw r<reg2>, r<reg3>" |
240 | { | |
241 | #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) | |
242 | unsigned32 value; | |
243 | TRACE_ALU_INPUT1 (GR[reg2]); | |
244 | ||
245 | value = GR[reg2]; | |
246 | value >>= 24; | |
247 | value |= (GR[reg2] << 24); | |
248 | value |= ((GR[reg2] << 8) & 0x00ff0000); | |
249 | value |= ((GR[reg2] >> 8) & 0x0000ff00); | |
250 | GR[reg3] = value; | |
251 | ||
252 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
253 | ||
254 | if (value == 0) PSW |= PSW_Z; | |
255 | if (value & 0x80000000) PSW |= PSW_S; | |
256 | if (WORDHASNULLBYTE (value)) PSW |= PSW_CY; | |
257 | ||
258 | TRACE_ALU_RESULT (GR[reg3]); | |
259 | } | |
260 | ||
2aaed979 KB |
261 | |
262 | ||
c906108c SS |
263 | // CALLT |
264 | 0000001000,iiiiii:II:::callt | |
265 | *v850e | |
c5ea1d53 | 266 | *v850e1 |
2aaed979 KB |
267 | *v850e2 |
268 | *v850e2v3 | |
67d7515b | 269 | *v850e3v5 |
c906108c SS |
270 | "callt <imm6>" |
271 | { | |
272 | unsigned32 adr; | |
273 | unsigned32 off; | |
274 | CTPC = cia + 2; | |
275 | CTPSW = PSW; | |
276 | adr = (CTBP & ~1) + (imm6 << 1); | |
277 | off = load_mem (adr, 2) & ~1; /* Force alignment */ | |
278 | nia = (CTBP & ~1) + off; | |
279 | TRACE_BRANCH3 (adr, CTBP, off); | |
280 | } | |
281 | ||
282 | ||
2aaed979 KB |
283 | |
284 | // CAXI | |
285 | rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi | |
286 | *v850e2 | |
287 | *v850e2v3 | |
67d7515b | 288 | *v850e3v5 |
2aaed979 KB |
289 | "caxi [reg1], reg2, reg3" |
290 | { | |
291 | unsigned int z,s,cy,ov; | |
292 | unsigned32 addr; | |
293 | unsigned32 token,result; | |
294 | ||
295 | addr = GR[reg1]; | |
296 | ||
297 | if (mpu_load_mem_test(sd, addr, 4, reg1) | |
298 | && mpu_store_mem_test(sd, addr, 4, reg1)) | |
299 | { | |
300 | token = load_data_mem (sd, addr, 4); | |
301 | ||
302 | TRACE_ALU_INPUT2 (token, GR[reg2]); | |
303 | ||
304 | result = GR[reg2] - token; | |
305 | ||
306 | z = (result == 0); | |
307 | s = (result & 0x80000000); | |
308 | cy = (GR[reg2] < token); | |
309 | ov = ((GR[reg2] & 0x80000000) != (token & 0x80000000) | |
310 | && (GR[reg2] & 0x80000000) != (result & 0x80000000)); | |
311 | ||
312 | if (result == 0) | |
313 | { | |
314 | store_data_mem (sd, addr, 4, GR[reg3]); | |
315 | GR[reg3] = token; | |
316 | } | |
317 | else | |
318 | { | |
319 | store_data_mem (sd, addr, 4, token); | |
320 | GR[reg3] = token; | |
321 | } | |
322 | ||
323 | /* Set condition codes. */ | |
324 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
325 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
326 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
327 | ||
328 | TRACE_ALU_RESULT1 (GR[reg3]); | |
329 | } | |
330 | } | |
331 | ||
332 | ||
c906108c SS |
333 | // CLR1 |
334 | 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1 | |
335 | "clr1 <bit3>, <disp16>[r<reg1>]" | |
336 | { | |
337 | COMPAT_2 (OP_87C0 ()); | |
338 | } | |
339 | ||
340 | rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 | |
341 | *v850e | |
c5ea1d53 | 342 | *v850e1 |
2aaed979 KB |
343 | *v850e2 |
344 | *v850e2v3 | |
67d7515b | 345 | *v850e3v5 |
c906108c SS |
346 | "clr1 r<reg2>, [r<reg1>]" |
347 | { | |
348 | COMPAT_2 (OP_E407E0 ()); | |
349 | } | |
350 | ||
351 | ||
2aaed979 | 352 | |
c906108c SS |
353 | // CTRET |
354 | 0000011111100000 + 0000000101000100:X:::ctret | |
355 | *v850e | |
c5ea1d53 | 356 | *v850e1 |
2aaed979 KB |
357 | *v850e2 |
358 | *v850e2v3 | |
67d7515b | 359 | *v850e3v5 |
c906108c SS |
360 | "ctret" |
361 | { | |
362 | nia = (CTPC & ~1); | |
363 | PSW = (CTPSW & (CPU)->psw_mask); | |
364 | TRACE_BRANCH1 (PSW); | |
365 | } | |
366 | ||
2aaed979 KB |
367 | |
368 | ||
c906108c SS |
369 | // CMOV |
370 | rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov | |
371 | *v850e | |
c5ea1d53 | 372 | *v850e1 |
2aaed979 KB |
373 | *v850e2 |
374 | *v850e2v3 | |
67d7515b | 375 | *v850e3v5 |
c906108c SS |
376 | "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>" |
377 | { | |
378 | int cond = condition_met (cccc); | |
379 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
380 | GR[reg3] = cond ? GR[reg1] : GR[reg2]; | |
381 | TRACE_ALU_RESULT (GR[reg3]); | |
382 | } | |
383 | ||
384 | rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov | |
385 | *v850e | |
c5ea1d53 | 386 | *v850e1 |
2aaed979 KB |
387 | *v850e2 |
388 | *v850e2v3 | |
67d7515b | 389 | *v850e3v5 |
c906108c SS |
390 | "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>" |
391 | { | |
392 | int cond = condition_met (cccc); | |
393 | TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]); | |
394 | GR[reg3] = cond ? imm5 : GR[reg2]; | |
395 | TRACE_ALU_RESULT (GR[reg3]); | |
396 | } | |
397 | ||
2aaed979 KB |
398 | |
399 | ||
c906108c SS |
400 | // CMP |
401 | rrrrr,001111,RRRRR:I:::cmp | |
402 | "cmp r<reg1>, r<reg2>" | |
403 | { | |
404 | COMPAT_1 (OP_1E0 ()); | |
405 | } | |
406 | ||
407 | rrrrr,010011,iiiii:II:::cmp | |
408 | "cmp <imm5>, r<reg2>" | |
409 | { | |
410 | COMPAT_1 (OP_260 ()); | |
411 | } | |
412 | ||
413 | ||
414 | ||
415 | // DI | |
416 | 0000011111100000 + 0000000101100000:X:::di | |
417 | "di" | |
418 | { | |
419 | COMPAT_2 (OP_16007E0 ()); | |
420 | } | |
421 | ||
422 | ||
423 | ||
424 | // DISPOSE | |
425 | // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose | |
426 | // "dispose <imm5>, <list12>" | |
427 | 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose | |
428 | *v850e | |
c5ea1d53 | 429 | *v850e1 |
2aaed979 KB |
430 | *v850e2 |
431 | *v850e2v3 | |
67d7515b | 432 | *v850e3v5 |
c906108c SS |
433 | "dispose <imm5>, <list12>":RRRRR == 0 |
434 | "dispose <imm5>, <list12>, [reg1]" | |
435 | { | |
436 | int i; | |
437 | SAVE_2; | |
438 | ||
439 | trace_input ("dispose", OP_PUSHPOP1, 0); | |
440 | ||
441 | SP += (OP[3] & 0x3e) << 1; | |
442 | ||
443 | /* Load the registers with lower number registers being retrieved | |
444 | from higher addresses. */ | |
445 | for (i = 12; i--;) | |
446 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
447 | { | |
448 | State.regs[ 20 + i ] = load_mem (SP, 4); | |
449 | SP += 4; | |
450 | } | |
451 | ||
452 | if ((OP[3] & 0x1f0000) != 0) | |
453 | { | |
454 | nia = State.regs[ (OP[3] >> 16) & 0x1f]; | |
455 | } | |
456 | ||
457 | trace_output (OP_PUSHPOP1); | |
458 | } | |
459 | ||
460 | ||
2aaed979 | 461 | |
c906108c SS |
462 | // DIV |
463 | rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div | |
464 | *v850e | |
c5ea1d53 | 465 | *v850e1 |
2aaed979 KB |
466 | *v850e2 |
467 | *v850e2v3 | |
67d7515b | 468 | *v850e3v5 |
c906108c SS |
469 | "div r<reg1>, r<reg2>, r<reg3>" |
470 | { | |
471 | COMPAT_2 (OP_2C007E0 ()); | |
472 | } | |
473 | ||
474 | ||
475 | // DIVH | |
476 | rrrrr!0,000010,RRRRR!0:I:::divh | |
477 | "divh r<reg1>, r<reg2>" | |
478 | { | |
ebc115b7 NC |
479 | unsigned32 ov, s, z; |
480 | signed long int op0, op1, result; | |
481 | ||
482 | trace_input ("divh", OP_REG_REG, 0); | |
483 | ||
484 | PC = cia; | |
485 | OP[0] = instruction_0 & 0x1f; | |
486 | OP[1] = (instruction_0 >> 11) & 0x1f; | |
487 | ||
488 | /* Compute the result. */ | |
489 | op0 = EXTEND16 (State.regs[OP[0]]); | |
490 | op1 = State.regs[OP[1]]; | |
491 | ||
98e460c3 | 492 | if (op0 == -1 && op1 == 0x80000000) |
ebc115b7 | 493 | { |
c5fbc25b DD |
494 | PSW &= ~PSW_Z; |
495 | PSW |= PSW_OV | PSW_S; | |
496 | State.regs[OP[1]] = 0x80000000; | |
ebc115b7 | 497 | } |
c5fbc25b | 498 | else if (op0 == 0) |
ebc115b7 | 499 | { |
c5fbc25b | 500 | PSW |= PSW_OV; |
ebc115b7 NC |
501 | } |
502 | else | |
503 | { | |
98e460c3 | 504 | result = (signed32) op1 / op0; |
c5fbc25b DD |
505 | ov = 0; |
506 | ||
507 | /* Compute the condition codes. */ | |
508 | z = (result == 0); | |
509 | s = (result & 0x80000000); | |
ebc115b7 | 510 | |
c5fbc25b DD |
511 | /* Store the result and condition codes. */ |
512 | State.regs[OP[1]] = result; | |
513 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
514 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); | |
515 | } | |
ebc115b7 NC |
516 | |
517 | trace_output (OP_REG_REG); | |
518 | ||
519 | PC += 2; | |
520 | nia = PC; | |
c906108c SS |
521 | } |
522 | ||
523 | rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh | |
524 | *v850e | |
c5ea1d53 | 525 | *v850e1 |
2aaed979 KB |
526 | *v850e2 |
527 | *v850e2v3 | |
67d7515b | 528 | *v850e3v5 |
c906108c SS |
529 | "divh r<reg1>, r<reg2>, r<reg3>" |
530 | { | |
531 | COMPAT_2 (OP_28007E0 ()); | |
532 | } | |
533 | ||
534 | ||
535 | // DIVHU | |
536 | rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu | |
537 | *v850e | |
c5ea1d53 | 538 | *v850e1 |
2aaed979 KB |
539 | *v850e2 |
540 | *v850e2v3 | |
67d7515b | 541 | *v850e3v5 |
c906108c SS |
542 | "divhu r<reg1>, r<reg2>, r<reg3>" |
543 | { | |
544 | COMPAT_2 (OP_28207E0 ()); | |
545 | } | |
546 | ||
547 | ||
548 | // DIVU | |
549 | rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu | |
550 | *v850e | |
c5ea1d53 | 551 | *v850e1 |
2aaed979 KB |
552 | *v850e2 |
553 | *v850e2v3 | |
67d7515b | 554 | *v850e3v5 |
c906108c SS |
555 | "divu r<reg1>, r<reg2>, r<reg3>" |
556 | { | |
557 | COMPAT_2 (OP_2C207E0 ()); | |
558 | } | |
559 | ||
560 | ||
2aaed979 KB |
561 | // DIVQ |
562 | rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq | |
563 | *v850e2 | |
564 | *v850e2v3 | |
67d7515b | 565 | *v850e3v5 |
2aaed979 KB |
566 | "divq r<reg1>, r<reg2>, r<reg3>" |
567 | { | |
568 | unsigned int quotient; | |
569 | unsigned int remainder; | |
570 | unsigned int divide_by; | |
571 | unsigned int divide_this; | |
572 | ||
573 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
574 | ||
575 | divide_by = GR[reg1]; | |
576 | divide_this = GR[reg2]; | |
577 | v850_div (sd, divide_by, divide_this, "ient, &remainder); | |
578 | GR[reg2] = quotient; | |
579 | GR[reg3] = remainder; | |
580 | ||
581 | TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); | |
582 | } | |
583 | ||
584 | ||
585 | // DIVQU | |
586 | rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu | |
587 | *v850e2 | |
588 | *v850e2v3 | |
67d7515b | 589 | *v850e3v5 |
2aaed979 KB |
590 | "divq r<reg1>, r<reg2>, r<reg3>" |
591 | { | |
592 | unsigned int quotient; | |
593 | unsigned int remainder; | |
594 | unsigned int divide_by; | |
595 | unsigned int divide_this; | |
596 | ||
597 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
598 | ||
599 | divide_by = GR[reg1]; | |
600 | divide_this = GR[reg2]; | |
601 | v850_divu (sd, divide_by, divide_this, "ient, &remainder); | |
602 | GR[reg2] = quotient; | |
603 | GR[reg3] = remainder; | |
604 | ||
605 | TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); | |
606 | } | |
607 | ||
608 | ||
c906108c SS |
609 | // EI |
610 | 1000011111100000 + 0000000101100000:X:::ei | |
611 | "ei" | |
612 | { | |
613 | COMPAT_2 (OP_16087E0 ()); | |
614 | } | |
615 | ||
616 | ||
617 | ||
2aaed979 KB |
618 | // EIRET |
619 | 0000011111100000 + 0000000101001000:X:::eiret | |
620 | "eiret" | |
621 | *v850e2 | |
622 | *v850e2v3 | |
67d7515b | 623 | *v850e3v5 |
2aaed979 KB |
624 | { |
625 | TRACE_ALU_INPUT1 (MPM & MPM_AUE); | |
626 | ||
627 | nia = EIPC; /* next PC */ | |
628 | if (MPM & MPM_AUE) | |
629 | { | |
630 | PSW = EIPSW; | |
631 | } | |
632 | else | |
633 | { | |
634 | PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) | |
635 | | (EIPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); | |
636 | } | |
637 | ||
638 | TRACE_ALU_RESULT1 (PSW); | |
639 | TRACE_BRANCH_RESULT (nia); | |
640 | } | |
641 | ||
642 | ||
643 | ||
644 | // FERET | |
645 | 0000011111100000 + 0000000101001010:X:::feret | |
646 | "feret" | |
647 | *v850e2 | |
648 | *v850e2v3 | |
67d7515b | 649 | *v850e3v5 |
2aaed979 KB |
650 | { |
651 | TRACE_ALU_INPUT1 (MPM & MPM_AUE); | |
652 | ||
653 | nia = FEPC; /* next PC */ | |
654 | if (MPM & MPM_AUE) | |
655 | { | |
656 | PSW = FEPSW; | |
657 | } | |
658 | else | |
659 | { | |
660 | PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) | |
661 | | (FEPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); | |
662 | } | |
663 | ||
664 | TRACE_ALU_RESULT1 (PSW); | |
665 | TRACE_BRANCH_RESULT (nia); | |
666 | } | |
667 | ||
668 | ||
669 | // FETRAP | |
670 | 0,bbbb!0,00001000000:I:::fetrap | |
671 | "fetrap" | |
672 | *v850e2 | |
673 | *v850e2v3 | |
67d7515b | 674 | *v850e3v5 |
2aaed979 KB |
675 | { |
676 | TRACE_ALU_INPUT0 (); | |
677 | ||
678 | FEPC = PC + 2; | |
679 | FEPSW = PSW; | |
680 | ECR &= ~ECR_FECC; | |
681 | ECR |= (0x30 + bit4) << 16; | |
682 | FEIC = 0x30 + bit4; | |
683 | PSW |= PSW_EP | PSW_ID | PSW_NP; | |
684 | nia = 0x30; /* next PC */ | |
685 | ||
686 | TRACE_ALU_RESULT1 (PSW); | |
687 | TRACE_BRANCH_RESULT (nia); | |
688 | } | |
689 | ||
690 | ||
c906108c SS |
691 | // HALT |
692 | 0000011111100000 + 0000000100100000:X:::halt | |
693 | "halt" | |
694 | { | |
695 | COMPAT_2 (OP_12007E0 ()); | |
696 | } | |
697 | ||
698 | ||
699 | ||
2aaed979 KB |
700 | // HSH |
701 | rrrrr,11111100000 + wwwww,01101000110:XII:::hsh | |
702 | *v850e2 | |
703 | *v850e2v3 | |
67d7515b | 704 | *v850e3v5 |
2aaed979 KB |
705 | "hsh r<reg2>, r<reg3>" |
706 | { | |
707 | unsigned32 value; | |
708 | TRACE_ALU_INPUT1 (GR[reg2]); | |
709 | ||
710 | value = 0xffff & GR[reg2]; | |
711 | GR[reg3] = GR[reg2]; | |
712 | ||
713 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
714 | ||
715 | if (value == 0) { PSW |= PSW_Z; PSW |= PSW_CY; } | |
716 | if (value & 0x80000000) PSW |= PSW_S; | |
717 | ||
718 | TRACE_ALU_RESULT1 (GR[reg3]); | |
719 | } | |
720 | ||
721 | ||
c906108c SS |
722 | // HSW |
723 | rrrrr,11111100000 + wwwww,01101000100:XII:::hsw | |
724 | *v850e | |
c5ea1d53 | 725 | *v850e1 |
2aaed979 KB |
726 | *v850e2 |
727 | *v850e2v3 | |
67d7515b | 728 | *v850e3v5 |
c906108c SS |
729 | "hsw r<reg2>, r<reg3>" |
730 | { | |
731 | unsigned32 value; | |
732 | TRACE_ALU_INPUT1 (GR[reg2]); | |
733 | ||
734 | value = GR[reg2]; | |
735 | value >>= 16; | |
736 | value |= (GR[reg2] << 16); | |
737 | ||
738 | GR[reg3] = value; | |
739 | ||
740 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
741 | ||
742 | if (value == 0) PSW |= PSW_Z; | |
743 | if (value & 0x80000000) PSW |= PSW_S; | |
744 | if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY; | |
745 | ||
746 | TRACE_ALU_RESULT (GR[reg3]); | |
747 | } | |
748 | ||
749 | ||
750 | ||
751 | // JARL | |
752 | rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl | |
753 | "jarl <disp22>, r<reg2>" | |
754 | { | |
755 | GR[reg2] = nia; | |
756 | nia = cia + disp22; | |
757 | TRACE_BRANCH1 (GR[reg2]); | |
758 | } | |
759 | ||
2aaed979 KB |
760 | 00000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32 |
761 | *v850e2 | |
762 | *v850e2v3 | |
67d7515b | 763 | *v850e3v5 |
2aaed979 KB |
764 | "jarl <imm32>, r<reg1>" |
765 | { | |
766 | GR[reg1] = nia; | |
767 | nia = (cia + imm32) & ~1; | |
768 | ||
769 | TRACE_BRANCH_RESULT (nia); | |
770 | } | |
c906108c SS |
771 | |
772 | ||
67d7515b NC |
773 | 11000111111,RRRRR + wwwww!0,00101100000:XI:::jarl_reg |
774 | *v850e3v5 | |
775 | "jarl [r<reg1>], r<reg3>" | |
776 | { | |
777 | GR[reg3] = nia; | |
778 | nia = GR[reg1]; | |
779 | TRACE_BRANCH_RESULT (nia); | |
780 | } | |
781 | ||
782 | ||
c906108c SS |
783 | // JMP |
784 | 00000000011,RRRRR:I:::jmp | |
785 | "jmp [r<reg1>]" | |
786 | { | |
787 | nia = GR[reg1] & ~1; | |
788 | TRACE_BRANCH0 (); | |
789 | } | |
790 | ||
2aaed979 KB |
791 | 00000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32 |
792 | *v850e2 | |
793 | *v850e2v3 | |
67d7515b | 794 | *v850e3v5 |
2aaed979 KB |
795 | "jmp <imm32>[r<reg1>]" |
796 | { | |
797 | nia = (GR[reg1] + imm32) & ~1; | |
798 | ||
799 | TRACE_BRANCH_RESULT (nia); | |
800 | } | |
c906108c SS |
801 | |
802 | ||
803 | // JR | |
804 | 0000011110,dddddd + ddddddddddddddd,0:V:::jr | |
805 | "jr <disp22>" | |
806 | { | |
807 | nia = cia + disp22; | |
808 | TRACE_BRANCH0 (); | |
809 | } | |
810 | ||
811 | ||
2aaed979 | 812 | // JR32 |
d99ff40f | 813 | 0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32 |
2aaed979 KB |
814 | *v850e2 |
815 | *v850e2v3 | |
67d7515b | 816 | *v850e3v5 |
2aaed979 KB |
817 | "jr <imm32>" |
818 | { | |
819 | nia = (cia + imm32) & ~1; | |
820 | ||
821 | TRACE_BRANCH_RESULT (nia); | |
822 | } | |
823 | ||
c906108c SS |
824 | |
825 | // LD | |
826 | rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b | |
827 | "ld.b <disp16>[r<reg1>], r<reg2>" | |
828 | { | |
829 | COMPAT_2 (OP_700 ()); | |
830 | } | |
831 | ||
2aaed979 KB |
832 | 00000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b |
833 | "ld.b <disp23>[r<reg1>], r<reg3>" | |
834 | *v850e2v3 | |
67d7515b | 835 | *v850e3v5 |
2aaed979 KB |
836 | { |
837 | unsigned32 addr = GR[reg1] + disp23; | |
838 | unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1)); | |
839 | GR[reg3] = result; | |
840 | TRACE_LD (addr, result); | |
841 | } | |
842 | ||
c906108c SS |
843 | rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h |
844 | "ld.h <disp16>[r<reg1>], r<reg2>" | |
845 | { | |
846 | COMPAT_2 (OP_720 ()); | |
847 | } | |
848 | ||
2aaed979 KB |
849 | 00000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h |
850 | *v850e2v3 | |
67d7515b | 851 | *v850e3v5 |
2aaed979 KB |
852 | "ld.h <disp23>[r<reg1>], r<reg3>" |
853 | { | |
854 | unsigned32 addr = GR[reg1] + disp23; | |
855 | unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2)); | |
856 | GR[reg3] = result; | |
857 | TRACE_LD (addr, result); | |
858 | } | |
859 | ||
c906108c SS |
860 | rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w |
861 | "ld.w <disp16>[r<reg1>], r<reg2>" | |
862 | { | |
863 | COMPAT_2 (OP_10720 ()); | |
864 | } | |
865 | ||
2aaed979 KB |
866 | 00000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w |
867 | *v850e2v3 | |
67d7515b | 868 | *v850e3v5 |
2aaed979 KB |
869 | "ld.w <disp23>[r<reg1>], r<reg3>" |
870 | { | |
871 | unsigned32 addr = GR[reg1] + disp23; | |
872 | unsigned32 result = load_data_mem (sd, addr, 4); | |
873 | GR[reg3] = result; | |
874 | TRACE_LD (addr, result); | |
875 | } | |
876 | ||
67d7515b NC |
877 | 00000111101,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.dw |
878 | *v850e3v5 | |
879 | "ld.dw <disp23>[r<reg1>], r<reg3>" | |
880 | { | |
881 | unsigned32 addr = GR[reg1] + disp23; | |
882 | unsigned32 result = load_data_mem (sd, addr, 4); | |
883 | GR[reg3] = result; | |
884 | TRACE_LD (addr, result); | |
885 | result = load_data_mem (sd, addr + 4, 4); | |
886 | GR[reg3 + 1] = result; | |
887 | TRACE_LD (addr + 4, result); | |
888 | } | |
889 | ||
c906108c SS |
890 | rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu |
891 | *v850e | |
c5ea1d53 | 892 | *v850e1 |
2aaed979 KB |
893 | *v850e2 |
894 | *v850e2v3 | |
67d7515b | 895 | *v850e3v5 |
c906108c SS |
896 | "ld.bu <disp16>[r<reg1>], r<reg2>" |
897 | { | |
898 | COMPAT_2 (OP_10780 ()); | |
899 | } | |
900 | ||
2aaed979 KB |
901 | 00000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu |
902 | *v850e2v3 | |
67d7515b | 903 | *v850e3v5 |
2aaed979 KB |
904 | "ld.bu <disp23>[r<reg1>], r<reg3>" |
905 | { | |
906 | unsigned32 addr = GR[reg1] + disp23; | |
907 | unsigned32 result = load_data_mem (sd, addr, 1); | |
908 | GR[reg3] = result; | |
909 | TRACE_LD (addr, result); | |
910 | } | |
911 | ||
c906108c SS |
912 | rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu |
913 | *v850e | |
c5ea1d53 | 914 | *v850e1 |
2aaed979 KB |
915 | *v850e2 |
916 | *v850e2v3 | |
67d7515b | 917 | *v850e3v5 |
c906108c SS |
918 | "ld.hu <disp16>[r<reg1>], r<reg2>" |
919 | { | |
920 | COMPAT_2 (OP_107E0 ()); | |
921 | } | |
922 | ||
2aaed979 KB |
923 | 00000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu |
924 | *v850e2v3 | |
67d7515b | 925 | *v850e3v5 |
2aaed979 KB |
926 | "ld.hu <disp23>[r<reg1>], r<reg3>" |
927 | { | |
928 | unsigned32 addr = GR[reg1] + disp23; | |
929 | unsigned32 result = load_data_mem (sd, addr, 2); | |
930 | GR[reg3] = result; | |
931 | TRACE_LD (addr, result); | |
932 | } | |
933 | ||
934 | ||
c906108c SS |
935 | |
936 | // LDSR | |
937 | regID,111111,RRRRR + 0000000000100000:IX:::ldsr | |
938 | "ldsr r<reg1>, s<regID>" | |
939 | { | |
2aaed979 | 940 | uint32 sreg = GR[reg1]; |
c906108c SS |
941 | TRACE_ALU_INPUT1 (GR[reg1]); |
942 | ||
2aaed979 | 943 | if ((idecode_issue == idecode_v850e2_issue |
67d7515b | 944 | || idecode_issue == idecode_v850e3v5_issue |
2aaed979 KB |
945 | || idecode_issue == idecode_v850e2v3_issue) |
946 | && regID < 28) | |
947 | { | |
948 | int protect_p = (PSW & PSW_NPV) ? 1 : 0; | |
949 | ||
950 | ||
951 | switch (BSEL & 0xffff) | |
952 | { | |
953 | case 0x0000: | |
954 | if ((PSW & PSW_NPV) | |
955 | && ((regID >= 8 && regID <= 12) | |
956 | || (regID >= 22 && regID <= 27) | |
957 | || regID == PSW_REGNO)) | |
958 | { | |
959 | protect_p = 0; | |
960 | } | |
961 | break; | |
962 | case 0x1000: /* MPU0 */ | |
963 | break; | |
964 | case 0x1001: /* MPU1 */ | |
965 | break; | |
966 | case 0x2000: /* FPU */ | |
967 | if ((PSW & PSW_NPV) | |
968 | && ((/* regID >= 0 && */ regID <= 5) | |
969 | || regID == 8 | |
970 | || regID == 9 | |
971 | || regID == 10 | |
972 | || (regID >= 11 && regID <= 26))) | |
973 | { | |
974 | protect_p = 0; | |
975 | } | |
976 | break; | |
977 | case 0xff00: | |
978 | if ((PSW & PSW_NPV) | |
979 | && (regID == 6 | |
980 | || regID == 7 | |
981 | || regID == 8 | |
982 | || regID == 9 | |
983 | || regID == 10 | |
984 | || (regID >= 11 && regID <= 15) | |
985 | || regID == 18 | |
986 | || regID == 19 | |
987 | || (regID >= 21 && regID <= 27))) | |
988 | { | |
989 | protect_p = 0; | |
990 | } | |
991 | break; | |
992 | case 0xffff: | |
993 | if ((PSW & PSW_NPV) | |
994 | && (regID == 6 | |
995 | || regID == 7 | |
996 | || regID == 8 | |
997 | || regID == 9 | |
998 | || regID == 10 | |
999 | || regID == 11 | |
1000 | || regID == 12 | |
1001 | || regID == 15 | |
1002 | || regID == 18 | |
1003 | || regID == 19 | |
1004 | || (regID >= 21 && regID <= 27))) | |
1005 | { | |
1006 | protect_p = 0; | |
1007 | } | |
1008 | break; | |
1009 | } | |
1010 | ||
1011 | if (!protect_p) | |
1012 | { | |
1013 | switch (BSEL & 0xffff) | |
1014 | { | |
1015 | case 0x0000: | |
1016 | case 0xff00: /* user0 bank */ | |
1017 | case 0xffff: /* user1 bank */ | |
1018 | if(regID == PSW_REGNO) | |
1019 | { | |
1020 | SR[regID] = sreg & ((PSW & PSW_NPV) ? 0xf : ~0); | |
1021 | } | |
1022 | else | |
1023 | { | |
1024 | SR[regID] = sreg; | |
1025 | } | |
1026 | break; | |
1027 | case 0x1000: | |
1028 | MPU0_SR[regID] = sreg; | |
1029 | break; | |
1030 | case 0x1001: | |
1031 | if (regID == MPC_REGNO) | |
1032 | { | |
1033 | PPC &= ~PPC_PPE; | |
1034 | SPAL &= ~SPAL_SPE; | |
1035 | IPA0L &= ~IPA_IPE; | |
1036 | IPA1L &= ~IPA_IPE; | |
1037 | IPA2L &= ~IPA_IPE; | |
1038 | IPA3L &= ~IPA_IPE; | |
1039 | DPA0L &= ~DPA_DPE; | |
1040 | DPA1L &= ~DPA_DPE; | |
1041 | DCC &= ~(DCC_DCE0 | DCC_DCE1); | |
1042 | } | |
1043 | else | |
1044 | { | |
1045 | MPU1_SR[regID] = sreg; | |
1046 | } | |
1047 | break; | |
1048 | case 0x2000: /* FPU */ | |
1049 | if (regID == FPST_REGNO) | |
1050 | { | |
1051 | unsigned int val = FPSR & ~(FPSR_PR | FPSR_XC | FPSR_XP); | |
1052 | ||
1053 | val |= ((sreg & FPST_PR) ? FPSR_PR : 0) | |
1054 | | ((sreg & FPST_XCE) ? FPSR_XCE : 0) | |
1055 | | ((sreg & FPST_XCV) ? FPSR_XCV : 0) | |
1056 | | ((sreg & FPST_XCZ) ? FPSR_XCZ : 0) | |
1057 | | ((sreg & FPST_XCO) ? FPSR_XCO : 0) | |
1058 | | ((sreg & FPST_XCU) ? FPSR_XCU : 0) | |
1059 | | ((sreg & FPST_XCI) ? FPSR_XCI : 0) | |
1060 | | ((sreg & FPST_XPV) ? FPSR_XPV : 0) | |
1061 | | ((sreg & FPST_XPZ) ? FPSR_XPZ : 0) | |
1062 | | ((sreg & FPST_XPO) ? FPSR_XPO : 0) | |
1063 | | ((sreg & FPST_XPU) ? FPSR_XPU : 0) | |
1064 | | ((sreg & FPST_XPI) ? FPSR_XPI : 0); | |
1065 | FPSR = val; | |
1066 | } | |
1067 | else if (regID == FPCFG_REGNO) | |
1068 | { | |
1069 | unsigned int val = FPSR & ~(FPSR_RM | FPSR_XE); | |
1070 | ||
1071 | val |= (((sreg & FPCFG_RM) >> 7) << 18) | |
1072 | | ((sreg & FPCFG_XEV) ? FPSR_XEV : 0) | |
1073 | | ((sreg & FPCFG_XEZ) ? FPSR_XEZ : 0) | |
1074 | | ((sreg & FPCFG_XEO) ? FPSR_XEO : 0) | |
1075 | | ((sreg & FPCFG_XEU) ? FPSR_XEU : 0) | |
1076 | | ((sreg & FPCFG_XEI) ? FPSR_XEI : 0); | |
1077 | FPSR = val; | |
1078 | } | |
1079 | ||
1080 | FPU_SR[regID] = sreg; | |
1081 | break; | |
1082 | } | |
1083 | } | |
1084 | } | |
c906108c | 1085 | else |
2aaed979 KB |
1086 | { |
1087 | SR[regID] = sreg; | |
1088 | } | |
1089 | ||
1090 | TRACE_ALU_RESULT (sreg); | |
1091 | } | |
1092 | ||
1093 | ||
1094 | ||
1095 | // MAC | |
1096 | rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac | |
1097 | *v850e2 | |
1098 | *v850e2v3 | |
67d7515b | 1099 | *v850e3v5 |
2aaed979 KB |
1100 | "mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" |
1101 | { | |
1102 | unsigned long op0; | |
1103 | unsigned long op1; | |
1104 | unsigned long op2; | |
1105 | unsigned long op2hi; | |
1106 | unsigned long lo; | |
1107 | unsigned long mid1; | |
1108 | unsigned long mid2; | |
1109 | unsigned long hi; | |
1110 | unsigned long RdLo; | |
1111 | unsigned long RdHi; | |
1112 | int carry; | |
1113 | bfd_boolean sign; | |
1114 | ||
1115 | op0 = GR[reg1]; | |
1116 | op1 = GR[reg2]; | |
1117 | op2 = GR[reg3e]; | |
1118 | op2hi = GR[reg3e+1]; | |
1119 | ||
1120 | TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); | |
1121 | ||
1122 | sign = (op0 ^ op1) & 0x80000000; | |
1123 | ||
1124 | if (((signed long) op0) < 0) | |
1125 | op0 = - op0; | |
1126 | ||
1127 | if (((signed long) op1) < 0) | |
1128 | op1 = - op1; | |
1129 | ||
1130 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
1131 | that we do not lose precision on 32bit only hosts: */ | |
1132 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
1133 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1134 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
1135 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1136 | ||
1137 | /* We now need to add all of these results together, taking care | |
1138 | to propogate the carries from the additions: */ | |
1139 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
1140 | RdHi = carry; | |
1141 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
1142 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
1143 | ||
1144 | if (sign) | |
1145 | { | |
1146 | RdLo = ~ RdLo; | |
1147 | RdHi = ~ RdHi; | |
1148 | if (RdLo == 0xFFFFFFFF) | |
1149 | { | |
1150 | RdLo = 0; | |
1151 | RdHi += 1; | |
1152 | } | |
1153 | else | |
1154 | RdLo += 1; | |
1155 | } | |
1156 | ||
1157 | RdLo = Add32 (RdLo, op2, & carry); | |
1158 | RdHi += carry + op2hi; | |
1159 | ||
1160 | /* Store the result and condition codes. */ | |
1161 | GR[reg4e] = RdLo; | |
1162 | GR[reg4e + 1 ] = RdHi; | |
1163 | ||
1164 | TRACE_ALU_RESULT2 (RdLo, RdHi); | |
1165 | } | |
1166 | ||
1167 | ||
1168 | ||
1169 | // MACU | |
1170 | rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu | |
1171 | *v850e2 | |
1172 | *v850e2v3 | |
67d7515b | 1173 | *v850e3v5 |
2aaed979 KB |
1174 | "macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" |
1175 | { | |
1176 | unsigned long op0; | |
1177 | unsigned long op1; | |
1178 | unsigned long op2; | |
1179 | unsigned long op2hi; | |
1180 | unsigned long lo; | |
1181 | unsigned long mid1; | |
1182 | unsigned long mid2; | |
1183 | unsigned long hi; | |
1184 | unsigned long RdLo; | |
1185 | unsigned long RdHi; | |
1186 | int carry; | |
1187 | ||
1188 | op0 = GR[reg1]; | |
1189 | op1 = GR[reg2]; | |
1190 | op2 = GR[reg3e]; | |
1191 | op2hi = GR[reg3e + 1]; | |
1192 | ||
1193 | TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); | |
1194 | ||
1195 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
1196 | that we do not lose precision on 32bit only hosts: */ | |
1197 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
1198 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1199 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
1200 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
c906108c | 1201 | |
2aaed979 KB |
1202 | /* We now need to add all of these results together, taking care |
1203 | to propogate the carries from the additions: */ | |
1204 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
1205 | RdHi = carry; | |
1206 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
1207 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
1208 | ||
1209 | RdLo = Add32 (RdLo, op2, & carry); | |
1210 | RdHi += carry + op2hi; | |
1211 | ||
1212 | /* Store the result and condition codes. */ | |
1213 | GR[reg4e] = RdLo; | |
1214 | GR[reg4e+1] = RdHi; | |
1215 | ||
1216 | TRACE_ALU_RESULT2 (RdLo, RdHi); | |
c906108c SS |
1217 | } |
1218 | ||
1219 | ||
1220 | ||
1221 | // MOV | |
1222 | rrrrr!0,000000,RRRRR:I:::mov | |
1223 | "mov r<reg1>, r<reg2>" | |
1224 | { | |
1225 | TRACE_ALU_INPUT0 (); | |
1226 | GR[reg2] = GR[reg1]; | |
1227 | TRACE_ALU_RESULT (GR[reg2]); | |
1228 | } | |
1229 | ||
c906108c SS |
1230 | rrrrr!0,010000,iiiii:II:::mov |
1231 | "mov <imm5>, r<reg2>" | |
1232 | { | |
1233 | COMPAT_1 (OP_200 ()); | |
1234 | } | |
1235 | ||
1236 | 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov | |
1237 | *v850e | |
c5ea1d53 | 1238 | *v850e1 |
2aaed979 KB |
1239 | *v850e2 |
1240 | *v850e2v3 | |
67d7515b | 1241 | *v850e3v5 |
c906108c SS |
1242 | "mov <imm32>, r<reg1>" |
1243 | { | |
1244 | SAVE_2; | |
1245 | trace_input ("mov", OP_IMM_REG, 4); | |
1246 | State.regs[ OP[0] ] = load_mem (PC + 2, 4); | |
1247 | trace_output (OP_IMM_REG); | |
1248 | } | |
1249 | ||
1250 | ||
1251 | ||
1252 | // MOVEA | |
1253 | rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea | |
1254 | "movea <simm16>, r<reg1>, r<reg2>" | |
1255 | { | |
1256 | TRACE_ALU_INPUT2 (GR[reg1], simm16); | |
1257 | GR[reg2] = GR[reg1] + simm16; | |
1258 | TRACE_ALU_RESULT (GR[reg2]); | |
1259 | } | |
1260 | ||
1261 | ||
1262 | ||
1263 | // MOVHI | |
1264 | rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi | |
1265 | "movhi <uimm16>, r<reg1>, r<reg2>" | |
1266 | { | |
1267 | COMPAT_2 (OP_640 ()); | |
1268 | } | |
1269 | ||
1270 | ||
1271 | ||
1272 | // MUL | |
1273 | rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul | |
1274 | *v850e | |
c5ea1d53 | 1275 | *v850e1 |
2aaed979 KB |
1276 | *v850e2 |
1277 | *v850e2v3 | |
67d7515b | 1278 | *v850e3v5 |
c906108c SS |
1279 | "mul r<reg1>, r<reg2>, r<reg3>" |
1280 | { | |
1281 | COMPAT_2 (OP_22007E0 ()); | |
1282 | } | |
1283 | ||
1284 | rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul | |
1285 | *v850e | |
c5ea1d53 | 1286 | *v850e1 |
2aaed979 KB |
1287 | *v850e2 |
1288 | *v850e2v3 | |
67d7515b | 1289 | *v850e3v5 |
c906108c SS |
1290 | "mul <imm9>, r<reg2>, r<reg3>" |
1291 | { | |
1292 | COMPAT_2 (OP_24007E0 ()); | |
1293 | } | |
1294 | ||
1295 | ||
1296 | // MULH | |
1297 | rrrrr!0,000111,RRRRR:I:::mulh | |
1298 | "mulh r<reg1>, r<reg2>" | |
1299 | { | |
1300 | COMPAT_1 (OP_E0 ()); | |
1301 | } | |
1302 | ||
1303 | rrrrr!0,010111,iiiii:II:::mulh | |
1304 | "mulh <imm5>, r<reg2>" | |
1305 | { | |
1306 | COMPAT_1 (OP_2E0 ()); | |
1307 | } | |
1308 | ||
1309 | ||
1310 | ||
1311 | // MULHI | |
1312 | rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi | |
1313 | "mulhi <uimm16>, r<reg1>, r<reg2>" | |
1314 | { | |
1315 | COMPAT_2 (OP_6E0 ()); | |
1316 | } | |
1317 | ||
1318 | ||
1319 | ||
1320 | // MULU | |
1321 | rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu | |
1322 | *v850e | |
c5ea1d53 | 1323 | *v850e1 |
2aaed979 KB |
1324 | *v850e2 |
1325 | *v850e2v3 | |
67d7515b | 1326 | *v850e3v5 |
c906108c SS |
1327 | "mulu r<reg1>, r<reg2>, r<reg3>" |
1328 | { | |
1329 | COMPAT_2 (OP_22207E0 ()); | |
1330 | } | |
1331 | ||
1332 | rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu | |
1333 | *v850e | |
c5ea1d53 | 1334 | *v850e1 |
2aaed979 KB |
1335 | *v850e2 |
1336 | *v850e2v3 | |
67d7515b | 1337 | *v850e3v5 |
c906108c SS |
1338 | "mulu <imm9>, r<reg2>, r<reg3>" |
1339 | { | |
1340 | COMPAT_2 (OP_24207E0 ()); | |
1341 | } | |
1342 | ||
1343 | ||
1344 | ||
1345 | // NOP | |
1346 | 0000000000000000:I:::nop | |
1347 | "nop" | |
1348 | { | |
1349 | /* do nothing, trace nothing */ | |
1350 | } | |
1351 | ||
1352 | ||
1353 | ||
1354 | // NOT | |
1355 | rrrrr,000001,RRRRR:I:::not | |
1356 | "not r<reg1>, r<reg2>" | |
1357 | { | |
1358 | COMPAT_1 (OP_20 ()); | |
1359 | } | |
1360 | ||
1361 | ||
1362 | ||
1363 | // NOT1 | |
1364 | 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1 | |
1365 | "not1 <bit3>, <disp16>[r<reg1>]" | |
1366 | { | |
1367 | COMPAT_2 (OP_47C0 ()); | |
1368 | } | |
1369 | ||
1370 | rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 | |
1371 | *v850e | |
c5ea1d53 | 1372 | *v850e1 |
2aaed979 KB |
1373 | *v850e2 |
1374 | *v850e2v3 | |
67d7515b | 1375 | *v850e3v5 |
c906108c SS |
1376 | "not1 r<reg2>, r<reg1>" |
1377 | { | |
1378 | COMPAT_2 (OP_E207E0 ()); | |
1379 | } | |
1380 | ||
1381 | ||
1382 | ||
1383 | // OR | |
1384 | rrrrr,001000,RRRRR:I:::or | |
1385 | "or r<reg1>, r<reg2>" | |
1386 | { | |
1387 | COMPAT_1 (OP_100 ()); | |
1388 | } | |
1389 | ||
1390 | ||
1391 | ||
1392 | // ORI | |
1393 | rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori | |
1394 | "ori <uimm16>, r<reg1>, r<reg2>" | |
1395 | { | |
1396 | COMPAT_2 (OP_680 ()); | |
1397 | } | |
1398 | ||
1399 | ||
1400 | ||
1401 | // PREPARE | |
1402 | 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare | |
1403 | *v850e | |
c5ea1d53 | 1404 | *v850e1 |
2aaed979 KB |
1405 | *v850e2 |
1406 | *v850e2v3 | |
67d7515b | 1407 | *v850e3v5 |
c906108c SS |
1408 | "prepare <list12>, <imm5>" |
1409 | { | |
1410 | int i; | |
1411 | SAVE_2; | |
1412 | ||
1413 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
1414 | ||
1415 | /* Store the registers with lower number registers being placed at | |
1416 | higher addresses. */ | |
1417 | for (i = 0; i < 12; i++) | |
1418 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
1419 | { | |
1420 | SP -= 4; | |
1421 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
1422 | } | |
1423 | ||
1424 | SP -= (OP[3] & 0x3e) << 1; | |
1425 | ||
1426 | trace_output (OP_PUSHPOP1); | |
1427 | } | |
1428 | ||
1429 | ||
1430 | 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 | |
1431 | *v850e | |
c5ea1d53 | 1432 | *v850e1 |
2aaed979 KB |
1433 | *v850e2 |
1434 | *v850e2v3 | |
67d7515b | 1435 | *v850e3v5 |
c906108c SS |
1436 | "prepare <list12>, <imm5>, sp" |
1437 | { | |
1438 | COMPAT_2 (OP_30780 ()); | |
1439 | } | |
1440 | ||
1441 | 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 | |
1442 | *v850e | |
c5ea1d53 | 1443 | *v850e1 |
2aaed979 KB |
1444 | *v850e2 |
1445 | *v850e2v3 | |
67d7515b | 1446 | *v850e3v5 |
c906108c SS |
1447 | "prepare <list12>, <imm5>, <uimm16>" |
1448 | { | |
1449 | COMPAT_2 (OP_B0780 ()); | |
1450 | } | |
1451 | ||
1452 | 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 | |
1453 | *v850e | |
c5ea1d53 | 1454 | *v850e1 |
2aaed979 KB |
1455 | *v850e2 |
1456 | *v850e2v3 | |
67d7515b | 1457 | *v850e3v5 |
c906108c SS |
1458 | "prepare <list12>, <imm5>, <uimm16>" |
1459 | { | |
1460 | COMPAT_2 (OP_130780 ()); | |
1461 | } | |
1462 | ||
1463 | 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 | |
1464 | *v850e | |
c5ea1d53 | 1465 | *v850e1 |
2aaed979 KB |
1466 | *v850e2 |
1467 | *v850e2v3 | |
67d7515b | 1468 | *v850e3v5 |
c906108c SS |
1469 | "prepare <list12>, <imm5>, <uimm32>" |
1470 | { | |
1471 | COMPAT_2 (OP_1B0780 ()); | |
1472 | } | |
1473 | ||
1474 | ||
1475 | ||
1476 | // RETI | |
1477 | 0000011111100000 + 0000000101000000:X:::reti | |
1478 | "reti" | |
1479 | { | |
1480 | if ((PSW & PSW_EP)) | |
1481 | { | |
1482 | nia = (EIPC & ~1); | |
1483 | PSW = EIPSW; | |
1484 | } | |
1485 | else if ((PSW & PSW_NP)) | |
1486 | { | |
1487 | nia = (FEPC & ~1); | |
1488 | PSW = FEPSW; | |
1489 | } | |
1490 | else | |
1491 | { | |
1492 | nia = (EIPC & ~1); | |
1493 | PSW = EIPSW; | |
1494 | } | |
1495 | TRACE_BRANCH1 (PSW); | |
1496 | } | |
1497 | ||
1498 | ||
1499 | ||
1500 | // SAR | |
1501 | rrrrr,111111,RRRRR + 0000000010100000:IX:::sar | |
1502 | "sar r<reg1>, r<reg2>" | |
1503 | { | |
1504 | COMPAT_2 (OP_A007E0 ()); | |
1505 | } | |
1506 | ||
1507 | rrrrr,010101,iiiii:II:::sar | |
1508 | "sar <imm5>, r<reg2>" | |
1509 | { | |
1510 | COMPAT_1 (OP_2A0 ()); | |
1511 | } | |
1512 | ||
2aaed979 KB |
1513 | rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar |
1514 | *v850e2 | |
1515 | *v850e2v3 | |
67d7515b | 1516 | *v850e3v5 |
2aaed979 KB |
1517 | "sar r<reg1>, r<reg2>, r<reg3>" |
1518 | { | |
1519 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1520 | v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1521 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1522 | } | |
c906108c SS |
1523 | |
1524 | ||
1525 | // SASF | |
1526 | rrrrr,1111110,cccc + 0000001000000000:IX:::sasf | |
1527 | *v850e | |
c5ea1d53 | 1528 | *v850e1 |
2aaed979 KB |
1529 | *v850e2 |
1530 | *v850e2v3 | |
67d7515b | 1531 | *v850e3v5 |
c906108c SS |
1532 | "sasf %s<cccc>, r<reg2>" |
1533 | { | |
1534 | COMPAT_2 (OP_20007E0 ()); | |
1535 | } | |
1536 | ||
1537 | ||
1538 | ||
c906108c SS |
1539 | // SATADD |
1540 | rrrrr!0,000110,RRRRR:I:::satadd | |
1541 | "satadd r<reg1>, r<reg2>" | |
1542 | { | |
1543 | COMPAT_1 (OP_C0 ()); | |
1544 | } | |
1545 | ||
1546 | rrrrr!0,010001,iiiii:II:::satadd | |
1547 | "satadd <imm5>, r<reg2>" | |
1548 | { | |
1549 | COMPAT_1 (OP_220 ()); | |
1550 | } | |
1551 | ||
2aaed979 KB |
1552 | rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd |
1553 | *v850e2 | |
1554 | *v850e2v3 | |
67d7515b | 1555 | *v850e3v5 |
2aaed979 KB |
1556 | "satadd r<reg1>, r<reg2>, r<reg3>" |
1557 | { | |
1558 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1559 | v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1560 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1561 | } | |
1562 | ||
c906108c SS |
1563 | |
1564 | ||
1565 | // SATSUB | |
1566 | rrrrr!0,000101,RRRRR:I:::satsub | |
1567 | "satsub r<reg1>, r<reg2>" | |
1568 | { | |
1569 | COMPAT_1 (OP_A0 ()); | |
1570 | } | |
1571 | ||
2aaed979 KB |
1572 | rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub |
1573 | *v850e2 | |
1574 | *v850e2v3 | |
67d7515b | 1575 | *v850e3v5 |
2aaed979 KB |
1576 | "satsub r<reg1>, r<reg2>, r<reg3>" |
1577 | { | |
1578 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1579 | v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1580 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1581 | } | |
1582 | ||
c906108c SS |
1583 | |
1584 | ||
1585 | // SATSUBI | |
1586 | rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi | |
1587 | "satsubi <simm16>, r<reg1>, r<reg2>" | |
1588 | { | |
1589 | COMPAT_2 (OP_660 ()); | |
1590 | } | |
1591 | ||
1592 | ||
1593 | ||
1594 | // SATSUBR | |
1595 | rrrrr!0,000100,RRRRR:I:::satsubr | |
1596 | "satsubr r<reg1>, r<reg2>" | |
1597 | { | |
1598 | COMPAT_1 (OP_80 ()); | |
1599 | } | |
1600 | ||
1601 | ||
1602 | ||
2aaed979 KB |
1603 | //SBF |
1604 | rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf | |
1605 | *v850e2 | |
1606 | *v850e2v3 | |
67d7515b | 1607 | *v850e3v5 |
2aaed979 KB |
1608 | "sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" |
1609 | { | |
1610 | int cond = condition_met (cccc); | |
1611 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
1612 | GR[reg3] = GR[reg2] - GR[reg1] - (cond ? 1 : 0); | |
1613 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1614 | } | |
1615 | ||
1616 | ||
1617 | ||
1618 | // SCH0L | |
1619 | rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l | |
1620 | *v850e2 | |
1621 | *v850e2v3 | |
67d7515b | 1622 | *v850e3v5 |
2aaed979 KB |
1623 | "sch0l r<reg2>, r<reg3>" |
1624 | { | |
1625 | unsigned int pos, op0; | |
1626 | ||
1627 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1628 | ||
1629 | op0 = GR[reg2]; | |
1630 | ||
1631 | if (op0 == 0xffffffff) | |
1632 | { | |
1633 | PSW &= ~PSW_CY; | |
1634 | PSW &= ~PSW_OV; | |
1635 | PSW &= ~PSW_S; | |
1636 | PSW |= PSW_Z; | |
1637 | pos = 0; | |
1638 | } | |
1639 | else if (op0 == 0xfffffffe) | |
1640 | { | |
1641 | PSW |= PSW_CY; | |
1642 | PSW &= ~PSW_OV; | |
1643 | PSW &= ~PSW_S; | |
1644 | PSW &= ~PSW_Z; | |
1645 | pos = 32; | |
1646 | } | |
1647 | else | |
1648 | { | |
1649 | pos = 1; | |
1650 | while (op0 & 0x80000000) | |
1651 | { | |
1652 | op0 <<= 1; | |
1653 | pos++; | |
1654 | } | |
1655 | PSW &= ~PSW_CY; | |
1656 | PSW &= ~PSW_OV; | |
1657 | PSW &= ~PSW_S; | |
1658 | PSW &= ~PSW_Z; | |
1659 | } | |
1660 | ||
1661 | GR[reg3] = pos; | |
1662 | ||
1663 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1664 | } | |
1665 | ||
1666 | ||
1667 | ||
1668 | // SCH0R | |
1669 | rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r | |
1670 | *v850e2 | |
1671 | *v850e2v3 | |
67d7515b | 1672 | *v850e3v5 |
2aaed979 KB |
1673 | "sch0r r<reg2>, r<reg3>" |
1674 | { | |
1675 | unsigned int pos, op0; | |
1676 | ||
1677 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1678 | ||
1679 | op0 = GR[reg2]; | |
1680 | ||
1681 | if (op0 == 0xffffffff) | |
1682 | { | |
1683 | PSW &= ~PSW_CY; | |
1684 | PSW &= ~PSW_OV; | |
1685 | PSW &= ~PSW_S; | |
1686 | PSW |= PSW_Z; | |
1687 | pos = 0; | |
1688 | } | |
1689 | else if (op0 == 0x7fffffff) | |
1690 | { | |
1691 | PSW |= PSW_CY; | |
1692 | PSW &= ~PSW_OV; | |
1693 | PSW &= ~PSW_S; | |
1694 | PSW &= ~PSW_Z; | |
1695 | pos = 32; | |
1696 | } | |
1697 | else | |
1698 | { | |
1699 | pos = 1; | |
1700 | while (op0 & 0x00000001) | |
1701 | { | |
1702 | op0 >>= 1; | |
1703 | pos++; | |
1704 | } | |
1705 | PSW &= ~PSW_CY; | |
1706 | PSW &= ~PSW_OV; | |
1707 | PSW &= ~PSW_S; | |
1708 | PSW &= ~PSW_Z; | |
1709 | } | |
1710 | ||
1711 | GR[reg3] = pos; | |
1712 | ||
1713 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1714 | } | |
1715 | ||
1716 | // SCH1L | |
1717 | rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l | |
1718 | *v850e2 | |
1719 | *v850e2v3 | |
67d7515b | 1720 | *v850e3v5 |
2aaed979 KB |
1721 | "sch1l r<reg2>, r<reg3>" |
1722 | { | |
1723 | unsigned int pos, op0; | |
1724 | ||
1725 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1726 | ||
1727 | op0 = GR[reg2]; | |
1728 | ||
1729 | if (op0 == 0x00000000) | |
1730 | { | |
1731 | PSW &= ~PSW_CY; | |
1732 | PSW &= ~PSW_OV; | |
1733 | PSW &= ~PSW_S; | |
1734 | PSW |= PSW_Z; | |
1735 | pos = 0; | |
1736 | } | |
1737 | else if (op0 == 0x00000001) | |
1738 | { | |
1739 | PSW |= PSW_CY; | |
1740 | PSW &= ~PSW_OV; | |
1741 | PSW &= ~PSW_S; | |
1742 | PSW &= ~PSW_Z; | |
1743 | pos = 32; | |
1744 | } | |
1745 | else | |
1746 | { | |
1747 | pos = 1; | |
1748 | while (!(op0 & 0x80000000)) | |
1749 | { | |
1750 | op0 <<= 1; | |
1751 | pos++; | |
1752 | } | |
1753 | PSW &= ~PSW_CY; | |
1754 | PSW &= ~PSW_OV; | |
1755 | PSW &= ~PSW_S; | |
1756 | PSW &= ~PSW_Z; | |
1757 | } | |
1758 | ||
1759 | GR[reg3] = pos; | |
1760 | ||
1761 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1762 | } | |
1763 | ||
1764 | // SCH1R | |
1765 | rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r | |
1766 | *v850e2 | |
1767 | *v850e2v3 | |
67d7515b | 1768 | *v850e3v5 |
2aaed979 KB |
1769 | "sch1r r<reg2>, r<reg3>" |
1770 | { | |
1771 | unsigned int pos, op0; | |
1772 | ||
1773 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1774 | ||
1775 | op0 = GR[reg2]; | |
1776 | ||
1777 | if (op0 == 0x00000000) | |
1778 | { | |
1779 | PSW &= ~PSW_CY; | |
1780 | PSW &= ~PSW_OV; | |
1781 | PSW &= ~PSW_S; | |
1782 | PSW |= PSW_Z; | |
1783 | pos = 0; | |
1784 | } | |
1785 | else if (op0 == 0x80000000) | |
1786 | { | |
1787 | PSW |= PSW_CY; | |
1788 | PSW &= ~PSW_OV; | |
1789 | PSW &= ~PSW_S; | |
1790 | PSW &= ~PSW_Z; | |
1791 | pos = 32; | |
1792 | } | |
1793 | else | |
1794 | { | |
1795 | pos = 1; | |
1796 | while (!(op0 & 0x00000001)) | |
1797 | { | |
1798 | op0 >>= 1; | |
1799 | pos++; | |
1800 | } | |
1801 | PSW &= ~PSW_CY; | |
1802 | PSW &= ~PSW_OV; | |
1803 | PSW &= ~PSW_S; | |
1804 | PSW &= ~PSW_Z; | |
1805 | } | |
1806 | ||
1807 | GR[reg3] = pos; | |
1808 | ||
1809 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1810 | } | |
1811 | ||
1812 | //SHL | |
1813 | rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl | |
1814 | *v850e2 | |
1815 | *v850e2v3 | |
67d7515b | 1816 | *v850e3v5 |
2aaed979 KB |
1817 | "shl r<reg1>, r<reg2>, r<reg3>" |
1818 | { | |
1819 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1820 | v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1821 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1822 | } | |
1823 | ||
1824 | //SHR | |
1825 | rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr | |
1826 | *v850e2 | |
1827 | *v850e2v3 | |
67d7515b | 1828 | *v850e3v5 |
2aaed979 KB |
1829 | "shr r<reg1>, r<reg2>, r<reg3>" |
1830 | { | |
1831 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1832 | v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1833 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1834 | } | |
1835 | ||
1836 | ||
1837 | ||
c906108c SS |
1838 | // SETF |
1839 | rrrrr,1111110,cccc + 0000000000000000:IX:::setf | |
1840 | "setf %s<cccc>, r<reg2>" | |
1841 | { | |
1842 | COMPAT_2 (OP_7E0 ()); | |
1843 | } | |
1844 | ||
1845 | ||
1846 | ||
1847 | // SET1 | |
1848 | 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1 | |
1849 | "set1 <bit3>, <disp16>[r<reg1>]" | |
1850 | { | |
1851 | COMPAT_2 (OP_7C0 ()); | |
1852 | } | |
1853 | ||
1854 | rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 | |
1855 | *v850e | |
c5ea1d53 | 1856 | *v850e1 |
2aaed979 KB |
1857 | *v850e2 |
1858 | *v850e2v3 | |
67d7515b | 1859 | *v850e3v5 |
c906108c SS |
1860 | "set1 r<reg2>, [r<reg1>]" |
1861 | { | |
1862 | COMPAT_2 (OP_E007E0 ()); | |
1863 | } | |
1864 | ||
1865 | ||
1866 | ||
1867 | // SHL | |
1868 | rrrrr,111111,RRRRR + 0000000011000000:IX:::shl | |
1869 | "shl r<reg1>, r<reg2>" | |
1870 | { | |
1871 | COMPAT_2 (OP_C007E0 ()); | |
1872 | } | |
1873 | ||
1874 | rrrrr,010110,iiiii:II:::shl | |
1875 | "shl <imm5>, r<reg2>" | |
1876 | { | |
1877 | COMPAT_1 (OP_2C0 ()); | |
1878 | } | |
1879 | ||
1880 | ||
1881 | ||
1882 | // SHR | |
1883 | rrrrr,111111,RRRRR + 0000000010000000:IX:::shr | |
1884 | "shr r<reg1>, r<reg2>" | |
1885 | { | |
1886 | COMPAT_2 (OP_8007E0 ()); | |
1887 | } | |
1888 | ||
1889 | rrrrr,010100,iiiii:II:::shr | |
1890 | "shr <imm5>, r<reg2>" | |
1891 | { | |
1892 | COMPAT_1 (OP_280 ()); | |
1893 | } | |
1894 | ||
1895 | ||
1896 | ||
1897 | // SLD | |
1898 | rrrrr,0110,ddddddd:IV:::sld.b | |
1899 | "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US) | |
1900 | "sld.b <disp7>[ep], r<reg2>" | |
1901 | { | |
1902 | unsigned32 addr = EP + disp7; | |
1903 | unsigned32 result = load_mem (addr, 1); | |
1904 | if (PSW & PSW_US) | |
1905 | { | |
1906 | GR[reg2] = result; | |
1907 | TRACE_LD_NAME ("sld.bu", addr, result); | |
1908 | } | |
1909 | else | |
1910 | { | |
1911 | result = EXTEND8 (result); | |
1912 | GR[reg2] = result; | |
1913 | TRACE_LD (addr, result); | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | rrrrr,1000,ddddddd:IV:::sld.h | |
1918 | "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US) | |
1919 | "sld.h <disp8>[ep], r<reg2>" | |
1920 | { | |
1921 | unsigned32 addr = EP + disp8; | |
1922 | unsigned32 result = load_mem (addr, 2); | |
1923 | if (PSW & PSW_US) | |
1924 | { | |
1925 | GR[reg2] = result; | |
1926 | TRACE_LD_NAME ("sld.hu", addr, result); | |
1927 | } | |
1928 | else | |
1929 | { | |
1930 | result = EXTEND16 (result); | |
1931 | GR[reg2] = result; | |
1932 | TRACE_LD (addr, result); | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | rrrrr,1010,dddddd,0:IV:::sld.w | |
1937 | "sld.w <disp8>[ep], r<reg2>" | |
1938 | { | |
1939 | unsigned32 addr = EP + disp8; | |
1940 | unsigned32 result = load_mem (addr, 4); | |
1941 | GR[reg2] = result; | |
1942 | TRACE_LD (addr, result); | |
1943 | } | |
1944 | ||
1945 | rrrrr!0,0000110,dddd:IV:::sld.bu | |
1946 | *v850e | |
c5ea1d53 | 1947 | *v850e1 |
2aaed979 KB |
1948 | *v850e2 |
1949 | *v850e2v3 | |
67d7515b | 1950 | *v850e3v5 |
c906108c SS |
1951 | "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US) |
1952 | "sld.bu <disp4>[ep], r<reg2>" | |
1953 | { | |
1954 | unsigned32 addr = EP + disp4; | |
1955 | unsigned32 result = load_mem (addr, 1); | |
1956 | if (PSW & PSW_US) | |
1957 | { | |
1958 | result = EXTEND8 (result); | |
1959 | GR[reg2] = result; | |
1960 | TRACE_LD_NAME ("sld.b", addr, result); | |
1961 | } | |
1962 | else | |
1963 | { | |
1964 | GR[reg2] = result; | |
1965 | TRACE_LD (addr, result); | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | rrrrr!0,0000111,dddd:IV:::sld.hu | |
1970 | *v850e | |
c5ea1d53 | 1971 | *v850e1 |
2aaed979 KB |
1972 | *v850e2 |
1973 | *v850e2v3 | |
67d7515b | 1974 | *v850e3v5 |
c906108c SS |
1975 | "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US) |
1976 | "sld.hu <disp5>[ep], r<reg2>" | |
1977 | { | |
1978 | unsigned32 addr = EP + disp5; | |
1979 | unsigned32 result = load_mem (addr, 2); | |
1980 | if (PSW & PSW_US) | |
1981 | { | |
1982 | result = EXTEND16 (result); | |
1983 | GR[reg2] = result; | |
1984 | TRACE_LD_NAME ("sld.h", addr, result); | |
1985 | } | |
1986 | else | |
1987 | { | |
1988 | GR[reg2] = result; | |
1989 | TRACE_LD (addr, result); | |
1990 | } | |
1991 | } | |
1992 | ||
2aaed979 KB |
1993 | |
1994 | ||
c906108c SS |
1995 | // SST |
1996 | rrrrr,0111,ddddddd:IV:::sst.b | |
1997 | "sst.b r<reg2>, <disp7>[ep]" | |
1998 | { | |
1999 | COMPAT_1 (OP_380 ()); | |
2000 | } | |
2001 | ||
2002 | rrrrr,1001,ddddddd:IV:::sst.h | |
2003 | "sst.h r<reg2>, <disp8>[ep]" | |
2004 | { | |
2005 | COMPAT_1 (OP_480 ()); | |
2006 | } | |
2007 | ||
2008 | rrrrr,1010,dddddd,1:IV:::sst.w | |
2009 | "sst.w r<reg2>, <disp8>[ep]" | |
2010 | { | |
2011 | COMPAT_1 (OP_501 ()); | |
2012 | } | |
2013 | ||
c906108c SS |
2014 | // ST |
2015 | rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b | |
2016 | "st.b r<reg2>, <disp16>[r<reg1>]" | |
2017 | { | |
2018 | COMPAT_2 (OP_740 ()); | |
2019 | } | |
2020 | ||
2aaed979 KB |
2021 | 00000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b |
2022 | *v850e2v3 | |
67d7515b | 2023 | *v850e3v5 |
2aaed979 KB |
2024 | "st.b r<reg3>, <disp23>[r<reg1>]" |
2025 | { | |
2026 | unsigned32 addr = GR[reg1] + disp23; | |
2027 | store_data_mem (sd, addr, 1, GR[reg3]); | |
2028 | TRACE_ST (addr, GR[reg3]); | |
2029 | } | |
2030 | ||
c906108c SS |
2031 | rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h |
2032 | "st.h r<reg2>, <disp16>[r<reg1>]" | |
2033 | { | |
2034 | COMPAT_2 (OP_760 ()); | |
2035 | } | |
2036 | ||
2aaed979 KB |
2037 | 00000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h |
2038 | *v850e2v3 | |
67d7515b | 2039 | *v850e3v5 |
2aaed979 KB |
2040 | "st.h r<reg3>, <disp23>[r<reg1>]" |
2041 | { | |
2042 | unsigned32 addr = GR[reg1] + disp23; | |
2043 | store_data_mem (sd, addr, 2, GR[reg3]); | |
2044 | TRACE_ST (addr, GR[reg3]); | |
2045 | } | |
2046 | ||
2047 | rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w | |
c906108c SS |
2048 | "st.w r<reg2>, <disp16>[r<reg1>]" |
2049 | { | |
2050 | COMPAT_2 (OP_10760 ()); | |
2051 | } | |
2052 | ||
2aaed979 KB |
2053 | 00000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w |
2054 | *v850e2v3 | |
67d7515b | 2055 | *v850e3v5 |
2aaed979 KB |
2056 | "st.w r<reg3>, <disp23>[r<reg1>]" |
2057 | { | |
2058 | unsigned32 addr = GR[reg1] + disp23; | |
2059 | store_data_mem (sd, addr, 4, GR[reg3]); | |
2060 | TRACE_ST (addr, GR[reg3]); | |
2061 | } | |
2062 | ||
67d7515b NC |
2063 | 00000111101,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.dw |
2064 | *v850e3v5 | |
2065 | "st.dw r<reg3>, <disp23>[r<reg1>]" | |
2066 | { | |
2067 | unsigned32 addr = GR[reg1] + disp23; | |
2068 | store_data_mem (sd, addr, 4, GR[reg3]); | |
2069 | TRACE_ST (addr, GR[reg3]); | |
2070 | store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]); | |
2071 | TRACE_ST (addr + 4, GR[reg3 + 1]); | |
2072 | } | |
2073 | ||
2aaed979 | 2074 | |
c906108c SS |
2075 | // STSR |
2076 | rrrrr,111111,regID + 0000000001000000:IX:::stsr | |
2077 | "stsr s<regID>, r<reg2>" | |
2078 | { | |
2aaed979 KB |
2079 | uint32 sreg = 0; |
2080 | ||
2081 | if ((idecode_issue == idecode_v850e2_issue | |
67d7515b | 2082 | || idecode_issue == idecode_v850e3v5_issue |
2aaed979 KB |
2083 | || idecode_issue == idecode_v850e2v3_issue) |
2084 | && regID < 28) | |
2085 | { | |
2086 | switch (BSEL & 0xffff) | |
2087 | { | |
2088 | case 0x0000: | |
2089 | case 0xff00: /* USER 0 */ | |
2090 | case 0xffff: /* USER 1 */ | |
2091 | sreg = SR[regID]; | |
2092 | break; | |
2093 | case 0x1000: | |
2094 | sreg = MPU0_SR[regID]; | |
2095 | break; | |
2096 | case 0x1001: | |
2097 | sreg = MPU1_SR[regID]; | |
2098 | break; | |
2099 | case 0x2000: | |
2100 | if (regID == FPST_REGNO) | |
2101 | { | |
2102 | sreg = ((FPSR & FPSR_PR) ? FPST_PR : 0) | |
2103 | | ((FPSR & FPSR_XCE) ? FPST_XCE : 0) | |
2104 | | ((FPSR & FPSR_XCV) ? FPST_XCV : 0) | |
2105 | | ((FPSR & FPSR_XCZ) ? FPST_XCZ : 0) | |
2106 | | ((FPSR & FPSR_XCO) ? FPST_XCO : 0) | |
2107 | | ((FPSR & FPSR_XCU) ? FPST_XCU : 0) | |
2108 | | ((FPSR & FPSR_XCI) ? FPST_XCI : 0) | |
2109 | | ((FPSR & FPSR_XPV) ? FPST_XPV : 0) | |
2110 | | ((FPSR & FPSR_XPZ) ? FPST_XPZ : 0) | |
2111 | | ((FPSR & FPSR_XPO) ? FPST_XPO : 0) | |
2112 | | ((FPSR & FPSR_XPU) ? FPST_XPU : 0) | |
2113 | | ((FPSR & FPSR_XPI) ? FPST_XPI : 0); | |
2114 | } | |
2115 | else if (regID == FPCFG_REGNO) | |
2116 | { | |
2117 | sreg = (((FPSR & FPSR_RM) >> 18) << 7) | |
2118 | | ((FPSR & FPSR_XEV) ? FPCFG_XEV : 0) | |
2119 | | ((FPSR & FPSR_XEZ) ? FPCFG_XEZ : 0) | |
2120 | | ((FPSR & FPSR_XEO) ? FPCFG_XEO : 0) | |
2121 | | ((FPSR & FPSR_XEU) ? FPCFG_XEU : 0) | |
2122 | | ((FPSR & FPSR_XEI) ? FPCFG_XEI : 0); | |
2123 | } | |
2124 | else | |
2125 | { | |
2126 | sreg = FPU_SR[regID]; | |
2127 | } | |
2128 | break; | |
2129 | } | |
2130 | } | |
2131 | else | |
2132 | { | |
2133 | sreg = SR[regID]; | |
2134 | } | |
2135 | ||
2136 | TRACE_ALU_INPUT1 (sreg); | |
2137 | GR[reg2] = sreg; | |
c906108c SS |
2138 | TRACE_ALU_RESULT (GR[reg2]); |
2139 | } | |
2140 | ||
c906108c SS |
2141 | // SUB |
2142 | rrrrr,001101,RRRRR:I:::sub | |
2143 | "sub r<reg1>, r<reg2>" | |
2144 | { | |
2145 | COMPAT_1 (OP_1A0 ()); | |
2146 | } | |
2147 | ||
c906108c SS |
2148 | // SUBR |
2149 | rrrrr,001100,RRRRR:I:::subr | |
2150 | "subr r<reg1>, r<reg2>" | |
2151 | { | |
2152 | COMPAT_1 (OP_180 ()); | |
2153 | } | |
2154 | ||
c906108c SS |
2155 | // SWITCH |
2156 | 00000000010,RRRRR:I:::switch | |
2157 | *v850e | |
c5ea1d53 | 2158 | *v850e1 |
2aaed979 KB |
2159 | *v850e2 |
2160 | *v850e2v3 | |
67d7515b | 2161 | *v850e3v5 |
c906108c SS |
2162 | "switch r<reg1>" |
2163 | { | |
2164 | unsigned long adr; | |
2165 | SAVE_1; | |
2166 | trace_input ("switch", OP_REG, 0); | |
2167 | adr = (cia + 2) + (State.regs[ reg1 ] << 1); | |
2168 | nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1); | |
2169 | trace_output (OP_REG); | |
2170 | } | |
2171 | ||
c906108c SS |
2172 | // SXB |
2173 | 00000000101,RRRRR:I:::sxb | |
2174 | *v850e | |
c5ea1d53 | 2175 | *v850e1 |
2aaed979 KB |
2176 | *v850e2 |
2177 | *v850e2v3 | |
67d7515b | 2178 | *v850e3v5 |
c906108c SS |
2179 | "sxb r<reg1>" |
2180 | { | |
2181 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2182 | GR[reg1] = EXTEND8 (GR[reg1]); | |
2183 | TRACE_ALU_RESULT (GR[reg1]); | |
2184 | } | |
2185 | ||
2186 | // SXH | |
2187 | 00000000111,RRRRR:I:::sxh | |
2188 | *v850e | |
c5ea1d53 | 2189 | *v850e1 |
2aaed979 KB |
2190 | *v850e2 |
2191 | *v850e2v3 | |
67d7515b | 2192 | *v850e3v5 |
c906108c SS |
2193 | "sxh r<reg1>" |
2194 | { | |
2195 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2196 | GR[reg1] = EXTEND16 (GR[reg1]); | |
2197 | TRACE_ALU_RESULT (GR[reg1]); | |
2198 | } | |
2199 | ||
c906108c SS |
2200 | // TRAP |
2201 | 00000111111,iiiii + 0000000100000000:X:::trap | |
2202 | "trap <vector>" | |
2203 | { | |
2204 | COMPAT_2 (OP_10007E0 ()); | |
2205 | } | |
2206 | ||
c906108c SS |
2207 | // TST |
2208 | rrrrr,001011,RRRRR:I:::tst | |
2209 | "tst r<reg1>, r<reg2>" | |
2210 | { | |
2211 | COMPAT_1 (OP_160 ()); | |
2212 | } | |
2213 | ||
c906108c SS |
2214 | // TST1 |
2215 | 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1 | |
2216 | "tst1 <bit3>, <disp16>[r<reg1>]" | |
2217 | { | |
2218 | COMPAT_2 (OP_C7C0 ()); | |
2219 | } | |
2220 | ||
2221 | rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 | |
2222 | *v850e | |
c5ea1d53 | 2223 | *v850e1 |
2aaed979 KB |
2224 | *v850e2 |
2225 | *v850e2v3 | |
67d7515b | 2226 | *v850e3v5 |
c906108c SS |
2227 | "tst1 r<reg2>, [r<reg1>]" |
2228 | { | |
2229 | COMPAT_2 (OP_E607E0 ()); | |
2230 | } | |
2231 | ||
c906108c SS |
2232 | // XOR |
2233 | rrrrr,001001,RRRRR:I:::xor | |
2234 | "xor r<reg1>, r<reg2>" | |
2235 | { | |
2236 | COMPAT_1 (OP_120 ()); | |
2237 | } | |
2238 | ||
c906108c SS |
2239 | // XORI |
2240 | rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori | |
2241 | "xori <uimm16>, r<reg1>, r<reg2>" | |
2242 | { | |
2243 | COMPAT_2 (OP_6A0 ()); | |
2244 | } | |
2245 | ||
c906108c SS |
2246 | // ZXB |
2247 | 00000000100,RRRRR:I:::zxb | |
2248 | *v850e | |
c5ea1d53 | 2249 | *v850e1 |
2aaed979 KB |
2250 | *v850e2 |
2251 | *v850e2v3 | |
67d7515b | 2252 | *v850e3v5 |
c906108c SS |
2253 | "zxb r<reg1>" |
2254 | { | |
2255 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2256 | GR[reg1] = GR[reg1] & 0xff; | |
2257 | TRACE_ALU_RESULT (GR[reg1]); | |
2258 | } | |
2259 | ||
2260 | // ZXH | |
2261 | 00000000110,RRRRR:I:::zxh | |
2262 | *v850e | |
c5ea1d53 | 2263 | *v850e1 |
2aaed979 KB |
2264 | *v850e2 |
2265 | *v850e2v3 | |
67d7515b | 2266 | *v850e3v5 |
c906108c SS |
2267 | "zxh r<reg1>" |
2268 | { | |
2269 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2270 | GR[reg1] = GR[reg1] & 0xffff; | |
2271 | TRACE_ALU_RESULT (GR[reg1]); | |
2272 | } | |
2273 | ||
c906108c SS |
2274 | // Right field must be zero so that it doesn't clash with DIVH |
2275 | // Left field must be non-zero so that it doesn't clash with SWITCH | |
2276 | 11111,000010,00000:I:::break | |
c5ea1d53 NC |
2277 | *v850 |
2278 | *v850e | |
c906108c SS |
2279 | { |
2280 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
2281 | } | |
2282 | ||
c5ea1d53 NC |
2283 | 11111,000010,00000:I:::dbtrap |
2284 | *v850e1 | |
2aaed979 KB |
2285 | *v850e2 |
2286 | *v850e2v3 | |
67d7515b | 2287 | *v850e3v5 |
c5ea1d53 NC |
2288 | "dbtrap" |
2289 | { | |
85367826 NC |
2290 | if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG) |
2291 | { | |
2292 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
2293 | } | |
2294 | else | |
2295 | { | |
2296 | DBPC = cia + 2; | |
2297 | DBPSW = PSW; | |
2298 | PSW = PSW | (PSW_NP | PSW_EP | PSW_ID); | |
2299 | PC = 0x00000060; | |
2300 | nia = 0x00000060; | |
2301 | TRACE_BRANCH0 (); | |
2302 | } | |
c5ea1d53 NC |
2303 | } |
2304 | ||
de616bc7 FCE |
2305 | // New breakpoint: 0x7E0 0x7E0 |
2306 | 00000,111111,00000 + 00000,11111,100000:X:::ilgop | |
2307 | { | |
2308 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
2309 | } | |
c5ea1d53 NC |
2310 | |
2311 | // Return from debug trap: 0x146007e0 | |
2312 | 0000011111100000 + 0000000101000110:X:::dbret | |
2313 | *v850e1 | |
2aaed979 KB |
2314 | *v850e2 |
2315 | *v850e2v3 | |
67d7515b | 2316 | *v850e3v5 |
c5ea1d53 NC |
2317 | "dbret" |
2318 | { | |
2319 | nia = DBPC; | |
2320 | PSW = DBPSW; | |
2321 | TRACE_BRANCH1 (PSW); | |
2322 | } | |
2aaed979 KB |
2323 | |
2324 | ||
2325 | // | |
2326 | // FLOAT | |
2327 | // | |
2328 | ||
2329 | // Map condition code to a string | |
2330 | :%s::::FFFF:int FFFF | |
2331 | { | |
2332 | switch (FFFF) | |
2333 | { | |
2334 | case 0: return "f"; | |
2335 | case 1: return "un"; | |
2336 | case 2: return "eq"; | |
2337 | case 3: return "ueq"; | |
2338 | case 4: return "olt"; | |
2339 | case 5: return "ult"; | |
2340 | case 6: return "ole"; | |
2341 | case 7: return "ule"; | |
2342 | case 8: return "sf"; | |
2343 | case 9: return "ngle"; | |
2344 | case 10: return "seq"; | |
2345 | case 11: return "ngl"; | |
2346 | case 12: return "lt"; | |
2347 | case 13: return "nge"; | |
2348 | case 14: return "le"; | |
2349 | case 15: return "ngt"; | |
2350 | } | |
2351 | return "(null)"; | |
2352 | } | |
2353 | ||
2354 | // ABSF.D | |
2355 | rrrr,011111100000 + wwww,010001011000:F_I:::absf_d | |
2356 | *v850e2v3 | |
67d7515b | 2357 | *v850e3v5 |
2aaed979 KB |
2358 | "absf.d r<reg2e>, r<reg3e>" |
2359 | { | |
2360 | sim_fpu ans, wop; | |
2361 | sim_fpu_status status; | |
2362 | ||
2363 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2364 | TRACE_FP_INPUT_FPU1 (&wop); | |
2365 | ||
2366 | status = sim_fpu_abs (&ans, &wop); | |
2367 | check_invalid_snan(sd, status, 1); | |
2368 | ||
2369 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2370 | ||
2371 | TRACE_FP_RESULT_FPU1 (&ans); | |
2372 | } | |
2373 | ||
2374 | // ABSF.S | |
2375 | rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s | |
2376 | *v850e2v3 | |
67d7515b | 2377 | *v850e3v5 |
2aaed979 KB |
2378 | "absf.s r<reg2>, r<reg3>" |
2379 | { | |
2380 | sim_fpu ans, wop; | |
2381 | sim_fpu_status status; | |
2382 | ||
2383 | sim_fpu_32to (&wop, GR[reg2]); | |
2384 | TRACE_FP_INPUT_FPU1 (&wop); | |
2385 | ||
2386 | status = sim_fpu_abs (&ans, &wop); | |
2387 | check_invalid_snan(sd, status, 0); | |
2388 | ||
2389 | sim_fpu_to32 (&GR[reg3], &ans); | |
2390 | TRACE_FP_RESULT_FPU1 (&ans); | |
2391 | } | |
2392 | ||
2393 | // ADDF.D | |
2394 | rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d | |
2395 | *v850e2v3 | |
67d7515b | 2396 | *v850e3v5 |
2aaed979 KB |
2397 | "addf.d r<reg1e>, r<reg2e>, r<reg3e>" |
2398 | { | |
2399 | sim_fpu ans, wop1, wop2; | |
2400 | sim_fpu_status status; | |
2401 | ||
2402 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2403 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2404 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2405 | ||
2406 | status = sim_fpu_add (&ans, &wop1, &wop2); | |
2407 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2408 | ||
2409 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
2410 | ||
2411 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2412 | TRACE_FP_RESULT_FPU1 (&ans); | |
2413 | } | |
2414 | ||
2415 | // ADDF.S | |
2416 | rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s | |
2417 | *v850e2v3 | |
67d7515b | 2418 | *v850e3v5 |
2aaed979 KB |
2419 | "addf.s r<reg1>, r<reg2>, r<reg3>" |
2420 | { | |
2421 | sim_fpu ans, wop1, wop2; | |
2422 | sim_fpu_status status; | |
2423 | ||
2424 | sim_fpu_32to (&wop1, GR[reg1]); | |
2425 | sim_fpu_32to (&wop2, GR[reg2]); | |
2426 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2427 | ||
2428 | status = sim_fpu_add (&ans, &wop1, &wop2); | |
2429 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2430 | ||
2431 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2432 | ||
2433 | sim_fpu_to32 (&GR[reg3], &ans); | |
2434 | TRACE_FP_RESULT_FPU1 (&ans); | |
2435 | } | |
2436 | ||
2437 | // CMOVF.D | |
2438 | rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d | |
2439 | *v850e2v3 | |
67d7515b | 2440 | *v850e3v5 |
2aaed979 KB |
2441 | "cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>" |
2442 | { | |
2443 | unsigned int ophi,oplow; | |
2444 | sim_fpu ans, wop1, wop2; | |
2445 | ||
2446 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2447 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2448 | TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); | |
2449 | ||
2450 | if (TEST_FPCC(bbb)) | |
2451 | { | |
2452 | ophi = GR[reg1e+1]; | |
2453 | oplow = GR[reg1e]; | |
2454 | ans = wop1; | |
2455 | } | |
2456 | else | |
2457 | { | |
2458 | ophi = GR[reg2e+1]; | |
2459 | oplow = GR[reg2e]; | |
2460 | ans = wop2; | |
2461 | } | |
2462 | ||
2463 | GR[reg3e+1] = ophi; | |
2464 | GR[reg3e] = oplow; | |
2465 | TRACE_FP_RESULT_FPU1 (&ans);; | |
2466 | } | |
2467 | ||
2468 | // CMOVF.S | |
d99ff40f | 2469 | rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s |
2aaed979 | 2470 | *v850e2v3 |
67d7515b | 2471 | *v850e3v5 |
2aaed979 KB |
2472 | "cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>" |
2473 | { | |
2474 | unsigned int op; | |
2475 | sim_fpu ans, wop1, wop2; | |
2476 | ||
2477 | sim_fpu_32to (&wop1, GR[reg1]); | |
2478 | sim_fpu_32to (&wop2, GR[reg2]); | |
2479 | TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); | |
2480 | ||
2481 | if (TEST_FPCC(bbb)) | |
2482 | { | |
2483 | op = GR[reg1]; | |
2484 | ans = wop1; | |
2485 | } | |
2486 | else | |
2487 | { | |
2488 | op = GR[reg2]; | |
2489 | ans = wop2; | |
2490 | } | |
2491 | ||
2492 | GR[reg3] = op; | |
2493 | TRACE_FP_RESULT_FPU1 (&ans); | |
2494 | } | |
2495 | ||
2496 | // CMPF.D | |
2497 | rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d | |
2498 | *v850e2v3 | |
67d7515b | 2499 | *v850e3v5 |
85367826 NC |
2500 | "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0) |
2501 | "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>" | |
2aaed979 KB |
2502 | { |
2503 | int result; | |
2504 | sim_fpu wop1; | |
2505 | sim_fpu wop2; | |
2506 | ||
2507 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2508 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
85367826 | 2509 | TRACE_FP_INPUT_FPU2 (&wop2, &wop1); |
2aaed979 | 2510 | |
85367826 | 2511 | result = v850_float_compare(sd, FFFF, wop2, wop1, 1); |
2aaed979 KB |
2512 | |
2513 | if (result) | |
2514 | SET_FPCC(bbb); | |
2515 | else | |
2516 | CLEAR_FPCC(bbb); | |
2517 | ||
2518 | TRACE_FP_RESULT_BOOL (result); | |
2519 | } | |
2520 | ||
2521 | // CMPF.S | |
2522 | rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s | |
2523 | *v850e2v3 | |
67d7515b | 2524 | *v850e3v5 |
85367826 NC |
2525 | "cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0) |
2526 | "cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>" | |
2aaed979 KB |
2527 | { |
2528 | int result; | |
2529 | sim_fpu wop1; | |
2530 | sim_fpu wop2; | |
2531 | ||
2532 | sim_fpu_32to( &wop1, GR[reg1] ); | |
2533 | sim_fpu_32to( &wop2, GR[reg2] ); | |
85367826 | 2534 | TRACE_FP_INPUT_FPU2 (&wop2, &wop1); |
2aaed979 | 2535 | |
85367826 | 2536 | result = v850_float_compare(sd, FFFF, wop2, wop1, 0); |
2aaed979 KB |
2537 | |
2538 | if (result) | |
2539 | SET_FPCC(bbb); | |
2540 | else | |
2541 | CLEAR_FPCC(bbb); | |
2542 | ||
2543 | TRACE_FP_RESULT_BOOL (result); | |
2544 | } | |
2545 | ||
2546 | // CVTF.DL | |
2547 | rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl | |
2548 | *v850e2v3 | |
67d7515b | 2549 | *v850e3v5 |
2aaed979 KB |
2550 | "cvtf.dl r<reg2e>, r<reg3e>" |
2551 | { | |
2552 | unsigned64 ans; | |
2553 | sim_fpu wop; | |
2554 | sim_fpu_status status; | |
2555 | ||
2556 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2557 | TRACE_FP_INPUT_FPU1 (&wop); | |
2558 | ||
2559 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2560 | status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); | |
2561 | ||
2562 | check_cvt_fi(sd, status, 1); | |
2563 | ||
2564 | GR[reg3e] = ans; | |
2565 | GR[reg3e+1] = ans>>32L; | |
2566 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
2567 | } | |
2568 | ||
2569 | // CVTF.DS | |
2570 | rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds | |
2571 | *v850e2v3 | |
67d7515b | 2572 | *v850e3v5 |
2aaed979 KB |
2573 | "cvtf.ds r<reg2e>, r<reg3>" |
2574 | { | |
2575 | sim_fpu wop; | |
2576 | sim_fpu_status status; | |
2577 | ||
2578 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2579 | TRACE_FP_INPUT_FPU1 (&wop); | |
2580 | ||
2581 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2582 | ||
2583 | check_cvt_fi(sd, status, 0); | |
2584 | ||
2585 | sim_fpu_to32 (&GR[reg3], &wop); | |
2586 | TRACE_FP_RESULT_FPU1 (&wop); | |
2587 | } | |
2588 | ||
2589 | // CVTF.DW | |
2590 | rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw | |
2591 | *v850e2v3 | |
67d7515b | 2592 | *v850e3v5 |
2aaed979 KB |
2593 | "cvtf.dw r<reg2e>, r<reg3>" |
2594 | { | |
2595 | uint32 ans; | |
2596 | sim_fpu wop; | |
2597 | sim_fpu_status status; | |
2598 | ||
2599 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2600 | TRACE_FP_INPUT_FPU1 (&wop); | |
2601 | ||
2602 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2603 | status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND()); | |
2604 | ||
2605 | check_cvt_fi(sd, status, 1); | |
2606 | ||
2607 | GR[reg3] = ans; | |
2608 | TRACE_FP_RESULT_WORD1 (ans); | |
2609 | } | |
2610 | ||
2611 | // CVTF.LD | |
2612 | rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld | |
2613 | *v850e2v3 | |
67d7515b | 2614 | *v850e3v5 |
2aaed979 KB |
2615 | "cvtf.ld r<reg2e>, r<reg3e>" |
2616 | { | |
2617 | signed64 op; | |
2618 | sim_fpu wop; | |
2619 | sim_fpu_status status; | |
2620 | ||
2621 | op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; | |
2622 | TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); | |
2623 | ||
2624 | sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); | |
2625 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2626 | ||
2627 | check_cvt_if(sd, status, 1); | |
2628 | ||
2629 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2630 | TRACE_FP_RESULT_FPU1 (&wop); | |
2631 | } | |
2632 | ||
2633 | // CVTF.LS | |
2634 | rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls | |
2635 | *v850e2v3 | |
67d7515b | 2636 | *v850e3v5 |
2aaed979 KB |
2637 | "cvtf.ls r<reg2e>, r<reg3>" |
2638 | { | |
2639 | signed64 op; | |
2640 | sim_fpu wop; | |
2641 | sim_fpu_status status; | |
2642 | ||
2643 | op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; | |
2644 | TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); | |
2645 | ||
2646 | sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); | |
2647 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2648 | ||
2649 | check_cvt_if(sd, status, 0); | |
2650 | ||
2651 | sim_fpu_to32 (&GR[reg3], &wop); | |
2652 | TRACE_FP_RESULT_FPU1 (&wop); | |
2653 | } | |
2654 | ||
2655 | // CVTF.SD | |
2656 | rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd | |
2657 | *v850e2v3 | |
67d7515b | 2658 | *v850e3v5 |
2aaed979 KB |
2659 | "cvtf.sd r<reg2>, r<reg3e>" |
2660 | { | |
2661 | sim_fpu wop; | |
2662 | sim_fpu_status status; | |
2663 | ||
2664 | sim_fpu_32to (&wop, GR[reg2]); | |
2665 | TRACE_FP_INPUT_FPU1 (&wop); | |
2666 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2667 | ||
2668 | check_cvt_ff(sd, status, 1); | |
2669 | ||
2670 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2671 | TRACE_FP_RESULT_FPU1 (&wop); | |
2672 | } | |
2673 | ||
2674 | // CVTF.SL | |
2675 | rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl | |
2676 | *v850e2v3 | |
67d7515b | 2677 | *v850e3v5 |
2aaed979 KB |
2678 | "cvtf.sl r<reg2>, r<reg3e>" |
2679 | { | |
2680 | signed64 ans; | |
2681 | sim_fpu wop; | |
2682 | sim_fpu_status status; | |
2683 | ||
2684 | sim_fpu_32to (&wop, GR[reg2]); | |
2685 | TRACE_FP_INPUT_FPU1 (&wop); | |
2686 | ||
2687 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2688 | status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); | |
2689 | ||
2690 | check_cvt_fi(sd, status, 0); | |
2691 | ||
2692 | GR[reg3e] = ans; | |
2693 | GR[reg3e+1] = ans >> 32L; | |
2694 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
2695 | } | |
2696 | ||
2697 | // CVTF.SW | |
2698 | rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw | |
2699 | *v850e2v3 | |
67d7515b | 2700 | *v850e3v5 |
2aaed979 KB |
2701 | "cvtf.sw r<reg2>, r<reg3>" |
2702 | { | |
2703 | uint32 ans; | |
2704 | sim_fpu wop; | |
2705 | sim_fpu_status status; | |
2706 | ||
2707 | sim_fpu_32to (&wop, GR[reg2]); | |
2708 | TRACE_FP_INPUT_FPU1 (&wop); | |
2709 | ||
2710 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2711 | status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); | |
2712 | ||
2713 | check_cvt_fi(sd, status, 0); | |
2714 | ||
2715 | GR[reg3] = ans; | |
2716 | TRACE_FP_RESULT_WORD1 (ans); | |
2717 | } | |
2718 | ||
2719 | // CVTF.WD | |
2720 | rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd | |
2721 | *v850e2v3 | |
67d7515b | 2722 | *v850e3v5 |
2aaed979 KB |
2723 | "cvtf.wd r<reg2>, r<reg3e>" |
2724 | { | |
2725 | sim_fpu wop; | |
2726 | sim_fpu_status status; | |
2727 | ||
2728 | TRACE_FP_INPUT_WORD1 (GR[reg2]); | |
2729 | sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); | |
2730 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2731 | ||
2732 | check_cvt_if(sd, status, 1); | |
2733 | ||
2734 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2735 | TRACE_FP_RESULT_FPU1 (&wop); | |
2736 | } | |
2737 | ||
2738 | // CVTF.WS | |
2739 | rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws | |
2740 | *v850e2v3 | |
67d7515b | 2741 | *v850e3v5 |
2aaed979 KB |
2742 | "cvtf.ws r<reg2>, r<reg3>" |
2743 | { | |
2744 | sim_fpu wop; | |
2745 | sim_fpu_status status; | |
2746 | ||
2747 | TRACE_FP_INPUT_WORD1 (GR[reg2]); | |
2748 | sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); | |
2749 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2750 | ||
2751 | check_cvt_if(sd, status, 0); | |
2752 | ||
2753 | sim_fpu_to32 (&GR[reg3], &wop); | |
2754 | TRACE_FP_RESULT_FPU1 (&wop); | |
2755 | } | |
2756 | ||
2757 | // DIVF.D | |
2758 | rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d | |
2759 | *v850e2v3 | |
67d7515b | 2760 | *v850e3v5 |
2aaed979 KB |
2761 | "divf.d r<reg1e>, r<reg2e>, r<reg3e>" |
2762 | { | |
2763 | sim_fpu ans, wop1, wop2; | |
2764 | sim_fpu_status status; | |
2765 | ||
2766 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2767 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2768 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2769 | ||
2770 | status = sim_fpu_div (&ans, &wop2, &wop1); | |
2771 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2772 | ||
2773 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
2774 | ||
2775 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2776 | TRACE_FP_RESULT_FPU1 (&ans); | |
2777 | } | |
2778 | ||
2779 | // DIVF.S | |
2780 | rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s | |
2781 | *v850e2v3 | |
67d7515b | 2782 | *v850e3v5 |
2aaed979 KB |
2783 | "divf.s r<reg1>, r<reg2>, r<reg3>" |
2784 | { | |
2785 | sim_fpu ans, wop1, wop2; | |
2786 | sim_fpu_status status; | |
2787 | ||
2788 | sim_fpu_32to (&wop1, GR[reg1]); | |
2789 | sim_fpu_32to (&wop2, GR[reg2]); | |
2790 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2791 | ||
2792 | status = sim_fpu_div (&ans, &wop2, &wop1); | |
2793 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2794 | ||
2795 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2796 | ||
2797 | sim_fpu_to32 (&GR[reg3], &ans); | |
2798 | TRACE_FP_RESULT_FPU1 (&ans); | |
2799 | } | |
2800 | ||
2801 | // MADDF.S | |
2802 | rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s | |
2803 | *v850e2v3 | |
67d7515b | 2804 | *v850e3v5 |
2aaed979 KB |
2805 | "maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" |
2806 | { | |
2807 | sim_fpu ans, wop1, wop2, wop3; | |
2808 | sim_fpu_status status; | |
2809 | ||
2810 | sim_fpu_32to (&wop1, GR[reg1]); | |
2811 | sim_fpu_32to (&wop2, GR[reg2]); | |
2812 | sim_fpu_32to (&wop3, GR[reg3]); | |
2813 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2814 | ||
2815 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2aaed979 KB |
2816 | wop1 = ans; |
2817 | status |= sim_fpu_add (&ans, &wop1, &wop3); | |
2818 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2819 | ||
2820 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2821 | ||
2822 | sim_fpu_to32 (&GR[reg4], &ans); | |
2823 | TRACE_FP_RESULT_FPU1 (&ans); | |
2824 | } | |
2825 | ||
2826 | // MAXF.D | |
2827 | rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d | |
2828 | *v850e2v3 | |
67d7515b | 2829 | *v850e3v5 |
2aaed979 KB |
2830 | "maxf.d r<reg1e>, r<reg2e>, r<reg3e>" |
2831 | { | |
2832 | sim_fpu ans, wop1, wop2; | |
2833 | ||
2834 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2835 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2836 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2837 | ||
2838 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2839 | { | |
2840 | if (FPSR & FPSR_XEV) | |
2841 | { | |
2842 | SignalExceptionFPE(sd, 1); | |
2843 | } | |
2844 | else | |
2845 | { | |
2846 | ans = sim_fpu_qnan; | |
2847 | } | |
2848 | } | |
2849 | else if (FPSR & FPSR_FS | |
2850 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2851 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2852 | { | |
2853 | ans = sim_fpu_zero; | |
2854 | } | |
2855 | else | |
2856 | { | |
2857 | sim_fpu_max (&ans, &wop1, &wop2); | |
2858 | } | |
2859 | ||
2860 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2861 | TRACE_FP_RESULT_FPU1 (&ans); | |
2862 | } | |
2863 | ||
2864 | // MAXF.S | |
2865 | rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s | |
2866 | *v850e2v3 | |
67d7515b | 2867 | *v850e3v5 |
2aaed979 KB |
2868 | "maxf.s r<reg1>, r<reg2>, r<reg3>" |
2869 | { | |
2870 | sim_fpu ans, wop1, wop2; | |
2871 | ||
2872 | sim_fpu_32to (&wop1, GR[reg1]); | |
2873 | sim_fpu_32to (&wop2, GR[reg2]); | |
2874 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2875 | ||
2876 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2877 | { | |
2878 | if (FPSR & FPSR_XEV) | |
2879 | { | |
2880 | SignalExceptionFPE(sd, 0); | |
2881 | } | |
2882 | else | |
2883 | { | |
2884 | ans = sim_fpu_qnan; | |
2885 | } | |
2886 | } | |
2887 | else if ((FPSR & FPSR_FS) | |
2888 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2889 | && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2)))) | |
2890 | { | |
2891 | ans = sim_fpu_zero; | |
2892 | } | |
2893 | else | |
2894 | { | |
2895 | sim_fpu_max (&ans, &wop1, &wop2); | |
2896 | } | |
2897 | ||
2898 | sim_fpu_to32 (&GR[reg3], &ans); | |
2899 | TRACE_FP_RESULT_FPU1 (&ans); | |
2900 | } | |
2901 | ||
2902 | // MINF.D | |
2903 | rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d | |
2904 | *v850e2v3 | |
67d7515b | 2905 | *v850e3v5 |
2aaed979 KB |
2906 | "minf.d r<reg1e>, r<reg2e>, r<reg3e>" |
2907 | { | |
2908 | sim_fpu ans, wop1, wop2; | |
2909 | ||
2910 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2911 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2912 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2913 | ||
2914 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2915 | { | |
2916 | if (FPSR & FPSR_XEV) | |
2917 | { | |
2918 | SignalExceptionFPE(sd, 1); | |
2919 | } | |
2920 | else | |
2921 | { | |
2922 | ans = sim_fpu_qnan; | |
2923 | } | |
2924 | } | |
2925 | else if (FPSR & FPSR_FS | |
2926 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2927 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2928 | { | |
2929 | ans = sim_fpu_zero; | |
2930 | } | |
2931 | else | |
2932 | { | |
2933 | sim_fpu_min (&ans, &wop1, &wop2); | |
2934 | } | |
2935 | ||
2936 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2937 | TRACE_FP_RESULT_FPU1 (&ans); | |
2938 | } | |
2939 | ||
2940 | // MINF.S | |
2941 | rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s | |
2942 | *v850e2v3 | |
67d7515b | 2943 | *v850e3v5 |
2aaed979 KB |
2944 | "minf.s r<reg1>, r<reg2>, r<reg3>" |
2945 | { | |
2946 | sim_fpu ans, wop1, wop2; | |
2947 | ||
2948 | sim_fpu_32to (&wop1, GR[reg1]); | |
2949 | sim_fpu_32to (&wop2, GR[reg2]); | |
2950 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2951 | ||
2952 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2953 | { | |
2954 | if (FPSR & FPSR_XEV) | |
2955 | { | |
2956 | SignalExceptionFPE(sd, 0); | |
2957 | } | |
2958 | else | |
2959 | { | |
2960 | ans = sim_fpu_qnan; | |
2961 | } | |
2962 | } | |
2963 | else if (FPSR & FPSR_FS | |
2964 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2965 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2966 | { | |
2967 | ans = sim_fpu_zero; | |
2968 | } | |
2969 | else | |
2970 | { | |
2971 | sim_fpu_min (&ans, &wop1, &wop2); | |
2972 | } | |
2973 | ||
2974 | sim_fpu_to32 (&GR[reg3], &ans); | |
2975 | TRACE_FP_RESULT_FPU1 (&ans); | |
2976 | } | |
2977 | ||
2978 | // MSUBF.S | |
2979 | rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s | |
2980 | *v850e2v3 | |
67d7515b | 2981 | *v850e3v5 |
2aaed979 KB |
2982 | "msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" |
2983 | { | |
2984 | sim_fpu ans, wop1, wop2, wop3; | |
2985 | sim_fpu_status status; | |
2986 | ||
2987 | sim_fpu_32to (&wop1, GR[reg1]); | |
2988 | sim_fpu_32to (&wop2, GR[reg2]); | |
2989 | sim_fpu_32to (&wop3, GR[reg3]); | |
2990 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2991 | ||
2992 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2993 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2994 | wop1 = ans; | |
2995 | status |= sim_fpu_sub (&ans, &wop1, &wop3); | |
2996 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2997 | ||
2998 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2999 | ||
3000 | sim_fpu_to32 (&GR[reg4], &ans); | |
3001 | TRACE_FP_RESULT_FPU1 (&ans); | |
3002 | } | |
3003 | ||
3004 | // MULF.D | |
3005 | rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d | |
3006 | *v850e2v3 | |
67d7515b | 3007 | *v850e3v5 |
2aaed979 KB |
3008 | "mulf.d r<reg1e>, r<reg2e>, r<reg3e>" |
3009 | { | |
3010 | sim_fpu ans, wop1, wop2; | |
3011 | sim_fpu_status status; | |
3012 | ||
3013 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
3014 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
3015 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3016 | ||
3017 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
3018 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3019 | ||
3020 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3021 | ||
3022 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3023 | TRACE_FP_RESULT_FPU1 (&ans); | |
3024 | } | |
3025 | ||
3026 | // MULF.S | |
3027 | rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s | |
3028 | *v850e2v3 | |
67d7515b | 3029 | *v850e3v5 |
2aaed979 KB |
3030 | "mulf.s r<reg1>, r<reg2>, r<reg3>" |
3031 | { | |
3032 | sim_fpu ans, wop1, wop2; | |
3033 | sim_fpu_status status; | |
3034 | ||
3035 | sim_fpu_32to (&wop1, GR[reg1]); | |
3036 | sim_fpu_32to (&wop2, GR[reg2]); | |
3037 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3038 | ||
3039 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
3040 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3041 | ||
3042 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3043 | ||
3044 | sim_fpu_to32 (&GR[reg3], &ans); | |
3045 | TRACE_FP_RESULT_FPU1 (&ans); | |
3046 | } | |
3047 | ||
3048 | // NEGF.D | |
3049 | rrrr,011111100001 + wwww,010001011000:F_I:::negf_d | |
3050 | *v850e2v3 | |
67d7515b | 3051 | *v850e3v5 |
2aaed979 KB |
3052 | "negf.d r<reg2e>, r<reg3e>" |
3053 | { | |
3054 | sim_fpu ans, wop; | |
3055 | sim_fpu_status status; | |
3056 | ||
3057 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3058 | TRACE_FP_INPUT_FPU1 (&wop); | |
3059 | ||
3060 | status = sim_fpu_neg (&ans, &wop); | |
3061 | ||
3062 | check_invalid_snan(sd, status, 1); | |
3063 | ||
3064 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3065 | TRACE_FP_RESULT_FPU1 (&ans); | |
3066 | } | |
3067 | ||
3068 | // NEGF.S | |
3069 | rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s | |
3070 | *v850e2v3 | |
67d7515b | 3071 | *v850e3v5 |
2aaed979 KB |
3072 | "negf.s r<reg2>, r<reg3>" |
3073 | { | |
3074 | sim_fpu ans, wop; | |
3075 | sim_fpu_status status; | |
3076 | ||
3077 | sim_fpu_32to (&wop, GR[reg2]); | |
3078 | TRACE_FP_INPUT_FPU1 (&wop); | |
3079 | ||
3080 | status = sim_fpu_neg (&ans, &wop); | |
3081 | ||
3082 | check_invalid_snan(sd, status, 0); | |
3083 | ||
3084 | sim_fpu_to32 (&GR[reg3], &ans); | |
3085 | TRACE_FP_RESULT_FPU1 (&ans); | |
3086 | } | |
3087 | ||
3088 | // NMADDF.S | |
3089 | rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s | |
3090 | *v850e2v3 | |
67d7515b | 3091 | *v850e3v5 |
2aaed979 KB |
3092 | "nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" |
3093 | { | |
3094 | sim_fpu ans, wop1, wop2, wop3; | |
3095 | sim_fpu_status status; | |
3096 | ||
3097 | sim_fpu_32to (&wop1, GR[reg1]); | |
3098 | sim_fpu_32to (&wop2, GR[reg2]); | |
3099 | sim_fpu_32to (&wop3, GR[reg3]); | |
3100 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
3101 | ||
3102 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2aaed979 KB |
3103 | wop1 = ans; |
3104 | status |= sim_fpu_add (&ans, &wop1, &wop3); | |
3105 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3106 | wop1 = ans; | |
3107 | status |= sim_fpu_neg (&ans, &wop1); | |
3108 | ||
3109 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3110 | ||
3111 | sim_fpu_to32 (&GR[reg4], &ans); | |
3112 | TRACE_FP_RESULT_FPU1 (&ans); | |
3113 | } | |
3114 | ||
3115 | // NMSUBF.S | |
3116 | rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s | |
3117 | *v850e2v3 | |
67d7515b | 3118 | *v850e3v5 |
2aaed979 KB |
3119 | "nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" |
3120 | { | |
3121 | sim_fpu ans, wop1, wop2, wop3; | |
3122 | sim_fpu_status status; | |
3123 | ||
3124 | sim_fpu_32to (&wop1, GR[reg1]); | |
3125 | sim_fpu_32to (&wop2, GR[reg2]); | |
3126 | sim_fpu_32to (&wop3, GR[reg3]); | |
3127 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
3128 | ||
3129 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
3130 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3131 | wop1 = ans; | |
3132 | status |= sim_fpu_sub (&ans, &wop1, &wop3); | |
3133 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3134 | wop1 = ans; | |
3135 | status |= sim_fpu_neg (&ans, &wop1); | |
3136 | ||
3137 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3138 | ||
3139 | sim_fpu_to32 (&GR[reg4], &ans); | |
3140 | TRACE_FP_RESULT_FPU1 (&ans); | |
3141 | } | |
3142 | ||
3143 | // RECIPF.D | |
3144 | rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d | |
3145 | *v850e2v3 | |
67d7515b | 3146 | *v850e3v5 |
2aaed979 KB |
3147 | "recipf.d r<reg2e>, r<reg3e>" |
3148 | { | |
3149 | sim_fpu ans, wop; | |
3150 | sim_fpu_status status; | |
3151 | ||
3152 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3153 | TRACE_FP_INPUT_FPU1 (&wop); | |
3154 | ||
3155 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3156 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3157 | ||
3158 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3159 | ||
3160 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3161 | TRACE_FP_RESULT_FPU1 (&ans); | |
3162 | } | |
3163 | ||
3164 | // RECIPF.S | |
3165 | rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s | |
3166 | *v850e2v3 | |
67d7515b | 3167 | *v850e3v5 |
2aaed979 KB |
3168 | "recipf.s r<reg2>, r<reg3>" |
3169 | { | |
3170 | sim_fpu ans, wop; | |
3171 | sim_fpu_status status; | |
3172 | ||
3173 | sim_fpu_32to (&wop, GR[reg2]); | |
3174 | TRACE_FP_INPUT_FPU1 (&wop); | |
3175 | ||
3176 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3177 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3178 | ||
3179 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3180 | ||
3181 | sim_fpu_to32 (&GR[reg3], &ans); | |
3182 | TRACE_FP_RESULT_FPU1 (&ans); | |
3183 | } | |
3184 | ||
3185 | // RSQRTF.D | |
3186 | rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d | |
3187 | *v850e2v3 | |
67d7515b | 3188 | *v850e3v5 |
2aaed979 KB |
3189 | "rsqrtf.d r<reg2e>, r<reg3e>" |
3190 | { | |
3191 | sim_fpu ans, wop; | |
3192 | sim_fpu_status status; | |
3193 | ||
3194 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3195 | TRACE_FP_INPUT_FPU1 (&wop); | |
3196 | ||
3197 | status = sim_fpu_sqrt (&ans, &wop); | |
3198 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3199 | wop = ans; | |
3200 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3201 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3202 | ||
3203 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3204 | ||
3205 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3206 | TRACE_FP_RESULT_FPU1 (&ans); | |
3207 | } | |
3208 | ||
3209 | // RSQRTF.S | |
3210 | rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s | |
3211 | *v850e2v3 | |
67d7515b | 3212 | *v850e3v5 |
2aaed979 KB |
3213 | "rsqrtf.s r<reg2>, r<reg3>" |
3214 | { | |
3215 | sim_fpu ans, wop; | |
3216 | sim_fpu_status status; | |
3217 | ||
3218 | sim_fpu_32to (&wop, GR[reg2]); | |
3219 | TRACE_FP_INPUT_FPU1 (&wop); | |
3220 | ||
3221 | status = sim_fpu_sqrt (&ans, &wop); | |
3222 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3223 | wop = ans; | |
3224 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3225 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3226 | ||
3227 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3228 | ||
3229 | sim_fpu_to32 (&GR[reg3], &ans); | |
3230 | TRACE_FP_RESULT_FPU1 (&ans); | |
3231 | } | |
3232 | ||
3233 | // SQRTF.D | |
3234 | rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d | |
3235 | *v850e2v3 | |
67d7515b | 3236 | *v850e3v5 |
2aaed979 KB |
3237 | "sqrtf.d r<reg2e>, r<reg3e>" |
3238 | { | |
3239 | sim_fpu ans, wop; | |
3240 | sim_fpu_status status; | |
3241 | ||
3242 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3243 | TRACE_FP_INPUT_FPU1 (&wop); | |
3244 | ||
3245 | status = sim_fpu_sqrt (&ans, &wop); | |
3246 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3247 | ||
3248 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1); | |
3249 | ||
3250 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3251 | TRACE_FP_RESULT_FPU1 (&ans); | |
3252 | } | |
3253 | ||
3254 | // SQRTF.S | |
3255 | rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s | |
3256 | *v850e2v3 | |
67d7515b | 3257 | *v850e3v5 |
2aaed979 KB |
3258 | "sqrtf.s r<reg2>, r<reg3>" |
3259 | { | |
3260 | sim_fpu ans, wop; | |
3261 | sim_fpu_status status; | |
3262 | ||
3263 | sim_fpu_32to (&wop, GR[reg2]); | |
3264 | TRACE_FP_INPUT_FPU1 (&wop); | |
3265 | ||
3266 | status = sim_fpu_sqrt (&ans, &wop); | |
3267 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3268 | ||
3269 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0); | |
3270 | ||
3271 | sim_fpu_to32 (&GR[reg3], &ans); | |
3272 | TRACE_FP_RESULT_FPU1 (&ans); | |
3273 | } | |
3274 | ||
3275 | // SUBF.D | |
3276 | rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d | |
3277 | *v850e2v3 | |
67d7515b | 3278 | *v850e3v5 |
2aaed979 KB |
3279 | "subf.d r<reg1e>, r<reg2e>, r<reg3e>" |
3280 | { | |
3281 | sim_fpu ans, wop1, wop2; | |
3282 | sim_fpu_status status; | |
3283 | ||
3284 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
3285 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
3286 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3287 | ||
3288 | status = sim_fpu_sub (&ans, &wop2, &wop1); | |
3289 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3290 | ||
3291 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3292 | ||
3293 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3294 | TRACE_FP_RESULT_FPU1 (&ans); | |
3295 | } | |
3296 | ||
3297 | // SUBF.S | |
3298 | rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s | |
3299 | *v850e2v3 | |
67d7515b | 3300 | *v850e3v5 |
2aaed979 KB |
3301 | "subf.s r<reg1>, r<reg2>, r<reg3>" |
3302 | { | |
3303 | sim_fpu ans, wop1, wop2; | |
3304 | sim_fpu_status status; | |
3305 | ||
3306 | sim_fpu_32to (&wop1, GR[reg1]); | |
3307 | sim_fpu_32to (&wop2, GR[reg2]); | |
3308 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3309 | ||
3310 | status = sim_fpu_sub (&ans, &wop2, &wop1); | |
3311 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3312 | ||
3313 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3314 | ||
3315 | sim_fpu_to32 (&GR[reg3], &ans); | |
3316 | TRACE_FP_RESULT_FPU1 (&ans); | |
3317 | } | |
3318 | ||
3319 | // TRFSR | |
3320 | 0000011111100000 + 000001000000,bbb,0:F_I:::trfsr | |
3321 | *v850e2v3 | |
67d7515b | 3322 | *v850e3v5 |
2aaed979 KB |
3323 | "trfsr":(bbb == 0) |
3324 | "trfsr <bbb>" | |
3325 | { | |
3326 | TRACE_ALU_INPUT1 (GET_FPCC()); | |
3327 | ||
3328 | if (TEST_FPCC (bbb)) | |
3329 | PSW |= PSW_Z; | |
3330 | else | |
3331 | PSW &= ~PSW_Z; | |
3332 | ||
3333 | TRACE_ALU_RESULT1 (PSW); | |
3334 | } | |
3335 | ||
3336 | // TRNCF.DL | |
3337 | rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl | |
3338 | *v850e2v3 | |
67d7515b | 3339 | *v850e3v5 |
2aaed979 KB |
3340 | "trncf.dl r<reg2e>, r<reg3e>" |
3341 | { | |
3342 | signed64 ans; | |
3343 | sim_fpu wop; | |
3344 | sim_fpu_status status; | |
3345 | ||
3346 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3347 | TRACE_FP_INPUT_FPU1 (&wop); | |
3348 | ||
d99ff40f | 3349 | status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3350 | |
3351 | check_cvt_fi(sd, status, 1); | |
3352 | ||
3353 | GR[reg3e] = ans; | |
3354 | GR[reg3e+1] = ans>>32L; | |
3355 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3356 | } | |
3357 | ||
85367826 NC |
3358 | // TRNCF.DUL |
3359 | rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul | |
3360 | *v850e2v3 | |
67d7515b | 3361 | *v850e3v5 |
85367826 NC |
3362 | "trncf.dul r<reg2e>, r<reg3e>" |
3363 | { | |
3364 | signed64 ans; | |
3365 | sim_fpu wop; | |
3366 | sim_fpu_status status; | |
3367 | ||
3368 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3369 | TRACE_FP_INPUT_FPU1 (&wop); | |
3370 | ||
3371 | status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); | |
3372 | ||
3373 | check_cvt_fi(sd, status, 1); | |
3374 | ||
3375 | GR[reg3e] = ans; | |
3376 | GR[reg3e+1] = ans>>32L; | |
3377 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3378 | } | |
3379 | ||
2aaed979 KB |
3380 | // TRNCF.DW |
3381 | rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw | |
3382 | *v850e2v3 | |
67d7515b | 3383 | *v850e3v5 |
2aaed979 KB |
3384 | "trncf.dw r<reg2e>, r<reg3>" |
3385 | { | |
3386 | uint32 ans; | |
3387 | sim_fpu wop; | |
3388 | sim_fpu_status status; | |
3389 | ||
3390 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3391 | TRACE_FP_INPUT_FPU1 (&wop); | |
3392 | ||
d99ff40f | 3393 | status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3394 | |
3395 | check_cvt_fi(sd, status, 1); | |
3396 | ||
3397 | GR[reg3] = ans; | |
3398 | TRACE_FP_RESULT_WORD1 (ans); | |
3399 | } | |
3400 | ||
85367826 NC |
3401 | // TRNCF.DUW |
3402 | rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw | |
3403 | *v850e2v3 | |
67d7515b | 3404 | *v850e3v5 |
85367826 NC |
3405 | "trncf.duw r<reg2e>, r<reg3>" |
3406 | { | |
3407 | uint32 ans; | |
3408 | sim_fpu wop; | |
3409 | sim_fpu_status status; | |
3410 | ||
3411 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3412 | TRACE_FP_INPUT_FPU1 (&wop); | |
3413 | ||
3414 | status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero); | |
3415 | ||
3416 | check_cvt_fi(sd, status, 1); | |
3417 | ||
3418 | GR[reg3] = ans; | |
3419 | TRACE_FP_RESULT_WORD1 (ans); | |
3420 | } | |
3421 | ||
2aaed979 KB |
3422 | // TRNCF.SL |
3423 | rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl | |
3424 | *v850e2v3 | |
67d7515b | 3425 | *v850e3v5 |
2aaed979 KB |
3426 | "trncf.sl r<reg2>, r<reg3e>" |
3427 | { | |
3428 | signed64 ans; | |
3429 | sim_fpu wop; | |
3430 | sim_fpu_status status; | |
3431 | ||
3432 | sim_fpu_32to (&wop, GR[reg2]); | |
3433 | TRACE_FP_INPUT_FPU1 (&wop); | |
3434 | ||
d99ff40f | 3435 | status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3436 | |
3437 | GR[reg3e] = ans; | |
3438 | GR[reg3e+1] = ans >> 32L; | |
3439 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3440 | } | |
3441 | ||
85367826 NC |
3442 | // TRNCF.SUL |
3443 | rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul | |
3444 | *v850e2v3 | |
67d7515b | 3445 | *v850e3v5 |
85367826 NC |
3446 | "trncf.sul r<reg2>, r<reg3e>" |
3447 | { | |
3448 | signed64 ans; | |
3449 | sim_fpu wop; | |
3450 | sim_fpu_status status; | |
3451 | ||
3452 | sim_fpu_32to (&wop, GR[reg2]); | |
3453 | TRACE_FP_INPUT_FPU1 (&wop); | |
3454 | ||
3455 | status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); | |
3456 | ||
3457 | GR[reg3e] = ans; | |
3458 | GR[reg3e+1] = ans >> 32L; | |
3459 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3460 | } | |
3461 | ||
2aaed979 KB |
3462 | // TRNCF.SW |
3463 | rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw | |
3464 | *v850e2v3 | |
67d7515b | 3465 | *v850e3v5 |
2aaed979 KB |
3466 | "trncf.sw r<reg2>, r<reg3>" |
3467 | { | |
3468 | uint32 ans; | |
3469 | sim_fpu wop; | |
3470 | sim_fpu_status status; | |
3471 | ||
3472 | sim_fpu_32to (&wop, GR[reg2]); | |
3473 | TRACE_FP_INPUT_FPU1 (&wop); | |
3474 | ||
d99ff40f | 3475 | status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3476 | |
3477 | check_cvt_fi(sd, status, 0); | |
3478 | ||
3479 | GR[reg3] = ans; | |
3480 | TRACE_FP_RESULT_WORD1 (ans); | |
3481 | } | |
85367826 NC |
3482 | |
3483 | ||
3484 | // TRNCF.SUW | |
3485 | rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw | |
3486 | *v850e2v3 | |
67d7515b | 3487 | *v850e3v5 |
85367826 NC |
3488 | "trncf.suw r<reg2>, r<reg3>" |
3489 | { | |
3490 | uint32 ans; | |
3491 | sim_fpu wop; | |
3492 | sim_fpu_status status; | |
3493 | ||
3494 | sim_fpu_32to (&wop, GR[reg2]); | |
3495 | TRACE_FP_INPUT_FPU1 (&wop); | |
3496 | ||
3497 | status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero); | |
3498 | ||
3499 | check_cvt_fi(sd, status, 0); | |
3500 | ||
3501 | GR[reg3] = ans; | |
3502 | TRACE_FP_RESULT_WORD1 (ans); | |
3503 | } | |
67d7515b NC |
3504 | |
3505 | ||
3506 | // ROTL | |
3507 | rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm | |
3508 | *v850e3v5 | |
3509 | "rotl imm5, r<reg2>, r<reg3>" | |
3510 | { | |
3511 | TRACE_ALU_INPUT1 (GR[reg2]); | |
3512 | v850_rotl (sd, imm5, GR[reg2], & GR[reg3]); | |
3513 | TRACE_ALU_RESULT1 (GR[reg3]); | |
3514 | } | |
3515 | ||
3516 | rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl | |
3517 | *v850e3v5 | |
3518 | "rotl r<reg1>, r<reg2>, r<reg3>" | |
3519 | { | |
3520 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
3521 | v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]); | |
3522 | TRACE_ALU_RESULT1 (GR[reg3]); | |
3523 | } | |
3524 | ||
3525 | // BINS | |
3526 | rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top | |
3527 | *v850e3v5 | |
3528 | "bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>" | |
3529 | { | |
3530 | TRACE_ALU_INPUT1 (GR[reg1]); | |
3531 | v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]); | |
3532 | TRACE_ALU_RESULT1 (GR[reg2]); | |
3533 | } | |
3534 | ||
3535 | rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle | |
3536 | *v850e3v5 | |
3537 | "bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>" | |
3538 | { | |
3539 | TRACE_ALU_INPUT1 (GR[reg1]); | |
3540 | v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]); | |
3541 | TRACE_ALU_RESULT1 (GR[reg2]); | |
3542 | } | |
3543 | ||
3544 | rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom | |
3545 | *v850e3v5 | |
3546 | "bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>" | |
3547 | { | |
3548 | TRACE_ALU_INPUT1 (GR[reg1]); | |
3549 | v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]); | |
3550 | TRACE_ALU_RESULT1 (GR[reg2]); | |
3551 | } |