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cb5a6ffc RK |
1 | /* |
2 | * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Documentation: ARM DDI 0173B | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/err.h> | |
a62c80e5 | 20 | #include <linux/amba/bus.h> |
cb5a6ffc RK |
21 | |
22 | #include <asm/io.h> | |
23 | #include <asm/irq.h> | |
c6b8fdad | 24 | #include <asm/sizes.h> |
cb5a6ffc RK |
25 | |
26 | #include <sound/driver.h> | |
27 | #include <sound/core.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/ac97_codec.h> | |
30 | #include <sound/pcm.h> | |
31 | #include <sound/pcm_params.h> | |
32 | ||
33 | #include "aaci.h" | |
34 | #include "devdma.h" | |
35 | ||
36 | #define DRIVER_NAME "aaci-pl041" | |
37 | ||
38 | /* | |
39 | * PM support is not complete. Turn it off. | |
40 | */ | |
41 | #undef CONFIG_PM | |
42 | ||
ceb9e476 | 43 | static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) |
cb5a6ffc RK |
44 | { |
45 | u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); | |
46 | ||
47 | /* | |
48 | * Ensure that the slot 1/2 RX registers are empty. | |
49 | */ | |
50 | v = readl(aaci->base + AACI_SLFR); | |
51 | if (v & SLFR_2RXV) | |
52 | readl(aaci->base + AACI_SL2RX); | |
53 | if (v & SLFR_1RXV) | |
54 | readl(aaci->base + AACI_SL1RX); | |
55 | ||
56 | writel(maincr, aaci->base + AACI_MAINCR); | |
57 | } | |
58 | ||
59 | /* | |
60 | * P29: | |
61 | * The recommended use of programming the external codec through slot 1 | |
62 | * and slot 2 data is to use the channels during setup routines and the | |
63 | * slot register at any other time. The data written into slot 1, slot 2 | |
64 | * and slot 12 registers is transmitted only when their corresponding | |
65 | * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR | |
66 | * register. | |
67 | */ | |
ceb9e476 | 68 | static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) |
cb5a6ffc RK |
69 | { |
70 | struct aaci *aaci = ac97->private_data; | |
71 | u32 v; | |
72 | ||
73 | if (ac97->num >= 4) | |
74 | return; | |
75 | ||
12aa7579 | 76 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
77 | |
78 | aaci_ac97_select_codec(aaci, ac97); | |
79 | ||
80 | /* | |
81 | * P54: You must ensure that AACI_SL2TX is always written | |
82 | * to, if required, before data is written to AACI_SL1TX. | |
83 | */ | |
84 | writel(val << 4, aaci->base + AACI_SL2TX); | |
85 | writel(reg << 12, aaci->base + AACI_SL1TX); | |
86 | ||
87 | /* | |
88 | * Wait for the transmission of both slots to complete. | |
89 | */ | |
90 | do { | |
91 | v = readl(aaci->base + AACI_SLFR); | |
92 | } while (v & (SLFR_1TXB|SLFR_2TXB)); | |
93 | ||
12aa7579 | 94 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
95 | } |
96 | ||
97 | /* | |
98 | * Read an AC'97 register. | |
99 | */ | |
ceb9e476 | 100 | static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
cb5a6ffc RK |
101 | { |
102 | struct aaci *aaci = ac97->private_data; | |
103 | u32 v; | |
104 | ||
105 | if (ac97->num >= 4) | |
106 | return ~0; | |
107 | ||
12aa7579 | 108 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
109 | |
110 | aaci_ac97_select_codec(aaci, ac97); | |
111 | ||
112 | /* | |
113 | * Write the register address to slot 1. | |
114 | */ | |
115 | writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); | |
116 | ||
117 | /* | |
118 | * Wait for the transmission to complete. | |
119 | */ | |
120 | do { | |
121 | v = readl(aaci->base + AACI_SLFR); | |
122 | } while (v & SLFR_1TXB); | |
123 | ||
124 | /* | |
125 | * Give the AC'97 codec more than enough time | |
126 | * to respond. (42us = ~2 frames at 48kHz.) | |
127 | */ | |
128 | udelay(42); | |
129 | ||
130 | /* | |
131 | * Wait for slot 2 to indicate data. | |
132 | */ | |
133 | do { | |
134 | cond_resched(); | |
135 | v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); | |
136 | } while (v != (SLFR_1RXV|SLFR_2RXV)); | |
137 | ||
138 | v = readl(aaci->base + AACI_SL1RX) >> 12; | |
139 | if (v == reg) { | |
140 | v = readl(aaci->base + AACI_SL2RX) >> 4; | |
141 | } else { | |
142 | dev_err(&aaci->dev->dev, | |
143 | "wrong ac97 register read back (%x != %x)\n", | |
144 | v, reg); | |
145 | v = ~0; | |
146 | } | |
147 | ||
12aa7579 | 148 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
149 | return v; |
150 | } | |
151 | ||
152 | static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun) | |
153 | { | |
154 | u32 val; | |
155 | int timeout = 5000; | |
156 | ||
157 | do { | |
158 | val = readl(aacirun->base + AACI_SR); | |
159 | } while (val & (SR_TXB|SR_RXB) && timeout--); | |
160 | } | |
161 | ||
162 | ||
163 | ||
164 | /* | |
165 | * Interrupt support. | |
166 | */ | |
62578cbf | 167 | static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) |
cb5a6ffc | 168 | { |
41762b8c KH |
169 | if (mask & ISR_ORINTR) { |
170 | dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); | |
171 | writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); | |
172 | } | |
173 | ||
174 | if (mask & ISR_RXTOINTR) { | |
175 | dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); | |
176 | writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); | |
177 | } | |
178 | ||
179 | if (mask & ISR_RXINTR) { | |
180 | struct aaci_runtime *aacirun = &aaci->capture; | |
181 | void *ptr; | |
182 | ||
183 | if (!aacirun->substream || !aacirun->start) { | |
184 | dev_warn(&aaci->dev->dev, "RX interrupt???"); | |
185 | writel(0, aacirun->base + AACI_IE); | |
186 | return; | |
187 | } | |
188 | ptr = aacirun->ptr; | |
189 | ||
190 | do { | |
191 | unsigned int len = aacirun->fifosz; | |
192 | u32 val; | |
193 | ||
194 | if (aacirun->bytes <= 0) { | |
195 | aacirun->bytes += aacirun->period; | |
196 | aacirun->ptr = ptr; | |
197 | spin_unlock(&aaci->lock); | |
198 | snd_pcm_period_elapsed(aacirun->substream); | |
199 | spin_lock(&aaci->lock); | |
200 | } | |
201 | if (!(aacirun->cr & CR_EN)) | |
202 | break; | |
203 | ||
204 | val = readl(aacirun->base + AACI_SR); | |
205 | if (!(val & SR_RXHF)) | |
206 | break; | |
207 | if (!(val & SR_RXFF)) | |
208 | len >>= 1; | |
209 | ||
210 | aacirun->bytes -= len; | |
211 | ||
212 | /* reading 16 bytes at a time */ | |
213 | for( ; len > 0; len -= 16) { | |
214 | asm( | |
215 | "ldmia %1, {r0, r1, r2, r3}\n\t" | |
216 | "stmia %0!, {r0, r1, r2, r3}" | |
217 | : "+r" (ptr) | |
218 | : "r" (aacirun->fifo) | |
219 | : "r0", "r1", "r2", "r3", "cc"); | |
220 | ||
221 | if (ptr >= aacirun->end) | |
222 | ptr = aacirun->start; | |
223 | } | |
224 | } while(1); | |
225 | aacirun->ptr = ptr; | |
226 | } | |
227 | ||
cb5a6ffc | 228 | if (mask & ISR_URINTR) { |
62578cbf KH |
229 | dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); |
230 | writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); | |
cb5a6ffc RK |
231 | } |
232 | ||
233 | if (mask & ISR_TXINTR) { | |
234 | struct aaci_runtime *aacirun = &aaci->playback; | |
235 | void *ptr; | |
236 | ||
237 | if (!aacirun->substream || !aacirun->start) { | |
238 | dev_warn(&aaci->dev->dev, "TX interrupt???"); | |
239 | writel(0, aacirun->base + AACI_IE); | |
240 | return; | |
241 | } | |
242 | ||
243 | ptr = aacirun->ptr; | |
244 | do { | |
245 | unsigned int len = aacirun->fifosz; | |
246 | u32 val; | |
247 | ||
248 | if (aacirun->bytes <= 0) { | |
249 | aacirun->bytes += aacirun->period; | |
250 | aacirun->ptr = ptr; | |
251 | spin_unlock(&aaci->lock); | |
252 | snd_pcm_period_elapsed(aacirun->substream); | |
253 | spin_lock(&aaci->lock); | |
254 | } | |
41762b8c | 255 | if (!(aacirun->cr & CR_EN)) |
cb5a6ffc RK |
256 | break; |
257 | ||
258 | val = readl(aacirun->base + AACI_SR); | |
259 | if (!(val & SR_TXHE)) | |
260 | break; | |
261 | if (!(val & SR_TXFE)) | |
262 | len >>= 1; | |
263 | ||
264 | aacirun->bytes -= len; | |
265 | ||
266 | /* writing 16 bytes at a time */ | |
267 | for ( ; len > 0; len -= 16) { | |
268 | asm( | |
269 | "ldmia %0!, {r0, r1, r2, r3}\n\t" | |
270 | "stmia %1, {r0, r1, r2, r3}" | |
271 | : "+r" (ptr) | |
272 | : "r" (aacirun->fifo) | |
273 | : "r0", "r1", "r2", "r3", "cc"); | |
274 | ||
275 | if (ptr >= aacirun->end) | |
276 | ptr = aacirun->start; | |
277 | } | |
278 | } while (1); | |
279 | ||
280 | aacirun->ptr = ptr; | |
281 | } | |
282 | } | |
283 | ||
7d12e780 | 284 | static irqreturn_t aaci_irq(int irq, void *devid) |
cb5a6ffc RK |
285 | { |
286 | struct aaci *aaci = devid; | |
287 | u32 mask; | |
288 | int i; | |
289 | ||
290 | spin_lock(&aaci->lock); | |
291 | mask = readl(aaci->base + AACI_ALLINTS); | |
292 | if (mask) { | |
293 | u32 m = mask; | |
294 | for (i = 0; i < 4; i++, m >>= 7) { | |
295 | if (m & 0x7f) { | |
62578cbf | 296 | aaci_fifo_irq(aaci, i, m); |
cb5a6ffc RK |
297 | } |
298 | } | |
299 | } | |
300 | spin_unlock(&aaci->lock); | |
301 | ||
302 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
303 | } | |
304 | ||
305 | ||
306 | ||
307 | /* | |
308 | * ALSA support. | |
309 | */ | |
310 | ||
311 | struct aaci_stream { | |
312 | unsigned char codec_idx; | |
313 | unsigned char rate_idx; | |
314 | }; | |
315 | ||
316 | static struct aaci_stream aaci_streams[] = { | |
317 | [ACSTREAM_FRONT] = { | |
318 | .codec_idx = 0, | |
319 | .rate_idx = AC97_RATES_FRONT_DAC, | |
320 | }, | |
321 | [ACSTREAM_SURROUND] = { | |
322 | .codec_idx = 0, | |
323 | .rate_idx = AC97_RATES_SURR_DAC, | |
324 | }, | |
325 | [ACSTREAM_LFE] = { | |
326 | .codec_idx = 0, | |
327 | .rate_idx = AC97_RATES_LFE_DAC, | |
328 | }, | |
329 | }; | |
330 | ||
331 | static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid) | |
332 | { | |
333 | struct aaci_stream *s = aaci_streams + streamid; | |
334 | return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx]; | |
335 | } | |
336 | ||
337 | static unsigned int rate_list[] = { | |
338 | 5512, 8000, 11025, 16000, 22050, 32000, 44100, | |
339 | 48000, 64000, 88200, 96000, 176400, 192000 | |
340 | }; | |
341 | ||
342 | /* | |
343 | * Double-rate rule: we can support double rate iff channels == 2 | |
344 | * (unimplemented) | |
345 | */ | |
346 | static int | |
ceb9e476 | 347 | aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) |
cb5a6ffc RK |
348 | { |
349 | struct aaci *aaci = rule->private; | |
350 | unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512; | |
ceb9e476 | 351 | struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS); |
cb5a6ffc RK |
352 | |
353 | switch (c->max) { | |
354 | case 6: | |
355 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE); | |
356 | case 4: | |
357 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND); | |
358 | case 2: | |
359 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT); | |
360 | } | |
361 | ||
362 | return snd_interval_list(hw_param_interval(p, rule->var), | |
363 | ARRAY_SIZE(rate_list), rate_list, | |
364 | rate_mask); | |
365 | } | |
366 | ||
ceb9e476 | 367 | static struct snd_pcm_hardware aaci_hw_info = { |
cb5a6ffc RK |
368 | .info = SNDRV_PCM_INFO_MMAP | |
369 | SNDRV_PCM_INFO_MMAP_VALID | | |
370 | SNDRV_PCM_INFO_INTERLEAVED | | |
371 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
372 | SNDRV_PCM_INFO_RESUME, | |
373 | ||
374 | /* | |
375 | * ALSA doesn't support 18-bit or 20-bit packed into 32-bit | |
376 | * words. It also doesn't support 12-bit at all. | |
377 | */ | |
378 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
379 | ||
380 | /* should this be continuous or knot? */ | |
381 | .rates = SNDRV_PCM_RATE_CONTINUOUS, | |
382 | .rate_max = 48000, | |
383 | .rate_min = 4000, | |
384 | .channels_min = 2, | |
385 | .channels_max = 6, | |
386 | .buffer_bytes_max = 64 * 1024, | |
387 | .period_bytes_min = 256, | |
388 | .period_bytes_max = PAGE_SIZE, | |
389 | .periods_min = 4, | |
390 | .periods_max = PAGE_SIZE / 16, | |
391 | }; | |
392 | ||
41762b8c KH |
393 | static int __aaci_pcm_open(struct aaci *aaci, |
394 | struct snd_pcm_substream *substream, | |
395 | struct aaci_runtime *aacirun) | |
cb5a6ffc | 396 | { |
ceb9e476 | 397 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
398 | int ret; |
399 | ||
400 | aacirun->substream = substream; | |
401 | runtime->private_data = aacirun; | |
402 | runtime->hw = aaci_hw_info; | |
403 | ||
404 | /* | |
405 | * FIXME: ALSA specifies fifo_size in bytes. If we're in normal | |
406 | * mode, each 32-bit word contains one sample. If we're in | |
407 | * compact mode, each 32-bit word contains two samples, effectively | |
408 | * halving the FIFO size. However, we don't know for sure which | |
409 | * we'll be using at this point. We set this to the lower limit. | |
410 | */ | |
411 | runtime->hw.fifo_size = aaci->fifosize * 2; | |
412 | ||
413 | /* | |
414 | * Add rule describing hardware rate dependency | |
415 | * on the number of channels. | |
416 | */ | |
417 | ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
418 | aaci_rule_rate_by_channels, aaci, | |
419 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
420 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
421 | if (ret) | |
422 | goto out; | |
423 | ||
65ca68b3 | 424 | ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED, |
cb5a6ffc RK |
425 | DRIVER_NAME, aaci); |
426 | if (ret) | |
427 | goto out; | |
428 | ||
429 | return 0; | |
430 | ||
431 | out: | |
432 | return ret; | |
433 | } | |
434 | ||
435 | ||
436 | /* | |
437 | * Common ALSA stuff | |
438 | */ | |
ceb9e476 | 439 | static int aaci_pcm_close(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
440 | { |
441 | struct aaci *aaci = substream->private_data; | |
442 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
443 | ||
41762b8c | 444 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
445 | |
446 | aacirun->substream = NULL; | |
447 | free_irq(aaci->dev->irq[0], aaci); | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
ceb9e476 | 452 | static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
453 | { |
454 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
455 | ||
456 | /* | |
457 | * This must not be called with the device enabled. | |
458 | */ | |
41762b8c | 459 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
460 | |
461 | if (aacirun->pcm_open) | |
462 | snd_ac97_pcm_close(aacirun->pcm); | |
463 | aacirun->pcm_open = 0; | |
464 | ||
465 | /* | |
466 | * Clear out the DMA and any allocated buffers. | |
467 | */ | |
468 | devdma_hw_free(NULL, substream); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
ceb9e476 | 473 | static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, |
cb5a6ffc | 474 | struct aaci_runtime *aacirun, |
ceb9e476 | 475 | struct snd_pcm_hw_params *params) |
cb5a6ffc RK |
476 | { |
477 | int err; | |
478 | ||
479 | aaci_pcm_hw_free(substream); | |
480 | ||
481 | err = devdma_hw_alloc(NULL, substream, | |
482 | params_buffer_bytes(params)); | |
483 | if (err < 0) | |
484 | goto out; | |
485 | ||
41762b8c KH |
486 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
487 | err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params), | |
488 | params_channels(params), | |
489 | aacirun->pcm->r[0].slots); | |
490 | else | |
491 | err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params), | |
492 | params_channels(params), | |
493 | aacirun->pcm->r[1].slots); | |
494 | ||
cb5a6ffc RK |
495 | if (err) |
496 | goto out; | |
497 | ||
498 | aacirun->pcm_open = 1; | |
499 | ||
500 | out: | |
501 | return err; | |
502 | } | |
503 | ||
ceb9e476 | 504 | static int aaci_pcm_prepare(struct snd_pcm_substream *substream) |
cb5a6ffc | 505 | { |
ceb9e476 | 506 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
507 | struct aaci_runtime *aacirun = runtime->private_data; |
508 | ||
509 | aacirun->start = (void *)runtime->dma_area; | |
510 | aacirun->end = aacirun->start + runtime->dma_bytes; | |
511 | aacirun->ptr = aacirun->start; | |
512 | aacirun->period = | |
513 | aacirun->bytes = frames_to_bytes(runtime, runtime->period_size); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
ceb9e476 | 518 | static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) |
cb5a6ffc | 519 | { |
ceb9e476 | 520 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
521 | struct aaci_runtime *aacirun = runtime->private_data; |
522 | ssize_t bytes = aacirun->ptr - aacirun->start; | |
523 | ||
524 | return bytes_to_frames(runtime, bytes); | |
525 | } | |
526 | ||
ceb9e476 | 527 | static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma) |
cb5a6ffc RK |
528 | { |
529 | return devdma_mmap(NULL, substream, vma); | |
530 | } | |
531 | ||
532 | ||
533 | /* | |
534 | * Playback specific ALSA stuff | |
535 | */ | |
536 | static const u32 channels_to_txmask[] = { | |
41762b8c KH |
537 | [2] = CR_SL3 | CR_SL4, |
538 | [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, | |
539 | [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, | |
cb5a6ffc RK |
540 | }; |
541 | ||
542 | /* | |
543 | * We can support two and four channel audio. Unfortunately | |
544 | * six channel audio requires a non-standard channel ordering: | |
545 | * 2 -> FL(3), FR(4) | |
546 | * 4 -> FL(3), FR(4), SL(7), SR(8) | |
547 | * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) | |
548 | * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) | |
549 | * This requires an ALSA configuration file to correct. | |
550 | */ | |
551 | static unsigned int channel_list[] = { 2, 4, 6 }; | |
552 | ||
553 | static int | |
ceb9e476 | 554 | aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) |
cb5a6ffc RK |
555 | { |
556 | struct aaci *aaci = rule->private; | |
557 | unsigned int chan_mask = 1 << 0, slots; | |
558 | ||
559 | /* | |
560 | * pcms[0] is the our 5.1 PCM instance. | |
561 | */ | |
562 | slots = aaci->ac97_bus->pcms[0].r[0].slots; | |
563 | if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
564 | chan_mask |= 1 << 1; | |
565 | if (slots & (1 << AC97_SLOT_LFE)) | |
566 | chan_mask |= 1 << 2; | |
567 | } | |
568 | ||
569 | return snd_interval_list(hw_param_interval(p, rule->var), | |
570 | ARRAY_SIZE(channel_list), channel_list, | |
571 | chan_mask); | |
572 | } | |
573 | ||
41762b8c | 574 | static int aaci_pcm_open(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
575 | { |
576 | struct aaci *aaci = substream->private_data; | |
577 | int ret; | |
578 | ||
579 | /* | |
580 | * Add rule describing channel dependency. | |
581 | */ | |
582 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
583 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
584 | aaci_rule_channels, aaci, | |
585 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
586 | if (ret) | |
587 | return ret; | |
588 | ||
41762b8c KH |
589 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
590 | ret = __aaci_pcm_open(aaci, substream, &aaci->playback); | |
591 | } else { | |
592 | ret = __aaci_pcm_open(aaci, substream, &aaci->capture); | |
593 | } | |
594 | return ret; | |
cb5a6ffc RK |
595 | } |
596 | ||
ceb9e476 TI |
597 | static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream, |
598 | struct snd_pcm_hw_params *params) | |
cb5a6ffc RK |
599 | { |
600 | struct aaci *aaci = substream->private_data; | |
601 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
602 | unsigned int channels = params_channels(params); | |
603 | int ret; | |
604 | ||
605 | WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) || | |
606 | !channels_to_txmask[channels]); | |
607 | ||
608 | ret = aaci_pcm_hw_params(substream, aacirun, params); | |
609 | ||
610 | /* | |
611 | * Enable FIFO, compact mode, 16 bits per sample. | |
612 | * FIXME: double rate slots? | |
613 | */ | |
614 | if (ret >= 0) { | |
41762b8c | 615 | aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; |
cb5a6ffc RK |
616 | aacirun->cr |= channels_to_txmask[channels]; |
617 | ||
618 | aacirun->fifosz = aaci->fifosize * 4; | |
41762b8c | 619 | if (aacirun->cr & CR_COMPACT) |
cb5a6ffc RK |
620 | aacirun->fifosz >>= 1; |
621 | } | |
622 | return ret; | |
623 | } | |
624 | ||
625 | static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) | |
626 | { | |
627 | u32 ie; | |
628 | ||
629 | ie = readl(aacirun->base + AACI_IE); | |
630 | ie &= ~(IE_URIE|IE_TXIE); | |
631 | writel(ie, aacirun->base + AACI_IE); | |
41762b8c | 632 | aacirun->cr &= ~CR_EN; |
cb5a6ffc RK |
633 | aaci_chan_wait_ready(aacirun); |
634 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
635 | } | |
636 | ||
637 | static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) | |
638 | { | |
639 | u32 ie; | |
640 | ||
641 | aaci_chan_wait_ready(aacirun); | |
41762b8c | 642 | aacirun->cr |= CR_EN; |
cb5a6ffc RK |
643 | |
644 | ie = readl(aacirun->base + AACI_IE); | |
645 | ie |= IE_URIE | IE_TXIE; | |
646 | writel(ie, aacirun->base + AACI_IE); | |
647 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
648 | } | |
649 | ||
ceb9e476 | 650 | static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
cb5a6ffc RK |
651 | { |
652 | struct aaci *aaci = substream->private_data; | |
653 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
654 | unsigned long flags; | |
655 | int ret = 0; | |
656 | ||
657 | spin_lock_irqsave(&aaci->lock, flags); | |
658 | switch (cmd) { | |
659 | case SNDRV_PCM_TRIGGER_START: | |
660 | aaci_pcm_playback_start(aacirun); | |
661 | break; | |
662 | ||
663 | case SNDRV_PCM_TRIGGER_RESUME: | |
664 | aaci_pcm_playback_start(aacirun); | |
665 | break; | |
666 | ||
667 | case SNDRV_PCM_TRIGGER_STOP: | |
668 | aaci_pcm_playback_stop(aacirun); | |
669 | break; | |
670 | ||
671 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
672 | aaci_pcm_playback_stop(aacirun); | |
673 | break; | |
674 | ||
675 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
676 | break; | |
677 | ||
678 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
679 | break; | |
680 | ||
681 | default: | |
682 | ret = -EINVAL; | |
683 | } | |
684 | spin_unlock_irqrestore(&aaci->lock, flags); | |
685 | ||
686 | return ret; | |
687 | } | |
688 | ||
ceb9e476 | 689 | static struct snd_pcm_ops aaci_playback_ops = { |
41762b8c | 690 | .open = aaci_pcm_open, |
cb5a6ffc RK |
691 | .close = aaci_pcm_close, |
692 | .ioctl = snd_pcm_lib_ioctl, | |
693 | .hw_params = aaci_pcm_playback_hw_params, | |
694 | .hw_free = aaci_pcm_hw_free, | |
695 | .prepare = aaci_pcm_prepare, | |
696 | .trigger = aaci_pcm_playback_trigger, | |
697 | .pointer = aaci_pcm_pointer, | |
698 | .mmap = aaci_pcm_mmap, | |
699 | }; | |
700 | ||
41762b8c KH |
701 | static int aaci_pcm_capture_hw_params(snd_pcm_substream_t *substream, |
702 | snd_pcm_hw_params_t *params) | |
703 | { | |
704 | struct aaci *aaci = substream->private_data; | |
705 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
706 | int ret; | |
707 | ||
708 | ret = aaci_pcm_hw_params(substream, aacirun, params); | |
709 | ||
710 | if (ret >= 0) { | |
711 | aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; | |
712 | ||
713 | /* Line in record: slot 3 and 4 */ | |
714 | aacirun->cr |= CR_SL3 | CR_SL4; | |
715 | ||
716 | aacirun->fifosz = aaci->fifosize * 4; | |
717 | ||
718 | if (aacirun->cr & CR_COMPACT) | |
719 | aacirun->fifosz >>= 1; | |
720 | } | |
721 | return ret; | |
722 | } | |
723 | ||
724 | static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) | |
725 | { | |
726 | u32 ie; | |
727 | ||
728 | aaci_chan_wait_ready(aacirun); | |
729 | ||
730 | ie = readl(aacirun->base + AACI_IE); | |
731 | ie &= ~(IE_ORIE | IE_RXIE); | |
732 | writel(ie, aacirun->base+AACI_IE); | |
733 | ||
734 | aacirun->cr &= ~CR_EN; | |
cb5a6ffc | 735 | |
41762b8c KH |
736 | writel(aacirun->cr, aacirun->base + AACI_RXCR); |
737 | } | |
738 | ||
739 | static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) | |
740 | { | |
741 | u32 ie; | |
742 | ||
743 | aaci_chan_wait_ready(aacirun); | |
744 | ||
745 | #ifdef DEBUG | |
746 | /* RX Timeout value: bits 28:17 in RXCR */ | |
747 | aacirun->cr |= 0xf << 17; | |
748 | #endif | |
749 | ||
750 | aacirun->cr |= CR_EN; | |
751 | writel(aacirun->cr, aacirun->base + AACI_RXCR); | |
752 | ||
753 | ie = readl(aacirun->base + AACI_IE); | |
754 | ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full | |
755 | writel(ie, aacirun->base + AACI_IE); | |
756 | } | |
757 | ||
758 | static int aaci_pcm_capture_trigger(snd_pcm_substream_t *substream, int cmd){ | |
759 | ||
760 | struct aaci *aaci = substream->private_data; | |
761 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
762 | unsigned long flags; | |
763 | int ret = 0; | |
764 | ||
765 | spin_lock_irqsave(&aaci->lock, flags); | |
766 | ||
767 | switch (cmd) { | |
768 | case SNDRV_PCM_TRIGGER_START: | |
769 | aaci_pcm_capture_start(aacirun); | |
770 | break; | |
771 | ||
772 | case SNDRV_PCM_TRIGGER_RESUME: | |
773 | aaci_pcm_capture_start(aacirun); | |
774 | break; | |
775 | ||
776 | case SNDRV_PCM_TRIGGER_STOP: | |
777 | aaci_pcm_capture_stop(aacirun); | |
778 | break; | |
779 | ||
780 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
781 | aaci_pcm_capture_stop(aacirun); | |
782 | break; | |
783 | ||
784 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
785 | break; | |
786 | ||
787 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
788 | break; | |
789 | ||
790 | default: | |
791 | ret = -EINVAL; | |
792 | } | |
793 | ||
794 | spin_unlock_irqrestore(&aaci->lock, flags); | |
795 | ||
796 | return ret; | |
797 | } | |
798 | ||
799 | static int aaci_pcm_capture_prepare(snd_pcm_substream_t *substream) | |
800 | { | |
801 | struct snd_pcm_runtime *runtime = substream->runtime; | |
802 | struct aaci *aaci = substream->private_data; | |
803 | ||
804 | aaci_pcm_prepare(substream); | |
805 | ||
806 | /* allow changing of sample rate */ | |
807 | aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ | |
808 | aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); | |
809 | aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); | |
810 | ||
811 | /* Record select: Mic: 0, Aux: 3, Line: 4 */ | |
812 | aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | static snd_pcm_ops_t aaci_capture_ops = { | |
818 | .open = aaci_pcm_open, | |
819 | .close = aaci_pcm_close, | |
820 | .ioctl = snd_pcm_lib_ioctl, | |
821 | .hw_params = aaci_pcm_capture_hw_params, | |
822 | .hw_free = aaci_pcm_hw_free, | |
823 | .prepare = aaci_pcm_capture_prepare, | |
824 | .trigger = aaci_pcm_capture_trigger, | |
825 | .pointer = aaci_pcm_pointer, | |
826 | .mmap = aaci_pcm_mmap, | |
827 | }; | |
cb5a6ffc RK |
828 | |
829 | /* | |
830 | * Power Management. | |
831 | */ | |
832 | #ifdef CONFIG_PM | |
ceb9e476 | 833 | static int aaci_do_suspend(struct snd_card *card, unsigned int state) |
cb5a6ffc RK |
834 | { |
835 | struct aaci *aaci = card->private_data; | |
792a6c51 TI |
836 | snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); |
837 | snd_pcm_suspend_all(aaci->pcm); | |
cb5a6ffc RK |
838 | return 0; |
839 | } | |
840 | ||
ceb9e476 | 841 | static int aaci_do_resume(struct snd_card *card, unsigned int state) |
cb5a6ffc | 842 | { |
792a6c51 | 843 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
cb5a6ffc RK |
844 | return 0; |
845 | } | |
846 | ||
e36d394d | 847 | static int aaci_suspend(struct amba_device *dev, pm_message_t state) |
cb5a6ffc | 848 | { |
ceb9e476 | 849 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
850 | return card ? aaci_do_suspend(card) : 0; |
851 | } | |
852 | ||
853 | static int aaci_resume(struct amba_device *dev) | |
854 | { | |
ceb9e476 | 855 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
856 | return card ? aaci_do_resume(card) : 0; |
857 | } | |
858 | #else | |
859 | #define aaci_do_suspend NULL | |
860 | #define aaci_do_resume NULL | |
861 | #define aaci_suspend NULL | |
862 | #define aaci_resume NULL | |
863 | #endif | |
864 | ||
865 | ||
866 | static struct ac97_pcm ac97_defs[] __devinitdata = { | |
41762b8c | 867 | [0] = { /* Front PCM */ |
cb5a6ffc RK |
868 | .exclusive = 1, |
869 | .r = { | |
870 | [0] = { | |
871 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
872 | (1 << AC97_SLOT_PCM_RIGHT) | | |
873 | (1 << AC97_SLOT_PCM_CENTER) | | |
874 | (1 << AC97_SLOT_PCM_SLEFT) | | |
875 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
876 | (1 << AC97_SLOT_LFE), | |
877 | }, | |
878 | }, | |
879 | }, | |
880 | [1] = { /* PCM in */ | |
881 | .stream = 1, | |
882 | .exclusive = 1, | |
883 | .r = { | |
884 | [0] = { | |
885 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
886 | (1 << AC97_SLOT_PCM_RIGHT), | |
887 | }, | |
888 | }, | |
889 | }, | |
890 | [2] = { /* Mic in */ | |
891 | .stream = 1, | |
892 | .exclusive = 1, | |
893 | .r = { | |
894 | [0] = { | |
895 | .slots = (1 << AC97_SLOT_MIC), | |
896 | }, | |
897 | }, | |
898 | } | |
899 | }; | |
900 | ||
ceb9e476 | 901 | static struct snd_ac97_bus_ops aaci_bus_ops = { |
cb5a6ffc RK |
902 | .write = aaci_ac97_write, |
903 | .read = aaci_ac97_read, | |
904 | }; | |
905 | ||
906 | static int __devinit aaci_probe_ac97(struct aaci *aaci) | |
907 | { | |
ceb9e476 TI |
908 | struct snd_ac97_template ac97_template; |
909 | struct snd_ac97_bus *ac97_bus; | |
910 | struct snd_ac97 *ac97; | |
cb5a6ffc RK |
911 | int ret; |
912 | ||
913 | /* | |
914 | * Assert AACIRESET for 2us | |
915 | */ | |
916 | writel(0, aaci->base + AACI_RESET); | |
917 | udelay(2); | |
918 | writel(RESET_NRST, aaci->base + AACI_RESET); | |
919 | ||
920 | /* | |
921 | * Give the AC'97 codec more than enough time | |
922 | * to wake up. (42us = ~2 frames at 48kHz.) | |
923 | */ | |
924 | udelay(42); | |
925 | ||
926 | ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); | |
927 | if (ret) | |
928 | goto out; | |
929 | ||
930 | ac97_bus->clock = 48000; | |
931 | aaci->ac97_bus = ac97_bus; | |
932 | ||
ceb9e476 | 933 | memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); |
cb5a6ffc RK |
934 | ac97_template.private_data = aaci; |
935 | ac97_template.num = 0; | |
936 | ac97_template.scaps = AC97_SCAP_SKIP_MODEM; | |
937 | ||
938 | ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); | |
939 | if (ret) | |
940 | goto out; | |
41762b8c | 941 | aaci->ac97 = ac97; |
cb5a6ffc RK |
942 | |
943 | /* | |
944 | * Disable AC97 PC Beep input on audio codecs. | |
945 | */ | |
946 | if (ac97_is_audio(ac97)) | |
947 | snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); | |
948 | ||
949 | ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); | |
950 | if (ret) | |
951 | goto out; | |
952 | ||
953 | aaci->playback.pcm = &ac97_bus->pcms[0]; | |
41762b8c | 954 | aaci->capture.pcm = &ac97_bus->pcms[1]; |
cb5a6ffc RK |
955 | |
956 | out: | |
957 | return ret; | |
958 | } | |
959 | ||
ceb9e476 | 960 | static void aaci_free_card(struct snd_card *card) |
cb5a6ffc RK |
961 | { |
962 | struct aaci *aaci = card->private_data; | |
963 | if (aaci->base) | |
964 | iounmap(aaci->base); | |
965 | } | |
966 | ||
967 | static struct aaci * __devinit aaci_init_card(struct amba_device *dev) | |
968 | { | |
969 | struct aaci *aaci; | |
ceb9e476 | 970 | struct snd_card *card; |
cb5a6ffc RK |
971 | |
972 | card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, | |
973 | THIS_MODULE, sizeof(struct aaci)); | |
974 | if (card == NULL) | |
975 | return ERR_PTR(-ENOMEM); | |
976 | ||
977 | card->private_free = aaci_free_card; | |
cb5a6ffc RK |
978 | |
979 | strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); | |
980 | strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); | |
981 | snprintf(card->longname, sizeof(card->longname), | |
aa0a2ddc GKH |
982 | "%s at 0x%016llx, irq %d", |
983 | card->shortname, (unsigned long long)dev->res.start, | |
984 | dev->irq[0]); | |
cb5a6ffc RK |
985 | |
986 | aaci = card->private_data; | |
12aa7579 | 987 | mutex_init(&aaci->ac97_sem); |
cb5a6ffc RK |
988 | spin_lock_init(&aaci->lock); |
989 | aaci->card = card; | |
990 | aaci->dev = dev; | |
991 | ||
992 | /* Set MAINCR to allow slot 1 and 2 data IO */ | |
993 | aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | | |
994 | MAINCR_SL2RXEN | MAINCR_SL2TXEN; | |
995 | ||
996 | return aaci; | |
997 | } | |
998 | ||
999 | static int __devinit aaci_init_pcm(struct aaci *aaci) | |
1000 | { | |
ceb9e476 | 1001 | struct snd_pcm *pcm; |
cb5a6ffc RK |
1002 | int ret; |
1003 | ||
41762b8c | 1004 | ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); |
cb5a6ffc RK |
1005 | if (ret == 0) { |
1006 | aaci->pcm = pcm; | |
1007 | pcm->private_data = aaci; | |
1008 | pcm->info_flags = 0; | |
1009 | ||
1010 | strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); | |
1011 | ||
1012 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); | |
41762b8c | 1013 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); |
cb5a6ffc RK |
1014 | } |
1015 | ||
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) | |
1020 | { | |
41762b8c | 1021 | struct aaci_runtime *aacirun = &aaci->playback; |
cb5a6ffc RK |
1022 | int i; |
1023 | ||
41762b8c | 1024 | writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); |
cb5a6ffc | 1025 | |
41762b8c KH |
1026 | for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) |
1027 | writel(0, aacirun->fifo); | |
cb5a6ffc | 1028 | |
41762b8c | 1029 | writel(0, aacirun->base + AACI_TXCR); |
cb5a6ffc RK |
1030 | |
1031 | /* | |
1032 | * Re-initialise the AACI after the FIFO depth test, to | |
1033 | * ensure that the FIFOs are empty. Unfortunately, merely | |
1034 | * disabling the channel doesn't clear the FIFO. | |
1035 | */ | |
1036 | writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); | |
1037 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
1038 | ||
1039 | /* | |
1040 | * If we hit 4096, we failed. Go back to the specified | |
1041 | * fifo depth. | |
1042 | */ | |
1043 | if (i == 4096) | |
1044 | i = 8; | |
1045 | ||
1046 | return i; | |
1047 | } | |
1048 | ||
1049 | static int __devinit aaci_probe(struct amba_device *dev, void *id) | |
1050 | { | |
1051 | struct aaci *aaci; | |
1052 | int ret, i; | |
1053 | ||
1054 | ret = amba_request_regions(dev, NULL); | |
1055 | if (ret) | |
1056 | return ret; | |
1057 | ||
1058 | aaci = aaci_init_card(dev); | |
1059 | if (IS_ERR(aaci)) { | |
1060 | ret = PTR_ERR(aaci); | |
1061 | goto out; | |
1062 | } | |
1063 | ||
1064 | aaci->base = ioremap(dev->res.start, SZ_4K); | |
1065 | if (!aaci->base) { | |
1066 | ret = -ENOMEM; | |
1067 | goto out; | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Playback uses AACI channel 0 | |
1072 | */ | |
1073 | aaci->playback.base = aaci->base + AACI_CSCH1; | |
1074 | aaci->playback.fifo = aaci->base + AACI_DR1; | |
1075 | ||
41762b8c KH |
1076 | /* |
1077 | * Capture uses AACI channel 0 | |
1078 | */ | |
1079 | aaci->capture.base = aaci->base + AACI_CSCH1; | |
1080 | aaci->capture.fifo = aaci->base + AACI_DR1; | |
1081 | ||
cb5a6ffc | 1082 | for (i = 0; i < 4; i++) { |
e12ba644 | 1083 | void __iomem *base = aaci->base + i * 0x14; |
cb5a6ffc RK |
1084 | |
1085 | writel(0, base + AACI_IE); | |
1086 | writel(0, base + AACI_TXCR); | |
1087 | writel(0, base + AACI_RXCR); | |
1088 | } | |
1089 | ||
1090 | writel(0x1fff, aaci->base + AACI_INTCLR); | |
1091 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
1092 | ||
f27f218c CM |
1093 | ret = aaci_probe_ac97(aaci); |
1094 | if (ret) | |
1095 | goto out; | |
1096 | ||
cb5a6ffc | 1097 | /* |
f27f218c | 1098 | * Size the FIFOs (must be multiple of 16). |
cb5a6ffc RK |
1099 | */ |
1100 | aaci->fifosize = aaci_size_fifo(aaci); | |
f27f218c CM |
1101 | if (aaci->fifosize & 15) { |
1102 | printk(KERN_WARNING "AACI: fifosize = %d not supported\n", | |
1103 | aaci->fifosize); | |
1104 | ret = -ENODEV; | |
cb5a6ffc | 1105 | goto out; |
f27f218c | 1106 | } |
cb5a6ffc RK |
1107 | |
1108 | ret = aaci_init_pcm(aaci); | |
1109 | if (ret) | |
1110 | goto out; | |
1111 | ||
a76af199 TI |
1112 | snd_card_set_dev(aaci->card, &dev->dev); |
1113 | ||
cb5a6ffc RK |
1114 | ret = snd_card_register(aaci->card); |
1115 | if (ret == 0) { | |
1116 | dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname, | |
41762b8c | 1117 | aaci->fifosize); |
cb5a6ffc RK |
1118 | amba_set_drvdata(dev, aaci->card); |
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | out: | |
1123 | if (aaci) | |
1124 | snd_card_free(aaci->card); | |
1125 | amba_release_regions(dev); | |
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | static int __devexit aaci_remove(struct amba_device *dev) | |
1130 | { | |
ceb9e476 | 1131 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
1132 | |
1133 | amba_set_drvdata(dev, NULL); | |
1134 | ||
1135 | if (card) { | |
1136 | struct aaci *aaci = card->private_data; | |
1137 | writel(0, aaci->base + AACI_MAINCR); | |
1138 | ||
1139 | snd_card_free(card); | |
1140 | amba_release_regions(dev); | |
1141 | } | |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static struct amba_id aaci_ids[] = { | |
1147 | { | |
1148 | .id = 0x00041041, | |
1149 | .mask = 0x000fffff, | |
1150 | }, | |
1151 | { 0, 0 }, | |
1152 | }; | |
1153 | ||
1154 | static struct amba_driver aaci_driver = { | |
1155 | .drv = { | |
1156 | .name = DRIVER_NAME, | |
1157 | }, | |
1158 | .probe = aaci_probe, | |
1159 | .remove = __devexit_p(aaci_remove), | |
1160 | .suspend = aaci_suspend, | |
1161 | .resume = aaci_resume, | |
1162 | .id_table = aaci_ids, | |
1163 | }; | |
1164 | ||
1165 | static int __init aaci_init(void) | |
1166 | { | |
1167 | return amba_driver_register(&aaci_driver); | |
1168 | } | |
1169 | ||
1170 | static void __exit aaci_exit(void) | |
1171 | { | |
1172 | amba_driver_unregister(&aaci_driver); | |
1173 | } | |
1174 | ||
1175 | module_init(aaci_init); | |
1176 | module_exit(aaci_exit); | |
1177 | ||
1178 | MODULE_LICENSE("GPL"); | |
1179 | MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); |