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[ARM] 4138/1: AACI: multiple channel support for IRQ handling
[deliverable/linux.git] / sound / arm / aaci.c
CommitLineData
cb5a6ffc
RK		 1/*
2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Documentation: ARM DDI 0173B
11 */
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/device.h>
17#include <linux/spinlock.h>
18#include <linux/interrupt.h>
19#include <linux/err.h>
a62c80e5 20#include <linux/amba/bus.h>
cb5a6ffc
RK		 21
22#include <asm/io.h>
23#include <asm/irq.h>
c6b8fdad 24#include <asm/sizes.h>
cb5a6ffc
RK		 25
26#include <sound/driver.h>
27#include <sound/core.h>
28#include <sound/initval.h>
29#include <sound/ac97_codec.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32
33#include "aaci.h"
34#include "devdma.h"
35
36#define DRIVER_NAME "aaci-pl041"
37
38/*
39 * PM support is not complete. Turn it off.
40 */
41#undef CONFIG_PM
42
ceb9e476 43static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
cb5a6ffc
RK		 44{
45 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
46
47 /*
48 * Ensure that the slot 1/2 RX registers are empty.
49 */
50 v = readl(aaci->base + AACI_SLFR);
51 if (v & SLFR_2RXV)
52 readl(aaci->base + AACI_SL2RX);
53 if (v & SLFR_1RXV)
54 readl(aaci->base + AACI_SL1RX);
55
56 writel(maincr, aaci->base + AACI_MAINCR);
57}
58
59/*
60 * P29:
61 * The recommended use of programming the external codec through slot 1
62 * and slot 2 data is to use the channels during setup routines and the
63 * slot register at any other time. The data written into slot 1, slot 2
64 * and slot 12 registers is transmitted only when their corresponding
65 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
66 * register.
67 */
ceb9e476 68static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
cb5a6ffc
RK		 69{
70 struct aaci *aaci = ac97->private_data;
71 u32 v;
72
73 if (ac97->num >= 4)
74 return;
75
12aa7579 76 mutex_lock(&aaci->ac97_sem);
cb5a6ffc
RK		 77
78 aaci_ac97_select_codec(aaci, ac97);
79
80 /*
81 * P54: You must ensure that AACI_SL2TX is always written
82 * to, if required, before data is written to AACI_SL1TX.
83 */
84 writel(val << 4, aaci->base + AACI_SL2TX);
85 writel(reg << 12, aaci->base + AACI_SL1TX);
86
87 /*
88 * Wait for the transmission of both slots to complete.
89 */
90 do {
91 v = readl(aaci->base + AACI_SLFR);
92 } while (v & (SLFR_1TXB|SLFR_2TXB));
93
12aa7579 94 mutex_unlock(&aaci->ac97_sem);
cb5a6ffc
RK		 95}
96
97/*
98 * Read an AC'97 register.
99 */
ceb9e476 100static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
cb5a6ffc
RK		 101{
102 struct aaci *aaci = ac97->private_data;
103 u32 v;
104
105 if (ac97->num >= 4)
106 return ~0;
107
12aa7579 108 mutex_lock(&aaci->ac97_sem);
cb5a6ffc
RK		 109
110 aaci_ac97_select_codec(aaci, ac97);
111
112 /*
113 * Write the register address to slot 1.
114 */
115 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
116
117 /*
118 * Wait for the transmission to complete.
119 */
120 do {
121 v = readl(aaci->base + AACI_SLFR);
122 } while (v & SLFR_1TXB);
123
124 /*
125 * Give the AC'97 codec more than enough time
126 * to respond. (42us = ~2 frames at 48kHz.)
127 */
128 udelay(42);
129
130 /*
131 * Wait for slot 2 to indicate data.
132 */
133 do {
134 cond_resched();
135 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
136 } while (v != (SLFR_1RXV|SLFR_2RXV));
137
138 v = readl(aaci->base + AACI_SL1RX) >> 12;
139 if (v == reg) {
140 v = readl(aaci->base + AACI_SL2RX) >> 4;
141 } else {
142 dev_err(&aaci->dev->dev,
143 "wrong ac97 register read back (%x != %x)\n",
144 v, reg);
145 v = ~0;
146 }
147
12aa7579 148 mutex_unlock(&aaci->ac97_sem);
cb5a6ffc
RK		 149 return v;
150}
151
152static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
153{
154 u32 val;
155 int timeout = 5000;
156
157 do {
158 val = readl(aacirun->base + AACI_SR);
159 } while (val & (SR_TXB|SR_RXB) && timeout--);
160}
161
162
163
164/*
165 * Interrupt support.
166 */
62578cbf 167static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
cb5a6ffc
RK		 168{
169 if (mask & ISR_URINTR) {
62578cbf
KH		 170 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
171 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
cb5a6ffc
RK		 172 }
173
174 if (mask & ISR_TXINTR) {
175 struct aaci_runtime *aacirun = &aaci->playback;
176 void *ptr;
177
178 if (!aacirun->substream || !aacirun->start) {
179 dev_warn(&aaci->dev->dev, "TX interrupt???");
180 writel(0, aacirun->base + AACI_IE);
181 return;
182 }
183
184 ptr = aacirun->ptr;
185 do {
186 unsigned int len = aacirun->fifosz;
187 u32 val;
188
189 if (aacirun->bytes <= 0) {
190 aacirun->bytes += aacirun->period;
191 aacirun->ptr = ptr;
192 spin_unlock(&aaci->lock);
193 snd_pcm_period_elapsed(aacirun->substream);
194 spin_lock(&aaci->lock);
195 }
196 if (!(aacirun->cr & TXCR_TXEN))
197 break;
198
199 val = readl(aacirun->base + AACI_SR);
200 if (!(val & SR_TXHE))
201 break;
202 if (!(val & SR_TXFE))
203 len >>= 1;
204
205 aacirun->bytes -= len;
206
207 /* writing 16 bytes at a time */
208 for ( ; len > 0; len -= 16) {
209 asm(
210 "ldmia %0!, {r0, r1, r2, r3}\n\t"
211 "stmia %1, {r0, r1, r2, r3}"
212 : "+r" (ptr)
213 : "r" (aacirun->fifo)
214 : "r0", "r1", "r2", "r3", "cc");
215
216 if (ptr >= aacirun->end)
217 ptr = aacirun->start;
218 }
219 } while (1);
220
221 aacirun->ptr = ptr;
222 }
223}
224
7d12e780 225static irqreturn_t aaci_irq(int irq, void *devid)
cb5a6ffc
RK		 226{
227 struct aaci *aaci = devid;
228 u32 mask;
229 int i;
230
231 spin_lock(&aaci->lock);
232 mask = readl(aaci->base + AACI_ALLINTS);
233 if (mask) {
234 u32 m = mask;
235 for (i = 0; i < 4; i++, m >>= 7) {
236 if (m & 0x7f) {
62578cbf 237 aaci_fifo_irq(aaci, i, m);
cb5a6ffc
RK		 238 }
239 }
240 }
241 spin_unlock(&aaci->lock);
242
243 return mask ? IRQ_HANDLED : IRQ_NONE;
244}
245
246
247
248/*
249 * ALSA support.
250 */
251
252struct aaci_stream {
253 unsigned char codec_idx;
254 unsigned char rate_idx;
255};
256
257static struct aaci_stream aaci_streams[] = {
258 [ACSTREAM_FRONT] = {
259 .codec_idx = 0,
260 .rate_idx = AC97_RATES_FRONT_DAC,
261 },
262 [ACSTREAM_SURROUND] = {
263 .codec_idx = 0,
264 .rate_idx = AC97_RATES_SURR_DAC,
265 },
266 [ACSTREAM_LFE] = {
267 .codec_idx = 0,
268 .rate_idx = AC97_RATES_LFE_DAC,
269 },
270};
271
272static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
273{
274 struct aaci_stream *s = aaci_streams + streamid;
275 return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
276}
277
278static unsigned int rate_list[] = {
279 5512, 8000, 11025, 16000, 22050, 32000, 44100,
280 48000, 64000, 88200, 96000, 176400, 192000
281};
282
283/*
284 * Double-rate rule: we can support double rate iff channels == 2
285 * (unimplemented)
286 */
287static int
ceb9e476 288aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
cb5a6ffc
RK		 289{
290 struct aaci *aaci = rule->private;
291 unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
ceb9e476 292 struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
cb5a6ffc
RK		 293
294 switch (c->max) {
295 case 6:
296 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
297 case 4:
298 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
299 case 2:
300 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
301 }
302
303 return snd_interval_list(hw_param_interval(p, rule->var),
304 ARRAY_SIZE(rate_list), rate_list,
305 rate_mask);
306}
307
ceb9e476 308static struct snd_pcm_hardware aaci_hw_info = {
cb5a6ffc
RK		 309 .info = SNDRV_PCM_INFO_MMAP |
310 SNDRV_PCM_INFO_MMAP_VALID |
311 SNDRV_PCM_INFO_INTERLEAVED |
312 SNDRV_PCM_INFO_BLOCK_TRANSFER |
313 SNDRV_PCM_INFO_RESUME,
314
315 /*
316 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
317 * words. It also doesn't support 12-bit at all.
318 */
319 .formats = SNDRV_PCM_FMTBIT_S16_LE,
320
321 /* should this be continuous or knot? */
322 .rates = SNDRV_PCM_RATE_CONTINUOUS,
323 .rate_max = 48000,
324 .rate_min = 4000,
325 .channels_min = 2,
326 .channels_max = 6,
327 .buffer_bytes_max = 64 * 1024,
328 .period_bytes_min = 256,
329 .period_bytes_max = PAGE_SIZE,
330 .periods_min = 4,
331 .periods_max = PAGE_SIZE / 16,
332};
333
ceb9e476 334static int aaci_pcm_open(struct aaci *aaci, struct snd_pcm_substream *substream,
cb5a6ffc
RK		 335 struct aaci_runtime *aacirun)
336{
ceb9e476 337 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 338 int ret;
339
340 aacirun->substream = substream;
341 runtime->private_data = aacirun;
342 runtime->hw = aaci_hw_info;
343
344 /*
345 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
346 * mode, each 32-bit word contains one sample. If we're in
347 * compact mode, each 32-bit word contains two samples, effectively
348 * halving the FIFO size. However, we don't know for sure which
349 * we'll be using at this point. We set this to the lower limit.
350 */
351 runtime->hw.fifo_size = aaci->fifosize * 2;
352
353 /*
354 * Add rule describing hardware rate dependency
355 * on the number of channels.
356 */
357 ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
358 aaci_rule_rate_by_channels, aaci,
359 SNDRV_PCM_HW_PARAM_CHANNELS,
360 SNDRV_PCM_HW_PARAM_RATE, -1);
361 if (ret)
362 goto out;
363
65ca68b3 364 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
cb5a6ffc
RK		 365 DRIVER_NAME, aaci);
366 if (ret)
367 goto out;
368
369 return 0;
370
371 out:
372 return ret;
373}
374
375
376/*
377 * Common ALSA stuff
378 */
ceb9e476 379static int aaci_pcm_close(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 380{
381 struct aaci *aaci = substream->private_data;
382 struct aaci_runtime *aacirun = substream->runtime->private_data;
383
384 WARN_ON(aacirun->cr & TXCR_TXEN);
385
386 aacirun->substream = NULL;
387 free_irq(aaci->dev->irq[0], aaci);
388
389 return 0;
390}
391
ceb9e476 392static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 393{
394 struct aaci_runtime *aacirun = substream->runtime->private_data;
395
396 /*
397 * This must not be called with the device enabled.
398 */
399 WARN_ON(aacirun->cr & TXCR_TXEN);
400
401 if (aacirun->pcm_open)
402 snd_ac97_pcm_close(aacirun->pcm);
403 aacirun->pcm_open = 0;
404
405 /*
406 * Clear out the DMA and any allocated buffers.
407 */
408 devdma_hw_free(NULL, substream);
409
410 return 0;
411}
412
ceb9e476 413static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
cb5a6ffc 414 struct aaci_runtime *aacirun,
ceb9e476 415 struct snd_pcm_hw_params *params)
cb5a6ffc
RK		 416{
417 int err;
418
419 aaci_pcm_hw_free(substream);
420
421 err = devdma_hw_alloc(NULL, substream,
422 params_buffer_bytes(params));
423 if (err < 0)
424 goto out;
425
426 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
427 params_channels(params),
428 aacirun->pcm->r[0].slots);
429 if (err)
430 goto out;
431
432 aacirun->pcm_open = 1;
433
434 out:
435 return err;
436}
437
ceb9e476 438static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
cb5a6ffc 439{
ceb9e476 440 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 441 struct aaci_runtime *aacirun = runtime->private_data;
442
443 aacirun->start = (void *)runtime->dma_area;
444 aacirun->end = aacirun->start + runtime->dma_bytes;
445 aacirun->ptr = aacirun->start;
446 aacirun->period =
447 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
448
449 return 0;
450}
451
ceb9e476 452static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
cb5a6ffc 453{
ceb9e476 454 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 455 struct aaci_runtime *aacirun = runtime->private_data;
456 ssize_t bytes = aacirun->ptr - aacirun->start;
457
458 return bytes_to_frames(runtime, bytes);
459}
460
ceb9e476 461static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
cb5a6ffc
RK		 462{
463 return devdma_mmap(NULL, substream, vma);
464}
465
466
467/*
468 * Playback specific ALSA stuff
469 */
470static const u32 channels_to_txmask[] = {
471 [2] = TXCR_TX3 | TXCR_TX4,
472 [4] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8,
473 [6] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8 | TXCR_TX6 | TXCR_TX9,
474};
475
476/*
477 * We can support two and four channel audio. Unfortunately
478 * six channel audio requires a non-standard channel ordering:
479 * 2 -> FL(3), FR(4)
480 * 4 -> FL(3), FR(4), SL(7), SR(8)
481 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
482 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
483 * This requires an ALSA configuration file to correct.
484 */
485static unsigned int channel_list[] = { 2, 4, 6 };
486
487static int
ceb9e476 488aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
cb5a6ffc
RK		 489{
490 struct aaci *aaci = rule->private;
491 unsigned int chan_mask = 1 << 0, slots;
492
493 /*
494 * pcms[0] is the our 5.1 PCM instance.
495 */
496 slots = aaci->ac97_bus->pcms[0].r[0].slots;
497 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
498 chan_mask |= 1 << 1;
499 if (slots & (1 << AC97_SLOT_LFE))
500 chan_mask |= 1 << 2;
501 }
502
503 return snd_interval_list(hw_param_interval(p, rule->var),
504 ARRAY_SIZE(channel_list), channel_list,
505 chan_mask);
506}
507
ceb9e476 508static int aaci_pcm_playback_open(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 509{
510 struct aaci *aaci = substream->private_data;
511 int ret;
512
513 /*
514 * Add rule describing channel dependency.
515 */
516 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
517 SNDRV_PCM_HW_PARAM_CHANNELS,
518 aaci_rule_channels, aaci,
519 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
520 if (ret)
521 return ret;
522
523 return aaci_pcm_open(aaci, substream, &aaci->playback);
524}
525
ceb9e476
TI		 526static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
527 struct snd_pcm_hw_params *params)
cb5a6ffc
RK		 528{
529 struct aaci *aaci = substream->private_data;
530 struct aaci_runtime *aacirun = substream->runtime->private_data;
531 unsigned int channels = params_channels(params);
532 int ret;
533
534 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
535 !channels_to_txmask[channels]);
536
537 ret = aaci_pcm_hw_params(substream, aacirun, params);
538
539 /*
540 * Enable FIFO, compact mode, 16 bits per sample.
541 * FIXME: double rate slots?
542 */
543 if (ret >= 0) {
544 aacirun->cr = TXCR_FEN | TXCR_COMPACT | TXCR_TSZ16;
545 aacirun->cr |= channels_to_txmask[channels];
546
547 aacirun->fifosz = aaci->fifosize * 4;
548 if (aacirun->cr & TXCR_COMPACT)
549 aacirun->fifosz >>= 1;
550 }
551 return ret;
552}
553
554static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
555{
556 u32 ie;
557
558 ie = readl(aacirun->base + AACI_IE);
559 ie &= ~(IE_URIE|IE_TXIE);
560 writel(ie, aacirun->base + AACI_IE);
561 aacirun->cr &= ~TXCR_TXEN;
562 aaci_chan_wait_ready(aacirun);
563 writel(aacirun->cr, aacirun->base + AACI_TXCR);
564}
565
566static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
567{
568 u32 ie;
569
570 aaci_chan_wait_ready(aacirun);
571 aacirun->cr |= TXCR_TXEN;
572
573 ie = readl(aacirun->base + AACI_IE);
574 ie |= IE_URIE | IE_TXIE;
575 writel(ie, aacirun->base + AACI_IE);
576 writel(aacirun->cr, aacirun->base + AACI_TXCR);
577}
578
ceb9e476 579static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
cb5a6ffc
RK		 580{
581 struct aaci *aaci = substream->private_data;
582 struct aaci_runtime *aacirun = substream->runtime->private_data;
583 unsigned long flags;
584 int ret = 0;
585
586 spin_lock_irqsave(&aaci->lock, flags);
587 switch (cmd) {
588 case SNDRV_PCM_TRIGGER_START:
589 aaci_pcm_playback_start(aacirun);
590 break;
591
592 case SNDRV_PCM_TRIGGER_RESUME:
593 aaci_pcm_playback_start(aacirun);
594 break;
595
596 case SNDRV_PCM_TRIGGER_STOP:
597 aaci_pcm_playback_stop(aacirun);
598 break;
599
600 case SNDRV_PCM_TRIGGER_SUSPEND:
601 aaci_pcm_playback_stop(aacirun);
602 break;
603
604 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
605 break;
606
607 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
608 break;
609
610 default:
611 ret = -EINVAL;
612 }
613 spin_unlock_irqrestore(&aaci->lock, flags);
614
615 return ret;
616}
617
ceb9e476 618static struct snd_pcm_ops aaci_playback_ops = {
cb5a6ffc
RK		 619 .open = aaci_pcm_playback_open,
620 .close = aaci_pcm_close,
621 .ioctl = snd_pcm_lib_ioctl,
622 .hw_params = aaci_pcm_playback_hw_params,
623 .hw_free = aaci_pcm_hw_free,
624 .prepare = aaci_pcm_prepare,
625 .trigger = aaci_pcm_playback_trigger,
626 .pointer = aaci_pcm_pointer,
627 .mmap = aaci_pcm_mmap,
628};
629
630
631
632/*
633 * Power Management.
634 */
635#ifdef CONFIG_PM
ceb9e476 636static int aaci_do_suspend(struct snd_card *card, unsigned int state)
cb5a6ffc
RK		 637{
638 struct aaci *aaci = card->private_data;
792a6c51
TI		 639 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
640 snd_pcm_suspend_all(aaci->pcm);
cb5a6ffc
RK		 641 return 0;
642}
643
ceb9e476 644static int aaci_do_resume(struct snd_card *card, unsigned int state)
cb5a6ffc 645{
792a6c51 646 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
cb5a6ffc
RK		 647 return 0;
648}
649
e36d394d 650static int aaci_suspend(struct amba_device *dev, pm_message_t state)
cb5a6ffc 651{
ceb9e476 652 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 653 return card ? aaci_do_suspend(card) : 0;
654}
655
656static int aaci_resume(struct amba_device *dev)
657{
ceb9e476 658 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 659 return card ? aaci_do_resume(card) : 0;
660}
661#else
662#define aaci_do_suspend NULL
663#define aaci_do_resume NULL
664#define aaci_suspend NULL
665#define aaci_resume NULL
666#endif
667
668
669static struct ac97_pcm ac97_defs[] __devinitdata = {
670 [0] = { /* Front PCM */
671 .exclusive = 1,
672 .r = {
673 [0] = {
674 .slots = (1 << AC97_SLOT_PCM_LEFT) |
675 (1 << AC97_SLOT_PCM_RIGHT) |
676 (1 << AC97_SLOT_PCM_CENTER) |
677 (1 << AC97_SLOT_PCM_SLEFT) |
678 (1 << AC97_SLOT_PCM_SRIGHT) |
679 (1 << AC97_SLOT_LFE),
680 },
681 },
682 },
683 [1] = { /* PCM in */
684 .stream = 1,
685 .exclusive = 1,
686 .r = {
687 [0] = {
688 .slots = (1 << AC97_SLOT_PCM_LEFT) |
689 (1 << AC97_SLOT_PCM_RIGHT),
690 },
691 },
692 },
693 [2] = { /* Mic in */
694 .stream = 1,
695 .exclusive = 1,
696 .r = {
697 [0] = {
698 .slots = (1 << AC97_SLOT_MIC),
699 },
700 },
701 }
702};
703
ceb9e476 704static struct snd_ac97_bus_ops aaci_bus_ops = {
cb5a6ffc
RK		 705 .write = aaci_ac97_write,
706 .read = aaci_ac97_read,
707};
708
709static int __devinit aaci_probe_ac97(struct aaci *aaci)
710{
ceb9e476
TI		 711 struct snd_ac97_template ac97_template;
712 struct snd_ac97_bus *ac97_bus;
713 struct snd_ac97 *ac97;
cb5a6ffc
RK		 714 int ret;
715
716 /*
717 * Assert AACIRESET for 2us
718 */
719 writel(0, aaci->base + AACI_RESET);
720 udelay(2);
721 writel(RESET_NRST, aaci->base + AACI_RESET);
722
723 /*
724 * Give the AC'97 codec more than enough time
725 * to wake up. (42us = ~2 frames at 48kHz.)
726 */
727 udelay(42);
728
729 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
730 if (ret)
731 goto out;
732
733 ac97_bus->clock = 48000;
734 aaci->ac97_bus = ac97_bus;
735
ceb9e476 736 memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
cb5a6ffc
RK		 737 ac97_template.private_data = aaci;
738 ac97_template.num = 0;
739 ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
740
741 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
742 if (ret)
743 goto out;
744
745 /*
746 * Disable AC97 PC Beep input on audio codecs.
747 */
748 if (ac97_is_audio(ac97))
749 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
750
751 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
752 if (ret)
753 goto out;
754
755 aaci->playback.pcm = &ac97_bus->pcms[0];
756
757 out:
758 return ret;
759}
760
ceb9e476 761static void aaci_free_card(struct snd_card *card)
cb5a6ffc
RK		 762{
763 struct aaci *aaci = card->private_data;
764 if (aaci->base)
765 iounmap(aaci->base);
766}
767
768static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
769{
770 struct aaci *aaci;
ceb9e476 771 struct snd_card *card;
cb5a6ffc
RK		 772
773 card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
774 THIS_MODULE, sizeof(struct aaci));
775 if (card == NULL)
776 return ERR_PTR(-ENOMEM);
777
778 card->private_free = aaci_free_card;
cb5a6ffc
RK		 779
780 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
781 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
782 snprintf(card->longname, sizeof(card->longname),
aa0a2ddc
GKH		 783 "%s at 0x%016llx, irq %d",
784 card->shortname, (unsigned long long)dev->res.start,
785 dev->irq[0]);
cb5a6ffc
RK		 786
787 aaci = card->private_data;
12aa7579 788 mutex_init(&aaci->ac97_sem);
cb5a6ffc
RK		 789 spin_lock_init(&aaci->lock);
790 aaci->card = card;
791 aaci->dev = dev;
792
793 /* Set MAINCR to allow slot 1 and 2 data IO */
794 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
795 MAINCR_SL2RXEN | MAINCR_SL2TXEN;
796
797 return aaci;
798}
799
800static int __devinit aaci_init_pcm(struct aaci *aaci)
801{
ceb9e476 802 struct snd_pcm *pcm;
cb5a6ffc
RK		 803 int ret;
804
805 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 0, &pcm);
806 if (ret == 0) {
807 aaci->pcm = pcm;
808 pcm->private_data = aaci;
809 pcm->info_flags = 0;
810
811 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
812
813 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
814 }
815
816 return ret;
817}
818
819static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
820{
e12ba644 821 void __iomem *base = aaci->base + AACI_CSCH1;
cb5a6ffc
RK		 822 int i;
823
824 writel(TXCR_FEN | TXCR_TSZ16 | TXCR_TXEN, base + AACI_TXCR);
825
826 for (i = 0; !(readl(base + AACI_SR) & SR_TXFF) && i < 4096; i++)
827 writel(0, aaci->base + AACI_DR1);
828
829 writel(0, base + AACI_TXCR);
830
831 /*
832 * Re-initialise the AACI after the FIFO depth test, to
833 * ensure that the FIFOs are empty. Unfortunately, merely
834 * disabling the channel doesn't clear the FIFO.
835 */
836 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
837 writel(aaci->maincr, aaci->base + AACI_MAINCR);
838
839 /*
840 * If we hit 4096, we failed. Go back to the specified
841 * fifo depth.
842 */
843 if (i == 4096)
844 i = 8;
845
846 return i;
847}
848
849static int __devinit aaci_probe(struct amba_device *dev, void *id)
850{
851 struct aaci *aaci;
852 int ret, i;
853
854 ret = amba_request_regions(dev, NULL);
855 if (ret)
856 return ret;
857
858 aaci = aaci_init_card(dev);
859 if (IS_ERR(aaci)) {
860 ret = PTR_ERR(aaci);
861 goto out;
862 }
863
864 aaci->base = ioremap(dev->res.start, SZ_4K);
865 if (!aaci->base) {
866 ret = -ENOMEM;
867 goto out;
868 }
869
870 /*
871 * Playback uses AACI channel 0
872 */
873 aaci->playback.base = aaci->base + AACI_CSCH1;
874 aaci->playback.fifo = aaci->base + AACI_DR1;
875
876 for (i = 0; i < 4; i++) {
e12ba644 877 void __iomem *base = aaci->base + i * 0x14;
cb5a6ffc
RK		 878
879 writel(0, base + AACI_IE);
880 writel(0, base + AACI_TXCR);
881 writel(0, base + AACI_RXCR);
882 }
883
884 writel(0x1fff, aaci->base + AACI_INTCLR);
885 writel(aaci->maincr, aaci->base + AACI_MAINCR);
886
f27f218c
CM		 887 ret = aaci_probe_ac97(aaci);
888 if (ret)
889 goto out;
890
cb5a6ffc 891 /*
f27f218c 892 * Size the FIFOs (must be multiple of 16).
cb5a6ffc
RK		 893 */
894 aaci->fifosize = aaci_size_fifo(aaci);
f27f218c
CM		 895 if (aaci->fifosize & 15) {
896 printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
897 aaci->fifosize);
898 ret = -ENODEV;
cb5a6ffc 899 goto out;
f27f218c 900 }
cb5a6ffc
RK		 901
902 ret = aaci_init_pcm(aaci);
903 if (ret)
904 goto out;
905
a76af199
TI		 906 snd_card_set_dev(aaci->card, &dev->dev);
907
cb5a6ffc
RK		 908 ret = snd_card_register(aaci->card);
909 if (ret == 0) {
910 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
911 aaci->fifosize);
912 amba_set_drvdata(dev, aaci->card);
913 return ret;
914 }
915
916 out:
917 if (aaci)
918 snd_card_free(aaci->card);
919 amba_release_regions(dev);
920 return ret;
921}
922
923static int __devexit aaci_remove(struct amba_device *dev)
924{
ceb9e476 925 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 926
927 amba_set_drvdata(dev, NULL);
928
929 if (card) {
930 struct aaci *aaci = card->private_data;
931 writel(0, aaci->base + AACI_MAINCR);
932
933 snd_card_free(card);
934 amba_release_regions(dev);
935 }
936
937 return 0;
938}
939
940static struct amba_id aaci_ids[] = {
941 {
942 .id = 0x00041041,
943 .mask = 0x000fffff,
944 },
945 { 0, 0 },
946};
947
948static struct amba_driver aaci_driver = {
949 .drv = {
950 .name = DRIVER_NAME,
951 },
952 .probe = aaci_probe,
953 .remove = __devexit_p(aaci_remove),
954 .suspend = aaci_suspend,
955 .resume = aaci_resume,
956 .id_table = aaci_ids,
957};
958
959static int __init aaci_init(void)
960{
961 return amba_driver_register(&aaci_driver);
962}
963
964static void __exit aaci_exit(void)
965{
966 amba_driver_unregister(&aaci_driver);
967}
968
969module_init(aaci_init);
970module_exit(aaci_exit);
971
972MODULE_LICENSE("GPL");
973MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
Linux kernel - Deliverables
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