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ALSA: AACI: factor common hw_params logic into aaci_pcm_hw_params
[deliverable/linux.git] / sound / arm / aaci.c
CommitLineData
cb5a6ffc
RK		 1/*
2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Documentation: ARM DDI 0173B
11 */
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/device.h>
17#include <linux/spinlock.h>
18#include <linux/interrupt.h>
19#include <linux/err.h>
a62c80e5 20#include <linux/amba/bus.h>
88cdca9c 21#include <linux/io.h>
cb5a6ffc 22
cb5a6ffc
RK		 23#include <sound/core.h>
24#include <sound/initval.h>
25#include <sound/ac97_codec.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28
29#include "aaci.h"
cb5a6ffc
RK		 30
31#define DRIVER_NAME "aaci-pl041"
32
33/*
34 * PM support is not complete. Turn it off.
35 */
36#undef CONFIG_PM
37
ceb9e476 38static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
cb5a6ffc
RK		 39{
40 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
41
42 /*
43 * Ensure that the slot 1/2 RX registers are empty.
44 */
45 v = readl(aaci->base + AACI_SLFR);
46 if (v & SLFR_2RXV)
47 readl(aaci->base + AACI_SL2RX);
48 if (v & SLFR_1RXV)
49 readl(aaci->base + AACI_SL1RX);
50
51 writel(maincr, aaci->base + AACI_MAINCR);
52}
53
54/*
55 * P29:
56 * The recommended use of programming the external codec through slot 1
57 * and slot 2 data is to use the channels during setup routines and the
58 * slot register at any other time. The data written into slot 1, slot 2
59 * and slot 12 registers is transmitted only when their corresponding
60 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
61 * register.
62 */
14d178a1
KH		 63static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
64 unsigned short val)
cb5a6ffc
RK		 65{
66 struct aaci *aaci = ac97->private_data;
67 u32 v;
14d178a1 68 int timeout = 5000;
cb5a6ffc
RK		 69
70 if (ac97->num >= 4)
71 return;
72
12aa7579 73 mutex_lock(&aaci->ac97_sem);
cb5a6ffc
RK		 74
75 aaci_ac97_select_codec(aaci, ac97);
76
77 /*
78 * P54: You must ensure that AACI_SL2TX is always written
79 * to, if required, before data is written to AACI_SL1TX.
80 */
81 writel(val << 4, aaci->base + AACI_SL2TX);
82 writel(reg << 12, aaci->base + AACI_SL1TX);
83
84 /*
85 * Wait for the transmission of both slots to complete.
86 */
87 do {
88 v = readl(aaci->base + AACI_SLFR);
f6f35bbe 89 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
14d178a1
KH		 90
91 if (!timeout)
92 dev_err(&aaci->dev->dev,
93 "timeout waiting for write to complete\n");
cb5a6ffc 94
12aa7579 95 mutex_unlock(&aaci->ac97_sem);
cb5a6ffc
RK		 96}
97
98/*
99 * Read an AC'97 register.
100 */
ceb9e476 101static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
cb5a6ffc
RK		 102{
103 struct aaci *aaci = ac97->private_data;
104 u32 v;
14d178a1
KH		 105 int timeout = 5000;
106 int retries = 10;
cb5a6ffc
RK		 107
108 if (ac97->num >= 4)
109 return ~0;
110
12aa7579 111 mutex_lock(&aaci->ac97_sem);
cb5a6ffc
RK		 112
113 aaci_ac97_select_codec(aaci, ac97);
114
115 /*
116 * Write the register address to slot 1.
117 */
118 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
119
120 /*
121 * Wait for the transmission to complete.
122 */
123 do {
124 v = readl(aaci->base + AACI_SLFR);
f6f35bbe 125 } while ((v & SLFR_1TXB) && --timeout);
14d178a1
KH		 126
127 if (!timeout) {
128 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
129 v = ~0;
130 goto out;
131 }
cb5a6ffc
RK		 132
133 /*
134 * Give the AC'97 codec more than enough time
135 * to respond. (42us = ~2 frames at 48kHz.)
136 */
137 udelay(42);
138
139 /*
140 * Wait for slot 2 to indicate data.
141 */
14d178a1 142 timeout = 5000;
cb5a6ffc
RK		 143 do {
144 cond_resched();
145 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
f6f35bbe 146 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
cb5a6ffc 147
14d178a1
KH		 148 if (!timeout) {
149 dev_err(&aaci->dev->dev, "timeout on RX valid\n");
cb5a6ffc 150 v = ~0;
14d178a1 151 goto out;
cb5a6ffc
RK		 152 }
153
14d178a1
KH		 154 do {
155 v = readl(aaci->base + AACI_SL1RX) >> 12;
156 if (v == reg) {
157 v = readl(aaci->base + AACI_SL2RX) >> 4;
158 break;
159 } else if (--retries) {
160 dev_warn(&aaci->dev->dev,
161 "ac97 read back fail. retry\n");
162 continue;
163 } else {
164 dev_warn(&aaci->dev->dev,
165 "wrong ac97 register read back (%x != %x)\n",
166 v, reg);
167 v = ~0;
168 }
169 } while (retries);
170 out:
12aa7579 171 mutex_unlock(&aaci->ac97_sem);
cb5a6ffc
RK		 172 return v;
173}
174
175static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
176{
177 u32 val;
178 int timeout = 5000;
179
180 do {
181 val = readl(aacirun->base + AACI_SR);
182 } while (val & (SR_TXB|SR_RXB) && timeout--);
183}
184
185
186
187/*
188 * Interrupt support.
189 */
62578cbf 190static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
cb5a6ffc 191{
41762b8c
KH		 192 if (mask & ISR_ORINTR) {
193 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
194 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
195 }
196
197 if (mask & ISR_RXTOINTR) {
198 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
199 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
200 }
201
202 if (mask & ISR_RXINTR) {
203 struct aaci_runtime *aacirun = &aaci->capture;
204 void *ptr;
205
206 if (!aacirun->substream || !aacirun->start) {
898eb71c 207 dev_warn(&aaci->dev->dev, "RX interrupt???\n");
41762b8c
KH		 208 writel(0, aacirun->base + AACI_IE);
209 return;
210 }
211 ptr = aacirun->ptr;
212
213 do {
214 unsigned int len = aacirun->fifosz;
215 u32 val;
216
217 if (aacirun->bytes <= 0) {
218 aacirun->bytes += aacirun->period;
219 aacirun->ptr = ptr;
220 spin_unlock(&aaci->lock);
221 snd_pcm_period_elapsed(aacirun->substream);
222 spin_lock(&aaci->lock);
223 }
224 if (!(aacirun->cr & CR_EN))
225 break;
226
227 val = readl(aacirun->base + AACI_SR);
228 if (!(val & SR_RXHF))
229 break;
230 if (!(val & SR_RXFF))
231 len >>= 1;
232
233 aacirun->bytes -= len;
234
235 /* reading 16 bytes at a time */
236 for( ; len > 0; len -= 16) {
237 asm(
238 "ldmia %1, {r0, r1, r2, r3}\n\t"
239 "stmia %0!, {r0, r1, r2, r3}"
240 : "+r" (ptr)
241 : "r" (aacirun->fifo)
242 : "r0", "r1", "r2", "r3", "cc");
243
244 if (ptr >= aacirun->end)
245 ptr = aacirun->start;
246 }
247 } while(1);
248 aacirun->ptr = ptr;
249 }
250
cb5a6ffc 251 if (mask & ISR_URINTR) {
62578cbf
KH		 252 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
253 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
cb5a6ffc
RK		 254 }
255
256 if (mask & ISR_TXINTR) {
257 struct aaci_runtime *aacirun = &aaci->playback;
258 void *ptr;
259
260 if (!aacirun->substream || !aacirun->start) {
898eb71c 261 dev_warn(&aaci->dev->dev, "TX interrupt???\n");
cb5a6ffc
RK		 262 writel(0, aacirun->base + AACI_IE);
263 return;
264 }
265
266 ptr = aacirun->ptr;
267 do {
268 unsigned int len = aacirun->fifosz;
269 u32 val;
270
271 if (aacirun->bytes <= 0) {
272 aacirun->bytes += aacirun->period;
273 aacirun->ptr = ptr;
274 spin_unlock(&aaci->lock);
275 snd_pcm_period_elapsed(aacirun->substream);
276 spin_lock(&aaci->lock);
277 }
41762b8c 278 if (!(aacirun->cr & CR_EN))
cb5a6ffc
RK		 279 break;
280
281 val = readl(aacirun->base + AACI_SR);
282 if (!(val & SR_TXHE))
283 break;
284 if (!(val & SR_TXFE))
285 len >>= 1;
286
287 aacirun->bytes -= len;
288
289 /* writing 16 bytes at a time */
290 for ( ; len > 0; len -= 16) {
291 asm(
292 "ldmia %0!, {r0, r1, r2, r3}\n\t"
293 "stmia %1, {r0, r1, r2, r3}"
294 : "+r" (ptr)
295 : "r" (aacirun->fifo)
296 : "r0", "r1", "r2", "r3", "cc");
297
298 if (ptr >= aacirun->end)
299 ptr = aacirun->start;
300 }
301 } while (1);
302
303 aacirun->ptr = ptr;
304 }
305}
306
7d12e780 307static irqreturn_t aaci_irq(int irq, void *devid)
cb5a6ffc
RK		 308{
309 struct aaci *aaci = devid;
310 u32 mask;
311 int i;
312
313 spin_lock(&aaci->lock);
314 mask = readl(aaci->base + AACI_ALLINTS);
315 if (mask) {
316 u32 m = mask;
317 for (i = 0; i < 4; i++, m >>= 7) {
318 if (m & 0x7f) {
62578cbf 319 aaci_fifo_irq(aaci, i, m);
cb5a6ffc
RK		 320 }
321 }
322 }
323 spin_unlock(&aaci->lock);
324
325 return mask ? IRQ_HANDLED : IRQ_NONE;
326}
327
328
329
330/*
331 * ALSA support.
332 */
ceb9e476 333static struct snd_pcm_hardware aaci_hw_info = {
cb5a6ffc
RK		 334 .info = SNDRV_PCM_INFO_MMAP |
335 SNDRV_PCM_INFO_MMAP_VALID |
336 SNDRV_PCM_INFO_INTERLEAVED |
337 SNDRV_PCM_INFO_BLOCK_TRANSFER |
338 SNDRV_PCM_INFO_RESUME,
339
340 /*
341 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
342 * words. It also doesn't support 12-bit at all.
343 */
344 .formats = SNDRV_PCM_FMTBIT_S16_LE,
345
6ca867c8 346 /* rates are setup from the AC'97 codec */
cb5a6ffc
RK		 347 .channels_min = 2,
348 .channels_max = 6,
349 .buffer_bytes_max = 64 * 1024,
350 .period_bytes_min = 256,
351 .period_bytes_max = PAGE_SIZE,
352 .periods_min = 4,
353 .periods_max = PAGE_SIZE / 16,
354};
355
41762b8c
KH		 356static int __aaci_pcm_open(struct aaci *aaci,
357 struct snd_pcm_substream *substream,
358 struct aaci_runtime *aacirun)
cb5a6ffc 359{
ceb9e476 360 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 361 int ret;
362
363 aacirun->substream = substream;
364 runtime->private_data = aacirun;
365 runtime->hw = aaci_hw_info;
6ca867c8
RK		 366 runtime->hw.rates = aacirun->pcm->rates;
367 snd_pcm_limit_hw_rates(runtime);
cb5a6ffc
RK		 368
369 /*
370 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
371 * mode, each 32-bit word contains one sample. If we're in
372 * compact mode, each 32-bit word contains two samples, effectively
373 * halving the FIFO size. However, we don't know for sure which
374 * we'll be using at this point. We set this to the lower limit.
375 */
376 runtime->hw.fifo_size = aaci->fifosize * 2;
377
65ca68b3 378 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
cb5a6ffc
RK		 379 DRIVER_NAME, aaci);
380 if (ret)
381 goto out;
382
383 return 0;
384
385 out:
386 return ret;
387}
388
389
390/*
391 * Common ALSA stuff
392 */
ceb9e476 393static int aaci_pcm_close(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 394{
395 struct aaci *aaci = substream->private_data;
396 struct aaci_runtime *aacirun = substream->runtime->private_data;
397
41762b8c 398 WARN_ON(aacirun->cr & CR_EN);
cb5a6ffc
RK		 399
400 aacirun->substream = NULL;
401 free_irq(aaci->dev->irq[0], aaci);
402
403 return 0;
404}
405
ceb9e476 406static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 407{
408 struct aaci_runtime *aacirun = substream->runtime->private_data;
409
410 /*
411 * This must not be called with the device enabled.
412 */
41762b8c 413 WARN_ON(aacirun->cr & CR_EN);
cb5a6ffc
RK		 414
415 if (aacirun->pcm_open)
416 snd_ac97_pcm_close(aacirun->pcm);
417 aacirun->pcm_open = 0;
418
419 /*
420 * Clear out the DMA and any allocated buffers.
421 */
d6797322 422 snd_pcm_lib_free_pages(substream);
cb5a6ffc
RK		 423
424 return 0;
425}
426
ceb9e476 427static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
cb5a6ffc 428 struct aaci_runtime *aacirun,
ceb9e476 429 struct snd_pcm_hw_params *params)
cb5a6ffc
RK		 430{
431 int err;
432
433 aaci_pcm_hw_free(substream);
4acd57c3
RK		 434 if (aacirun->pcm_open) {
435 snd_ac97_pcm_close(aacirun->pcm);
436 aacirun->pcm_open = 0;
437 }
cb5a6ffc 438
d6797322
TI		 439 err = snd_pcm_lib_malloc_pages(substream,
440 params_buffer_bytes(params));
4e30b691
RK		 441 if (err >= 0) {
442 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
443 params_channels(params),
444 aacirun->pcm->r[0].slots);
cb5a6ffc 445
4e30b691 446 aacirun->pcm_open = err == 0;
d3aee799
RK		 447 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
448 aacirun->fifosz = aaci->fifosize * 4;
449
450 if (aacirun->cr & CR_COMPACT)
451 aacirun->fifosz >>= 1;
4e30b691 452 }
cb5a6ffc 453
cb5a6ffc
RK		 454 return err;
455}
456
ceb9e476 457static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
cb5a6ffc 458{
ceb9e476 459 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 460 struct aaci_runtime *aacirun = runtime->private_data;
461
4e30b691 462 aacirun->start = runtime->dma_area;
88cdca9c 463 aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
cb5a6ffc
RK		 464 aacirun->ptr = aacirun->start;
465 aacirun->period =
466 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
467
468 return 0;
469}
470
ceb9e476 471static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
cb5a6ffc 472{
ceb9e476 473 struct snd_pcm_runtime *runtime = substream->runtime;
cb5a6ffc
RK		 474 struct aaci_runtime *aacirun = runtime->private_data;
475 ssize_t bytes = aacirun->ptr - aacirun->start;
476
477 return bytes_to_frames(runtime, bytes);
478}
479
cb5a6ffc
RK		 480
481/*
482 * Playback specific ALSA stuff
483 */
484static const u32 channels_to_txmask[] = {
41762b8c
KH		 485 [2] = CR_SL3 | CR_SL4,
486 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
487 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
cb5a6ffc
RK		 488};
489
490/*
491 * We can support two and four channel audio. Unfortunately
492 * six channel audio requires a non-standard channel ordering:
493 * 2 -> FL(3), FR(4)
494 * 4 -> FL(3), FR(4), SL(7), SR(8)
495 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
496 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
497 * This requires an ALSA configuration file to correct.
498 */
499static unsigned int channel_list[] = { 2, 4, 6 };
500
501static int
ceb9e476 502aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
cb5a6ffc
RK		 503{
504 struct aaci *aaci = rule->private;
505 unsigned int chan_mask = 1 << 0, slots;
506
507 /*
508 * pcms[0] is the our 5.1 PCM instance.
509 */
510 slots = aaci->ac97_bus->pcms[0].r[0].slots;
511 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
512 chan_mask |= 1 << 1;
513 if (slots & (1 << AC97_SLOT_LFE))
514 chan_mask |= 1 << 2;
515 }
516
517 return snd_interval_list(hw_param_interval(p, rule->var),
518 ARRAY_SIZE(channel_list), channel_list,
519 chan_mask);
520}
521
41762b8c 522static int aaci_pcm_open(struct snd_pcm_substream *substream)
cb5a6ffc
RK		 523{
524 struct aaci *aaci = substream->private_data;
525 int ret;
526
527 /*
528 * Add rule describing channel dependency.
529 */
530 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
531 SNDRV_PCM_HW_PARAM_CHANNELS,
532 aaci_rule_channels, aaci,
533 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
534 if (ret)
535 return ret;
536
41762b8c
KH		 537 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
538 ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
539 } else {
540 ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
541 }
542 return ret;
cb5a6ffc
RK		 543}
544
ceb9e476
TI		 545static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
546 struct snd_pcm_hw_params *params)
cb5a6ffc
RK		 547{
548 struct aaci *aaci = substream->private_data;
549 struct aaci_runtime *aacirun = substream->runtime->private_data;
550 unsigned int channels = params_channels(params);
551 int ret;
552
553 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
554 !channels_to_txmask[channels]);
555
556 ret = aaci_pcm_hw_params(substream, aacirun, params);
557
558 /*
559 * Enable FIFO, compact mode, 16 bits per sample.
560 * FIXME: double rate slots?
561 */
d3aee799 562 if (ret >= 0)
cb5a6ffc
RK		 563 aacirun->cr |= channels_to_txmask[channels];
564
cb5a6ffc
RK		 565 return ret;
566}
567
568static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
569{
570 u32 ie;
571
572 ie = readl(aacirun->base + AACI_IE);
573 ie &= ~(IE_URIE|IE_TXIE);
574 writel(ie, aacirun->base + AACI_IE);
41762b8c 575 aacirun->cr &= ~CR_EN;
cb5a6ffc
RK		 576 aaci_chan_wait_ready(aacirun);
577 writel(aacirun->cr, aacirun->base + AACI_TXCR);
578}
579
580static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
581{
582 u32 ie;
583
584 aaci_chan_wait_ready(aacirun);
41762b8c 585 aacirun->cr |= CR_EN;
cb5a6ffc
RK		 586
587 ie = readl(aacirun->base + AACI_IE);
588 ie |= IE_URIE | IE_TXIE;
589 writel(ie, aacirun->base + AACI_IE);
590 writel(aacirun->cr, aacirun->base + AACI_TXCR);
591}
592
ceb9e476 593static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
cb5a6ffc
RK		 594{
595 struct aaci *aaci = substream->private_data;
596 struct aaci_runtime *aacirun = substream->runtime->private_data;
597 unsigned long flags;
598 int ret = 0;
599
600 spin_lock_irqsave(&aaci->lock, flags);
601 switch (cmd) {
602 case SNDRV_PCM_TRIGGER_START:
603 aaci_pcm_playback_start(aacirun);
604 break;
605
606 case SNDRV_PCM_TRIGGER_RESUME:
607 aaci_pcm_playback_start(aacirun);
608 break;
609
610 case SNDRV_PCM_TRIGGER_STOP:
611 aaci_pcm_playback_stop(aacirun);
612 break;
613
614 case SNDRV_PCM_TRIGGER_SUSPEND:
615 aaci_pcm_playback_stop(aacirun);
616 break;
617
618 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
619 break;
620
621 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
622 break;
623
624 default:
625 ret = -EINVAL;
626 }
627 spin_unlock_irqrestore(&aaci->lock, flags);
628
629 return ret;
630}
631
ceb9e476 632static struct snd_pcm_ops aaci_playback_ops = {
41762b8c 633 .open = aaci_pcm_open,
cb5a6ffc
RK		 634 .close = aaci_pcm_close,
635 .ioctl = snd_pcm_lib_ioctl,
636 .hw_params = aaci_pcm_playback_hw_params,
637 .hw_free = aaci_pcm_hw_free,
638 .prepare = aaci_pcm_prepare,
639 .trigger = aaci_pcm_playback_trigger,
640 .pointer = aaci_pcm_pointer,
cb5a6ffc
RK		 641};
642
8a371840
RK		 643static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
644 struct snd_pcm_hw_params *params)
41762b8c
KH		 645{
646 struct aaci *aaci = substream->private_data;
647 struct aaci_runtime *aacirun = substream->runtime->private_data;
648 int ret;
649
650 ret = aaci_pcm_hw_params(substream, aacirun, params);
d3aee799 651 if (ret >= 0)
41762b8c
KH		 652 /* Line in record: slot 3 and 4 */
653 aacirun->cr |= CR_SL3 | CR_SL4;
654
41762b8c
KH		 655 return ret;
656}
657
658static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
659{
660 u32 ie;
661
662 aaci_chan_wait_ready(aacirun);
663
664 ie = readl(aacirun->base + AACI_IE);
665 ie &= ~(IE_ORIE | IE_RXIE);
666 writel(ie, aacirun->base+AACI_IE);
667
668 aacirun->cr &= ~CR_EN;
cb5a6ffc 669
41762b8c
KH		 670 writel(aacirun->cr, aacirun->base + AACI_RXCR);
671}
672
673static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
674{
675 u32 ie;
676
677 aaci_chan_wait_ready(aacirun);
678
679#ifdef DEBUG
680 /* RX Timeout value: bits 28:17 in RXCR */
681 aacirun->cr |= 0xf << 17;
682#endif
683
684 aacirun->cr |= CR_EN;
685 writel(aacirun->cr, aacirun->base + AACI_RXCR);
686
687 ie = readl(aacirun->base + AACI_IE);
688 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
689 writel(ie, aacirun->base + AACI_IE);
690}
691
8a371840
RK		 692static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
693{
41762b8c
KH		 694 struct aaci *aaci = substream->private_data;
695 struct aaci_runtime *aacirun = substream->runtime->private_data;
696 unsigned long flags;
697 int ret = 0;
698
699 spin_lock_irqsave(&aaci->lock, flags);
700
701 switch (cmd) {
702 case SNDRV_PCM_TRIGGER_START:
703 aaci_pcm_capture_start(aacirun);
704 break;
705
706 case SNDRV_PCM_TRIGGER_RESUME:
707 aaci_pcm_capture_start(aacirun);
708 break;
709
710 case SNDRV_PCM_TRIGGER_STOP:
711 aaci_pcm_capture_stop(aacirun);
712 break;
713
714 case SNDRV_PCM_TRIGGER_SUSPEND:
715 aaci_pcm_capture_stop(aacirun);
716 break;
717
718 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
719 break;
720
721 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
722 break;
723
724 default:
725 ret = -EINVAL;
726 }
727
728 spin_unlock_irqrestore(&aaci->lock, flags);
729
730 return ret;
731}
732
8a371840 733static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
41762b8c
KH		 734{
735 struct snd_pcm_runtime *runtime = substream->runtime;
736 struct aaci *aaci = substream->private_data;
737
738 aaci_pcm_prepare(substream);
739
740 /* allow changing of sample rate */
741 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
742 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
743 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
744
745 /* Record select: Mic: 0, Aux: 3, Line: 4 */
746 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
747
748 return 0;
749}
750
8a371840 751static struct snd_pcm_ops aaci_capture_ops = {
41762b8c
KH		 752 .open = aaci_pcm_open,
753 .close = aaci_pcm_close,
754 .ioctl = snd_pcm_lib_ioctl,
755 .hw_params = aaci_pcm_capture_hw_params,
756 .hw_free = aaci_pcm_hw_free,
757 .prepare = aaci_pcm_capture_prepare,
758 .trigger = aaci_pcm_capture_trigger,
759 .pointer = aaci_pcm_pointer,
41762b8c 760};
cb5a6ffc
RK		 761
762/*
763 * Power Management.
764 */
765#ifdef CONFIG_PM
ceb9e476 766static int aaci_do_suspend(struct snd_card *card, unsigned int state)
cb5a6ffc
RK		 767{
768 struct aaci *aaci = card->private_data;
792a6c51
TI		 769 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
770 snd_pcm_suspend_all(aaci->pcm);
cb5a6ffc
RK		 771 return 0;
772}
773
ceb9e476 774static int aaci_do_resume(struct snd_card *card, unsigned int state)
cb5a6ffc 775{
792a6c51 776 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
cb5a6ffc
RK		 777 return 0;
778}
779
e36d394d 780static int aaci_suspend(struct amba_device *dev, pm_message_t state)
cb5a6ffc 781{
ceb9e476 782 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 783 return card ? aaci_do_suspend(card) : 0;
784}
785
786static int aaci_resume(struct amba_device *dev)
787{
ceb9e476 788 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 789 return card ? aaci_do_resume(card) : 0;
790}
791#else
792#define aaci_do_suspend NULL
793#define aaci_do_resume NULL
794#define aaci_suspend NULL
795#define aaci_resume NULL
796#endif
797
798
799static struct ac97_pcm ac97_defs[] __devinitdata = {
41762b8c 800 [0] = { /* Front PCM */
cb5a6ffc
RK		 801 .exclusive = 1,
802 .r = {
803 [0] = {
804 .slots = (1 << AC97_SLOT_PCM_LEFT) |
805 (1 << AC97_SLOT_PCM_RIGHT) |
806 (1 << AC97_SLOT_PCM_CENTER) |
807 (1 << AC97_SLOT_PCM_SLEFT) |
808 (1 << AC97_SLOT_PCM_SRIGHT) |
809 (1 << AC97_SLOT_LFE),
810 },
811 },
812 },
813 [1] = { /* PCM in */
814 .stream = 1,
815 .exclusive = 1,
816 .r = {
817 [0] = {
818 .slots = (1 << AC97_SLOT_PCM_LEFT) |
819 (1 << AC97_SLOT_PCM_RIGHT),
820 },
821 },
822 },
823 [2] = { /* Mic in */
824 .stream = 1,
825 .exclusive = 1,
826 .r = {
827 [0] = {
828 .slots = (1 << AC97_SLOT_MIC),
829 },
830 },
831 }
832};
833
ceb9e476 834static struct snd_ac97_bus_ops aaci_bus_ops = {
cb5a6ffc
RK		 835 .write = aaci_ac97_write,
836 .read = aaci_ac97_read,
837};
838
839static int __devinit aaci_probe_ac97(struct aaci *aaci)
840{
ceb9e476
TI		 841 struct snd_ac97_template ac97_template;
842 struct snd_ac97_bus *ac97_bus;
843 struct snd_ac97 *ac97;
cb5a6ffc
RK		 844 int ret;
845
29a4f2d3 846 writel(0, aaci->base + AC97_POWERDOWN);
cb5a6ffc
RK		 847 /*
848 * Assert AACIRESET for 2us
849 */
850 writel(0, aaci->base + AACI_RESET);
851 udelay(2);
852 writel(RESET_NRST, aaci->base + AACI_RESET);
853
854 /*
855 * Give the AC'97 codec more than enough time
856 * to wake up. (42us = ~2 frames at 48kHz.)
857 */
858 udelay(42);
859
860 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
861 if (ret)
862 goto out;
863
864 ac97_bus->clock = 48000;
865 aaci->ac97_bus = ac97_bus;
866
ceb9e476 867 memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
cb5a6ffc
RK		 868 ac97_template.private_data = aaci;
869 ac97_template.num = 0;
870 ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
871
872 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
873 if (ret)
874 goto out;
41762b8c 875 aaci->ac97 = ac97;
cb5a6ffc
RK		 876
877 /*
878 * Disable AC97 PC Beep input on audio codecs.
879 */
880 if (ac97_is_audio(ac97))
881 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
882
883 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
884 if (ret)
885 goto out;
886
887 aaci->playback.pcm = &ac97_bus->pcms[0];
41762b8c 888 aaci->capture.pcm = &ac97_bus->pcms[1];
cb5a6ffc
RK		 889
890 out:
891 return ret;
892}
893
ceb9e476 894static void aaci_free_card(struct snd_card *card)
cb5a6ffc
RK		 895{
896 struct aaci *aaci = card->private_data;
897 if (aaci->base)
898 iounmap(aaci->base);
899}
900
901static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
902{
903 struct aaci *aaci;
ceb9e476 904 struct snd_card *card;
bd7dd77c 905 int err;
cb5a6ffc 906
bd7dd77c
TI		 907 err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
908 THIS_MODULE, sizeof(struct aaci), &card);
909 if (err < 0)
631e8ad4 910 return NULL;
cb5a6ffc
RK		 911
912 card->private_free = aaci_free_card;
cb5a6ffc
RK		 913
914 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
915 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
916 snprintf(card->longname, sizeof(card->longname),
aa0a2ddc
GKH		 917 "%s at 0x%016llx, irq %d",
918 card->shortname, (unsigned long long)dev->res.start,
919 dev->irq[0]);
cb5a6ffc
RK		 920
921 aaci = card->private_data;
12aa7579 922 mutex_init(&aaci->ac97_sem);
cb5a6ffc
RK		 923 spin_lock_init(&aaci->lock);
924 aaci->card = card;
925 aaci->dev = dev;
926
927 /* Set MAINCR to allow slot 1 and 2 data IO */
928 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
929 MAINCR_SL2RXEN | MAINCR_SL2TXEN;
930
931 return aaci;
932}
933
934static int __devinit aaci_init_pcm(struct aaci *aaci)
935{
ceb9e476 936 struct snd_pcm *pcm;
cb5a6ffc
RK		 937 int ret;
938
41762b8c 939 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
cb5a6ffc
RK		 940 if (ret == 0) {
941 aaci->pcm = pcm;
942 pcm->private_data = aaci;
943 pcm->info_flags = 0;
944
945 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
946
947 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
41762b8c 948 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
d6797322 949 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
d4946431 950 NULL, 0, 64 * 1024);
cb5a6ffc
RK		 951 }
952
953 return ret;
954}
955
956static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
957{
41762b8c 958 struct aaci_runtime *aacirun = &aaci->playback;
cb5a6ffc
RK		 959 int i;
960
41762b8c 961 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
cb5a6ffc 962
41762b8c
KH		 963 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
964 writel(0, aacirun->fifo);
cb5a6ffc 965
41762b8c 966 writel(0, aacirun->base + AACI_TXCR);
cb5a6ffc
RK		 967
968 /*
969 * Re-initialise the AACI after the FIFO depth test, to
970 * ensure that the FIFOs are empty. Unfortunately, merely
971 * disabling the channel doesn't clear the FIFO.
972 */
973 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
974 writel(aaci->maincr, aaci->base + AACI_MAINCR);
975
976 /*
977 * If we hit 4096, we failed. Go back to the specified
978 * fifo depth.
979 */
980 if (i == 4096)
981 i = 8;
982
983 return i;
984}
985
03fbdb15 986static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
cb5a6ffc
RK		 987{
988 struct aaci *aaci;
989 int ret, i;
990
991 ret = amba_request_regions(dev, NULL);
992 if (ret)
993 return ret;
994
995 aaci = aaci_init_card(dev);
631e8ad4
TI		 996 if (!aaci) {
997 ret = -ENOMEM;
cb5a6ffc
RK		 998 goto out;
999 }
1000
dc890c2d 1001 aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
cb5a6ffc
RK		 1002 if (!aaci->base) {
1003 ret = -ENOMEM;
1004 goto out;
1005 }
1006
1007 /*
1008 * Playback uses AACI channel 0
1009 */
1010 aaci->playback.base = aaci->base + AACI_CSCH1;
1011 aaci->playback.fifo = aaci->base + AACI_DR1;
1012
41762b8c
KH		 1013 /*
1014 * Capture uses AACI channel 0
1015 */
1016 aaci->capture.base = aaci->base + AACI_CSCH1;
1017 aaci->capture.fifo = aaci->base + AACI_DR1;
1018
cb5a6ffc 1019 for (i = 0; i < 4; i++) {
e12ba644 1020 void __iomem *base = aaci->base + i * 0x14;
cb5a6ffc
RK		 1021
1022 writel(0, base + AACI_IE);
1023 writel(0, base + AACI_TXCR);
1024 writel(0, base + AACI_RXCR);
1025 }
1026
1027 writel(0x1fff, aaci->base + AACI_INTCLR);
1028 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1029
f27f218c
CM		 1030 ret = aaci_probe_ac97(aaci);
1031 if (ret)
1032 goto out;
1033
cb5a6ffc 1034 /*
f27f218c 1035 * Size the FIFOs (must be multiple of 16).
cb5a6ffc
RK		 1036 */
1037 aaci->fifosize = aaci_size_fifo(aaci);
f27f218c
CM		 1038 if (aaci->fifosize & 15) {
1039 printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
1040 aaci->fifosize);
1041 ret = -ENODEV;
cb5a6ffc 1042 goto out;
f27f218c 1043 }
cb5a6ffc
RK		 1044
1045 ret = aaci_init_pcm(aaci);
1046 if (ret)
1047 goto out;
1048
a76af199
TI		 1049 snd_card_set_dev(aaci->card, &dev->dev);
1050
cb5a6ffc
RK		 1051 ret = snd_card_register(aaci->card);
1052 if (ret == 0) {
1053 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
41762b8c 1054 aaci->fifosize);
cb5a6ffc
RK		 1055 amba_set_drvdata(dev, aaci->card);
1056 return ret;
1057 }
1058
1059 out:
1060 if (aaci)
1061 snd_card_free(aaci->card);
1062 amba_release_regions(dev);
1063 return ret;
1064}
1065
1066static int __devexit aaci_remove(struct amba_device *dev)
1067{
ceb9e476 1068 struct snd_card *card = amba_get_drvdata(dev);
cb5a6ffc
RK		 1069
1070 amba_set_drvdata(dev, NULL);
1071
1072 if (card) {
1073 struct aaci *aaci = card->private_data;
1074 writel(0, aaci->base + AACI_MAINCR);
1075
1076 snd_card_free(card);
1077 amba_release_regions(dev);
1078 }
1079
1080 return 0;
1081}
1082
1083static struct amba_id aaci_ids[] = {
1084 {
1085 .id = 0x00041041,
1086 .mask = 0x000fffff,
1087 },
1088 { 0, 0 },
1089};
1090
1091static struct amba_driver aaci_driver = {
1092 .drv = {
1093 .name = DRIVER_NAME,
1094 },
1095 .probe = aaci_probe,
1096 .remove = __devexit_p(aaci_remove),
1097 .suspend = aaci_suspend,
1098 .resume = aaci_resume,
1099 .id_table = aaci_ids,
1100};
1101
1102static int __init aaci_init(void)
1103{
1104 return amba_driver_register(&aaci_driver);
1105}
1106
1107static void __exit aaci_exit(void)
1108{
1109 amba_driver_unregister(&aaci_driver);
1110}
1111
1112module_init(aaci_init);
1113module_exit(aaci_exit);
1114
1115MODULE_LICENSE("GPL");
1116MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
Linux kernel - Deliverables
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