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cb5a6ffc RK |
1 | /* |
2 | * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Documentation: ARM DDI 0173B | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/err.h> | |
a62c80e5 | 20 | #include <linux/amba/bus.h> |
88cdca9c | 21 | #include <linux/io.h> |
cb5a6ffc | 22 | |
cb5a6ffc RK |
23 | #include <sound/core.h> |
24 | #include <sound/initval.h> | |
25 | #include <sound/ac97_codec.h> | |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | ||
29 | #include "aaci.h" | |
cb5a6ffc RK |
30 | |
31 | #define DRIVER_NAME "aaci-pl041" | |
32 | ||
250c7a61 RK |
33 | #define FRAME_PERIOD_US 21 |
34 | ||
cb5a6ffc RK |
35 | /* |
36 | * PM support is not complete. Turn it off. | |
37 | */ | |
38 | #undef CONFIG_PM | |
39 | ||
ceb9e476 | 40 | static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) |
cb5a6ffc RK |
41 | { |
42 | u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); | |
43 | ||
44 | /* | |
45 | * Ensure that the slot 1/2 RX registers are empty. | |
46 | */ | |
47 | v = readl(aaci->base + AACI_SLFR); | |
48 | if (v & SLFR_2RXV) | |
49 | readl(aaci->base + AACI_SL2RX); | |
50 | if (v & SLFR_1RXV) | |
51 | readl(aaci->base + AACI_SL1RX); | |
52 | ||
53 | writel(maincr, aaci->base + AACI_MAINCR); | |
54 | } | |
55 | ||
56 | /* | |
57 | * P29: | |
58 | * The recommended use of programming the external codec through slot 1 | |
59 | * and slot 2 data is to use the channels during setup routines and the | |
60 | * slot register at any other time. The data written into slot 1, slot 2 | |
61 | * and slot 12 registers is transmitted only when their corresponding | |
62 | * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR | |
63 | * register. | |
64 | */ | |
14d178a1 KH |
65 | static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
66 | unsigned short val) | |
cb5a6ffc RK |
67 | { |
68 | struct aaci *aaci = ac97->private_data; | |
250c7a61 | 69 | int timeout; |
cb5a6ffc RK |
70 | u32 v; |
71 | ||
72 | if (ac97->num >= 4) | |
73 | return; | |
74 | ||
12aa7579 | 75 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
76 | |
77 | aaci_ac97_select_codec(aaci, ac97); | |
78 | ||
79 | /* | |
80 | * P54: You must ensure that AACI_SL2TX is always written | |
81 | * to, if required, before data is written to AACI_SL1TX. | |
82 | */ | |
83 | writel(val << 4, aaci->base + AACI_SL2TX); | |
84 | writel(reg << 12, aaci->base + AACI_SL1TX); | |
85 | ||
250c7a61 RK |
86 | /* Initially, wait one frame period */ |
87 | udelay(FRAME_PERIOD_US); | |
88 | ||
89 | /* And then wait an additional eight frame periods for it to be sent */ | |
90 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 91 | do { |
250c7a61 | 92 | udelay(1); |
cb5a6ffc | 93 | v = readl(aaci->base + AACI_SLFR); |
f6f35bbe | 94 | } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); |
14d178a1 | 95 | |
69058cd6 | 96 | if (v & (SLFR_1TXB|SLFR_2TXB)) |
14d178a1 KH |
97 | dev_err(&aaci->dev->dev, |
98 | "timeout waiting for write to complete\n"); | |
cb5a6ffc | 99 | |
12aa7579 | 100 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
101 | } |
102 | ||
103 | /* | |
104 | * Read an AC'97 register. | |
105 | */ | |
ceb9e476 | 106 | static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
cb5a6ffc RK |
107 | { |
108 | struct aaci *aaci = ac97->private_data; | |
250c7a61 | 109 | int timeout, retries = 10; |
cb5a6ffc RK |
110 | u32 v; |
111 | ||
112 | if (ac97->num >= 4) | |
113 | return ~0; | |
114 | ||
12aa7579 | 115 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
116 | |
117 | aaci_ac97_select_codec(aaci, ac97); | |
118 | ||
119 | /* | |
120 | * Write the register address to slot 1. | |
121 | */ | |
122 | writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); | |
123 | ||
250c7a61 RK |
124 | /* Initially, wait one frame period */ |
125 | udelay(FRAME_PERIOD_US); | |
126 | ||
127 | /* And then wait an additional eight frame periods for it to be sent */ | |
128 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 129 | do { |
250c7a61 | 130 | udelay(1); |
cb5a6ffc | 131 | v = readl(aaci->base + AACI_SLFR); |
f6f35bbe | 132 | } while ((v & SLFR_1TXB) && --timeout); |
14d178a1 | 133 | |
69058cd6 | 134 | if (v & SLFR_1TXB) { |
14d178a1 KH |
135 | dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); |
136 | v = ~0; | |
137 | goto out; | |
138 | } | |
cb5a6ffc | 139 | |
250c7a61 RK |
140 | /* Now wait for the response frame */ |
141 | udelay(FRAME_PERIOD_US); | |
cb5a6ffc | 142 | |
250c7a61 RK |
143 | /* And then wait an additional eight frame periods for data */ |
144 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 145 | do { |
250c7a61 | 146 | udelay(1); |
cb5a6ffc RK |
147 | cond_resched(); |
148 | v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); | |
f6f35bbe | 149 | } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); |
cb5a6ffc | 150 | |
69058cd6 | 151 | if (v != (SLFR_1RXV|SLFR_2RXV)) { |
14d178a1 | 152 | dev_err(&aaci->dev->dev, "timeout on RX valid\n"); |
cb5a6ffc | 153 | v = ~0; |
14d178a1 | 154 | goto out; |
cb5a6ffc RK |
155 | } |
156 | ||
14d178a1 KH |
157 | do { |
158 | v = readl(aaci->base + AACI_SL1RX) >> 12; | |
159 | if (v == reg) { | |
160 | v = readl(aaci->base + AACI_SL2RX) >> 4; | |
161 | break; | |
162 | } else if (--retries) { | |
163 | dev_warn(&aaci->dev->dev, | |
164 | "ac97 read back fail. retry\n"); | |
165 | continue; | |
166 | } else { | |
167 | dev_warn(&aaci->dev->dev, | |
168 | "wrong ac97 register read back (%x != %x)\n", | |
169 | v, reg); | |
170 | v = ~0; | |
171 | } | |
172 | } while (retries); | |
173 | out: | |
12aa7579 | 174 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
175 | return v; |
176 | } | |
177 | ||
d6a89fef RK |
178 | static inline void |
179 | aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) | |
cb5a6ffc RK |
180 | { |
181 | u32 val; | |
182 | int timeout = 5000; | |
183 | ||
184 | do { | |
250c7a61 | 185 | udelay(1); |
cb5a6ffc | 186 | val = readl(aacirun->base + AACI_SR); |
d6a89fef | 187 | } while (val & mask && timeout--); |
cb5a6ffc RK |
188 | } |
189 | ||
190 | ||
191 | ||
192 | /* | |
193 | * Interrupt support. | |
194 | */ | |
62578cbf | 195 | static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) |
cb5a6ffc | 196 | { |
41762b8c KH |
197 | if (mask & ISR_ORINTR) { |
198 | dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); | |
199 | writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); | |
200 | } | |
201 | ||
202 | if (mask & ISR_RXTOINTR) { | |
203 | dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); | |
204 | writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); | |
205 | } | |
206 | ||
207 | if (mask & ISR_RXINTR) { | |
208 | struct aaci_runtime *aacirun = &aaci->capture; | |
ea51d0b1 | 209 | bool period_elapsed = false; |
41762b8c KH |
210 | void *ptr; |
211 | ||
212 | if (!aacirun->substream || !aacirun->start) { | |
898eb71c | 213 | dev_warn(&aaci->dev->dev, "RX interrupt???\n"); |
41762b8c KH |
214 | writel(0, aacirun->base + AACI_IE); |
215 | return; | |
216 | } | |
41762b8c | 217 | |
d6a89fef RK |
218 | spin_lock(&aacirun->lock); |
219 | ||
220 | ptr = aacirun->ptr; | |
41762b8c KH |
221 | do { |
222 | unsigned int len = aacirun->fifosz; | |
223 | u32 val; | |
224 | ||
225 | if (aacirun->bytes <= 0) { | |
226 | aacirun->bytes += aacirun->period; | |
ea51d0b1 | 227 | period_elapsed = true; |
41762b8c KH |
228 | } |
229 | if (!(aacirun->cr & CR_EN)) | |
230 | break; | |
231 | ||
232 | val = readl(aacirun->base + AACI_SR); | |
233 | if (!(val & SR_RXHF)) | |
234 | break; | |
235 | if (!(val & SR_RXFF)) | |
236 | len >>= 1; | |
237 | ||
238 | aacirun->bytes -= len; | |
239 | ||
240 | /* reading 16 bytes at a time */ | |
241 | for( ; len > 0; len -= 16) { | |
242 | asm( | |
243 | "ldmia %1, {r0, r1, r2, r3}\n\t" | |
244 | "stmia %0!, {r0, r1, r2, r3}" | |
245 | : "+r" (ptr) | |
246 | : "r" (aacirun->fifo) | |
247 | : "r0", "r1", "r2", "r3", "cc"); | |
248 | ||
249 | if (ptr >= aacirun->end) | |
250 | ptr = aacirun->start; | |
251 | } | |
252 | } while(1); | |
d6a89fef | 253 | |
41762b8c | 254 | aacirun->ptr = ptr; |
d6a89fef RK |
255 | |
256 | spin_unlock(&aacirun->lock); | |
ea51d0b1 RK |
257 | |
258 | if (period_elapsed) | |
259 | snd_pcm_period_elapsed(aacirun->substream); | |
41762b8c KH |
260 | } |
261 | ||
cb5a6ffc | 262 | if (mask & ISR_URINTR) { |
62578cbf KH |
263 | dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); |
264 | writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); | |
cb5a6ffc RK |
265 | } |
266 | ||
267 | if (mask & ISR_TXINTR) { | |
268 | struct aaci_runtime *aacirun = &aaci->playback; | |
ea51d0b1 | 269 | bool period_elapsed = false; |
cb5a6ffc RK |
270 | void *ptr; |
271 | ||
272 | if (!aacirun->substream || !aacirun->start) { | |
898eb71c | 273 | dev_warn(&aaci->dev->dev, "TX interrupt???\n"); |
cb5a6ffc RK |
274 | writel(0, aacirun->base + AACI_IE); |
275 | return; | |
276 | } | |
277 | ||
d6a89fef RK |
278 | spin_lock(&aacirun->lock); |
279 | ||
cb5a6ffc RK |
280 | ptr = aacirun->ptr; |
281 | do { | |
282 | unsigned int len = aacirun->fifosz; | |
283 | u32 val; | |
284 | ||
285 | if (aacirun->bytes <= 0) { | |
286 | aacirun->bytes += aacirun->period; | |
ea51d0b1 | 287 | period_elapsed = true; |
cb5a6ffc | 288 | } |
41762b8c | 289 | if (!(aacirun->cr & CR_EN)) |
cb5a6ffc RK |
290 | break; |
291 | ||
292 | val = readl(aacirun->base + AACI_SR); | |
293 | if (!(val & SR_TXHE)) | |
294 | break; | |
295 | if (!(val & SR_TXFE)) | |
296 | len >>= 1; | |
297 | ||
298 | aacirun->bytes -= len; | |
299 | ||
300 | /* writing 16 bytes at a time */ | |
301 | for ( ; len > 0; len -= 16) { | |
302 | asm( | |
303 | "ldmia %0!, {r0, r1, r2, r3}\n\t" | |
304 | "stmia %1, {r0, r1, r2, r3}" | |
305 | : "+r" (ptr) | |
306 | : "r" (aacirun->fifo) | |
307 | : "r0", "r1", "r2", "r3", "cc"); | |
308 | ||
309 | if (ptr >= aacirun->end) | |
310 | ptr = aacirun->start; | |
311 | } | |
312 | } while (1); | |
313 | ||
314 | aacirun->ptr = ptr; | |
d6a89fef RK |
315 | |
316 | spin_unlock(&aacirun->lock); | |
ea51d0b1 RK |
317 | |
318 | if (period_elapsed) | |
319 | snd_pcm_period_elapsed(aacirun->substream); | |
cb5a6ffc RK |
320 | } |
321 | } | |
322 | ||
7d12e780 | 323 | static irqreturn_t aaci_irq(int irq, void *devid) |
cb5a6ffc RK |
324 | { |
325 | struct aaci *aaci = devid; | |
326 | u32 mask; | |
327 | int i; | |
328 | ||
cb5a6ffc RK |
329 | mask = readl(aaci->base + AACI_ALLINTS); |
330 | if (mask) { | |
331 | u32 m = mask; | |
332 | for (i = 0; i < 4; i++, m >>= 7) { | |
333 | if (m & 0x7f) { | |
62578cbf | 334 | aaci_fifo_irq(aaci, i, m); |
cb5a6ffc RK |
335 | } |
336 | } | |
337 | } | |
cb5a6ffc RK |
338 | |
339 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
340 | } | |
341 | ||
342 | ||
343 | ||
344 | /* | |
345 | * ALSA support. | |
346 | */ | |
ceb9e476 | 347 | static struct snd_pcm_hardware aaci_hw_info = { |
cb5a6ffc RK |
348 | .info = SNDRV_PCM_INFO_MMAP | |
349 | SNDRV_PCM_INFO_MMAP_VALID | | |
350 | SNDRV_PCM_INFO_INTERLEAVED | | |
351 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
352 | SNDRV_PCM_INFO_RESUME, | |
353 | ||
354 | /* | |
355 | * ALSA doesn't support 18-bit or 20-bit packed into 32-bit | |
356 | * words. It also doesn't support 12-bit at all. | |
357 | */ | |
358 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
359 | ||
6ca867c8 | 360 | /* rates are setup from the AC'97 codec */ |
cb5a6ffc | 361 | .channels_min = 2, |
e831d80b | 362 | .channels_max = 2, |
cb5a6ffc RK |
363 | .buffer_bytes_max = 64 * 1024, |
364 | .period_bytes_min = 256, | |
365 | .period_bytes_max = PAGE_SIZE, | |
366 | .periods_min = 4, | |
367 | .periods_max = PAGE_SIZE / 16, | |
368 | }; | |
369 | ||
e831d80b RK |
370 | /* |
371 | * We can support two and four channel audio. Unfortunately | |
372 | * six channel audio requires a non-standard channel ordering: | |
373 | * 2 -> FL(3), FR(4) | |
374 | * 4 -> FL(3), FR(4), SL(7), SR(8) | |
375 | * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) | |
376 | * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) | |
377 | * This requires an ALSA configuration file to correct. | |
378 | */ | |
379 | static int aaci_rule_channels(struct snd_pcm_hw_params *p, | |
380 | struct snd_pcm_hw_rule *rule) | |
381 | { | |
382 | static unsigned int channel_list[] = { 2, 4, 6 }; | |
383 | struct aaci *aaci = rule->private; | |
384 | unsigned int mask = 1 << 0, slots; | |
385 | ||
386 | /* pcms[0] is the our 5.1 PCM instance. */ | |
387 | slots = aaci->ac97_bus->pcms[0].r[0].slots; | |
388 | if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
389 | mask |= 1 << 1; | |
390 | if (slots & (1 << AC97_SLOT_LFE)) | |
391 | mask |= 1 << 2; | |
392 | } | |
393 | ||
394 | return snd_interval_list(hw_param_interval(p, rule->var), | |
395 | ARRAY_SIZE(channel_list), channel_list, mask); | |
396 | } | |
397 | ||
398 | static int aaci_pcm_open(struct snd_pcm_substream *substream) | |
cb5a6ffc | 399 | { |
ceb9e476 | 400 | struct snd_pcm_runtime *runtime = substream->runtime; |
e831d80b RK |
401 | struct aaci *aaci = substream->private_data; |
402 | struct aaci_runtime *aacirun; | |
b60fb519 | 403 | int ret = 0; |
cb5a6ffc | 404 | |
e831d80b RK |
405 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
406 | aacirun = &aaci->playback; | |
407 | } else { | |
408 | aacirun = &aaci->capture; | |
409 | } | |
410 | ||
cb5a6ffc RK |
411 | aacirun->substream = substream; |
412 | runtime->private_data = aacirun; | |
413 | runtime->hw = aaci_hw_info; | |
6ca867c8 RK |
414 | runtime->hw.rates = aacirun->pcm->rates; |
415 | snd_pcm_limit_hw_rates(runtime); | |
cb5a6ffc | 416 | |
e831d80b RK |
417 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
418 | runtime->hw.channels_max = 6; | |
419 | ||
420 | /* Add rule describing channel dependency. */ | |
421 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
422 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
423 | aaci_rule_channels, aaci, | |
424 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
425 | if (ret) | |
426 | return ret; | |
427 | ||
428 | if (aacirun->pcm->r[1].slots) | |
429 | snd_ac97_pcm_double_rate_rules(runtime); | |
430 | } | |
a08d5658 | 431 | |
cb5a6ffc RK |
432 | /* |
433 | * FIXME: ALSA specifies fifo_size in bytes. If we're in normal | |
434 | * mode, each 32-bit word contains one sample. If we're in | |
435 | * compact mode, each 32-bit word contains two samples, effectively | |
436 | * halving the FIFO size. However, we don't know for sure which | |
437 | * we'll be using at this point. We set this to the lower limit. | |
438 | */ | |
439 | runtime->hw.fifo_size = aaci->fifosize * 2; | |
440 | ||
b60fb519 RK |
441 | mutex_lock(&aaci->irq_lock); |
442 | if (!aaci->users++) { | |
443 | ret = request_irq(aaci->dev->irq[0], aaci_irq, | |
444 | IRQF_SHARED | IRQF_DISABLED, DRIVER_NAME, aaci); | |
445 | if (ret != 0) | |
446 | aaci->users--; | |
447 | } | |
448 | mutex_unlock(&aaci->irq_lock); | |
cb5a6ffc | 449 | |
cb5a6ffc RK |
450 | return ret; |
451 | } | |
452 | ||
453 | ||
454 | /* | |
455 | * Common ALSA stuff | |
456 | */ | |
ceb9e476 | 457 | static int aaci_pcm_close(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
458 | { |
459 | struct aaci *aaci = substream->private_data; | |
460 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
461 | ||
41762b8c | 462 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
463 | |
464 | aacirun->substream = NULL; | |
b60fb519 RK |
465 | |
466 | mutex_lock(&aaci->irq_lock); | |
467 | if (!--aaci->users) | |
468 | free_irq(aaci->dev->irq[0], aaci); | |
469 | mutex_unlock(&aaci->irq_lock); | |
cb5a6ffc RK |
470 | |
471 | return 0; | |
472 | } | |
473 | ||
ceb9e476 | 474 | static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
475 | { |
476 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
477 | ||
478 | /* | |
479 | * This must not be called with the device enabled. | |
480 | */ | |
41762b8c | 481 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
482 | |
483 | if (aacirun->pcm_open) | |
484 | snd_ac97_pcm_close(aacirun->pcm); | |
485 | aacirun->pcm_open = 0; | |
486 | ||
487 | /* | |
488 | * Clear out the DMA and any allocated buffers. | |
489 | */ | |
d6797322 | 490 | snd_pcm_lib_free_pages(substream); |
cb5a6ffc RK |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
58e8a474 RK |
495 | /* Channel to slot mask */ |
496 | static const u32 channels_to_slotmask[] = { | |
497 | [2] = CR_SL3 | CR_SL4, | |
498 | [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, | |
499 | [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, | |
500 | }; | |
501 | ||
ceb9e476 | 502 | static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, |
ceb9e476 | 503 | struct snd_pcm_hw_params *params) |
cb5a6ffc | 504 | { |
58e8a474 RK |
505 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
506 | unsigned int channels = params_channels(params); | |
507 | unsigned int rate = params_rate(params); | |
508 | int dbl = rate > 48000; | |
cb5a6ffc RK |
509 | int err; |
510 | ||
511 | aaci_pcm_hw_free(substream); | |
4acd57c3 RK |
512 | if (aacirun->pcm_open) { |
513 | snd_ac97_pcm_close(aacirun->pcm); | |
514 | aacirun->pcm_open = 0; | |
515 | } | |
cb5a6ffc | 516 | |
58e8a474 RK |
517 | /* channels is already limited to 2, 4, or 6 by aaci_rule_channels */ |
518 | if (dbl && channels != 2) | |
519 | return -EINVAL; | |
520 | ||
d6797322 TI |
521 | err = snd_pcm_lib_malloc_pages(substream, |
522 | params_buffer_bytes(params)); | |
4e30b691 | 523 | if (err >= 0) { |
58e8a474 | 524 | struct aaci *aaci = substream->private_data; |
a08d5658 | 525 | |
58e8a474 | 526 | err = snd_ac97_pcm_open(aacirun->pcm, rate, channels, |
a08d5658 | 527 | aacirun->pcm->r[dbl].slots); |
cb5a6ffc | 528 | |
4e30b691 | 529 | aacirun->pcm_open = err == 0; |
d3aee799 | 530 | aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; |
58e8a474 | 531 | aacirun->cr |= channels_to_slotmask[channels + dbl * 2]; |
d3aee799 RK |
532 | aacirun->fifosz = aaci->fifosize * 4; |
533 | ||
534 | if (aacirun->cr & CR_COMPACT) | |
535 | aacirun->fifosz >>= 1; | |
4e30b691 | 536 | } |
cb5a6ffc | 537 | |
cb5a6ffc RK |
538 | return err; |
539 | } | |
540 | ||
ceb9e476 | 541 | static int aaci_pcm_prepare(struct snd_pcm_substream *substream) |
cb5a6ffc | 542 | { |
ceb9e476 | 543 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
544 | struct aaci_runtime *aacirun = runtime->private_data; |
545 | ||
c0dea82c | 546 | aacirun->period = snd_pcm_lib_period_bytes(substream); |
4e30b691 | 547 | aacirun->start = runtime->dma_area; |
88cdca9c | 548 | aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream); |
cb5a6ffc | 549 | aacirun->ptr = aacirun->start; |
c0dea82c | 550 | aacirun->bytes = aacirun->period; |
cb5a6ffc RK |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
ceb9e476 | 555 | static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) |
cb5a6ffc | 556 | { |
ceb9e476 | 557 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
558 | struct aaci_runtime *aacirun = runtime->private_data; |
559 | ssize_t bytes = aacirun->ptr - aacirun->start; | |
560 | ||
561 | return bytes_to_frames(runtime, bytes); | |
562 | } | |
563 | ||
cb5a6ffc RK |
564 | |
565 | /* | |
566 | * Playback specific ALSA stuff | |
567 | */ | |
cb5a6ffc RK |
568 | static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) |
569 | { | |
570 | u32 ie; | |
571 | ||
572 | ie = readl(aacirun->base + AACI_IE); | |
573 | ie &= ~(IE_URIE|IE_TXIE); | |
574 | writel(ie, aacirun->base + AACI_IE); | |
41762b8c | 575 | aacirun->cr &= ~CR_EN; |
d6a89fef | 576 | aaci_chan_wait_ready(aacirun, SR_TXB); |
cb5a6ffc RK |
577 | writel(aacirun->cr, aacirun->base + AACI_TXCR); |
578 | } | |
579 | ||
580 | static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) | |
581 | { | |
582 | u32 ie; | |
583 | ||
d6a89fef | 584 | aaci_chan_wait_ready(aacirun, SR_TXB); |
41762b8c | 585 | aacirun->cr |= CR_EN; |
cb5a6ffc RK |
586 | |
587 | ie = readl(aacirun->base + AACI_IE); | |
588 | ie |= IE_URIE | IE_TXIE; | |
589 | writel(ie, aacirun->base + AACI_IE); | |
590 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
591 | } | |
592 | ||
ceb9e476 | 593 | static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
cb5a6ffc | 594 | { |
cb5a6ffc RK |
595 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
596 | unsigned long flags; | |
597 | int ret = 0; | |
598 | ||
d6a89fef RK |
599 | spin_lock_irqsave(&aacirun->lock, flags); |
600 | ||
cb5a6ffc RK |
601 | switch (cmd) { |
602 | case SNDRV_PCM_TRIGGER_START: | |
603 | aaci_pcm_playback_start(aacirun); | |
604 | break; | |
605 | ||
606 | case SNDRV_PCM_TRIGGER_RESUME: | |
607 | aaci_pcm_playback_start(aacirun); | |
608 | break; | |
609 | ||
610 | case SNDRV_PCM_TRIGGER_STOP: | |
611 | aaci_pcm_playback_stop(aacirun); | |
612 | break; | |
613 | ||
614 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
615 | aaci_pcm_playback_stop(aacirun); | |
616 | break; | |
617 | ||
618 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
619 | break; | |
620 | ||
621 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
622 | break; | |
623 | ||
624 | default: | |
625 | ret = -EINVAL; | |
626 | } | |
d6a89fef RK |
627 | |
628 | spin_unlock_irqrestore(&aacirun->lock, flags); | |
cb5a6ffc RK |
629 | |
630 | return ret; | |
631 | } | |
632 | ||
ceb9e476 | 633 | static struct snd_pcm_ops aaci_playback_ops = { |
41762b8c | 634 | .open = aaci_pcm_open, |
cb5a6ffc RK |
635 | .close = aaci_pcm_close, |
636 | .ioctl = snd_pcm_lib_ioctl, | |
58e8a474 | 637 | .hw_params = aaci_pcm_hw_params, |
cb5a6ffc RK |
638 | .hw_free = aaci_pcm_hw_free, |
639 | .prepare = aaci_pcm_prepare, | |
640 | .trigger = aaci_pcm_playback_trigger, | |
641 | .pointer = aaci_pcm_pointer, | |
cb5a6ffc RK |
642 | }; |
643 | ||
41762b8c KH |
644 | static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) |
645 | { | |
646 | u32 ie; | |
647 | ||
d6a89fef | 648 | aaci_chan_wait_ready(aacirun, SR_RXB); |
41762b8c KH |
649 | |
650 | ie = readl(aacirun->base + AACI_IE); | |
651 | ie &= ~(IE_ORIE | IE_RXIE); | |
652 | writel(ie, aacirun->base+AACI_IE); | |
653 | ||
654 | aacirun->cr &= ~CR_EN; | |
cb5a6ffc | 655 | |
41762b8c KH |
656 | writel(aacirun->cr, aacirun->base + AACI_RXCR); |
657 | } | |
658 | ||
659 | static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) | |
660 | { | |
661 | u32 ie; | |
662 | ||
d6a89fef | 663 | aaci_chan_wait_ready(aacirun, SR_RXB); |
41762b8c KH |
664 | |
665 | #ifdef DEBUG | |
666 | /* RX Timeout value: bits 28:17 in RXCR */ | |
667 | aacirun->cr |= 0xf << 17; | |
668 | #endif | |
669 | ||
670 | aacirun->cr |= CR_EN; | |
671 | writel(aacirun->cr, aacirun->base + AACI_RXCR); | |
672 | ||
673 | ie = readl(aacirun->base + AACI_IE); | |
674 | ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full | |
675 | writel(ie, aacirun->base + AACI_IE); | |
676 | } | |
677 | ||
8a371840 RK |
678 | static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) |
679 | { | |
41762b8c KH |
680 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
681 | unsigned long flags; | |
682 | int ret = 0; | |
683 | ||
d6a89fef | 684 | spin_lock_irqsave(&aacirun->lock, flags); |
41762b8c KH |
685 | |
686 | switch (cmd) { | |
687 | case SNDRV_PCM_TRIGGER_START: | |
688 | aaci_pcm_capture_start(aacirun); | |
689 | break; | |
690 | ||
691 | case SNDRV_PCM_TRIGGER_RESUME: | |
692 | aaci_pcm_capture_start(aacirun); | |
693 | break; | |
694 | ||
695 | case SNDRV_PCM_TRIGGER_STOP: | |
696 | aaci_pcm_capture_stop(aacirun); | |
697 | break; | |
698 | ||
699 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
700 | aaci_pcm_capture_stop(aacirun); | |
701 | break; | |
702 | ||
703 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
704 | break; | |
705 | ||
706 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
707 | break; | |
708 | ||
709 | default: | |
710 | ret = -EINVAL; | |
711 | } | |
712 | ||
d6a89fef | 713 | spin_unlock_irqrestore(&aacirun->lock, flags); |
41762b8c KH |
714 | |
715 | return ret; | |
716 | } | |
717 | ||
8a371840 | 718 | static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) |
41762b8c KH |
719 | { |
720 | struct snd_pcm_runtime *runtime = substream->runtime; | |
721 | struct aaci *aaci = substream->private_data; | |
722 | ||
723 | aaci_pcm_prepare(substream); | |
724 | ||
725 | /* allow changing of sample rate */ | |
726 | aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ | |
727 | aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); | |
728 | aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); | |
729 | ||
730 | /* Record select: Mic: 0, Aux: 3, Line: 4 */ | |
731 | aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
8a371840 | 736 | static struct snd_pcm_ops aaci_capture_ops = { |
41762b8c KH |
737 | .open = aaci_pcm_open, |
738 | .close = aaci_pcm_close, | |
739 | .ioctl = snd_pcm_lib_ioctl, | |
58e8a474 | 740 | .hw_params = aaci_pcm_hw_params, |
41762b8c KH |
741 | .hw_free = aaci_pcm_hw_free, |
742 | .prepare = aaci_pcm_capture_prepare, | |
743 | .trigger = aaci_pcm_capture_trigger, | |
744 | .pointer = aaci_pcm_pointer, | |
41762b8c | 745 | }; |
cb5a6ffc RK |
746 | |
747 | /* | |
748 | * Power Management. | |
749 | */ | |
750 | #ifdef CONFIG_PM | |
ceb9e476 | 751 | static int aaci_do_suspend(struct snd_card *card, unsigned int state) |
cb5a6ffc RK |
752 | { |
753 | struct aaci *aaci = card->private_data; | |
792a6c51 TI |
754 | snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); |
755 | snd_pcm_suspend_all(aaci->pcm); | |
cb5a6ffc RK |
756 | return 0; |
757 | } | |
758 | ||
ceb9e476 | 759 | static int aaci_do_resume(struct snd_card *card, unsigned int state) |
cb5a6ffc | 760 | { |
792a6c51 | 761 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
cb5a6ffc RK |
762 | return 0; |
763 | } | |
764 | ||
e36d394d | 765 | static int aaci_suspend(struct amba_device *dev, pm_message_t state) |
cb5a6ffc | 766 | { |
ceb9e476 | 767 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
768 | return card ? aaci_do_suspend(card) : 0; |
769 | } | |
770 | ||
771 | static int aaci_resume(struct amba_device *dev) | |
772 | { | |
ceb9e476 | 773 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
774 | return card ? aaci_do_resume(card) : 0; |
775 | } | |
776 | #else | |
777 | #define aaci_do_suspend NULL | |
778 | #define aaci_do_resume NULL | |
779 | #define aaci_suspend NULL | |
780 | #define aaci_resume NULL | |
781 | #endif | |
782 | ||
783 | ||
784 | static struct ac97_pcm ac97_defs[] __devinitdata = { | |
41762b8c | 785 | [0] = { /* Front PCM */ |
cb5a6ffc RK |
786 | .exclusive = 1, |
787 | .r = { | |
788 | [0] = { | |
789 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
790 | (1 << AC97_SLOT_PCM_RIGHT) | | |
791 | (1 << AC97_SLOT_PCM_CENTER) | | |
792 | (1 << AC97_SLOT_PCM_SLEFT) | | |
793 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
794 | (1 << AC97_SLOT_LFE), | |
795 | }, | |
a08d5658 RK |
796 | [1] = { |
797 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
798 | (1 << AC97_SLOT_PCM_RIGHT) | | |
799 | (1 << AC97_SLOT_PCM_LEFT_0) | | |
800 | (1 << AC97_SLOT_PCM_RIGHT_0), | |
801 | }, | |
cb5a6ffc RK |
802 | }, |
803 | }, | |
804 | [1] = { /* PCM in */ | |
805 | .stream = 1, | |
806 | .exclusive = 1, | |
807 | .r = { | |
808 | [0] = { | |
809 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
810 | (1 << AC97_SLOT_PCM_RIGHT), | |
811 | }, | |
812 | }, | |
813 | }, | |
814 | [2] = { /* Mic in */ | |
815 | .stream = 1, | |
816 | .exclusive = 1, | |
817 | .r = { | |
818 | [0] = { | |
819 | .slots = (1 << AC97_SLOT_MIC), | |
820 | }, | |
821 | }, | |
822 | } | |
823 | }; | |
824 | ||
ceb9e476 | 825 | static struct snd_ac97_bus_ops aaci_bus_ops = { |
cb5a6ffc RK |
826 | .write = aaci_ac97_write, |
827 | .read = aaci_ac97_read, | |
828 | }; | |
829 | ||
830 | static int __devinit aaci_probe_ac97(struct aaci *aaci) | |
831 | { | |
ceb9e476 TI |
832 | struct snd_ac97_template ac97_template; |
833 | struct snd_ac97_bus *ac97_bus; | |
834 | struct snd_ac97 *ac97; | |
cb5a6ffc RK |
835 | int ret; |
836 | ||
837 | /* | |
838 | * Assert AACIRESET for 2us | |
839 | */ | |
840 | writel(0, aaci->base + AACI_RESET); | |
841 | udelay(2); | |
842 | writel(RESET_NRST, aaci->base + AACI_RESET); | |
843 | ||
844 | /* | |
845 | * Give the AC'97 codec more than enough time | |
846 | * to wake up. (42us = ~2 frames at 48kHz.) | |
847 | */ | |
250c7a61 | 848 | udelay(FRAME_PERIOD_US * 2); |
cb5a6ffc RK |
849 | |
850 | ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); | |
851 | if (ret) | |
852 | goto out; | |
853 | ||
854 | ac97_bus->clock = 48000; | |
855 | aaci->ac97_bus = ac97_bus; | |
856 | ||
ceb9e476 | 857 | memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); |
cb5a6ffc RK |
858 | ac97_template.private_data = aaci; |
859 | ac97_template.num = 0; | |
860 | ac97_template.scaps = AC97_SCAP_SKIP_MODEM; | |
861 | ||
862 | ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); | |
863 | if (ret) | |
864 | goto out; | |
41762b8c | 865 | aaci->ac97 = ac97; |
cb5a6ffc RK |
866 | |
867 | /* | |
868 | * Disable AC97 PC Beep input on audio codecs. | |
869 | */ | |
870 | if (ac97_is_audio(ac97)) | |
871 | snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); | |
872 | ||
873 | ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); | |
874 | if (ret) | |
875 | goto out; | |
876 | ||
877 | aaci->playback.pcm = &ac97_bus->pcms[0]; | |
41762b8c | 878 | aaci->capture.pcm = &ac97_bus->pcms[1]; |
cb5a6ffc RK |
879 | |
880 | out: | |
881 | return ret; | |
882 | } | |
883 | ||
ceb9e476 | 884 | static void aaci_free_card(struct snd_card *card) |
cb5a6ffc RK |
885 | { |
886 | struct aaci *aaci = card->private_data; | |
887 | if (aaci->base) | |
888 | iounmap(aaci->base); | |
889 | } | |
890 | ||
891 | static struct aaci * __devinit aaci_init_card(struct amba_device *dev) | |
892 | { | |
893 | struct aaci *aaci; | |
ceb9e476 | 894 | struct snd_card *card; |
bd7dd77c | 895 | int err; |
cb5a6ffc | 896 | |
bd7dd77c TI |
897 | err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, |
898 | THIS_MODULE, sizeof(struct aaci), &card); | |
899 | if (err < 0) | |
631e8ad4 | 900 | return NULL; |
cb5a6ffc RK |
901 | |
902 | card->private_free = aaci_free_card; | |
cb5a6ffc RK |
903 | |
904 | strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); | |
905 | strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); | |
906 | snprintf(card->longname, sizeof(card->longname), | |
f006d8fc RK |
907 | "%s PL%03x rev%u at 0x%08llx, irq %d", |
908 | card->shortname, amba_part(dev), amba_rev(dev), | |
909 | (unsigned long long)dev->res.start, dev->irq[0]); | |
cb5a6ffc RK |
910 | |
911 | aaci = card->private_data; | |
12aa7579 | 912 | mutex_init(&aaci->ac97_sem); |
b60fb519 | 913 | mutex_init(&aaci->irq_lock); |
cb5a6ffc RK |
914 | aaci->card = card; |
915 | aaci->dev = dev; | |
916 | ||
917 | /* Set MAINCR to allow slot 1 and 2 data IO */ | |
918 | aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | | |
919 | MAINCR_SL2RXEN | MAINCR_SL2TXEN; | |
920 | ||
921 | return aaci; | |
922 | } | |
923 | ||
924 | static int __devinit aaci_init_pcm(struct aaci *aaci) | |
925 | { | |
ceb9e476 | 926 | struct snd_pcm *pcm; |
cb5a6ffc RK |
927 | int ret; |
928 | ||
41762b8c | 929 | ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); |
cb5a6ffc RK |
930 | if (ret == 0) { |
931 | aaci->pcm = pcm; | |
932 | pcm->private_data = aaci; | |
933 | pcm->info_flags = 0; | |
934 | ||
935 | strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); | |
936 | ||
937 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); | |
41762b8c | 938 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); |
d6797322 | 939 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
d4946431 | 940 | NULL, 0, 64 * 1024); |
cb5a6ffc RK |
941 | } |
942 | ||
943 | return ret; | |
944 | } | |
945 | ||
946 | static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) | |
947 | { | |
41762b8c | 948 | struct aaci_runtime *aacirun = &aaci->playback; |
cb5a6ffc RK |
949 | int i; |
950 | ||
41762b8c | 951 | writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); |
cb5a6ffc | 952 | |
41762b8c KH |
953 | for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) |
954 | writel(0, aacirun->fifo); | |
cb5a6ffc | 955 | |
41762b8c | 956 | writel(0, aacirun->base + AACI_TXCR); |
cb5a6ffc RK |
957 | |
958 | /* | |
959 | * Re-initialise the AACI after the FIFO depth test, to | |
960 | * ensure that the FIFOs are empty. Unfortunately, merely | |
961 | * disabling the channel doesn't clear the FIFO. | |
962 | */ | |
963 | writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); | |
964 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
965 | ||
966 | /* | |
967 | * If we hit 4096, we failed. Go back to the specified | |
968 | * fifo depth. | |
969 | */ | |
970 | if (i == 4096) | |
971 | i = 8; | |
972 | ||
973 | return i; | |
974 | } | |
975 | ||
03fbdb15 | 976 | static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id) |
cb5a6ffc RK |
977 | { |
978 | struct aaci *aaci; | |
979 | int ret, i; | |
980 | ||
981 | ret = amba_request_regions(dev, NULL); | |
982 | if (ret) | |
983 | return ret; | |
984 | ||
985 | aaci = aaci_init_card(dev); | |
631e8ad4 TI |
986 | if (!aaci) { |
987 | ret = -ENOMEM; | |
cb5a6ffc RK |
988 | goto out; |
989 | } | |
990 | ||
dc890c2d | 991 | aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); |
cb5a6ffc RK |
992 | if (!aaci->base) { |
993 | ret = -ENOMEM; | |
994 | goto out; | |
995 | } | |
996 | ||
997 | /* | |
998 | * Playback uses AACI channel 0 | |
999 | */ | |
d6a89fef | 1000 | spin_lock_init(&aaci->playback.lock); |
cb5a6ffc RK |
1001 | aaci->playback.base = aaci->base + AACI_CSCH1; |
1002 | aaci->playback.fifo = aaci->base + AACI_DR1; | |
1003 | ||
41762b8c KH |
1004 | /* |
1005 | * Capture uses AACI channel 0 | |
1006 | */ | |
d6a89fef | 1007 | spin_lock_init(&aaci->capture.lock); |
41762b8c KH |
1008 | aaci->capture.base = aaci->base + AACI_CSCH1; |
1009 | aaci->capture.fifo = aaci->base + AACI_DR1; | |
1010 | ||
cb5a6ffc | 1011 | for (i = 0; i < 4; i++) { |
e12ba644 | 1012 | void __iomem *base = aaci->base + i * 0x14; |
cb5a6ffc RK |
1013 | |
1014 | writel(0, base + AACI_IE); | |
1015 | writel(0, base + AACI_TXCR); | |
1016 | writel(0, base + AACI_RXCR); | |
1017 | } | |
1018 | ||
1019 | writel(0x1fff, aaci->base + AACI_INTCLR); | |
1020 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
b68b58fd PJ |
1021 | /* |
1022 | * Fix: ac97 read back fail errors by reading | |
1023 | * from any arbitrary aaci register. | |
1024 | */ | |
1025 | readl(aaci->base + AACI_CSCH1); | |
f27f218c CM |
1026 | ret = aaci_probe_ac97(aaci); |
1027 | if (ret) | |
1028 | goto out; | |
1029 | ||
cb5a6ffc | 1030 | /* |
f27f218c | 1031 | * Size the FIFOs (must be multiple of 16). |
cb5a6ffc RK |
1032 | */ |
1033 | aaci->fifosize = aaci_size_fifo(aaci); | |
f27f218c CM |
1034 | if (aaci->fifosize & 15) { |
1035 | printk(KERN_WARNING "AACI: fifosize = %d not supported\n", | |
1036 | aaci->fifosize); | |
1037 | ret = -ENODEV; | |
cb5a6ffc | 1038 | goto out; |
f27f218c | 1039 | } |
cb5a6ffc RK |
1040 | |
1041 | ret = aaci_init_pcm(aaci); | |
1042 | if (ret) | |
1043 | goto out; | |
1044 | ||
a76af199 TI |
1045 | snd_card_set_dev(aaci->card, &dev->dev); |
1046 | ||
cb5a6ffc RK |
1047 | ret = snd_card_register(aaci->card); |
1048 | if (ret == 0) { | |
1049 | dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname, | |
41762b8c | 1050 | aaci->fifosize); |
cb5a6ffc RK |
1051 | amba_set_drvdata(dev, aaci->card); |
1052 | return ret; | |
1053 | } | |
1054 | ||
1055 | out: | |
1056 | if (aaci) | |
1057 | snd_card_free(aaci->card); | |
1058 | amba_release_regions(dev); | |
1059 | return ret; | |
1060 | } | |
1061 | ||
1062 | static int __devexit aaci_remove(struct amba_device *dev) | |
1063 | { | |
ceb9e476 | 1064 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
1065 | |
1066 | amba_set_drvdata(dev, NULL); | |
1067 | ||
1068 | if (card) { | |
1069 | struct aaci *aaci = card->private_data; | |
1070 | writel(0, aaci->base + AACI_MAINCR); | |
1071 | ||
1072 | snd_card_free(card); | |
1073 | amba_release_regions(dev); | |
1074 | } | |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static struct amba_id aaci_ids[] = { | |
1080 | { | |
1081 | .id = 0x00041041, | |
1082 | .mask = 0x000fffff, | |
1083 | }, | |
1084 | { 0, 0 }, | |
1085 | }; | |
1086 | ||
1087 | static struct amba_driver aaci_driver = { | |
1088 | .drv = { | |
1089 | .name = DRIVER_NAME, | |
1090 | }, | |
1091 | .probe = aaci_probe, | |
1092 | .remove = __devexit_p(aaci_remove), | |
1093 | .suspend = aaci_suspend, | |
1094 | .resume = aaci_resume, | |
1095 | .id_table = aaci_ids, | |
1096 | }; | |
1097 | ||
1098 | static int __init aaci_init(void) | |
1099 | { | |
1100 | return amba_driver_register(&aaci_driver); | |
1101 | } | |
1102 | ||
1103 | static void __exit aaci_exit(void) | |
1104 | { | |
1105 | amba_driver_unregister(&aaci_driver); | |
1106 | } | |
1107 | ||
1108 | module_init(aaci_init); | |
1109 | module_exit(aaci_exit); | |
1110 | ||
1111 | MODULE_LICENSE("GPL"); | |
1112 | MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); |