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9c636342 DB |
1 | /* |
2 | * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c | |
3 | * which contain: | |
4 | * | |
5 | * Author: Nicolas Pitre | |
6 | * Created: Dec 02, 2004 | |
7 | * Copyright: MontaVista Software Inc. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/delay.h> | |
da155d5b | 19 | #include <linux/module.h> |
23019a73 | 20 | #include <linux/io.h> |
9c636342 DB |
21 | |
22 | #include <sound/ac97_codec.h> | |
23 | #include <sound/pxa2xx-lib.h> | |
24 | ||
9482ee71 | 25 | #include <mach/irqs.h> |
1f017a99 | 26 | #include <mach/regs-ac97.h> |
9c636342 DB |
27 | #include <mach/audio.h> |
28 | ||
29 | static DEFINE_MUTEX(car_mutex); | |
30 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); | |
31 | static volatile long gsr_bits; | |
32 | static struct clk *ac97_clk; | |
9c636342 | 33 | static struct clk *ac97conf_clk; |
26ade896 | 34 | static int reset_gpio; |
9c636342 | 35 | |
fb1bf8cd EM |
36 | extern void pxa27x_assert_ac97reset(int reset_gpio, int on); |
37 | ||
9c636342 DB |
38 | /* |
39 | * Beware PXA27x bugs: | |
40 | * | |
41 | * o Slot 12 read from modem space will hang controller. | |
42 | * o CDONE, SDONE interrupt fails after any slot 12 IO. | |
43 | * | |
44 | * We therefore have an hybrid approach for waiting on SDONE (interrupt or | |
45 | * 1 jiffy timeout if interrupt never comes). | |
46 | */ | |
47 | ||
48 | unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) | |
49 | { | |
50 | unsigned short val = -1; | |
51 | volatile u32 *reg_addr; | |
52 | ||
53 | mutex_lock(&car_mutex); | |
54 | ||
55 | /* set up primary or secondary codec space */ | |
8825e8e8 | 56 | if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) |
9c636342 DB |
57 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; |
58 | else | |
59 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
9c636342 DB |
60 | reg_addr += (reg >> 1); |
61 | ||
62 | /* start read access across the ac97 link */ | |
63 | GSR = GSR_CDONE | GSR_SDONE; | |
64 | gsr_bits = 0; | |
65 | val = *reg_addr; | |
66 | if (reg == AC97_GPIO_STATUS) | |
67 | goto out; | |
68 | if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 && | |
69 | !((GSR | gsr_bits) & GSR_SDONE)) { | |
70 | printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n", | |
71 | __func__, reg, GSR | gsr_bits); | |
72 | val = -1; | |
73 | goto out; | |
74 | } | |
75 | ||
76 | /* valid data now */ | |
77 | GSR = GSR_CDONE | GSR_SDONE; | |
78 | gsr_bits = 0; | |
79 | val = *reg_addr; | |
80 | /* but we've just started another cycle... */ | |
81 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); | |
82 | ||
83 | out: mutex_unlock(&car_mutex); | |
84 | return val; | |
85 | } | |
86 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_read); | |
87 | ||
88 | void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |
89 | unsigned short val) | |
90 | { | |
91 | volatile u32 *reg_addr; | |
92 | ||
93 | mutex_lock(&car_mutex); | |
94 | ||
95 | /* set up primary or secondary codec space */ | |
8825e8e8 | 96 | if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) |
9c636342 DB |
97 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; |
98 | else | |
99 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
9c636342 DB |
100 | reg_addr += (reg >> 1); |
101 | ||
102 | GSR = GSR_CDONE | GSR_SDONE; | |
103 | gsr_bits = 0; | |
104 | *reg_addr = val; | |
105 | if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 && | |
106 | !((GSR | gsr_bits) & GSR_CDONE)) | |
107 | printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n", | |
108 | __func__, reg, GSR | gsr_bits); | |
109 | ||
110 | mutex_unlock(&car_mutex); | |
111 | } | |
112 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_write); | |
113 | ||
9d1cf39b DB |
114 | #ifdef CONFIG_PXA25x |
115 | static inline void pxa_ac97_warm_pxa25x(void) | |
9c636342 | 116 | { |
9c636342 DB |
117 | gsr_bits = 0; |
118 | ||
9d1cf39b DB |
119 | GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; |
120 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
121 | } | |
122 | ||
123 | static inline void pxa_ac97_cold_pxa25x(void) | |
124 | { | |
125 | GCR &= GCR_COLD_RST; /* clear everything but nCRST */ | |
126 | GCR &= ~GCR_COLD_RST; /* then assert nCRST */ | |
127 | ||
128 | gsr_bits = 0; | |
129 | ||
130 | GCR = GCR_COLD_RST; | |
131 | GCR |= GCR_CDONE_IE|GCR_SDONE_IE; | |
132 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
133 | } | |
134 | #endif | |
135 | ||
9c636342 | 136 | #ifdef CONFIG_PXA27x |
9d1cf39b DB |
137 | static inline void pxa_ac97_warm_pxa27x(void) |
138 | { | |
139 | gsr_bits = 0; | |
140 | ||
fb1bf8cd EM |
141 | /* warm reset broken on Bulverde, so manually keep AC97 reset high */ |
142 | pxa27x_assert_ac97reset(reset_gpio, 1); | |
9c636342 DB |
143 | udelay(10); |
144 | GCR |= GCR_WARM_RST; | |
fb1bf8cd | 145 | pxa27x_assert_ac97reset(reset_gpio, 0); |
9c636342 | 146 | udelay(500); |
9d1cf39b DB |
147 | } |
148 | ||
149 | static inline void pxa_ac97_cold_pxa27x(void) | |
150 | { | |
41b645c8 MD |
151 | unsigned int timeout; |
152 | ||
9d1cf39b DB |
153 | GCR &= GCR_COLD_RST; /* clear everything but nCRST */ |
154 | GCR &= ~GCR_COLD_RST; /* then assert nCRST */ | |
155 | ||
156 | gsr_bits = 0; | |
157 | ||
158 | /* PXA27x Developers Manual section 13.5.2.2.1 */ | |
159 | clk_enable(ac97conf_clk); | |
160 | udelay(5); | |
161 | clk_disable(ac97conf_clk); | |
41b645c8 MD |
162 | GCR = GCR_COLD_RST | GCR_WARM_RST; |
163 | timeout = 100; /* wait for the codec-ready bit to be set */ | |
164 | while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) | |
165 | mdelay(1); | |
9d1cf39b | 166 | } |
9c636342 DB |
167 | #endif |
168 | ||
9d1cf39b DB |
169 | #ifdef CONFIG_PXA3xx |
170 | static inline void pxa_ac97_warm_pxa3xx(void) | |
171 | { | |
172 | int timeout = 100; | |
9c636342 | 173 | |
9d1cf39b | 174 | gsr_bits = 0; |
9c636342 | 175 | |
9d1cf39b DB |
176 | /* Can't use interrupts */ |
177 | GCR |= GCR_WARM_RST; | |
178 | while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) | |
179 | mdelay(1); | |
9c636342 | 180 | } |
9c636342 | 181 | |
9d1cf39b | 182 | static inline void pxa_ac97_cold_pxa3xx(void) |
9c636342 | 183 | { |
9c636342 DB |
184 | int timeout = 1000; |
185 | ||
186 | /* Hold CLKBPB for 100us */ | |
187 | GCR = 0; | |
188 | GCR = GCR_CLKBPB; | |
189 | udelay(100); | |
190 | GCR = 0; | |
9c636342 DB |
191 | |
192 | GCR &= GCR_COLD_RST; /* clear everything but nCRST */ | |
193 | GCR &= ~GCR_COLD_RST; /* then assert nCRST */ | |
194 | ||
195 | gsr_bits = 0; | |
9d1cf39b | 196 | |
9c636342 DB |
197 | /* Can't use interrupts on PXA3xx */ |
198 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
199 | ||
200 | GCR = GCR_WARM_RST | GCR_COLD_RST; | |
201 | while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--) | |
202 | mdelay(10); | |
9d1cf39b DB |
203 | } |
204 | #endif | |
205 | ||
206 | bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97) | |
207 | { | |
057de50c LF |
208 | unsigned long gsr; |
209 | ||
9d1cf39b | 210 | #ifdef CONFIG_PXA25x |
8825e8e8 | 211 | if (cpu_is_pxa25x()) |
9d1cf39b DB |
212 | pxa_ac97_warm_pxa25x(); |
213 | else | |
9c636342 | 214 | #endif |
9d1cf39b DB |
215 | #ifdef CONFIG_PXA27x |
216 | if (cpu_is_pxa27x()) | |
217 | pxa_ac97_warm_pxa27x(); | |
218 | else | |
219 | #endif | |
220 | #ifdef CONFIG_PXA3xx | |
221 | if (cpu_is_pxa3xx()) | |
222 | pxa_ac97_warm_pxa3xx(); | |
223 | else | |
224 | #endif | |
225 | BUG(); | |
057de50c LF |
226 | gsr = GSR | gsr_bits; |
227 | if (!(gsr & (GSR_PCR | GSR_SCR))) { | |
9d1cf39b | 228 | printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", |
057de50c | 229 | __func__, gsr); |
9d1cf39b DB |
230 | |
231 | return false; | |
232 | } | |
233 | ||
234 | return true; | |
235 | } | |
236 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset); | |
237 | ||
238 | bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97) | |
239 | { | |
057de50c LF |
240 | unsigned long gsr; |
241 | ||
9d1cf39b | 242 | #ifdef CONFIG_PXA25x |
8825e8e8 | 243 | if (cpu_is_pxa25x()) |
9d1cf39b DB |
244 | pxa_ac97_cold_pxa25x(); |
245 | else | |
246 | #endif | |
247 | #ifdef CONFIG_PXA27x | |
248 | if (cpu_is_pxa27x()) | |
249 | pxa_ac97_cold_pxa27x(); | |
250 | else | |
251 | #endif | |
252 | #ifdef CONFIG_PXA3xx | |
253 | if (cpu_is_pxa3xx()) | |
254 | pxa_ac97_cold_pxa3xx(); | |
255 | else | |
256 | #endif | |
257 | BUG(); | |
9c636342 | 258 | |
057de50c LF |
259 | gsr = GSR | gsr_bits; |
260 | if (!(gsr & (GSR_PCR | GSR_SCR))) { | |
9c636342 | 261 | printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", |
057de50c | 262 | __func__, gsr); |
9c636342 DB |
263 | |
264 | return false; | |
265 | } | |
266 | ||
267 | return true; | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset); | |
270 | ||
271 | ||
272 | void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97) | |
273 | { | |
274 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
275 | GCR |= GCR_SDONE_IE|GCR_CDONE_IE; | |
276 | } | |
277 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset); | |
278 | ||
279 | static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) | |
280 | { | |
281 | long status; | |
282 | ||
283 | status = GSR; | |
284 | if (status) { | |
285 | GSR = status; | |
286 | gsr_bits |= status; | |
287 | wake_up(&gsr_wq); | |
288 | ||
9c636342 DB |
289 | /* Although we don't use those we still need to clear them |
290 | since they tend to spuriously trigger when MMC is used | |
291 | (hardware bug? go figure)... */ | |
9d1cf39b DB |
292 | if (cpu_is_pxa27x()) { |
293 | MISR = MISR_EOC; | |
294 | PISR = PISR_EOC; | |
295 | MCSR = MCSR_EOC; | |
296 | } | |
9c636342 DB |
297 | |
298 | return IRQ_HANDLED; | |
299 | } | |
300 | ||
301 | return IRQ_NONE; | |
302 | } | |
303 | ||
304 | #ifdef CONFIG_PM | |
305 | int pxa2xx_ac97_hw_suspend(void) | |
306 | { | |
307 | GCR |= GCR_ACLINK_OFF; | |
308 | clk_disable(ac97_clk); | |
309 | return 0; | |
310 | } | |
311 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend); | |
312 | ||
313 | int pxa2xx_ac97_hw_resume(void) | |
314 | { | |
9c636342 DB |
315 | clk_enable(ac97_clk); |
316 | return 0; | |
317 | } | |
318 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume); | |
319 | #endif | |
320 | ||
e21596bb | 321 | int pxa2xx_ac97_hw_probe(struct platform_device *dev) |
9c636342 DB |
322 | { |
323 | int ret; | |
eae17754 | 324 | pxa2xx_audio_ops_t *pdata = dev->dev.platform_data; |
26ade896 RJ |
325 | |
326 | if (pdata) { | |
327 | switch (pdata->reset_gpio) { | |
328 | case 95: | |
329 | case 113: | |
330 | reset_gpio = pdata->reset_gpio; | |
331 | break; | |
332 | case 0: | |
333 | reset_gpio = 113; | |
334 | break; | |
335 | case -1: | |
336 | break; | |
337 | default: | |
1f218695 | 338 | dev_err(&dev->dev, "Invalid reset GPIO %d\n", |
26ade896 RJ |
339 | pdata->reset_gpio); |
340 | } | |
341 | } else { | |
342 | if (cpu_is_pxa27x()) | |
343 | reset_gpio = 113; | |
344 | } | |
9c636342 | 345 | |
9d1cf39b DB |
346 | if (cpu_is_pxa27x()) { |
347 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | |
fb1bf8cd | 348 | pxa27x_assert_ac97reset(reset_gpio, 0); |
9d1cf39b DB |
349 | ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); |
350 | if (IS_ERR(ac97conf_clk)) { | |
351 | ret = PTR_ERR(ac97conf_clk); | |
352 | ac97conf_clk = NULL; | |
79612336 | 353 | goto err_conf; |
9d1cf39b | 354 | } |
9c636342 | 355 | } |
9c636342 DB |
356 | |
357 | ac97_clk = clk_get(&dev->dev, "AC97CLK"); | |
358 | if (IS_ERR(ac97_clk)) { | |
359 | ret = PTR_ERR(ac97_clk); | |
360 | ac97_clk = NULL; | |
79612336 | 361 | goto err_clk; |
9c636342 DB |
362 | } |
363 | ||
79612336 DB |
364 | ret = clk_enable(ac97_clk); |
365 | if (ret) | |
366 | goto err_clk2; | |
367 | ||
88e24c3a | 368 | ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL); |
79612336 DB |
369 | if (ret < 0) |
370 | goto err_irq; | |
371 | ||
372 | return 0; | |
9c636342 DB |
373 | |
374 | err_irq: | |
375 | GCR |= GCR_ACLINK_OFF; | |
79612336 DB |
376 | err_clk2: |
377 | clk_put(ac97_clk); | |
378 | ac97_clk = NULL; | |
379 | err_clk: | |
9c636342 DB |
380 | if (ac97conf_clk) { |
381 | clk_put(ac97conf_clk); | |
382 | ac97conf_clk = NULL; | |
383 | } | |
79612336 | 384 | err_conf: |
9c636342 DB |
385 | return ret; |
386 | } | |
387 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe); | |
388 | ||
389 | void pxa2xx_ac97_hw_remove(struct platform_device *dev) | |
390 | { | |
391 | GCR |= GCR_ACLINK_OFF; | |
392 | free_irq(IRQ_AC97, NULL); | |
9d1cf39b DB |
393 | if (ac97conf_clk) { |
394 | clk_put(ac97conf_clk); | |
395 | ac97conf_clk = NULL; | |
396 | } | |
9c636342 DB |
397 | clk_disable(ac97_clk); |
398 | clk_put(ac97_clk); | |
399 | ac97_clk = NULL; | |
400 | } | |
401 | EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove); | |
402 | ||
403 | MODULE_AUTHOR("Nicolas Pitre"); | |
404 | MODULE_DESCRIPTION("Intel/Marvell PXA sound library"); | |
405 | MODULE_LICENSE("GPL"); | |
406 |