[deliverable/linux.git] / sound / arm / pxa2xx-ac97.c

/*
 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/delay.h>

#include <sound/driver.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>

#include <asm/irq.h>
#include <linux/mutex.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/audio.h>

#include "pxa2xx-pcm.h"


static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */ 

static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__FUNCTION__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;			
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}

static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__FUNCTION__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}

static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
{
	/* First, try cold reset */
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;
#ifdef CONFIG_PXA27x
	/* PXA27x Developers Manual section 13.5.2.2.1 */
	pxa_set_cken(1 << 31, 1);
	udelay(5);
	pxa_set_cken(1 << 31, 0);
	GCR = GCR_COLD_RST;
	udelay(50);
#else
	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif

	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __FUNCTION__, gsr_bits);

		/* let's try warm reset */
		gsr_bits = 0;
#ifdef CONFIG_PXA27x
		/* warm reset broken on Bulverde,
		   so manually keep AC97 reset high */
		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
		udelay(10);
		GCR |= GCR_WARM_RST;
		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
		udelay(500);
#else
		GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
		wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif			

		if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
			printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
					 __FUNCTION__, gsr_bits);
	}

	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

#ifdef CONFIG_PXA27x
		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		MISR = MISR_EOC;
		PISR = PISR_EOC;
		MCSR = MCSR_EOC;
#endif

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
	.read	= pxa2xx_ac97_read,
	.write	= pxa2xx_ac97_write,
	.reset	= pxa2xx_ac97_reset,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
	.name			= "AC97 PCM out",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRTXPCDR,
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
	.name			= "AC97 PCM in",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRRXPCDR,
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct snd_pcm *pxa2xx_ac97_pcm;
static struct snd_ac97 *pxa2xx_ac97_ac97;

static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	pxa2xx_audio_ops_t *platform_ops;
	int r;

	runtime->hw.channels_min = 2;
	runtime->hw.channels_max = 2;

	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	    AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	snd_pcm_limit_hw_rates(runtime);

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->startup)
		return platform_ops->startup(substream, platform_ops->priv);
	else
		return 0;
}

static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
{
	pxa2xx_audio_ops_t *platform_ops;

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->shutdown)
		platform_ops->shutdown(substream, platform_ops->priv);
}

static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
		  AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
}

static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
	.playback_params	= &pxa2xx_ac97_pcm_out,
	.capture_params		= &pxa2xx_ac97_pcm_in,
	.startup		= pxa2xx_ac97_pcm_startup,
	.shutdown		= pxa2xx_ac97_pcm_shutdown,
	.prepare		= pxa2xx_ac97_pcm_prepare,
};

#ifdef CONFIG_PM

static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	snd_ac97_suspend(pxa2xx_ac97_ac97);
	if (platform_ops && platform_ops->suspend)
		platform_ops->suspend(platform_ops->priv);
	GCR |= GCR_ACLINK_OFF;
	pxa_set_cken(CKEN2_AC97, 0);

	return 0;
}

static int pxa2xx_ac97_do_resume(struct snd_card *card)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	pxa_set_cken(CKEN2_AC97, 1);
	if (platform_ops && platform_ops->resume)
		platform_ops->resume(platform_ops->priv);
	snd_ac97_resume(pxa2xx_ac97_ac97);
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}

static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);

	return ret;
}

static int pxa2xx_ac97_resume(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_resume(card);

	return ret;
}

#else
#define pxa2xx_ac97_suspend	NULL
#define pxa2xx_ac97_resume	NULL
#endif

static int pxa2xx_ac97_probe(struct platform_device *dev)
{
	struct snd_card *card;
	struct snd_ac97_bus *ac97_bus;
	struct snd_ac97_template ac97_template;
	int ret;

	ret = -ENOMEM;
	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			    THIS_MODULE, 0);
	if (!card)
		goto err;

	card->dev = &dev->dev;
	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));

	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	if (ret)
		goto err;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err;

	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
#ifdef CONFIG_PXA27x
	/* Use GPIO 113 as AC97 Reset on Bulverde */
	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
#endif
	pxa_set_cken(CKEN2_AC97, 1);

	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	if (ret)
		goto err;
	memset(&ac97_template, 0, sizeof(ac97_template));
	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	if (ret)
		goto err;

	snprintf(card->shortname, sizeof(card->shortname),
		 "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	snprintf(card->longname, sizeof(card->longname),
		 "%s (%s)", dev->dev.driver->name, card->mixername);

	ret = snd_card_register(card);
	if (ret == 0) {
		platform_set_drvdata(dev, card);
		return 0;
	}

 err:
	if (card)
		snd_card_free(card);
	if (CKEN & CKEN2_AC97) {
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		pxa_set_cken(CKEN2_AC97, 0);
	}
	return ret;
}

static int pxa2xx_ac97_remove(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);

	if (card) {
		snd_card_free(card);
		platform_set_drvdata(dev, NULL);
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		pxa_set_cken(CKEN2_AC97, 0);
	}

	return 0;
}

static struct platform_driver pxa2xx_ac97_driver = {
	.probe		= pxa2xx_ac97_probe,
	.remove		= pxa2xx_ac97_remove,
	.suspend	= pxa2xx_ac97_suspend,
	.resume		= pxa2xx_ac97_resume,
	.driver		= {
		.name	= "pxa2xx-ac97",
	},
};

static int __init pxa2xx_ac97_init(void)
{
	return platform_driver_register(&pxa2xx_ac97_driver);
}

static void __exit pxa2xx_ac97_exit(void)
{
	platform_driver_unregister(&pxa2xx_ac97_driver);
}

module_init(pxa2xx_ac97_init);
module_exit(pxa2xx_ac97_exit);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
MODULE_LICENSE("GPL");
Commit	Line	Data
2c484df0 TI	1	/*
	2	* linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Dec 02, 2004
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
d052d1be	16	#include <linux/platform_device.h>
2c484df0 TI	17	#include <linux/interrupt.h>
	18	#include <linux/wait.h>
	19	#include <linux/delay.h>
	20
	21	#include <sound/driver.h>
	22	#include <sound/core.h>
	23	#include <sound/pcm.h>
	24	#include <sound/ac97_codec.h>
	25	#include <sound/initval.h>
	26
	27	#include <asm/irq.h>
12aa7579	28	#include <linux/mutex.h>
2c484df0 TI	29	#include <asm/hardware.h>
	30	#include <asm/arch/pxa-regs.h>
	31	#include <asm/arch/audio.h>
	32
	33	#include "pxa2xx-pcm.h"
	34
	35
12aa7579	36	static DEFINE_MUTEX(car_mutex);
2c484df0 TI	37	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	38	static volatile long gsr_bits;
	39
ea265c0a NP	40	/*
	41	* Beware PXA27x bugs:
	42	*
	43	* o Slot 12 read from modem space will hang controller.
	44	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	45	*
	46	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	47	* 1 jiffy timeout if interrupt never comes).
	48	*/
	49
d18f8376	50	static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
2c484df0 TI	51	{
	52	unsigned short val = -1;
	53	volatile u32 *reg_addr;
	54
12aa7579	55	mutex_lock(&car_mutex);
2c484df0 TI	56
	57	/* set up primary or secondary codec space */
	58	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	59	reg_addr += (reg >> 1);
	60
	61	/* start read access across the ac97 link */
ea265c0a	62	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	63	gsr_bits = 0;
	64	val = *reg_addr;
	65	if (reg == AC97_GPIO_STATUS)
	66	goto out;
ea265c0a NP	67	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
ea265c0a NP	68	!((GSR \| gsr_bits) & GSR_SDONE)) {
2c484df0	69	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
ea265c0a	70	__FUNCTION__, reg, GSR \| gsr_bits);
2c484df0 TI	71	val = -1;
	72	goto out;
	73	}
	74
	75	/* valid data now */
ea265c0a	76	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	77	gsr_bits = 0;
	78	val = *reg_addr;
	79	/* but we've just started another cycle... */
ea265c0a	80	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
2c484df0	81
12aa7579	82	out: mutex_unlock(&car_mutex);
2c484df0 TI	83	return val;
	84	}
	85
d18f8376	86	static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2c484df0 TI	87	{
	88	volatile u32 *reg_addr;
	89
12aa7579	90	mutex_lock(&car_mutex);
2c484df0	91
2c484df0 TI	92	/* set up primary or secondary codec space */
	93	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	94	reg_addr += (reg >> 1);
ea265c0a NP	95
ea265c0a NP	96	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	97	gsr_bits = 0;
2c484df0 TI	98	*reg_addr = val;
ea265c0a NP	99	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
ea265c0a NP	100	!((GSR \| gsr_bits) & GSR_CDONE))
2c484df0	101	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
ea265c0a	102	__FUNCTION__, reg, GSR \| gsr_bits);
2c484df0	103
12aa7579	104	mutex_unlock(&car_mutex);
2c484df0 TI	105	}
2c484df0 TI	106
d18f8376	107	static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
2c484df0 TI	108	{
	109	/* First, try cold reset */
	110	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	111	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	112
	113	gsr_bits = 0;
	114	#ifdef CONFIG_PXA27x
	115	/* PXA27x Developers Manual section 13.5.2.2.1 */
	116	pxa_set_cken(1 << 31, 1);
	117	udelay(5);
	118	pxa_set_cken(1 << 31, 0);
	119	GCR = GCR_COLD_RST;
	120	udelay(50);
	121	#else
	122	GCR = GCR_COLD_RST;
	123	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	124	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	125	#endif
	126
	127	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR))) {
	128	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
	129	__FUNCTION__, gsr_bits);
	130
	131	/* let's try warm reset */
	132	gsr_bits = 0;
	133	#ifdef CONFIG_PXA27x
	134	/* warm reset broken on Bulverde,
	135	so manually keep AC97 reset high */
	136	pxa_gpio_mode(113 \| GPIO_OUT \| GPIO_DFLT_HIGH);
	137	udelay(10);
	138	GCR \|= GCR_WARM_RST;
	139	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
4a677ac5	140	udelay(500);
2c484df0	141	#else
4a677ac5	142	GCR \|= GCR_WARM_RST\|GCR_PRIRDY_IEN\|GCR_SECRDY_IEN;
2c484df0 TI	143	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	144	#endif
	145
	146	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)))
	147	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
	148	__FUNCTION__, gsr_bits);
	149	}
	150
	151	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	152	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	153	}
	154
7d12e780	155	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
2c484df0 TI	156	{
	157	long status;
	158
	159	status = GSR;
	160	if (status) {
	161	GSR = status;
	162	gsr_bits \|= status;
	163	wake_up(&gsr_wq);
	164
	165	#ifdef CONFIG_PXA27x
	166	/* Although we don't use those we still need to clear them
	167	since they tend to spuriously trigger when MMC is used
	168	(hardware bug? go figure)... */
	169	MISR = MISR_EOC;
	170	PISR = PISR_EOC;
	171	MCSR = MCSR_EOC;
	172	#endif
	173
	174	return IRQ_HANDLED;
	175	}
	176
	177	return IRQ_NONE;
	178	}
	179
d18f8376	180	static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
2c484df0 TI	181	.read = pxa2xx_ac97_read,
	182	.write = pxa2xx_ac97_write,
	183	.reset = pxa2xx_ac97_reset,
	184	};
	185
d18f8376	186	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
2c484df0 TI	187	.name = "AC97 PCM out",
	188	.dev_addr = __PREG(PCDR),
	189	.drcmr = &DRCMRTXPCDR,
	190	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	191	DCMD_BURST32 \| DCMD_WIDTH4,
	192	};
	193
d18f8376	194	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
2c484df0 TI	195	.name = "AC97 PCM in",
	196	.dev_addr = __PREG(PCDR),
	197	.drcmr = &DRCMRRXPCDR,
	198	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	199	DCMD_BURST32 \| DCMD_WIDTH4,
	200	};
	201
d18f8376 TI	202	static struct snd_pcm *pxa2xx_ac97_pcm;
d18f8376 TI	203	static struct snd_ac97 *pxa2xx_ac97_ac97;
2c484df0	204
d18f8376	205	static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
2c484df0	206	{
d18f8376	207	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	208	pxa2xx_audio_ops_t *platform_ops;
	209	int r;
	210
	211	runtime->hw.channels_min = 2;
	212	runtime->hw.channels_max = 2;
	213
	214	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	215	AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	216	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	217	snd_pcm_limit_hw_rates(runtime);
	218
	219	platform_ops = substream->pcm->card->dev->platform_data;
	220	if (platform_ops && platform_ops->startup)
	221	return platform_ops->startup(substream, platform_ops->priv);
	222	else
	223	return 0;
	224	}
	225
d18f8376	226	static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
2c484df0 TI	227	{
	228	pxa2xx_audio_ops_t *platform_ops;
	229
	230	platform_ops = substream->pcm->card->dev->platform_data;
	231	if (platform_ops && platform_ops->shutdown)
	232	platform_ops->shutdown(substream, platform_ops->priv);
	233	}
	234
d18f8376	235	static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
2c484df0	236	{
d18f8376	237	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	238	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	239	AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	240	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
	241	}
	242
d18f8376	243	static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
2c484df0 TI	244	.playback_params = &pxa2xx_ac97_pcm_out,
	245	.capture_params = &pxa2xx_ac97_pcm_in,
	246	.startup = pxa2xx_ac97_pcm_startup,
	247	.shutdown = pxa2xx_ac97_pcm_shutdown,
	248	.prepare = pxa2xx_ac97_pcm_prepare,
	249	};
	250
	251	#ifdef CONFIG_PM
	252
d18f8376	253	static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
2c484df0	254	{
792a6c51 TI	255	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
	256
	257	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	258	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	259	snd_ac97_suspend(pxa2xx_ac97_ac97);
	260	if (platform_ops && platform_ops->suspend)
	261	platform_ops->suspend(platform_ops->priv);
	262	GCR \|= GCR_ACLINK_OFF;
	263	pxa_set_cken(CKEN2_AC97, 0);
2c484df0 TI	264
	265	return 0;
	266	}
	267
d18f8376	268	static int pxa2xx_ac97_do_resume(struct snd_card *card)
2c484df0	269	{
792a6c51 TI	270	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
	271
	272	pxa_set_cken(CKEN2_AC97, 1);
	273	if (platform_ops && platform_ops->resume)
	274	platform_ops->resume(platform_ops->priv);
	275	snd_ac97_resume(pxa2xx_ac97_ac97);
	276	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2c484df0 TI	277
	278	return 0;
	279	}
	280
3ae5eaec	281	static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
2c484df0	282	{
d18f8376	283	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	284	int ret = 0;
2c484df0 TI	285
9480e307	286	if (card)
a55bfdc5	287	ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);
2c484df0 TI	288
	289	return ret;
	290	}
	291
3ae5eaec	292	static int pxa2xx_ac97_resume(struct platform_device *dev)
2c484df0	293	{
d18f8376	294	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	295	int ret = 0;
2c484df0 TI	296
9480e307	297	if (card)
a55bfdc5	298	ret = pxa2xx_ac97_do_resume(card);
2c484df0 TI	299
	300	return ret;
	301	}
	302
	303	#else
	304	#define pxa2xx_ac97_suspend NULL
	305	#define pxa2xx_ac97_resume NULL
	306	#endif
	307
3ae5eaec	308	static int pxa2xx_ac97_probe(struct platform_device *dev)
2c484df0	309	{
d18f8376 TI	310	struct snd_card *card;
	311	struct snd_ac97_bus *ac97_bus;
	312	struct snd_ac97_template ac97_template;
2c484df0 TI	313	int ret;
	314
	315	ret = -ENOMEM;
	316	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	317	THIS_MODULE, 0);
	318	if (!card)
	319	goto err;
	320
3ae5eaec RK	321	card->dev = &dev->dev;
3ae5eaec RK	322	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));
2c484df0 TI	323
	324	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	325	if (ret)
	326	goto err;
	327
	328	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	329	if (ret < 0)
	330	goto err;
	331
	332	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	333	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	334	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	335	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	336	#ifdef CONFIG_PXA27x
	337	/* Use GPIO 113 as AC97 Reset on Bulverde */
	338	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
	339	#endif
	340	pxa_set_cken(CKEN2_AC97, 1);
	341
	342	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	343	if (ret)
	344	goto err;
	345	memset(&ac97_template, 0, sizeof(ac97_template));
	346	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	347	if (ret)
	348	goto err;
	349
	350	snprintf(card->shortname, sizeof(card->shortname),
	351	"%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	352	snprintf(card->longname, sizeof(card->longname),
3ae5eaec	353	"%s (%s)", dev->dev.driver->name, card->mixername);
2c484df0	354
2c484df0 TI	355	ret = snd_card_register(card);
2c484df0 TI	356	if (ret == 0) {
3ae5eaec	357	platform_set_drvdata(dev, card);
2c484df0 TI	358	return 0;
	359	}
	360
	361	err:
	362	if (card)
	363	snd_card_free(card);
	364	if (CKEN & CKEN2_AC97) {
	365	GCR \|= GCR_ACLINK_OFF;
	366	free_irq(IRQ_AC97, NULL);
	367	pxa_set_cken(CKEN2_AC97, 0);
	368	}
	369	return ret;
	370	}
	371
3ae5eaec	372	static int pxa2xx_ac97_remove(struct platform_device *dev)
2c484df0	373	{
d18f8376	374	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	375
	376	if (card) {
	377	snd_card_free(card);
3ae5eaec	378	platform_set_drvdata(dev, NULL);
2c484df0 TI	379	GCR \|= GCR_ACLINK_OFF;
	380	free_irq(IRQ_AC97, NULL);
	381	pxa_set_cken(CKEN2_AC97, 0);
	382	}
	383
	384	return 0;
	385	}
	386
3ae5eaec	387	static struct platform_driver pxa2xx_ac97_driver = {
2c484df0 TI	388	.probe = pxa2xx_ac97_probe,
	389	.remove = pxa2xx_ac97_remove,
	390	.suspend = pxa2xx_ac97_suspend,
	391	.resume = pxa2xx_ac97_resume,
3ae5eaec RK	392	.driver = {
	393	.name = "pxa2xx-ac97",
	394	},
2c484df0 TI	395	};
	396
	397	static int __init pxa2xx_ac97_init(void)
	398	{
3ae5eaec	399	return platform_driver_register(&pxa2xx_ac97_driver);
2c484df0 TI	400	}
	401
	402	static void __exit pxa2xx_ac97_exit(void)
	403	{
3ae5eaec	404	platform_driver_unregister(&pxa2xx_ac97_driver);
2c484df0 TI	405	}
	406
	407	module_init(pxa2xx_ac97_init);
	408	module_exit(pxa2xx_ac97_exit);
	409
	410	MODULE_AUTHOR("Nicolas Pitre");
	411	MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
	412	MODULE_LICENSE("GPL");