Commit | Line | Data |
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14752412 TI |
1 | /* |
2 | * HD-audio stream operations | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/export.h> | |
8 | #include <sound/core.h> | |
9 | #include <sound/pcm.h> | |
10 | #include <sound/hdaudio.h> | |
11 | #include <sound/hda_register.h> | |
12 | ||
13 | /** | |
14 | * snd_hdac_stream_init - initialize each stream (aka device) | |
15 | * @bus: HD-audio core bus | |
16 | * @azx_dev: HD-audio core stream object to initialize | |
17 | * @idx: stream index number | |
18 | * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) | |
19 | * @tag: the tag id to assign | |
20 | * | |
21 | * Assign the starting bdl address to each stream (device) and initialize. | |
22 | */ | |
23 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
24 | int idx, int direction, int tag) | |
25 | { | |
26 | azx_dev->bus = bus; | |
14752412 TI |
27 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
28 | azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); | |
29 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
30 | azx_dev->sd_int_sta_mask = 1 << idx; | |
31 | azx_dev->index = idx; | |
32 | azx_dev->direction = direction; | |
33 | azx_dev->stream_tag = tag; | |
8f3f600b | 34 | snd_hdac_dsp_lock_init(azx_dev); |
14752412 TI |
35 | list_add_tail(&azx_dev->list, &bus->stream_list); |
36 | } | |
37 | EXPORT_SYMBOL_GPL(snd_hdac_stream_init); | |
38 | ||
39 | /** | |
40 | * snd_hdac_stream_start - start a stream | |
41 | * @azx_dev: HD-audio core stream to start | |
42 | * @fresh_start: false = wallclock timestamp relative to period wallclock | |
43 | * | |
44 | * Start a stream, set start_wallclk and set the running flag. | |
45 | */ | |
46 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) | |
47 | { | |
48 | struct hdac_bus *bus = azx_dev->bus; | |
49 | ||
50 | azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); | |
51 | if (!fresh_start) | |
52 | azx_dev->start_wallclk -= azx_dev->period_wallclk; | |
53 | ||
54 | /* enable SIE */ | |
55 | snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index); | |
56 | /* set DMA start and interrupt mask */ | |
57 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
58 | 0, SD_CTL_DMA_START | SD_INT_MASK); | |
59 | azx_dev->running = true; | |
60 | } | |
61 | EXPORT_SYMBOL_GPL(snd_hdac_stream_start); | |
62 | ||
63 | /** | |
64 | * snd_hdac_stream_clear - stop a stream DMA | |
65 | * @azx_dev: HD-audio core stream to stop | |
66 | */ | |
67 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev) | |
68 | { | |
69 | snd_hdac_stream_updateb(azx_dev, SD_CTL, | |
70 | SD_CTL_DMA_START | SD_INT_MASK, 0); | |
71 | snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
72 | azx_dev->running = false; | |
73 | } | |
74 | EXPORT_SYMBOL_GPL(snd_hdac_stream_clear); | |
75 | ||
76 | /** | |
77 | * snd_hdac_stream_stop - stop a stream | |
78 | * @azx_dev: HD-audio core stream to stop | |
79 | * | |
80 | * Stop a stream DMA and disable stream interrupt | |
81 | */ | |
82 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev) | |
83 | { | |
84 | snd_hdac_stream_clear(azx_dev); | |
85 | /* disable SIE */ | |
86 | snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); | |
87 | } | |
88 | EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); | |
89 | ||
90 | /** | |
91 | * snd_hdac_stream_reset - reset a stream | |
92 | * @azx_dev: HD-audio core stream to reset | |
93 | */ | |
94 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev) | |
95 | { | |
96 | unsigned char val; | |
97 | int timeout; | |
98 | ||
99 | snd_hdac_stream_clear(azx_dev); | |
100 | ||
101 | snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); | |
102 | udelay(3); | |
103 | timeout = 300; | |
104 | do { | |
105 | val = snd_hdac_stream_readb(azx_dev, SD_CTL) & | |
106 | SD_CTL_STREAM_RESET; | |
107 | if (val) | |
108 | break; | |
109 | } while (--timeout); | |
110 | val &= ~SD_CTL_STREAM_RESET; | |
111 | snd_hdac_stream_writeb(azx_dev, SD_CTL, val); | |
112 | udelay(3); | |
113 | ||
114 | timeout = 300; | |
115 | /* waiting for hardware to report that the stream is out of reset */ | |
116 | do { | |
117 | val = snd_hdac_stream_readb(azx_dev, SD_CTL) & | |
118 | SD_CTL_STREAM_RESET; | |
119 | if (!val) | |
120 | break; | |
121 | } while (--timeout); | |
122 | ||
123 | /* reset first position - may not be synced with hw at this time */ | |
124 | if (azx_dev->posbuf) | |
125 | *azx_dev->posbuf = 0; | |
126 | } | |
127 | EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); | |
128 | ||
129 | /** | |
130 | * snd_hdac_stream_setup - set up the SD for streaming | |
131 | * @azx_dev: HD-audio core stream to set up | |
132 | */ | |
133 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev) | |
134 | { | |
135 | struct hdac_bus *bus = azx_dev->bus; | |
136 | struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; | |
137 | unsigned int val; | |
138 | ||
139 | /* make sure the run bit is zero for SD */ | |
140 | snd_hdac_stream_clear(azx_dev); | |
141 | /* program the stream_tag */ | |
142 | val = snd_hdac_stream_readl(azx_dev, SD_CTL); | |
143 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
144 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
145 | if (!bus->snoop) | |
146 | val |= SD_CTL_TRAFFIC_PRIO; | |
147 | snd_hdac_stream_writel(azx_dev, SD_CTL, val); | |
148 | ||
149 | /* program the length of samples in cyclic buffer */ | |
150 | snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
151 | ||
152 | /* program the stream format */ | |
153 | /* this value needs to be the same as the one programmed */ | |
154 | snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
155 | ||
156 | /* program the stream LVI (last valid index) of the BDL */ | |
157 | snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
158 | ||
159 | /* program the BDL address */ | |
160 | /* lower BDL address */ | |
161 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
162 | /* upper BDL address */ | |
163 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, | |
164 | upper_32_bits(azx_dev->bdl.addr)); | |
165 | ||
166 | /* enable the position buffer */ | |
167 | if (bus->use_posbuf && bus->posbuf.addr) { | |
168 | if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) | |
169 | snd_hdac_chip_writel(bus, DPLBASE, | |
170 | (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); | |
171 | } | |
172 | ||
173 | /* set the interrupt enable bits in the descriptor control register */ | |
174 | snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); | |
175 | ||
176 | if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK) | |
177 | azx_dev->fifo_size = | |
178 | snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; | |
179 | else | |
180 | azx_dev->fifo_size = 0; | |
181 | ||
182 | /* when LPIB delay correction gives a small negative value, | |
183 | * we ignore it; currently set the threshold statically to | |
184 | * 64 frames | |
185 | */ | |
186 | if (runtime->period_size > 64) | |
187 | azx_dev->delay_negative_threshold = | |
188 | -frames_to_bytes(runtime, 64); | |
189 | else | |
190 | azx_dev->delay_negative_threshold = 0; | |
191 | ||
192 | /* wallclk has 24Mhz clock source */ | |
193 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
194 | runtime->rate) * 1000); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); | |
199 | ||
200 | /** | |
201 | * snd_hdac_stream_cleanup - cleanup a stream | |
202 | * @azx_dev: HD-audio core stream to clean up | |
203 | */ | |
204 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) | |
205 | { | |
206 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
207 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
208 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
209 | azx_dev->bufsize = 0; | |
210 | azx_dev->period_bytes = 0; | |
211 | azx_dev->format_val = 0; | |
212 | } | |
213 | EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); | |
214 | ||
215 | /** | |
216 | * snd_hdac_stream_assign - assign a stream for the PCM | |
217 | * @bus: HD-audio core bus | |
218 | * @substream: PCM substream to assign | |
219 | * | |
220 | * Look for an unused stream for the given PCM substream, assign it | |
221 | * and return the stream object. If no stream is free, returns NULL. | |
222 | * The function tries to keep using the same stream object when it's used | |
223 | * beforehand. Also, when bus->reverse_assign flag is set, the last free | |
224 | * or matching entry is returned. This is needed for some strange codecs. | |
225 | */ | |
226 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
227 | struct snd_pcm_substream *substream) | |
228 | { | |
229 | struct hdac_stream *azx_dev; | |
230 | struct hdac_stream *res = NULL; | |
231 | ||
232 | /* make a non-zero unique key for the substream */ | |
233 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
234 | (substream->stream + 1); | |
235 | ||
236 | list_for_each_entry(azx_dev, &bus->stream_list, list) { | |
237 | if (azx_dev->direction != substream->stream) | |
238 | continue; | |
239 | if (azx_dev->opened) | |
240 | continue; | |
241 | if (azx_dev->assigned_key == key) { | |
242 | res = azx_dev; | |
243 | break; | |
244 | } | |
245 | if (!res || bus->reverse_assign) | |
246 | res = azx_dev; | |
247 | } | |
248 | if (res) { | |
249 | spin_lock_irq(&bus->reg_lock); | |
250 | res->opened = 1; | |
251 | res->running = 0; | |
252 | res->assigned_key = key; | |
253 | res->substream = substream; | |
254 | spin_unlock_irq(&bus->reg_lock); | |
255 | } | |
256 | return res; | |
257 | } | |
258 | EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); | |
259 | ||
260 | /** | |
261 | * snd_hdac_stream_release - release the assigned stream | |
262 | * @azx_dev: HD-audio core stream to release | |
263 | * | |
264 | * Release the stream that has been assigned by snd_hdac_stream_assign(). | |
265 | */ | |
266 | void snd_hdac_stream_release(struct hdac_stream *azx_dev) | |
267 | { | |
268 | struct hdac_bus *bus = azx_dev->bus; | |
269 | ||
270 | spin_lock_irq(&bus->reg_lock); | |
271 | azx_dev->opened = 0; | |
272 | azx_dev->running = 0; | |
273 | azx_dev->substream = NULL; | |
274 | spin_unlock_irq(&bus->reg_lock); | |
275 | } | |
276 | EXPORT_SYMBOL_GPL(snd_hdac_stream_release); | |
277 | ||
278 | /* | |
279 | * set up a BDL entry | |
280 | */ | |
281 | static int setup_bdle(struct hdac_bus *bus, | |
282 | struct snd_dma_buffer *dmab, | |
283 | struct hdac_stream *azx_dev, __le32 **bdlp, | |
284 | int ofs, int size, int with_ioc) | |
285 | { | |
286 | __le32 *bdl = *bdlp; | |
287 | ||
288 | while (size > 0) { | |
289 | dma_addr_t addr; | |
290 | int chunk; | |
291 | ||
292 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
293 | return -EINVAL; | |
294 | ||
295 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
296 | /* program the address field of the BDL entry */ | |
297 | bdl[0] = cpu_to_le32((u32)addr); | |
298 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
299 | /* program the size field of the BDL entry */ | |
300 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
301 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
302 | if (bus->align_bdle_4k) { | |
303 | u32 remain = 0x1000 - (ofs & 0xfff); | |
304 | ||
305 | if (chunk > remain) | |
306 | chunk = remain; | |
307 | } | |
308 | bdl[2] = cpu_to_le32(chunk); | |
309 | /* program the IOC to enable interrupt | |
310 | * only when the whole fragment is processed | |
311 | */ | |
312 | size -= chunk; | |
313 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
314 | bdl += 4; | |
315 | azx_dev->frags++; | |
316 | ofs += chunk; | |
317 | } | |
318 | *bdlp = bdl; | |
319 | return ofs; | |
320 | } | |
321 | ||
322 | /** | |
323 | * snd_hdac_stream_setup_periods - set up BDL entries | |
324 | * @azx_dev: HD-audio core stream to set up | |
325 | * | |
326 | * Set up the buffer descriptor table of the given stream based on the | |
327 | * period and buffer sizes of the assigned PCM substream. | |
328 | */ | |
329 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) | |
330 | { | |
331 | struct hdac_bus *bus = azx_dev->bus; | |
332 | struct snd_pcm_substream *substream = azx_dev->substream; | |
333 | struct snd_pcm_runtime *runtime = substream->runtime; | |
334 | __le32 *bdl; | |
335 | int i, ofs, periods, period_bytes; | |
336 | int pos_adj, pos_align; | |
337 | ||
338 | /* reset BDL address */ | |
339 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
340 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
341 | ||
342 | period_bytes = azx_dev->period_bytes; | |
343 | periods = azx_dev->bufsize / period_bytes; | |
344 | ||
345 | /* program the initial BDL entries */ | |
346 | bdl = (__le32 *)azx_dev->bdl.area; | |
347 | ofs = 0; | |
348 | azx_dev->frags = 0; | |
349 | ||
350 | pos_adj = bus->bdl_pos_adj; | |
351 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { | |
352 | pos_align = pos_adj; | |
353 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; | |
354 | if (!pos_adj) | |
355 | pos_adj = pos_align; | |
356 | else | |
357 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
358 | pos_align; | |
359 | pos_adj = frames_to_bytes(runtime, pos_adj); | |
360 | if (pos_adj >= period_bytes) { | |
361 | dev_warn(bus->dev, "Too big adjustment %d\n", | |
362 | pos_adj); | |
363 | pos_adj = 0; | |
364 | } else { | |
365 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
366 | azx_dev, | |
367 | &bdl, ofs, pos_adj, true); | |
368 | if (ofs < 0) | |
369 | goto error; | |
370 | } | |
371 | } else | |
372 | pos_adj = 0; | |
373 | ||
374 | for (i = 0; i < periods; i++) { | |
375 | if (i == periods - 1 && pos_adj) | |
376 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
377 | azx_dev, &bdl, ofs, | |
378 | period_bytes - pos_adj, 0); | |
379 | else | |
380 | ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), | |
381 | azx_dev, &bdl, ofs, | |
382 | period_bytes, | |
383 | !azx_dev->no_period_wakeup); | |
384 | if (ofs < 0) | |
385 | goto error; | |
386 | } | |
387 | return 0; | |
388 | ||
389 | error: | |
390 | dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", | |
391 | azx_dev->bufsize, period_bytes); | |
392 | return -EINVAL; | |
393 | } | |
394 | EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); | |
395 | ||
396 | static cycle_t azx_cc_read(const struct cyclecounter *cc) | |
397 | { | |
398 | struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); | |
399 | ||
400 | return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); | |
401 | } | |
402 | ||
403 | static void azx_timecounter_init(struct hdac_stream *azx_dev, | |
404 | bool force, cycle_t last) | |
405 | { | |
406 | struct timecounter *tc = &azx_dev->tc; | |
407 | struct cyclecounter *cc = &azx_dev->cc; | |
408 | u64 nsec; | |
409 | ||
410 | cc->read = azx_cc_read; | |
411 | cc->mask = CLOCKSOURCE_MASK(32); | |
412 | ||
413 | /* | |
414 | * Converting from 24 MHz to ns means applying a 125/3 factor. | |
415 | * To avoid any saturation issues in intermediate operations, | |
416 | * the 125 factor is applied first. The division is applied | |
417 | * last after reading the timecounter value. | |
418 | * Applying the 1/3 factor as part of the multiplication | |
419 | * requires at least 20 bits for a decent precision, however | |
420 | * overflows occur after about 4 hours or less, not a option. | |
421 | */ | |
422 | ||
423 | cc->mult = 125; /* saturation after 195 years */ | |
424 | cc->shift = 0; | |
425 | ||
426 | nsec = 0; /* audio time is elapsed time since trigger */ | |
427 | timecounter_init(tc, cc, nsec); | |
428 | if (force) { | |
429 | /* | |
430 | * force timecounter to use predefined value, | |
431 | * used for synchronized starts | |
432 | */ | |
433 | tc->cycle_last = last; | |
434 | } | |
435 | } | |
436 | ||
437 | /** | |
438 | * snd_hdac_stream_timecounter_init - initialize time counter | |
439 | * @azx_dev: HD-audio core stream (master stream) | |
440 | * @streams: bit flags of streams to set up | |
441 | * | |
442 | * Initializes the time counter of streams marked by the bit flags (each | |
443 | * bit corresponds to the stream index). | |
444 | * The trigger timestamp of PCM substream assigned to the given stream is | |
445 | * updated accordingly, too. | |
446 | */ | |
447 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
448 | unsigned int streams) | |
449 | { | |
450 | struct hdac_bus *bus = azx_dev->bus; | |
451 | struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; | |
452 | struct hdac_stream *s; | |
453 | bool inited = false; | |
454 | cycle_t cycle_last = 0; | |
455 | int i = 0; | |
456 | ||
457 | list_for_each_entry(s, &bus->stream_list, list) { | |
458 | if (streams & (1 << i)) { | |
459 | azx_timecounter_init(s, inited, cycle_last); | |
460 | if (!inited) { | |
461 | inited = true; | |
462 | cycle_last = s->tc.cycle_last; | |
463 | } | |
464 | } | |
465 | i++; | |
466 | } | |
467 | ||
468 | snd_pcm_gettime(runtime, &runtime->trigger_tstamp); | |
469 | runtime->trigger_tstamp_latched = true; | |
470 | } | |
471 | EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); | |
472 | ||
473 | /** | |
474 | * snd_hdac_stream_sync_trigger - turn on/off stream sync register | |
475 | * @azx_dev: HD-audio core stream (master stream) | |
476 | * @streams: bit flags of streams to sync | |
477 | */ | |
478 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
479 | unsigned int streams, unsigned int reg) | |
480 | { | |
481 | struct hdac_bus *bus = azx_dev->bus; | |
482 | unsigned int val; | |
483 | ||
484 | if (!reg) | |
485 | reg = AZX_REG_SSYNC; | |
486 | val = _snd_hdac_chip_read(l, bus, reg); | |
487 | if (set) | |
488 | val |= streams; | |
489 | else | |
490 | val &= ~streams; | |
491 | _snd_hdac_chip_write(l, bus, reg, val); | |
492 | } | |
493 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); | |
494 | ||
495 | /** | |
496 | * snd_hdac_stream_sync - sync with start/strop trigger operation | |
497 | * @azx_dev: HD-audio core stream (master stream) | |
498 | * @start: true = start, false = stop | |
499 | * @streams: bit flags of streams to sync | |
500 | * | |
501 | * For @start = true, wait until all FIFOs get ready. | |
502 | * For @start = false, wait until all RUN bits are cleared. | |
503 | */ | |
504 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
505 | unsigned int streams) | |
506 | { | |
507 | struct hdac_bus *bus = azx_dev->bus; | |
508 | int i, nwait, timeout; | |
509 | struct hdac_stream *s; | |
510 | ||
511 | for (timeout = 5000; timeout; timeout--) { | |
512 | nwait = 0; | |
513 | i = 0; | |
514 | list_for_each_entry(s, &bus->stream_list, list) { | |
515 | if (streams & (1 << i)) { | |
516 | if (start) { | |
517 | /* check FIFO gets ready */ | |
518 | if (!(snd_hdac_stream_readb(s, SD_STS) & | |
519 | SD_STS_FIFO_READY)) | |
520 | nwait++; | |
521 | } else { | |
522 | /* check RUN bit is cleared */ | |
523 | if (snd_hdac_stream_readb(s, SD_CTL) & | |
524 | SD_CTL_DMA_START) | |
525 | nwait++; | |
526 | } | |
527 | } | |
528 | i++; | |
529 | } | |
530 | if (!nwait) | |
531 | break; | |
532 | cpu_relax(); | |
533 | } | |
534 | } | |
535 | EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); | |
8f3f600b TI |
536 | |
537 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
538 | /** | |
539 | * snd_hdac_dsp_prepare - prepare for DSP loading | |
540 | * @azx_dev: HD-audio core stream used for DSP loading | |
541 | * @format: HD-audio stream format | |
542 | * @byte_size: data chunk byte size | |
543 | * @bufp: allocated buffer | |
544 | * | |
545 | * Allocate the buffer for the given size and set up the given stream for | |
546 | * DSP loading. Returns the stream tag (>= 0), or a negative error code. | |
547 | */ | |
548 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
549 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
550 | { | |
551 | struct hdac_bus *bus = azx_dev->bus; | |
552 | u32 *bdl; | |
553 | int err; | |
554 | ||
555 | snd_hdac_dsp_lock(azx_dev); | |
556 | spin_lock_irq(&bus->reg_lock); | |
557 | if (azx_dev->running || azx_dev->locked) { | |
558 | spin_unlock_irq(&bus->reg_lock); | |
559 | err = -EBUSY; | |
560 | goto unlock; | |
561 | } | |
562 | azx_dev->locked = true; | |
563 | spin_unlock_irq(&bus->reg_lock); | |
564 | ||
565 | err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG, | |
566 | byte_size, bufp); | |
567 | if (err < 0) | |
568 | goto err_alloc; | |
569 | ||
570 | azx_dev->bufsize = byte_size; | |
571 | azx_dev->period_bytes = byte_size; | |
572 | azx_dev->format_val = format; | |
573 | ||
574 | snd_hdac_stream_reset(azx_dev); | |
575 | ||
576 | /* reset BDL address */ | |
577 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
578 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
579 | ||
580 | azx_dev->frags = 0; | |
581 | bdl = (u32 *)azx_dev->bdl.area; | |
582 | err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); | |
583 | if (err < 0) | |
584 | goto error; | |
585 | ||
586 | snd_hdac_stream_setup(azx_dev); | |
587 | snd_hdac_dsp_unlock(azx_dev); | |
588 | return azx_dev->stream_tag; | |
589 | ||
590 | error: | |
591 | bus->io_ops->dma_free_pages(bus, bufp); | |
592 | err_alloc: | |
593 | spin_lock_irq(&bus->reg_lock); | |
594 | azx_dev->locked = false; | |
595 | spin_unlock_irq(&bus->reg_lock); | |
596 | unlock: | |
597 | snd_hdac_dsp_unlock(azx_dev); | |
598 | return err; | |
599 | } | |
600 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); | |
601 | ||
602 | /** | |
603 | * snd_hdac_dsp_trigger - start / stop DSP loading | |
604 | * @azx_dev: HD-audio core stream used for DSP loading | |
605 | * @start: trigger start or stop | |
606 | */ | |
607 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
608 | { | |
609 | if (start) | |
610 | snd_hdac_stream_start(azx_dev, true); | |
611 | else | |
612 | snd_hdac_stream_stop(azx_dev); | |
613 | } | |
614 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); | |
615 | ||
616 | /** | |
617 | * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal | |
618 | * @azx_dev: HD-audio core stream used for DSP loading | |
619 | * @dmab: buffer used by DSP loading | |
620 | */ | |
621 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
622 | struct snd_dma_buffer *dmab) | |
623 | { | |
624 | struct hdac_bus *bus = azx_dev->bus; | |
625 | ||
626 | if (!dmab->area || !azx_dev->locked) | |
627 | return; | |
628 | ||
629 | snd_hdac_dsp_lock(azx_dev); | |
630 | /* reset BDL address */ | |
631 | snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); | |
632 | snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); | |
633 | snd_hdac_stream_writel(azx_dev, SD_CTL, 0); | |
634 | azx_dev->bufsize = 0; | |
635 | azx_dev->period_bytes = 0; | |
636 | azx_dev->format_val = 0; | |
637 | ||
638 | bus->io_ops->dma_free_pages(bus, dmab); | |
639 | dmab->area = NULL; | |
640 | ||
641 | spin_lock_irq(&bus->reg_lock); | |
642 | azx_dev->locked = false; | |
643 | spin_unlock_irq(&bus->reg_lock); | |
644 | snd_hdac_dsp_unlock(azx_dev); | |
645 | } | |
646 | EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); | |
647 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |