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MIPS: Alchemy: remove dbdma compat macros
[deliverable/linux.git] / sound / oss / au1550_ac97.c
CommitLineData
1da177e4
LT		 1/*
2 * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
3 * Processor.
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * Mostly copied from the au1000.c driver and some from the
9 * PowerMac dbdma driver.
10 * We assume the processor can do memory coherent DMA.
11 *
12 * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 */
35
36#undef DEBUG
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/string.h>
40#include <linux/ioport.h>
41#include <linux/sched.h>
42#include <linux/delay.h>
43#include <linux/sound.h>
44#include <linux/slab.h>
45#include <linux/soundcard.h>
46#include <linux/init.h>
47#include <linux/interrupt.h>
48#include <linux/kernel.h>
49#include <linux/poll.h>
1da177e4
LT		 50#include <linux/bitops.h>
51#include <linux/spinlock.h>
52#include <linux/smp_lock.h>
53#include <linux/ac97_codec.h>
910f5d20
IM		 54#include <linux/mutex.h>
55
1da177e4
LT		 56#include <asm/io.h>
57#include <asm/uaccess.h>
58#include <asm/hardirq.h>
1da177e4
LT		 59#include <asm/mach-au1x00/au1xxx_psc.h>
60#include <asm/mach-au1x00/au1xxx_dbdma.h>
f2c780c1 61#include <asm/mach-au1x00/au1xxx.h>
1da177e4
LT		 62
63#undef OSS_DOCUMENTED_MIXER_SEMANTICS
64
65/* misc stuff */
66#define POLL_COUNT 0x50000
67#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
68
69/* The number of DBDMA ring descriptors to allocate. No sense making
70 * this too large....if you can't keep up with a few you aren't likely
71 * to be able to with lots of them, either.
72 */
73#define NUM_DBDMA_DESCRIPTORS 4
74
75#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
76
77/* Boot options
78 * 0 = no VRA, 1 = use VRA if codec supports it
79 */
80static int vra = 1;
8d3b33f6 81module_param(vra, bool, 0);
1da177e4
LT		 82MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
83
84static struct au1550_state {
85 /* soundcore stuff */
86 int dev_audio;
87
88 struct ac97_codec *codec;
89 unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
90 unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
91 int no_vra; /* do not use VRA */
92
93 spinlock_t lock;
910f5d20
IM		 94 struct mutex open_mutex;
95 struct mutex sem;
aeb5d727 96 fmode_t open_mode;
1da177e4
LT		 97 wait_queue_head_t open_wait;
98
99 struct dmabuf {
100 u32 dmanr;
101 unsigned sample_rate;
102 unsigned src_factor;
103 unsigned sample_size;
104 int num_channels;
105 int dma_bytes_per_sample;
106 int user_bytes_per_sample;
107 int cnt_factor;
108
109 void *rawbuf;
110 unsigned buforder;
111 unsigned numfrag;
112 unsigned fragshift;
113 void *nextIn;
114 void *nextOut;
115 int count;
116 unsigned total_bytes;
117 unsigned error;
118 wait_queue_head_t wait;
119
120 /* redundant, but makes calculations easier */
121 unsigned fragsize;
122 unsigned dma_fragsize;
123 unsigned dmasize;
124 unsigned dma_qcount;
125
126 /* OSS stuff */
127 unsigned mapped:1;
128 unsigned ready:1;
129 unsigned stopped:1;
130 unsigned ossfragshift;
131 int ossmaxfrags;
132 unsigned subdivision;
133 } dma_dac, dma_adc;
134} au1550_state;
135
136static unsigned
137ld2(unsigned int x)
138{
139 unsigned r = 0;
140
141 if (x >= 0x10000) {
142 x >>= 16;
143 r += 16;
144 }
145 if (x >= 0x100) {
146 x >>= 8;
147 r += 8;
148 }
149 if (x >= 0x10) {
150 x >>= 4;
151 r += 4;
152 }
153 if (x >= 4) {
154 x >>= 2;
155 r += 2;
156 }
157 if (x >= 2)
158 r++;
159 return r;
160}
161
162static void
163au1550_delay(int msec)
164{
165 unsigned long tmo;
166 signed long tmo2;
167
168 if (in_interrupt())
169 return;
170
171 tmo = jiffies + (msec * HZ) / 1000;
172 for (;;) {
173 tmo2 = tmo - jiffies;
174 if (tmo2 <= 0)
175 break;
176 schedule_timeout(tmo2);
177 }
178}
179
180static u16
181rdcodec(struct ac97_codec *codec, u8 addr)
182{
183 struct au1550_state *s = (struct au1550_state *)codec->private_data;
184 unsigned long flags;
185 u32 cmd, val;
186 u16 data;
187 int i;
188
189 spin_lock_irqsave(&s->lock, flags);
190
191 for (i = 0; i < POLL_COUNT; i++) {
192 val = au_readl(PSC_AC97STAT);
193 au_sync();
194 if (!(val & PSC_AC97STAT_CP))
195 break;
196 }
197 if (i == POLL_COUNT)
198 err("rdcodec: codec cmd pending expired!");
199
200 cmd = (u32)PSC_AC97CDC_INDX(addr);
201 cmd |= PSC_AC97CDC_RD; /* read command */
202 au_writel(cmd, PSC_AC97CDC);
203 au_sync();
204
205 /* now wait for the data
206 */
207 for (i = 0; i < POLL_COUNT; i++) {
208 val = au_readl(PSC_AC97STAT);
209 au_sync();
210 if (!(val & PSC_AC97STAT_CP))
211 break;
212 }
213 if (i == POLL_COUNT) {
214 err("rdcodec: read poll expired!");
5e37ed37
DP		 215 data = 0;
216 goto out;
1da177e4
LT		 217 }
218
219 /* wait for command done?
220 */
221 for (i = 0; i < POLL_COUNT; i++) {
222 val = au_readl(PSC_AC97EVNT);
223 au_sync();
224 if (val & PSC_AC97EVNT_CD)
225 break;
226 }
227 if (i == POLL_COUNT) {
228 err("rdcodec: read cmdwait expired!");
5e37ed37
DP		 229 data = 0;
230 goto out;
1da177e4
LT		 231 }
232
233 data = au_readl(PSC_AC97CDC) & 0xffff;
234 au_sync();
235
236 /* Clear command done event.
237 */
238 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
239 au_sync();
240
5e37ed37 241 out:
1da177e4
LT		 242 spin_unlock_irqrestore(&s->lock, flags);
243
244 return data;
245}
246
247
248static void
249wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
250{
251 struct au1550_state *s = (struct au1550_state *)codec->private_data;
252 unsigned long flags;
253 u32 cmd, val;
254 int i;
255
256 spin_lock_irqsave(&s->lock, flags);
257
258 for (i = 0; i < POLL_COUNT; i++) {
259 val = au_readl(PSC_AC97STAT);
260 au_sync();
261 if (!(val & PSC_AC97STAT_CP))
262 break;
263 }
264 if (i == POLL_COUNT)
265 err("wrcodec: codec cmd pending expired!");
266
267 cmd = (u32)PSC_AC97CDC_INDX(addr);
268 cmd |= (u32)data;
269 au_writel(cmd, PSC_AC97CDC);
270 au_sync();
271
272 for (i = 0; i < POLL_COUNT; i++) {
273 val = au_readl(PSC_AC97STAT);
274 au_sync();
275 if (!(val & PSC_AC97STAT_CP))
276 break;
277 }
278 if (i == POLL_COUNT)
279 err("wrcodec: codec cmd pending expired!");
280
281 for (i = 0; i < POLL_COUNT; i++) {
282 val = au_readl(PSC_AC97EVNT);
283 au_sync();
284 if (val & PSC_AC97EVNT_CD)
285 break;
286 }
287 if (i == POLL_COUNT)
288 err("wrcodec: read cmdwait expired!");
289
290 /* Clear command done event.
291 */
292 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
293 au_sync();
294
295 spin_unlock_irqrestore(&s->lock, flags);
296}
297
298static void
299waitcodec(struct ac97_codec *codec)
300{
301 u16 temp;
302 u32 val;
303 int i;
304
305 /* codec_wait is used to wait for a ready state after
306 * an AC97C_RESET.
307 */
308 au1550_delay(10);
309
310 /* first poll the CODEC_READY tag bit
311 */
312 for (i = 0; i < POLL_COUNT; i++) {
313 val = au_readl(PSC_AC97STAT);
314 au_sync();
315 if (val & PSC_AC97STAT_CR)
316 break;
317 }
318 if (i == POLL_COUNT) {
319 err("waitcodec: CODEC_READY poll expired!");
320 return;
321 }
322
323 /* get AC'97 powerdown control/status register
324 */
325 temp = rdcodec(codec, AC97_POWER_CONTROL);
326
327 /* If anything is powered down, power'em up
328 */
329 if (temp & 0x7f00) {
330 /* Power on
331 */
332 wrcodec(codec, AC97_POWER_CONTROL, 0);
333 au1550_delay(100);
334
335 /* Reread
336 */
337 temp = rdcodec(codec, AC97_POWER_CONTROL);
338 }
339
340 /* Check if Codec REF,ANL,DAC,ADC ready
341 */
342 if ((temp & 0x7f0f) != 0x000f)
343 err("codec reg 26 status (0x%x) not ready!!", temp);
344}
345
346/* stop the ADC before calling */
347static void
348set_adc_rate(struct au1550_state *s, unsigned rate)
349{
350 struct dmabuf *adc = &s->dma_adc;
351 struct dmabuf *dac = &s->dma_dac;
352 unsigned adc_rate, dac_rate;
353 u16 ac97_extstat;
354
355 if (s->no_vra) {
356 /* calc SRC factor
357 */
358 adc->src_factor = ((96000 / rate) + 1) >> 1;
359 adc->sample_rate = 48000 / adc->src_factor;
360 return;
361 }
362
363 adc->src_factor = 1;
364
365 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
366
367 rate = rate > 48000 ? 48000 : rate;
368
369 /* enable VRA
370 */
371 wrcodec(s->codec, AC97_EXTENDED_STATUS,
372 ac97_extstat | AC97_EXTSTAT_VRA);
373
374 /* now write the sample rate
375 */
376 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
377
378 /* read it back for actual supported rate
379 */
380 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
381
382 pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
383
384 /* some codec's don't allow unequal DAC and ADC rates, in which case
385 * writing one rate reg actually changes both.
386 */
387 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
388 if (dac->num_channels > 2)
389 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
390 if (dac->num_channels > 4)
391 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
392
393 adc->sample_rate = adc_rate;
394 dac->sample_rate = dac_rate;
395}
396
397/* stop the DAC before calling */
398static void
399set_dac_rate(struct au1550_state *s, unsigned rate)
400{
401 struct dmabuf *dac = &s->dma_dac;
402 struct dmabuf *adc = &s->dma_adc;
403 unsigned adc_rate, dac_rate;
404 u16 ac97_extstat;
405
406 if (s->no_vra) {
407 /* calc SRC factor
408 */
409 dac->src_factor = ((96000 / rate) + 1) >> 1;
410 dac->sample_rate = 48000 / dac->src_factor;
411 return;
412 }
413
414 dac->src_factor = 1;
415
416 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
417
418 rate = rate > 48000 ? 48000 : rate;
419
420 /* enable VRA
421 */
422 wrcodec(s->codec, AC97_EXTENDED_STATUS,
423 ac97_extstat | AC97_EXTSTAT_VRA);
424
425 /* now write the sample rate
426 */
427 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
428
429 /* I don't support different sample rates for multichannel,
430 * so make these channels the same.
431 */
432 if (dac->num_channels > 2)
433 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
434 if (dac->num_channels > 4)
435 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
436 /* read it back for actual supported rate
437 */
438 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
439
440 pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
441
442 /* some codec's don't allow unequal DAC and ADC rates, in which case
443 * writing one rate reg actually changes both.
444 */
445 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
446
447 dac->sample_rate = dac_rate;
448 adc->sample_rate = adc_rate;
449}
450
451static void
452stop_dac(struct au1550_state *s)
453{
454 struct dmabuf *db = &s->dma_dac;
455 u32 stat;
456 unsigned long flags;
457
458 if (db->stopped)
459 return;
460
461 spin_lock_irqsave(&s->lock, flags);
462
463 au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
464 au_sync();
465
466 /* Wait for Transmit Busy to show disabled.
467 */
468 do {
05090fc9 469 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 470 au_sync();
471 } while ((stat & PSC_AC97STAT_TB) != 0);
472
473 au1xxx_dbdma_reset(db->dmanr);
474
475 db->stopped = 1;
476
477 spin_unlock_irqrestore(&s->lock, flags);
478}
479
480static void
481stop_adc(struct au1550_state *s)
482{
483 struct dmabuf *db = &s->dma_adc;
484 unsigned long flags;
485 u32 stat;
486
487 if (db->stopped)
488 return;
489
490 spin_lock_irqsave(&s->lock, flags);
491
492 au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
493 au_sync();
494
495 /* Wait for Receive Busy to show disabled.
496 */
497 do {
05090fc9 498 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 499 au_sync();
500 } while ((stat & PSC_AC97STAT_RB) != 0);
501
502 au1xxx_dbdma_reset(db->dmanr);
503
504 db->stopped = 1;
505
506 spin_unlock_irqrestore(&s->lock, flags);
507}
508
509
510static void
511set_xmit_slots(int num_channels)
512{
513 u32 ac97_config, stat;
514
515 ac97_config = au_readl(PSC_AC97CFG);
516 au_sync();
517 ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
518 au_writel(ac97_config, PSC_AC97CFG);
519 au_sync();
520
521 switch (num_channels) {
522 case 6: /* stereo with surround and center/LFE,
523 * slots 3,4,6,7,8,9
524 */
525 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
526 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
527
528 case 4: /* stereo with surround, slots 3,4,7,8 */
529 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
530 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
531
532 case 2: /* stereo, slots 3,4 */
533 case 1: /* mono */
534 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
535 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
536 }
537
538 au_writel(ac97_config, PSC_AC97CFG);
539 au_sync();
540
541 ac97_config |= PSC_AC97CFG_DE_ENABLE;
542 au_writel(ac97_config, PSC_AC97CFG);
543 au_sync();
544
545 /* Wait for Device ready.
546 */
547 do {
05090fc9 548 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 549 au_sync();
550 } while ((stat & PSC_AC97STAT_DR) == 0);
551}
552
553static void
554set_recv_slots(int num_channels)
555{
556 u32 ac97_config, stat;
557
558 ac97_config = au_readl(PSC_AC97CFG);
559 au_sync();
560 ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
561 au_writel(ac97_config, PSC_AC97CFG);
562 au_sync();
563
564 /* Always enable slots 3 and 4 (stereo). Slot 6 is
565 * optional Mic ADC, which we don't support yet.
566 */
567 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
568 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
569
570 au_writel(ac97_config, PSC_AC97CFG);
571 au_sync();
572
573 ac97_config |= PSC_AC97CFG_DE_ENABLE;
574 au_writel(ac97_config, PSC_AC97CFG);
575 au_sync();
576
577 /* Wait for Device ready.
578 */
579 do {
05090fc9 580 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 581 au_sync();
582 } while ((stat & PSC_AC97STAT_DR) == 0);
583}
584
7b666653 585/* Hold spinlock for both start_dac() and start_adc() calls */
1da177e4
LT		 586static void
587start_dac(struct au1550_state *s)
588{
589 struct dmabuf *db = &s->dma_dac;
1da177e4
LT		 590
591 if (!db->stopped)
592 return;
593
1da177e4
LT		 594 set_xmit_slots(db->num_channels);
595 au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
596 au_sync();
597 au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
598 au_sync();
599
600 au1xxx_dbdma_start(db->dmanr);
601
602 db->stopped = 0;
1da177e4
LT		 603}
604
605static void
606start_adc(struct au1550_state *s)
607{
608 struct dmabuf *db = &s->dma_adc;
609 int i;
610
611 if (!db->stopped)
612 return;
613
614 /* Put two buffers on the ring to get things started.
615 */
616 for (i=0; i<2; i++) {
ea071cc7
ML		 617 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn,
618 db->dma_fragsize, DDMA_FLAGS_IE);
1da177e4
LT		 619
620 db->nextIn += db->dma_fragsize;
621 if (db->nextIn >= db->rawbuf + db->dmasize)
622 db->nextIn -= db->dmasize;
623 }
624
625 set_recv_slots(db->num_channels);
626 au1xxx_dbdma_start(db->dmanr);
627 au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
628 au_sync();
629 au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
630 au_sync();
631
632 db->stopped = 0;
633}
634
635static int
636prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
637{
638 unsigned user_bytes_per_sec;
639 unsigned bufs;
640 unsigned rate = db->sample_rate;
641
642 if (!db->rawbuf) {
643 db->ready = db->mapped = 0;
644 db->buforder = 5; /* 32 * PAGE_SIZE */
645 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
646 if (!db->rawbuf)
647 return -ENOMEM;
648 }
649
650 db->cnt_factor = 1;
651 if (db->sample_size == 8)
652 db->cnt_factor *= 2;
653 if (db->num_channels == 1)
654 db->cnt_factor *= 2;
655 db->cnt_factor *= db->src_factor;
656
657 db->count = 0;
658 db->dma_qcount = 0;
659 db->nextIn = db->nextOut = db->rawbuf;
660
661 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
662 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
663 2 : db->num_channels);
664
665 user_bytes_per_sec = rate * db->user_bytes_per_sample;
666 bufs = PAGE_SIZE << db->buforder;
667 if (db->ossfragshift) {
668 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
669 db->fragshift = ld2(user_bytes_per_sec/1000);
670 else
671 db->fragshift = db->ossfragshift;
672 } else {
673 db->fragshift = ld2(user_bytes_per_sec / 100 /
674 (db->subdivision ? db->subdivision : 1));
675 if (db->fragshift < 3)
676 db->fragshift = 3;
677 }
678
679 db->fragsize = 1 << db->fragshift;
680 db->dma_fragsize = db->fragsize * db->cnt_factor;
681 db->numfrag = bufs / db->dma_fragsize;
682
683 while (db->numfrag < 4 && db->fragshift > 3) {
684 db->fragshift--;
685 db->fragsize = 1 << db->fragshift;
686 db->dma_fragsize = db->fragsize * db->cnt_factor;
687 db->numfrag = bufs / db->dma_fragsize;
688 }
689
690 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
691 db->numfrag = db->ossmaxfrags;
692
693 db->dmasize = db->dma_fragsize * db->numfrag;
694 memset(db->rawbuf, 0, bufs);
695
696 pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
697 rate, db->sample_size, db->num_channels);
698 pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
699 db->fragsize, db->cnt_factor, db->dma_fragsize);
700 pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
701
702 db->ready = 1;
703 return 0;
704}
705
706static int
707prog_dmabuf_adc(struct au1550_state *s)
708{
709 stop_adc(s);
710 return prog_dmabuf(s, &s->dma_adc);
711
712}
713
714static int
715prog_dmabuf_dac(struct au1550_state *s)
716{
717 stop_dac(s);
718 return prog_dmabuf(s, &s->dma_dac);
719}
720
721
53e62d3a 722static void dac_dma_interrupt(int irq, void *dev_id)
1da177e4
LT		 723{
724 struct au1550_state *s = (struct au1550_state *) dev_id;
725 struct dmabuf *db = &s->dma_dac;
726 u32 ac97c_stat;
727
7b666653
SS		 728 spin_lock(&s->lock);
729
1da177e4
LT		 730 ac97c_stat = au_readl(PSC_AC97STAT);
731 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
732 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
733 db->dma_qcount--;
734
735 if (db->count >= db->fragsize) {
736 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
ea071cc7 737 db->fragsize, DDMA_FLAGS_IE) == 0) {
1da177e4
LT		 738 err("qcount < 2 and no ring room!");
739 }
740 db->nextOut += db->fragsize;
741 if (db->nextOut >= db->rawbuf + db->dmasize)
742 db->nextOut -= db->dmasize;
743 db->count -= db->fragsize;
744 db->total_bytes += db->dma_fragsize;
745 db->dma_qcount++;
746 }
747
748 /* wake up anybody listening */
749 if (waitqueue_active(&db->wait))
750 wake_up(&db->wait);
7b666653
SS		 751
752 spin_unlock(&s->lock);
1da177e4
LT		 753}
754
755
53e62d3a 756static void adc_dma_interrupt(int irq, void *dev_id)
1da177e4
LT		 757{
758 struct au1550_state *s = (struct au1550_state *)dev_id;
759 struct dmabuf *dp = &s->dma_adc;
760 u32 obytes;
761 char *obuf;
762
7b666653
SS		 763 spin_lock(&s->lock);
764
1da177e4
LT		 765 /* Pull the buffer from the dma queue.
766 */
767 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
768
769 if ((dp->count + obytes) > dp->dmasize) {
770 /* Overrun. Stop ADC and log the error
771 */
7b666653 772 spin_unlock(&s->lock);
1da177e4
LT		 773 stop_adc(s);
774 dp->error++;
775 err("adc overrun");
776 return;
777 }
778
779 /* Put a new empty buffer on the destination DMA.
780 */
ea071cc7
ML		 781 au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn,
782 dp->dma_fragsize, DDMA_FLAGS_IE);
1da177e4
LT		 783
784 dp->nextIn += dp->dma_fragsize;
785 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
786 dp->nextIn -= dp->dmasize;
787
788 dp->count += obytes;
789 dp->total_bytes += obytes;
790
791 /* wake up anybody listening
792 */
793 if (waitqueue_active(&dp->wait))
794 wake_up(&dp->wait);
795
7b666653 796 spin_unlock(&s->lock);
1da177e4
LT		 797}
798
799static loff_t
800au1550_llseek(struct file *file, loff_t offset, int origin)
801{
802 return -ESPIPE;
803}
804
805
806static int
807au1550_open_mixdev(struct inode *inode, struct file *file)
808{
809 file->private_data = &au1550_state;
810 return 0;
811}
812
813static int
814au1550_release_mixdev(struct inode *inode, struct file *file)
815{
816 return 0;
817}
818
819static int
820mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
821 unsigned long arg)
822{
823 return codec->mixer_ioctl(codec, cmd, arg);
824}
825
826static int
827au1550_ioctl_mixdev(struct inode *inode, struct file *file,
828 unsigned int cmd, unsigned long arg)
829{
830 struct au1550_state *s = (struct au1550_state *)file->private_data;
831 struct ac97_codec *codec = s->codec;
832
833 return mixdev_ioctl(codec, cmd, arg);
834}
835
836static /*const */ struct file_operations au1550_mixer_fops = {
837 owner:THIS_MODULE,
838 llseek:au1550_llseek,
839 ioctl:au1550_ioctl_mixdev,
840 open:au1550_open_mixdev,
841 release:au1550_release_mixdev,
842};
843
844static int
845drain_dac(struct au1550_state *s, int nonblock)
846{
847 unsigned long flags;
848 int count, tmo;
849
850 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
851 return 0;
852
853 for (;;) {
854 spin_lock_irqsave(&s->lock, flags);
855 count = s->dma_dac.count;
856 spin_unlock_irqrestore(&s->lock, flags);
857 if (count <= s->dma_dac.fragsize)
858 break;
859 if (signal_pending(current))
860 break;
861 if (nonblock)
862 return -EBUSY;
863 tmo = 1000 * count / (s->no_vra ?
864 48000 : s->dma_dac.sample_rate);
865 tmo /= s->dma_dac.dma_bytes_per_sample;
866 au1550_delay(tmo);
867 }
868 if (signal_pending(current))
869 return -ERESTARTSYS;
870 return 0;
871}
872
873static inline u8 S16_TO_U8(s16 ch)
874{
875 return (u8) (ch >> 8) + 0x80;
876}
877static inline s16 U8_TO_S16(u8 ch)
878{
879 return (s16) (ch - 0x80) << 8;
880}
881
882/*
883 * Translates user samples to dma buffer suitable for AC'97 DAC data:
884 * If mono, copy left channel to right channel in dma buffer.
885 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
886 * If interpolating (no VRA), duplicate every audio frame src_factor times.
887 */
888static int
889translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
890 int dmacount)
891{
892 int sample, i;
893 int interp_bytes_per_sample;
894 int num_samples;
895 int mono = (db->num_channels == 1);
896 char usersample[12];
897 s16 ch, dmasample[6];
898
899 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
900 /* no translation necessary, just copy
901 */
902 if (copy_from_user(dmabuf, userbuf, dmacount))
903 return -EFAULT;
904 return dmacount;
905 }
906
907 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
908 num_samples = dmacount / interp_bytes_per_sample;
909
910 for (sample = 0; sample < num_samples; sample++) {
911 if (copy_from_user(usersample, userbuf,
912 db->user_bytes_per_sample)) {
913 return -EFAULT;
914 }
915
916 for (i = 0; i < db->num_channels; i++) {
917 if (db->sample_size == 8)
918 ch = U8_TO_S16(usersample[i]);
919 else
920 ch = *((s16 *) (&usersample[i * 2]));
921 dmasample[i] = ch;
922 if (mono)
923 dmasample[i + 1] = ch; /* right channel */
924 }
925
926 /* duplicate every audio frame src_factor times
927 */
928 for (i = 0; i < db->src_factor; i++)
929 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
930
931 userbuf += db->user_bytes_per_sample;
932 dmabuf += interp_bytes_per_sample;
933 }
934
935 return num_samples * interp_bytes_per_sample;
936}
937
938/*
939 * Translates AC'97 ADC samples to user buffer:
940 * If mono, send only left channel to user buffer.
941 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
942 * If decimating (no VRA), skip over src_factor audio frames.
943 */
944static int
945translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
946 int dmacount)
947{
948 int sample, i;
949 int interp_bytes_per_sample;
950 int num_samples;
951 int mono = (db->num_channels == 1);
952 char usersample[12];
953
954 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
955 /* no translation necessary, just copy
956 */
957 if (copy_to_user(userbuf, dmabuf, dmacount))
958 return -EFAULT;
959 return dmacount;
960 }
961
962 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
963 num_samples = dmacount / interp_bytes_per_sample;
964
965 for (sample = 0; sample < num_samples; sample++) {
966 for (i = 0; i < db->num_channels; i++) {
967 if (db->sample_size == 8)
968 usersample[i] =
969 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
970 else
971 *((s16 *) (&usersample[i * 2])) =
972 *((s16 *) (&dmabuf[i * 2]));
973 }
974
975 if (copy_to_user(userbuf, usersample,
976 db->user_bytes_per_sample)) {
977 return -EFAULT;
978 }
979
980 userbuf += db->user_bytes_per_sample;
981 dmabuf += interp_bytes_per_sample;
982 }
983
984 return num_samples * interp_bytes_per_sample;
985}
986
987/*
988 * Copy audio data to/from user buffer from/to dma buffer, taking care
989 * that we wrap when reading/writing the dma buffer. Returns actual byte
990 * count written to or read from the dma buffer.
991 */
992static int
993copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
994{
995 char *bufptr = to_user ? db->nextOut : db->nextIn;
996 char *bufend = db->rawbuf + db->dmasize;
997 int cnt, ret;
998
999 if (bufptr + count > bufend) {
1000 int partial = (int) (bufend - bufptr);
1001 if (to_user) {
1002 if ((cnt = translate_to_user(db, userbuf,
1003 bufptr, partial)) < 0)
1004 return cnt;
1005 ret = cnt;
1006 if ((cnt = translate_to_user(db, userbuf + partial,
1007 db->rawbuf,
1008 count - partial)) < 0)
1009 return cnt;
1010 ret += cnt;
1011 } else {
1012 if ((cnt = translate_from_user(db, bufptr, userbuf,
1013 partial)) < 0)
1014 return cnt;
1015 ret = cnt;
1016 if ((cnt = translate_from_user(db, db->rawbuf,
1017 userbuf + partial,
1018 count - partial)) < 0)
1019 return cnt;
1020 ret += cnt;
1021 }
1022 } else {
1023 if (to_user)
1024 ret = translate_to_user(db, userbuf, bufptr, count);
1025 else
1026 ret = translate_from_user(db, bufptr, userbuf, count);
1027 }
1028
1029 return ret;
1030}
1031
1032
1033static ssize_t
1034au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1035{
1036 struct au1550_state *s = (struct au1550_state *)file->private_data;
1037 struct dmabuf *db = &s->dma_adc;
1038 DECLARE_WAITQUEUE(wait, current);
1039 ssize_t ret;
1040 unsigned long flags;
1041 int cnt, usercnt, avail;
1042
1043 if (db->mapped)
1044 return -ENXIO;
1045 if (!access_ok(VERIFY_WRITE, buffer, count))
1046 return -EFAULT;
1047 ret = 0;
1048
1049 count *= db->cnt_factor;
1050
910f5d20 1051 mutex_lock(&s->sem);
1da177e4
LT		 1052 add_wait_queue(&db->wait, &wait);
1053
1054 while (count > 0) {
1055 /* wait for samples in ADC dma buffer
1056 */
1057 do {
7b666653 1058 spin_lock_irqsave(&s->lock, flags);
1da177e4
LT		 1059 if (db->stopped)
1060 start_adc(s);
1da177e4
LT		 1061 avail = db->count;
1062 if (avail <= 0)
1063 __set_current_state(TASK_INTERRUPTIBLE);
1064 spin_unlock_irqrestore(&s->lock, flags);
1065 if (avail <= 0) {
1066 if (file->f_flags & O_NONBLOCK) {
1067 if (!ret)
1068 ret = -EAGAIN;
1069 goto out;
1070 }
910f5d20 1071 mutex_unlock(&s->sem);
1da177e4
LT		 1072 schedule();
1073 if (signal_pending(current)) {
1074 if (!ret)
1075 ret = -ERESTARTSYS;
1076 goto out2;
1077 }
910f5d20 1078 mutex_lock(&s->sem);
1da177e4
LT		 1079 }
1080 } while (avail <= 0);
1081
1082 /* copy from nextOut to user
1083 */
1084 if ((cnt = copy_dmabuf_user(db, buffer,
1085 count > avail ?
1086 avail : count, 1)) < 0) {
1087 if (!ret)
1088 ret = -EFAULT;
1089 goto out;
1090 }
1091
1092 spin_lock_irqsave(&s->lock, flags);
1093 db->count -= cnt;
1094 db->nextOut += cnt;
1095 if (db->nextOut >= db->rawbuf + db->dmasize)
1096 db->nextOut -= db->dmasize;
1097 spin_unlock_irqrestore(&s->lock, flags);
1098
1099 count -= cnt;
1100 usercnt = cnt / db->cnt_factor;
1101 buffer += usercnt;
1102 ret += usercnt;
1103 } /* while (count > 0) */
1104
1105out:
910f5d20 1106 mutex_unlock(&s->sem);
1da177e4
LT		 1107out2:
1108 remove_wait_queue(&db->wait, &wait);
1109 set_current_state(TASK_RUNNING);
1110 return ret;
1111}
1112
1113static ssize_t
1114au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1115{
1116 struct au1550_state *s = (struct au1550_state *)file->private_data;
1117 struct dmabuf *db = &s->dma_dac;
1118 DECLARE_WAITQUEUE(wait, current);
1119 ssize_t ret = 0;
1120 unsigned long flags;
1121 int cnt, usercnt, avail;
1122
1123 pr_debug("write: count=%d\n", count);
1124
1125 if (db->mapped)
1126 return -ENXIO;
1127 if (!access_ok(VERIFY_READ, buffer, count))
1128 return -EFAULT;
1129
1130 count *= db->cnt_factor;
1131
910f5d20 1132 mutex_lock(&s->sem);
1da177e4
LT		 1133 add_wait_queue(&db->wait, &wait);
1134
1135 while (count > 0) {
1136 /* wait for space in playback buffer
1137 */
1138 do {
1139 spin_lock_irqsave(&s->lock, flags);
1140 avail = (int) db->dmasize - db->count;
1141 if (avail <= 0)
1142 __set_current_state(TASK_INTERRUPTIBLE);
1143 spin_unlock_irqrestore(&s->lock, flags);
1144 if (avail <= 0) {
1145 if (file->f_flags & O_NONBLOCK) {
1146 if (!ret)
1147 ret = -EAGAIN;
1148 goto out;
1149 }
910f5d20 1150 mutex_unlock(&s->sem);
1da177e4
LT		 1151 schedule();
1152 if (signal_pending(current)) {
1153 if (!ret)
1154 ret = -ERESTARTSYS;
1155 goto out2;
1156 }
910f5d20 1157 mutex_lock(&s->sem);
1da177e4
LT		 1158 }
1159 } while (avail <= 0);
1160
1161 /* copy from user to nextIn
1162 */
1163 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1164 count > avail ?
1165 avail : count, 0)) < 0) {
1166 if (!ret)
1167 ret = -EFAULT;
1168 goto out;
1169 }
1170
1171 spin_lock_irqsave(&s->lock, flags);
1172 db->count += cnt;
1173 db->nextIn += cnt;
1174 if (db->nextIn >= db->rawbuf + db->dmasize)
1175 db->nextIn -= db->dmasize;
1176
1177 /* If the data is available, we want to keep two buffers
1178 * on the dma queue. If the queue count reaches zero,
1179 * we know the dma has stopped.
1180 */
1181 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
ea071cc7
ML		 1182 if (au1xxx_dbdma_put_source(db->dmanr,
1183 db->nextOut, db->fragsize, DDMA_FLAGS_IE) == 0) {
1da177e4
LT		 1184 err("qcount < 2 and no ring room!");
1185 }
1186 db->nextOut += db->fragsize;
1187 if (db->nextOut >= db->rawbuf + db->dmasize)
1188 db->nextOut -= db->dmasize;
1189 db->total_bytes += db->dma_fragsize;
1190 if (db->dma_qcount == 0)
1191 start_dac(s);
1192 db->dma_qcount++;
1193 }
1194 spin_unlock_irqrestore(&s->lock, flags);
1195
1196 count -= cnt;
1197 usercnt = cnt / db->cnt_factor;
1198 buffer += usercnt;
1199 ret += usercnt;
1200 } /* while (count > 0) */
1201
1202out:
910f5d20 1203 mutex_unlock(&s->sem);
1da177e4
LT		 1204out2:
1205 remove_wait_queue(&db->wait, &wait);
1206 set_current_state(TASK_RUNNING);
1207 return ret;
1208}
1209
1210
1211/* No kernel lock - we have our own spinlock */
1212static unsigned int
1213au1550_poll(struct file *file, struct poll_table_struct *wait)
1214{
1215 struct au1550_state *s = (struct au1550_state *)file->private_data;
1216 unsigned long flags;
1217 unsigned int mask = 0;
1218
1219 if (file->f_mode & FMODE_WRITE) {
1220 if (!s->dma_dac.ready)
1221 return 0;
1222 poll_wait(file, &s->dma_dac.wait, wait);
1223 }
1224 if (file->f_mode & FMODE_READ) {
1225 if (!s->dma_adc.ready)
1226 return 0;
1227 poll_wait(file, &s->dma_adc.wait, wait);
1228 }
1229
1230 spin_lock_irqsave(&s->lock, flags);
1231
1232 if (file->f_mode & FMODE_READ) {
1233 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1234 mask |= POLLIN | POLLRDNORM;
1235 }
1236 if (file->f_mode & FMODE_WRITE) {
1237 if (s->dma_dac.mapped) {
1238 if (s->dma_dac.count >=
1239 (signed)s->dma_dac.dma_fragsize)
1240 mask |= POLLOUT | POLLWRNORM;
1241 } else {
1242 if ((signed) s->dma_dac.dmasize >=
1243 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1244 mask |= POLLOUT | POLLWRNORM;
1245 }
1246 }
1247 spin_unlock_irqrestore(&s->lock, flags);
1248 return mask;
1249}
1250
1251static int
1252au1550_mmap(struct file *file, struct vm_area_struct *vma)
1253{
1254 struct au1550_state *s = (struct au1550_state *)file->private_data;
1255 struct dmabuf *db;
1256 unsigned long size;
1257 int ret = 0;
1258
1259 lock_kernel();
910f5d20 1260 mutex_lock(&s->sem);
1da177e4
LT		 1261 if (vma->vm_flags & VM_WRITE)
1262 db = &s->dma_dac;
1263 else if (vma->vm_flags & VM_READ)
1264 db = &s->dma_adc;
1265 else {
1266 ret = -EINVAL;
1267 goto out;
1268 }
1269 if (vma->vm_pgoff != 0) {
1270 ret = -EINVAL;
1271 goto out;
1272 }
1273 size = vma->vm_end - vma->vm_start;
1274 if (size > (PAGE_SIZE << db->buforder)) {
1275 ret = -EINVAL;
1276 goto out;
1277 }
1278 if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1279 size, vma->vm_page_prot)) {
1280 ret = -EAGAIN;
1281 goto out;
1282 }
1283 vma->vm_flags &= ~VM_IO;
1284 db->mapped = 1;
1285out:
910f5d20 1286 mutex_unlock(&s->sem);
1da177e4
LT		 1287 unlock_kernel();
1288 return ret;
1289}
1290
1291#ifdef DEBUG
1292static struct ioctl_str_t {
1293 unsigned int cmd;
1294 const char *str;
1295} ioctl_str[] = {
1296 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1297 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1298 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1299 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1300 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1301 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1302 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1303 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1304 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1305 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1306 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1307 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1308 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1309 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1310 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1311 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1312 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1313 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1314 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1315 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1316 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1317 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1318 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1319 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1320 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1321 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1322 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1323 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1324 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1325 {OSS_GETVERSION, "OSS_GETVERSION"},
1326 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1327 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1328 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1329 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1330};
1331#endif
1332
1333static int
1334dma_count_done(struct dmabuf *db)
1335{
1336 if (db->stopped)
1337 return 0;
1338
1339 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1340}
1341
1342
1343static int
1344au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1345 unsigned long arg)
1346{
1347 struct au1550_state *s = (struct au1550_state *)file->private_data;
1348 unsigned long flags;
1349 audio_buf_info abinfo;
1350 count_info cinfo;
1351 int count;
1352 int val, mapped, ret, diff;
1353
1354 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1355 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1356
1357#ifdef DEBUG
8b5925fd 1358 for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1da177e4
LT		 1359 if (ioctl_str[count].cmd == cmd)
1360 break;
1361 }
8b5925fd 1362 if (count < ARRAY_SIZE(ioctl_str))
1da177e4
LT		 1363 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1364 else
1365 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1366#endif
1367
1368 switch (cmd) {
1369 case OSS_GETVERSION:
1370 return put_user(SOUND_VERSION, (int *) arg);
1371
1372 case SNDCTL_DSP_SYNC:
1373 if (file->f_mode & FMODE_WRITE)
1374 return drain_dac(s, file->f_flags & O_NONBLOCK);
1375 return 0;
1376
1377 case SNDCTL_DSP_SETDUPLEX:
1378 return 0;
1379
1380 case SNDCTL_DSP_GETCAPS:
1381 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1382 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1383
1384 case SNDCTL_DSP_RESET:
1385 if (file->f_mode & FMODE_WRITE) {
1386 stop_dac(s);
1387 synchronize_irq();
1388 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1389 s->dma_dac.nextIn = s->dma_dac.nextOut =
1390 s->dma_dac.rawbuf;
1391 }
1392 if (file->f_mode & FMODE_READ) {
1393 stop_adc(s);
1394 synchronize_irq();
1395 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1396 s->dma_adc.nextIn = s->dma_adc.nextOut =
1397 s->dma_adc.rawbuf;
1398 }
1399 return 0;
1400
1401 case SNDCTL_DSP_SPEED:
1402 if (get_user(val, (int *) arg))
1403 return -EFAULT;
1404 if (val >= 0) {
1405 if (file->f_mode & FMODE_READ) {
1406 stop_adc(s);
1407 set_adc_rate(s, val);
1408 }
1409 if (file->f_mode & FMODE_WRITE) {
1410 stop_dac(s);
1411 set_dac_rate(s, val);
1412 }
1413 if (s->open_mode & FMODE_READ)
1414 if ((ret = prog_dmabuf_adc(s)))
1415 return ret;
1416 if (s->open_mode & FMODE_WRITE)
1417 if ((ret = prog_dmabuf_dac(s)))
1418 return ret;
1419 }
1420 return put_user((file->f_mode & FMODE_READ) ?
1421 s->dma_adc.sample_rate :
1422 s->dma_dac.sample_rate,
1423 (int *)arg);
1424
1425 case SNDCTL_DSP_STEREO:
1426 if (get_user(val, (int *) arg))
1427 return -EFAULT;
1428 if (file->f_mode & FMODE_READ) {
1429 stop_adc(s);
1430 s->dma_adc.num_channels = val ? 2 : 1;
1431 if ((ret = prog_dmabuf_adc(s)))
1432 return ret;
1433 }
1434 if (file->f_mode & FMODE_WRITE) {
1435 stop_dac(s);
1436 s->dma_dac.num_channels = val ? 2 : 1;
1437 if (s->codec_ext_caps & AC97_EXT_DACS) {
1438 /* disable surround and center/lfe in AC'97
1439 */
1440 u16 ext_stat = rdcodec(s->codec,
1441 AC97_EXTENDED_STATUS);
1442 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1443 ext_stat | (AC97_EXTSTAT_PRI |
1444 AC97_EXTSTAT_PRJ |
1445 AC97_EXTSTAT_PRK));
1446 }
1447 if ((ret = prog_dmabuf_dac(s)))
1448 return ret;
1449 }
1450 return 0;
1451
1452 case SNDCTL_DSP_CHANNELS:
1453 if (get_user(val, (int *) arg))
1454 return -EFAULT;
1455 if (val != 0) {
1456 if (file->f_mode & FMODE_READ) {
1457 if (val < 0 || val > 2)
1458 return -EINVAL;
1459 stop_adc(s);
1460 s->dma_adc.num_channels = val;
1461 if ((ret = prog_dmabuf_adc(s)))
1462 return ret;
1463 }
1464 if (file->f_mode & FMODE_WRITE) {
1465 switch (val) {
1466 case 1:
1467 case 2:
1468 break;
1469 case 3:
1470 case 5:
1471 return -EINVAL;
1472 case 4:
1473 if (!(s->codec_ext_caps &
1474 AC97_EXTID_SDAC))
1475 return -EINVAL;
1476 break;
1477 case 6:
1478 if ((s->codec_ext_caps &
1479 AC97_EXT_DACS) != AC97_EXT_DACS)
1480 return -EINVAL;
1481 break;
1482 default:
1483 return -EINVAL;
1484 }
1485
1486 stop_dac(s);
1487 if (val <= 2 &&
1488 (s->codec_ext_caps & AC97_EXT_DACS)) {
1489 /* disable surround and center/lfe
1490 * channels in AC'97
1491 */
1492 u16 ext_stat =
1493 rdcodec(s->codec,
1494 AC97_EXTENDED_STATUS);
1495 wrcodec(s->codec,
1496 AC97_EXTENDED_STATUS,
1497 ext_stat | (AC97_EXTSTAT_PRI |
1498 AC97_EXTSTAT_PRJ |
1499 AC97_EXTSTAT_PRK));
1500 } else if (val >= 4) {
1501 /* enable surround, center/lfe
1502 * channels in AC'97
1503 */
1504 u16 ext_stat =
1505 rdcodec(s->codec,
1506 AC97_EXTENDED_STATUS);
1507 ext_stat &= ~AC97_EXTSTAT_PRJ;
1508 if (val == 6)
1509 ext_stat &=
1510 ~(AC97_EXTSTAT_PRI |
1511 AC97_EXTSTAT_PRK);
1512 wrcodec(s->codec,
1513 AC97_EXTENDED_STATUS,
1514 ext_stat);
1515 }
1516
1517 s->dma_dac.num_channels = val;
1518 if ((ret = prog_dmabuf_dac(s)))
1519 return ret;
1520 }
1521 }
1522 return put_user(val, (int *) arg);
1523
1524 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1525 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1526
1527 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1528 if (get_user(val, (int *) arg))
1529 return -EFAULT;
1530 if (val != AFMT_QUERY) {
1531 if (file->f_mode & FMODE_READ) {
1532 stop_adc(s);
1533 if (val == AFMT_S16_LE)
1534 s->dma_adc.sample_size = 16;
1535 else {
1536 val = AFMT_U8;
1537 s->dma_adc.sample_size = 8;
1538 }
1539 if ((ret = prog_dmabuf_adc(s)))
1540 return ret;
1541 }
1542 if (file->f_mode & FMODE_WRITE) {
1543 stop_dac(s);
1544 if (val == AFMT_S16_LE)
1545 s->dma_dac.sample_size = 16;
1546 else {
1547 val = AFMT_U8;
1548 s->dma_dac.sample_size = 8;
1549 }
1550 if ((ret = prog_dmabuf_dac(s)))
1551 return ret;
1552 }
1553 } else {
1554 if (file->f_mode & FMODE_READ)
1555 val = (s->dma_adc.sample_size == 16) ?
1556 AFMT_S16_LE : AFMT_U8;
1557 else
1558 val = (s->dma_dac.sample_size == 16) ?
1559 AFMT_S16_LE : AFMT_U8;
1560 }
1561 return put_user(val, (int *) arg);
1562
1563 case SNDCTL_DSP_POST:
1564 return 0;
1565
1566 case SNDCTL_DSP_GETTRIGGER:
1567 val = 0;
1568 spin_lock_irqsave(&s->lock, flags);
1569 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1570 val |= PCM_ENABLE_INPUT;
1571 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1572 val |= PCM_ENABLE_OUTPUT;
1573 spin_unlock_irqrestore(&s->lock, flags);
1574 return put_user(val, (int *) arg);
1575
1576 case SNDCTL_DSP_SETTRIGGER:
1577 if (get_user(val, (int *) arg))
1578 return -EFAULT;
1579 if (file->f_mode & FMODE_READ) {
7b666653
SS		 1580 if (val & PCM_ENABLE_INPUT) {
1581 spin_lock_irqsave(&s->lock, flags);
1da177e4 1582 start_adc(s);
7b666653
SS		 1583 spin_unlock_irqrestore(&s->lock, flags);
1584 } else
1da177e4
LT		 1585 stop_adc(s);
1586 }
1587 if (file->f_mode & FMODE_WRITE) {
7b666653
SS		 1588 if (val & PCM_ENABLE_OUTPUT) {
1589 spin_lock_irqsave(&s->lock, flags);
1da177e4 1590 start_dac(s);
7b666653
SS		 1591 spin_unlock_irqrestore(&s->lock, flags);
1592 } else
1da177e4
LT		 1593 stop_dac(s);
1594 }
1595 return 0;
1596
1597 case SNDCTL_DSP_GETOSPACE:
1598 if (!(file->f_mode & FMODE_WRITE))
1599 return -EINVAL;
1600 abinfo.fragsize = s->dma_dac.fragsize;
1601 spin_lock_irqsave(&s->lock, flags);
1602 count = s->dma_dac.count;
1603 count -= dma_count_done(&s->dma_dac);
1604 spin_unlock_irqrestore(&s->lock, flags);
1605 if (count < 0)
1606 count = 0;
1607 abinfo.bytes = (s->dma_dac.dmasize - count) /
1608 s->dma_dac.cnt_factor;
1609 abinfo.fragstotal = s->dma_dac.numfrag;
1610 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1611 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1612 return copy_to_user((void *) arg, &abinfo,
1613 sizeof(abinfo)) ? -EFAULT : 0;
1614
1615 case SNDCTL_DSP_GETISPACE:
1616 if (!(file->f_mode & FMODE_READ))
1617 return -EINVAL;
1618 abinfo.fragsize = s->dma_adc.fragsize;
1619 spin_lock_irqsave(&s->lock, flags);
1620 count = s->dma_adc.count;
1621 count += dma_count_done(&s->dma_adc);
1622 spin_unlock_irqrestore(&s->lock, flags);
1623 if (count < 0)
1624 count = 0;
1625 abinfo.bytes = count / s->dma_adc.cnt_factor;
1626 abinfo.fragstotal = s->dma_adc.numfrag;
1627 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1628 return copy_to_user((void *) arg, &abinfo,
1629 sizeof(abinfo)) ? -EFAULT : 0;
1630
1631 case SNDCTL_DSP_NONBLOCK:
db1dd4d3 1632 spin_lock(&file->f_lock);
1da177e4 1633 file->f_flags |= O_NONBLOCK;
db1dd4d3 1634 spin_unlock(&file->f_lock);
1da177e4
LT		 1635 return 0;
1636
1637 case SNDCTL_DSP_GETODELAY:
1638 if (!(file->f_mode & FMODE_WRITE))
1639 return -EINVAL;
1640 spin_lock_irqsave(&s->lock, flags);
1641 count = s->dma_dac.count;
1642 count -= dma_count_done(&s->dma_dac);
1643 spin_unlock_irqrestore(&s->lock, flags);
1644 if (count < 0)
1645 count = 0;
1646 count /= s->dma_dac.cnt_factor;
1647 return put_user(count, (int *) arg);
1648
1649 case SNDCTL_DSP_GETIPTR:
1650 if (!(file->f_mode & FMODE_READ))
1651 return -EINVAL;
1652 spin_lock_irqsave(&s->lock, flags);
1653 cinfo.bytes = s->dma_adc.total_bytes;
1654 count = s->dma_adc.count;
1655 if (!s->dma_adc.stopped) {
1656 diff = dma_count_done(&s->dma_adc);
1657 count += diff;
1658 cinfo.bytes += diff;
1659 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1660 virt_to_phys(s->dma_adc.rawbuf);
1661 } else
1662 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1663 virt_to_phys(s->dma_adc.rawbuf);
1664 if (s->dma_adc.mapped)
1665 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1666 spin_unlock_irqrestore(&s->lock, flags);
1667 if (count < 0)
1668 count = 0;
1669 cinfo.blocks = count >> s->dma_adc.fragshift;
1670 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1671
1672 case SNDCTL_DSP_GETOPTR:
1673 if (!(file->f_mode & FMODE_READ))
1674 return -EINVAL;
1675 spin_lock_irqsave(&s->lock, flags);
1676 cinfo.bytes = s->dma_dac.total_bytes;
1677 count = s->dma_dac.count;
1678 if (!s->dma_dac.stopped) {
1679 diff = dma_count_done(&s->dma_dac);
1680 count -= diff;
1681 cinfo.bytes += diff;
1682 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1683 virt_to_phys(s->dma_dac.rawbuf);
1684 } else
1685 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1686 virt_to_phys(s->dma_dac.rawbuf);
1687 if (s->dma_dac.mapped)
1688 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1689 spin_unlock_irqrestore(&s->lock, flags);
1690 if (count < 0)
1691 count = 0;
1692 cinfo.blocks = count >> s->dma_dac.fragshift;
1693 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1694
1695 case SNDCTL_DSP_GETBLKSIZE:
1696 if (file->f_mode & FMODE_WRITE)
1697 return put_user(s->dma_dac.fragsize, (int *) arg);
1698 else
1699 return put_user(s->dma_adc.fragsize, (int *) arg);
1700
1701 case SNDCTL_DSP_SETFRAGMENT:
1702 if (get_user(val, (int *) arg))
1703 return -EFAULT;
1704 if (file->f_mode & FMODE_READ) {
1705 stop_adc(s);
1706 s->dma_adc.ossfragshift = val & 0xffff;
1707 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1708 if (s->dma_adc.ossfragshift < 4)
1709 s->dma_adc.ossfragshift = 4;
1710 if (s->dma_adc.ossfragshift > 15)
1711 s->dma_adc.ossfragshift = 15;
1712 if (s->dma_adc.ossmaxfrags < 4)
1713 s->dma_adc.ossmaxfrags = 4;
1714 if ((ret = prog_dmabuf_adc(s)))
1715 return ret;
1716 }
1717 if (file->f_mode & FMODE_WRITE) {
1718 stop_dac(s);
1719 s->dma_dac.ossfragshift = val & 0xffff;
1720 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1721 if (s->dma_dac.ossfragshift < 4)
1722 s->dma_dac.ossfragshift = 4;
1723 if (s->dma_dac.ossfragshift > 15)
1724 s->dma_dac.ossfragshift = 15;
1725 if (s->dma_dac.ossmaxfrags < 4)
1726 s->dma_dac.ossmaxfrags = 4;
1727 if ((ret = prog_dmabuf_dac(s)))
1728 return ret;
1729 }
1730 return 0;
1731
1732 case SNDCTL_DSP_SUBDIVIDE:
1733 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1734 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1735 return -EINVAL;
1736 if (get_user(val, (int *) arg))
1737 return -EFAULT;
1738 if (val != 1 && val != 2 && val != 4)
1739 return -EINVAL;
1740 if (file->f_mode & FMODE_READ) {
1741 stop_adc(s);
1742 s->dma_adc.subdivision = val;
1743 if ((ret = prog_dmabuf_adc(s)))
1744 return ret;
1745 }
1746 if (file->f_mode & FMODE_WRITE) {
1747 stop_dac(s);
1748 s->dma_dac.subdivision = val;
1749 if ((ret = prog_dmabuf_dac(s)))
1750 return ret;
1751 }
1752 return 0;
1753
1754 case SOUND_PCM_READ_RATE:
1755 return put_user((file->f_mode & FMODE_READ) ?
1756 s->dma_adc.sample_rate :
1757 s->dma_dac.sample_rate,
1758 (int *)arg);
1759
1760 case SOUND_PCM_READ_CHANNELS:
1761 if (file->f_mode & FMODE_READ)
1762 return put_user(s->dma_adc.num_channels, (int *)arg);
1763 else
1764 return put_user(s->dma_dac.num_channels, (int *)arg);
1765
1766 case SOUND_PCM_READ_BITS:
1767 if (file->f_mode & FMODE_READ)
1768 return put_user(s->dma_adc.sample_size, (int *)arg);
1769 else
1770 return put_user(s->dma_dac.sample_size, (int *)arg);
1771
1772 case SOUND_PCM_WRITE_FILTER:
1773 case SNDCTL_DSP_SETSYNCRO:
1774 case SOUND_PCM_READ_FILTER:
1775 return -EINVAL;
1776 }
1777
1778 return mixdev_ioctl(s->codec, cmd, arg);
1779}
1780
1781
1782static int
1783au1550_open(struct inode *inode, struct file *file)
1784{
1785 int minor = MINOR(inode->i_rdev);
1786 DECLARE_WAITQUEUE(wait, current);
1787 struct au1550_state *s = &au1550_state;
1788 int ret;
1789
1790#ifdef DEBUG
1791 if (file->f_flags & O_NONBLOCK)
1792 pr_debug("open: non-blocking\n");
1793 else
1794 pr_debug("open: blocking\n");
1795#endif
1796
1797 file->private_data = s;
1798 /* wait for device to become free */
910f5d20 1799 mutex_lock(&s->open_mutex);
1da177e4
LT		 1800 while (s->open_mode & file->f_mode) {
1801 if (file->f_flags & O_NONBLOCK) {
910f5d20 1802 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1803 return -EBUSY;
1804 }
1805 add_wait_queue(&s->open_wait, &wait);
1806 __set_current_state(TASK_INTERRUPTIBLE);
910f5d20 1807 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1808 schedule();
1809 remove_wait_queue(&s->open_wait, &wait);
1810 set_current_state(TASK_RUNNING);
1811 if (signal_pending(current))
1812 return -ERESTARTSYS;
910f5d20 1813 mutex_lock(&s->open_mutex);
1da177e4
LT		 1814 }
1815
1816 stop_dac(s);
1817 stop_adc(s);
1818
1819 if (file->f_mode & FMODE_READ) {
1820 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1821 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1822 s->dma_adc.num_channels = 1;
1823 s->dma_adc.sample_size = 8;
1824 set_adc_rate(s, 8000);
1825 if ((minor & 0xf) == SND_DEV_DSP16)
1826 s->dma_adc.sample_size = 16;
1827 }
1828
1829 if (file->f_mode & FMODE_WRITE) {
1830 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1831 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1832 s->dma_dac.num_channels = 1;
1833 s->dma_dac.sample_size = 8;
1834 set_dac_rate(s, 8000);
1835 if ((minor & 0xf) == SND_DEV_DSP16)
1836 s->dma_dac.sample_size = 16;
1837 }
1838
1839 if (file->f_mode & FMODE_READ) {
1840 if ((ret = prog_dmabuf_adc(s)))
1841 return ret;
1842 }
1843 if (file->f_mode & FMODE_WRITE) {
1844 if ((ret = prog_dmabuf_dac(s)))
1845 return ret;
1846 }
1847
1848 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
910f5d20
IM		 1849 mutex_unlock(&s->open_mutex);
1850 mutex_init(&s->sem);
1da177e4
LT		 1851 return 0;
1852}
1853
1854static int
1855au1550_release(struct inode *inode, struct file *file)
1856{
1857 struct au1550_state *s = (struct au1550_state *)file->private_data;
1858
1859 lock_kernel();
1860
1861 if (file->f_mode & FMODE_WRITE) {
1862 unlock_kernel();
1863 drain_dac(s, file->f_flags & O_NONBLOCK);
1864 lock_kernel();
1865 }
1866
910f5d20 1867 mutex_lock(&s->open_mutex);
1da177e4
LT		 1868 if (file->f_mode & FMODE_WRITE) {
1869 stop_dac(s);
1870 kfree(s->dma_dac.rawbuf);
1871 s->dma_dac.rawbuf = NULL;
1872 }
1873 if (file->f_mode & FMODE_READ) {
1874 stop_adc(s);
1875 kfree(s->dma_adc.rawbuf);
1876 s->dma_adc.rawbuf = NULL;
1877 }
1878 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
910f5d20 1879 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1880 wake_up(&s->open_wait);
1881 unlock_kernel();
1882 return 0;
1883}
1884
1885static /*const */ struct file_operations au1550_audio_fops = {
1886 owner: THIS_MODULE,
1887 llseek: au1550_llseek,
1888 read: au1550_read,
1889 write: au1550_write,
1890 poll: au1550_poll,
1891 ioctl: au1550_ioctl,
1892 mmap: au1550_mmap,
1893 open: au1550_open,
1894 release: au1550_release,
1895};
1896
1897MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1898MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
bb12b76e
DP		 1899MODULE_LICENSE("GPL");
1900
1da177e4
LT		 1901
1902static int __devinit
1903au1550_probe(void)
1904{
1905 struct au1550_state *s = &au1550_state;
1906 int val;
1907
1908 memset(s, 0, sizeof(struct au1550_state));
1909
1910 init_waitqueue_head(&s->dma_adc.wait);
1911 init_waitqueue_head(&s->dma_dac.wait);
1912 init_waitqueue_head(&s->open_wait);
910f5d20 1913 mutex_init(&s->open_mutex);
1da177e4
LT		 1914 spin_lock_init(&s->lock);
1915
1916 s->codec = ac97_alloc_codec();
1917 if(s->codec == NULL) {
1918 err("Out of memory");
1919 return -1;
1920 }
1921 s->codec->private_data = s;
1922 s->codec->id = 0;
1923 s->codec->codec_read = rdcodec;
1924 s->codec->codec_write = wrcodec;
1925 s->codec->codec_wait = waitcodec;
1926
1927 if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1928 0x30, "Au1550 AC97")) {
1929 err("AC'97 ports in use");
1930 }
1931
1932 /* Allocate the DMA Channels
1933 */
1934 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1935 DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1936 err("Can't get DAC DMA");
1937 goto err_dma1;
1938 }
1939 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1940 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1941 NUM_DBDMA_DESCRIPTORS) == 0) {
1942 err("Can't get DAC DMA descriptors");
1943 goto err_dma1;
1944 }
1945
1946 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1947 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1948 err("Can't get ADC DMA");
1949 goto err_dma2;
1950 }
1951 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1952 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1953 NUM_DBDMA_DESCRIPTORS) == 0) {
1954 err("Can't get ADC DMA descriptors");
1955 goto err_dma2;
1956 }
1957
1958 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1959
1960 /* register devices */
1961
1962 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1963 goto err_dev1;
1964 if ((s->codec->dev_mixer =
1965 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1966 goto err_dev2;
1967
1968 /* The GPIO for the appropriate PSC was configured by the
1969 * board specific start up.
1970 *
1971 * configure PSC for AC'97
1972 */
1973 au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
1974 au_sync();
1975 au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1976 au_sync();
1977
1978 /* cold reset the AC'97
1979 */
1980 au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1981 au_sync();
1982 au1550_delay(10);
1983 au_writel(0, PSC_AC97RST);
1984 au_sync();
1985
1986 /* need to delay around 500msec(bleech) to give
1987 some CODECs enough time to wakeup */
1988 au1550_delay(500);
1989
1990 /* warm reset the AC'97 to start the bitclk
1991 */
1992 au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1993 au_sync();
1994 udelay(100);
1995 au_writel(0, PSC_AC97RST);
1996 au_sync();
1997
1998 /* Enable PSC
1999 */
2000 au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2001 au_sync();
2002
2003 /* Wait for PSC ready.
2004 */
2005 do {
05090fc9 2006 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2007 au_sync();
2008 } while ((val & PSC_AC97STAT_SR) == 0);
2009
2010 /* Configure AC97 controller.
2011 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2012 */
2013 val = PSC_AC97CFG_SET_LEN(16);
2014 val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2015
2016 /* Enable device so we can at least
2017 * talk over the AC-link.
2018 */
2019 au_writel(val, PSC_AC97CFG);
2020 au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2021 au_sync();
2022 val |= PSC_AC97CFG_DE_ENABLE;
2023 au_writel(val, PSC_AC97CFG);
2024 au_sync();
2025
2026 /* Wait for Device ready.
2027 */
2028 do {
05090fc9 2029 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2030 au_sync();
2031 } while ((val & PSC_AC97STAT_DR) == 0);
2032
2033 /* codec init */
2034 if (!ac97_probe_codec(s->codec))
2035 goto err_dev3;
2036
2037 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2038 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2039 pr_info("AC'97 Base/Extended ID = %04x/%04x",
2040 s->codec_base_caps, s->codec_ext_caps);
2041
2042 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2043 /* codec does not support VRA
2044 */
2045 s->no_vra = 1;
2046 } else if (!vra) {
2047 /* Boot option says disable VRA
2048 */
2049 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2050 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2051 ac97_extstat & ~AC97_EXTSTAT_VRA);
2052 s->no_vra = 1;
2053 }
2054 if (s->no_vra)
2055 pr_info("no VRA, interpolating and decimating");
2056
2057 /* set mic to be the recording source */
2058 val = SOUND_MASK_MIC;
2059 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2060 (unsigned long) &val);
2061
2062 return 0;
2063
2064 err_dev3:
2065 unregister_sound_mixer(s->codec->dev_mixer);
2066 err_dev2:
2067 unregister_sound_dsp(s->dev_audio);
2068 err_dev1:
2069 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2070 err_dma2:
2071 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2072 err_dma1:
2073 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2074
2075 ac97_release_codec(s->codec);
2076 return -1;
2077}
2078
2079static void __devinit
2080au1550_remove(void)
2081{
2082 struct au1550_state *s = &au1550_state;
2083
2084 if (!s)
2085 return;
2086 synchronize_irq();
2087 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2088 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2089 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2090 unregister_sound_dsp(s->dev_audio);
2091 unregister_sound_mixer(s->codec->dev_mixer);
2092 ac97_release_codec(s->codec);
2093}
2094
2095static int __init
2096init_au1550(void)
2097{
2098 return au1550_probe();
2099}
2100
2101static void __exit
2102cleanup_au1550(void)
2103{
2104 au1550_remove();
2105}
2106
2107module_init(init_au1550);
2108module_exit(cleanup_au1550);
2109
2110#ifndef MODULE
2111
2112static int __init
2113au1550_setup(char *options)
2114{
2115 char *this_opt;
2116
2117 if (!options || !*options)
2118 return 0;
2119
2120 while ((this_opt = strsep(&options, ","))) {
2121 if (!*this_opt)
2122 continue;
2123 if (!strncmp(this_opt, "vra", 3)) {
2124 vra = 1;
2125 }
2126 }
2127
2128 return 1;
2129}
2130
2131__setup("au1550_audio=", au1550_setup);
2132
2133#endif /* MODULE */
Linux kernel - Deliverables
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