projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: asihpi - Add include guard.
[deliverable/linux.git] / sound / pci / asihpi / hpi6000.c
CommitLineData
719f82d3
EB		 1/******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
21
22 Exported functions:
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
24
25 #defines
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
28
29(C) Copyright AudioScience Inc. 1998-2003
30*******************************************************************************/
31#define SOURCEFILE_NAME "hpi6000.c"
32
33#include "hpi_internal.h"
34#include "hpimsginit.h"
35#include "hpidebug.h"
36#include "hpi6000.h"
37#include "hpidspcd.h"
38#include "hpicmn.h"
39
40#define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41#define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43#define HPI_HIF_ERROR_MASK 0x4000
44
45/* HPI6000 specific error codes */
3285ea10
EB		 46#define HPI6000_ERROR_BASE 900 /* not actually used anywhere */
47/* operational/messaging errors */
719f82d3 48#define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
3285ea10 49
719f82d3
EB		 50#define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
51#define HPI6000_ERROR_MSG_GET_ADR 904
52#define HPI6000_ERROR_RESP_GET_ADR 905
53#define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
54#define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
3285ea10 55
719f82d3
EB		 56#define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
57
58#define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
59#define HPI6000_ERROR_SEND_DATA_ACK 912
60#define HPI6000_ERROR_SEND_DATA_ADR 913
61#define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
62#define HPI6000_ERROR_SEND_DATA_CMD 915
63#define HPI6000_ERROR_SEND_DATA_WRITE 916
64#define HPI6000_ERROR_SEND_DATA_IDLECMD 917
719f82d3
EB		 65
66#define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
67#define HPI6000_ERROR_GET_DATA_ACK 922
68#define HPI6000_ERROR_GET_DATA_CMD 923
69#define HPI6000_ERROR_GET_DATA_READ 924
70#define HPI6000_ERROR_GET_DATA_IDLECMD 925
71
72#define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
73#define HPI6000_ERROR_CONTROL_CACHE_READ 952
74#define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
75
76#define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
77#define HPI6000_ERROR_MSG_RESP_IDLECMD 962
719f82d3 78
3285ea10 79/* Initialisation/bootload errors */
719f82d3
EB		 80#define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
81
82/* can't access PCI2040 */
83#define HPI6000_ERROR_INIT_PCI2040 931
84/* can't access DSP HPI i/f */
85#define HPI6000_ERROR_INIT_DSPHPI 932
86/* can't access internal DSP memory */
87#define HPI6000_ERROR_INIT_DSPINTMEM 933
88/* can't access SDRAM - test#1 */
89#define HPI6000_ERROR_INIT_SDRAM1 934
90/* can't access SDRAM - test#2 */
91#define HPI6000_ERROR_INIT_SDRAM2 935
92
93#define HPI6000_ERROR_INIT_VERIFY 938
94
95#define HPI6000_ERROR_INIT_NOACK 939
96
97#define HPI6000_ERROR_INIT_PLDTEST1 941
98#define HPI6000_ERROR_INIT_PLDTEST2 942
99
100/* local defines */
101
102#define HIDE_PCI_ASSERTS
103#define PROFILE_DSP2
104
105/* for PCI2040 i/f chip */
106/* HPI CSR registers */
107/* word offsets from CSR base */
108/* use when io addresses defined as u32 * */
109
110#define INTERRUPT_EVENT_SET 0
111#define INTERRUPT_EVENT_CLEAR 1
112#define INTERRUPT_MASK_SET 2
113#define INTERRUPT_MASK_CLEAR 3
114#define HPI_ERROR_REPORT 4
115#define HPI_RESET 5
116#define HPI_DATA_WIDTH 6
117
118#define MAX_DSPS 2
119/* HPI registers, spaced 8K bytes = 2K words apart */
120#define DSP_SPACING 0x800
121
122#define CONTROL 0x0000
123#define ADDRESS 0x0200
124#define DATA_AUTOINC 0x0400
125#define DATA 0x0600
126
127#define TIMEOUT 500000
128
129struct dsp_obj {
130 __iomem u32 *prHPI_control;
131 __iomem u32 *prHPI_address;
132 __iomem u32 *prHPI_data;
133 __iomem u32 *prHPI_data_auto_inc;
134 char c_dsp_rev; /*A, B */
135 u32 control_cache_address_on_dsp;
136 u32 control_cache_length_on_dsp;
137 struct hpi_adapter_obj *pa_parent_adapter;
138};
139
140struct hpi_hw_obj {
141 __iomem u32 *dw2040_HPICSR;
142 __iomem u32 *dw2040_HPIDSP;
143
144 u16 num_dsp;
145 struct dsp_obj ado[MAX_DSPS];
146
147 u32 message_buffer_address_on_dsp;
148 u32 response_buffer_address_on_dsp;
149 u32 pCI2040HPI_error_count;
150
151 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
152 struct hpi_control_cache *p_cache;
153};
154
155static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
156 u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
157static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
158 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
159
160static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
161 u32 *pos_error_code);
162static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
163 u16 read_or_write);
164#define H6READ 1
165#define H6WRITE 0
166
167static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
168 struct hpi_message *phm);
169static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
170 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
171
172static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
173 struct hpi_response *phr);
174
175static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
176 u32 ack_value);
177
178static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
179 u16 dsp_index, u32 host_cmd);
180
181static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
182
183static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
184 struct hpi_message *phm, struct hpi_response *phr);
185
186static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
187 struct hpi_message *phm, struct hpi_response *phr);
188
189static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
190
191static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
192
193static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
194 u32 length);
195
196static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
197 u32 length);
198
199static void subsys_create_adapter(struct hpi_message *phm,
200 struct hpi_response *phr);
201
202static void subsys_delete_adapter(struct hpi_message *phm,
203 struct hpi_response *phr);
204
205static void adapter_get_asserts(struct hpi_adapter_obj *pao,
206 struct hpi_message *phm, struct hpi_response *phr);
207
208static short create_adapter_obj(struct hpi_adapter_obj *pao,
209 u32 *pos_error_code);
210
3285ea10
EB		 211static void delete_adapter_obj(struct hpi_adapter_obj *pao);
212
719f82d3
EB		 213/* local globals */
214
215static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
216static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
217
218static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
219{
719f82d3 220 switch (phm->function) {
719f82d3
EB		 221 case HPI_SUBSYS_CREATE_ADAPTER:
222 subsys_create_adapter(phm, phr);
223 break;
224 case HPI_SUBSYS_DELETE_ADAPTER:
225 subsys_delete_adapter(phm, phr);
226 break;
227 default:
228 phr->error = HPI_ERROR_INVALID_FUNC;
229 break;
230 }
231}
232
233static void control_message(struct hpi_adapter_obj *pao,
234 struct hpi_message *phm, struct hpi_response *phr)
235{
719f82d3
EB		 236 switch (phm->function) {
237 case HPI_CONTROL_GET_STATE:
238 if (pao->has_control_cache) {
3285ea10 239 phr->error = hpi6000_update_control_cache(pao, phm);
719f82d3 240
3285ea10 241 if (phr->error)
719f82d3 242 break;
719f82d3
EB		 243
244 if (hpi_check_control_cache(((struct hpi_hw_obj *)
245 pao->priv)->p_cache, phm,
246 phr))
247 break;
248 }
249 hw_message(pao, phm, phr);
250 break;
719f82d3
EB		 251 case HPI_CONTROL_SET_STATE:
252 hw_message(pao, phm, phr);
3285ea10
EB		 253 hpi_cmn_control_cache_sync_to_msg(((struct hpi_hw_obj *)pao->
254 priv)->p_cache, phm, phr);
719f82d3 255 break;
3285ea10
EB		 256
257 case HPI_CONTROL_GET_INFO:
719f82d3 258 default:
3285ea10 259 hw_message(pao, phm, phr);
719f82d3
EB		 260 break;
261 }
262}
263
264static void adapter_message(struct hpi_adapter_obj *pao,
265 struct hpi_message *phm, struct hpi_response *phr)
266{
267 switch (phm->function) {
719f82d3
EB		 268 case HPI_ADAPTER_GET_ASSERT:
269 adapter_get_asserts(pao, phm, phr);
270 break;
3285ea10 271
719f82d3 272 default:
3285ea10 273 hw_message(pao, phm, phr);
719f82d3
EB		 274 break;
275 }
276}
277
278static void outstream_message(struct hpi_adapter_obj *pao,
279 struct hpi_message *phm, struct hpi_response *phr)
280{
281 switch (phm->function) {
282 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
283 case HPI_OSTREAM_HOSTBUFFER_FREE:
284 /* Don't let these messages go to the HW function because
3285ea10 285 * they're called without locking the spinlock.
719f82d3
EB		 286 * For the HPI6000 adapters the HW would return
287 * HPI_ERROR_INVALID_FUNC anyway.
288 */
289 phr->error = HPI_ERROR_INVALID_FUNC;
290 break;
291 default:
292 hw_message(pao, phm, phr);
293 return;
294 }
295}
296
297static void instream_message(struct hpi_adapter_obj *pao,
298 struct hpi_message *phm, struct hpi_response *phr)
299{
300
301 switch (phm->function) {
302 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
303 case HPI_ISTREAM_HOSTBUFFER_FREE:
304 /* Don't let these messages go to the HW function because
3285ea10 305 * they're called without locking the spinlock.
719f82d3
EB		 306 * For the HPI6000 adapters the HW would return
307 * HPI_ERROR_INVALID_FUNC anyway.
308 */
309 phr->error = HPI_ERROR_INVALID_FUNC;
310 break;
311 default:
312 hw_message(pao, phm, phr);
313 return;
314 }
315}
316
317/************************************************************************/
318/** HPI_6000()
319 * Entry point from HPIMAN
320 * All calls to the HPI start here
321 */
322void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
323{
324 struct hpi_adapter_obj *pao = NULL;
325
326 /* subsytem messages get executed by every HPI. */
327 /* All other messages are ignored unless the adapter index matches */
328 /* an adapter in the HPI */
3285ea10 329 /*HPI_DEBUG_LOG(DEBUG, "O %d,F %x\n", phm->wObject, phm->wFunction); */
719f82d3
EB		 330
331 /* if Dsp has crashed then do not communicate with it any more */
332 if (phm->object != HPI_OBJ_SUBSYSTEM) {
333 pao = hpi_find_adapter(phm->adapter_index);
334 if (!pao) {
335 HPI_DEBUG_LOG(DEBUG,
336 " %d,%d refused, for another HPI?\n",
337 phm->object, phm->function);
338 return;
339 }
340
341 if (pao->dsp_crashed >= 10) {
342 hpi_init_response(phr, phm->object, phm->function,
343 HPI_ERROR_DSP_HARDWARE);
344 HPI_DEBUG_LOG(DEBUG, " %d,%d dsp crashed.\n",
345 phm->object, phm->function);
346 return;
347 }
348 }
349 /* Init default response including the size field */
350 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
351 hpi_init_response(phr, phm->object, phm->function,
352 HPI_ERROR_PROCESSING_MESSAGE);
353
354 switch (phm->type) {
355 case HPI_TYPE_MESSAGE:
356 switch (phm->object) {
357 case HPI_OBJ_SUBSYSTEM:
358 subsys_message(phm, phr);
359 break;
360
361 case HPI_OBJ_ADAPTER:
362 phr->size =
363 sizeof(struct hpi_response_header) +
364 sizeof(struct hpi_adapter_res);
365 adapter_message(pao, phm, phr);
366 break;
367
368 case HPI_OBJ_CONTROL:
369 control_message(pao, phm, phr);
370 break;
371
372 case HPI_OBJ_OSTREAM:
373 outstream_message(pao, phm, phr);
374 break;
375
376 case HPI_OBJ_ISTREAM:
377 instream_message(pao, phm, phr);
378 break;
379
380 default:
381 hw_message(pao, phm, phr);
382 break;
383 }
384 break;
385
386 default:
387 phr->error = HPI_ERROR_INVALID_TYPE;
388 break;
389 }
390}
391
392/************************************************************************/
393/* SUBSYSTEM */
394
395/* create an adapter object and initialise it based on resource information
396 * passed in in the message
397 * NOTE - you cannot use this function AND the FindAdapters function at the
398 * same time, the application must use only one of them to get the adapters
399 */
400static void subsys_create_adapter(struct hpi_message *phm,
401 struct hpi_response *phr)
402{
403 /* create temp adapter obj, because we don't know what index yet */
404 struct hpi_adapter_obj ao;
405 struct hpi_adapter_obj *pao;
406 u32 os_error_code;
407 short error = 0;
408 u32 dsp_index = 0;
409
410 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
411
412 memset(&ao, 0, sizeof(ao));
413
550a8b69 414 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
719f82d3
EB		 415 if (!ao.priv) {
416 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
417 phr->error = HPI_ERROR_MEMORY_ALLOC;
418 return;
419 }
420
719f82d3 421 /* create the adapter object based on the resource information */
719f82d3
EB		 422 ao.pci = *phm->u.s.resource.r.pci;
423
424 error = create_adapter_obj(&ao, &os_error_code);
719f82d3 425 if (error) {
3285ea10 426 delete_adapter_obj(&ao);
719f82d3 427 phr->error = error;
3285ea10 428 phr->u.s.data = os_error_code;
719f82d3
EB		 429 return;
430 }
431 /* need to update paParentAdapter */
432 pao = hpi_find_adapter(ao.index);
433 if (!pao) {
434 /* We just added this adapter, why can't we find it!? */
435 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
436 phr->error = 950;
437 return;
438 }
439
440 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
441 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
442 phw->ado[dsp_index].pa_parent_adapter = pao;
443 }
444
445 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
446 phr->u.s.adapter_index = ao.index;
447 phr->u.s.num_adapters++;
448 phr->error = 0;
449}
450
451static void subsys_delete_adapter(struct hpi_message *phm,
452 struct hpi_response *phr)
453{
454 struct hpi_adapter_obj *pao = NULL;
719f82d3 455
3285ea10 456 pao = hpi_find_adapter(phm->obj_index);
719f82d3
EB		 457 if (!pao)
458 return;
459
3285ea10 460 delete_adapter_obj(pao);
719f82d3 461 hpi_delete_adapter(pao);
719f82d3
EB		 462 phr->error = 0;
463}
464
465/* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
466static short create_adapter_obj(struct hpi_adapter_obj *pao,
467 u32 *pos_error_code)
468{
469 short boot_error = 0;
470 u32 dsp_index = 0;
471 u32 control_cache_size = 0;
472 u32 control_cache_count = 0;
473 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
474
719f82d3
EB		 475 /* The PCI2040 has the following address map */
476 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
477 /* BAR1 - 32K = HPI registers on DSP */
478 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
479 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
480 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
481 phw->dw2040_HPIDSP);
482
483 /* set addresses for the possible DSP HPI interfaces */
484 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
485 phw->ado[dsp_index].prHPI_control =
486 phw->dw2040_HPIDSP + (CONTROL +
487 DSP_SPACING * dsp_index);
488
489 phw->ado[dsp_index].prHPI_address =
490 phw->dw2040_HPIDSP + (ADDRESS +
491 DSP_SPACING * dsp_index);
492 phw->ado[dsp_index].prHPI_data =
493 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
494
495 phw->ado[dsp_index].prHPI_data_auto_inc =
496 phw->dw2040_HPIDSP + (DATA_AUTOINC +
497 DSP_SPACING * dsp_index);
498
499 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
500 phw->ado[dsp_index].prHPI_control,
501 phw->ado[dsp_index].prHPI_address,
502 phw->ado[dsp_index].prHPI_data,
503 phw->ado[dsp_index].prHPI_data_auto_inc);
504
505 phw->ado[dsp_index].pa_parent_adapter = pao;
506 }
507
508 phw->pCI2040HPI_error_count = 0;
509 pao->has_control_cache = 0;
510
511 /* Set the default number of DSPs on this card */
512 /* This is (conditionally) adjusted after bootloading */
513 /* of the first DSP in the bootload section. */
514 phw->num_dsp = 1;
515
516 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
517 if (boot_error)
518 return boot_error;
519
520 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
521
522 phw->message_buffer_address_on_dsp = 0L;
523 phw->response_buffer_address_on_dsp = 0L;
524
525 /* get info about the adapter by asking the adapter */
526 /* send a HPI_ADAPTER_GET_INFO message */
527 {
3285ea10
EB		 528 struct hpi_message hm;
529 struct hpi_response hr0; /* response from DSP 0 */
530 struct hpi_response hr1; /* response from DSP 1 */
719f82d3
EB		 531 u16 error = 0;
532
533 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
3285ea10
EB		 534 memset(&hm, 0, sizeof(hm));
535 hm.type = HPI_TYPE_MESSAGE;
536 hm.size = sizeof(struct hpi_message);
537 hm.object = HPI_OBJ_ADAPTER;
538 hm.function = HPI_ADAPTER_GET_INFO;
539 hm.adapter_index = 0;
540 memset(&hr0, 0, sizeof(hr0));
541 memset(&hr1, 0, sizeof(hr1));
542 hr0.size = sizeof(hr0);
543 hr1.size = sizeof(hr1);
544
545 error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
546 if (hr0.error) {
547 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
548 return hr0.error;
719f82d3
EB		 549 }
550 if (phw->num_dsp == 2) {
3285ea10
EB		 551 error = hpi6000_message_response_sequence(pao, 1, &hm,
552 &hr1);
719f82d3
EB		 553 if (error)
554 return error;
555 }
3285ea10
EB		 556 pao->adapter_type = hr0.u.ax.info.adapter_type;
557 pao->index = hr0.u.ax.info.adapter_index;
719f82d3
EB		 558 }
559
560 memset(&phw->control_cache[0], 0,
561 sizeof(struct hpi_control_cache_single) *
562 HPI_NMIXER_CONTROLS);
563 /* Read the control cache length to figure out if it is turned on */
564 control_cache_size =
565 hpi_read_word(&phw->ado[0],
566 HPI_HIF_ADDR(control_cache_size_in_bytes));
567 if (control_cache_size) {
568 control_cache_count =
569 hpi_read_word(&phw->ado[0],
570 HPI_HIF_ADDR(control_cache_count));
719f82d3
EB		 571
572 phw->p_cache =
573 hpi_alloc_control_cache(control_cache_count,
3285ea10 574 control_cache_size, (unsigned char *)
719f82d3
EB		 575 &phw->control_cache[0]
576 );
3285ea10
EB		 577 if (phw->p_cache)
578 pao->has_control_cache = 1;
579 }
719f82d3
EB		 580
581 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
582 pao->adapter_type, pao->index);
583 pao->open = 0; /* upon creation the adapter is closed */
3285ea10 584
ffdb5787
EB		 585 if (phw->p_cache)
586 phw->p_cache->adap_idx = pao->index;
587
3285ea10
EB		 588 return hpi_add_adapter(pao);
589}
590
591static void delete_adapter_obj(struct hpi_adapter_obj *pao)
592{
593 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
594
595 if (pao->has_control_cache)
596 hpi_free_control_cache(phw->p_cache);
597
598 /* reset DSPs on adapter */
599 iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
600
601 kfree(phw);
719f82d3
EB		 602}
603
604/************************************************************************/
605/* ADAPTER */
606
607static void adapter_get_asserts(struct hpi_adapter_obj *pao,
608 struct hpi_message *phm, struct hpi_response *phr)
609{
610#ifndef HIDE_PCI_ASSERTS
611 /* if we have PCI2040 asserts then collect them */
612 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
3285ea10 613 phr->u.ax.assert.p1 =
719f82d3 614 gw_pci_read_asserts * 100 + gw_pci_write_asserts;
3285ea10
EB		 615 phr->u.ax.assert.p2 = 0;
616 phr->u.ax.assert.count = 1; /* assert count */
617 phr->u.ax.assert.dsp_index = -1; /* "dsp index" */
618 strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
619 phr->u.ax.assert.dsp_msg_addr = 0;
719f82d3
EB		 620 gw_pci_read_asserts = 0;
621 gw_pci_write_asserts = 0;
622 phr->error = 0;
623 } else
624#endif
625 hw_message(pao, phm, phr); /*get DSP asserts */
626
627 return;
628}
629
630/************************************************************************/
631/* LOW-LEVEL */
632
633static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
634 u32 *pos_error_code)
635{
636 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
637 short error;
638 u32 timeout;
639 u32 read = 0;
640 u32 i = 0;
641 u32 data = 0;
642 u32 j = 0;
643 u32 test_addr = 0x80000000;
644 u32 test_data = 0x00000001;
645 u32 dw2040_reset = 0;
646 u32 dsp_index = 0;
647 u32 endian = 0;
648 u32 adapter_info = 0;
649 u32 delay = 0;
650
651 struct dsp_code dsp_code;
652 u16 boot_load_family = 0;
653
654 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
655
3285ea10 656 switch (pao->pci.pci_dev->subsystem_device) {
719f82d3
EB		 657 case 0x5100:
658 case 0x5110: /* ASI5100 revB or higher with C6711D */
3285ea10 659 case 0x5200: /* ASI5200 PCIe version of ASI5100 */
719f82d3
EB		 660 case 0x6100:
661 case 0x6200:
662 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
663 break;
719f82d3
EB		 664 default:
665 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
666 }
667
668 /* reset all DSPs, indicate two DSPs are present
669 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
670 */
671 endian = 0;
672 dw2040_reset = 0x0003000F;
673 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
674
675 /* read back register to make sure PCI2040 chip is functioning
676 * note that bits 4..15 are read-only and so should always return zero,
677 * even though we wrote 1 to them
678 */
3285ea10
EB		 679 hpios_delay_micro_seconds(1000);
680 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
681
719f82d3
EB		 682 if (delay != dw2040_reset) {
683 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
684 delay);
685 return HPI6000_ERROR_INIT_PCI2040;
686 }
687
688 /* Indicate that DSP#0,1 is a C6X */
689 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
690 /* set Bit30 and 29 - which will prevent Target aborts from being
691 * issued upon HPI or GP error
692 */
693 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
694
695 /* isolate DSP HAD8 line from PCI2040 so that
696 * Little endian can be set by pullup
697 */
698 dw2040_reset = dw2040_reset & (~(endian << 3));
699 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
700
701 phw->ado[0].c_dsp_rev = 'B'; /* revB */
702 phw->ado[1].c_dsp_rev = 'B'; /* revB */
703
704 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
705 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
706 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
707 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
708 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
709
710 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
711 dw2040_reset = dw2040_reset & (~0x00000008);
712 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
713 /*delay to allow DSP to get going */
3285ea10 714 hpios_delay_micro_seconds(100);
719f82d3
EB		 715
716 /* loop through all DSPs, downloading DSP code */
717 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
718 struct dsp_obj *pdo = &phw->ado[dsp_index];
719
720 /* configure DSP so that we download code into the SRAM */
721 /* set control reg for little endian, HWOB=1 */
722 iowrite32(0x00010001, pdo->prHPI_control);
723
724 /* test access to the HPI address register (HPIA) */
725 test_data = 0x00000001;
726 for (j = 0; j < 32; j++) {
727 iowrite32(test_data, pdo->prHPI_address);
728 data = ioread32(pdo->prHPI_address);
729 if (data != test_data) {
730 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
731 test_data, data, dsp_index);
732 return HPI6000_ERROR_INIT_DSPHPI;
733 }
734 test_data = test_data << 1;
735 }
736
737/* if C6713 the setup PLL to generate 225MHz from 25MHz.
738* Since the PLLDIV1 read is sometimes wrong, even on a C6713,
739* we're going to do this unconditionally
740*/
741/* PLLDIV1 should have a value of 8000 after reset */
742/*
743 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
744*/
745 {
746 /* C6713 datasheet says we cannot program PLL from HPI,
747 * and indeed if we try to set the PLL multiply from the
748 * HPI, the PLL does not seem to lock,
749 * so we enable the PLL and use the default of x 7
750 */
751 /* bypass PLL */
752 hpi_write_word(pdo, 0x01B7C100, 0x0000);
3285ea10 753 hpios_delay_micro_seconds(100);
719f82d3
EB		 754
755 /* ** use default of PLL x7 ** */
756 /* EMIF = 225/3=75MHz */
757 hpi_write_word(pdo, 0x01B7C120, 0x8002);
3285ea10
EB		 758 hpios_delay_micro_seconds(100);
759
719f82d3
EB		 760 /* peri = 225/2 */
761 hpi_write_word(pdo, 0x01B7C11C, 0x8001);
3285ea10
EB		 762 hpios_delay_micro_seconds(100);
763
719f82d3
EB		 764 /* cpu = 225/1 */
765 hpi_write_word(pdo, 0x01B7C118, 0x8000);
3285ea10
EB		 766
767 /* ~2ms delay */
768 hpios_delay_micro_seconds(2000);
769
719f82d3
EB		 770 /* PLL not bypassed */
771 hpi_write_word(pdo, 0x01B7C100, 0x0001);
3285ea10
EB		 772 /* ~2ms delay */
773 hpios_delay_micro_seconds(2000);
719f82d3
EB		 774 }
775
776 /* test r/w to internal DSP memory
777 * C6711 has L2 cache mapped to 0x0 when reset
778 *
779 * revB - because of bug 3.0.1 last HPI read
780 * (before HPI address issued) must be non-autoinc
781 */
782 /* test each bit in the 32bit word */
783 for (i = 0; i < 100; i++) {
784 test_addr = 0x00000000;
785 test_data = 0x00000001;
786 for (j = 0; j < 32; j++) {
787 hpi_write_word(pdo, test_addr + i, test_data);
788 data = hpi_read_word(pdo, test_addr + i);
789 if (data != test_data) {
790 HPI_DEBUG_LOG(ERROR,
791 "DSP mem %x %x %x %x\n",
792 test_addr + i, test_data,
793 data, dsp_index);
794
795 return HPI6000_ERROR_INIT_DSPINTMEM;
796 }
797 test_data = test_data << 1;
798 }
799 }
800
801 /* memory map of ASI6200
802 00000000-0000FFFF 16Kx32 internal program
803 01800000-019FFFFF Internal peripheral
804 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
805 90000000-9000FFFF CE1 Async peripherals:
806
807 EMIF config
808 ------------
809 Global EMIF control
810 0 -
811 1 -
812 2 -
813 3 CLK2EN = 1 CLKOUT2 enabled
814 4 CLK1EN = 0 CLKOUT1 disabled
815 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
816 6 -
817 7 NOHOLD = 1 external HOLD disabled
818 8 HOLDA = 0 HOLDA output is low
819 9 HOLD = 0 HOLD input is low
820 10 ARDY = 1 ARDY input is high
821 11 BUSREQ = 0 BUSREQ output is low
822 12,13 Reserved = 1
823 */
824 hpi_write_word(pdo, 0x01800000, 0x34A8);
825
826 /* EMIF CE0 setup - 2Mx32 Sync DRAM
827 31..28 Wr setup
828 27..22 Wr strobe
829 21..20 Wr hold
830 19..16 Rd setup
831 15..14 -
832 13..8 Rd strobe
833 7..4 MTYPE 0011 Sync DRAM 32bits
834 3 Wr hold MSB
835 2..0 Rd hold
836 */
837 hpi_write_word(pdo, 0x01800008, 0x00000030);
838
839 /* EMIF SDRAM Extension
840 31-21 0
841 20 WR2RD = 0
842 19-18 WR2DEAC = 1
843 17 WR2WR = 0
844 16-15 R2WDQM = 2
845 14-12 RD2WR = 4
846 11-10 RD2DEAC = 1
847 9 RD2RD = 1
848 8-7 THZP = 10b
849 6-5 TWR = 2-1 = 01b (tWR = 10ns)
850 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
851 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
852 1 CAS latency = 3 ECLK
853 (for Micron 2M32-7 operating at 100Mhz)
854 */
855
856 /* need to use this else DSP code crashes */
857 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
858
859 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
860 31 - -
861 30 SDBSZ 1 4 bank
862 29..28 SDRSZ 00 11 row address pins
863 27..26 SDCSZ 01 8 column address pins
864 25 RFEN 1 refersh enabled
865 24 INIT 1 init SDRAM
866 23..20 TRCD 0001
867 19..16 TRP 0001
868 15..12 TRC 0110
869 11..0 - -
870 */
871 /* need to use this else DSP code crashes */
872 hpi_write_word(pdo, 0x01800018, 0x47117000);
873
874 /* EMIF SDRAM Refresh Timing */
875 hpi_write_word(pdo, 0x0180001C, 0x00000410);
876
877 /*MIF CE1 setup - Async peripherals
878 @100MHz bus speed, each cycle is 10ns,
879 31..28 Wr setup = 1
880 27..22 Wr strobe = 3 30ns
881 21..20 Wr hold = 1
882 19..16 Rd setup =1
883 15..14 Ta = 2
884 13..8 Rd strobe = 3 30ns
885 7..4 MTYPE 0010 Async 32bits
886 3 Wr hold MSB =0
887 2..0 Rd hold = 1
888 */
889 {
890 u32 cE1 =
891 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
892 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
893 hpi_write_word(pdo, 0x01800004, cE1);
894 }
895
896 /* delay a little to allow SDRAM and DSP to "get going" */
3285ea10 897 hpios_delay_micro_seconds(1000);
719f82d3
EB		 898
899 /* test access to SDRAM */
900 {
901 test_addr = 0x80000000;
902 test_data = 0x00000001;
903 /* test each bit in the 32bit word */
904 for (j = 0; j < 32; j++) {
905 hpi_write_word(pdo, test_addr, test_data);
906 data = hpi_read_word(pdo, test_addr);
907 if (data != test_data) {
908 HPI_DEBUG_LOG(ERROR,
909 "DSP dram %x %x %x %x\n",
910 test_addr, test_data, data,
911 dsp_index);
912
913 return HPI6000_ERROR_INIT_SDRAM1;
914 }
915 test_data = test_data << 1;
916 }
917 /* test every Nth address in the DRAM */
918#define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
919#define DRAM_INC 1024
920 test_addr = 0x80000000;
921 test_data = 0x0;
922 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
923 hpi_write_word(pdo, test_addr + i, test_data);
924 test_data++;
925 }
926 test_addr = 0x80000000;
927 test_data = 0x0;
928 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
929 data = hpi_read_word(pdo, test_addr + i);
930 if (data != test_data) {
931 HPI_DEBUG_LOG(ERROR,
932 "DSP dram %x %x %x %x\n",
933 test_addr + i, test_data,
934 data, dsp_index);
935 return HPI6000_ERROR_INIT_SDRAM2;
936 }
937 test_data++;
938 }
939
940 }
941
942 /* write the DSP code down into the DSPs memory */
943 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
3285ea10 944 dsp_code.ps_dev = pao->pci.pci_dev;
719f82d3
EB		 945
946 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
947 pos_error_code);
948
949 if (error)
950 return error;
951
952 while (1) {
953 u32 length;
954 u32 address;
955 u32 type;
956 u32 *pcode;
957
958 error = hpi_dsp_code_read_word(&dsp_code, &length);
959 if (error)
960 break;
961 if (length == 0xFFFFFFFF)
962 break; /* end of code */
963
964 error = hpi_dsp_code_read_word(&dsp_code, &address);
965 if (error)
966 break;
967 error = hpi_dsp_code_read_word(&dsp_code, &type);
968 if (error)
969 break;
970 error = hpi_dsp_code_read_block(length, &dsp_code,
971 &pcode);
972 if (error)
973 break;
974 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
975 address, pcode, length);
976 if (error)
977 break;
978 }
979
980 if (error) {
981 hpi_dsp_code_close(&dsp_code);
982 return error;
983 }
984 /* verify that code was written correctly */
985 /* this time through, assume no errors in DSP code file/array */
986 hpi_dsp_code_rewind(&dsp_code);
987 while (1) {
988 u32 length;
989 u32 address;
990 u32 type;
991 u32 *pcode;
992
993 hpi_dsp_code_read_word(&dsp_code, &length);
994 if (length == 0xFFFFFFFF)
995 break; /* end of code */
996
997 hpi_dsp_code_read_word(&dsp_code, &address);
998 hpi_dsp_code_read_word(&dsp_code, &type);
999 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1000
1001 for (i = 0; i < length; i++) {
1002 data = hpi_read_word(pdo, address);
1003 if (data != *pcode) {
1004 error = HPI6000_ERROR_INIT_VERIFY;
1005 HPI_DEBUG_LOG(ERROR,
1006 "DSP verify %x %x %x %x\n",
1007 address, *pcode, data,
1008 dsp_index);
1009 break;
1010 }
1011 pcode++;
1012 address += 4;
1013 }
1014 if (error)
1015 break;
1016 }
1017 hpi_dsp_code_close(&dsp_code);
1018 if (error)
1019 return error;
1020
1021 /* zero out the hostmailbox */
1022 {
1023 u32 address = HPI_HIF_ADDR(host_cmd);
1024 for (i = 0; i < 4; i++) {
1025 hpi_write_word(pdo, address, 0);
1026 address += 4;
1027 }
1028 }
1029 /* write the DSP number into the hostmailbox */
1030 /* structure before starting the DSP */
1031 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1032
1033 /* write the DSP adapter Info into the */
1034 /* hostmailbox before starting the DSP */
1035 if (dsp_index > 0)
1036 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1037 adapter_info);
1038
1039 /* step 3. Start code by sending interrupt */
1040 iowrite32(0x00030003, pdo->prHPI_control);
3285ea10 1041 hpios_delay_micro_seconds(10000);
719f82d3
EB		 1042
1043 /* wait for a non-zero value in hostcmd -
1044 * indicating initialization is complete
1045 *
1046 * Init could take a while if DSP checks SDRAM memory
1047 * Was 200000. Increased to 2000000 for ASI8801 so we
1048 * don't get 938 errors.
1049 */
1050 timeout = 2000000;
1051 while (timeout) {
1052 do {
1053 read = hpi_read_word(pdo,
1054 HPI_HIF_ADDR(host_cmd));
1055 } while (--timeout
1056 && hpi6000_check_PCI2040_error_flag(pao,
1057 H6READ));
1058
1059 if (read)
1060 break;
1061 /* The following is a workaround for bug #94:
1062 * Bluescreen on install and subsequent boots on a
1063 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1064 * ServerWorks chipset. Without this delay the system
1065 * locks up with a bluescreen (NOT GPF or pagefault).
1066 */
1067 else
3285ea10 1068 hpios_delay_micro_seconds(10000);
719f82d3
EB		 1069 }
1070 if (timeout == 0)
1071 return HPI6000_ERROR_INIT_NOACK;
1072
1073 /* read the DSP adapter Info from the */
1074 /* hostmailbox structure after starting the DSP */
1075 if (dsp_index == 0) {
1076 /*u32 dwTestData=0; */
1077 u32 mask = 0;
1078
1079 adapter_info =
1080 hpi_read_word(pdo,
1081 HPI_HIF_ADDR(adapter_info));
1082 if (HPI_ADAPTER_FAMILY_ASI
1083 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1084 (adapter_info)) ==
1085 HPI_ADAPTER_FAMILY_ASI(0x6200))
1086 /* all 6200 cards have this many DSPs */
1087 phw->num_dsp = 2;
1088
1089 /* test that the PLD is programmed */
1090 /* and we can read/write 24bits */
1091#define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1092
1093 switch (boot_load_family) {
1094 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1095 /* ASI6100/6200 has 24bit path to FPGA */
1096 mask = 0xFFFFFF00L;
1097 /* ASI5100 uses AX6 code, */
1098 /* but has no PLD r/w register to test */
3285ea10
EB		 1099 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1100 subsystem_device) ==
719f82d3
EB		 1101 HPI_ADAPTER_FAMILY_ASI(0x5100))
1102 mask = 0x00000000L;
38439146
EB		 1103 /* ASI5200 uses AX6 code, */
1104 /* but has no PLD r/w register to test */
3285ea10
EB		 1105 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1106 subsystem_device) ==
38439146
EB		 1107 HPI_ADAPTER_FAMILY_ASI(0x5200))
1108 mask = 0x00000000L;
719f82d3
EB		 1109 break;
1110 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1111 /* ASI8800 has 16bit path to FPGA */
1112 mask = 0xFFFF0000L;
1113 break;
1114 }
1115 test_data = 0xAAAAAA00L & mask;
1116 /* write to 24 bit Debug register (D31-D8) */
1117 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1118 read = hpi_read_word(pdo,
1119 PLD_BASE_ADDRESS + 4L) & mask;
1120 if (read != test_data) {
1121 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1122 read);
1123 return HPI6000_ERROR_INIT_PLDTEST1;
1124 }
1125 test_data = 0x55555500L & mask;
1126 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1127 read = hpi_read_word(pdo,
1128 PLD_BASE_ADDRESS + 4L) & mask;
1129 if (read != test_data) {
1130 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1131 read);
1132 return HPI6000_ERROR_INIT_PLDTEST2;
1133 }
1134 }
1135 } /* for numDSP */
1136 return 0;
1137}
1138
1139#define PCI_TIMEOUT 100
1140
1141static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1142{
1143 u32 timeout = PCI_TIMEOUT;
1144
1145 do {
1146 iowrite32(address, pdo->prHPI_address);
1147 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1148 H6WRITE)
1149 && --timeout);
1150
1151 if (timeout)
1152 return 0;
1153
1154 return 1;
1155}
1156
1157/* write one word to the HPI port */
1158static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1159{
1160 if (hpi_set_address(pdo, address))
1161 return;
1162 iowrite32(data, pdo->prHPI_data);
1163}
1164
1165/* read one word from the HPI port */
1166static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1167{
1168 u32 data = 0;
1169
1170 if (hpi_set_address(pdo, address))
3285ea10 1171 return 0; /*? No way to return error */
719f82d3
EB		 1172
1173 /* take care of errata in revB DSP (2.0.1) */
1174 data = ioread32(pdo->prHPI_data);
1175 return data;
1176}
1177
1178/* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1179static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1180 u32 length)
1181{
1182 u16 length16 = length - 1;
1183
1184 if (length == 0)
1185 return;
1186
1187 if (hpi_set_address(pdo, address))
1188 return;
1189
1190 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1191
1192 /* take care of errata in revB DSP (2.0.1) */
1193 /* must end with non auto-inc */
1194 iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1195}
1196
1197/** read a block of 32bit words from the DSP HPI port using auto-inc mode
1198 */
1199static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1200 u32 length)
1201{
1202 u16 length16 = length - 1;
1203
1204 if (length == 0)
1205 return;
1206
1207 if (hpi_set_address(pdo, address))
1208 return;
1209
1210 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1211
1212 /* take care of errata in revB DSP (2.0.1) */
1213 /* must end with non auto-inc */
1214 *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1215}
1216
1217static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1218 u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1219{
1220 struct dsp_obj *pdo =
1221 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1222 u32 time_out = PCI_TIMEOUT;
1223 int c6711_burst_size = 128;
1224 u32 local_hpi_address = hpi_address;
1225 int local_count = count;
1226 int xfer_size;
1227 u32 *pdata = source;
1228
1229 while (local_count) {
1230 if (local_count > c6711_burst_size)
1231 xfer_size = c6711_burst_size;
1232 else
1233 xfer_size = local_count;
1234
1235 time_out = PCI_TIMEOUT;
1236 do {
1237 hpi_write_block(pdo, local_hpi_address, pdata,
1238 xfer_size);
1239 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1240 && --time_out);
1241
1242 if (!time_out)
1243 break;
1244 pdata += xfer_size;
1245 local_hpi_address += sizeof(u32) * xfer_size;
1246 local_count -= xfer_size;
1247 }
1248
1249 if (time_out)
1250 return 0;
1251 else
1252 return 1;
1253}
1254
1255static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1256 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1257{
1258 struct dsp_obj *pdo =
1259 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1260 u32 time_out = PCI_TIMEOUT;
1261 int c6711_burst_size = 16;
1262 u32 local_hpi_address = hpi_address;
1263 int local_count = count;
1264 int xfer_size;
1265 u32 *pdata = dest;
1266 u32 loop_count = 0;
1267
1268 while (local_count) {
1269 if (local_count > c6711_burst_size)
1270 xfer_size = c6711_burst_size;
1271 else
1272 xfer_size = local_count;
1273
1274 time_out = PCI_TIMEOUT;
1275 do {
1276 hpi_read_block(pdo, local_hpi_address, pdata,
1277 xfer_size);
1278 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1279 && --time_out);
1280 if (!time_out)
1281 break;
1282
1283 pdata += xfer_size;
1284 local_hpi_address += sizeof(u32) * xfer_size;
1285 local_count -= xfer_size;
1286 loop_count++;
1287 }
1288
1289 if (time_out)
1290 return 0;
1291 else
1292 return 1;
1293}
1294
1295static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1296 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1297{
1298 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1299 struct dsp_obj *pdo = &phw->ado[dsp_index];
1300 u32 timeout;
1301 u16 ack;
1302 u32 address;
1303 u32 length;
1304 u32 *p_data;
1305 u16 error = 0;
1306
719f82d3
EB		 1307 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1308 if (ack & HPI_HIF_ERROR_MASK) {
1309 pao->dsp_crashed++;
1310 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1311 }
1312 pao->dsp_crashed = 0;
1313
3285ea10 1314 /* get the message address and size */
719f82d3
EB		 1315 if (phw->message_buffer_address_on_dsp == 0) {
1316 timeout = TIMEOUT;
1317 do {
1318 address =
1319 hpi_read_word(pdo,
1320 HPI_HIF_ADDR(message_buffer_address));
1321 phw->message_buffer_address_on_dsp = address;
1322 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1323 && --timeout);
1324 if (!timeout)
1325 return HPI6000_ERROR_MSG_GET_ADR;
1326 } else
1327 address = phw->message_buffer_address_on_dsp;
1328
719f82d3
EB		 1329 length = phm->size;
1330
3285ea10 1331 /* send the message */
719f82d3
EB		 1332 p_data = (u32 *)phm;
1333 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1334 (u16)length / 4))
1335 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1336
1337 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1338 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1339 hpi6000_send_dsp_interrupt(pdo);
1340
1341 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1342 if (ack & HPI_HIF_ERROR_MASK)
1343 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1344
3285ea10 1345 /* get the response address */
719f82d3
EB		 1346 if (phw->response_buffer_address_on_dsp == 0) {
1347 timeout = TIMEOUT;
1348 do {
1349 address =
1350 hpi_read_word(pdo,
1351 HPI_HIF_ADDR(response_buffer_address));
1352 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1353 && --timeout);
1354 phw->response_buffer_address_on_dsp = address;
1355
1356 if (!timeout)
1357 return HPI6000_ERROR_RESP_GET_ADR;
1358 } else
1359 address = phw->response_buffer_address_on_dsp;
1360
1361 /* read the length of the response back from the DSP */
1362 timeout = TIMEOUT;
1363 do {
1364 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1365 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1366 if (!timeout)
1367 length = sizeof(struct hpi_response);
1368
3285ea10 1369 /* get the response */
719f82d3
EB		 1370 p_data = (u32 *)phr;
1371 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1372 (u16)length / 4))
1373 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1374
1375 /* set i/f back to idle */
1376 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1377 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1378 hpi6000_send_dsp_interrupt(pdo);
1379
1380 error = hpi_validate_response(phm, phr);
1381 return error;
1382}
1383
1384/* have to set up the below defines to match stuff in the MAP file */
1385
1386#define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1387#define MSG_LENGTH 11
1388#define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1389#define RESP_LENGTH 16
1390#define QUEUE_START (HPI_HIF_BASE+0x88)
1391#define QUEUE_SIZE 0x8000
1392
1393static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1394{
1395/*#define CHECKING // comment this line in to enable checking */
1396#ifdef CHECKING
1397 if (address < (u32)MSG_ADDRESS)
1398 return 0;
1399 if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1400 return 0;
1401 if ((address + (length_in_dwords << 2)) >
1402 (u32)(QUEUE_START + QUEUE_SIZE))
1403 return 0;
1404#else
1405 (void)address;
1406 (void)length_in_dwords;
1407 return 1;
1408#endif
1409}
1410
1411static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1412 struct hpi_message *phm, struct hpi_response *phr)
1413{
1414 struct dsp_obj *pdo =
1415 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1416 u32 data_sent = 0;
1417 u16 ack;
1418 u32 length, address;
1419 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1420 u16 time_out = 8;
1421
1422 (void)phr;
1423
1424 /* round dwDataSize down to nearest 4 bytes */
1425 while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1426 && --time_out) {
1427 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1428 if (ack & HPI_HIF_ERROR_MASK)
1429 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1430
1431 if (hpi6000_send_host_command(pao, dsp_index,
1432 HPI_HIF_SEND_DATA))
1433 return HPI6000_ERROR_SEND_DATA_CMD;
1434
1435 hpi6000_send_dsp_interrupt(pdo);
1436
1437 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1438
1439 if (ack & HPI_HIF_ERROR_MASK)
1440 return HPI6000_ERROR_SEND_DATA_ACK;
1441
1442 do {
1443 /* get the address and size */
1444 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1445 /* DSP returns number of DWORDS */
1446 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1447 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1448
1449 if (!hpi6000_send_data_check_adr(address, length))
1450 return HPI6000_ERROR_SEND_DATA_ADR;
1451
1452 /* send the data. break data into 512 DWORD blocks (2K bytes)
1453 * and send using block write. 2Kbytes is the max as this is the
1454 * memory window given to the HPI data register by the PCI2040
1455 */
1456
1457 {
1458 u32 len = length;
1459 u32 blk_len = 512;
1460 while (len) {
1461 if (len < blk_len)
1462 blk_len = len;
1463 if (hpi6000_dsp_block_write32(pao, dsp_index,
1464 address, p_data, blk_len))
1465 return HPI6000_ERROR_SEND_DATA_WRITE;
1466 address += blk_len * 4;
1467 p_data += blk_len;
1468 len -= blk_len;
1469 }
1470 }
1471
1472 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1473 return HPI6000_ERROR_SEND_DATA_IDLECMD;
1474
1475 hpi6000_send_dsp_interrupt(pdo);
1476
1477 data_sent += length * 4;
1478 }
1479 if (!time_out)
1480 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1481 return 0;
1482}
1483
1484static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1485 struct hpi_message *phm, struct hpi_response *phr)
1486{
1487 struct dsp_obj *pdo =
1488 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1489 u32 data_got = 0;
1490 u16 ack;
1491 u32 length, address;
1492 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1493
1494 (void)phr; /* this parameter not used! */
1495
1496 /* round dwDataSize down to nearest 4 bytes */
1497 while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1498 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1499 if (ack & HPI_HIF_ERROR_MASK)
1500 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1501
1502 if (hpi6000_send_host_command(pao, dsp_index,
1503 HPI_HIF_GET_DATA))
1504 return HPI6000_ERROR_GET_DATA_CMD;
1505 hpi6000_send_dsp_interrupt(pdo);
1506
1507 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1508
1509 if (ack & HPI_HIF_ERROR_MASK)
1510 return HPI6000_ERROR_GET_DATA_ACK;
1511
1512 /* get the address and size */
1513 do {
1514 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1515 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1516 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1517
1518 /* read the data */
1519 {
1520 u32 len = length;
1521 u32 blk_len = 512;
1522 while (len) {
1523 if (len < blk_len)
1524 blk_len = len;
1525 if (hpi6000_dsp_block_read32(pao, dsp_index,
1526 address, p_data, blk_len))
1527 return HPI6000_ERROR_GET_DATA_READ;
1528 address += blk_len * 4;
1529 p_data += blk_len;
1530 len -= blk_len;
1531 }
1532 }
1533
1534 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1535 return HPI6000_ERROR_GET_DATA_IDLECMD;
1536 hpi6000_send_dsp_interrupt(pdo);
1537
1538 data_got += length * 4;
1539 }
1540 return 0;
1541}
1542
1543static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1544{
1545 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
1546}
1547
1548static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1549 u16 dsp_index, u32 host_cmd)
1550{
1551 struct dsp_obj *pdo =
1552 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1553 u32 timeout = TIMEOUT;
1554
1555 /* set command */
1556 do {
1557 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1558 /* flush the FIFO */
1559 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1560 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1561
1562 /* reset the interrupt bit */
1563 iowrite32(0x00040004, pdo->prHPI_control);
1564
1565 if (timeout)
1566 return 0;
1567 else
1568 return 1;
1569}
1570
1571/* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1572static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1573 u16 read_or_write)
1574{
1575 u32 hPI_error;
1576
1577 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1578
1579 /* read the error bits from the PCI2040 */
1580 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1581 if (hPI_error) {
1582 /* reset the error flag */
1583 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1584 phw->pCI2040HPI_error_count++;
1585 if (read_or_write == 1)
1586 gw_pci_read_asserts++; /************* inc global */
1587 else
1588 gw_pci_write_asserts++;
1589 return 1;
1590 } else
1591 return 0;
1592}
1593
1594static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1595 u32 ack_value)
1596{
1597 struct dsp_obj *pdo =
1598 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1599 u32 ack = 0L;
1600 u32 timeout;
1601 u32 hPIC = 0L;
1602
1603 /* wait for host interrupt to signal ack is ready */
1604 timeout = TIMEOUT;
1605 while (--timeout) {
1606 hPIC = ioread32(pdo->prHPI_control);
1607 if (hPIC & 0x04) /* 0x04 = HINT from DSP */
1608 break;
1609 }
1610 if (timeout == 0)
1611 return HPI_HIF_ERROR_MASK;
1612
1613 /* wait for dwAckValue */
1614 timeout = TIMEOUT;
1615 while (--timeout) {
1616 /* read the ack mailbox */
1617 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1618 if (ack == ack_value)
1619 break;
1620 if ((ack & HPI_HIF_ERROR_MASK)
1621 && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1622 break;
1623 /*for (i=0;i<1000;i++) */
1624 /* dwPause=i+1; */
1625 }
1626 if (ack & HPI_HIF_ERROR_MASK)
1627 /* indicates bad read from DSP -
1628 typically 0xffffff is read for some reason */
1629 ack = HPI_HIF_ERROR_MASK;
1630
1631 if (timeout == 0)
1632 ack = HPI_HIF_ERROR_MASK;
1633 return (short)ack;
1634}
1635
1636static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1637 struct hpi_message *phm)
1638{
1639 const u16 dsp_index = 0;
1640 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1641 struct dsp_obj *pdo = &phw->ado[dsp_index];
1642 u32 timeout;
1643 u32 cache_dirty_flag;
1644 u16 err;
1645
1646 hpios_dsplock_lock(pao);
1647
1648 timeout = TIMEOUT;
1649 do {
1650 cache_dirty_flag =
1651 hpi_read_word((struct dsp_obj *)pdo,
1652 HPI_HIF_ADDR(control_cache_is_dirty));
1653 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1654 if (!timeout) {
1655 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1656 goto unlock;
1657 }
1658
1659 if (cache_dirty_flag) {
1660 /* read the cached controls */
1661 u32 address;
1662 u32 length;
1663
1664 timeout = TIMEOUT;
1665 if (pdo->control_cache_address_on_dsp == 0) {
1666 do {
1667 address =
1668 hpi_read_word((struct dsp_obj *)pdo,
1669 HPI_HIF_ADDR(control_cache_address));
1670
1671 length = hpi_read_word((struct dsp_obj *)pdo,
1672 HPI_HIF_ADDR
1673 (control_cache_size_in_bytes));
1674 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1675 && --timeout);
1676 if (!timeout) {
1677 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1678 goto unlock;
1679 }
1680 pdo->control_cache_address_on_dsp = address;
1681 pdo->control_cache_length_on_dsp = length;
1682 } else {
1683 address = pdo->control_cache_address_on_dsp;
1684 length = pdo->control_cache_length_on_dsp;
1685 }
1686
1687 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1688 (u32 *)&phw->control_cache[0],
1689 length / sizeof(u32))) {
1690 err = HPI6000_ERROR_CONTROL_CACHE_READ;
1691 goto unlock;
1692 }
1693 do {
1694 hpi_write_word((struct dsp_obj *)pdo,
1695 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1696 /* flush the FIFO */
1697 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1698 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1699 && --timeout);
1700 if (!timeout) {
1701 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1702 goto unlock;
1703 }
1704
1705 }
1706 err = 0;
1707
1708unlock:
1709 hpios_dsplock_unlock(pao);
1710 return err;
1711}
1712
1713/** Get dsp index for multi DSP adapters only */
1714static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1715{
1716 u16 ret = 0;
1717 switch (phm->object) {
1718 case HPI_OBJ_ISTREAM:
1719 if (phm->obj_index < 2)
1720 ret = 1;
1721 break;
1722 case HPI_OBJ_PROFILE:
1723 ret = phm->obj_index;
1724 break;
1725 default:
1726 break;
1727 }
1728 return ret;
1729}
1730
1731/** Complete transaction with DSP
1732
1733Send message, get response, send or get stream data if any.
1734*/
1735static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1736 struct hpi_response *phr)
1737{
1738 u16 error = 0;
1739 u16 dsp_index = 0;
1740 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
719f82d3
EB		 1741
1742 if (num_dsp < 2)
1743 dsp_index = 0;
1744 else {
1745 dsp_index = get_dsp_index(pao, phm);
1746
1747 /* is this checked on the DSP anyway? */
1748 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1749 || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1750 struct hpi_message hm;
1751 u16 add_index;
1752 hm.obj_index = phm->u.d.u.stream.stream_index;
1753 hm.object = phm->u.d.u.stream.object_type;
1754 add_index = get_dsp_index(pao, &hm);
1755 if (add_index != dsp_index) {
1756 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1757 return;
1758 }
1759 }
1760 }
bca516bf
EB		 1761
1762 hpios_dsplock_lock(pao);
719f82d3
EB		 1763 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1764
1765 /* maybe an error response */
1766 if (error) {
1767 /* something failed in the HPI/DSP interface */
1768 phr->error = error;
1769 /* just the header of the response is valid */
1770 phr->size = sizeof(struct hpi_response_header);
1771 goto err;
1772 }
1773
1774 if (phr->error != 0) /* something failed in the DSP */
1775 goto err;
1776
1777 switch (phm->function) {
1778 case HPI_OSTREAM_WRITE:
1779 case HPI_ISTREAM_ANC_WRITE:
1780 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1781 break;
1782 case HPI_ISTREAM_READ:
1783 case HPI_OSTREAM_ANC_READ:
1784 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1785 break;
1786 case HPI_ADAPTER_GET_ASSERT:
3285ea10 1787 phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
719f82d3 1788 if (num_dsp == 2) {
3285ea10 1789 if (!phr->u.ax.assert.count) {
719f82d3
EB		 1790 /* no assert from dsp 0, check dsp 1 */
1791 error = hpi6000_message_response_sequence(pao,
1792 1, phm, phr);
3285ea10 1793 phr->u.ax.assert.dsp_index = 1;
719f82d3
EB		 1794 }
1795 }
1796 }
1797
1798 if (error)
1799 phr->error = error;
1800
1801err:
1802 hpios_dsplock_unlock(pao);
1803 return;
1804}
Linux kernel - Deliverables
This page took 0.129252 seconds and 5 git commands to generate.