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ALSA: asihpi - Increase debug response buffer size.
[deliverable/linux.git] / sound / pci / asihpi / hpi6205.c
CommitLineData
719f82d3
EB		 1/******************************************************************************
2
3 AudioScience HPI driver
40818b62 4 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
719f82d3
EB		 5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience
20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
21 These PCI and PCIe bus adapters are based on a
22 TMS320C6205 PCI bus mastering DSP,
23 and (except ASI50xx) TI TMS320C6xxx floating point DSP
24
25 Exported function:
26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
27
28(C) Copyright AudioScience Inc. 1998-2010
29*******************************************************************************/
30#define SOURCEFILE_NAME "hpi6205.c"
31
32#include "hpi_internal.h"
33#include "hpimsginit.h"
34#include "hpidebug.h"
35#include "hpi6205.h"
36#include "hpidspcd.h"
37#include "hpicmn.h"
38
39/*****************************************************************************/
40/* HPI6205 specific error codes */
deb21a23 41#define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
3285ea10
EB		 42
43/* operational/messaging errors */
44#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
45#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
46
47/* initialization/bootload errors */
719f82d3
EB		 48#define HPI6205_ERROR_6205_NO_IRQ 1002
49#define HPI6205_ERROR_6205_INIT_FAILED 1003
719f82d3
EB		 50#define HPI6205_ERROR_6205_REG 1006
51#define HPI6205_ERROR_6205_DSPPAGE 1007
719f82d3
EB		 52#define HPI6205_ERROR_C6713_HPIC 1009
53#define HPI6205_ERROR_C6713_HPIA 1010
54#define HPI6205_ERROR_C6713_PLL 1011
55#define HPI6205_ERROR_DSP_INTMEM 1012
56#define HPI6205_ERROR_DSP_EXTMEM 1013
57#define HPI6205_ERROR_DSP_PLD 1014
719f82d3
EB		 58#define HPI6205_ERROR_6205_EEPROM 1017
59#define HPI6205_ERROR_DSP_EMIF 1018
60
719f82d3
EB		 61/*****************************************************************************/
62/* for C6205 PCI i/f */
63/* Host Status Register (HSR) bitfields */
64#define C6205_HSR_INTSRC 0x01
65#define C6205_HSR_INTAVAL 0x02
66#define C6205_HSR_INTAM 0x04
67#define C6205_HSR_CFGERR 0x08
68#define C6205_HSR_EEREAD 0x10
69/* Host-to-DSP Control Register (HDCR) bitfields */
70#define C6205_HDCR_WARMRESET 0x01
71#define C6205_HDCR_DSPINT 0x02
72#define C6205_HDCR_PCIBOOT 0x04
73/* DSP Page Register (DSPP) bitfields, */
74/* defines 4 Mbyte page that BAR0 points to */
75#define C6205_DSPP_MAP1 0x400
76
77/* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
78 * BAR1 maps to non-prefetchable 8 Mbyte memory block
79 * of DSP memory mapped registers (starting at 0x01800000).
80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
81 * needs to be added to the BAR1 base address set in the PCI config reg
82 */
83#define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
84#define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
85#define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
86#define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
87
88/* used to control LED (revA) and reset C6713 (revB) */
89#define C6205_BAR0_TIMER1_CTL (0x01980000L)
90
91/* For first 6713 in CE1 space, using DA17,16,2 */
92#define HPICL_ADDR 0x01400000L
93#define HPICH_ADDR 0x01400004L
94#define HPIAL_ADDR 0x01410000L
95#define HPIAH_ADDR 0x01410004L
96#define HPIDIL_ADDR 0x01420000L
97#define HPIDIH_ADDR 0x01420004L
98#define HPIDL_ADDR 0x01430000L
99#define HPIDH_ADDR 0x01430004L
100
101#define C6713_EMIF_GCTL 0x01800000
102#define C6713_EMIF_CE1 0x01800004
103#define C6713_EMIF_CE0 0x01800008
104#define C6713_EMIF_CE2 0x01800010
105#define C6713_EMIF_CE3 0x01800014
106#define C6713_EMIF_SDRAMCTL 0x01800018
107#define C6713_EMIF_SDRAMTIMING 0x0180001C
108#define C6713_EMIF_SDRAMEXT 0x01800020
109
110struct hpi_hw_obj {
111 /* PCI registers */
112 __iomem u32 *prHSR;
113 __iomem u32 *prHDCR;
114 __iomem u32 *prDSPP;
115
116 u32 dsp_page;
117
118 struct consistent_dma_area h_locked_mem;
119 struct bus_master_interface *p_interface_buffer;
120
121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
122 /* a non-NULL handle means there is an HPI allocated buffer */
123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
125 /* non-zero size means a buffer exists, may be external */
126 u32 instream_host_buffer_size[HPI_MAX_STREAMS];
127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
128
129 struct consistent_dma_area h_control_cache;
719f82d3
EB		 130 struct hpi_control_cache *p_cache;
131};
132
133/*****************************************************************************/
134/* local prototypes */
135
136#define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
137
138static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
139
140static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
141
142static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
143 u32 *pos_error_code);
144
145static u16 message_response_sequence(struct hpi_adapter_obj *pao,
146 struct hpi_message *phm, struct hpi_response *phr);
147
148static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
149 struct hpi_response *phr);
150
151#define HPI6205_TIMEOUT 1000000
152
153static void subsys_create_adapter(struct hpi_message *phm,
154 struct hpi_response *phr);
6d0b898e
EB		 155static void adapter_delete(struct hpi_adapter_obj *pao,
156 struct hpi_message *phm, struct hpi_response *phr);
719f82d3
EB		 157
158static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
159 u32 *pos_error_code);
160
161static void delete_adapter_obj(struct hpi_adapter_obj *pao);
162
163static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
164 struct hpi_message *phm, struct hpi_response *phr);
165
166static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
167 struct hpi_message *phm, struct hpi_response *phr);
168
169static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm, struct hpi_response *phr);
171static void outstream_write(struct hpi_adapter_obj *pao,
172 struct hpi_message *phm, struct hpi_response *phr);
173
174static void outstream_get_info(struct hpi_adapter_obj *pao,
175 struct hpi_message *phm, struct hpi_response *phr);
176
177static void outstream_start(struct hpi_adapter_obj *pao,
178 struct hpi_message *phm, struct hpi_response *phr);
179
180static void outstream_open(struct hpi_adapter_obj *pao,
181 struct hpi_message *phm, struct hpi_response *phr);
182
183static void outstream_reset(struct hpi_adapter_obj *pao,
184 struct hpi_message *phm, struct hpi_response *phr);
185
186static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
187 struct hpi_message *phm, struct hpi_response *phr);
188
189static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
190 struct hpi_message *phm, struct hpi_response *phr);
191
192static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
193 struct hpi_message *phm, struct hpi_response *phr);
194
195static void instream_read(struct hpi_adapter_obj *pao,
196 struct hpi_message *phm, struct hpi_response *phr);
197
198static void instream_get_info(struct hpi_adapter_obj *pao,
199 struct hpi_message *phm, struct hpi_response *phr);
200
201static void instream_start(struct hpi_adapter_obj *pao,
202 struct hpi_message *phm, struct hpi_response *phr);
203
204static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
205 u32 address);
206
3285ea10
EB		 207static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
208 int dsp_index, u32 address, u32 data);
719f82d3
EB		 209
210static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
211 int dsp_index);
212
213static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
214 u32 address, u32 length);
215
216static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
217 int dsp_index);
218
219static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
220 int dsp_index);
221
222static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
223
224/*****************************************************************************/
225
6d0b898e
EB		 226static void subsys_message(struct hpi_adapter_obj *pao,
227 struct hpi_message *phm, struct hpi_response *phr)
719f82d3 228{
719f82d3 229 switch (phm->function) {
719f82d3
EB		 230 case HPI_SUBSYS_CREATE_ADAPTER:
231 subsys_create_adapter(phm, phr);
232 break;
719f82d3
EB		 233 default:
234 phr->error = HPI_ERROR_INVALID_FUNC;
235 break;
236 }
237}
238
239static void control_message(struct hpi_adapter_obj *pao,
240 struct hpi_message *phm, struct hpi_response *phr)
241{
242
243 struct hpi_hw_obj *phw = pao->priv;
3285ea10 244 u16 pending_cache_error = 0;
719f82d3
EB		 245
246 switch (phm->function) {
247 case HPI_CONTROL_GET_STATE:
248 if (pao->has_control_cache) {
3285ea10
EB		 249 rmb(); /* make sure we see updates DMAed from DSP */
250 if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
719f82d3 251 break;
3285ea10
EB		 252 } else if (phm->u.c.attribute == HPI_METER_PEAK) {
253 pending_cache_error =
254 HPI_ERROR_CONTROL_CACHING;
255 }
719f82d3
EB		 256 }
257 hw_message(pao, phm, phr);
3285ea10
EB		 258 if (pending_cache_error && !phr->error)
259 phr->error = pending_cache_error;
719f82d3
EB		 260 break;
261 case HPI_CONTROL_GET_INFO:
262 hw_message(pao, phm, phr);
263 break;
264 case HPI_CONTROL_SET_STATE:
265 hw_message(pao, phm, phr);
266 if (pao->has_control_cache)
3285ea10
EB		 267 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
268 phr);
719f82d3
EB		 269 break;
270 default:
271 phr->error = HPI_ERROR_INVALID_FUNC;
272 break;
273 }
274}
275
276static void adapter_message(struct hpi_adapter_obj *pao,
277 struct hpi_message *phm, struct hpi_response *phr)
278{
279 switch (phm->function) {
6d0b898e
EB		 280 case HPI_ADAPTER_DELETE:
281 adapter_delete(pao, phm, phr);
282 break;
283
719f82d3
EB		 284 default:
285 hw_message(pao, phm, phr);
286 break;
287 }
288}
289
290static void outstream_message(struct hpi_adapter_obj *pao,
291 struct hpi_message *phm, struct hpi_response *phr)
292{
293
294 if (phm->obj_index >= HPI_MAX_STREAMS) {
deb21a23 295 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
719f82d3 296 HPI_DEBUG_LOG(WARNING,
3285ea10 297 "Message referencing invalid stream %d "
719f82d3
EB		 298 "on adapter index %d\n", phm->obj_index,
299 phm->adapter_index);
300 return;
301 }
302
303 switch (phm->function) {
304 case HPI_OSTREAM_WRITE:
305 outstream_write(pao, phm, phr);
306 break;
307 case HPI_OSTREAM_GET_INFO:
308 outstream_get_info(pao, phm, phr);
309 break;
310 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
311 outstream_host_buffer_allocate(pao, phm, phr);
312 break;
313 case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
314 outstream_host_buffer_get_info(pao, phm, phr);
315 break;
316 case HPI_OSTREAM_HOSTBUFFER_FREE:
317 outstream_host_buffer_free(pao, phm, phr);
318 break;
319 case HPI_OSTREAM_START:
320 outstream_start(pao, phm, phr);
321 break;
322 case HPI_OSTREAM_OPEN:
323 outstream_open(pao, phm, phr);
324 break;
325 case HPI_OSTREAM_RESET:
326 outstream_reset(pao, phm, phr);
327 break;
328 default:
329 hw_message(pao, phm, phr);
330 break;
331 }
332}
333
334static void instream_message(struct hpi_adapter_obj *pao,
335 struct hpi_message *phm, struct hpi_response *phr)
336{
337
338 if (phm->obj_index >= HPI_MAX_STREAMS) {
deb21a23 339 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
719f82d3 340 HPI_DEBUG_LOG(WARNING,
3285ea10 341 "Message referencing invalid stream %d "
719f82d3
EB		 342 "on adapter index %d\n", phm->obj_index,
343 phm->adapter_index);
344 return;
345 }
346
347 switch (phm->function) {
348 case HPI_ISTREAM_READ:
349 instream_read(pao, phm, phr);
350 break;
351 case HPI_ISTREAM_GET_INFO:
352 instream_get_info(pao, phm, phr);
353 break;
354 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
355 instream_host_buffer_allocate(pao, phm, phr);
356 break;
357 case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
358 instream_host_buffer_get_info(pao, phm, phr);
359 break;
360 case HPI_ISTREAM_HOSTBUFFER_FREE:
361 instream_host_buffer_free(pao, phm, phr);
362 break;
363 case HPI_ISTREAM_START:
364 instream_start(pao, phm, phr);
365 break;
366 default:
367 hw_message(pao, phm, phr);
368 break;
369 }
370}
371
372/*****************************************************************************/
373/** Entry point to this HPI backend
374 * All calls to the HPI start here
375 */
33162d2d 376static
6d0b898e
EB		 377void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
378 struct hpi_response *phr)
719f82d3 379{
6d0b898e
EB		 380 if (pao && (pao->dsp_crashed >= 10)
381 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
382 /* allow last resort debug read even after crash */
383 hpi_init_response(phr, phm->object, phm->function,
384 HPI_ERROR_DSP_HARDWARE);
385 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
386 phm->function);
387 return;
719f82d3
EB		 388 }
389
390 /* Init default response */
391 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
3285ea10 392 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
719f82d3
EB		 393
394 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
395 switch (phm->type) {
82b5774f 396 case HPI_TYPE_REQUEST:
719f82d3
EB		 397 switch (phm->object) {
398 case HPI_OBJ_SUBSYSTEM:
6d0b898e 399 subsys_message(pao, phm, phr);
719f82d3
EB		 400 break;
401
402 case HPI_OBJ_ADAPTER:
719f82d3
EB		 403 adapter_message(pao, phm, phr);
404 break;
405
719f82d3
EB		 406 case HPI_OBJ_CONTROL:
407 control_message(pao, phm, phr);
408 break;
409
410 case HPI_OBJ_OSTREAM:
411 outstream_message(pao, phm, phr);
412 break;
413
414 case HPI_OBJ_ISTREAM:
415 instream_message(pao, phm, phr);
416 break;
417
418 default:
419 hw_message(pao, phm, phr);
420 break;
421 }
422 break;
423
424 default:
425 phr->error = HPI_ERROR_INVALID_TYPE;
426 break;
427 }
428}
429
6d0b898e
EB		 430void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
431{
432 struct hpi_adapter_obj *pao = NULL;
433
434 if (phm->object != HPI_OBJ_SUBSYSTEM) {
435 /* normal messages must have valid adapter index */
436 pao = hpi_find_adapter(phm->adapter_index);
437 } else {
438 /* subsys messages don't address an adapter */
439 _HPI_6205(NULL, phm, phr);
440 return;
441 }
442
443 if (pao)
444 _HPI_6205(pao, phm, phr);
445 else
446 hpi_init_response(phr, phm->object, phm->function,
447 HPI_ERROR_BAD_ADAPTER_NUMBER);
448}
449
719f82d3
EB		 450/*****************************************************************************/
451/* SUBSYSTEM */
452
453/** Create an adapter object and initialise it based on resource information
454 * passed in in the message
455 * *** NOTE - you cannot use this function AND the FindAdapters function at the
456 * same time, the application must use only one of them to get the adapters ***
457 */
458static void subsys_create_adapter(struct hpi_message *phm,
459 struct hpi_response *phr)
460{
461 /* create temp adapter obj, because we don't know what index yet */
462 struct hpi_adapter_obj ao;
463 u32 os_error_code;
464 u16 err;
465
466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
467
468 memset(&ao, 0, sizeof(ao));
469
550a8b69 470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
719f82d3 471 if (!ao.priv) {
25985edc 472 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
719f82d3
EB		 473 phr->error = HPI_ERROR_MEMORY_ALLOC;
474 return;
475 }
719f82d3
EB		 476
477 ao.pci = *phm->u.s.resource.r.pci;
478 err = create_adapter_obj(&ao, &os_error_code);
719f82d3 479 if (err) {
719f82d3 480 delete_adapter_obj(&ao);
0a00044d
EB		 481 if (err >= HPI_ERROR_BACKEND_BASE) {
482 phr->error = HPI_ERROR_DSP_BOOTLOAD;
483 phr->specific_error = err;
484 } else {
485 phr->error = err;
486 }
3285ea10 487 phr->u.s.data = os_error_code;
719f82d3
EB		 488 return;
489 }
490
2f918a64 491 phr->u.s.adapter_type = ao.adapter_type;
719f82d3 492 phr->u.s.adapter_index = ao.index;
719f82d3
EB		 493 phr->error = 0;
494}
495
496/** delete an adapter - required by WDM driver */
6d0b898e
EB		 497static void adapter_delete(struct hpi_adapter_obj *pao,
498 struct hpi_message *phm, struct hpi_response *phr)
719f82d3 499{
719f82d3
EB		 500 struct hpi_hw_obj *phw;
501
719f82d3
EB		 502 if (!pao) {
503 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
504 return;
505 }
506 phw = (struct hpi_hw_obj *)pao->priv;
507 /* reset adapter h/w */
508 /* Reset C6713 #1 */
509 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
510 /* reset C6205 */
511 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
512
513 delete_adapter_obj(pao);
3285ea10 514 hpi_delete_adapter(pao);
719f82d3
EB		 515 phr->error = 0;
516}
517
518/** Create adapter object
519 allocate buffers, bootload DSPs, initialise control cache
520*/
521static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
522 u32 *pos_error_code)
523{
524 struct hpi_hw_obj *phw = pao->priv;
525 struct bus_master_interface *interface;
526 u32 phys_addr;
719f82d3
EB		 527 int i;
528 u16 err;
529
530 /* init error reporting */
531 pao->dsp_crashed = 0;
532
533 for (i = 0; i < HPI_MAX_STREAMS; i++)
534 phw->flag_outstream_just_reset[i] = 1;
535
536 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
537 phw->prHSR =
538 pao->pci.ap_mem_base[1] +
539 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
540 phw->prHDCR =
541 pao->pci.ap_mem_base[1] +
542 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
543 phw->prDSPP =
544 pao->pci.ap_mem_base[1] +
545 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
546
547 pao->has_control_cache = 0;
548
549 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
550 sizeof(struct bus_master_interface),
3285ea10 551 pao->pci.pci_dev))
719f82d3
EB		 552 phw->p_interface_buffer = NULL;
553 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
554 (void *)&phw->p_interface_buffer))
555 phw->p_interface_buffer = NULL;
556
557 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
558 phw->p_interface_buffer);
559
560 if (phw->p_interface_buffer) {
561 memset((void *)phw->p_interface_buffer, 0,
562 sizeof(struct bus_master_interface));
563 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
564 }
565
566 err = adapter_boot_load_dsp(pao, pos_error_code);
6d0b898e
EB		 567 if (err) {
568 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
719f82d3
EB		 569 /* no need to clean up as SubSysCreateAdapter */
570 /* calls DeleteAdapter on error. */
571 return err;
6d0b898e 572 }
719f82d3
EB		 573 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
574
575 /* allow boot load even if mem alloc wont work */
576 if (!phw->p_interface_buffer)
3285ea10 577 return HPI_ERROR_MEMORY_ALLOC;
719f82d3
EB		 578
579 interface = phw->p_interface_buffer;
580
719f82d3
EB		 581 /* make sure the DSP has started ok */
582 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
583 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
3285ea10 584 return HPI6205_ERROR_6205_INIT_FAILED;
719f82d3
EB		 585 }
586 /* Note that *pao, *phw are zeroed after allocation,
587 * so pointers and flags are NULL by default.
588 * Allocate bus mastering control cache buffer and tell the DSP about it
589 */
590 if (interface->control_cache.number_of_controls) {
3285ea10 591 u8 *p_control_cache_virtual;
719f82d3
EB		 592
593 err = hpios_locked_mem_alloc(&phw->h_control_cache,
594 interface->control_cache.size_in_bytes,
3285ea10 595 pao->pci.pci_dev);
719f82d3
EB		 596 if (!err)
597 err = hpios_locked_mem_get_virt_addr(&phw->
3285ea10
EB		 598 h_control_cache,
599 (void *)&p_control_cache_virtual);
719f82d3
EB		 600 if (!err) {
601 memset(p_control_cache_virtual, 0,
602 interface->control_cache.size_in_bytes);
603
604 phw->p_cache =
605 hpi_alloc_control_cache(interface->
606 control_cache.number_of_controls,
607 interface->control_cache.size_in_bytes,
719f82d3 608 p_control_cache_virtual);
6d0b898e 609
fd0977d0
JJ		 610 if (!phw->p_cache)
611 err = HPI_ERROR_MEMORY_ALLOC;
719f82d3
EB		 612 }
613 if (!err) {
614 err = hpios_locked_mem_get_phys_addr(&phw->
615 h_control_cache, &phys_addr);
616 interface->control_cache.physical_address32 =
617 phys_addr;
618 }
619
620 if (!err)
621 pao->has_control_cache = 1;
622 else {
623 if (hpios_locked_mem_valid(&phw->h_control_cache))
624 hpios_locked_mem_free(&phw->h_control_cache);
625 pao->has_control_cache = 0;
626 }
627 }
719f82d3
EB		 628 send_dsp_command(phw, H620_HIF_IDLE);
629
630 {
3285ea10
EB		 631 struct hpi_message hm;
632 struct hpi_response hr;
719f82d3
EB		 633 u32 max_streams;
634
635 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
3285ea10 636 memset(&hm, 0, sizeof(hm));
82b5774f
EB		 637 /* wAdapterIndex == version == 0 */
638 hm.type = HPI_TYPE_REQUEST;
3285ea10
EB		 639 hm.size = sizeof(hm);
640 hm.object = HPI_OBJ_ADAPTER;
641 hm.function = HPI_ADAPTER_GET_INFO;
82b5774f 642
3285ea10
EB		 643 memset(&hr, 0, sizeof(hr));
644 hr.size = sizeof(hr);
645
646 err = message_response_sequence(pao, &hm, &hr);
719f82d3
EB		 647 if (err) {
648 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
649 err);
650 return err;
651 }
3285ea10
EB		 652 if (hr.error)
653 return hr.error;
719f82d3 654
3285ea10
EB		 655 pao->adapter_type = hr.u.ax.info.adapter_type;
656 pao->index = hr.u.ax.info.adapter_index;
719f82d3 657
3285ea10
EB		 658 max_streams =
659 hr.u.ax.info.num_outstreams +
660 hr.u.ax.info.num_instreams;
719f82d3 661
719f82d3
EB		 662 HPI_DEBUG_LOG(VERBOSE,
663 "got adapter info type %x index %d serial %d\n",
3285ea10
EB		 664 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
665 hr.u.ax.info.serial_number);
719f82d3
EB		 666 }
667
668 pao->open = 0; /* upon creation the adapter is closed */
669
ffdb5787
EB		 670 if (phw->p_cache)
671 phw->p_cache->adap_idx = pao->index;
672
719f82d3 673 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
3285ea10
EB		 674
675 return hpi_add_adapter(pao);
719f82d3
EB		 676}
677
678/** Free memory areas allocated by adapter
6d0b898e 679 * this routine is called from AdapterDelete,
719f82d3
EB		 680 * and SubSysCreateAdapter if duplicate index
681*/
682static void delete_adapter_obj(struct hpi_adapter_obj *pao)
683{
6d0b898e 684 struct hpi_hw_obj *phw = pao->priv;
719f82d3
EB		 685 int i;
686
719f82d3
EB		 687 if (hpios_locked_mem_valid(&phw->h_control_cache)) {
688 hpios_locked_mem_free(&phw->h_control_cache);
689 hpi_free_control_cache(phw->p_cache);
690 }
691
692 if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
693 hpios_locked_mem_free(&phw->h_locked_mem);
694 phw->p_interface_buffer = NULL;
695 }
696
697 for (i = 0; i < HPI_MAX_STREAMS; i++)
698 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
699 hpios_locked_mem_free(&phw->instream_host_buffers[i]);
700 /*?phw->InStreamHostBuffers[i] = NULL; */
701 phw->instream_host_buffer_size[i] = 0;
702 }
703
704 for (i = 0; i < HPI_MAX_STREAMS; i++)
705 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
706 hpios_locked_mem_free(&phw->outstream_host_buffers
707 [i]);
708 phw->outstream_host_buffer_size[i] = 0;
709 }
719f82d3
EB		 710 kfree(phw);
711}
712
1d595d2a
EB		 713/*****************************************************************************/
714/* Adapter functions */
715
719f82d3
EB		 716/*****************************************************************************/
717/* OutStream Host buffer functions */
718
719/** Allocate or attach buffer for busmastering
720*/
721static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
722 struct hpi_message *phm, struct hpi_response *phr)
723{
724 u16 err = 0;
725 u32 command = phm->u.d.u.buffer.command;
726 struct hpi_hw_obj *phw = pao->priv;
727 struct bus_master_interface *interface = phw->p_interface_buffer;
728
729 hpi_init_response(phr, phm->object, phm->function, 0);
730
731 if (command == HPI_BUFFER_CMD_EXTERNAL
732 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
733 /* ALLOC phase, allocate a buffer with power of 2 size,
734 get its bus address for PCI bus mastering
735 */
736 phm->u.d.u.buffer.buffer_size =
737 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
738 /* return old size and allocated size,
739 so caller can detect change */
740 phr->u.d.u.stream_info.data_available =
741 phw->outstream_host_buffer_size[phm->obj_index];
742 phr->u.d.u.stream_info.buffer_size =
743 phm->u.d.u.buffer.buffer_size;
744
745 if (phw->outstream_host_buffer_size[phm->obj_index] ==
746 phm->u.d.u.buffer.buffer_size) {
747 /* Same size, no action required */
748 return;
749 }
750
751 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
752 obj_index]))
753 hpios_locked_mem_free(&phw->outstream_host_buffers
754 [phm->obj_index]);
755
756 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
757 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
3285ea10 758 pao->pci.pci_dev);
719f82d3
EB		 759
760 if (err) {
761 phr->error = HPI_ERROR_INVALID_DATASIZE;
762 phw->outstream_host_buffer_size[phm->obj_index] = 0;
763 return;
764 }
765
766 err = hpios_locked_mem_get_phys_addr
767 (&phw->outstream_host_buffers[phm->obj_index],
768 &phm->u.d.u.buffer.pci_address);
769 /* get the phys addr into msg for single call alloc caller
770 * needs to do this for split alloc (or use the same message)
771 * return the phy address for split alloc in the respose too
772 */
773 phr->u.d.u.stream_info.auxiliary_data_available =
774 phm->u.d.u.buffer.pci_address;
775
776 if (err) {
777 hpios_locked_mem_free(&phw->outstream_host_buffers
778 [phm->obj_index]);
779 phw->outstream_host_buffer_size[phm->obj_index] = 0;
780 phr->error = HPI_ERROR_MEMORY_ALLOC;
781 return;
782 }
783 }
784
785 if (command == HPI_BUFFER_CMD_EXTERNAL
786 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
787 /* GRANT phase. Set up the BBM status, tell the DSP about
788 the buffer so it can start using BBM.
789 */
790 struct hpi_hostbuffer_status *status;
791
792 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
793 buffer_size - 1)) {
794 HPI_DEBUG_LOG(ERROR,
3285ea10 795 "Buffer size must be 2^N not %d\n",
719f82d3
EB		 796 phm->u.d.u.buffer.buffer_size);
797 phr->error = HPI_ERROR_INVALID_DATASIZE;
798 return;
799 }
800 phw->outstream_host_buffer_size[phm->obj_index] =
801 phm->u.d.u.buffer.buffer_size;
802 status = &interface->outstream_host_buffer_status[phm->
803 obj_index];
804 status->samples_processed = 0;
805 status->stream_state = HPI_STATE_STOPPED;
8e0874ea
EB		 806 status->dsp_index = 0;
807 status->host_index = status->dsp_index;
719f82d3 808 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
deb21a23 809 status->auxiliary_data_available = 0;
719f82d3
EB		 810
811 hw_message(pao, phm, phr);
812
813 if (phr->error
814 && hpios_locked_mem_valid(&phw->
815 outstream_host_buffers[phm->obj_index])) {
816 hpios_locked_mem_free(&phw->outstream_host_buffers
817 [phm->obj_index]);
818 phw->outstream_host_buffer_size[phm->obj_index] = 0;
819 }
820 }
821}
822
823static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
824 struct hpi_message *phm, struct hpi_response *phr)
825{
826 struct hpi_hw_obj *phw = pao->priv;
827 struct bus_master_interface *interface = phw->p_interface_buffer;
828 struct hpi_hostbuffer_status *status;
829 u8 *p_bbm_data;
830
831 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
832 obj_index])) {
833 if (hpios_locked_mem_get_virt_addr(&phw->
834 outstream_host_buffers[phm->obj_index],
835 (void *)&p_bbm_data)) {
836 phr->error = HPI_ERROR_INVALID_OPERATION;
837 return;
838 }
839 status = &interface->outstream_host_buffer_status[phm->
840 obj_index];
841 hpi_init_response(phr, HPI_OBJ_OSTREAM,
842 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
843 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
844 phr->u.d.u.hostbuffer_info.p_status = status;
845 } else {
846 hpi_init_response(phr, HPI_OBJ_OSTREAM,
847 HPI_OSTREAM_HOSTBUFFER_GET_INFO,
848 HPI_ERROR_INVALID_OPERATION);
849 }
850}
851
852static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
853 struct hpi_message *phm, struct hpi_response *phr)
854{
855 struct hpi_hw_obj *phw = pao->priv;
856 u32 command = phm->u.d.u.buffer.command;
857
858 if (phw->outstream_host_buffer_size[phm->obj_index]) {
859 if (command == HPI_BUFFER_CMD_EXTERNAL
860 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
861 phw->outstream_host_buffer_size[phm->obj_index] = 0;
862 hw_message(pao, phm, phr);
863 /* Tell adapter to stop using the host buffer. */
864 }
865 if (command == HPI_BUFFER_CMD_EXTERNAL
866 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
867 hpios_locked_mem_free(&phw->outstream_host_buffers
868 [phm->obj_index]);
869 }
870 /* Should HPI_ERROR_INVALID_OPERATION be returned
871 if no host buffer is allocated? */
872 else
873 hpi_init_response(phr, HPI_OBJ_OSTREAM,
874 HPI_OSTREAM_HOSTBUFFER_FREE, 0);
875
876}
877
60f1deb5 878static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
719f82d3 879{
2a383cb3 880 return status->size_in_bytes - (status->host_index -
8e0874ea 881 status->dsp_index);
719f82d3
EB		 882}
883
884static void outstream_write(struct hpi_adapter_obj *pao,
885 struct hpi_message *phm, struct hpi_response *phr)
886{
887 struct hpi_hw_obj *phw = pao->priv;
888 struct bus_master_interface *interface = phw->p_interface_buffer;
889 struct hpi_hostbuffer_status *status;
2a383cb3 890 u32 space_available;
719f82d3
EB		 891
892 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
893 /* there is no BBM buffer, write via message */
894 hw_message(pao, phm, phr);
895 return;
896 }
897
898 hpi_init_response(phr, phm->object, phm->function, 0);
899 status = &interface->outstream_host_buffer_status[phm->obj_index];
900
719f82d3 901 space_available = outstream_get_space_available(status);
2a383cb3 902 if (space_available < phm->u.d.u.data.data_size) {
719f82d3
EB		 903 phr->error = HPI_ERROR_INVALID_DATASIZE;
904 return;
905 }
906
907 /* HostBuffers is used to indicate host buffer is internally allocated.
908 otherwise, assumed external, data written externally */
909 if (phm->u.d.u.data.pb_data
910 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
911 obj_index])) {
912 u8 *p_bbm_data;
2a383cb3 913 u32 l_first_write;
719f82d3
EB		 914 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
915
916 if (hpios_locked_mem_get_virt_addr(&phw->
917 outstream_host_buffers[phm->obj_index],
918 (void *)&p_bbm_data)) {
919 phr->error = HPI_ERROR_INVALID_OPERATION;
920 return;
921 }
922
923 /* either all data,
924 or enough to fit from current to end of BBM buffer */
925 l_first_write =
926 min(phm->u.d.u.data.data_size,
927 status->size_in_bytes -
928 (status->host_index & (status->size_in_bytes - 1)));
929
930 memcpy(p_bbm_data +
931 (status->host_index & (status->size_in_bytes - 1)),
932 p_app_data, l_first_write);
933 /* remaining data if any */
934 memcpy(p_bbm_data, p_app_data + l_first_write,
935 phm->u.d.u.data.data_size - l_first_write);
936 }
3285ea10
EB		 937
938 /*
939 * This version relies on the DSP code triggering an OStream buffer
940 * update immediately following a SET_FORMAT call. The host has
deb21a23
EB		 941 * already written data into the BBM buffer, but the DSP won't know
942 * about it until dwHostIndex is adjusted.
3285ea10
EB		 943 */
944 if (phw->flag_outstream_just_reset[phm->obj_index]) {
945 /* Format can only change after reset. Must tell DSP. */
946 u16 function = phm->function;
947 phw->flag_outstream_just_reset[phm->obj_index] = 0;
948 phm->function = HPI_OSTREAM_SET_FORMAT;
949 hw_message(pao, phm, phr); /* send the format to the DSP */
950 phm->function = function;
951 if (phr->error)
952 return;
953 }
954
719f82d3
EB		 955 status->host_index += phm->u.d.u.data.data_size;
956}
957
958static void outstream_get_info(struct hpi_adapter_obj *pao,
959 struct hpi_message *phm, struct hpi_response *phr)
960{
961 struct hpi_hw_obj *phw = pao->priv;
962 struct bus_master_interface *interface = phw->p_interface_buffer;
963 struct hpi_hostbuffer_status *status;
964
965 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
966 hw_message(pao, phm, phr);
967 return;
968 }
969
970 hpi_init_response(phr, phm->object, phm->function, 0);
971
972 status = &interface->outstream_host_buffer_status[phm->obj_index];
973
974 phr->u.d.u.stream_info.state = (u16)status->stream_state;
975 phr->u.d.u.stream_info.samples_transferred =
976 status->samples_processed;
977 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
978 phr->u.d.u.stream_info.data_available =
979 status->size_in_bytes - outstream_get_space_available(status);
980 phr->u.d.u.stream_info.auxiliary_data_available =
981 status->auxiliary_data_available;
982}
983
984static void outstream_start(struct hpi_adapter_obj *pao,
985 struct hpi_message *phm, struct hpi_response *phr)
986{
987 hw_message(pao, phm, phr);
988}
989
990static void outstream_reset(struct hpi_adapter_obj *pao,
991 struct hpi_message *phm, struct hpi_response *phr)
992{
993 struct hpi_hw_obj *phw = pao->priv;
994 phw->flag_outstream_just_reset[phm->obj_index] = 1;
995 hw_message(pao, phm, phr);
996}
997
998static void outstream_open(struct hpi_adapter_obj *pao,
999 struct hpi_message *phm, struct hpi_response *phr)
1000{
1001 outstream_reset(pao, phm, phr);
1002}
1003
1004/*****************************************************************************/
1005/* InStream Host buffer functions */
1006
1007static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1008 struct hpi_message *phm, struct hpi_response *phr)
1009{
1010 u16 err = 0;
1011 u32 command = phm->u.d.u.buffer.command;
1012 struct hpi_hw_obj *phw = pao->priv;
1013 struct bus_master_interface *interface = phw->p_interface_buffer;
1014
1015 hpi_init_response(phr, phm->object, phm->function, 0);
1016
1017 if (command == HPI_BUFFER_CMD_EXTERNAL
1018 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1019
1020 phm->u.d.u.buffer.buffer_size =
1021 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1022 phr->u.d.u.stream_info.data_available =
1023 phw->instream_host_buffer_size[phm->obj_index];
1024 phr->u.d.u.stream_info.buffer_size =
1025 phm->u.d.u.buffer.buffer_size;
1026
1027 if (phw->instream_host_buffer_size[phm->obj_index] ==
1028 phm->u.d.u.buffer.buffer_size) {
1029 /* Same size, no action required */
1030 return;
1031 }
1032
1033 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1034 obj_index]))
1035 hpios_locked_mem_free(&phw->instream_host_buffers
1036 [phm->obj_index]);
1037
1038 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1039 obj_index], phm->u.d.u.buffer.buffer_size,
3285ea10 1040 pao->pci.pci_dev);
719f82d3
EB		 1041
1042 if (err) {
1043 phr->error = HPI_ERROR_INVALID_DATASIZE;
1044 phw->instream_host_buffer_size[phm->obj_index] = 0;
1045 return;
1046 }
1047
1048 err = hpios_locked_mem_get_phys_addr
1049 (&phw->instream_host_buffers[phm->obj_index],
1050 &phm->u.d.u.buffer.pci_address);
1051 /* get the phys addr into msg for single call alloc. Caller
1052 needs to do this for split alloc so return the phy address */
1053 phr->u.d.u.stream_info.auxiliary_data_available =
1054 phm->u.d.u.buffer.pci_address;
1055 if (err) {
1056 hpios_locked_mem_free(&phw->instream_host_buffers
1057 [phm->obj_index]);
1058 phw->instream_host_buffer_size[phm->obj_index] = 0;
1059 phr->error = HPI_ERROR_MEMORY_ALLOC;
1060 return;
1061 }
1062 }
1063
1064 if (command == HPI_BUFFER_CMD_EXTERNAL
1065 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1066 struct hpi_hostbuffer_status *status;
1067
1068 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1069 buffer_size - 1)) {
1070 HPI_DEBUG_LOG(ERROR,
3285ea10 1071 "Buffer size must be 2^N not %d\n",
719f82d3
EB		 1072 phm->u.d.u.buffer.buffer_size);
1073 phr->error = HPI_ERROR_INVALID_DATASIZE;
1074 return;
1075 }
1076
1077 phw->instream_host_buffer_size[phm->obj_index] =
1078 phm->u.d.u.buffer.buffer_size;
1079 status = &interface->instream_host_buffer_status[phm->
1080 obj_index];
1081 status->samples_processed = 0;
1082 status->stream_state = HPI_STATE_STOPPED;
8e0874ea
EB		 1083 status->dsp_index = 0;
1084 status->host_index = status->dsp_index;
719f82d3 1085 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
deb21a23 1086 status->auxiliary_data_available = 0;
719f82d3
EB		 1087
1088 hw_message(pao, phm, phr);
ba3a9099 1089
719f82d3
EB		 1090 if (phr->error
1091 && hpios_locked_mem_valid(&phw->
1092 instream_host_buffers[phm->obj_index])) {
1093 hpios_locked_mem_free(&phw->instream_host_buffers
1094 [phm->obj_index]);
1095 phw->instream_host_buffer_size[phm->obj_index] = 0;
1096 }
1097 }
1098}
1099
1100static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1101 struct hpi_message *phm, struct hpi_response *phr)
1102{
1103 struct hpi_hw_obj *phw = pao->priv;
1104 struct bus_master_interface *interface = phw->p_interface_buffer;
1105 struct hpi_hostbuffer_status *status;
1106 u8 *p_bbm_data;
1107
1108 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1109 obj_index])) {
1110 if (hpios_locked_mem_get_virt_addr(&phw->
1111 instream_host_buffers[phm->obj_index],
1112 (void *)&p_bbm_data)) {
1113 phr->error = HPI_ERROR_INVALID_OPERATION;
1114 return;
1115 }
1116 status = &interface->instream_host_buffer_status[phm->
1117 obj_index];
1118 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1119 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1120 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1121 phr->u.d.u.hostbuffer_info.p_status = status;
1122 } else {
1123 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1124 HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1125 HPI_ERROR_INVALID_OPERATION);
1126 }
1127}
1128
1129static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1130 struct hpi_message *phm, struct hpi_response *phr)
1131{
1132 struct hpi_hw_obj *phw = pao->priv;
1133 u32 command = phm->u.d.u.buffer.command;
1134
1135 if (phw->instream_host_buffer_size[phm->obj_index]) {
1136 if (command == HPI_BUFFER_CMD_EXTERNAL
1137 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1138 phw->instream_host_buffer_size[phm->obj_index] = 0;
1139 hw_message(pao, phm, phr);
1140 }
1141
1142 if (command == HPI_BUFFER_CMD_EXTERNAL
1143 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1144 hpios_locked_mem_free(&phw->instream_host_buffers
1145 [phm->obj_index]);
1146
1147 } else {
1148 /* Should HPI_ERROR_INVALID_OPERATION be returned
1149 if no host buffer is allocated? */
1150 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1151 HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1152
1153 }
1154
1155}
1156
1157static void instream_start(struct hpi_adapter_obj *pao,
1158 struct hpi_message *phm, struct hpi_response *phr)
1159{
1160 hw_message(pao, phm, phr);
1161}
1162
2a383cb3 1163static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
719f82d3 1164{
8e0874ea 1165 return status->dsp_index - status->host_index;
719f82d3
EB		 1166}
1167
1168static void instream_read(struct hpi_adapter_obj *pao,
1169 struct hpi_message *phm, struct hpi_response *phr)
1170{
1171 struct hpi_hw_obj *phw = pao->priv;
1172 struct bus_master_interface *interface = phw->p_interface_buffer;
1173 struct hpi_hostbuffer_status *status;
2a383cb3 1174 u32 data_available;
719f82d3 1175 u8 *p_bbm_data;
2a383cb3 1176 u32 l_first_read;
719f82d3
EB		 1177 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1178
1179 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1180 hw_message(pao, phm, phr);
1181 return;
1182 }
1183 hpi_init_response(phr, phm->object, phm->function, 0);
1184
1185 status = &interface->instream_host_buffer_status[phm->obj_index];
1186 data_available = instream_get_bytes_available(status);
2a383cb3 1187 if (data_available < phm->u.d.u.data.data_size) {
719f82d3
EB		 1188 phr->error = HPI_ERROR_INVALID_DATASIZE;
1189 return;
1190 }
1191
1192 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1193 obj_index])) {
1194 if (hpios_locked_mem_get_virt_addr(&phw->
1195 instream_host_buffers[phm->obj_index],
1196 (void *)&p_bbm_data)) {
1197 phr->error = HPI_ERROR_INVALID_OPERATION;
1198 return;
1199 }
1200
1201 /* either all data,
1202 or enough to fit from current to end of BBM buffer */
1203 l_first_read =
1204 min(phm->u.d.u.data.data_size,
1205 status->size_in_bytes -
1206 (status->host_index & (status->size_in_bytes - 1)));
1207
1208 memcpy(p_app_data,
1209 p_bbm_data +
1210 (status->host_index & (status->size_in_bytes - 1)),
1211 l_first_read);
1212 /* remaining data if any */
1213 memcpy(p_app_data + l_first_read, p_bbm_data,
1214 phm->u.d.u.data.data_size - l_first_read);
1215 }
1216 status->host_index += phm->u.d.u.data.data_size;
1217}
1218
1219static void instream_get_info(struct hpi_adapter_obj *pao,
1220 struct hpi_message *phm, struct hpi_response *phr)
1221{
1222 struct hpi_hw_obj *phw = pao->priv;
1223 struct bus_master_interface *interface = phw->p_interface_buffer;
1224 struct hpi_hostbuffer_status *status;
1225 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1226 hw_message(pao, phm, phr);
1227 return;
1228 }
1229
1230 status = &interface->instream_host_buffer_status[phm->obj_index];
1231
1232 hpi_init_response(phr, phm->object, phm->function, 0);
1233
1234 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1235 phr->u.d.u.stream_info.samples_transferred =
1236 status->samples_processed;
1237 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1238 phr->u.d.u.stream_info.data_available =
1239 instream_get_bytes_available(status);
1240 phr->u.d.u.stream_info.auxiliary_data_available =
1241 status->auxiliary_data_available;
1242}
1243
1244/*****************************************************************************/
1245/* LOW-LEVEL */
1246#define HPI6205_MAX_FILES_TO_LOAD 2
1247
1248static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1249 u32 *pos_error_code)
1250{
1251 struct hpi_hw_obj *phw = pao->priv;
1252 struct dsp_code dsp_code;
1253 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
719f82d3
EB		 1254 u32 temp;
1255 int dsp = 0, i = 0;
1256 u16 err = 0;
1257
1258 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1259
ee246fc0
EB		 1260 boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
1261 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
1262
1263 /* fix up cases where bootcode id[1] != subsys id */
1264 switch (boot_code_id[1]) {
719f82d3 1265 case HPI_ADAPTER_FAMILY_ASI(0x5000):
ee246fc0
EB		 1266 boot_code_id[0] = boot_code_id[1];
1267 boot_code_id[1] = 0;
719f82d3
EB		 1268 break;
1269 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1270 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1271 case HPI_ADAPTER_FAMILY_ASI(0x6300):
ee246fc0 1272 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
719f82d3 1273 break;
6d0b898e 1274 case HPI_ADAPTER_FAMILY_ASI(0x5500):
719f82d3
EB		 1275 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1276 case HPI_ADAPTER_FAMILY_ASI(0x6500):
ee246fc0 1277 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
719f82d3 1278 break;
cadae428 1279 case HPI_ADAPTER_FAMILY_ASI(0x8800):
ee246fc0
EB		 1280 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
1281 break;
1282 default:
cadae428 1283 break;
719f82d3 1284 }
719f82d3
EB		 1285
1286 /* reset DSP by writing a 1 to the WARMRESET bit */
1287 temp = C6205_HDCR_WARMRESET;
1288 iowrite32(temp, phw->prHDCR);
1289 hpios_delay_micro_seconds(1000);
1290
1291 /* check that PCI i/f was configured by EEPROM */
1292 temp = ioread32(phw->prHSR);
1293 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1294 C6205_HSR_EEREAD)
3285ea10 1295 return HPI6205_ERROR_6205_EEPROM;
719f82d3
EB		 1296 temp |= 0x04;
1297 /* disable PINTA interrupt */
1298 iowrite32(temp, phw->prHSR);
1299
1300 /* check control register reports PCI boot mode */
1301 temp = ioread32(phw->prHDCR);
1302 if (!(temp & C6205_HDCR_PCIBOOT))
3285ea10 1303 return HPI6205_ERROR_6205_REG;
719f82d3 1304
3285ea10 1305 /* try writing a few numbers to the DSP page register */
719f82d3 1306 /* and reading them back. */
3285ea10 1307 temp = 3;
719f82d3
EB		 1308 iowrite32(temp, phw->prDSPP);
1309 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
3285ea10 1310 return HPI6205_ERROR_6205_DSPPAGE;
719f82d3
EB		 1311 temp = 2;
1312 iowrite32(temp, phw->prDSPP);
1313 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
3285ea10
EB		 1314 return HPI6205_ERROR_6205_DSPPAGE;
1315 temp = 1;
719f82d3
EB		 1316 iowrite32(temp, phw->prDSPP);
1317 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
3285ea10 1318 return HPI6205_ERROR_6205_DSPPAGE;
719f82d3
EB		 1319 /* reset DSP page to the correct number */
1320 temp = 0;
1321 iowrite32(temp, phw->prDSPP);
1322 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
3285ea10 1323 return HPI6205_ERROR_6205_DSPPAGE;
719f82d3
EB		 1324 phw->dsp_page = 0;
1325
1326 /* release 6713 from reset before 6205 is bootloaded.
1327 This ensures that the EMIF is inactive,
1328 and the 6713 HPI gets the correct bootmode etc
1329 */
1330 if (boot_code_id[1] != 0) {
1331 /* DSP 1 is a C6713 */
1332 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1333 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202);
1334 hpios_delay_micro_seconds(100);
1335 /* Reset the 6713 #1 - revB */
1336 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1337
1338 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1339 boot_loader_read_mem32(pao, 0, 0);
1340
1341 hpios_delay_micro_seconds(100);
1342 /* Release C6713 from reset - revB */
1343 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1344 hpios_delay_micro_seconds(100);
1345 }
1346
1347 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1348 /* is there a DSP to load? */
1349 if (boot_code_id[dsp] == 0)
1350 continue;
1351
1352 err = boot_loader_config_emif(pao, dsp);
1353 if (err)
1354 return err;
1355
1356 err = boot_loader_test_internal_memory(pao, dsp);
1357 if (err)
1358 return err;
1359
1360 err = boot_loader_test_external_memory(pao, dsp);
1361 if (err)
1362 return err;
1363
1364 err = boot_loader_test_pld(pao, dsp);
1365 if (err)
1366 return err;
1367
1368 /* write the DSP code down into the DSPs memory */
95a4c6e7
EB		 1369 err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
1370 &dsp_code, pos_error_code);
719f82d3
EB		 1371 if (err)
1372 return err;
1373
1374 while (1) {
1375 u32 length;
1376 u32 address;
1377 u32 type;
1378 u32 *pcode;
1379
1380 err = hpi_dsp_code_read_word(&dsp_code, &length);
1381 if (err)
1382 break;
1383 if (length == 0xFFFFFFFF)
1384 break; /* end of code */
1385
1386 err = hpi_dsp_code_read_word(&dsp_code, &address);
1387 if (err)
1388 break;
1389 err = hpi_dsp_code_read_word(&dsp_code, &type);
1390 if (err)
1391 break;
1392 err = hpi_dsp_code_read_block(length, &dsp_code,
1393 &pcode);
1394 if (err)
1395 break;
1396 for (i = 0; i < (int)length; i++) {
3285ea10
EB		 1397 boot_loader_write_mem32(pao, dsp, address,
1398 *pcode);
719f82d3
EB		 1399 /* dummy read every 4 words */
1400 /* for 6205 advisory 1.4.4 */
1401 if (i % 4 == 0)
1402 boot_loader_read_mem32(pao, dsp,
1403 address);
1404 pcode++;
1405 address += 4;
1406 }
1407
1408 }
1409 if (err) {
1410 hpi_dsp_code_close(&dsp_code);
1411 return err;
1412 }
1413
1414 /* verify code */
1415 hpi_dsp_code_rewind(&dsp_code);
1416 while (1) {
1417 u32 length = 0;
1418 u32 address = 0;
1419 u32 type = 0;
1420 u32 *pcode = NULL;
1421 u32 data = 0;
1422
1423 hpi_dsp_code_read_word(&dsp_code, &length);
1424 if (length == 0xFFFFFFFF)
1425 break; /* end of code */
1426
1427 hpi_dsp_code_read_word(&dsp_code, &address);
1428 hpi_dsp_code_read_word(&dsp_code, &type);
1429 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1430
1431 for (i = 0; i < (int)length; i++) {
1432 data = boot_loader_read_mem32(pao, dsp,
1433 address);
1434 if (data != *pcode) {
1435 err = 0;
1436 break;
1437 }
1438 pcode++;
1439 address += 4;
1440 }
1441 if (err)
1442 break;
1443 }
1444 hpi_dsp_code_close(&dsp_code);
1445 if (err)
1446 return err;
1447 }
1448
1449 /* After bootloading all DSPs, start DSP0 running
1450 * The DSP0 code will handle starting and synchronizing with its slaves
1451 */
1452 if (phw->p_interface_buffer) {
1453 /* we need to tell the card the physical PCI address */
1454 u32 physicalPC_iaddress;
1455 struct bus_master_interface *interface =
1456 phw->p_interface_buffer;
1457 u32 host_mailbox_address_on_dsp;
1458 u32 physicalPC_iaddress_verify = 0;
1459 int time_out = 10;
1460 /* set ack so we know when DSP is ready to go */
1461 /* (dwDspAck will be changed to HIF_RESET) */
1462 interface->dsp_ack = H620_HIF_UNKNOWN;
1463 wmb(); /* ensure ack is written before dsp writes back */
1464
1465 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1466 &physicalPC_iaddress);
1467
1468 /* locate the host mailbox on the DSP. */
1469 host_mailbox_address_on_dsp = 0x80000000;
1470 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1471 && time_out--) {
3285ea10 1472 boot_loader_write_mem32(pao, 0,
719f82d3
EB		 1473 host_mailbox_address_on_dsp,
1474 physicalPC_iaddress);
1475 physicalPC_iaddress_verify =
1476 boot_loader_read_mem32(pao, 0,
1477 host_mailbox_address_on_dsp);
1478 }
1479 }
1480 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1481 /* enable interrupts */
1482 temp = ioread32(phw->prHSR);
1483 temp &= ~(u32)C6205_HSR_INTAM;
1484 iowrite32(temp, phw->prHSR);
1485
1486 /* start code running... */
1487 temp = ioread32(phw->prHDCR);
1488 temp |= (u32)C6205_HDCR_DSPINT;
1489 iowrite32(temp, phw->prHDCR);
1490
1491 /* give the DSP 10ms to start up */
1492 hpios_delay_micro_seconds(10000);
1493 return err;
1494
1495}
1496
1497/*****************************************************************************/
1498/* Bootloader utility functions */
1499
1500static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1501 u32 address)
1502{
1503 struct hpi_hw_obj *phw = pao->priv;
1504 u32 data = 0;
1505 __iomem u32 *p_data;
1506
1507 if (dsp_index == 0) {
1508 /* DSP 0 is always C6205 */
1509 if ((address >= 0x01800000) & (address < 0x02000000)) {
1510 /* BAR1 register access */
1511 p_data = pao->pci.ap_mem_base[1] +
1512 (address & 0x007fffff) /
1513 sizeof(*pao->pci.ap_mem_base[1]);
1514 /* HPI_DEBUG_LOG(WARNING,
1515 "BAR1 access %08x\n", dwAddress); */
1516 } else {
1517 u32 dw4M_page = address >> 22L;
1518 if (dw4M_page != phw->dsp_page) {
1519 phw->dsp_page = dw4M_page;
1520 /* *INDENT OFF* */
1521 iowrite32(phw->dsp_page, phw->prDSPP);
1522 /* *INDENT-ON* */
1523 }
1524 address &= 0x3fffff; /* address within 4M page */
1525 /* BAR0 memory access */
1526 p_data = pao->pci.ap_mem_base[0] +
1527 address / sizeof(u32);
1528 }
1529 data = ioread32(p_data);
1530 } else if (dsp_index == 1) {
1531 /* DSP 1 is a C6713 */
1532 u32 lsb;
1533 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1534 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1535 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1536 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1537 data = (data << 16) | (lsb & 0xFFFF);
1538 }
1539 return data;
1540}
1541
3285ea10
EB		 1542static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1543 int dsp_index, u32 address, u32 data)
719f82d3
EB		 1544{
1545 struct hpi_hw_obj *phw = pao->priv;
719f82d3
EB		 1546 __iomem u32 *p_data;
1547 /* u32 dwVerifyData=0; */
1548
1549 if (dsp_index == 0) {
1550 /* DSP 0 is always C6205 */
1551 if ((address >= 0x01800000) & (address < 0x02000000)) {
1552 /* BAR1 - DSP register access using */
1553 /* Non-prefetchable PCI access */
1554 p_data = pao->pci.ap_mem_base[1] +
1555 (address & 0x007fffff) /
1556 sizeof(*pao->pci.ap_mem_base[1]);
1557 } else {
1558 /* BAR0 access - all of DSP memory using */
1559 /* pre-fetchable PCI access */
1560 u32 dw4M_page = address >> 22L;
1561 if (dw4M_page != phw->dsp_page) {
1562 phw->dsp_page = dw4M_page;
1563 /* *INDENT-OFF* */
1564 iowrite32(phw->dsp_page, phw->prDSPP);
1565 /* *INDENT-ON* */
1566 }
1567 address &= 0x3fffff; /* address within 4M page */
1568 p_data = pao->pci.ap_mem_base[0] +
1569 address / sizeof(u32);
1570 }
1571 iowrite32(data, p_data);
1572 } else if (dsp_index == 1) {
1573 /* DSP 1 is a C6713 */
1574 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1575 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1576
1577 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1578 boot_loader_read_mem32(pao, 0, 0);
1579
1580 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1581 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1582
1583 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1584 boot_loader_read_mem32(pao, 0, 0);
3285ea10 1585 }
719f82d3
EB		 1586}
1587
1588static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1589{
719f82d3
EB		 1590 if (dsp_index == 0) {
1591 u32 setting;
1592
1593 /* DSP 0 is always C6205 */
1594
1595 /* Set the EMIF */
1596 /* memory map of C6205 */
1597 /* 00000000-0000FFFF 16Kx32 internal program */
1598 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
1599
1600 /* EMIF config */
1601 /*------------ */
1602 /* Global EMIF control */
1603 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1604#define WS_OFS 28
1605#define WST_OFS 22
1606#define WH_OFS 20
1607#define RS_OFS 16
1608#define RST_OFS 8
1609#define MTYPE_OFS 4
1610#define RH_OFS 0
1611
1612 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1613 setting = 0x00000030;
1614 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1615 if (setting != boot_loader_read_mem32(pao, dsp_index,
1616 0x01800008))
3285ea10 1617 return HPI6205_ERROR_DSP_EMIF;
719f82d3
EB		 1618
1619 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1620 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1621 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1622 /* WST should be 71, but 63 is max possible */
1623 setting =
1624 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1625 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1626 (2L << MTYPE_OFS);
1627 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1628 if (setting != boot_loader_read_mem32(pao, dsp_index,
1629 0x01800004))
3285ea10 1630 return HPI6205_ERROR_DSP_EMIF;
719f82d3
EB		 1631
1632 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1633 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1634 /* plenty of wait states */
1635 setting =
1636 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1637 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1638 (2L << MTYPE_OFS);
1639 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1640 if (setting != boot_loader_read_mem32(pao, dsp_index,
1641 0x01800010))
3285ea10 1642 return HPI6205_ERROR_DSP_EMIF;
719f82d3
EB		 1643
1644 /* EMIF CE3 setup - 32 bit async. */
1645 /* This is the PLD on the ASI5000 cards only */
1646 setting =
1647 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1648 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1649 (2L << MTYPE_OFS);
1650 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1651 if (setting != boot_loader_read_mem32(pao, dsp_index,
1652 0x01800014))
3285ea10 1653 return HPI6205_ERROR_DSP_EMIF;
719f82d3
EB		 1654
1655 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1656 /* need to use this else DSP code crashes? */
1657 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1658 0x07117000);
1659
1660 /* EMIF SDRAM Refresh Timing */
1661 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
1662 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1663 0x00000410);
1664
1665 } else if (dsp_index == 1) {
1666 /* test access to the C6713s HPI registers */
1667 u32 write_data = 0, read_data = 0, i = 0;
1668
1669 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1670 write_data = 1;
1671 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1672 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1673 /* C67 HPI is on lower 16bits of 32bit EMIF */
1674 read_data =
1675 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1676 if (write_data != read_data) {
719f82d3
EB		 1677 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1678 read_data);
3285ea10 1679 return HPI6205_ERROR_C6713_HPIC;
719f82d3
EB		 1680 }
1681 /* HPIA - walking ones test */
1682 write_data = 1;
1683 for (i = 0; i < 32; i++) {
1684 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1685 write_data);
1686 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1687 (write_data >> 16));
1688 read_data =
1689 0xFFFF & boot_loader_read_mem32(pao, 0,
1690 HPIAL_ADDR);
1691 read_data =
1692 read_data | ((0xFFFF &
1693 boot_loader_read_mem32(pao, 0,
1694 HPIAH_ADDR))
1695 << 16);
1696 if (read_data != write_data) {
719f82d3
EB		 1697 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1698 write_data, read_data);
3285ea10 1699 return HPI6205_ERROR_C6713_HPIA;
719f82d3
EB		 1700 }
1701 write_data = write_data << 1;
1702 }
1703
1704 /* setup C67x PLL
1705 * ** C6713 datasheet says we cannot program PLL from HPI,
1706 * and indeed if we try to set the PLL multiply from the HPI,
1707 * the PLL does not seem to lock, so we enable the PLL and
1708 * use the default multiply of x 7, which for a 27MHz clock
1709 * gives a DSP speed of 189MHz
1710 */
1711 /* bypass PLL */
1712 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1713 hpios_delay_micro_seconds(1000);
1714 /* EMIF = 189/3=63MHz */
1715 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1716 /* peri = 189/2 */
1717 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1718 /* cpu = 189/1 */
1719 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1720 hpios_delay_micro_seconds(1000);
1721 /* ** SGT test to take GPO3 high when we start the PLL */
1722 /* and low when the delay is completed */
1723 /* FSX0 <- '1' (GPO3) */
1724 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1725 /* PLL not bypassed */
1726 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1727 hpios_delay_micro_seconds(1000);
1728 /* FSX0 <- '0' (GPO3) */
1729 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1730
1731 /* 6205 EMIF CE1 resetup - 32 bit async. */
1732 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1733 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */
1734 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1735 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1736 (2L << MTYPE_OFS));
1737
1738 hpios_delay_micro_seconds(1000);
1739
1740 /* check that we can read one of the PLL registers */
1741 /* PLL should not be bypassed! */
1742 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1743 != 0x0001) {
3285ea10 1744 return HPI6205_ERROR_C6713_PLL;
719f82d3
EB		 1745 }
1746 /* setup C67x EMIF (note this is the only use of
1747 BAR1 via BootLoader_WriteMem32) */
1748 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1749 0x000034A8);
1d595d2a
EB		 1750
1751 /* EMIF CE0 setup - 2Mx32 Sync DRAM
1752 31..28 Wr setup
1753 27..22 Wr strobe
1754 21..20 Wr hold
1755 19..16 Rd setup
1756 15..14 -
1757 13..8 Rd strobe
1758 7..4 MTYPE 0011 Sync DRAM 32bits
1759 3 Wr hold MSB
1760 2..0 Rd hold
1761 */
719f82d3
EB		 1762 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1763 0x00000030);
1d595d2a
EB		 1764
1765 /* EMIF SDRAM Extension
1766 0x00
1767 31-21 0000b 0000b 000b
1768 20 WR2RD = 2cycles-1 = 1b
1769
1770 19-18 WR2DEAC = 3cycle-1 = 10b
1771 17 WR2WR = 2cycle-1 = 1b
1772 16-15 R2WDQM = 4cycle-1 = 11b
1773 14-12 RD2WR = 6cycles-1 = 101b
1774
1775 11-10 RD2DEAC = 4cycle-1 = 11b
1776 9 RD2RD = 2cycle-1 = 1b
1777 8-7 THZP = 3cycle-1 = 10b
1778 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns)
1779 4 TRRD = 2cycle = 0b (tRRD = 14ns)
1780 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns)
1781 1 CAS latency = 3cyc = 1b
1782 (for Micron 2M32-7 operating at 100MHz)
1783 */
719f82d3
EB		 1784 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1785 0x001BDF29);
1d595d2a
EB		 1786
1787 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
1788 31 - 0b -
1789 30 SDBSZ 1b 4 bank
1790 29..28 SDRSZ 00b 11 row address pins
1791
1792 27..26 SDCSZ 01b 8 column address pins
1793 25 RFEN 1b refersh enabled
1794 24 INIT 1b init SDRAM!
1795
1796 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1
1797
1798 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1
1799
1800 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6
1801
1802 11..0 - 0000b 0000b 0000b
1803 */
719f82d3 1804 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1d595d2a
EB		 1805 0x47116000);
1806
1807 /* SDRAM refresh timing
1808 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
1809 */
719f82d3
EB		 1810 boot_loader_write_mem32(pao, dsp_index,
1811 C6713_EMIF_SDRAMTIMING, 0x00000410);
1812
1813 hpios_delay_micro_seconds(1000);
1814 } else if (dsp_index == 2) {
1815 /* DSP 2 is a C6713 */
3285ea10 1816 }
719f82d3 1817
3285ea10 1818 return 0;
719f82d3
EB		 1819}
1820
1821static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1822 u32 start_address, u32 length)
1823{
1824 u32 i = 0, j = 0;
1825 u32 test_addr = 0;
1826 u32 test_data = 0, data = 0;
1827
1828 length = 1000;
1829
1830 /* for 1st word, test each bit in the 32bit word, */
1831 /* dwLength specifies number of 32bit words to test */
1832 /*for(i=0; i<dwLength; i++) */
1833 i = 0;
1834 {
1835 test_addr = start_address + i * 4;
1836 test_data = 0x00000001;
1837 for (j = 0; j < 32; j++) {
1838 boot_loader_write_mem32(pao, dsp_index, test_addr,
1839 test_data);
1840 data = boot_loader_read_mem32(pao, dsp_index,
1841 test_addr);
1842 if (data != test_data) {
1843 HPI_DEBUG_LOG(VERBOSE,
3285ea10 1844 "Memtest error details "
719f82d3
EB		 1845 "%08x %08x %08x %i\n", test_addr,
1846 test_data, data, dsp_index);
1847 return 1; /* error */
1848 }
1849 test_data = test_data << 1;
1850 } /* for(j) */
1851 } /* for(i) */
1852
1853 /* for the next 100 locations test each location, leaving it as zero */
1854 /* write a zero to the next word in memory before we read */
1855 /* the previous write to make sure every memory location is unique */
1856 for (i = 0; i < 100; i++) {
1857 test_addr = start_address + i * 4;
1858 test_data = 0xA5A55A5A;
1859 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1860 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1861 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1862 if (data != test_data) {
1863 HPI_DEBUG_LOG(VERBOSE,
3285ea10 1864 "Memtest error details "
719f82d3
EB		 1865 "%08x %08x %08x %i\n", test_addr, test_data,
1866 data, dsp_index);
1867 return 1; /* error */
1868 }
1869 /* leave location as zero */
1870 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1871 }
1872
1873 /* zero out entire memory block */
1874 for (i = 0; i < length; i++) {
1875 test_addr = start_address + i * 4;
1876 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1877 }
1878 return 0;
1879}
1880
1881static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1882 int dsp_index)
1883{
1884 int err = 0;
1885 if (dsp_index == 0) {
1886 /* DSP 0 is a C6205 */
1887 /* 64K prog mem */
1888 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1889 0x10000);
1890 if (!err)
1891 /* 64K data mem */
1892 err = boot_loader_test_memory(pao, dsp_index,
1893 0x80000000, 0x10000);
3285ea10
EB		 1894 } else if (dsp_index == 1) {
1895 /* DSP 1 is a C6713 */
719f82d3
EB		 1896 /* 192K internal mem */
1897 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1898 0x30000);
1899 if (!err)
1900 /* 64K internal mem / L2 cache */
1901 err = boot_loader_test_memory(pao, dsp_index,
1902 0x00030000, 0x10000);
3285ea10 1903 }
719f82d3
EB		 1904
1905 if (err)
3285ea10 1906 return HPI6205_ERROR_DSP_INTMEM;
719f82d3
EB		 1907 else
1908 return 0;
1909}
1910
1911static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1912 int dsp_index)
1913{
1914 u32 dRAM_start_address = 0;
1915 u32 dRAM_size = 0;
1916
1917 if (dsp_index == 0) {
1918 /* only test for SDRAM if an ASI5000 card */
3285ea10 1919 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
719f82d3
EB		 1920 /* DSP 0 is always C6205 */
1921 dRAM_start_address = 0x00400000;
1922 dRAM_size = 0x200000;
1923 /*dwDRAMinc=1024; */
1924 } else
1925 return 0;
3285ea10 1926 } else if (dsp_index == 1) {
719f82d3
EB		 1927 /* DSP 1 is a C6713 */
1928 dRAM_start_address = 0x80000000;
1929 dRAM_size = 0x200000;
1930 /*dwDRAMinc=1024; */
3285ea10 1931 }
719f82d3
EB		 1932
1933 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1934 dRAM_size))
3285ea10 1935 return HPI6205_ERROR_DSP_EXTMEM;
719f82d3
EB		 1936 return 0;
1937}
1938
1939static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1940{
1941 u32 data = 0;
1942 if (dsp_index == 0) {
1943 /* only test for DSP0 PLD on ASI5000 card */
3285ea10 1944 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
719f82d3
EB		 1945 /* PLD is located at CE3=0x03000000 */
1946 data = boot_loader_read_mem32(pao, dsp_index,
1947 0x03000008);
1948 if ((data & 0xF) != 0x5)
3285ea10 1949 return HPI6205_ERROR_DSP_PLD;
719f82d3
EB		 1950 data = boot_loader_read_mem32(pao, dsp_index,
1951 0x0300000C);
1952 if ((data & 0xF) != 0xA)
3285ea10 1953 return HPI6205_ERROR_DSP_PLD;
719f82d3
EB		 1954 }
1955 } else if (dsp_index == 1) {
1956 /* DSP 1 is a C6713 */
3285ea10 1957 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
719f82d3
EB		 1958 /* PLD is located at CE1=0x90000000 */
1959 data = boot_loader_read_mem32(pao, dsp_index,
1960 0x90000010);
1961 if ((data & 0xFF) != 0xAA)
3285ea10 1962 return HPI6205_ERROR_DSP_PLD;
719f82d3
EB		 1963 /* 8713 - LED on */
1964 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1965 0x02);
1966 }
1967 }
1968 return 0;
1969}
1970
1971/** Transfer data to or from DSP
1972 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
1973*/
1974static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1975 u32 data_size, int operation)
1976{
1977 struct hpi_hw_obj *phw = pao->priv;
1978 u32 data_transferred = 0;
1979 u16 err = 0;
719f82d3
EB		 1980 u32 temp2;
1981 struct bus_master_interface *interface = phw->p_interface_buffer;
1982
1983 if (!p_data)
deb21a23 1984 return HPI_ERROR_INVALID_DATA_POINTER;
719f82d3
EB		 1985
1986 data_size &= ~3L; /* round data_size down to nearest 4 bytes */
1987
1988 /* make sure state is IDLE */
1989 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
1990 return HPI_ERROR_DSP_HARDWARE;
1991
1992 while (data_transferred < data_size) {
1993 u32 this_copy = data_size - data_transferred;
1994
1995 if (this_copy > HPI6205_SIZEOF_DATA)
1996 this_copy = HPI6205_SIZEOF_DATA;
1997
1998 if (operation == H620_HIF_SEND_DATA)
1999 memcpy((void *)&interface->u.b_data[0],
2000 &p_data[data_transferred], this_copy);
2001
2002 interface->transfer_size_in_bytes = this_copy;
2003
719f82d3
EB		 2004 /* DSP must change this back to nOperation */
2005 interface->dsp_ack = H620_HIF_IDLE;
719f82d3
EB		 2006 send_dsp_command(phw, operation);
2007
719f82d3
EB		 2008 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2009 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2010 HPI6205_TIMEOUT - temp2, this_copy);
2011
2012 if (!temp2) {
2013 /* timed out */
2014 HPI_DEBUG_LOG(ERROR,
3285ea10 2015 "Timed out waiting for " "state %d got %d\n",
719f82d3
EB		 2016 operation, interface->dsp_ack);
2017
2018 break;
2019 }
719f82d3
EB		 2020 if (operation == H620_HIF_GET_DATA)
2021 memcpy(&p_data[data_transferred],
2022 (void *)&interface->u.b_data[0], this_copy);
2023
2024 data_transferred += this_copy;
2025 }
2026 if (interface->dsp_ack != operation)
2027 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2028 interface->dsp_ack, operation);
2029 /* err=HPI_ERROR_DSP_HARDWARE; */
2030
2031 send_dsp_command(phw, H620_HIF_IDLE);
2032
2033 return err;
2034}
2035
2036/* wait for up to timeout_us microseconds for the DSP
2037 to signal state by DMA into dwDspAck
2038*/
2039static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2040{
2041 struct bus_master_interface *interface = phw->p_interface_buffer;
2042 int t = timeout_us / 4;
2043
2044 rmb(); /* ensure interface->dsp_ack is up to date */
2045 while ((interface->dsp_ack != state) && --t) {
2046 hpios_delay_micro_seconds(4);
2047 rmb(); /* DSP changes dsp_ack by DMA */
2048 }
2049
2050 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2051 return t * 4;
2052}
2053
2054/* set the busmaster interface to cmd, then interrupt the DSP */
2055static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2056{
2057 struct bus_master_interface *interface = phw->p_interface_buffer;
719f82d3
EB		 2058 u32 r;
2059
2060 interface->host_cmd = cmd;
2061 wmb(); /* DSP gets state by DMA, make sure it is written to memory */
2062 /* before we interrupt the DSP */
2063 r = ioread32(phw->prHDCR);
2064 r |= (u32)C6205_HDCR_DSPINT;
2065 iowrite32(r, phw->prHDCR);
2066 r &= ~(u32)C6205_HDCR_DSPINT;
2067 iowrite32(r, phw->prHDCR);
2068}
2069
2070static unsigned int message_count;
2071
2072static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2073 struct hpi_message *phm, struct hpi_response *phr)
2074{
719f82d3
EB		 2075 u32 time_out, time_out2;
2076 struct hpi_hw_obj *phw = pao->priv;
2077 struct bus_master_interface *interface = phw->p_interface_buffer;
2078 u16 err = 0;
2079
2080 message_count++;
c6c2c9ab 2081 if (phm->size > sizeof(interface->u.message_buffer)) {
deb21a23 2082 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
c6c2c9ab 2083 phr->specific_error = sizeof(interface->u.message_buffer);
3285ea10
EB		 2084 phr->size = sizeof(struct hpi_response_header);
2085 HPI_DEBUG_LOG(ERROR,
a2800300 2086 "message len %d too big for buffer %zd \n", phm->size,
c6c2c9ab 2087 sizeof(interface->u.message_buffer));
3285ea10
EB		 2088 return 0;
2089 }
2090
719f82d3
EB		 2091 /* Assume buffer of type struct bus_master_interface
2092 is allocated "noncacheable" */
2093
2094 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2095 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
3285ea10 2096 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
719f82d3 2097 }
3285ea10
EB		 2098
2099 memcpy(&interface->u.message_buffer, phm, phm->size);
719f82d3
EB		 2100 /* signal we want a response */
2101 send_dsp_command(phw, H620_HIF_GET_RESP);
2102
2103 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2104
3285ea10 2105 if (!time_out2) {
719f82d3 2106 HPI_DEBUG_LOG(ERROR,
3285ea10 2107 "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
719f82d3
EB		 2108 message_count, interface->dsp_ack);
2109 } else {
2110 HPI_DEBUG_LOG(VERBOSE,
2111 "(%u) transition to GET_RESP after %u\n",
2112 message_count, HPI6205_TIMEOUT - time_out2);
2113 }
2114 /* spin waiting on HIF interrupt flag (end of msg process) */
2115 time_out = HPI6205_TIMEOUT;
2116
719f82d3 2117 /* read the result */
3285ea10 2118 if (time_out) {
c6c2c9ab 2119 if (interface->u.response_buffer.response.size <= phr->size)
3285ea10 2120 memcpy(phr, &interface->u.response_buffer,
c6c2c9ab 2121 interface->u.response_buffer.response.size);
3285ea10
EB		 2122 else {
2123 HPI_DEBUG_LOG(ERROR,
2124 "response len %d too big for buffer %d\n",
c6c2c9ab
EB		 2125 interface->u.response_buffer.response.size,
2126 phr->size);
3285ea10
EB		 2127 memcpy(phr, &interface->u.response_buffer,
2128 sizeof(struct hpi_response_header));
2129 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2130 phr->specific_error =
c6c2c9ab 2131 interface->u.response_buffer.response.size;
3285ea10
EB		 2132 phr->size = sizeof(struct hpi_response_header);
2133 }
2134 }
719f82d3
EB		 2135 /* set interface back to idle */
2136 send_dsp_command(phw, H620_HIF_IDLE);
2137
3285ea10 2138 if (!time_out || !time_out2) {
719f82d3 2139 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
3285ea10 2140 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
719f82d3
EB		 2141 }
2142 /* special case for adapter close - */
2143 /* wait for the DSP to indicate it is idle */
2144 if (phm->function == HPI_ADAPTER_CLOSE) {
2145 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2146 HPI_DEBUG_LOG(DEBUG,
3285ea10 2147 "Timeout waiting for idle "
719f82d3 2148 "(on adapter_close)\n");
3285ea10 2149 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
719f82d3
EB		 2150 }
2151 }
2152 err = hpi_validate_response(phm, phr);
2153 return err;
2154}
2155
2156static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2157 struct hpi_response *phr)
2158{
2159
2160 u16 err = 0;
2161
2162 hpios_dsplock_lock(pao);
2163
2164 err = message_response_sequence(pao, phm, phr);
2165
2166 /* maybe an error response */
2167 if (err) {
2168 /* something failed in the HPI/DSP interface */
0a00044d
EB		 2169 if (err >= HPI_ERROR_BACKEND_BASE) {
2170 phr->error = HPI_ERROR_DSP_COMMUNICATION;
2171 phr->specific_error = err;
2172 } else {
2173 phr->error = err;
2174 }
2175
719f82d3
EB		 2176 pao->dsp_crashed++;
2177
2178 /* just the header of the response is valid */
2179 phr->size = sizeof(struct hpi_response_header);
2180 goto err;
2181 } else
2182 pao->dsp_crashed = 0;
2183
2184 if (phr->error != 0) /* something failed in the DSP */
2185 goto err;
2186
2187 switch (phm->function) {
2188 case HPI_OSTREAM_WRITE:
2189 case HPI_ISTREAM_ANC_WRITE:
2190 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2191 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2192 break;
2193
2194 case HPI_ISTREAM_READ:
2195 case HPI_OSTREAM_ANC_READ:
2196 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2197 phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2198 break;
2199
719f82d3
EB		 2200 }
2201 phr->error = err;
2202
2203err:
2204 hpios_dsplock_unlock(pao);
2205
2206 return;
2207}
Linux kernel - Deliverables
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