projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: azt3328: cosmetics, minor updates
[deliverable/linux.git] / sound / pci / azt3328.c
CommitLineData
1da177e4
LT		 1/*
2 * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
adf5931f 3 * Copyright (C) 2002, 2005 - 2010 by Andreas Mohr <andi AT lisas.de>
1da177e4
LT		 4 *
5 * Framework borrowed from Bart Hartgers's als4000.c.
6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
8 * Other versions are:
9 * PCI168 A(W), sub ID 1800
10 * PCI168 A/AP, sub ID 8000
11 * Please give me feedback in case you try my driver with one of these!!
12 *
dfbf9511
AM		 13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
14 * (XP/Vista do not support this card at all but every Linux distribution
15 * has very good support out of the box;
16 * just to make sure that the right people hit this and get to know that,
17 * despite the high level of Internet ignorance - as usual :-P -
78df617a 18 * about very good support for this card - on Linux!)
dfbf9511 19 *
1da177e4
LT		 20 * GPL LICENSE
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation; either version 2 of the License, or
24 * (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 *
35 * NOTES
36 * Since Aztech does not provide any chipset documentation,
37 * even on repeated request to various addresses,
38 * and the answer that was finally given was negative
39 * (and I was stupid enough to manage to get hold of a PCI168 soundcard
40 * in the first place >:-P}),
41 * I was forced to base this driver on reverse engineering
42 * (3 weeks' worth of evenings filled with driver work).
e2f87260 43 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
1da177e4 44 *
02330fba
AM		 45 * It is quite likely that the AZF3328 chip is the PCI cousin of the
46 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
47 *
1da177e4 48 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
02330fba
AM		 49 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
50 * Fincitec acquired by National Semiconductor in 2002, together with the
51 * Fincitec-related company ARSmikro) has the following features:
1da177e4 52 *
02330fba
AM		 53 * - compatibility & compliance:
54 * - Microsoft PC 97 ("PC 97 Hardware Design Guide",
55 * http://www.microsoft.com/whdc/archive/pcguides.mspx)
56 * - Microsoft PC 98 Baseline Audio
57 * - MPU401 UART
58 * - Sound Blaster Emulation (DOS Box)
1da177e4 59 * - builtin AC97 conformant codec (SNR over 80dB)
13769e3f
AM		 60 * Note that "conformant" != "compliant"!! this chip's mixer register layout
61 * *differs* from the standard AC97 layout:
62 * they chose to not implement the headphone register (which is not a
63 * problem since it's merely optional), yet when doing this, they committed
64 * the grave sin of letting other registers follow immediately instead of
65 * keeping a headphone dummy register, thereby shifting the mixer register
66 * addresses illegally. So far unfortunately it looks like the very flexible
67 * ALSA AC97 support is still not enough to easily compensate for such a
68 * grave layout violation despite all tweaks and quirks mechanisms it offers.
02330fba 69 * - builtin genuine OPL3 - verified to work fine, 20080506
1da177e4 70 * - full duplex 16bit playback/record at independent sampling rate
02330fba
AM		 71 * - MPU401 (+ legacy address support, claimed by one official spec sheet)
72 * FIXME: how to enable legacy addr??
1da177e4 73 * - game port (legacy address support)
e24a121a 74 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
02330fba
AM		 75 * features supported). - See common term "Digital Enhanced Game Port"...
76 * (probably DirectInput 3.0 spec - confirm)
77 * - builtin 3D enhancement (said to be YAMAHA Ymersion)
1da177e4 78 * - built-in General DirectX timer having a 20 bits counter
d91c64c8 79 * with 1us resolution (see below!)
02330fba 80 * - I2S serial output port for external DAC
dfbf9511 81 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
1da177e4
LT		 82 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
83 * - supports hardware volume control
84 * - single chip low cost solution (128 pin QFP)
dfbf9511 85 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
1da177e4 86 * required for Microsoft's logo compliance (FIXME: where?)
02330fba
AM		 87 * At least the Trident 4D Wave DX has one bit somewhere
88 * to enable writes to PCI subsystem VID registers, that should be it.
89 * This might easily be in extended PCI reg space, since PCI168 also has
90 * some custom data starting at 0x80. What kind of config settings
91 * are located in our extended PCI space anyway??
1da177e4 92 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
dfbf9511 93 * [TDA1517P chip]
1da177e4 94 *
d91c64c8
AM		 95 * Note that this driver now is actually *better* than the Windows driver,
96 * since it additionally supports the card's 1MHz DirectX timer - just try
97 * the following snd-seq module parameters etc.:
98 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
99 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
100 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
101 * - "timidity -iAv -B2,8 -Os -EFreverb=0"
102 * - "pmidi -p 128:0 jazz.mid"
103 *
02330fba
AM		 104 * OPL3 hardware playback testing, try something like:
105 * cat /proc/asound/hwdep
106 * and
107 * aconnect -o
108 * Then use
109 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
110 * where x,y is the xx-yy number as given in hwdep.
111 * Then try
112 * pmidi -p a:b jazz.mid
113 * where a:b is the client number plus 0 usually, as given by aconnect above.
114 * Oh, and make sure to unmute the FM mixer control (doh!)
115 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
116 * despite no CPU activity, possibly due to hindering ACPI idling somehow.
117 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
118 * Higher PCM / FM mixer levels seem to conflict (causes crackling),
119 * at least sometimes. Maybe even use with hardware sequencer timer above :)
120 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
121 *
1da177e4
LT		 122 * Certain PCI versions of this card are susceptible to DMA traffic underruns
123 * in some systems (resulting in sound crackling/clicking/popping),
124 * probably because they don't have a DMA FIFO buffer or so.
125 * Overview (PCI ID/PCI subID/PCI rev.):
126 * - no DMA crackling on SiS735: 0x50DC/0x1801/16
127 * - unknown performance: 0x50DC/0x1801/10
d91c64c8
AM		 128 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
129 *
1da177e4
LT		 130 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
131 * supposed to be very fast and supposed to get rid of crackling much
132 * better than a VIA, yet ironically I still get crackling, like many other
133 * people with the same chipset.
134 * Possible remedies:
02330fba
AM		 135 * - use speaker (amplifier) output instead of headphone output
136 * (in case crackling is due to overloaded output clipping)
1da177e4
LT		 137 * - plug card into a different PCI slot, preferrably one that isn't shared
138 * too much (this helps a lot, but not completely!)
139 * - get rid of PCI VGA card, use AGP instead
140 * - upgrade or downgrade BIOS
141 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
142 * Not too helpful.
143 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
02330fba 144 *
1da177e4 145 * BUGS
02330fba 146 * - full-duplex might *still* be problematic, however a recent test was fine
e24a121a
AM		 147 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
148 * if you set PCM output switch to "pre 3D" instead of "post 3D".
149 * If this can't be set, then get a mixer application that Isn't Stupid (tm)
150 * (e.g. kmix, gamix) - unfortunately several are!!
02330fba
AM		 151 * - locking is not entirely clean, especially the audio stream activity
152 * ints --> may be racy
153 * - an _unconnected_ secondary joystick at the gameport will be reported
154 * to be "active" (floating values, not precisely -1) due to the way we need
155 * to read the Digital Enhanced Game Port. Not sure whether it is fixable.
156 *
1da177e4 157 * TODO
dfbf9511
AM		 158 * - use PCI_VDEVICE
159 * - verify driver status on x86_64
160 * - test multi-card driver operation
161 * - (ab)use 1MHz DirectX timer as kernel clocksource
1da177e4 162 * - test MPU401 MIDI playback etc.
02330fba 163 * - add more power micro-management (disable various units of the card
dfbf9511
AM		 164 * as long as they're unused, to improve audio quality and save power).
165 * However this requires more I/O ports which I haven't figured out yet
166 * and which thus might not even exist...
ca54bde3
AM		 167 * The standard suspend/resume functionality could probably make use of
168 * some improvement, too...
1da177e4 169 * - figure out what all unknown port bits are responsible for
13769e3f
AM		 170 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
171 * fully accept our quite incompatible ""AC97"" mixer and thus save some
172 * code (but I'm not too optimistic that doing this is possible at all)
02330fba 173 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
1da177e4
LT		 174 */
175
1da177e4
LT		 176#include <asm/io.h>
177#include <linux/init.h>
178#include <linux/pci.h>
179#include <linux/delay.h>
180#include <linux/slab.h>
181#include <linux/gameport.h>
182#include <linux/moduleparam.h>
910638ae 183#include <linux/dma-mapping.h>
1da177e4
LT		 184#include <sound/core.h>
185#include <sound/control.h>
186#include <sound/pcm.h>
187#include <sound/rawmidi.h>
188#include <sound/mpu401.h>
189#include <sound/opl3.h>
190#include <sound/initval.h>
191#include "azt3328.h"
192
d91c64c8 193MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
1da177e4
LT		 194MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
195MODULE_LICENSE("GPL");
196MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
197
198#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
02330fba 199#define SUPPORT_GAMEPORT 1
1da177e4
LT		 200#endif
201
dfbf9511
AM		 202/* === Debug settings ===
203 Further diagnostic functionality than the settings below
adf5931f 204 does not need to be provided, since one can easily write a POSIX shell script
dfbf9511 205 to dump the card's I/O ports (those listed in lspci -v -v):
adf5931f 206 dump()
dfbf9511
AM		 207 {
208 local descr=$1; local addr=$2; local count=$3
209
210 echo "${descr}: ${count} @ ${addr}:"
adf5931f
AM		 211 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
212 2>/dev/null| hexdump -C
dfbf9511
AM		 213 }
214 and then use something like
215 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
216 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
217 possibly within a "while true; do ... sleep 1; done" loop.
218 Tweaking ports could be done using
219 VALSTRING="`printf "%02x" $value`"
adf5931f
AM		 220 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
221 2>/dev/null
dfbf9511
AM		 222*/
223
1da177e4
LT		 224#define DEBUG_MISC 0
225#define DEBUG_CALLS 0
226#define DEBUG_MIXER 0
78df617a 227#define DEBUG_CODEC 0
d91c64c8 228#define DEBUG_TIMER 0
02330fba 229#define DEBUG_GAME 0
78df617a 230#define DEBUG_PM 0
1da177e4
LT		 231#define MIXER_TESTING 0
232
233#if DEBUG_MISC
78df617a 234#define snd_azf3328_dbgmisc(format, args...) printk(KERN_DEBUG format, ##args)
1da177e4
LT		 235#else
236#define snd_azf3328_dbgmisc(format, args...)
02330fba 237#endif
1da177e4
LT		 238
239#if DEBUG_CALLS
240#define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
78df617a
AM		 241#define snd_azf3328_dbgcallenter() printk(KERN_DEBUG "--> %s\n", __func__)
242#define snd_azf3328_dbgcallleave() printk(KERN_DEBUG "<-- %s\n", __func__)
1da177e4
LT		 243#else
244#define snd_azf3328_dbgcalls(format, args...)
245#define snd_azf3328_dbgcallenter()
246#define snd_azf3328_dbgcallleave()
02330fba 247#endif
1da177e4
LT		 248
249#if DEBUG_MIXER
ee419653 250#define snd_azf3328_dbgmixer(format, args...) printk(KERN_DEBUG format, ##args)
1da177e4
LT		 251#else
252#define snd_azf3328_dbgmixer(format, args...)
02330fba 253#endif
1da177e4 254
78df617a
AM		 255#if DEBUG_CODEC
256#define snd_azf3328_dbgcodec(format, args...) printk(KERN_DEBUG format, ##args)
1da177e4 257#else
78df617a 258#define snd_azf3328_dbgcodec(format, args...)
02330fba 259#endif
1da177e4 260
d91c64c8 261#if DEBUG_MISC
ee419653 262#define snd_azf3328_dbgtimer(format, args...) printk(KERN_DEBUG format, ##args)
1da177e4 263#else
d91c64c8 264#define snd_azf3328_dbgtimer(format, args...)
02330fba
AM		 265#endif
266
267#if DEBUG_GAME
ee419653 268#define snd_azf3328_dbggame(format, args...) printk(KERN_DEBUG format, ##args)
02330fba
AM		 269#else
270#define snd_azf3328_dbggame(format, args...)
271#endif
d91c64c8 272
78df617a
AM		 273#if DEBUG_PM
274#define snd_azf3328_dbgpm(format, args...) printk(KERN_DEBUG format, ##args)
275#else
276#define snd_azf3328_dbgpm(format, args...)
277#endif
278
1da177e4
LT		 279static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
280module_param_array(index, int, NULL, 0444);
281MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
282
283static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
284module_param_array(id, charp, NULL, 0444);
285MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
286
287static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
288module_param_array(enable, bool, NULL, 0444);
289MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
290
d91c64c8
AM		 291static int seqtimer_scaling = 128;
292module_param(seqtimer_scaling, int, 0444);
293MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
1da177e4 294
dfbf9511
AM		 295struct snd_azf3328_codec_data {
296 unsigned long io_base;
02330fba 297 struct snd_pcm_substream *substream;
dfbf9511
AM		 298 bool running;
299 const char *name;
02330fba
AM		 300};
301
dfbf9511 302enum snd_azf3328_codec_type {
adf5931f 303 /* warning: fixed indices (also used for bitmask checks!) */
dfbf9511
AM		 304 AZF_CODEC_PLAYBACK = 0,
305 AZF_CODEC_CAPTURE = 1,
306 AZF_CODEC_I2S_OUT = 2,
02330fba
AM		 307};
308
95de7766 309struct snd_azf3328 {
d91c64c8 310 /* often-used fields towards beginning, then grouped */
02330fba 311
dfbf9511 312 unsigned long ctrl_io; /* usually 0xb000, size 128 */
02330fba
AM		 313 unsigned long game_io; /* usually 0xb400, size 8 */
314 unsigned long mpu_io; /* usually 0xb800, size 4 */
315 unsigned long opl3_io; /* usually 0xbc00, size 8 */
316 unsigned long mixer_io; /* usually 0xc000, size 64 */
1da177e4 317
d91c64c8 318 spinlock_t reg_lock;
1da177e4 319
95de7766 320 struct snd_timer *timer;
02330fba 321
dfbf9511
AM		 322 struct snd_pcm *pcm[3];
323
324 /* playback, recording and I2S out codecs */
325 struct snd_azf3328_codec_data codecs[3];
1da177e4 326
95de7766
TI		 327 struct snd_card *card;
328 struct snd_rawmidi *rmidi;
d91c64c8 329
02330fba 330#ifdef SUPPORT_GAMEPORT
d91c64c8 331 struct gameport *gameport;
dfbf9511 332 u16 axes[4];
d91c64c8 333#endif
1da177e4 334
d91c64c8
AM		 335 struct pci_dev *pci;
336 int irq;
ca54bde3 337
627d3e7a
AM		 338 /* register 0x6a is write-only, thus need to remember setting.
339 * If we need to add more registers here, then we might try to fold this
340 * into some transparent combined shadow register handling with
341 * CONFIG_PM register storage below, but that's slightly difficult. */
dfbf9511 342 u16 shadow_reg_ctrl_6AH;
627d3e7a 343
ca54bde3
AM		 344#ifdef CONFIG_PM
345 /* register value containers for power management
78df617a
AM		 346 * Note: not always full I/O range preserved (similar to Win driver!) */
347 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
348 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
349 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
350 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
351 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
ca54bde3 352#endif
95de7766 353};
d91c64c8 354
cebe41d4 355static DEFINE_PCI_DEVICE_TABLE(snd_azf3328_ids) = {
1da177e4
LT		 356 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
357 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
358 { 0, }
359};
360
361MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
362
02330fba
AM		 363
364static int
dfbf9511 365snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
02330fba 366{
adf5931f
AM		 367 /* Well, strictly spoken, the inb/outb sequence isn't atomic
368 and would need locking. However we currently don't care
369 since it potentially complicates matters. */
02330fba
AM		 370 u8 prev = inb(reg), new;
371
372 new = (do_set) ? (prev|mask) : (prev & ~mask);
373 /* we need to always write the new value no matter whether it differs
374 * or not, since some register bits don't indicate their setting */
375 outb(new, reg);
376 if (new != prev)
377 return 1;
378
379 return 0;
380}
381
d91c64c8 382static inline void
dfbf9511
AM		 383snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
384 unsigned reg,
385 u8 value
386)
d91c64c8 387{
dfbf9511 388 outb(value, codec->io_base + reg);
d91c64c8
AM		 389}
390
391static inline u8
dfbf9511 392snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
d91c64c8 393{
dfbf9511 394 return inb(codec->io_base + reg);
d91c64c8
AM		 395}
396
397static inline void
dfbf9511
AM		 398snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
399 unsigned reg,
400 u16 value
401)
d91c64c8 402{
dfbf9511 403 outw(value, codec->io_base + reg);
d91c64c8
AM		 404}
405
406static inline u16
dfbf9511 407snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
02330fba 408{
dfbf9511 409 return inw(codec->io_base + reg);
02330fba
AM		 410}
411
412static inline void
dfbf9511
AM		 413snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
414 unsigned reg,
415 u32 value
416)
02330fba 417{
dfbf9511 418 outl(value, codec->io_base + reg);
02330fba
AM		 419}
420
421static inline u32
dfbf9511
AM		 422snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
423{
424 return inl(codec->io_base + reg);
425}
426
427static inline void
428snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
d91c64c8 429{
dfbf9511
AM		 430 outb(value, chip->ctrl_io + reg);
431}
432
433static inline u8
434snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
435{
436 return inb(chip->ctrl_io + reg);
437}
438
439static inline void
440snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
441{
442 outw(value, chip->ctrl_io + reg);
443}
444
445static inline void
446snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
447{
448 outl(value, chip->ctrl_io + reg);
d91c64c8
AM		 449}
450
451static inline void
02330fba 452snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
d91c64c8 453{
02330fba 454 outb(value, chip->game_io + reg);
d91c64c8
AM		 455}
456
457static inline void
02330fba 458snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
1da177e4 459{
02330fba 460 outw(value, chip->game_io + reg);
1da177e4
LT		 461}
462
d91c64c8 463static inline u8
02330fba
AM		 464snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
465{
466 return inb(chip->game_io + reg);
467}
468
469static inline u16
470snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
1da177e4 471{
02330fba 472 return inw(chip->game_io + reg);
1da177e4
LT		 473}
474
d91c64c8 475static inline void
02330fba 476snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
1da177e4 477{
02330fba 478 outw(value, chip->mixer_io + reg);
d91c64c8
AM		 479}
480
481static inline u16
02330fba 482snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
d91c64c8 483{
02330fba 484 return inw(chip->mixer_io + reg);
1da177e4
LT		 485}
486
02330fba
AM		 487#define AZF_MUTE_BIT 0x80
488
dfbf9511 489static bool
02330fba 490snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip,
dfbf9511 491 unsigned reg, bool do_mute
02330fba 492)
1da177e4 493{
02330fba 494 unsigned long portbase = chip->mixer_io + reg + 1;
dfbf9511 495 bool updated;
1da177e4
LT		 496
497 /* the mute bit is on the *second* (i.e. right) register of a
498 * left/right channel setting */
02330fba
AM		 499 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
500
501 /* indicate whether it was muted before */
502 return (do_mute) ? !updated : updated;
1da177e4
LT		 503}
504
d91c64c8 505static void
02330fba
AM		 506snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
507 unsigned reg,
508 unsigned char dst_vol_left,
509 unsigned char dst_vol_right,
510 int chan_sel, int delay
511)
1da177e4 512{
02330fba 513 unsigned long portbase = chip->mixer_io + reg;
1da177e4 514 unsigned char curr_vol_left = 0, curr_vol_right = 0;
02330fba
AM		 515 int left_change = 0, right_change = 0;
516
1da177e4 517 snd_azf3328_dbgcallenter();
02330fba
AM		 518
519 if (chan_sel & SET_CHAN_LEFT) {
d91c64c8 520 curr_vol_left = inb(portbase + 1);
02330fba
AM		 521
522 /* take care of muting flag contained in left channel */
523 if (curr_vol_left & AZF_MUTE_BIT)
524 dst_vol_left |= AZF_MUTE_BIT;
525 else
526 dst_vol_left &= ~AZF_MUTE_BIT;
527
528 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
529 }
530
531 if (chan_sel & SET_CHAN_RIGHT) {
d91c64c8 532 curr_vol_right = inb(portbase + 0);
02330fba
AM		 533
534 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
535 }
1da177e4 536
e2f87260 537 do {
02330fba
AM		 538 if (left_change) {
539 if (curr_vol_left != dst_vol_left) {
540 curr_vol_left += left_change;
541 outb(curr_vol_left, portbase + 1);
542 } else
543 left_change = 0;
1da177e4 544 }
02330fba
AM		 545 if (right_change) {
546 if (curr_vol_right != dst_vol_right) {
547 curr_vol_right += right_change;
548
1da177e4
LT		 549 /* during volume change, the right channel is crackling
550 * somewhat more than the left channel, unfortunately.
551 * This seems to be a hardware issue. */
02330fba
AM		 552 outb(curr_vol_right, portbase + 0);
553 } else
554 right_change = 0;
1da177e4
LT		 555 }
556 if (delay)
557 mdelay(delay);
02330fba 558 } while ((left_change) || (right_change));
1da177e4
LT		 559 snd_azf3328_dbgcallleave();
560}
561
562/*
563 * general mixer element
564 */
95de7766 565struct azf3328_mixer_reg {
02330fba 566 unsigned reg;
1da177e4
LT		 567 unsigned int lchan_shift, rchan_shift;
568 unsigned int mask;
569 unsigned int invert: 1;
570 unsigned int stereo: 1;
571 unsigned int enum_c: 4;
95de7766 572};
1da177e4
LT		 573
574#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
d91c64c8
AM		 575 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
576 (mask << 16) | \
577 (invert << 24) | \
578 (stereo << 25) | \
579 (enum_c << 26))
1da177e4 580
95de7766 581static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
1da177e4
LT		 582{
583 r->reg = val & 0xff;
584 r->lchan_shift = (val >> 8) & 0x0f;
585 r->rchan_shift = (val >> 12) & 0x0f;
586 r->mask = (val >> 16) & 0xff;
587 r->invert = (val >> 24) & 1;
588 r->stereo = (val >> 25) & 1;
589 r->enum_c = (val >> 26) & 0x0f;
590}
591
592/*
593 * mixer switches/volumes
594 */
595
596#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
597{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
598 .info = snd_azf3328_info_mixer, \
599 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
600 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
601}
602
603#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
604{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
605 .info = snd_azf3328_info_mixer, \
606 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
607 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
608}
609
610#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
611{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
612 .info = snd_azf3328_info_mixer, \
613 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
614 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
615}
616
617#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
618{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
619 .info = snd_azf3328_info_mixer, \
620 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
621 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
622}
623
624#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
625{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
626 .info = snd_azf3328_info_mixer_enum, \
627 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
628 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
629}
630
d91c64c8 631static int
95de7766
TI		 632snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
633 struct snd_ctl_elem_info *uinfo)
1da177e4 634{
95de7766 635 struct azf3328_mixer_reg reg;
1da177e4
LT		 636
637 snd_azf3328_dbgcallenter();
638 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
d91c64c8
AM		 639 uinfo->type = reg.mask == 1 ?
640 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1da177e4
LT		 641 uinfo->count = reg.stereo + 1;
642 uinfo->value.integer.min = 0;
643 uinfo->value.integer.max = reg.mask;
644 snd_azf3328_dbgcallleave();
645 return 0;
646}
647
d91c64c8 648static int
95de7766
TI		 649snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
650 struct snd_ctl_elem_value *ucontrol)
1da177e4 651{
95de7766
TI		 652 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
653 struct azf3328_mixer_reg reg;
dfbf9511 654 u16 oreg, val;
1da177e4
LT		 655
656 snd_azf3328_dbgcallenter();
657 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
658
d91c64c8 659 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1da177e4
LT		 660 val = (oreg >> reg.lchan_shift) & reg.mask;
661 if (reg.invert)
662 val = reg.mask - val;
663 ucontrol->value.integer.value[0] = val;
664 if (reg.stereo) {
665 val = (oreg >> reg.rchan_shift) & reg.mask;
666 if (reg.invert)
667 val = reg.mask - val;
668 ucontrol->value.integer.value[1] = val;
669 }
d91c64c8
AM		 670 snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
671 "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
672 reg.reg, oreg,
673 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
674 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
1da177e4
LT		 675 snd_azf3328_dbgcallleave();
676 return 0;
677}
678
d91c64c8 679static int
95de7766
TI		 680snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
681 struct snd_ctl_elem_value *ucontrol)
1da177e4 682{
95de7766
TI		 683 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
684 struct azf3328_mixer_reg reg;
dfbf9511 685 u16 oreg, nreg, val;
1da177e4
LT		 686
687 snd_azf3328_dbgcallenter();
688 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
d91c64c8 689 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1da177e4
LT		 690 val = ucontrol->value.integer.value[0] & reg.mask;
691 if (reg.invert)
692 val = reg.mask - val;
693 nreg = oreg & ~(reg.mask << reg.lchan_shift);
694 nreg |= (val << reg.lchan_shift);
695 if (reg.stereo) {
696 val = ucontrol->value.integer.value[1] & reg.mask;
697 if (reg.invert)
698 val = reg.mask - val;
699 nreg &= ~(reg.mask << reg.rchan_shift);
700 nreg |= (val << reg.rchan_shift);
701 }
702 if (reg.mask >= 0x07) /* it's a volume control, so better take care */
d91c64c8
AM		 703 snd_azf3328_mixer_write_volume_gradually(
704 chip, reg.reg, nreg >> 8, nreg & 0xff,
705 /* just set both channels, doesn't matter */
706 SET_CHAN_LEFT|SET_CHAN_RIGHT,
707 0);
1da177e4 708 else
d91c64c8 709 snd_azf3328_mixer_outw(chip, reg.reg, nreg);
1da177e4 710
d91c64c8
AM		 711 snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
712 "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
713 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
714 oreg, reg.lchan_shift, reg.rchan_shift,
715 nreg, snd_azf3328_mixer_inw(chip, reg.reg));
1da177e4
LT		 716 snd_azf3328_dbgcallleave();
717 return (nreg != oreg);
718}
719
d91c64c8 720static int
95de7766
TI		 721snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
722 struct snd_ctl_elem_info *uinfo)
1da177e4 723{
d91c64c8 724 static const char * const texts1[] = {
13769e3f 725 "Mic1", "Mic2"
d91c64c8
AM		 726 };
727 static const char * const texts2[] = {
13769e3f 728 "Mix", "Mic"
d91c64c8
AM		 729 };
730 static const char * const texts3[] = {
02330fba 731 "Mic", "CD", "Video", "Aux",
d91c64c8 732 "Line", "Mix", "Mix Mono", "Phone"
1da177e4 733 };
13769e3f
AM		 734 static const char * const texts4[] = {
735 "pre 3D", "post 3D"
736 };
95de7766 737 struct azf3328_mixer_reg reg;
627d3e7a 738 const char * const *p = NULL;
1da177e4
LT		 739
740 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
741 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
742 uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
743 uinfo->value.enumerated.items = reg.enum_c;
744 if (uinfo->value.enumerated.item > reg.enum_c - 1U)
745 uinfo->value.enumerated.item = reg.enum_c - 1U;
e2f87260 746 if (reg.reg == IDX_MIXER_ADVCTL2) {
13769e3f
AM		 747 switch(reg.lchan_shift) {
748 case 8: /* modem out sel */
627d3e7a 749 p = texts1;
13769e3f
AM		 750 break;
751 case 9: /* mono sel source */
627d3e7a 752 p = texts2;
13769e3f
AM		 753 break;
754 case 15: /* PCM Out Path */
627d3e7a 755 p = texts4;
13769e3f
AM		 756 break;
757 }
e2f87260 758 } else
02330fba 759 if (reg.reg == IDX_MIXER_REC_SELECT)
627d3e7a 760 p = texts3;
02330fba 761
627d3e7a 762 strcpy(uinfo->value.enumerated.name, p[uinfo->value.enumerated.item]);
1da177e4
LT		 763 return 0;
764}
765
d91c64c8 766static int
95de7766
TI		 767snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
768 struct snd_ctl_elem_value *ucontrol)
1da177e4 769{
95de7766
TI		 770 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
771 struct azf3328_mixer_reg reg;
1da177e4 772 unsigned short val;
02330fba 773
1da177e4 774 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
d91c64c8 775 val = snd_azf3328_mixer_inw(chip, reg.reg);
e2f87260 776 if (reg.reg == IDX_MIXER_REC_SELECT) {
1da177e4
LT		 777 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
778 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
e2f87260 779 } else
1da177e4 780 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
d91c64c8
AM		 781
782 snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
783 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
784 reg.lchan_shift, reg.enum_c);
1da177e4
LT		 785 return 0;
786}
787
d91c64c8 788static int
95de7766
TI		 789snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
790 struct snd_ctl_elem_value *ucontrol)
1da177e4 791{
95de7766
TI		 792 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
793 struct azf3328_mixer_reg reg;
dfbf9511 794 u16 oreg, nreg, val;
02330fba 795
1da177e4 796 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
d91c64c8 797 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1da177e4 798 val = oreg;
e2f87260 799 if (reg.reg == IDX_MIXER_REC_SELECT) {
1da177e4
LT		 800 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
801 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
802 return -EINVAL;
803 val = (ucontrol->value.enumerated.item[0] << 8) |
804 (ucontrol->value.enumerated.item[1] << 0);
e2f87260 805 } else {
1da177e4
LT		 806 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
807 return -EINVAL;
808 val &= ~((reg.enum_c - 1) << reg.lchan_shift);
809 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
810 }
d91c64c8 811 snd_azf3328_mixer_outw(chip, reg.reg, val);
1da177e4
LT		 812 nreg = val;
813
814 snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
815 return (nreg != oreg);
816}
817
1b60f6b0 818static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
1da177e4
LT		 819 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
820 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
627d3e7a
AM		 821 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
822 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
823 IDX_MIXER_WAVEOUT, 0x1f, 1),
824 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
825 IDX_MIXER_ADVCTL2, 7, 1),
1da177e4
LT		 826 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
827 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
828 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
829 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
830 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
831 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
832 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
833 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
834 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
835 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
836 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
837 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
d355c82a
JK		 838 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
839 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
1da177e4
LT		 840 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
841 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
842 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
843 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
844 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
845 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
846 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
847 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
13769e3f
AM		 848 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
849 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
e24a121a 850 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
1da177e4
LT		 851 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
852 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
d91c64c8 853 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
13769e3f
AM		 854 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
855 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
1da177e4
LT		 856#if MIXER_TESTING
857 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
858 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
859 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
860 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
861 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
862 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
863 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
864 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
865 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
866 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
867 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
868 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
869 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
870 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
871 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
872 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
873#endif
874};
875
1b60f6b0 876static u16 __devinitdata snd_azf3328_init_values[][2] = {
1da177e4
LT		 877 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
878 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
879 { IDX_MIXER_BASSTREBLE, 0x0000 },
880 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
881 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
882 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
883 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
884 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
885 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
886 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
887 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
888 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
889 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
890};
891
d91c64c8 892static int __devinit
95de7766 893snd_azf3328_mixer_new(struct snd_azf3328 *chip)
1da177e4 894{
95de7766
TI		 895 struct snd_card *card;
896 const struct snd_kcontrol_new *sw;
1da177e4
LT		 897 unsigned int idx;
898 int err;
899
900 snd_azf3328_dbgcallenter();
da3cec35
TI		 901 if (snd_BUG_ON(!chip || !chip->card))
902 return -EINVAL;
1da177e4
LT		 903
904 card = chip->card;
905
906 /* mixer reset */
d91c64c8 907 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
1da177e4
LT		 908
909 /* mute and zero volume channels */
02330fba 910 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
d91c64c8
AM		 911 snd_azf3328_mixer_outw(chip,
912 snd_azf3328_init_values[idx][0],
913 snd_azf3328_init_values[idx][1]);
1da177e4 914 }
02330fba 915
1da177e4
LT		 916 /* add mixer controls */
917 sw = snd_azf3328_mixer_controls;
02330fba
AM		 918 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
919 ++idx, ++sw) {
1da177e4
LT		 920 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
921 return err;
922 }
923 snd_component_add(card, "AZF3328 mixer");
924 strcpy(card->mixername, "AZF3328 mixer");
925
926 snd_azf3328_dbgcallleave();
927 return 0;
928}
929
d91c64c8 930static int
95de7766
TI		 931snd_azf3328_hw_params(struct snd_pcm_substream *substream,
932 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 933{
934 int res;
935 snd_azf3328_dbgcallenter();
936 res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
937 snd_azf3328_dbgcallleave();
938 return res;
939}
940
d91c64c8 941static int
95de7766 942snd_azf3328_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 943{
944 snd_azf3328_dbgcallenter();
945 snd_pcm_lib_free_pages(substream);
946 snd_azf3328_dbgcallleave();
947 return 0;
948}
949
d91c64c8 950static void
02330fba 951snd_azf3328_codec_setfmt(struct snd_azf3328 *chip,
dfbf9511 952 enum snd_azf3328_codec_type codec_type,
627d3e7a 953 enum azf_freq_t bitrate,
1da177e4
LT		 954 unsigned int format_width,
955 unsigned int channels
956)
957{
1da177e4 958 unsigned long flags;
dfbf9511
AM		 959 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
960 u16 val = 0xff00;
1da177e4
LT		 961
962 snd_azf3328_dbgcallenter();
963 switch (bitrate) {
02330fba
AM		 964 case AZF_FREQ_4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
965 case AZF_FREQ_4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
966 case AZF_FREQ_5512:
967 /* the AZF3328 names it "5510" for some strange reason */
968 val |= SOUNDFORMAT_FREQ_5510; break;
969 case AZF_FREQ_6620: val |= SOUNDFORMAT_FREQ_6620; break;
970 case AZF_FREQ_8000: val |= SOUNDFORMAT_FREQ_8000; break;
971 case AZF_FREQ_9600: val |= SOUNDFORMAT_FREQ_9600; break;
972 case AZF_FREQ_11025: val |= SOUNDFORMAT_FREQ_11025; break;
973 case AZF_FREQ_13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
974 case AZF_FREQ_16000: val |= SOUNDFORMAT_FREQ_16000; break;
975 case AZF_FREQ_22050: val |= SOUNDFORMAT_FREQ_22050; break;
976 case AZF_FREQ_32000: val |= SOUNDFORMAT_FREQ_32000; break;
1da177e4 977 default:
99b359ba 978 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
02330fba
AM		 979 /* fall-through */
980 case AZF_FREQ_44100: val |= SOUNDFORMAT_FREQ_44100; break;
981 case AZF_FREQ_48000: val |= SOUNDFORMAT_FREQ_48000; break;
982 case AZF_FREQ_66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
1da177e4 983 }
d91c64c8
AM		 984 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
985 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
986 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
987 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
1da177e4
LT		 988 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
989 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
990 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
991 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
992 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
d91c64c8 993
1da177e4
LT		 994 if (channels == 2)
995 val |= SOUNDFORMAT_FLAG_2CHANNELS;
996
997 if (format_width == 16)
998 val |= SOUNDFORMAT_FLAG_16BIT;
999
1000 spin_lock_irqsave(&chip->reg_lock, flags);
02330fba 1001
1da177e4 1002 /* set bitrate/format */
dfbf9511 1003 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
02330fba 1004
1da177e4
LT		 1005 /* changing the bitrate/format settings switches off the
1006 * audio output with an annoying click in case of 8/16bit format change
1007 * (maybe shutting down DAC/ADC?), thus immediately
1008 * do some tweaking to reenable it and get rid of the clicking
1009 * (FIXME: yes, it works, but what exactly am I doing here?? :)
1010 * FIXME: does this have some side effects for full-duplex
1011 * or other dramatic side effects? */
adf5931f
AM		 1012 /* do it for non-capture codecs only */
1013 if (codec_type == AZF_CODEC_PLAYBACK)
dfbf9511
AM		 1014 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1015 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
1016 DMA_RUN_SOMETHING1 |
1017 DMA_RUN_SOMETHING2 |
d91c64c8
AM		 1018 SOMETHING_ALMOST_ALWAYS_SET |
1019 DMA_EPILOGUE_SOMETHING |
1020 DMA_SOMETHING_ELSE
1021 );
1da177e4
LT		 1022
1023 spin_unlock_irqrestore(&chip->reg_lock, flags);
1024 snd_azf3328_dbgcallleave();
1025}
1026
02330fba
AM		 1027static inline void
1028snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328 *chip,
dfbf9511 1029 enum snd_azf3328_codec_type codec_type
02330fba
AM		 1030)
1031{
1032 /* choose lowest frequency for low power consumption.
1033 * While this will cause louder noise due to rather coarse frequency,
1034 * it should never matter since output should always
1035 * get disabled properly when idle anyway. */
dfbf9511 1036 snd_azf3328_codec_setfmt(chip, codec_type, AZF_FREQ_4000, 8, 1);
02330fba
AM		 1037}
1038
627d3e7a 1039static void
dfbf9511 1040snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
627d3e7a 1041 unsigned bitmask,
dfbf9511 1042 bool enable
627d3e7a
AM		 1043)
1044{
78df617a
AM		 1045 bool do_mask = !enable;
1046 if (do_mask)
dfbf9511 1047 chip->shadow_reg_ctrl_6AH |= bitmask;
78df617a
AM		 1048 else
1049 chip->shadow_reg_ctrl_6AH &= ~bitmask;
1050 snd_azf3328_dbgcodec("6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
1051 bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
dfbf9511 1052 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
627d3e7a
AM		 1053}
1054
02330fba 1055static inline void
dfbf9511 1056snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
02330fba 1057{
78df617a 1058 snd_azf3328_dbgcodec("codec_enable %d\n", enable);
02330fba
AM		 1059 /* no idea what exactly is being done here, but I strongly assume it's
1060 * PM related */
dfbf9511 1061 snd_azf3328_ctrl_reg_6AH_update(
627d3e7a 1062 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
02330fba
AM		 1063 );
1064}
1065
1066static void
dfbf9511
AM		 1067snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1068 enum snd_azf3328_codec_type codec_type,
1069 bool enable
02330fba
AM		 1070)
1071{
dfbf9511
AM		 1072 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1073 bool need_change = (codec->running != enable);
02330fba 1074
78df617a 1075 snd_azf3328_dbgcodec(
dfbf9511
AM		 1076 "codec_activity: %s codec, enable %d, need_change %d\n",
1077 codec->name, enable, need_change
02330fba
AM		 1078 );
1079 if (need_change) {
dfbf9511
AM		 1080 static const struct {
1081 enum snd_azf3328_codec_type other1;
1082 enum snd_azf3328_codec_type other2;
1083 } peer_codecs[3] =
1084 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
1085 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
1086 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
1087 bool call_function;
1088
1089 if (enable)
1090 /* if enable codec, call enable_codecs func
1091 to enable codec supply... */
1092 call_function = 1;
1093 else {
1094 /* ...otherwise call enable_codecs func
1095 (which globally shuts down operation of codecs)
1096 only in case the other codecs are currently
1097 not active either! */
78df617a
AM		 1098 call_function =
1099 ((!chip->codecs[peer_codecs[codec_type].other1]
1100 .running)
1101 && (!chip->codecs[peer_codecs[codec_type].other2]
1102 .running));
dfbf9511
AM		 1103 }
1104 if (call_function)
1105 snd_azf3328_ctrl_enable_codecs(chip, enable);
02330fba
AM		 1106
1107 /* ...and adjust clock, too
1108 * (reduce noise and power consumption) */
1109 if (!enable)
1110 snd_azf3328_codec_setfmt_lowpower(
1111 chip,
dfbf9511 1112 codec_type
02330fba 1113 );
78df617a 1114 codec->running = enable;
02330fba 1115 }
02330fba
AM		 1116}
1117
d91c64c8 1118static void
dfbf9511
AM		 1119snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
1120 enum snd_azf3328_codec_type codec_type,
1121 unsigned long addr,
1122 unsigned int count,
1123 unsigned int size
02330fba 1124)
1da177e4 1125{
dfbf9511 1126 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1da177e4 1127 snd_azf3328_dbgcallenter();
dfbf9511
AM		 1128 if (!codec->running) {
1129 /* AZF3328 uses a two buffer pointer DMA transfer approach */
02330fba 1130
78df617a 1131 unsigned long flags, addr_area2;
02330fba
AM		 1132
1133 /* width 32bit (prevent overflow): */
78df617a 1134 u32 count_areas, lengths;
d91c64c8 1135
d91c64c8
AM		 1136 count_areas = size/2;
1137 addr_area2 = addr+count_areas;
78df617a
AM		 1138 snd_azf3328_dbgcodec("setdma: buffers %08lx[%u] / %08lx[%u]\n",
1139 addr, count_areas, addr_area2, count_areas);
d91c64c8 1140
7974150c
AM		 1141 count_areas--; /* max. index */
1142
d91c64c8 1143 /* build combined I/O buffer length word */
dfbf9511 1144 lengths = (count_areas << 16) | (count_areas);
1da177e4 1145 spin_lock_irqsave(&chip->reg_lock, flags);
dfbf9511
AM		 1146 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_1, addr);
1147 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_2,
1148 addr_area2);
1149 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_LENGTHS,
1150 lengths);
1da177e4
LT		 1151 spin_unlock_irqrestore(&chip->reg_lock, flags);
1152 }
1153 snd_azf3328_dbgcallleave();
1154}
1155
d91c64c8 1156static int
dfbf9511 1157snd_azf3328_codec_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1158{
1159#if 0
95de7766
TI		 1160 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1161 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1162 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1163 unsigned int count = snd_pcm_lib_period_bytes(substream);
1164#endif
1165
1166 snd_azf3328_dbgcallenter();
1167#if 0
dfbf9511 1168 snd_azf3328_codec_setfmt(chip, AZF_CODEC_...,
d91c64c8
AM		 1169 runtime->rate,
1170 snd_pcm_format_width(runtime->format),
1171 runtime->channels);
dfbf9511
AM		 1172 snd_azf3328_codec_setdmaa(chip, AZF_CODEC_...,
1173 runtime->dma_addr, count, size);
1da177e4
LT		 1174#endif
1175 snd_azf3328_dbgcallleave();
1176 return 0;
1177}
1178
d91c64c8 1179static int
dfbf9511
AM		 1180snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
1181 struct snd_pcm_substream *substream, int cmd)
1da177e4 1182{
95de7766 1183 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
dfbf9511 1184 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
95de7766 1185 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1186 int result = 0;
dfbf9511
AM		 1187 u16 flags1;
1188 bool previously_muted = 0;
1189 bool is_playback_codec = (AZF_CODEC_PLAYBACK == codec_type);
1da177e4 1190
dfbf9511 1191 snd_azf3328_dbgcalls("snd_azf3328_codec_trigger cmd %d\n", cmd);
d91c64c8 1192
1da177e4
LT		 1193 switch (cmd) {
1194 case SNDRV_PCM_TRIGGER_START:
78df617a 1195 snd_azf3328_dbgcodec("START %s\n", codec->name);
dfbf9511
AM		 1196
1197 if (is_playback_codec) {
1198 /* mute WaveOut (avoid clicking during setup) */
1199 previously_muted =
1200 snd_azf3328_mixer_set_mute(
1201 chip, IDX_MIXER_WAVEOUT, 1
1202 );
1203 }
1da177e4 1204
dfbf9511 1205 snd_azf3328_codec_setfmt(chip, codec_type,
d91c64c8
AM		 1206 runtime->rate,
1207 snd_pcm_format_width(runtime->format),
1208 runtime->channels);
1da177e4
LT		 1209
1210 spin_lock(&chip->reg_lock);
02330fba 1211 /* first, remember current value: */
dfbf9511 1212 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
02330fba 1213
dfbf9511
AM		 1214 /* stop transfer */
1215 flags1 &= ~DMA_RESUME;
1216 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
02330fba 1217
1da177e4 1218 /* FIXME: clear interrupts or what??? */
dfbf9511 1219 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
1da177e4
LT		 1220 spin_unlock(&chip->reg_lock);
1221
dfbf9511 1222 snd_azf3328_codec_setdmaa(chip, codec_type, runtime->dma_addr,
d91c64c8 1223 snd_pcm_lib_period_bytes(substream),
dfbf9511
AM		 1224 snd_pcm_lib_buffer_bytes(substream)
1225 );
1da177e4
LT		 1226
1227 spin_lock(&chip->reg_lock);
1228#ifdef WIN9X
1229 /* FIXME: enable playback/recording??? */
dfbf9511
AM		 1230 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
1231 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1da177e4 1232
dfbf9511 1233 /* start transfer again */
1da177e4 1234 /* FIXME: what is this value (0x0010)??? */
dfbf9511
AM		 1235 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1236 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1da177e4 1237#else /* NT4 */
dfbf9511 1238 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
d91c64c8 1239 0x0000);
dfbf9511
AM		 1240 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1241 DMA_RUN_SOMETHING1);
1242 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1243 DMA_RUN_SOMETHING1 |
1244 DMA_RUN_SOMETHING2);
1245 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
d91c64c8
AM		 1246 DMA_RESUME |
1247 SOMETHING_ALMOST_ALWAYS_SET |
1248 DMA_EPILOGUE_SOMETHING |
1249 DMA_SOMETHING_ELSE);
1da177e4
LT		 1250#endif
1251 spin_unlock(&chip->reg_lock);
dfbf9511
AM		 1252 snd_azf3328_ctrl_codec_activity(chip, codec_type, 1);
1253
1254 if (is_playback_codec) {
1255 /* now unmute WaveOut */
1256 if (!previously_muted)
1257 snd_azf3328_mixer_set_mute(
1258 chip, IDX_MIXER_WAVEOUT, 0
1259 );
1260 }
1da177e4 1261
78df617a 1262 snd_azf3328_dbgcodec("STARTED %s\n", codec->name);
1da177e4 1263 break;
ca54bde3 1264 case SNDRV_PCM_TRIGGER_RESUME:
78df617a 1265 snd_azf3328_dbgcodec("RESUME %s\n", codec->name);
dfbf9511 1266 /* resume codec if we were active */
02330fba 1267 spin_lock(&chip->reg_lock);
dfbf9511
AM		 1268 if (codec->running)
1269 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1270 snd_azf3328_codec_inw(
1271 codec, IDX_IO_CODEC_DMA_FLAGS
1272 ) | DMA_RESUME
1273 );
02330fba 1274 spin_unlock(&chip->reg_lock);
ca54bde3 1275 break;
d91c64c8 1276 case SNDRV_PCM_TRIGGER_STOP:
78df617a 1277 snd_azf3328_dbgcodec("STOP %s\n", codec->name);
dfbf9511
AM		 1278
1279 if (is_playback_codec) {
1280 /* mute WaveOut (avoid clicking during setup) */
1281 previously_muted =
1282 snd_azf3328_mixer_set_mute(
1283 chip, IDX_MIXER_WAVEOUT, 1
1284 );
1285 }
1da177e4
LT		 1286
1287 spin_lock(&chip->reg_lock);
02330fba 1288 /* first, remember current value: */
dfbf9511 1289 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1da177e4 1290
dfbf9511
AM		 1291 /* stop transfer */
1292 flags1 &= ~DMA_RESUME;
1293 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1da177e4 1294
d91c64c8
AM		 1295 /* hmm, is this really required? we're resetting the same bit
1296 * immediately thereafter... */
dfbf9511
AM		 1297 flags1 |= DMA_RUN_SOMETHING1;
1298 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1da177e4 1299
dfbf9511
AM		 1300 flags1 &= ~DMA_RUN_SOMETHING1;
1301 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1da177e4 1302 spin_unlock(&chip->reg_lock);
dfbf9511
AM		 1303 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
1304
1305 if (is_playback_codec) {
1306 /* now unmute WaveOut */
1307 if (!previously_muted)
1308 snd_azf3328_mixer_set_mute(
1309 chip, IDX_MIXER_WAVEOUT, 0
1310 );
1311 }
02330fba 1312
78df617a 1313 snd_azf3328_dbgcodec("STOPPED %s\n", codec->name);
1da177e4 1314 break;
ca54bde3 1315 case SNDRV_PCM_TRIGGER_SUSPEND:
78df617a 1316 snd_azf3328_dbgcodec("SUSPEND %s\n", codec->name);
dfbf9511
AM		 1317 /* make sure codec is stopped */
1318 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1319 snd_azf3328_codec_inw(
1320 codec, IDX_IO_CODEC_DMA_FLAGS
1321 ) & ~DMA_RESUME
1322 );
ca54bde3 1323 break;
1da177e4 1324 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
99b359ba 1325 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1da177e4
LT		 1326 break;
1327 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
99b359ba 1328 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1da177e4
LT		 1329 break;
1330 default:
78df617a 1331 snd_printk(KERN_ERR "FIXME: unknown trigger mode!\n");
1da177e4
LT		 1332 return -EINVAL;
1333 }
02330fba 1334
1da177e4
LT		 1335 snd_azf3328_dbgcallleave();
1336 return result;
1337}
1338
d91c64c8 1339static int
dfbf9511 1340snd_azf3328_codec_playback_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 1341{
dfbf9511
AM		 1342 return snd_azf3328_codec_trigger(AZF_CODEC_PLAYBACK, substream, cmd);
1343}
02330fba 1344
dfbf9511
AM		 1345static int
1346snd_azf3328_codec_capture_trigger(struct snd_pcm_substream *substream, int cmd)
1347{
1348 return snd_azf3328_codec_trigger(AZF_CODEC_CAPTURE, substream, cmd);
1349}
02330fba 1350
dfbf9511
AM		 1351static int
1352snd_azf3328_codec_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd)
1353{
1354 return snd_azf3328_codec_trigger(AZF_CODEC_I2S_OUT, substream, cmd);
1da177e4
LT		 1355}
1356
d91c64c8 1357static snd_pcm_uframes_t
dfbf9511
AM		 1358snd_azf3328_codec_pointer(struct snd_pcm_substream *substream,
1359 enum snd_azf3328_codec_type codec_type
1360)
1da177e4 1361{
dfbf9511
AM		 1362 const struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1363 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
d91c64c8 1364 unsigned long bufptr, result;
1da177e4
LT		 1365 snd_pcm_uframes_t frmres;
1366
1367#ifdef QUERY_HARDWARE
dfbf9511 1368 bufptr = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
1da177e4
LT		 1369#else
1370 bufptr = substream->runtime->dma_addr;
1371#endif
dfbf9511 1372 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
1da177e4 1373
d91c64c8
AM		 1374 /* calculate offset */
1375 result -= bufptr;
1376 frmres = bytes_to_frames( substream->runtime, result);
adf5931f
AM		 1377 snd_azf3328_dbgcodec("%08li %s @ 0x%8lx, frames %8ld\n",
1378 jiffies, codec->name, result, frmres);
1da177e4
LT		 1379 return frmres;
1380}
1381
d91c64c8 1382static snd_pcm_uframes_t
dfbf9511 1383snd_azf3328_codec_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1384{
dfbf9511
AM		 1385 return snd_azf3328_codec_pointer(substream, AZF_CODEC_PLAYBACK);
1386}
1da177e4 1387
dfbf9511
AM		 1388static snd_pcm_uframes_t
1389snd_azf3328_codec_capture_pointer(struct snd_pcm_substream *substream)
1390{
1391 return snd_azf3328_codec_pointer(substream, AZF_CODEC_CAPTURE);
1392}
1da177e4 1393
dfbf9511
AM		 1394static snd_pcm_uframes_t
1395snd_azf3328_codec_i2s_out_pointer(struct snd_pcm_substream *substream)
1396{
1397 return snd_azf3328_codec_pointer(substream, AZF_CODEC_I2S_OUT);
1da177e4
LT		 1398}
1399
02330fba
AM		 1400/******************************************************************/
1401
1402#ifdef SUPPORT_GAMEPORT
1403static inline void
dfbf9511
AM		 1404snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1405 bool enable
1406)
02330fba
AM		 1407{
1408 snd_azf3328_io_reg_setb(
1409 chip->game_io+IDX_GAME_HWCONFIG,
1410 GAME_HWCFG_IRQ_ENABLE,
1411 enable
1412 );
1413}
1414
1415static inline void
dfbf9511
AM		 1416snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1417 bool enable
1418)
02330fba
AM		 1419{
1420 snd_azf3328_io_reg_setb(
1421 chip->game_io+IDX_GAME_HWCONFIG,
1422 GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1423 enable
1424 );
1425}
1426
dfbf9511
AM		 1427static void
1428snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1429 unsigned int freq_cfg
1430)
1431{
1432 snd_azf3328_io_reg_setb(
1433 chip->game_io+IDX_GAME_HWCONFIG,
1434 0x02,
1435 (freq_cfg & 1) != 0
1436 );
1437 snd_azf3328_io_reg_setb(
1438 chip->game_io+IDX_GAME_HWCONFIG,
1439 0x04,
1440 (freq_cfg & 2) != 0
1441 );
1442}
1443
02330fba 1444static inline void
dfbf9511 1445snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
02330fba 1446{
dfbf9511 1447 snd_azf3328_ctrl_reg_6AH_update(
627d3e7a 1448 chip, IO_6A_SOMETHING2_GAMEPORT, enable
02330fba
AM		 1449 );
1450}
1451
1452static inline void
1453snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1454{
1455 /*
1456 * skeleton handler only
1457 * (we do not want axis reading in interrupt handler - too much load!)
1458 */
1459 snd_azf3328_dbggame("gameport irq\n");
1460
1461 /* this should ACK the gameport IRQ properly, hopefully. */
1462 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1463}
1464
1465static int
1466snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1467{
1468 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1469 int res;
1470
1471 snd_azf3328_dbggame("gameport_open, mode %d\n", mode);
1472 switch (mode) {
1473 case GAMEPORT_MODE_COOKED:
1474 case GAMEPORT_MODE_RAW:
1475 res = 0;
1476 break;
1477 default:
1478 res = -1;
1479 break;
1480 }
1481
dfbf9511
AM		 1482 snd_azf3328_gameport_set_counter_frequency(chip,
1483 GAME_HWCFG_ADC_COUNTER_FREQ_STD);
02330fba
AM		 1484 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1485
1486 return res;
1487}
1488
1489static void
1490snd_azf3328_gameport_close(struct gameport *gameport)
1491{
1492 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1493
1494 snd_azf3328_dbggame("gameport_close\n");
dfbf9511
AM		 1495 snd_azf3328_gameport_set_counter_frequency(chip,
1496 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
02330fba
AM		 1497 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1498}
1499
1500static int
1501snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1502 int *axes,
1503 int *buttons
1504)
1505{
1506 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1507 int i;
1508 u8 val;
1509 unsigned long flags;
1510
da3cec35
TI		 1511 if (snd_BUG_ON(!chip))
1512 return 0;
02330fba
AM		 1513
1514 spin_lock_irqsave(&chip->reg_lock, flags);
1515 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1516 *buttons = (~(val) >> 4) & 0xf;
1517
1518 /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
1519 * thus we're atomic and cannot actively wait in here
1520 * (which would be useful for us since it probably would be better
1521 * to trigger a measurement in here, then wait a short amount of
1522 * time until it's finished, then read values of _this_ measurement).
1523 *
1524 * Thus we simply resort to reading values if they're available already
1525 * and trigger the next measurement.
1526 */
1527
1528 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1529 if (val & GAME_AXES_SAMPLING_READY) {
dfbf9511 1530 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
02330fba
AM		 1531 /* configure the axis to read */
1532 val = (i << 4) | 0x0f;
1533 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1534
1535 chip->axes[i] = snd_azf3328_game_inw(
1536 chip, IDX_GAME_AXIS_VALUE
1537 );
1538 }
1539 }
1540
adf5931f 1541 /* trigger next sampling of axes, to be evaluated the next time we
02330fba
AM		 1542 * enter this function */
1543
1544 /* for some very, very strange reason we cannot enable
1545 * Measurement Ready monitoring for all axes here,
1546 * at least not when only one joystick connected */
1547 val = 0x03; /* we're able to monitor axes 1 and 2 only */
1548 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1549
1550 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1551 spin_unlock_irqrestore(&chip->reg_lock, flags);
1552
dfbf9511 1553 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
02330fba
AM		 1554 axes[i] = chip->axes[i];
1555 if (axes[i] == 0xffff)
1556 axes[i] = -1;
1557 }
1558
1559 snd_azf3328_dbggame("cooked_read: axes %d %d %d %d buttons %d\n",
1560 axes[0], axes[1], axes[2], axes[3], *buttons
1561 );
1562
1563 return 0;
1564}
1565
1566static int __devinit
1567snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1568{
1569 struct gameport *gp;
1570
02330fba
AM		 1571 chip->gameport = gp = gameport_allocate_port();
1572 if (!gp) {
1573 printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n");
1574 return -ENOMEM;
1575 }
1576
1577 gameport_set_name(gp, "AZF3328 Gameport");
1578 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1579 gameport_set_dev_parent(gp, &chip->pci->dev);
627d3e7a 1580 gp->io = chip->game_io;
02330fba
AM		 1581 gameport_set_port_data(gp, chip);
1582
1583 gp->open = snd_azf3328_gameport_open;
1584 gp->close = snd_azf3328_gameport_close;
1585 gp->fuzz = 16; /* seems ok */
1586 gp->cooked_read = snd_azf3328_gameport_cooked_read;
1587
1588 /* DISABLE legacy address: we don't need it! */
1589 snd_azf3328_gameport_legacy_address_enable(chip, 0);
1590
dfbf9511
AM		 1591 snd_azf3328_gameport_set_counter_frequency(chip,
1592 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
02330fba
AM		 1593 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1594
1595 gameport_register_port(chip->gameport);
1596
1597 return 0;
1598}
1599
1600static void
1601snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1602{
1603 if (chip->gameport) {
1604 gameport_unregister_port(chip->gameport);
1605 chip->gameport = NULL;
1606 }
1607 snd_azf3328_gameport_irq_enable(chip, 0);
1608}
1609#else
1610static inline int
1611snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1612static inline void
1613snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1614static inline void
1615snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1616{
1617 printk(KERN_WARNING "huh, game port IRQ occurred!?\n");
1618}
1619#endif /* SUPPORT_GAMEPORT */
1620
1621/******************************************************************/
1622
627d3e7a
AM		 1623static inline void
1624snd_azf3328_irq_log_unknown_type(u8 which)
1625{
78df617a 1626 snd_azf3328_dbgcodec(
627d3e7a
AM		 1627 "azt3328: unknown IRQ type (%x) occurred, please report!\n",
1628 which
1629 );
1630}
1631
dfbf9511
AM		 1632static inline void
1633snd_azf3328_codec_interrupt(struct snd_azf3328 *chip, u8 status)
1634{
1635 u8 which;
1636 enum snd_azf3328_codec_type codec_type;
1637 const struct snd_azf3328_codec_data *codec;
1638
1639 for (codec_type = AZF_CODEC_PLAYBACK;
1640 codec_type <= AZF_CODEC_I2S_OUT;
1641 ++codec_type) {
1642
1643 /* skip codec if there's no interrupt for it */
1644 if (!(status & (1 << codec_type)))
1645 continue;
1646
1647 codec = &chip->codecs[codec_type];
1648
1649 spin_lock(&chip->reg_lock);
1650 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
1651 /* ack all IRQ types immediately */
1652 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
1653 spin_unlock(&chip->reg_lock);
1654
78df617a
AM		 1655 if ((chip->pcm[codec_type]) && (codec->substream)) {
1656 snd_pcm_period_elapsed(codec->substream);
1657 snd_azf3328_dbgcodec("%s period done (#%x), @ %x\n",
dfbf9511
AM		 1658 codec->name,
1659 which,
1660 snd_azf3328_codec_inl(
1661 codec, IDX_IO_CODEC_DMA_CURRPOS
1662 )
1663 );
1664 } else
1665 printk(KERN_WARNING "azt3328: irq handler problem!\n");
1666 if (which & IRQ_SOMETHING)
1667 snd_azf3328_irq_log_unknown_type(which);
1668 }
1669}
1670
d91c64c8 1671static irqreturn_t
7d12e780 1672snd_azf3328_interrupt(int irq, void *dev_id)
1da177e4 1673{
95de7766 1674 struct snd_azf3328 *chip = dev_id;
dfbf9511 1675 u8 status;
78df617a 1676#if DEBUG_CODEC
d91c64c8 1677 static unsigned long irq_count;
02330fba 1678#endif
1da177e4 1679
dfbf9511 1680 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1da177e4
LT		 1681
1682 /* fast path out, to ease interrupt sharing */
02330fba 1683 if (!(status &
dfbf9511
AM		 1684 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
1685 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
02330fba 1686 ))
1da177e4
LT		 1687 return IRQ_NONE; /* must be interrupt for another device */
1688
78df617a 1689 snd_azf3328_dbgcodec(
dfbf9511 1690 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
627d3e7a 1691 irq_count++ /* debug-only */,
627d3e7a
AM		 1692 status
1693 );
02330fba 1694
e2f87260 1695 if (status & IRQ_TIMER) {
78df617a 1696 /* snd_azf3328_dbgcodec("timer %ld\n",
02330fba
AM		 1697 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1698 & TIMER_VALUE_MASK
1699 ); */
d91c64c8
AM		 1700 if (chip->timer)
1701 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1702 /* ACK timer */
1703 spin_lock(&chip->reg_lock);
dfbf9511 1704 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
d91c64c8 1705 spin_unlock(&chip->reg_lock);
78df617a 1706 snd_azf3328_dbgcodec("azt3328: timer IRQ\n");
d91c64c8 1707 }
d91c64c8 1708
dfbf9511
AM		 1709 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
1710 snd_azf3328_codec_interrupt(chip, status);
d91c64c8 1711
02330fba
AM		 1712 if (status & IRQ_GAMEPORT)
1713 snd_azf3328_gameport_interrupt(chip);
dfbf9511 1714
d91c64c8
AM		 1715 /* MPU401 has less critical IRQ requirements
1716 * than timer and playback/recording, right? */
e2f87260 1717 if (status & IRQ_MPU401) {
7d12e780 1718 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
d91c64c8
AM		 1719
1720 /* hmm, do we have to ack the IRQ here somehow?
dfbf9511 1721 * If so, then I don't know how yet... */
78df617a 1722 snd_azf3328_dbgcodec("azt3328: MPU401 IRQ\n");
d91c64c8 1723 }
1da177e4
LT		 1724 return IRQ_HANDLED;
1725}
1726
1727/*****************************************************************/
1728
dfbf9511
AM		 1729/* as long as we think we have identical snd_pcm_hardware parameters
1730 for playback, capture and i2s out, we can use the same physical struct
1731 since the struct is simply being copied into a member.
1732*/
1733static const struct snd_pcm_hardware snd_azf3328_hardware =
1da177e4
LT		 1734{
1735 /* FIXME!! Correct? */
d91c64c8
AM		 1736 .info = SNDRV_PCM_INFO_MMAP |
1737 SNDRV_PCM_INFO_INTERLEAVED |
1738 SNDRV_PCM_INFO_MMAP_VALID,
1739 .formats = SNDRV_PCM_FMTBIT_S8 |
1740 SNDRV_PCM_FMTBIT_U8 |
1741 SNDRV_PCM_FMTBIT_S16_LE |
1742 SNDRV_PCM_FMTBIT_U16_LE,
1743 .rates = SNDRV_PCM_RATE_5512 |
1744 SNDRV_PCM_RATE_8000_48000 |
1745 SNDRV_PCM_RATE_KNOT,
02330fba
AM		 1746 .rate_min = AZF_FREQ_4000,
1747 .rate_max = AZF_FREQ_66200,
1da177e4
LT		 1748 .channels_min = 1,
1749 .channels_max = 2,
7974150c
AM		 1750 .buffer_bytes_max = (64*1024),
1751 .period_bytes_min = 1024,
1752 .period_bytes_max = (32*1024),
1753 /* We simply have two DMA areas (instead of a list of descriptors
1754 such as other cards); I believe that this is a fixed hardware
1755 attribute and there isn't much driver magic to be done to expand it.
1756 Thus indicate that we have at least and at most 2 periods. */
1757 .periods_min = 2,
1758 .periods_max = 2,
1da177e4
LT		 1759 /* FIXME: maybe that card actually has a FIFO?
1760 * Hmm, it seems newer revisions do have one, but we still don't know
1761 * its size... */
1762 .fifo_size = 0,
1763};
1764
1da177e4
LT		 1765
1766static unsigned int snd_azf3328_fixed_rates[] = {
02330fba
AM		 1767 AZF_FREQ_4000,
1768 AZF_FREQ_4800,
1769 AZF_FREQ_5512,
1770 AZF_FREQ_6620,
1771 AZF_FREQ_8000,
1772 AZF_FREQ_9600,
1773 AZF_FREQ_11025,
1774 AZF_FREQ_13240,
1775 AZF_FREQ_16000,
1776 AZF_FREQ_22050,
1777 AZF_FREQ_32000,
1778 AZF_FREQ_44100,
1779 AZF_FREQ_48000,
1780 AZF_FREQ_66200
1781};
1782
95de7766 1783static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
02330fba 1784 .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
1da177e4
LT		 1785 .list = snd_azf3328_fixed_rates,
1786 .mask = 0,
1787};
1788
1789/*****************************************************************/
1790
d91c64c8 1791static int
dfbf9511
AM		 1792snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
1793 enum snd_azf3328_codec_type codec_type
1794)
1da177e4 1795{
95de7766
TI		 1796 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1797 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1798
1799 snd_azf3328_dbgcallenter();
dfbf9511
AM		 1800 chip->codecs[codec_type].substream = substream;
1801
1802 /* same parameters for all our codecs - at least we think so... */
1803 runtime->hw = snd_azf3328_hardware;
1804
1da177e4
LT		 1805 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1806 &snd_azf3328_hw_constraints_rates);
1807 snd_azf3328_dbgcallleave();
1808 return 0;
1809}
1810
dfbf9511
AM		 1811static int
1812snd_azf3328_playback_open(struct snd_pcm_substream *substream)
1813{
1814 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
1815}
1816
d91c64c8 1817static int
95de7766 1818snd_azf3328_capture_open(struct snd_pcm_substream *substream)
1da177e4 1819{
dfbf9511
AM		 1820 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
1821}
1da177e4 1822
dfbf9511
AM		 1823static int
1824snd_azf3328_i2s_out_open(struct snd_pcm_substream *substream)
1825{
1826 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
1da177e4
LT		 1827}
1828
d91c64c8 1829static int
dfbf9511
AM		 1830snd_azf3328_pcm_close(struct snd_pcm_substream *substream,
1831 enum snd_azf3328_codec_type codec_type
1832)
1da177e4 1833{
95de7766 1834 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1835
1836 snd_azf3328_dbgcallenter();
dfbf9511 1837 chip->codecs[codec_type].substream = NULL;
1da177e4
LT		 1838 snd_azf3328_dbgcallleave();
1839 return 0;
1840}
1841
dfbf9511
AM		 1842static int
1843snd_azf3328_playback_close(struct snd_pcm_substream *substream)
1844{
1845 return snd_azf3328_pcm_close(substream, AZF_CODEC_PLAYBACK);
1846}
1847
d91c64c8 1848static int
95de7766 1849snd_azf3328_capture_close(struct snd_pcm_substream *substream)
1da177e4 1850{
dfbf9511
AM		 1851 return snd_azf3328_pcm_close(substream, AZF_CODEC_CAPTURE);
1852}
1da177e4 1853
dfbf9511
AM		 1854static int
1855snd_azf3328_i2s_out_close(struct snd_pcm_substream *substream)
1856{
1857 return snd_azf3328_pcm_close(substream, AZF_CODEC_I2S_OUT);
1da177e4
LT		 1858}
1859
1860/******************************************************************/
1861
95de7766 1862static struct snd_pcm_ops snd_azf3328_playback_ops = {
1da177e4
LT		 1863 .open = snd_azf3328_playback_open,
1864 .close = snd_azf3328_playback_close,
1865 .ioctl = snd_pcm_lib_ioctl,
1866 .hw_params = snd_azf3328_hw_params,
1867 .hw_free = snd_azf3328_hw_free,
dfbf9511
AM		 1868 .prepare = snd_azf3328_codec_prepare,
1869 .trigger = snd_azf3328_codec_playback_trigger,
1870 .pointer = snd_azf3328_codec_playback_pointer
1da177e4
LT		 1871};
1872
95de7766 1873static struct snd_pcm_ops snd_azf3328_capture_ops = {
1da177e4
LT		 1874 .open = snd_azf3328_capture_open,
1875 .close = snd_azf3328_capture_close,
1876 .ioctl = snd_pcm_lib_ioctl,
1877 .hw_params = snd_azf3328_hw_params,
1878 .hw_free = snd_azf3328_hw_free,
dfbf9511
AM		 1879 .prepare = snd_azf3328_codec_prepare,
1880 .trigger = snd_azf3328_codec_capture_trigger,
1881 .pointer = snd_azf3328_codec_capture_pointer
1882};
1883
1884static struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
1885 .open = snd_azf3328_i2s_out_open,
1886 .close = snd_azf3328_i2s_out_close,
1887 .ioctl = snd_pcm_lib_ioctl,
1888 .hw_params = snd_azf3328_hw_params,
1889 .hw_free = snd_azf3328_hw_free,
1890 .prepare = snd_azf3328_codec_prepare,
1891 .trigger = snd_azf3328_codec_i2s_out_trigger,
1892 .pointer = snd_azf3328_codec_i2s_out_pointer
1da177e4
LT		 1893};
1894
d91c64c8 1895static int __devinit
dfbf9511 1896snd_azf3328_pcm(struct snd_azf3328 *chip)
1da177e4 1897{
dfbf9511
AM		 1898enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; /* pcm devices */
1899
95de7766 1900 struct snd_pcm *pcm;
1da177e4
LT		 1901 int err;
1902
1903 snd_azf3328_dbgcallenter();
dfbf9511
AM		 1904
1905 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
1906 1, 1, &pcm);
1907 if (err < 0)
1da177e4 1908 return err;
dfbf9511
AM		 1909 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1910 &snd_azf3328_playback_ops);
1911 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1912 &snd_azf3328_capture_ops);
1da177e4
LT		 1913
1914 pcm->private_data = chip;
1da177e4
LT		 1915 pcm->info_flags = 0;
1916 strcpy(pcm->name, chip->card->shortname);
dfbf9511
AM		 1917 /* same pcm object for playback/capture (see snd_pcm_new() above) */
1918 chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
1919 chip->pcm[AZF_CODEC_CAPTURE] = pcm;
1da177e4
LT		 1920
1921 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
dfbf9511
AM		 1922 snd_dma_pci_data(chip->pci),
1923 64*1024, 64*1024);
1924
1925 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
1926 1, 0, &pcm);
1927 if (err < 0)
1928 return err;
1929 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1930 &snd_azf3328_i2s_out_ops);
1931
1932 pcm->private_data = chip;
1933 pcm->info_flags = 0;
1934 strcpy(pcm->name, chip->card->shortname);
1935 chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
1936
1937 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1938 snd_dma_pci_data(chip->pci),
1939 64*1024, 64*1024);
1da177e4
LT		 1940
1941 snd_azf3328_dbgcallleave();
1942 return 0;
1943}
1944
1945/******************************************************************/
1946
02330fba
AM		 1947/*** NOTE: the physical timer resolution actually is 1024000 ticks per second
1948 *** (probably derived from main crystal via a divider of 24),
d91c64c8
AM		 1949 *** but announcing those attributes to user-space would make programs
1950 *** configure the timer to a 1 tick value, resulting in an absolutely fatal
1951 *** timer IRQ storm.
1952 *** Thus I chose to announce a down-scaled virtual timer to the outside and
1953 *** calculate real timer countdown values internally.
1954 *** (the scale factor can be set via module parameter "seqtimer_scaling").
1955 ***/
1956
1957static int
95de7766 1958snd_azf3328_timer_start(struct snd_timer *timer)
d91c64c8 1959{
95de7766 1960 struct snd_azf3328 *chip;
d91c64c8
AM		 1961 unsigned long flags;
1962 unsigned int delay;
1963
1964 snd_azf3328_dbgcallenter();
1965 chip = snd_timer_chip(timer);
1966 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
e2f87260 1967 if (delay < 49) {
d91c64c8
AM		 1968 /* uhoh, that's not good, since user-space won't know about
1969 * this timing tweak
1970 * (we need to do it to avoid a lockup, though) */
1971
1972 snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
1973 delay = 49; /* minimum time is 49 ticks */
1974 }
adf5931f 1975 snd_azf3328_dbgtimer("setting timer countdown value %d\n", delay);
02330fba 1976 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
d91c64c8 1977 spin_lock_irqsave(&chip->reg_lock, flags);
dfbf9511 1978 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
d91c64c8
AM		 1979 spin_unlock_irqrestore(&chip->reg_lock, flags);
1980 snd_azf3328_dbgcallleave();
1981 return 0;
1982}
1983
1984static int
95de7766 1985snd_azf3328_timer_stop(struct snd_timer *timer)
d91c64c8 1986{
95de7766 1987 struct snd_azf3328 *chip;
d91c64c8
AM		 1988 unsigned long flags;
1989
1990 snd_azf3328_dbgcallenter();
1991 chip = snd_timer_chip(timer);
1992 spin_lock_irqsave(&chip->reg_lock, flags);
1993 /* disable timer countdown and interrupt */
7974150c
AM		 1994 /* Hmm, should we write TIMER_IRQ_ACK here?
1995 YES indeed, otherwise a rogue timer operation - which prompts
1996 ALSA(?) to call repeated stop() in vain, but NOT start() -
1997 will never end (value 0x03 is kept shown in control byte).
1998 Simply manually poking 0x04 _once_ immediately successfully stops
1999 the hardware/ALSA interrupt activity. */
2000 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
d91c64c8
AM		 2001 spin_unlock_irqrestore(&chip->reg_lock, flags);
2002 snd_azf3328_dbgcallleave();
2003 return 0;
2004}
2005
2006
2007static int
95de7766 2008snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
d91c64c8
AM		 2009 unsigned long *num, unsigned long *den)
2010{
2011 snd_azf3328_dbgcallenter();
2012 *num = 1;
2013 *den = 1024000 / seqtimer_scaling;
2014 snd_azf3328_dbgcallleave();
2015 return 0;
2016}
2017
95de7766 2018static struct snd_timer_hardware snd_azf3328_timer_hw = {
d91c64c8
AM		 2019 .flags = SNDRV_TIMER_HW_AUTO,
2020 .resolution = 977, /* 1000000/1024000 = 0.9765625us */
2021 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
2022 .start = snd_azf3328_timer_start,
2023 .stop = snd_azf3328_timer_stop,
2024 .precise_resolution = snd_azf3328_timer_precise_resolution,
2025};
2026
2027static int __devinit
95de7766 2028snd_azf3328_timer(struct snd_azf3328 *chip, int device)
d91c64c8 2029{
95de7766
TI		 2030 struct snd_timer *timer = NULL;
2031 struct snd_timer_id tid;
d91c64c8
AM		 2032 int err;
2033
2034 snd_azf3328_dbgcallenter();
2035 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
2036 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
2037 tid.card = chip->card->number;
2038 tid.device = device;
2039 tid.subdevice = 0;
2040
2041 snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
2042 snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
02330fba
AM		 2043
2044 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
2045 if (err < 0)
d91c64c8 2046 goto out;
d91c64c8
AM		 2047
2048 strcpy(timer->name, "AZF3328 timer");
2049 timer->private_data = chip;
2050 timer->hw = snd_azf3328_timer_hw;
2051
2052 chip->timer = timer;
2053
02330fba
AM		 2054 snd_azf3328_timer_stop(timer);
2055
d91c64c8
AM		 2056 err = 0;
2057
2058out:
2059 snd_azf3328_dbgcallleave();
2060 return err;
2061}
2062
2063/******************************************************************/
2064
02330fba
AM		 2065static int
2066snd_azf3328_free(struct snd_azf3328 *chip)
2067{
2068 if (chip->irq < 0)
2069 goto __end_hw;
2070
2071 /* reset (close) mixer:
2072 * first mute master volume, then reset
2073 */
2074 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2075 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
2076
2077 snd_azf3328_timer_stop(chip->timer);
2078 snd_azf3328_gameport_free(chip);
2079
2080 if (chip->irq >= 0)
2081 synchronize_irq(chip->irq);
2082__end_hw:
2083 if (chip->irq >= 0)
2084 free_irq(chip->irq, chip);
2085 pci_release_regions(chip->pci);
2086 pci_disable_device(chip->pci);
2087
2088 kfree(chip);
2089 return 0;
2090}
2091
2092static int
2093snd_azf3328_dev_free(struct snd_device *device)
2094{
2095 struct snd_azf3328 *chip = device->device_data;
2096 return snd_azf3328_free(chip);
2097}
2098
1da177e4
LT		 2099#if 0
2100/* check whether a bit can be modified */
d91c64c8 2101static void
02330fba 2102snd_azf3328_test_bit(unsigned unsigned reg, int bit)
1da177e4
LT		 2103{
2104 unsigned char val, valoff, valon;
2105
2106 val = inb(reg);
2107
2108 outb(val & ~(1 << bit), reg);
2109 valoff = inb(reg);
2110
2111 outb(val|(1 << bit), reg);
2112 valon = inb(reg);
02330fba 2113
1da177e4
LT		 2114 outb(val, reg);
2115
78df617a 2116 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
02330fba
AM		 2117 reg, bit, val, valoff, valon
2118 );
1da177e4
LT		 2119}
2120#endif
2121
02330fba 2122static inline void
95de7766 2123snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
d91c64c8 2124{
02330fba 2125#if DEBUG_MISC
d91c64c8
AM		 2126 u16 tmp;
2127
02330fba 2128 snd_azf3328_dbgmisc(
dfbf9511 2129 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
02330fba 2130 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
dfbf9511 2131 chip->ctrl_io, chip->game_io, chip->mpu_io,
02330fba
AM		 2132 chip->opl3_io, chip->mixer_io, chip->irq
2133 );
2134
2135 snd_azf3328_dbgmisc("game %02x %02x %02x %02x %02x %02x\n",
2136 snd_azf3328_game_inb(chip, 0),
2137 snd_azf3328_game_inb(chip, 1),
2138 snd_azf3328_game_inb(chip, 2),
2139 snd_azf3328_game_inb(chip, 3),
2140 snd_azf3328_game_inb(chip, 4),
2141 snd_azf3328_game_inb(chip, 5)
2142 );
2143
2144 for (tmp = 0; tmp < 0x07; tmp += 1)
2145 snd_azf3328_dbgmisc("mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2146
2147 for (tmp = 0; tmp <= 0x07; tmp += 1)
2148 snd_azf3328_dbgmisc("0x%02x: game200 0x%04x, game208 0x%04x\n",
2149 tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2150
2151 for (tmp = 0; tmp <= 0x01; tmp += 1)
2152 snd_azf3328_dbgmisc(
2153 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2154 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2155 tmp,
2156 inb(0x300 + tmp),
2157 inb(0x310 + tmp),
2158 inb(0x320 + tmp),
2159 inb(0x330 + tmp),
2160 inb(0x388 + tmp),
2161 inb(0x38c + tmp)
2162 );
d91c64c8 2163
dfbf9511
AM		 2164 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
2165 snd_azf3328_dbgmisc("ctrl 0x%02x: 0x%04x\n",
2166 tmp, snd_azf3328_ctrl_inw(chip, tmp)
02330fba 2167 );
e24a121a
AM		 2168
2169 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
02330fba
AM		 2170 snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n",
2171 tmp, snd_azf3328_mixer_inw(chip, tmp)
2172 );
2173#endif /* DEBUG_MISC */
d91c64c8
AM		 2174}
2175
2176static int __devinit
95de7766 2177snd_azf3328_create(struct snd_card *card,
02330fba
AM		 2178 struct pci_dev *pci,
2179 unsigned long device_type,
2180 struct snd_azf3328 **rchip)
1da177e4 2181{
95de7766 2182 struct snd_azf3328 *chip;
1da177e4 2183 int err;
95de7766 2184 static struct snd_device_ops ops = {
1da177e4
LT		 2185 .dev_free = snd_azf3328_dev_free,
2186 };
dfbf9511
AM		 2187 u8 dma_init;
2188 enum snd_azf3328_codec_type codec_type;
1da177e4
LT		 2189
2190 *rchip = NULL;
2191
02330fba
AM		 2192 err = pci_enable_device(pci);
2193 if (err < 0)
1da177e4
LT		 2194 return err;
2195
e560d8d8 2196 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4 2197 if (chip == NULL) {
d91c64c8
AM		 2198 err = -ENOMEM;
2199 goto out_err;
1da177e4
LT		 2200 }
2201 spin_lock_init(&chip->reg_lock);
2202 chip->card = card;
2203 chip->pci = pci;
2204 chip->irq = -1;
2205
2206 /* check if we can restrict PCI DMA transfers to 24 bits */
2f4f27d4
YH		 2207 if (pci_set_dma_mask(pci, DMA_BIT_MASK(24)) < 0 ||
2208 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(24)) < 0) {
02330fba
AM		 2209 snd_printk(KERN_ERR "architecture does not support "
2210 "24bit PCI busmaster DMA\n"
2211 );
d91c64c8
AM		 2212 err = -ENXIO;
2213 goto out_err;
1da177e4
LT		 2214 }
2215
02330fba
AM		 2216 err = pci_request_regions(pci, "Aztech AZF3328");
2217 if (err < 0)
d91c64c8 2218 goto out_err;
1da177e4 2219
dfbf9511 2220 chip->ctrl_io = pci_resource_start(pci, 0);
02330fba
AM		 2221 chip->game_io = pci_resource_start(pci, 1);
2222 chip->mpu_io = pci_resource_start(pci, 2);
dfbf9511 2223 chip->opl3_io = pci_resource_start(pci, 3);
02330fba
AM		 2224 chip->mixer_io = pci_resource_start(pci, 4);
2225
dfbf9511
AM		 2226 chip->codecs[AZF_CODEC_PLAYBACK].io_base =
2227 chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2228 chip->codecs[AZF_CODEC_PLAYBACK].name = "PLAYBACK";
2229 chip->codecs[AZF_CODEC_CAPTURE].io_base =
2230 chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2231 chip->codecs[AZF_CODEC_CAPTURE].name = "CAPTURE";
2232 chip->codecs[AZF_CODEC_I2S_OUT].io_base =
2233 chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2234 chip->codecs[AZF_CODEC_I2S_OUT].name = "I2S_OUT";
1da177e4 2235
437a5a46
TI		 2236 if (request_irq(pci->irq, snd_azf3328_interrupt,
2237 IRQF_SHARED, card->shortname, chip)) {
99b359ba 2238 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
d91c64c8
AM		 2239 err = -EBUSY;
2240 goto out_err;
1da177e4
LT		 2241 }
2242 chip->irq = pci->irq;
2243 pci_set_master(pci);
2244 synchronize_irq(chip->irq);
2245
d91c64c8 2246 snd_azf3328_debug_show_ports(chip);
02330fba
AM		 2247
2248 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2249 if (err < 0)
d91c64c8 2250 goto out_err;
1da177e4
LT		 2251
2252 /* create mixer interface & switches */
02330fba
AM		 2253 err = snd_azf3328_mixer_new(chip);
2254 if (err < 0)
d91c64c8 2255 goto out_err;
1da177e4 2256
dfbf9511
AM		 2257 /* standard codec init stuff */
2258 /* default DMA init value */
2259 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2260
2261 for (codec_type = AZF_CODEC_PLAYBACK;
2262 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
2263 struct snd_azf3328_codec_data *codec =
2264 &chip->codecs[codec_type];
1da177e4 2265
adf5931f 2266 /* shutdown codecs to reduce power / noise */
dfbf9511
AM		 2267 /* have ...ctrl_codec_activity() act properly */
2268 codec->running = 1;
2269 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
1da177e4 2270
dfbf9511
AM		 2271 spin_lock_irq(&chip->reg_lock);
2272 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
2273 dma_init);
2274 spin_unlock_irq(&chip->reg_lock);
2275 }
1da177e4
LT		 2276
2277 snd_card_set_dev(card, &pci->dev);
2278
2279 *rchip = chip;
d91c64c8
AM		 2280
2281 err = 0;
2282 goto out;
2283
2284out_err:
2285 if (chip)
2286 snd_azf3328_free(chip);
2287 pci_disable_device(pci);
2288
2289out:
2290 return err;
1da177e4
LT		 2291}
2292
d91c64c8
AM		 2293static int __devinit
2294snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1da177e4
LT		 2295{
2296 static int dev;
95de7766
TI		 2297 struct snd_card *card;
2298 struct snd_azf3328 *chip;
2299 struct snd_opl3 *opl3;
1da177e4
LT		 2300 int err;
2301
2302 snd_azf3328_dbgcallenter();
2303 if (dev >= SNDRV_CARDS)
2304 return -ENODEV;
2305 if (!enable[dev]) {
2306 dev++;
2307 return -ENOENT;
2308 }
2309
e58de7ba
TI		 2310 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2311 if (err < 0)
2312 return err;
1da177e4
LT		 2313
2314 strcpy(card->driver, "AZF3328");
2315 strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
2316
02330fba
AM		 2317 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2318 if (err < 0)
d91c64c8 2319 goto out_err;
1da177e4 2320
ca54bde3
AM		 2321 card->private_data = chip;
2322
78df617a
AM		 2323 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
2324 since our hardware ought to be similar, thus use same ID. */
02330fba 2325 err = snd_mpu401_uart_new(
78df617a
AM		 2326 card, 0,
2327 MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED,
02330fba
AM		 2328 pci->irq, 0, &chip->rmidi
2329 );
2330 if (err < 0) {
2331 snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n",
2332 chip->mpu_io
2333 );
d91c64c8
AM		 2334 goto out_err;
2335 }
2336
02330fba
AM		 2337 err = snd_azf3328_timer(chip, 0);
2338 if (err < 0)
d91c64c8 2339 goto out_err;
1da177e4 2340
dfbf9511 2341 err = snd_azf3328_pcm(chip);
02330fba 2342 if (err < 0)
d91c64c8 2343 goto out_err;
1da177e4 2344
02330fba 2345 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
1da177e4 2346 OPL3_HW_AUTO, 1, &opl3) < 0) {
99b359ba 2347 snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
02330fba
AM		 2348 chip->opl3_io, chip->opl3_io+2
2349 );
1da177e4 2350 } else {
02330fba
AM		 2351 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
2352 err = snd_opl3_timer_new(opl3, 1, 2);
2353 if (err < 0)
2354 goto out_err;
2355 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2356 if (err < 0)
d91c64c8 2357 goto out_err;
1da177e4
LT		 2358 }
2359
ca54bde3
AM		 2360 opl3->private_data = chip;
2361
1da177e4 2362 sprintf(card->longname, "%s at 0x%lx, irq %i",
dfbf9511 2363 card->shortname, chip->ctrl_io, chip->irq);
1da177e4 2364
02330fba
AM		 2365 err = snd_card_register(card);
2366 if (err < 0)
d91c64c8 2367 goto out_err;
1da177e4
LT		 2368
2369#ifdef MODULE
78df617a 2370 printk(KERN_INFO
e24a121a
AM		 2371"azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
2372"azt3328: Hardware was completely undocumented, unfortunately.\n"
d91c64c8
AM		 2373"azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
2374"azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2375 1024000 / seqtimer_scaling, seqtimer_scaling);
1da177e4
LT		 2376#endif
2377
02330fba 2378 snd_azf3328_gameport(chip, dev);
1da177e4
LT		 2379
2380 pci_set_drvdata(pci, card);
2381 dev++;
2382
d91c64c8
AM		 2383 err = 0;
2384 goto out;
02330fba 2385
d91c64c8 2386out_err:
02330fba 2387 snd_printk(KERN_ERR "azf3328: something failed, exiting\n");
d91c64c8 2388 snd_card_free(card);
02330fba 2389
d91c64c8 2390out:
1da177e4 2391 snd_azf3328_dbgcallleave();
d91c64c8 2392 return err;
1da177e4
LT		 2393}
2394
d91c64c8
AM		 2395static void __devexit
2396snd_azf3328_remove(struct pci_dev *pci)
1da177e4
LT		 2397{
2398 snd_azf3328_dbgcallenter();
2399 snd_card_free(pci_get_drvdata(pci));
2400 pci_set_drvdata(pci, NULL);
2401 snd_azf3328_dbgcallleave();
2402}
2403
ca54bde3 2404#ifdef CONFIG_PM
78df617a
AM		 2405static inline void
2406snd_azf3328_suspend_regs(unsigned long io_addr, unsigned count, u32 *saved_regs)
2407{
2408 unsigned reg;
2409
2410 for (reg = 0; reg < count; ++reg) {
2411 *saved_regs = inl(io_addr);
2412 snd_azf3328_dbgpm("suspend: io 0x%04lx: 0x%08x\n",
2413 io_addr, *saved_regs);
2414 ++saved_regs;
2415 io_addr += sizeof(*saved_regs);
2416 }
2417}
2418
ca54bde3
AM		 2419static int
2420snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
2421{
2422 struct snd_card *card = pci_get_drvdata(pci);
2423 struct snd_azf3328 *chip = card->private_data;
78df617a 2424 u16 *saved_regs_ctrl_u16;
ca54bde3
AM		 2425
2426 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
02330fba 2427
adf5931f 2428 /* same pcm object for playback/capture */
dfbf9511
AM		 2429 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_PLAYBACK]);
2430 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_I2S_OUT]);
ca54bde3 2431
78df617a
AM		 2432 snd_azf3328_suspend_regs(chip->mixer_io,
2433 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
ca54bde3
AM		 2434
2435 /* make sure to disable master volume etc. to prevent looping sound */
2436 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2437 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
02330fba 2438
78df617a
AM		 2439 snd_azf3328_suspend_regs(chip->ctrl_io,
2440 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
627d3e7a
AM		 2441
2442 /* manually store the one currently relevant write-only reg, too */
78df617a
AM		 2443 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2444 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
627d3e7a 2445
78df617a
AM		 2446 snd_azf3328_suspend_regs(chip->game_io,
2447 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
2448 snd_azf3328_suspend_regs(chip->mpu_io,
2449 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
2450 snd_azf3328_suspend_regs(chip->opl3_io,
2451 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
ca54bde3 2452
ca54bde3
AM		 2453 pci_disable_device(pci);
2454 pci_save_state(pci);
30b35399 2455 pci_set_power_state(pci, pci_choose_state(pci, state));
ca54bde3
AM		 2456 return 0;
2457}
2458
78df617a
AM		 2459static inline void
2460snd_azf3328_resume_regs(const u32 *saved_regs,
2461 unsigned long io_addr,
2462 unsigned count
2463)
2464{
2465 unsigned reg;
2466
2467 for (reg = 0; reg < count; ++reg) {
2468 outl(*saved_regs, io_addr);
2469 snd_azf3328_dbgpm("resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
2470 io_addr, *saved_regs, inl(io_addr));
2471 ++saved_regs;
2472 io_addr += sizeof(*saved_regs);
2473 }
2474}
2475
ca54bde3
AM		 2476static int
2477snd_azf3328_resume(struct pci_dev *pci)
2478{
2479 struct snd_card *card = pci_get_drvdata(pci);
dfbf9511 2480 const struct snd_azf3328 *chip = card->private_data;
ca54bde3 2481
ca54bde3 2482 pci_set_power_state(pci, PCI_D0);
30b35399
TI		 2483 pci_restore_state(pci);
2484 if (pci_enable_device(pci) < 0) {
2485 printk(KERN_ERR "azt3328: pci_enable_device failed, "
2486 "disabling device\n");
2487 snd_card_disconnect(card);
2488 return -EIO;
2489 }
ca54bde3
AM		 2490 pci_set_master(pci);
2491
78df617a
AM		 2492 snd_azf3328_resume_regs(chip->saved_regs_game, chip->game_io,
2493 ARRAY_SIZE(chip->saved_regs_game));
2494 snd_azf3328_resume_regs(chip->saved_regs_mpu, chip->mpu_io,
2495 ARRAY_SIZE(chip->saved_regs_mpu));
2496 snd_azf3328_resume_regs(chip->saved_regs_opl3, chip->opl3_io,
2497 ARRAY_SIZE(chip->saved_regs_opl3));
2498
2499 snd_azf3328_resume_regs(chip->saved_regs_mixer, chip->mixer_io,
2500 ARRAY_SIZE(chip->saved_regs_mixer));
2501
2502 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
2503 and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
2504 resulting in a mixer reset condition persisting until _after_
2505 master vol was restored. Thus master vol needs an extra restore. */
2506 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2507
2508 snd_azf3328_resume_regs(chip->saved_regs_ctrl, chip->ctrl_io,
2509 ARRAY_SIZE(chip->saved_regs_ctrl));
ca54bde3
AM		 2510
2511 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2512 return 0;
2513}
02330fba 2514#endif /* CONFIG_PM */
ca54bde3
AM		 2515
2516
1da177e4
LT		 2517static struct pci_driver driver = {
2518 .name = "AZF3328",
2519 .id_table = snd_azf3328_ids,
2520 .probe = snd_azf3328_probe,
2521 .remove = __devexit_p(snd_azf3328_remove),
ca54bde3
AM		 2522#ifdef CONFIG_PM
2523 .suspend = snd_azf3328_suspend,
2524 .resume = snd_azf3328_resume,
2525#endif
1da177e4
LT		 2526};
2527
d91c64c8
AM		 2528static int __init
2529alsa_card_azf3328_init(void)
1da177e4
LT		 2530{
2531 int err;
2532 snd_azf3328_dbgcallenter();
01d25d46 2533 err = pci_register_driver(&driver);
1da177e4
LT		 2534 snd_azf3328_dbgcallleave();
2535 return err;
2536}
2537
d91c64c8
AM		 2538static void __exit
2539alsa_card_azf3328_exit(void)
1da177e4
LT		 2540{
2541 snd_azf3328_dbgcallenter();
2542 pci_unregister_driver(&driver);
2543 snd_azf3328_dbgcallleave();
2544}
2545
2546module_init(alsa_card_azf3328_init)
2547module_exit(alsa_card_azf3328_exit)
Linux kernel - Deliverables
This page took 0.780325 seconds and 5 git commands to generate.