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1da177e4 LT |
1 | /* |
2 | * Driver for C-Media CMI8338 and 8738 PCI soundcards. | |
3 | * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | /* Does not work. Warning may block system in capture mode */ | |
21 | /* #define USE_VAR48KRATE */ | |
22 | ||
23 | #include <sound/driver.h> | |
24 | #include <asm/io.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/gameport.h> | |
31 | #include <linux/moduleparam.h> | |
62932df8 | 32 | #include <linux/mutex.h> |
1da177e4 LT |
33 | #include <sound/core.h> |
34 | #include <sound/info.h> | |
35 | #include <sound/control.h> | |
36 | #include <sound/pcm.h> | |
37 | #include <sound/rawmidi.h> | |
38 | #include <sound/mpu401.h> | |
39 | #include <sound/opl3.h> | |
40 | #include <sound/sb.h> | |
41 | #include <sound/asoundef.h> | |
42 | #include <sound/initval.h> | |
43 | ||
44 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
45 | MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); | |
46 | MODULE_LICENSE("GPL"); | |
47 | MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," | |
48 | "{C-Media,CMI8738B}," | |
49 | "{C-Media,CMI8338A}," | |
50 | "{C-Media,CMI8338B}}"); | |
51 | ||
52 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) | |
53 | #define SUPPORT_JOYSTICK 1 | |
54 | #endif | |
55 | ||
56 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
57 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
58 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ | |
59 | static long mpu_port[SNDRV_CARDS]; | |
2f24d159 | 60 | static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; |
1da177e4 LT |
61 | static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; |
62 | #ifdef SUPPORT_JOYSTICK | |
63 | static int joystick_port[SNDRV_CARDS]; | |
64 | #endif | |
65 | ||
66 | module_param_array(index, int, NULL, 0444); | |
67 | MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); | |
68 | module_param_array(id, charp, NULL, 0444); | |
69 | MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); | |
70 | module_param_array(enable, bool, NULL, 0444); | |
71 | MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); | |
72 | module_param_array(mpu_port, long, NULL, 0444); | |
73 | MODULE_PARM_DESC(mpu_port, "MPU-401 port."); | |
74 | module_param_array(fm_port, long, NULL, 0444); | |
75 | MODULE_PARM_DESC(fm_port, "FM port."); | |
76 | module_param_array(soft_ac3, bool, NULL, 0444); | |
77 | MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); | |
78 | #ifdef SUPPORT_JOYSTICK | |
79 | module_param_array(joystick_port, int, NULL, 0444); | |
80 | MODULE_PARM_DESC(joystick_port, "Joystick port address."); | |
81 | #endif | |
82 | ||
1da177e4 LT |
83 | /* |
84 | * CM8x38 registers definition | |
85 | */ | |
86 | ||
87 | #define CM_REG_FUNCTRL0 0x00 | |
88 | #define CM_RST_CH1 0x00080000 | |
89 | #define CM_RST_CH0 0x00040000 | |
90 | #define CM_CHEN1 0x00020000 /* ch1: enable */ | |
91 | #define CM_CHEN0 0x00010000 /* ch0: enable */ | |
92 | #define CM_PAUSE1 0x00000008 /* ch1: pause */ | |
93 | #define CM_PAUSE0 0x00000004 /* ch0: pause */ | |
94 | #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ | |
95 | #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ | |
96 | ||
97 | #define CM_REG_FUNCTRL1 0x04 | |
98 | #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ | |
99 | #define CM_ASFC_SHIFT 13 | |
100 | #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ | |
101 | #define CM_DSFC_SHIFT 10 | |
102 | #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ | |
103 | #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ | |
104 | #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ | |
105 | #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ | |
106 | #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ | |
107 | #define CM_BREQ 0x00000010 /* bus master enabled */ | |
108 | #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ | |
109 | #define CM_UART_EN 0x00000004 /* UART */ | |
110 | #define CM_JYSTK_EN 0x00000002 /* joy stick */ | |
111 | ||
112 | #define CM_REG_CHFORMAT 0x08 | |
113 | ||
114 | #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ | |
115 | #define CM_CHB3D 0x20000000 /* 4 channels */ | |
116 | ||
117 | #define CM_CHIP_MASK1 0x1f000000 | |
118 | #define CM_CHIP_037 0x01000000 | |
119 | ||
120 | #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ | |
121 | #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ | |
122 | #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ | |
123 | /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ | |
124 | ||
125 | #define CM_ADCBITLEN_MASK 0x0000C000 | |
126 | #define CM_ADCBITLEN_16 0x00000000 | |
127 | #define CM_ADCBITLEN_15 0x00004000 | |
128 | #define CM_ADCBITLEN_14 0x00008000 | |
129 | #define CM_ADCBITLEN_13 0x0000C000 | |
130 | ||
131 | #define CM_ADCDACLEN_MASK 0x00003000 | |
132 | #define CM_ADCDACLEN_060 0x00000000 | |
133 | #define CM_ADCDACLEN_066 0x00001000 | |
134 | #define CM_ADCDACLEN_130 0x00002000 | |
135 | #define CM_ADCDACLEN_280 0x00003000 | |
136 | ||
137 | #define CM_CH1_SRATE_176K 0x00000800 | |
8992e18d | 138 | #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */ |
1da177e4 LT |
139 | #define CM_CH1_SRATE_88K 0x00000400 |
140 | #define CM_CH0_SRATE_176K 0x00000200 | |
8992e18d | 141 | #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */ |
1da177e4 LT |
142 | #define CM_CH0_SRATE_88K 0x00000100 |
143 | ||
144 | #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ | |
8992e18d | 145 | #define CM_DBLSPDS 0x00000040 |
1da177e4 LT |
146 | |
147 | #define CM_CH1FMT_MASK 0x0000000C | |
148 | #define CM_CH1FMT_SHIFT 2 | |
149 | #define CM_CH0FMT_MASK 0x00000003 | |
150 | #define CM_CH0FMT_SHIFT 0 | |
151 | ||
152 | #define CM_REG_INT_HLDCLR 0x0C | |
153 | #define CM_CHIP_MASK2 0xff000000 | |
154 | #define CM_CHIP_039 0x04000000 | |
155 | #define CM_CHIP_039_6CH 0x01000000 | |
156 | #define CM_CHIP_055 0x08000000 | |
157 | #define CM_CHIP_8768 0x20000000 | |
158 | #define CM_TDMA_INT_EN 0x00040000 | |
159 | #define CM_CH1_INT_EN 0x00020000 | |
160 | #define CM_CH0_INT_EN 0x00010000 | |
161 | #define CM_INT_HOLD 0x00000002 | |
162 | #define CM_INT_CLEAR 0x00000001 | |
163 | ||
164 | #define CM_REG_INT_STATUS 0x10 | |
165 | #define CM_INTR 0x80000000 | |
166 | #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ | |
167 | #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ | |
168 | #define CM_UARTINT 0x00010000 | |
169 | #define CM_LTDMAINT 0x00008000 | |
170 | #define CM_HTDMAINT 0x00004000 | |
171 | #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ | |
172 | #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ | |
173 | #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ | |
174 | #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ | |
175 | #define CM_CH1BUSY 0x00000008 | |
176 | #define CM_CH0BUSY 0x00000004 | |
177 | #define CM_CHINT1 0x00000002 | |
178 | #define CM_CHINT0 0x00000001 | |
179 | ||
180 | #define CM_REG_LEGACY_CTRL 0x14 | |
181 | #define CM_NXCHG 0x80000000 /* h/w multi channels? */ | |
182 | #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ | |
183 | #define CM_VMPU_330 0x00000000 | |
184 | #define CM_VMPU_320 0x20000000 | |
185 | #define CM_VMPU_310 0x40000000 | |
186 | #define CM_VMPU_300 0x60000000 | |
187 | #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ | |
188 | #define CM_VSBSEL_220 0x00000000 | |
189 | #define CM_VSBSEL_240 0x04000000 | |
190 | #define CM_VSBSEL_260 0x08000000 | |
191 | #define CM_VSBSEL_280 0x0C000000 | |
192 | #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ | |
193 | #define CM_FMSEL_388 0x00000000 | |
194 | #define CM_FMSEL_3C8 0x01000000 | |
195 | #define CM_FMSEL_3E0 0x02000000 | |
196 | #define CM_FMSEL_3E8 0x03000000 | |
197 | #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ | |
198 | #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ | |
199 | #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ | |
200 | #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ | |
201 | #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ | |
202 | #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ | |
203 | ||
204 | #define CM_REG_MISC_CTRL 0x18 | |
205 | #define CM_PWD 0x80000000 | |
206 | #define CM_RESET 0x40000000 | |
207 | #define CM_SFIL_MASK 0x30000000 | |
208 | #define CM_TXVX 0x08000000 | |
209 | #define CM_N4SPK3D 0x04000000 /* 4ch output */ | |
210 | #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ | |
211 | #define CM_SPDIF48K 0x01000000 /* write */ | |
212 | #define CM_SPATUS48K 0x01000000 /* read */ | |
213 | #define CM_ENDBDAC 0x00800000 /* enable dual dac */ | |
214 | #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ | |
215 | #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ | |
216 | #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ | |
217 | #define CM_FM_EN 0x00080000 /* enalbe FM */ | |
218 | #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ | |
219 | #define CM_VIDWPDSB 0x00010000 | |
220 | #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ | |
221 | #define CM_MASK_EN 0x00004000 | |
222 | #define CM_VIDWPPRT 0x00002000 | |
223 | #define CM_SFILENB 0x00001000 | |
224 | #define CM_MMODE_MASK 0x00000E00 | |
225 | #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ | |
226 | #define CM_ENCENTER 0x00000080 | |
227 | #define CM_FLINKON 0x00000040 | |
228 | #define CM_FLINKOFF 0x00000020 | |
229 | #define CM_MIDSMP 0x00000010 | |
230 | #define CM_UPDDMA_MASK 0x0000000C | |
231 | #define CM_TWAIT_MASK 0x00000003 | |
232 | ||
233 | /* byte */ | |
234 | #define CM_REG_MIXER0 0x20 | |
235 | ||
236 | #define CM_REG_SB16_DATA 0x22 | |
237 | #define CM_REG_SB16_ADDR 0x23 | |
238 | ||
239 | #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ | |
240 | #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ | |
241 | #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ | |
242 | #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ | |
243 | ||
244 | #define CM_REG_MIXER1 0x24 | |
245 | #define CM_FMMUTE 0x80 /* mute FM */ | |
246 | #define CM_FMMUTE_SHIFT 7 | |
247 | #define CM_WSMUTE 0x40 /* mute PCM */ | |
248 | #define CM_WSMUTE_SHIFT 6 | |
249 | #define CM_SPK4 0x20 /* lin-in -> rear line out */ | |
250 | #define CM_SPK4_SHIFT 5 | |
251 | #define CM_REAR2FRONT 0x10 /* exchange rear/front */ | |
252 | #define CM_REAR2FRONT_SHIFT 4 | |
253 | #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ | |
254 | #define CM_WAVEINL_SHIFT 3 | |
255 | #define CM_WAVEINR 0x04 /* digical wave rec. right */ | |
256 | #define CM_WAVEINR_SHIFT 2 | |
257 | #define CM_X3DEN 0x02 /* 3D surround enable */ | |
258 | #define CM_X3DEN_SHIFT 1 | |
259 | #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ | |
260 | #define CM_CDPLAY_SHIFT 0 | |
261 | ||
262 | #define CM_REG_MIXER2 0x25 | |
263 | #define CM_RAUXREN 0x80 /* AUX right capture */ | |
264 | #define CM_RAUXREN_SHIFT 7 | |
265 | #define CM_RAUXLEN 0x40 /* AUX left capture */ | |
266 | #define CM_RAUXLEN_SHIFT 6 | |
267 | #define CM_VAUXRM 0x20 /* AUX right mute */ | |
268 | #define CM_VAUXRM_SHIFT 5 | |
269 | #define CM_VAUXLM 0x10 /* AUX left mute */ | |
270 | #define CM_VAUXLM_SHIFT 4 | |
271 | #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ | |
272 | #define CM_VADMIC_SHIFT 1 | |
273 | #define CM_MICGAINZ 0x01 /* mic boost */ | |
274 | #define CM_MICGAINZ_SHIFT 0 | |
275 | ||
cb60e5f5 | 276 | #define CM_REG_MIXER3 0x24 |
1da177e4 LT |
277 | #define CM_REG_AUX_VOL 0x26 |
278 | #define CM_VAUXL_MASK 0xf0 | |
279 | #define CM_VAUXR_MASK 0x0f | |
280 | ||
281 | #define CM_REG_MISC 0x27 | |
282 | #define CM_XGPO1 0x20 | |
283 | // #define CM_XGPBIO 0x04 | |
284 | #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ | |
285 | #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ | |
286 | #define CM_SPDVALID 0x02 /* spdif input valid check */ | |
287 | #define CM_DMAUTO 0x01 | |
288 | ||
289 | #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ | |
290 | /* | |
291 | * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 | |
292 | * or identical with AC97 codec? | |
293 | */ | |
294 | #define CM_REG_EXTERN_CODEC CM_REG_AC97 | |
295 | ||
296 | /* | |
297 | * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) | |
298 | */ | |
299 | #define CM_REG_MPU_PCI 0x40 | |
300 | ||
301 | /* | |
302 | * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) | |
303 | */ | |
304 | #define CM_REG_FM_PCI 0x50 | |
305 | ||
306 | /* | |
2eff7ec8 | 307 | * access from SB-mixer port |
1da177e4 LT |
308 | */ |
309 | #define CM_REG_EXTENT_IND 0xf0 | |
310 | #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ | |
311 | #define CM_VPHONE_SHIFT 5 | |
312 | #define CM_VPHOM 0x10 /* Phone mute control */ | |
313 | #define CM_VSPKM 0x08 /* Speaker mute control, default high */ | |
314 | #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ | |
315 | #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ | |
2eff7ec8 | 316 | #define CM_VADMIC3 0x01 /* Mic record boost */ |
1da177e4 LT |
317 | |
318 | /* | |
319 | * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): | |
320 | * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL | |
321 | * unit (readonly?). | |
322 | */ | |
323 | #define CM_REG_PLL 0xf8 | |
324 | ||
325 | /* | |
326 | * extended registers | |
327 | */ | |
328 | #define CM_REG_CH0_FRAME1 0x80 /* base address */ | |
329 | #define CM_REG_CH0_FRAME2 0x84 | |
330 | #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ | |
331 | #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ | |
cb60e5f5 | 332 | #define CM_REG_EXT_MISC 0x90 |
1da177e4 LT |
333 | #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ |
334 | #define CM_CHB3D8C 0x20 /* 7.1 channels support */ | |
335 | #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ | |
336 | #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ | |
337 | #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ | |
338 | #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ | |
339 | #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ | |
340 | ||
341 | /* | |
342 | * size of i/o region | |
343 | */ | |
344 | #define CM_EXTENT_CODEC 0x100 | |
345 | #define CM_EXTENT_MIDI 0x2 | |
346 | #define CM_EXTENT_SYNTH 0x4 | |
347 | ||
348 | ||
1da177e4 LT |
349 | /* |
350 | * channels for playback / capture | |
351 | */ | |
352 | #define CM_CH_PLAY 0 | |
353 | #define CM_CH_CAPT 1 | |
354 | ||
355 | /* | |
356 | * flags to check device open/close | |
357 | */ | |
358 | #define CM_OPEN_NONE 0 | |
359 | #define CM_OPEN_CH_MASK 0x01 | |
360 | #define CM_OPEN_DAC 0x10 | |
361 | #define CM_OPEN_ADC 0x20 | |
362 | #define CM_OPEN_SPDIF 0x40 | |
363 | #define CM_OPEN_MCHAN 0x80 | |
364 | #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) | |
365 | #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) | |
366 | #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) | |
367 | #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) | |
368 | #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) | |
369 | #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) | |
370 | ||
371 | ||
372 | #if CM_CH_PLAY == 1 | |
373 | #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K | |
374 | #define CM_PLAYBACK_SPDF CM_SPDF_1 | |
375 | #define CM_CAPTURE_SPDF CM_SPDF_0 | |
376 | #else | |
377 | #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K | |
378 | #define CM_PLAYBACK_SPDF CM_SPDF_0 | |
379 | #define CM_CAPTURE_SPDF CM_SPDF_1 | |
380 | #endif | |
381 | ||
382 | ||
383 | /* | |
384 | * driver data | |
385 | */ | |
386 | ||
2cbdb686 TI |
387 | struct cmipci_pcm { |
388 | struct snd_pcm_substream *substream; | |
1da177e4 LT |
389 | int running; /* dac/adc running? */ |
390 | unsigned int dma_size; /* in frames */ | |
391 | unsigned int period_size; /* in frames */ | |
392 | unsigned int offset; /* physical address of the buffer */ | |
393 | unsigned int fmt; /* format bits */ | |
394 | int ch; /* channel (0/1) */ | |
395 | unsigned int is_dac; /* is dac? */ | |
396 | int bytes_per_frame; | |
397 | int shift; | |
398 | }; | |
399 | ||
400 | /* mixer elements toggled/resumed during ac3 playback */ | |
401 | struct cmipci_mixer_auto_switches { | |
402 | const char *name; /* switch to toggle */ | |
403 | int toggle_on; /* value to change when ac3 mode */ | |
404 | }; | |
405 | static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { | |
406 | {"PCM Playback Switch", 0}, | |
407 | {"IEC958 Output Switch", 1}, | |
408 | {"IEC958 Mix Analog", 0}, | |
409 | // {"IEC958 Out To DAC", 1}, // no longer used | |
410 | {"IEC958 Loop", 0}, | |
411 | }; | |
412 | #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) | |
413 | ||
2cbdb686 TI |
414 | struct cmipci { |
415 | struct snd_card *card; | |
1da177e4 LT |
416 | |
417 | struct pci_dev *pci; | |
418 | unsigned int device; /* device ID */ | |
419 | int irq; | |
420 | ||
421 | unsigned long iobase; | |
422 | unsigned int ctrl; /* FUNCTRL0 current value */ | |
423 | ||
2cbdb686 TI |
424 | struct snd_pcm *pcm; /* DAC/ADC PCM */ |
425 | struct snd_pcm *pcm2; /* 2nd DAC */ | |
426 | struct snd_pcm *pcm_spdif; /* SPDIF */ | |
1da177e4 LT |
427 | |
428 | int chip_version; | |
429 | int max_channels; | |
1da177e4 LT |
430 | unsigned int can_ac3_sw: 1; |
431 | unsigned int can_ac3_hw: 1; | |
432 | unsigned int can_multi_ch: 1; | |
433 | unsigned int do_soft_ac3: 1; | |
434 | ||
435 | unsigned int spdif_playback_avail: 1; /* spdif ready? */ | |
436 | unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ | |
437 | int spdif_counter; /* for software AC3 */ | |
438 | ||
439 | unsigned int dig_status; | |
440 | unsigned int dig_pcm_status; | |
441 | ||
2cbdb686 | 442 | struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ |
1da177e4 LT |
443 | |
444 | int opened[2]; /* open mode */ | |
62932df8 | 445 | struct mutex open_mutex; |
1da177e4 LT |
446 | |
447 | unsigned int mixer_insensitive: 1; | |
2cbdb686 | 448 | struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; |
1da177e4 LT |
449 | int mixer_res_status[CM_SAVED_MIXERS]; |
450 | ||
2cbdb686 | 451 | struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ |
1da177e4 LT |
452 | |
453 | /* external MIDI */ | |
2cbdb686 | 454 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
455 | |
456 | #ifdef SUPPORT_JOYSTICK | |
457 | struct gameport *gameport; | |
458 | #endif | |
459 | ||
460 | spinlock_t reg_lock; | |
cb60e5f5 TI |
461 | |
462 | #ifdef CONFIG_PM | |
463 | unsigned int saved_regs[0x20]; | |
464 | unsigned char saved_mixers[0x20]; | |
465 | #endif | |
1da177e4 LT |
466 | }; |
467 | ||
468 | ||
469 | /* read/write operations for dword register */ | |
2cbdb686 | 470 | static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) |
1da177e4 LT |
471 | { |
472 | outl(data, cm->iobase + cmd); | |
473 | } | |
77933d72 | 474 | |
2cbdb686 | 475 | static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
476 | { |
477 | return inl(cm->iobase + cmd); | |
478 | } | |
479 | ||
480 | /* read/write operations for word register */ | |
2cbdb686 | 481 | static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) |
1da177e4 LT |
482 | { |
483 | outw(data, cm->iobase + cmd); | |
484 | } | |
77933d72 | 485 | |
2cbdb686 | 486 | static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
487 | { |
488 | return inw(cm->iobase + cmd); | |
489 | } | |
490 | ||
491 | /* read/write operations for byte register */ | |
2cbdb686 | 492 | static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) |
1da177e4 LT |
493 | { |
494 | outb(data, cm->iobase + cmd); | |
495 | } | |
496 | ||
2cbdb686 | 497 | static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
498 | { |
499 | return inb(cm->iobase + cmd); | |
500 | } | |
501 | ||
502 | /* bit operations for dword register */ | |
2cbdb686 | 503 | static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 504 | { |
01d25d46 TI |
505 | unsigned int val, oval; |
506 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 507 | val |= flag; |
01d25d46 TI |
508 | if (val == oval) |
509 | return 0; | |
1da177e4 | 510 | outl(val, cm->iobase + cmd); |
01d25d46 | 511 | return 1; |
1da177e4 LT |
512 | } |
513 | ||
2cbdb686 | 514 | static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 515 | { |
01d25d46 TI |
516 | unsigned int val, oval; |
517 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 518 | val &= ~flag; |
01d25d46 TI |
519 | if (val == oval) |
520 | return 0; | |
1da177e4 | 521 | outl(val, cm->iobase + cmd); |
01d25d46 | 522 | return 1; |
1da177e4 LT |
523 | } |
524 | ||
1da177e4 | 525 | /* bit operations for byte register */ |
2cbdb686 | 526 | static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 527 | { |
01d25d46 TI |
528 | unsigned char val, oval; |
529 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 530 | val |= flag; |
01d25d46 TI |
531 | if (val == oval) |
532 | return 0; | |
1da177e4 | 533 | outb(val, cm->iobase + cmd); |
01d25d46 | 534 | return 1; |
1da177e4 LT |
535 | } |
536 | ||
2cbdb686 | 537 | static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 538 | { |
01d25d46 TI |
539 | unsigned char val, oval; |
540 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 541 | val &= ~flag; |
01d25d46 TI |
542 | if (val == oval) |
543 | return 0; | |
1da177e4 | 544 | outb(val, cm->iobase + cmd); |
01d25d46 | 545 | return 1; |
1da177e4 | 546 | } |
1da177e4 LT |
547 | |
548 | ||
549 | /* | |
550 | * PCM interface | |
551 | */ | |
552 | ||
553 | /* | |
554 | * calculate frequency | |
555 | */ | |
556 | ||
557 | static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; | |
558 | ||
559 | static unsigned int snd_cmipci_rate_freq(unsigned int rate) | |
560 | { | |
561 | unsigned int i; | |
562 | for (i = 0; i < ARRAY_SIZE(rates); i++) { | |
563 | if (rates[i] == rate) | |
564 | return i; | |
565 | } | |
566 | snd_BUG(); | |
567 | return 0; | |
568 | } | |
569 | ||
570 | #ifdef USE_VAR48KRATE | |
571 | /* | |
572 | * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) | |
573 | * does it this way .. maybe not. Never get any information from C-Media about | |
574 | * that <werner@suse.de>. | |
575 | */ | |
576 | static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) | |
577 | { | |
578 | unsigned int delta, tolerance; | |
579 | int xm, xn, xr; | |
580 | ||
581 | for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) | |
582 | rate <<= 1; | |
583 | *n = -1; | |
584 | if (*r > 0xff) | |
585 | goto out; | |
586 | tolerance = rate*CM_TOLERANCE_RATE; | |
587 | ||
588 | for (xn = (1+2); xn < (0x1f+2); xn++) { | |
589 | for (xm = (1+2); xm < (0xff+2); xm++) { | |
590 | xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; | |
591 | ||
592 | if (xr < rate) | |
593 | delta = rate - xr; | |
594 | else | |
595 | delta = xr - rate; | |
596 | ||
597 | /* | |
598 | * If we found one, remember this, | |
599 | * and try to find a closer one | |
600 | */ | |
601 | if (delta < tolerance) { | |
602 | tolerance = delta; | |
603 | *m = xm - 2; | |
604 | *n = xn - 2; | |
605 | } | |
606 | } | |
607 | } | |
608 | out: | |
609 | return (*n > -1); | |
610 | } | |
611 | ||
612 | /* | |
613 | * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff | |
614 | * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen | |
615 | * at the register CM_REG_FUNCTRL1 (0x04). | |
616 | * Problem: other ways are also possible (any information about that?) | |
617 | */ | |
2cbdb686 | 618 | static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) |
1da177e4 LT |
619 | { |
620 | unsigned int reg = CM_REG_PLL + slot; | |
621 | /* | |
622 | * Guess that this programs at reg. 0x04 the pos 15:13/12:10 | |
623 | * for DSFC/ASFC (000 upto 111). | |
624 | */ | |
625 | ||
626 | /* FIXME: Init (Do we've to set an other register first before programming?) */ | |
627 | ||
628 | /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ | |
629 | snd_cmipci_write_b(cm, reg, rate>>8); | |
630 | snd_cmipci_write_b(cm, reg, rate&0xff); | |
631 | ||
632 | /* FIXME: Setup (Do we've to set an other register first to enable this?) */ | |
633 | } | |
634 | #endif /* USE_VAR48KRATE */ | |
635 | ||
2cbdb686 TI |
636 | static int snd_cmipci_hw_params(struct snd_pcm_substream *substream, |
637 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
638 | { |
639 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
640 | } | |
641 | ||
2cbdb686 TI |
642 | static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, |
643 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 644 | { |
2cbdb686 | 645 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 | 646 | if (params_channels(hw_params) > 2) { |
62932df8 | 647 | mutex_lock(&cm->open_mutex); |
1da177e4 | 648 | if (cm->opened[CM_CH_PLAY]) { |
62932df8 | 649 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
650 | return -EBUSY; |
651 | } | |
652 | /* reserve the channel A */ | |
653 | cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; | |
62932df8 | 654 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
655 | } |
656 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
657 | } | |
658 | ||
2cbdb686 | 659 | static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) |
1da177e4 LT |
660 | { |
661 | int reset = CM_RST_CH0 << (cm->channel[ch].ch); | |
662 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
663 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
664 | udelay(10); | |
665 | } | |
666 | ||
2cbdb686 | 667 | static int snd_cmipci_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
668 | { |
669 | return snd_pcm_lib_free_pages(substream); | |
670 | } | |
671 | ||
672 | ||
673 | /* | |
674 | */ | |
675 | ||
676 | static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; | |
2cbdb686 | 677 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { |
1da177e4 LT |
678 | .count = 3, |
679 | .list = hw_channels, | |
680 | .mask = 0, | |
681 | }; | |
2cbdb686 | 682 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { |
1da177e4 LT |
683 | .count = 5, |
684 | .list = hw_channels, | |
685 | .mask = 0, | |
686 | }; | |
2cbdb686 | 687 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { |
1da177e4 LT |
688 | .count = 6, |
689 | .list = hw_channels, | |
690 | .mask = 0, | |
691 | }; | |
692 | ||
2cbdb686 | 693 | static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) |
1da177e4 LT |
694 | { |
695 | if (channels > 2) { | |
696 | if (! cm->can_multi_ch) | |
697 | return -EINVAL; | |
698 | if (rec->fmt != 0x03) /* stereo 16bit only */ | |
699 | return -EINVAL; | |
700 | ||
701 | spin_lock_irq(&cm->reg_lock); | |
702 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); | |
703 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
704 | if (channels > 4) { | |
705 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
706 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
707 | } else { | |
708 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
709 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
710 | } | |
711 | if (channels >= 6) { | |
712 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
713 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
714 | } else { | |
715 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
716 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
717 | } | |
718 | if (cm->chip_version == 68) { | |
719 | if (channels == 8) { | |
720 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); | |
721 | } else { | |
722 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); | |
723 | } | |
724 | } | |
725 | spin_unlock_irq(&cm->reg_lock); | |
726 | ||
727 | } else { | |
728 | if (cm->can_multi_ch) { | |
729 | spin_lock_irq(&cm->reg_lock); | |
730 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); | |
731 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
732 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
733 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
734 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
735 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
736 | spin_unlock_irq(&cm->reg_lock); | |
737 | } | |
738 | } | |
739 | return 0; | |
740 | } | |
741 | ||
742 | ||
743 | /* | |
744 | * prepare playback/capture channel | |
745 | * channel to be used must have been set in rec->ch. | |
746 | */ | |
2cbdb686 TI |
747 | static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, |
748 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
749 | { |
750 | unsigned int reg, freq, val; | |
2cbdb686 | 751 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
752 | |
753 | rec->fmt = 0; | |
754 | rec->shift = 0; | |
755 | if (snd_pcm_format_width(runtime->format) >= 16) { | |
756 | rec->fmt |= 0x02; | |
757 | if (snd_pcm_format_width(runtime->format) > 16) | |
758 | rec->shift++; /* 24/32bit */ | |
759 | } | |
760 | if (runtime->channels > 1) | |
761 | rec->fmt |= 0x01; | |
762 | if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { | |
763 | snd_printd("cannot set dac channels\n"); | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
767 | rec->offset = runtime->dma_addr; | |
768 | /* buffer and period sizes in frame */ | |
769 | rec->dma_size = runtime->buffer_size << rec->shift; | |
770 | rec->period_size = runtime->period_size << rec->shift; | |
771 | if (runtime->channels > 2) { | |
772 | /* multi-channels */ | |
773 | rec->dma_size = (rec->dma_size * runtime->channels) / 2; | |
774 | rec->period_size = (rec->period_size * runtime->channels) / 2; | |
775 | } | |
776 | ||
777 | spin_lock_irq(&cm->reg_lock); | |
778 | ||
779 | /* set buffer address */ | |
780 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
781 | snd_cmipci_write(cm, reg, rec->offset); | |
782 | /* program sample counts */ | |
783 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
784 | snd_cmipci_write_w(cm, reg, rec->dma_size - 1); | |
785 | snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); | |
786 | ||
787 | /* set adc/dac flag */ | |
788 | val = rec->ch ? CM_CHADC1 : CM_CHADC0; | |
789 | if (rec->is_dac) | |
790 | cm->ctrl &= ~val; | |
791 | else | |
792 | cm->ctrl |= val; | |
793 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
794 | //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); | |
795 | ||
796 | /* set sample rate */ | |
797 | freq = snd_cmipci_rate_freq(runtime->rate); | |
798 | val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); | |
799 | if (rec->ch) { | |
800 | val &= ~CM_ASFC_MASK; | |
801 | val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; | |
802 | } else { | |
803 | val &= ~CM_DSFC_MASK; | |
804 | val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; | |
805 | } | |
806 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); | |
807 | //snd_printd("cmipci: functrl1 = %08x\n", val); | |
808 | ||
809 | /* set format */ | |
810 | val = snd_cmipci_read(cm, CM_REG_CHFORMAT); | |
811 | if (rec->ch) { | |
812 | val &= ~CM_CH1FMT_MASK; | |
813 | val |= rec->fmt << CM_CH1FMT_SHIFT; | |
814 | } else { | |
815 | val &= ~CM_CH0FMT_MASK; | |
816 | val |= rec->fmt << CM_CH0FMT_SHIFT; | |
817 | } | |
8992e18d CL |
818 | if (cm->chip_version == 68) { |
819 | if (runtime->rate == 88200) | |
820 | val |= CM_CH0_SRATE_88K << (rec->ch * 2); | |
821 | else | |
822 | val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2)); | |
823 | if (runtime->rate == 96000) | |
824 | val |= CM_CH0_SRATE_96K << (rec->ch * 2); | |
825 | else | |
826 | val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2)); | |
827 | } | |
1da177e4 LT |
828 | snd_cmipci_write(cm, CM_REG_CHFORMAT, val); |
829 | //snd_printd("cmipci: chformat = %08x\n", val); | |
830 | ||
831 | rec->running = 0; | |
832 | spin_unlock_irq(&cm->reg_lock); | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | /* | |
838 | * PCM trigger/stop | |
839 | */ | |
2cbdb686 TI |
840 | static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, |
841 | struct snd_pcm_substream *substream, int cmd) | |
1da177e4 LT |
842 | { |
843 | unsigned int inthld, chen, reset, pause; | |
844 | int result = 0; | |
845 | ||
846 | inthld = CM_CH0_INT_EN << rec->ch; | |
847 | chen = CM_CHEN0 << rec->ch; | |
848 | reset = CM_RST_CH0 << rec->ch; | |
849 | pause = CM_PAUSE0 << rec->ch; | |
850 | ||
851 | spin_lock(&cm->reg_lock); | |
852 | switch (cmd) { | |
853 | case SNDRV_PCM_TRIGGER_START: | |
854 | rec->running = 1; | |
855 | /* set interrupt */ | |
856 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
857 | cm->ctrl |= chen; | |
858 | /* enable channel */ | |
859 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
860 | //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); | |
861 | break; | |
862 | case SNDRV_PCM_TRIGGER_STOP: | |
863 | rec->running = 0; | |
864 | /* disable interrupt */ | |
865 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
866 | /* reset */ | |
867 | cm->ctrl &= ~chen; | |
868 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
869 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
870 | break; | |
871 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
cb60e5f5 | 872 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
873 | cm->ctrl |= pause; |
874 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
875 | break; | |
876 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
cb60e5f5 | 877 | case SNDRV_PCM_TRIGGER_RESUME: |
1da177e4 LT |
878 | cm->ctrl &= ~pause; |
879 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
880 | break; | |
881 | default: | |
882 | result = -EINVAL; | |
883 | break; | |
884 | } | |
885 | spin_unlock(&cm->reg_lock); | |
886 | return result; | |
887 | } | |
888 | ||
889 | /* | |
890 | * return the current pointer | |
891 | */ | |
2cbdb686 TI |
892 | static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, |
893 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
894 | { |
895 | size_t ptr; | |
896 | unsigned int reg; | |
897 | if (!rec->running) | |
898 | return 0; | |
899 | #if 1 // this seems better.. | |
900 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
901 | ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); | |
902 | ptr >>= rec->shift; | |
903 | #else | |
904 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
905 | ptr = snd_cmipci_read(cm, reg) - rec->offset; | |
906 | ptr = bytes_to_frames(substream->runtime, ptr); | |
907 | #endif | |
908 | if (substream->runtime->channels > 2) | |
909 | ptr = (ptr * 2) / substream->runtime->channels; | |
910 | return ptr; | |
911 | } | |
912 | ||
913 | /* | |
914 | * playback | |
915 | */ | |
916 | ||
2cbdb686 | 917 | static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
918 | int cmd) |
919 | { | |
2cbdb686 | 920 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
921 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); |
922 | } | |
923 | ||
2cbdb686 | 924 | static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 925 | { |
2cbdb686 | 926 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
927 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); |
928 | } | |
929 | ||
930 | ||
931 | ||
932 | /* | |
933 | * capture | |
934 | */ | |
935 | ||
2cbdb686 | 936 | static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
937 | int cmd) |
938 | { | |
2cbdb686 | 939 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
940 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); |
941 | } | |
942 | ||
2cbdb686 | 943 | static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 944 | { |
2cbdb686 | 945 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
946 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); |
947 | } | |
948 | ||
949 | ||
950 | /* | |
951 | * hw preparation for spdif | |
952 | */ | |
953 | ||
2cbdb686 TI |
954 | static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, |
955 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
956 | { |
957 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
958 | uinfo->count = 1; | |
959 | return 0; | |
960 | } | |
961 | ||
2cbdb686 TI |
962 | static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, |
963 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 964 | { |
2cbdb686 | 965 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
966 | int i; |
967 | ||
968 | spin_lock_irq(&chip->reg_lock); | |
969 | for (i = 0; i < 4; i++) | |
970 | ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; | |
971 | spin_unlock_irq(&chip->reg_lock); | |
972 | return 0; | |
973 | } | |
974 | ||
2cbdb686 TI |
975 | static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, |
976 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 977 | { |
2cbdb686 | 978 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
979 | int i, change; |
980 | unsigned int val; | |
981 | ||
982 | val = 0; | |
983 | spin_lock_irq(&chip->reg_lock); | |
984 | for (i = 0; i < 4; i++) | |
985 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
986 | change = val != chip->dig_status; | |
987 | chip->dig_status = val; | |
988 | spin_unlock_irq(&chip->reg_lock); | |
989 | return change; | |
990 | } | |
991 | ||
2cbdb686 | 992 | static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata = |
1da177e4 LT |
993 | { |
994 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
995 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
996 | .info = snd_cmipci_spdif_default_info, | |
997 | .get = snd_cmipci_spdif_default_get, | |
998 | .put = snd_cmipci_spdif_default_put | |
999 | }; | |
1000 | ||
2cbdb686 TI |
1001 | static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, |
1002 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1003 | { |
1004 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1005 | uinfo->count = 1; | |
1006 | return 0; | |
1007 | } | |
1008 | ||
2cbdb686 TI |
1009 | static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, |
1010 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
1011 | { |
1012 | ucontrol->value.iec958.status[0] = 0xff; | |
1013 | ucontrol->value.iec958.status[1] = 0xff; | |
1014 | ucontrol->value.iec958.status[2] = 0xff; | |
1015 | ucontrol->value.iec958.status[3] = 0xff; | |
1016 | return 0; | |
1017 | } | |
1018 | ||
2cbdb686 | 1019 | static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata = |
1da177e4 LT |
1020 | { |
1021 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 1022 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1023 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
1024 | .info = snd_cmipci_spdif_mask_info, | |
1025 | .get = snd_cmipci_spdif_mask_get, | |
1026 | }; | |
1027 | ||
2cbdb686 TI |
1028 | static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, |
1029 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1030 | { |
1031 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1032 | uinfo->count = 1; | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2cbdb686 TI |
1036 | static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, |
1037 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1038 | { |
2cbdb686 | 1039 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1040 | int i; |
1041 | ||
1042 | spin_lock_irq(&chip->reg_lock); | |
1043 | for (i = 0; i < 4; i++) | |
1044 | ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; | |
1045 | spin_unlock_irq(&chip->reg_lock); | |
1046 | return 0; | |
1047 | } | |
1048 | ||
2cbdb686 TI |
1049 | static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, |
1050 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1051 | { |
2cbdb686 | 1052 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1053 | int i, change; |
1054 | unsigned int val; | |
1055 | ||
1056 | val = 0; | |
1057 | spin_lock_irq(&chip->reg_lock); | |
1058 | for (i = 0; i < 4; i++) | |
1059 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
1060 | change = val != chip->dig_pcm_status; | |
1061 | chip->dig_pcm_status = val; | |
1062 | spin_unlock_irq(&chip->reg_lock); | |
1063 | return change; | |
1064 | } | |
1065 | ||
2cbdb686 | 1066 | static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata = |
1da177e4 LT |
1067 | { |
1068 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
1069 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1070 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
1071 | .info = snd_cmipci_spdif_stream_info, | |
1072 | .get = snd_cmipci_spdif_stream_get, | |
1073 | .put = snd_cmipci_spdif_stream_put | |
1074 | }; | |
1075 | ||
1076 | /* | |
1077 | */ | |
1078 | ||
1079 | /* save mixer setting and mute for AC3 playback */ | |
2cbdb686 | 1080 | static int save_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1081 | { |
1082 | if (! cm->mixer_insensitive) { | |
2cbdb686 | 1083 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1084 | unsigned int i; |
1085 | ||
1086 | val = kmalloc(sizeof(*val), GFP_ATOMIC); | |
1087 | if (!val) | |
1088 | return -ENOMEM; | |
1089 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1090 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1091 | if (ctl) { |
1092 | int event; | |
1093 | memset(val, 0, sizeof(*val)); | |
1094 | ctl->get(ctl, val); | |
1095 | cm->mixer_res_status[i] = val->value.integer.value[0]; | |
1096 | val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; | |
1097 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1098 | if (cm->mixer_res_status[i] != val->value.integer.value[0]) { | |
1099 | ctl->put(ctl, val); /* toggle */ | |
1100 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1101 | } | |
1102 | ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1103 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1104 | } | |
1105 | } | |
1106 | kfree(val); | |
1107 | cm->mixer_insensitive = 1; | |
1108 | } | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | ||
1113 | /* restore the previously saved mixer status */ | |
2cbdb686 | 1114 | static void restore_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1115 | { |
1116 | if (cm->mixer_insensitive) { | |
2cbdb686 | 1117 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1118 | unsigned int i; |
1119 | ||
1120 | val = kmalloc(sizeof(*val), GFP_KERNEL); | |
1121 | if (!val) | |
1122 | return; | |
1123 | cm->mixer_insensitive = 0; /* at first clear this; | |
1124 | otherwise the changes will be ignored */ | |
1125 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1126 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1127 | if (ctl) { |
1128 | int event; | |
1129 | ||
1130 | memset(val, 0, sizeof(*val)); | |
1131 | ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1132 | ctl->get(ctl, val); | |
1133 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1134 | if (val->value.integer.value[0] != cm->mixer_res_status[i]) { | |
1135 | val->value.integer.value[0] = cm->mixer_res_status[i]; | |
1136 | ctl->put(ctl, val); | |
1137 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1138 | } | |
1139 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1140 | } | |
1141 | } | |
1142 | kfree(val); | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | /* spinlock held! */ | |
2cbdb686 | 1147 | static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) |
1da177e4 LT |
1148 | { |
1149 | if (do_ac3) { | |
1150 | /* AC3EN for 037 */ | |
1151 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1152 | /* AC3EN for 039 */ | |
1153 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1154 | ||
1155 | if (cm->can_ac3_hw) { | |
1156 | /* SPD24SEL for 037, 0x02 */ | |
1157 | /* SPD24SEL for 039, 0x20, but cannot be set */ | |
1158 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1159 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1160 | } else { /* can_ac3_sw */ | |
1161 | /* SPD32SEL for 037 & 039, 0x20 */ | |
1162 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1163 | /* set 176K sample rate to fix 033 HW bug */ | |
1164 | if (cm->chip_version == 33) { | |
1165 | if (rate >= 48000) { | |
1166 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1167 | } else { | |
1168 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1169 | } | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | } else { | |
1174 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1175 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1176 | ||
1177 | if (cm->can_ac3_hw) { | |
1178 | /* chip model >= 37 */ | |
1179 | if (snd_pcm_format_width(subs->runtime->format) > 16) { | |
1180 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1181 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1182 | } else { | |
1183 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1184 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1185 | } | |
1186 | } else { | |
1187 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1188 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1189 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1190 | } | |
1191 | } | |
1192 | } | |
1193 | ||
2cbdb686 | 1194 | static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) |
1da177e4 LT |
1195 | { |
1196 | int rate, err; | |
1197 | ||
1198 | rate = subs->runtime->rate; | |
1199 | ||
1200 | if (up && do_ac3) | |
1201 | if ((err = save_mixer_state(cm)) < 0) | |
1202 | return err; | |
1203 | ||
1204 | spin_lock_irq(&cm->reg_lock); | |
1205 | cm->spdif_playback_avail = up; | |
1206 | if (up) { | |
1207 | /* they are controlled via "IEC958 Output Switch" */ | |
1208 | /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1209 | /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
1210 | if (cm->spdif_playback_enabled) | |
1211 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
1212 | setup_ac3(cm, subs, do_ac3, rate); | |
1213 | ||
8992e18d | 1214 | if (rate == 48000 || rate == 96000) |
1da177e4 LT |
1215 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); |
1216 | else | |
1217 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); | |
8992e18d CL |
1218 | if (rate > 48000) |
1219 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1220 | else | |
1221 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1da177e4 LT |
1222 | } else { |
1223 | /* they are controlled via "IEC958 Output Switch" */ | |
1224 | /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1225 | /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
8992e18d | 1226 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); |
1da177e4 LT |
1227 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); |
1228 | setup_ac3(cm, subs, 0, 0); | |
1229 | } | |
1230 | spin_unlock_irq(&cm->reg_lock); | |
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | ||
1235 | /* | |
1236 | * preparation | |
1237 | */ | |
1238 | ||
1239 | /* playback - enable spdif only on the certain condition */ | |
2cbdb686 | 1240 | static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1241 | { |
2cbdb686 | 1242 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1243 | int rate = substream->runtime->rate; |
1244 | int err, do_spdif, do_ac3 = 0; | |
1245 | ||
8992e18d | 1246 | do_spdif = (rate >= 44100 && |
1da177e4 LT |
1247 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && |
1248 | substream->runtime->channels == 2); | |
1249 | if (do_spdif && cm->can_ac3_hw) | |
1250 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
1251 | if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) | |
1252 | return err; | |
1253 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1254 | } | |
1255 | ||
1256 | /* playback (via device #2) - enable spdif always */ | |
2cbdb686 | 1257 | static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1258 | { |
2cbdb686 | 1259 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1260 | int err, do_ac3; |
1261 | ||
1262 | if (cm->can_ac3_hw) | |
1263 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
1264 | else | |
1265 | do_ac3 = 1; /* doesn't matter */ | |
1266 | if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) | |
1267 | return err; | |
1268 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1269 | } | |
1270 | ||
2cbdb686 | 1271 | static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1272 | { |
2cbdb686 | 1273 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1274 | setup_spdif_playback(cm, substream, 0, 0); |
1275 | restore_mixer_state(cm); | |
1276 | return snd_cmipci_hw_free(substream); | |
1277 | } | |
1278 | ||
1279 | /* capture */ | |
2cbdb686 | 1280 | static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1281 | { |
2cbdb686 | 1282 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1283 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); |
1284 | } | |
1285 | ||
1286 | /* capture with spdif (via device #2) */ | |
2cbdb686 | 1287 | static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1288 | { |
2cbdb686 | 1289 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1290 | |
1291 | spin_lock_irq(&cm->reg_lock); | |
1292 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
1293 | spin_unlock_irq(&cm->reg_lock); | |
1294 | ||
1295 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); | |
1296 | } | |
1297 | ||
2cbdb686 | 1298 | static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) |
1da177e4 | 1299 | { |
2cbdb686 | 1300 | struct cmipci *cm = snd_pcm_substream_chip(subs); |
1da177e4 LT |
1301 | |
1302 | spin_lock_irq(&cm->reg_lock); | |
1303 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
1304 | spin_unlock_irq(&cm->reg_lock); | |
1305 | ||
1306 | return snd_cmipci_hw_free(subs); | |
1307 | } | |
1308 | ||
1309 | ||
1310 | /* | |
1311 | * interrupt handler | |
1312 | */ | |
7d12e780 | 1313 | static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) |
1da177e4 | 1314 | { |
2cbdb686 | 1315 | struct cmipci *cm = dev_id; |
1da177e4 LT |
1316 | unsigned int status, mask = 0; |
1317 | ||
1318 | /* fastpath out, to ease interrupt sharing */ | |
1319 | status = snd_cmipci_read(cm, CM_REG_INT_STATUS); | |
1320 | if (!(status & CM_INTR)) | |
1321 | return IRQ_NONE; | |
1322 | ||
1323 | /* acknowledge interrupt */ | |
1324 | spin_lock(&cm->reg_lock); | |
1325 | if (status & CM_CHINT0) | |
1326 | mask |= CM_CH0_INT_EN; | |
1327 | if (status & CM_CHINT1) | |
1328 | mask |= CM_CH1_INT_EN; | |
1329 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1330 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1331 | spin_unlock(&cm->reg_lock); | |
1332 | ||
1333 | if (cm->rmidi && (status & CM_UARTINT)) | |
7d12e780 | 1334 | snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); |
1da177e4 LT |
1335 | |
1336 | if (cm->pcm) { | |
1337 | if ((status & CM_CHINT0) && cm->channel[0].running) | |
1338 | snd_pcm_period_elapsed(cm->channel[0].substream); | |
1339 | if ((status & CM_CHINT1) && cm->channel[1].running) | |
1340 | snd_pcm_period_elapsed(cm->channel[1].substream); | |
1341 | } | |
1342 | return IRQ_HANDLED; | |
1343 | } | |
1344 | ||
1345 | /* | |
1346 | * h/w infos | |
1347 | */ | |
1348 | ||
1349 | /* playback on channel A */ | |
2cbdb686 | 1350 | static struct snd_pcm_hardware snd_cmipci_playback = |
1da177e4 LT |
1351 | { |
1352 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1353 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1354 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1355 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1356 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1357 | .rate_min = 5512, | |
1358 | .rate_max = 48000, | |
1359 | .channels_min = 1, | |
1360 | .channels_max = 2, | |
1361 | .buffer_bytes_max = (128*1024), | |
1362 | .period_bytes_min = 64, | |
1363 | .period_bytes_max = (128*1024), | |
1364 | .periods_min = 2, | |
1365 | .periods_max = 1024, | |
1366 | .fifo_size = 0, | |
1367 | }; | |
1368 | ||
1369 | /* capture on channel B */ | |
2cbdb686 | 1370 | static struct snd_pcm_hardware snd_cmipci_capture = |
1da177e4 LT |
1371 | { |
1372 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1373 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1374 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1375 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1376 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1377 | .rate_min = 5512, | |
1378 | .rate_max = 48000, | |
1379 | .channels_min = 1, | |
1380 | .channels_max = 2, | |
1381 | .buffer_bytes_max = (128*1024), | |
1382 | .period_bytes_min = 64, | |
1383 | .period_bytes_max = (128*1024), | |
1384 | .periods_min = 2, | |
1385 | .periods_max = 1024, | |
1386 | .fifo_size = 0, | |
1387 | }; | |
1388 | ||
1389 | /* playback on channel B - stereo 16bit only? */ | |
2cbdb686 | 1390 | static struct snd_pcm_hardware snd_cmipci_playback2 = |
1da177e4 LT |
1391 | { |
1392 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1393 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1394 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1395 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1396 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1397 | .rate_min = 5512, | |
1398 | .rate_max = 48000, | |
1399 | .channels_min = 2, | |
1400 | .channels_max = 2, | |
1401 | .buffer_bytes_max = (128*1024), | |
1402 | .period_bytes_min = 64, | |
1403 | .period_bytes_max = (128*1024), | |
1404 | .periods_min = 2, | |
1405 | .periods_max = 1024, | |
1406 | .fifo_size = 0, | |
1407 | }; | |
1408 | ||
1409 | /* spdif playback on channel A */ | |
2cbdb686 | 1410 | static struct snd_pcm_hardware snd_cmipci_playback_spdif = |
1da177e4 LT |
1411 | { |
1412 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1413 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1414 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1415 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1416 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1417 | .rate_min = 44100, | |
1418 | .rate_max = 48000, | |
1419 | .channels_min = 2, | |
1420 | .channels_max = 2, | |
1421 | .buffer_bytes_max = (128*1024), | |
1422 | .period_bytes_min = 64, | |
1423 | .period_bytes_max = (128*1024), | |
1424 | .periods_min = 2, | |
1425 | .periods_max = 1024, | |
1426 | .fifo_size = 0, | |
1427 | }; | |
1428 | ||
1429 | /* spdif playback on channel A (32bit, IEC958 subframes) */ | |
2cbdb686 | 1430 | static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = |
1da177e4 LT |
1431 | { |
1432 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1433 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1434 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1435 | .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, |
1436 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1437 | .rate_min = 44100, | |
1438 | .rate_max = 48000, | |
1439 | .channels_min = 2, | |
1440 | .channels_max = 2, | |
1441 | .buffer_bytes_max = (128*1024), | |
1442 | .period_bytes_min = 64, | |
1443 | .period_bytes_max = (128*1024), | |
1444 | .periods_min = 2, | |
1445 | .periods_max = 1024, | |
1446 | .fifo_size = 0, | |
1447 | }; | |
1448 | ||
1449 | /* spdif capture on channel B */ | |
2cbdb686 | 1450 | static struct snd_pcm_hardware snd_cmipci_capture_spdif = |
1da177e4 LT |
1451 | { |
1452 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1453 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1454 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1455 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1456 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1457 | .rate_min = 44100, | |
1458 | .rate_max = 48000, | |
1459 | .channels_min = 2, | |
1460 | .channels_max = 2, | |
1461 | .buffer_bytes_max = (128*1024), | |
1462 | .period_bytes_min = 64, | |
1463 | .period_bytes_max = (128*1024), | |
1464 | .periods_min = 2, | |
1465 | .periods_max = 1024, | |
1466 | .fifo_size = 0, | |
1467 | }; | |
1468 | ||
1469 | /* | |
1470 | * check device open/close | |
1471 | */ | |
2cbdb686 | 1472 | static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) |
1da177e4 LT |
1473 | { |
1474 | int ch = mode & CM_OPEN_CH_MASK; | |
1475 | ||
1476 | /* FIXME: a file should wait until the device becomes free | |
1477 | * when it's opened on blocking mode. however, since the current | |
1478 | * pcm framework doesn't pass file pointer before actually opened, | |
1479 | * we can't know whether blocking mode or not in open callback.. | |
1480 | */ | |
62932df8 | 1481 | mutex_lock(&cm->open_mutex); |
1da177e4 | 1482 | if (cm->opened[ch]) { |
62932df8 | 1483 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1484 | return -EBUSY; |
1485 | } | |
1486 | cm->opened[ch] = mode; | |
1487 | cm->channel[ch].substream = subs; | |
1488 | if (! (mode & CM_OPEN_DAC)) { | |
1489 | /* disable dual DAC mode */ | |
1490 | cm->channel[ch].is_dac = 0; | |
1491 | spin_lock_irq(&cm->reg_lock); | |
1492 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1493 | spin_unlock_irq(&cm->reg_lock); | |
1494 | } | |
62932df8 | 1495 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1496 | return 0; |
1497 | } | |
1498 | ||
2cbdb686 | 1499 | static void close_device_check(struct cmipci *cm, int mode) |
1da177e4 LT |
1500 | { |
1501 | int ch = mode & CM_OPEN_CH_MASK; | |
1502 | ||
62932df8 | 1503 | mutex_lock(&cm->open_mutex); |
1da177e4 LT |
1504 | if (cm->opened[ch] == mode) { |
1505 | if (cm->channel[ch].substream) { | |
1506 | snd_cmipci_ch_reset(cm, ch); | |
1507 | cm->channel[ch].running = 0; | |
1508 | cm->channel[ch].substream = NULL; | |
1509 | } | |
1510 | cm->opened[ch] = 0; | |
1511 | if (! cm->channel[ch].is_dac) { | |
1512 | /* enable dual DAC mode again */ | |
1513 | cm->channel[ch].is_dac = 1; | |
1514 | spin_lock_irq(&cm->reg_lock); | |
1515 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1516 | spin_unlock_irq(&cm->reg_lock); | |
1517 | } | |
1518 | } | |
62932df8 | 1519 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1520 | } |
1521 | ||
1522 | /* | |
1523 | */ | |
1524 | ||
2cbdb686 | 1525 | static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1526 | { |
2cbdb686 TI |
1527 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1528 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1529 | int err; |
1530 | ||
1531 | if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) | |
1532 | return err; | |
1533 | runtime->hw = snd_cmipci_playback; | |
8992e18d CL |
1534 | if (cm->chip_version == 68) { |
1535 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1536 | SNDRV_PCM_RATE_96000; | |
1537 | runtime->hw.rate_max = 96000; | |
1538 | } | |
1da177e4 LT |
1539 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); |
1540 | cm->dig_pcm_status = cm->dig_status; | |
1541 | return 0; | |
1542 | } | |
1543 | ||
2cbdb686 | 1544 | static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1545 | { |
2cbdb686 TI |
1546 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1547 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1548 | int err; |
1549 | ||
1550 | if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) | |
1551 | return err; | |
1552 | runtime->hw = snd_cmipci_capture; | |
1553 | if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording | |
1554 | runtime->hw.rate_min = 41000; | |
1555 | runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; | |
1556 | } | |
1557 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1558 | return 0; | |
1559 | } | |
1560 | ||
2cbdb686 | 1561 | static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1562 | { |
2cbdb686 TI |
1563 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1564 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1565 | int err; |
1566 | ||
1567 | if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ | |
1568 | return err; | |
1569 | runtime->hw = snd_cmipci_playback2; | |
62932df8 | 1570 | mutex_lock(&cm->open_mutex); |
1da177e4 LT |
1571 | if (! cm->opened[CM_CH_PLAY]) { |
1572 | if (cm->can_multi_ch) { | |
1573 | runtime->hw.channels_max = cm->max_channels; | |
1574 | if (cm->max_channels == 4) | |
1575 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); | |
1576 | else if (cm->max_channels == 6) | |
1577 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); | |
1578 | else if (cm->max_channels == 8) | |
1579 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); | |
1580 | } | |
8992e18d CL |
1581 | if (cm->chip_version == 68) { |
1582 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1583 | SNDRV_PCM_RATE_96000; | |
1584 | runtime->hw.rate_max = 96000; | |
1585 | } | |
1da177e4 LT |
1586 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); |
1587 | } | |
62932df8 | 1588 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1589 | return 0; |
1590 | } | |
1591 | ||
2cbdb686 | 1592 | static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1593 | { |
2cbdb686 TI |
1594 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1595 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1596 | int err; |
1597 | ||
1598 | if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ | |
1599 | return err; | |
1600 | if (cm->can_ac3_hw) { | |
1601 | runtime->hw = snd_cmipci_playback_spdif; | |
57bd68b8 | 1602 | if (cm->chip_version >= 37) { |
1da177e4 | 1603 | runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; |
57bd68b8 CL |
1604 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); |
1605 | } | |
8992e18d CL |
1606 | if (cm->chip_version == 68) { |
1607 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1608 | SNDRV_PCM_RATE_96000; | |
1609 | runtime->hw.rate_max = 96000; | |
1610 | } | |
1da177e4 LT |
1611 | } else { |
1612 | runtime->hw = snd_cmipci_playback_iec958_subframe; | |
1613 | } | |
1614 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); | |
1615 | cm->dig_pcm_status = cm->dig_status; | |
1616 | return 0; | |
1617 | } | |
1618 | ||
2cbdb686 | 1619 | static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1620 | { |
2cbdb686 TI |
1621 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1622 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1623 | int err; |
1624 | ||
1625 | if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ | |
1626 | return err; | |
1627 | runtime->hw = snd_cmipci_capture_spdif; | |
1628 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); | |
1629 | return 0; | |
1630 | } | |
1631 | ||
1632 | ||
1633 | /* | |
1634 | */ | |
1635 | ||
2cbdb686 | 1636 | static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1637 | { |
2cbdb686 | 1638 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1639 | close_device_check(cm, CM_OPEN_PLAYBACK); |
1640 | return 0; | |
1641 | } | |
1642 | ||
2cbdb686 | 1643 | static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1644 | { |
2cbdb686 | 1645 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1646 | close_device_check(cm, CM_OPEN_CAPTURE); |
1647 | return 0; | |
1648 | } | |
1649 | ||
2cbdb686 | 1650 | static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1651 | { |
2cbdb686 | 1652 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1653 | close_device_check(cm, CM_OPEN_PLAYBACK2); |
1654 | close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); | |
1655 | return 0; | |
1656 | } | |
1657 | ||
2cbdb686 | 1658 | static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1659 | { |
2cbdb686 | 1660 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1661 | close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); |
1662 | return 0; | |
1663 | } | |
1664 | ||
2cbdb686 | 1665 | static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1666 | { |
2cbdb686 | 1667 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1668 | close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); |
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | ||
1673 | /* | |
1674 | */ | |
1675 | ||
2cbdb686 | 1676 | static struct snd_pcm_ops snd_cmipci_playback_ops = { |
1da177e4 LT |
1677 | .open = snd_cmipci_playback_open, |
1678 | .close = snd_cmipci_playback_close, | |
1679 | .ioctl = snd_pcm_lib_ioctl, | |
1680 | .hw_params = snd_cmipci_hw_params, | |
1681 | .hw_free = snd_cmipci_playback_hw_free, | |
1682 | .prepare = snd_cmipci_playback_prepare, | |
1683 | .trigger = snd_cmipci_playback_trigger, | |
1684 | .pointer = snd_cmipci_playback_pointer, | |
1685 | }; | |
1686 | ||
2cbdb686 | 1687 | static struct snd_pcm_ops snd_cmipci_capture_ops = { |
1da177e4 LT |
1688 | .open = snd_cmipci_capture_open, |
1689 | .close = snd_cmipci_capture_close, | |
1690 | .ioctl = snd_pcm_lib_ioctl, | |
1691 | .hw_params = snd_cmipci_hw_params, | |
1692 | .hw_free = snd_cmipci_hw_free, | |
1693 | .prepare = snd_cmipci_capture_prepare, | |
1694 | .trigger = snd_cmipci_capture_trigger, | |
1695 | .pointer = snd_cmipci_capture_pointer, | |
1696 | }; | |
1697 | ||
2cbdb686 | 1698 | static struct snd_pcm_ops snd_cmipci_playback2_ops = { |
1da177e4 LT |
1699 | .open = snd_cmipci_playback2_open, |
1700 | .close = snd_cmipci_playback2_close, | |
1701 | .ioctl = snd_pcm_lib_ioctl, | |
1702 | .hw_params = snd_cmipci_playback2_hw_params, | |
1703 | .hw_free = snd_cmipci_hw_free, | |
1704 | .prepare = snd_cmipci_capture_prepare, /* channel B */ | |
1705 | .trigger = snd_cmipci_capture_trigger, /* channel B */ | |
1706 | .pointer = snd_cmipci_capture_pointer, /* channel B */ | |
1707 | }; | |
1708 | ||
2cbdb686 | 1709 | static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { |
1da177e4 LT |
1710 | .open = snd_cmipci_playback_spdif_open, |
1711 | .close = snd_cmipci_playback_spdif_close, | |
1712 | .ioctl = snd_pcm_lib_ioctl, | |
1713 | .hw_params = snd_cmipci_hw_params, | |
1714 | .hw_free = snd_cmipci_playback_hw_free, | |
1715 | .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ | |
1716 | .trigger = snd_cmipci_playback_trigger, | |
1717 | .pointer = snd_cmipci_playback_pointer, | |
1718 | }; | |
1719 | ||
2cbdb686 | 1720 | static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { |
1da177e4 LT |
1721 | .open = snd_cmipci_capture_spdif_open, |
1722 | .close = snd_cmipci_capture_spdif_close, | |
1723 | .ioctl = snd_pcm_lib_ioctl, | |
1724 | .hw_params = snd_cmipci_hw_params, | |
1725 | .hw_free = snd_cmipci_capture_spdif_hw_free, | |
1726 | .prepare = snd_cmipci_capture_spdif_prepare, | |
1727 | .trigger = snd_cmipci_capture_trigger, | |
1728 | .pointer = snd_cmipci_capture_pointer, | |
1729 | }; | |
1730 | ||
1731 | ||
1732 | /* | |
1733 | */ | |
1734 | ||
2cbdb686 | 1735 | static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device) |
1da177e4 | 1736 | { |
2cbdb686 | 1737 | struct snd_pcm *pcm; |
1da177e4 LT |
1738 | int err; |
1739 | ||
1740 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1741 | if (err < 0) | |
1742 | return err; | |
1743 | ||
1744 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); | |
1745 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); | |
1746 | ||
1747 | pcm->private_data = cm; | |
1da177e4 LT |
1748 | pcm->info_flags = 0; |
1749 | strcpy(pcm->name, "C-Media PCI DAC/ADC"); | |
1750 | cm->pcm = pcm; | |
1751 | ||
1752 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1753 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1754 | ||
1755 | return 0; | |
1756 | } | |
1757 | ||
2cbdb686 | 1758 | static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device) |
1da177e4 | 1759 | { |
2cbdb686 | 1760 | struct snd_pcm *pcm; |
1da177e4 LT |
1761 | int err; |
1762 | ||
1763 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); | |
1764 | if (err < 0) | |
1765 | return err; | |
1766 | ||
1767 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); | |
1768 | ||
1769 | pcm->private_data = cm; | |
1da177e4 LT |
1770 | pcm->info_flags = 0; |
1771 | strcpy(pcm->name, "C-Media PCI 2nd DAC"); | |
1772 | cm->pcm2 = pcm; | |
1773 | ||
1774 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1775 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
2cbdb686 | 1780 | static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) |
1da177e4 | 1781 | { |
2cbdb686 | 1782 | struct snd_pcm *pcm; |
1da177e4 LT |
1783 | int err; |
1784 | ||
1785 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1786 | if (err < 0) | |
1787 | return err; | |
1788 | ||
1789 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); | |
1790 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); | |
1791 | ||
1792 | pcm->private_data = cm; | |
1da177e4 LT |
1793 | pcm->info_flags = 0; |
1794 | strcpy(pcm->name, "C-Media PCI IEC958"); | |
1795 | cm->pcm_spdif = pcm; | |
1796 | ||
1797 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1798 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1799 | ||
1800 | return 0; | |
1801 | } | |
1802 | ||
1803 | /* | |
1804 | * mixer interface: | |
1805 | * - CM8338/8738 has a compatible mixer interface with SB16, but | |
1806 | * lack of some elements like tone control, i/o gain and AGC. | |
1807 | * - Access to native registers: | |
1808 | * - A 3D switch | |
1809 | * - Output mute switches | |
1810 | */ | |
1811 | ||
2cbdb686 | 1812 | static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) |
1da177e4 LT |
1813 | { |
1814 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1815 | outb(data, s->iobase + CM_REG_SB16_DATA); | |
1816 | } | |
1817 | ||
2cbdb686 | 1818 | static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) |
1da177e4 LT |
1819 | { |
1820 | unsigned char v; | |
1821 | ||
1822 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1823 | v = inb(s->iobase + CM_REG_SB16_DATA); | |
1824 | return v; | |
1825 | } | |
1826 | ||
1827 | /* | |
1828 | * general mixer element | |
1829 | */ | |
2cbdb686 | 1830 | struct cmipci_sb_reg { |
1da177e4 LT |
1831 | unsigned int left_reg, right_reg; |
1832 | unsigned int left_shift, right_shift; | |
1833 | unsigned int mask; | |
1834 | unsigned int invert: 1; | |
1835 | unsigned int stereo: 1; | |
2cbdb686 | 1836 | }; |
1da177e4 LT |
1837 | |
1838 | #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ | |
1839 | ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) | |
1840 | ||
1841 | #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ | |
1842 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1843 | .info = snd_cmipci_info_volume, \ | |
1844 | .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ | |
1845 | .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ | |
1846 | } | |
1847 | ||
1848 | #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) | |
1849 | #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) | |
1850 | #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) | |
1851 | #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) | |
1852 | ||
2cbdb686 | 1853 | static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) |
1da177e4 LT |
1854 | { |
1855 | r->left_reg = val & 0xff; | |
1856 | r->right_reg = (val >> 8) & 0xff; | |
1857 | r->left_shift = (val >> 16) & 0x07; | |
1858 | r->right_shift = (val >> 19) & 0x07; | |
1859 | r->invert = (val >> 22) & 1; | |
1860 | r->stereo = (val >> 23) & 1; | |
1861 | r->mask = (val >> 24) & 0xff; | |
1862 | } | |
1863 | ||
2cbdb686 TI |
1864 | static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, |
1865 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 1866 | { |
2cbdb686 | 1867 | struct cmipci_sb_reg reg; |
1da177e4 LT |
1868 | |
1869 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1870 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1871 | uinfo->count = reg.stereo + 1; | |
1872 | uinfo->value.integer.min = 0; | |
1873 | uinfo->value.integer.max = reg.mask; | |
1874 | return 0; | |
1875 | } | |
1876 | ||
2cbdb686 TI |
1877 | static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, |
1878 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1879 | { |
2cbdb686 TI |
1880 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1881 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1882 | int val; |
1883 | ||
1884 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1885 | spin_lock_irq(&cm->reg_lock); | |
1886 | val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; | |
1887 | if (reg.invert) | |
1888 | val = reg.mask - val; | |
1889 | ucontrol->value.integer.value[0] = val; | |
1890 | if (reg.stereo) { | |
1891 | val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; | |
1892 | if (reg.invert) | |
1893 | val = reg.mask - val; | |
1894 | ucontrol->value.integer.value[1] = val; | |
1895 | } | |
1896 | spin_unlock_irq(&cm->reg_lock); | |
1897 | return 0; | |
1898 | } | |
1899 | ||
2cbdb686 TI |
1900 | static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, |
1901 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1902 | { |
2cbdb686 TI |
1903 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1904 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1905 | int change; |
1906 | int left, right, oleft, oright; | |
1907 | ||
1908 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1909 | left = ucontrol->value.integer.value[0] & reg.mask; | |
1910 | if (reg.invert) | |
1911 | left = reg.mask - left; | |
1912 | left <<= reg.left_shift; | |
1913 | if (reg.stereo) { | |
1914 | right = ucontrol->value.integer.value[1] & reg.mask; | |
1915 | if (reg.invert) | |
1916 | right = reg.mask - right; | |
1917 | right <<= reg.right_shift; | |
1918 | } else | |
1919 | right = 0; | |
1920 | spin_lock_irq(&cm->reg_lock); | |
1921 | oleft = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1922 | left |= oleft & ~(reg.mask << reg.left_shift); | |
1923 | change = left != oleft; | |
1924 | if (reg.stereo) { | |
1925 | if (reg.left_reg != reg.right_reg) { | |
1926 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
1927 | oright = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1928 | } else | |
1929 | oright = left; | |
1930 | right |= oright & ~(reg.mask << reg.right_shift); | |
1931 | change |= right != oright; | |
1932 | snd_cmipci_mixer_write(cm, reg.right_reg, right); | |
1933 | } else | |
1934 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
1935 | spin_unlock_irq(&cm->reg_lock); | |
1936 | return change; | |
1937 | } | |
1938 | ||
1939 | /* | |
1940 | * input route (left,right) -> (left,right) | |
1941 | */ | |
1942 | #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ | |
1943 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1944 | .info = snd_cmipci_info_input_sw, \ | |
1945 | .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ | |
1946 | .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ | |
1947 | } | |
1948 | ||
2cbdb686 TI |
1949 | static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, |
1950 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1951 | { |
1952 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
1953 | uinfo->count = 4; | |
1954 | uinfo->value.integer.min = 0; | |
1955 | uinfo->value.integer.max = 1; | |
1956 | return 0; | |
1957 | } | |
1958 | ||
2cbdb686 TI |
1959 | static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, |
1960 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1961 | { |
2cbdb686 TI |
1962 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1963 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1964 | int val1, val2; |
1965 | ||
1966 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1967 | spin_lock_irq(&cm->reg_lock); | |
1968 | val1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1969 | val2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1970 | spin_unlock_irq(&cm->reg_lock); | |
1971 | ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; | |
1972 | ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; | |
1973 | ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; | |
1974 | ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; | |
1975 | return 0; | |
1976 | } | |
1977 | ||
2cbdb686 TI |
1978 | static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, |
1979 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1980 | { |
2cbdb686 TI |
1981 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1982 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1983 | int change; |
1984 | int val1, val2, oval1, oval2; | |
1985 | ||
1986 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1987 | spin_lock_irq(&cm->reg_lock); | |
1988 | oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1989 | oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1990 | val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
1991 | val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
1992 | val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; | |
1993 | val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; | |
1994 | val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; | |
1995 | val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; | |
1996 | change = val1 != oval1 || val2 != oval2; | |
1997 | snd_cmipci_mixer_write(cm, reg.left_reg, val1); | |
1998 | snd_cmipci_mixer_write(cm, reg.right_reg, val2); | |
1999 | spin_unlock_irq(&cm->reg_lock); | |
2000 | return change; | |
2001 | } | |
2002 | ||
2003 | /* | |
2004 | * native mixer switches/volumes | |
2005 | */ | |
2006 | ||
2007 | #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ | |
2008 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2009 | .info = snd_cmipci_info_native_mixer, \ | |
2010 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2011 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ | |
2012 | } | |
2013 | ||
2014 | #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ | |
2015 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2016 | .info = snd_cmipci_info_native_mixer, \ | |
2017 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2018 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ | |
2019 | } | |
2020 | ||
2021 | #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ | |
2022 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2023 | .info = snd_cmipci_info_native_mixer, \ | |
2024 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2025 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ | |
2026 | } | |
2027 | ||
2028 | #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ | |
2029 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2030 | .info = snd_cmipci_info_native_mixer, \ | |
2031 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2032 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ | |
2033 | } | |
2034 | ||
2cbdb686 TI |
2035 | static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, |
2036 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 2037 | { |
2cbdb686 | 2038 | struct cmipci_sb_reg reg; |
1da177e4 LT |
2039 | |
2040 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2041 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2042 | uinfo->count = reg.stereo + 1; | |
2043 | uinfo->value.integer.min = 0; | |
2044 | uinfo->value.integer.max = reg.mask; | |
2045 | return 0; | |
2046 | ||
2047 | } | |
2048 | ||
2cbdb686 TI |
2049 | static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, |
2050 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2051 | { |
2cbdb686 TI |
2052 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2053 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2054 | unsigned char oreg, val; |
2055 | ||
2056 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2057 | spin_lock_irq(&cm->reg_lock); | |
2058 | oreg = inb(cm->iobase + reg.left_reg); | |
2059 | val = (oreg >> reg.left_shift) & reg.mask; | |
2060 | if (reg.invert) | |
2061 | val = reg.mask - val; | |
2062 | ucontrol->value.integer.value[0] = val; | |
2063 | if (reg.stereo) { | |
2064 | val = (oreg >> reg.right_shift) & reg.mask; | |
2065 | if (reg.invert) | |
2066 | val = reg.mask - val; | |
2067 | ucontrol->value.integer.value[1] = val; | |
2068 | } | |
2069 | spin_unlock_irq(&cm->reg_lock); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2cbdb686 TI |
2073 | static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, |
2074 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2075 | { |
2cbdb686 TI |
2076 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2077 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2078 | unsigned char oreg, nreg, val; |
2079 | ||
2080 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2081 | spin_lock_irq(&cm->reg_lock); | |
2082 | oreg = inb(cm->iobase + reg.left_reg); | |
2083 | val = ucontrol->value.integer.value[0] & reg.mask; | |
2084 | if (reg.invert) | |
2085 | val = reg.mask - val; | |
2086 | nreg = oreg & ~(reg.mask << reg.left_shift); | |
2087 | nreg |= (val << reg.left_shift); | |
2088 | if (reg.stereo) { | |
2089 | val = ucontrol->value.integer.value[1] & reg.mask; | |
2090 | if (reg.invert) | |
2091 | val = reg.mask - val; | |
2092 | nreg &= ~(reg.mask << reg.right_shift); | |
2093 | nreg |= (val << reg.right_shift); | |
2094 | } | |
2095 | outb(nreg, cm->iobase + reg.left_reg); | |
2096 | spin_unlock_irq(&cm->reg_lock); | |
2097 | return (nreg != oreg); | |
2098 | } | |
2099 | ||
2100 | /* | |
2101 | * special case - check mixer sensitivity | |
2102 | */ | |
2cbdb686 TI |
2103 | static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2104 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2105 | { |
2cbdb686 | 2106 | //struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2107 | return snd_cmipci_get_native_mixer(kcontrol, ucontrol); |
2108 | } | |
2109 | ||
2cbdb686 TI |
2110 | static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2111 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2112 | { |
2cbdb686 | 2113 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2114 | if (cm->mixer_insensitive) { |
2115 | /* ignored */ | |
2116 | return 0; | |
2117 | } | |
2118 | return snd_cmipci_put_native_mixer(kcontrol, ucontrol); | |
2119 | } | |
2120 | ||
2121 | ||
2cbdb686 | 2122 | static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = { |
1da177e4 LT |
2123 | CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), |
2124 | CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), | |
2125 | CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), | |
2126 | //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), | |
2127 | { /* switch with sensitivity */ | |
2128 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2129 | .name = "PCM Playback Switch", | |
2130 | .info = snd_cmipci_info_native_mixer, | |
2131 | .get = snd_cmipci_get_native_mixer_sensitive, | |
2132 | .put = snd_cmipci_put_native_mixer_sensitive, | |
2133 | .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), | |
2134 | }, | |
2135 | CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), | |
2136 | CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), | |
2137 | CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), | |
2138 | CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), | |
2139 | CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), | |
2140 | CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), | |
2141 | CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), | |
2142 | CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), | |
2143 | CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), | |
2144 | CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), | |
2145 | CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), | |
2146 | CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), | |
2147 | CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), | |
2148 | CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), | |
2149 | CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), | |
2150 | CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), | |
2151 | CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), | |
2eff7ec8 | 2152 | CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), |
1da177e4 | 2153 | CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), |
2eff7ec8 TI |
2154 | CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), |
2155 | CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), | |
f26eb78f | 2156 | CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), |
2eff7ec8 | 2157 | CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), |
1da177e4 LT |
2158 | }; |
2159 | ||
2160 | /* | |
2161 | * other switches | |
2162 | */ | |
2163 | ||
2cbdb686 | 2164 | struct cmipci_switch_args { |
1da177e4 LT |
2165 | int reg; /* register index */ |
2166 | unsigned int mask; /* mask bits */ | |
2167 | unsigned int mask_on; /* mask bits to turn on */ | |
2168 | unsigned int is_byte: 1; /* byte access? */ | |
2cbdb686 TI |
2169 | unsigned int ac3_sensitive: 1; /* access forbidden during |
2170 | * non-audio operation? | |
2171 | */ | |
2172 | }; | |
1da177e4 | 2173 | |
a5ce8890 | 2174 | #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info |
1da177e4 | 2175 | |
2cbdb686 TI |
2176 | static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2177 | struct snd_ctl_elem_value *ucontrol, | |
2178 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2179 | { |
2180 | unsigned int val; | |
2cbdb686 | 2181 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2182 | |
2183 | spin_lock_irq(&cm->reg_lock); | |
2184 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2185 | ucontrol->value.integer.value[0] = 0; | |
2186 | spin_unlock_irq(&cm->reg_lock); | |
2187 | return 0; | |
2188 | } | |
2189 | if (args->is_byte) | |
2190 | val = inb(cm->iobase + args->reg); | |
2191 | else | |
2192 | val = snd_cmipci_read(cm, args->reg); | |
2193 | ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; | |
2194 | spin_unlock_irq(&cm->reg_lock); | |
2195 | return 0; | |
2196 | } | |
2197 | ||
2cbdb686 TI |
2198 | static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2199 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2200 | { |
2cbdb686 TI |
2201 | struct cmipci_switch_args *args; |
2202 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
1da177e4 LT |
2203 | snd_assert(args != NULL, return -EINVAL); |
2204 | return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); | |
2205 | } | |
2206 | ||
2cbdb686 TI |
2207 | static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2208 | struct snd_ctl_elem_value *ucontrol, | |
2209 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2210 | { |
2211 | unsigned int val; | |
2212 | int change; | |
2cbdb686 | 2213 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2214 | |
2215 | spin_lock_irq(&cm->reg_lock); | |
2216 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2217 | /* ignored */ | |
2218 | spin_unlock_irq(&cm->reg_lock); | |
2219 | return 0; | |
2220 | } | |
2221 | if (args->is_byte) | |
2222 | val = inb(cm->iobase + args->reg); | |
2223 | else | |
2224 | val = snd_cmipci_read(cm, args->reg); | |
8c670714 TB |
2225 | change = (val & args->mask) != (ucontrol->value.integer.value[0] ? |
2226 | args->mask_on : (args->mask & ~args->mask_on)); | |
1da177e4 LT |
2227 | if (change) { |
2228 | val &= ~args->mask; | |
2229 | if (ucontrol->value.integer.value[0]) | |
2230 | val |= args->mask_on; | |
2231 | else | |
2232 | val |= (args->mask & ~args->mask_on); | |
2233 | if (args->is_byte) | |
2234 | outb((unsigned char)val, cm->iobase + args->reg); | |
2235 | else | |
2236 | snd_cmipci_write(cm, args->reg, val); | |
2237 | } | |
2238 | spin_unlock_irq(&cm->reg_lock); | |
2239 | return change; | |
2240 | } | |
2241 | ||
2cbdb686 TI |
2242 | static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2243 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2244 | { |
2cbdb686 TI |
2245 | struct cmipci_switch_args *args; |
2246 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
1da177e4 LT |
2247 | snd_assert(args != NULL, return -EINVAL); |
2248 | return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); | |
2249 | } | |
2250 | ||
2251 | #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ | |
2cbdb686 | 2252 | static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ |
1da177e4 LT |
2253 | .reg = xreg, \ |
2254 | .mask = xmask, \ | |
2255 | .mask_on = xmask_on, \ | |
2256 | .is_byte = xis_byte, \ | |
2257 | .ac3_sensitive = xac3, \ | |
2258 | } | |
2259 | ||
2260 | #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ | |
2261 | DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) | |
2262 | ||
2263 | #if 0 /* these will be controlled in pcm device */ | |
2264 | DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); | |
2265 | DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); | |
2266 | #endif | |
2267 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); | |
2268 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); | |
2269 | DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); | |
2270 | DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); | |
2271 | DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); | |
2272 | DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); | |
2273 | DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); | |
2274 | DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ | |
2275 | // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); | |
2276 | DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); | |
2277 | DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); | |
2278 | /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ | |
2279 | DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); | |
2280 | DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); | |
2281 | #if CM_CH_PLAY == 1 | |
2282 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ | |
2283 | #else | |
2284 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); | |
2285 | #endif | |
2286 | DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); | |
01d25d46 TI |
2287 | // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); |
2288 | // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); | |
1da177e4 LT |
2289 | // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ |
2290 | DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); | |
2291 | ||
2292 | #define DEFINE_SWITCH(sname, stype, sarg) \ | |
2293 | { .name = sname, \ | |
2294 | .iface = stype, \ | |
2295 | .info = snd_cmipci_uswitch_info, \ | |
2296 | .get = snd_cmipci_uswitch_get, \ | |
2297 | .put = snd_cmipci_uswitch_put, \ | |
2298 | .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ | |
2299 | } | |
2300 | ||
2301 | #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) | |
2302 | #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) | |
2303 | ||
2304 | ||
2305 | /* | |
2306 | * callbacks for spdif output switch | |
2307 | * needs toggle two registers.. | |
2308 | */ | |
2cbdb686 TI |
2309 | static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, |
2310 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
2311 | { |
2312 | int changed; | |
2313 | changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2314 | changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2315 | return changed; | |
2316 | } | |
2317 | ||
2cbdb686 TI |
2318 | static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, |
2319 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2320 | { |
2cbdb686 | 2321 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2322 | int changed; |
2323 | changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2324 | changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2325 | if (changed) { | |
2326 | if (ucontrol->value.integer.value[0]) { | |
2327 | if (chip->spdif_playback_avail) | |
2328 | snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2329 | } else { | |
2330 | if (chip->spdif_playback_avail) | |
2331 | snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2332 | } | |
2333 | } | |
2334 | chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; | |
2335 | return changed; | |
2336 | } | |
2337 | ||
2338 | ||
2cbdb686 TI |
2339 | static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, |
2340 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 | 2341 | { |
2cbdb686 | 2342 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2343 | static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; |
2344 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2345 | uinfo->count = 1; | |
2346 | uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; | |
2347 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2348 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2349 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2cbdb686 | 2353 | static inline unsigned int get_line_in_mode(struct cmipci *cm) |
01d25d46 TI |
2354 | { |
2355 | unsigned int val; | |
2356 | if (cm->chip_version >= 39) { | |
2357 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); | |
2358 | if (val & CM_LINE_AS_BASS) | |
2359 | return 2; | |
2360 | } | |
2361 | val = snd_cmipci_read_b(cm, CM_REG_MIXER1); | |
2362 | if (val & CM_SPK4) | |
2363 | return 1; | |
2364 | return 0; | |
2365 | } | |
2366 | ||
2cbdb686 TI |
2367 | static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, |
2368 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2369 | { |
2cbdb686 | 2370 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2371 | |
2372 | spin_lock_irq(&cm->reg_lock); | |
2373 | ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); | |
2374 | spin_unlock_irq(&cm->reg_lock); | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2cbdb686 TI |
2378 | static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, |
2379 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2380 | { |
2cbdb686 | 2381 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2382 | int change; |
2383 | ||
2384 | spin_lock_irq(&cm->reg_lock); | |
2385 | if (ucontrol->value.enumerated.item[0] == 2) | |
2386 | change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); | |
2387 | else | |
2388 | change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); | |
2389 | if (ucontrol->value.enumerated.item[0] == 1) | |
2390 | change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); | |
2391 | else | |
2392 | change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); | |
2393 | spin_unlock_irq(&cm->reg_lock); | |
2394 | return change; | |
2395 | } | |
2396 | ||
2cbdb686 TI |
2397 | static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, |
2398 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 TI |
2399 | { |
2400 | static char *texts[2] = { "Mic-In", "Center/LFE Output" }; | |
2401 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2402 | uinfo->count = 1; | |
2403 | uinfo->value.enumerated.items = 2; | |
2404 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2405 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2406 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2407 | return 0; | |
2408 | } | |
2409 | ||
2cbdb686 TI |
2410 | static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, |
2411 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2412 | { |
2cbdb686 | 2413 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2414 | /* same bit as spdi_phase */ |
2415 | spin_lock_irq(&cm->reg_lock); | |
2416 | ucontrol->value.enumerated.item[0] = | |
2417 | (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; | |
2418 | spin_unlock_irq(&cm->reg_lock); | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2cbdb686 TI |
2422 | static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, |
2423 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2424 | { |
2cbdb686 | 2425 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2426 | int change; |
2427 | ||
2428 | spin_lock_irq(&cm->reg_lock); | |
2429 | if (ucontrol->value.enumerated.item[0]) | |
2430 | change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2431 | else | |
2432 | change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2433 | spin_unlock_irq(&cm->reg_lock); | |
2434 | return change; | |
2435 | } | |
2436 | ||
1da177e4 | 2437 | /* both for CM8338/8738 */ |
2cbdb686 | 2438 | static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = { |
1da177e4 | 2439 | DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), |
01d25d46 TI |
2440 | { |
2441 | .name = "Line-In Mode", | |
2442 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2443 | .info = snd_cmipci_line_in_mode_info, | |
2444 | .get = snd_cmipci_line_in_mode_get, | |
2445 | .put = snd_cmipci_line_in_mode_put, | |
2446 | }, | |
1da177e4 LT |
2447 | }; |
2448 | ||
2449 | /* for non-multichannel chips */ | |
2cbdb686 | 2450 | static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata = |
1da177e4 LT |
2451 | DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); |
2452 | ||
2453 | /* only for CM8738 */ | |
2cbdb686 | 2454 | static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2455 | #if 0 /* controlled in pcm device */ |
2456 | DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), | |
2457 | DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), | |
2458 | DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), | |
2459 | #endif | |
2460 | // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), | |
2461 | { .name = "IEC958 Output Switch", | |
2462 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2463 | .info = snd_cmipci_uswitch_info, | |
2464 | .get = snd_cmipci_spdout_enable_get, | |
2465 | .put = snd_cmipci_spdout_enable_put, | |
2466 | }, | |
2467 | DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), | |
2468 | DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), | |
2469 | DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), | |
2470 | // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), | |
2471 | DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), | |
2472 | DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), | |
2473 | }; | |
2474 | ||
2475 | /* only for model 033/037 */ | |
2cbdb686 | 2476 | static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2477 | DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), |
2478 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), | |
2479 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), | |
2480 | }; | |
2481 | ||
2482 | /* only for model 039 or later */ | |
2cbdb686 | 2483 | static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2484 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), |
2485 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), | |
01d25d46 TI |
2486 | { |
2487 | .name = "Mic-In Mode", | |
2488 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2489 | .info = snd_cmipci_mic_in_mode_info, | |
2490 | .get = snd_cmipci_mic_in_mode_get, | |
2491 | .put = snd_cmipci_mic_in_mode_put, | |
2492 | } | |
1da177e4 LT |
2493 | }; |
2494 | ||
2495 | /* card control switches */ | |
2cbdb686 | 2496 | static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = { |
1da177e4 LT |
2497 | // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */ |
2498 | DEFINE_CARD_SWITCH("Modem", modem), | |
2499 | }; | |
2500 | ||
2501 | ||
2cbdb686 | 2502 | static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) |
1da177e4 | 2503 | { |
2cbdb686 TI |
2504 | struct snd_card *card; |
2505 | struct snd_kcontrol_new *sw; | |
2506 | struct snd_kcontrol *kctl; | |
1da177e4 LT |
2507 | unsigned int idx; |
2508 | int err; | |
2509 | ||
2510 | snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); | |
2511 | ||
2512 | card = cm->card; | |
2513 | ||
2514 | strcpy(card->mixername, "CMedia PCI"); | |
2515 | ||
2516 | spin_lock_irq(&cm->reg_lock); | |
2517 | snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ | |
2518 | spin_unlock_irq(&cm->reg_lock); | |
2519 | ||
2520 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { | |
2521 | if (cm->chip_version == 68) { // 8768 has no PCM volume | |
2522 | if (!strcmp(snd_cmipci_mixers[idx].name, | |
2523 | "PCM Playback Volume")) | |
2524 | continue; | |
2525 | } | |
2526 | if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) | |
2527 | return err; | |
2528 | } | |
2529 | ||
2530 | /* mixer switches */ | |
2531 | sw = snd_cmipci_mixer_switches; | |
2532 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { | |
2533 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2534 | if (err < 0) | |
2535 | return err; | |
2536 | } | |
2537 | if (! cm->can_multi_ch) { | |
2538 | err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); | |
2539 | if (err < 0) | |
2540 | return err; | |
2541 | } | |
2542 | if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || | |
2543 | cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { | |
2544 | sw = snd_cmipci_8738_mixer_switches; | |
2545 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { | |
2546 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2547 | if (err < 0) | |
2548 | return err; | |
2549 | } | |
2550 | if (cm->can_ac3_hw) { | |
2551 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) | |
2552 | return err; | |
2553 | kctl->id.device = pcm_spdif_device; | |
2554 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) | |
2555 | return err; | |
2556 | kctl->id.device = pcm_spdif_device; | |
2557 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) | |
2558 | return err; | |
2559 | kctl->id.device = pcm_spdif_device; | |
2560 | } | |
2561 | if (cm->chip_version <= 37) { | |
2562 | sw = snd_cmipci_old_mixer_switches; | |
2563 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { | |
2564 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2565 | if (err < 0) | |
2566 | return err; | |
2567 | } | |
2568 | } | |
2569 | } | |
2570 | if (cm->chip_version >= 39) { | |
2571 | sw = snd_cmipci_extra_mixer_switches; | |
2572 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { | |
2573 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2574 | if (err < 0) | |
2575 | return err; | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | /* card switches */ | |
2580 | sw = snd_cmipci_control_switches; | |
2581 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { | |
2582 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2583 | if (err < 0) | |
2584 | return err; | |
2585 | } | |
2586 | ||
2587 | for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { | |
2cbdb686 TI |
2588 | struct snd_ctl_elem_id id; |
2589 | struct snd_kcontrol *ctl; | |
1da177e4 LT |
2590 | memset(&id, 0, sizeof(id)); |
2591 | id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; | |
2592 | strcpy(id.name, cm_saved_mixer[idx].name); | |
2593 | if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) | |
2594 | cm->mixer_res_ctl[idx] = ctl; | |
2595 | } | |
2596 | ||
2597 | return 0; | |
2598 | } | |
2599 | ||
2600 | ||
2601 | /* | |
2602 | * proc interface | |
2603 | */ | |
2604 | ||
2605 | #ifdef CONFIG_PROC_FS | |
2cbdb686 TI |
2606 | static void snd_cmipci_proc_read(struct snd_info_entry *entry, |
2607 | struct snd_info_buffer *buffer) | |
1da177e4 | 2608 | { |
2cbdb686 | 2609 | struct cmipci *cm = entry->private_data; |
1da177e4 LT |
2610 | int i; |
2611 | ||
2612 | snd_iprintf(buffer, "%s\n\n", cm->card->longname); | |
2613 | for (i = 0; i < 0x40; i++) { | |
2614 | int v = inb(cm->iobase + i); | |
2615 | if (i % 4 == 0) | |
2616 | snd_iprintf(buffer, "%02x: ", i); | |
2617 | snd_iprintf(buffer, "%02x", v); | |
2618 | if (i % 4 == 3) | |
2619 | snd_iprintf(buffer, "\n"); | |
2620 | else | |
2621 | snd_iprintf(buffer, " "); | |
2622 | } | |
2623 | } | |
2624 | ||
2cbdb686 | 2625 | static void __devinit snd_cmipci_proc_init(struct cmipci *cm) |
1da177e4 | 2626 | { |
2cbdb686 | 2627 | struct snd_info_entry *entry; |
1da177e4 LT |
2628 | |
2629 | if (! snd_card_proc_new(cm->card, "cmipci", &entry)) | |
bf850204 | 2630 | snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read); |
1da177e4 LT |
2631 | } |
2632 | #else /* !CONFIG_PROC_FS */ | |
2cbdb686 | 2633 | static inline void snd_cmipci_proc_init(struct cmipci *cm) {} |
1da177e4 LT |
2634 | #endif |
2635 | ||
2636 | ||
f40b6890 | 2637 | static struct pci_device_id snd_cmipci_ids[] = { |
1da177e4 LT |
2638 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
2639 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2640 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2641 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2642 | {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2643 | {0,}, | |
2644 | }; | |
2645 | ||
2646 | ||
2647 | /* | |
2648 | * check chip version and capabilities | |
2649 | * driver name is modified according to the chip model | |
2650 | */ | |
2cbdb686 | 2651 | static void __devinit query_chip(struct cmipci *cm) |
1da177e4 LT |
2652 | { |
2653 | unsigned int detect; | |
2654 | ||
2655 | /* check reg 0Ch, bit 24-31 */ | |
2656 | detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; | |
2657 | if (! detect) { | |
2658 | /* check reg 08h, bit 24-28 */ | |
2659 | detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; | |
133271fe CL |
2660 | switch (detect) { |
2661 | case 0: | |
1da177e4 | 2662 | cm->chip_version = 33; |
1da177e4 LT |
2663 | if (cm->do_soft_ac3) |
2664 | cm->can_ac3_sw = 1; | |
2665 | else | |
2666 | cm->can_ac3_hw = 1; | |
133271fe | 2667 | break; |
6935e688 | 2668 | case CM_CHIP_037: |
1da177e4 | 2669 | cm->chip_version = 37; |
1da177e4 | 2670 | cm->can_ac3_hw = 1; |
133271fe CL |
2671 | break; |
2672 | default: | |
2673 | cm->chip_version = 39; | |
2674 | cm->can_ac3_hw = 1; | |
2675 | break; | |
1da177e4 | 2676 | } |
133271fe | 2677 | cm->max_channels = 2; |
1da177e4 | 2678 | } else { |
133271fe | 2679 | if (detect & CM_CHIP_039) { |
1da177e4 LT |
2680 | cm->chip_version = 39; |
2681 | if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ | |
2682 | cm->max_channels = 6; | |
2683 | else | |
2684 | cm->max_channels = 4; | |
133271fe CL |
2685 | } else if (detect & CM_CHIP_8768) { |
2686 | cm->chip_version = 68; | |
2687 | cm->max_channels = 8; | |
1da177e4 | 2688 | } else { |
133271fe CL |
2689 | cm->chip_version = 55; |
2690 | cm->max_channels = 6; | |
1da177e4 | 2691 | } |
133271fe | 2692 | cm->can_ac3_hw = 1; |
133271fe | 2693 | cm->can_multi_ch = 1; |
1da177e4 LT |
2694 | } |
2695 | } | |
2696 | ||
2697 | #ifdef SUPPORT_JOYSTICK | |
2cbdb686 | 2698 | static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev) |
1da177e4 LT |
2699 | { |
2700 | static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ | |
2701 | struct gameport *gp; | |
2702 | struct resource *r = NULL; | |
2703 | int i, io_port = 0; | |
2704 | ||
2705 | if (joystick_port[dev] == 0) | |
2706 | return -ENODEV; | |
2707 | ||
2708 | if (joystick_port[dev] == 1) { /* auto-detect */ | |
2709 | for (i = 0; ports[i]; i++) { | |
2710 | io_port = ports[i]; | |
2711 | r = request_region(io_port, 1, "CMIPCI gameport"); | |
2712 | if (r) | |
2713 | break; | |
2714 | } | |
2715 | } else { | |
2716 | io_port = joystick_port[dev]; | |
2717 | r = request_region(io_port, 1, "CMIPCI gameport"); | |
2718 | } | |
2719 | ||
2720 | if (!r) { | |
2721 | printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); | |
2722 | return -EBUSY; | |
2723 | } | |
2724 | ||
2725 | cm->gameport = gp = gameport_allocate_port(); | |
2726 | if (!gp) { | |
2727 | printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); | |
b1d5776d | 2728 | release_and_free_resource(r); |
1da177e4 LT |
2729 | return -ENOMEM; |
2730 | } | |
2731 | gameport_set_name(gp, "C-Media Gameport"); | |
2732 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); | |
2733 | gameport_set_dev_parent(gp, &cm->pci->dev); | |
2734 | gp->io = io_port; | |
2735 | gameport_set_port_data(gp, r); | |
2736 | ||
2737 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
2738 | ||
2739 | gameport_register_port(cm->gameport); | |
2740 | ||
2741 | return 0; | |
2742 | } | |
2743 | ||
2cbdb686 | 2744 | static void snd_cmipci_free_gameport(struct cmipci *cm) |
1da177e4 LT |
2745 | { |
2746 | if (cm->gameport) { | |
2747 | struct resource *r = gameport_get_port_data(cm->gameport); | |
2748 | ||
2749 | gameport_unregister_port(cm->gameport); | |
2750 | cm->gameport = NULL; | |
2751 | ||
2752 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
b1d5776d | 2753 | release_and_free_resource(r); |
1da177e4 LT |
2754 | } |
2755 | } | |
2756 | #else | |
2cbdb686 TI |
2757 | static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } |
2758 | static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } | |
1da177e4 LT |
2759 | #endif |
2760 | ||
2cbdb686 | 2761 | static int snd_cmipci_free(struct cmipci *cm) |
1da177e4 LT |
2762 | { |
2763 | if (cm->irq >= 0) { | |
2764 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2765 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); | |
2766 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ | |
2767 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
2768 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
2769 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
2770 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
2771 | ||
2772 | /* reset mixer */ | |
2773 | snd_cmipci_mixer_write(cm, 0, 0); | |
2774 | ||
2775 | synchronize_irq(cm->irq); | |
2776 | ||
2cbdb686 | 2777 | free_irq(cm->irq, cm); |
1da177e4 LT |
2778 | } |
2779 | ||
2780 | snd_cmipci_free_gameport(cm); | |
2781 | pci_release_regions(cm->pci); | |
2782 | pci_disable_device(cm->pci); | |
2783 | kfree(cm); | |
2784 | return 0; | |
2785 | } | |
2786 | ||
2cbdb686 | 2787 | static int snd_cmipci_dev_free(struct snd_device *device) |
1da177e4 | 2788 | { |
2cbdb686 | 2789 | struct cmipci *cm = device->device_data; |
1da177e4 LT |
2790 | return snd_cmipci_free(cm); |
2791 | } | |
2792 | ||
2cbdb686 | 2793 | static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port) |
5747e540 CL |
2794 | { |
2795 | long iosynth; | |
2796 | unsigned int val; | |
2cbdb686 | 2797 | struct snd_opl3 *opl3; |
5747e540 CL |
2798 | int err; |
2799 | ||
2f24d159 TI |
2800 | if (!fm_port) |
2801 | goto disable_fm; | |
2802 | ||
c78c950d | 2803 | if (cm->chip_version >= 39) { |
45c41b48 CL |
2804 | /* first try FM regs in PCI port range */ |
2805 | iosynth = cm->iobase + CM_REG_FM_PCI; | |
2806 | err = snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2807 | OPL3_HW_OPL3, 1, &opl3); | |
2808 | } else { | |
2809 | err = -EIO; | |
2810 | } | |
5747e540 CL |
2811 | if (err < 0) { |
2812 | /* then try legacy ports */ | |
2813 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; | |
2814 | iosynth = fm_port; | |
2815 | switch (iosynth) { | |
2816 | case 0x3E8: val |= CM_FMSEL_3E8; break; | |
2817 | case 0x3E0: val |= CM_FMSEL_3E0; break; | |
2818 | case 0x3C8: val |= CM_FMSEL_3C8; break; | |
2819 | case 0x388: val |= CM_FMSEL_388; break; | |
2820 | default: | |
2f24d159 | 2821 | goto disable_fm; |
5747e540 CL |
2822 | } |
2823 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
2824 | /* enable FM */ | |
2825 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2826 | ||
2827 | if (snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2828 | OPL3_HW_OPL3, 0, &opl3) < 0) { | |
2829 | printk(KERN_ERR "cmipci: no OPL device at %#lx, " | |
2830 | "skipping...\n", iosynth); | |
2f24d159 | 2831 | goto disable_fm; |
5747e540 CL |
2832 | } |
2833 | } | |
2834 | if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { | |
2835 | printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); | |
2836 | return err; | |
2837 | } | |
2838 | return 0; | |
2f24d159 TI |
2839 | |
2840 | disable_fm: | |
2841 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); | |
2842 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2843 | return 0; | |
5747e540 CL |
2844 | } |
2845 | ||
2cbdb686 TI |
2846 | static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, |
2847 | int dev, struct cmipci **rcmipci) | |
1da177e4 | 2848 | { |
2cbdb686 | 2849 | struct cmipci *cm; |
1da177e4 | 2850 | int err; |
2cbdb686 | 2851 | static struct snd_device_ops ops = { |
1da177e4 LT |
2852 | .dev_free = snd_cmipci_dev_free, |
2853 | }; | |
d6426257 | 2854 | unsigned int val; |
5747e540 | 2855 | long iomidi; |
c9116ae4 | 2856 | int integrated_midi = 0; |
b7e054a7 | 2857 | char modelstr[16]; |
1da177e4 LT |
2858 | int pcm_index, pcm_spdif_index; |
2859 | static struct pci_device_id intel_82437vx[] = { | |
2860 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, | |
2861 | { }, | |
2862 | }; | |
2863 | ||
2864 | *rcmipci = NULL; | |
2865 | ||
2866 | if ((err = pci_enable_device(pci)) < 0) | |
2867 | return err; | |
2868 | ||
e560d8d8 | 2869 | cm = kzalloc(sizeof(*cm), GFP_KERNEL); |
1da177e4 LT |
2870 | if (cm == NULL) { |
2871 | pci_disable_device(pci); | |
2872 | return -ENOMEM; | |
2873 | } | |
2874 | ||
2875 | spin_lock_init(&cm->reg_lock); | |
62932df8 | 2876 | mutex_init(&cm->open_mutex); |
1da177e4 LT |
2877 | cm->device = pci->device; |
2878 | cm->card = card; | |
2879 | cm->pci = pci; | |
2880 | cm->irq = -1; | |
2881 | cm->channel[0].ch = 0; | |
2882 | cm->channel[1].ch = 1; | |
2883 | cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ | |
2884 | ||
2885 | if ((err = pci_request_regions(pci, card->driver)) < 0) { | |
2886 | kfree(cm); | |
2887 | pci_disable_device(pci); | |
2888 | return err; | |
2889 | } | |
2890 | cm->iobase = pci_resource_start(pci, 0); | |
2891 | ||
2cbdb686 | 2892 | if (request_irq(pci->irq, snd_cmipci_interrupt, |
437a5a46 | 2893 | IRQF_SHARED, card->driver, cm)) { |
99b359ba | 2894 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
2895 | snd_cmipci_free(cm); |
2896 | return -EBUSY; | |
2897 | } | |
2898 | cm->irq = pci->irq; | |
2899 | ||
2900 | pci_set_master(cm->pci); | |
2901 | ||
2902 | /* | |
2903 | * check chip version, max channels and capabilities | |
2904 | */ | |
2905 | ||
2906 | cm->chip_version = 0; | |
2907 | cm->max_channels = 2; | |
2908 | cm->do_soft_ac3 = soft_ac3[dev]; | |
2909 | ||
2910 | if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && | |
2911 | pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) | |
2912 | query_chip(cm); | |
2913 | /* added -MCx suffix for chip supporting multi-channels */ | |
2914 | if (cm->can_multi_ch) | |
2915 | sprintf(cm->card->driver + strlen(cm->card->driver), | |
2916 | "-MC%d", cm->max_channels); | |
2917 | else if (cm->can_ac3_sw) | |
2918 | strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); | |
2919 | ||
2920 | cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
2921 | cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
2922 | ||
2923 | #if CM_CH_PLAY == 1 | |
2924 | cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ | |
2925 | #else | |
2926 | cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ | |
2927 | #endif | |
2928 | ||
2929 | /* initialize codec registers */ | |
2930 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ | |
2931 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
2932 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
2933 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
2934 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
2935 | ||
2936 | snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); | |
2937 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); | |
2938 | #if CM_CH_PLAY == 1 | |
2939 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
2940 | #else | |
2941 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
2942 | #endif | |
2943 | /* Set Bus Master Request */ | |
2944 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); | |
2945 | ||
2946 | /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ | |
2947 | switch (pci->device) { | |
2948 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
2949 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
2950 | if (!pci_dev_present(intel_82437vx)) | |
2951 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); | |
2952 | break; | |
2953 | default: | |
2954 | break; | |
2955 | } | |
2956 | ||
d6426257 CL |
2957 | if (cm->chip_version < 68) { |
2958 | val = pci->device < 0x110 ? 8338 : 8738; | |
d6426257 CL |
2959 | } else { |
2960 | switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) { | |
2961 | case 0: | |
2962 | val = 8769; | |
2963 | break; | |
2964 | case 2: | |
2965 | val = 8762; | |
2966 | break; | |
2967 | default: | |
2968 | switch ((pci->subsystem_vendor << 16) | | |
2969 | pci->subsystem_device) { | |
2970 | case 0x13f69761: | |
2971 | case 0x584d3741: | |
2972 | case 0x584d3751: | |
2973 | case 0x584d3761: | |
2974 | case 0x584d3771: | |
2975 | case 0x72848384: | |
2976 | val = 8770; | |
2977 | break; | |
2978 | default: | |
2979 | val = 8768; | |
2980 | break; | |
2981 | } | |
2982 | } | |
d6426257 | 2983 | } |
b7e054a7 CL |
2984 | sprintf(card->shortname, "C-Media CMI%d", val); |
2985 | if (cm->chip_version < 68) | |
2986 | sprintf(modelstr, " (model %d)", cm->chip_version); | |
2987 | else | |
2988 | modelstr[0] = '\0'; | |
2989 | sprintf(card->longname, "%s%s at %#lx, irq %i", | |
2990 | card->shortname, modelstr, cm->iobase, cm->irq); | |
1e02d6ea | 2991 | |
1da177e4 LT |
2992 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { |
2993 | snd_cmipci_free(cm); | |
2994 | return err; | |
2995 | } | |
2996 | ||
c78c950d | 2997 | if (cm->chip_version >= 39) { |
c9116ae4 CL |
2998 | val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); |
2999 | if (val != 0x00 && val != 0xff) { | |
3000 | iomidi = cm->iobase + CM_REG_MPU_PCI; | |
3001 | integrated_midi = 1; | |
3002 | } | |
3003 | } | |
3004 | if (!integrated_midi) { | |
c78c950d | 3005 | val = 0; |
5747e540 CL |
3006 | iomidi = mpu_port[dev]; |
3007 | switch (iomidi) { | |
3008 | case 0x320: val = CM_VMPU_320; break; | |
3009 | case 0x310: val = CM_VMPU_310; break; | |
3010 | case 0x300: val = CM_VMPU_300; break; | |
3011 | case 0x330: val = CM_VMPU_330; break; | |
3012 | default: | |
3013 | iomidi = 0; break; | |
3014 | } | |
3015 | if (iomidi > 0) { | |
3016 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
3017 | /* enable UART */ | |
3018 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); | |
88039815 CL |
3019 | if (inb(iomidi + 1) == 0xff) { |
3020 | snd_printk(KERN_ERR "cannot enable MPU-401 port" | |
3021 | " at %#lx\n", iomidi); | |
3022 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, | |
3023 | CM_UART_EN); | |
3024 | iomidi = 0; | |
3025 | } | |
1da177e4 LT |
3026 | } |
3027 | } | |
5747e540 | 3028 | |
45c41b48 CL |
3029 | if (cm->chip_version < 68) { |
3030 | err = snd_cmipci_create_fm(cm, fm_port[dev]); | |
3031 | if (err < 0) | |
3032 | return err; | |
3033 | } | |
1da177e4 LT |
3034 | |
3035 | /* reset mixer */ | |
3036 | snd_cmipci_mixer_write(cm, 0, 0); | |
3037 | ||
3038 | snd_cmipci_proc_init(cm); | |
3039 | ||
3040 | /* create pcm devices */ | |
3041 | pcm_index = pcm_spdif_index = 0; | |
3042 | if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) | |
3043 | return err; | |
3044 | pcm_index++; | |
b080ebbf CL |
3045 | if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) |
3046 | return err; | |
3047 | pcm_index++; | |
1da177e4 LT |
3048 | if (cm->can_ac3_hw || cm->can_ac3_sw) { |
3049 | pcm_spdif_index = pcm_index; | |
3050 | if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) | |
3051 | return err; | |
3052 | } | |
3053 | ||
3054 | /* create mixer interface & switches */ | |
3055 | if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) | |
3056 | return err; | |
3057 | ||
3058 | if (iomidi > 0) { | |
3059 | if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, | |
302e4c2f TI |
3060 | iomidi, |
3061 | (integrated_midi ? | |
3062 | MPU401_INFO_INTEGRATED : 0), | |
1da177e4 LT |
3063 | cm->irq, 0, &cm->rmidi)) < 0) { |
3064 | printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); | |
3065 | } | |
3066 | } | |
3067 | ||
3068 | #ifdef USE_VAR48KRATE | |
3069 | for (val = 0; val < ARRAY_SIZE(rates); val++) | |
3070 | snd_cmipci_set_pll(cm, rates[val], val); | |
3071 | ||
3072 | /* | |
3073 | * (Re-)Enable external switch spdo_48k | |
3074 | */ | |
3075 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); | |
3076 | #endif /* USE_VAR48KRATE */ | |
3077 | ||
3078 | if (snd_cmipci_create_gameport(cm, dev) < 0) | |
3079 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
3080 | ||
3081 | snd_card_set_dev(card, &pci->dev); | |
3082 | ||
3083 | *rcmipci = cm; | |
3084 | return 0; | |
3085 | } | |
3086 | ||
3087 | /* | |
3088 | */ | |
3089 | ||
3090 | MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); | |
3091 | ||
3092 | static int __devinit snd_cmipci_probe(struct pci_dev *pci, | |
3093 | const struct pci_device_id *pci_id) | |
3094 | { | |
3095 | static int dev; | |
2cbdb686 TI |
3096 | struct snd_card *card; |
3097 | struct cmipci *cm; | |
1da177e4 LT |
3098 | int err; |
3099 | ||
3100 | if (dev >= SNDRV_CARDS) | |
3101 | return -ENODEV; | |
3102 | if (! enable[dev]) { | |
3103 | dev++; | |
3104 | return -ENOENT; | |
3105 | } | |
3106 | ||
3107 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); | |
3108 | if (card == NULL) | |
3109 | return -ENOMEM; | |
3110 | ||
3111 | switch (pci->device) { | |
3112 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
3113 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
3114 | strcpy(card->driver, "CMI8738"); | |
3115 | break; | |
3116 | case PCI_DEVICE_ID_CMEDIA_CM8338A: | |
3117 | case PCI_DEVICE_ID_CMEDIA_CM8338B: | |
3118 | strcpy(card->driver, "CMI8338"); | |
3119 | break; | |
3120 | default: | |
3121 | strcpy(card->driver, "CMIPCI"); | |
3122 | break; | |
3123 | } | |
3124 | ||
3125 | if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { | |
3126 | snd_card_free(card); | |
3127 | return err; | |
3128 | } | |
cb60e5f5 | 3129 | card->private_data = cm; |
1da177e4 | 3130 | |
1da177e4 LT |
3131 | if ((err = snd_card_register(card)) < 0) { |
3132 | snd_card_free(card); | |
3133 | return err; | |
3134 | } | |
3135 | pci_set_drvdata(pci, card); | |
3136 | dev++; | |
3137 | return 0; | |
3138 | ||
3139 | } | |
3140 | ||
3141 | static void __devexit snd_cmipci_remove(struct pci_dev *pci) | |
3142 | { | |
3143 | snd_card_free(pci_get_drvdata(pci)); | |
3144 | pci_set_drvdata(pci, NULL); | |
3145 | } | |
3146 | ||
3147 | ||
cb60e5f5 TI |
3148 | #ifdef CONFIG_PM |
3149 | /* | |
3150 | * power management | |
3151 | */ | |
3152 | static unsigned char saved_regs[] = { | |
3153 | CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, | |
3154 | CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, | |
3155 | CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, | |
3156 | CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, | |
3157 | CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, | |
3158 | }; | |
3159 | ||
3160 | static unsigned char saved_mixers[] = { | |
3161 | SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, | |
3162 | SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, | |
3163 | SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, | |
3164 | SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, | |
3165 | SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, | |
3166 | SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, | |
3167 | CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, | |
3168 | SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, | |
3169 | }; | |
3170 | ||
3171 | static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state) | |
3172 | { | |
3173 | struct snd_card *card = pci_get_drvdata(pci); | |
3174 | struct cmipci *cm = card->private_data; | |
3175 | int i; | |
3176 | ||
3177 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
3178 | ||
3179 | snd_pcm_suspend_all(cm->pcm); | |
3180 | snd_pcm_suspend_all(cm->pcm2); | |
3181 | snd_pcm_suspend_all(cm->pcm_spdif); | |
3182 | ||
3183 | /* save registers */ | |
3184 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3185 | cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); | |
3186 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3187 | cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); | |
3188 | ||
3189 | /* disable ints */ | |
3190 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
3191 | ||
cb60e5f5 TI |
3192 | pci_disable_device(pci); |
3193 | pci_save_state(pci); | |
30b35399 | 3194 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
cb60e5f5 TI |
3195 | return 0; |
3196 | } | |
3197 | ||
3198 | static int snd_cmipci_resume(struct pci_dev *pci) | |
3199 | { | |
3200 | struct snd_card *card = pci_get_drvdata(pci); | |
3201 | struct cmipci *cm = card->private_data; | |
3202 | int i; | |
3203 | ||
cb60e5f5 | 3204 | pci_set_power_state(pci, PCI_D0); |
30b35399 TI |
3205 | pci_restore_state(pci); |
3206 | if (pci_enable_device(pci) < 0) { | |
3207 | printk(KERN_ERR "cmipci: pci_enable_device failed, " | |
3208 | "disabling device\n"); | |
3209 | snd_card_disconnect(card); | |
3210 | return -EIO; | |
3211 | } | |
cb60e5f5 TI |
3212 | pci_set_master(pci); |
3213 | ||
3214 | /* reset / initialize to a sane state */ | |
3215 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
3216 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
3217 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
3218 | snd_cmipci_mixer_write(cm, 0, 0); | |
3219 | ||
3220 | /* restore registers */ | |
3221 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3222 | snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); | |
3223 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3224 | snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); | |
3225 | ||
3226 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
3227 | return 0; | |
3228 | } | |
3229 | #endif /* CONFIG_PM */ | |
3230 | ||
1da177e4 LT |
3231 | static struct pci_driver driver = { |
3232 | .name = "C-Media PCI", | |
3233 | .id_table = snd_cmipci_ids, | |
3234 | .probe = snd_cmipci_probe, | |
3235 | .remove = __devexit_p(snd_cmipci_remove), | |
cb60e5f5 TI |
3236 | #ifdef CONFIG_PM |
3237 | .suspend = snd_cmipci_suspend, | |
3238 | .resume = snd_cmipci_resume, | |
3239 | #endif | |
1da177e4 LT |
3240 | }; |
3241 | ||
3242 | static int __init alsa_card_cmipci_init(void) | |
3243 | { | |
01d25d46 | 3244 | return pci_register_driver(&driver); |
1da177e4 LT |
3245 | } |
3246 | ||
3247 | static void __exit alsa_card_cmipci_exit(void) | |
3248 | { | |
3249 | pci_unregister_driver(&driver); | |
3250 | } | |
3251 | ||
3252 | module_init(alsa_card_cmipci_init) | |
3253 | module_exit(alsa_card_cmipci_exit) |