Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright (c) by Jaroslav Kysela <perex@suse.cz> | |
3 | * Abramo Bagnara <abramo@alsa-project.org> | |
4 | * Cirrus Logic, Inc. | |
5 | * Routines for control of Cirrus Logic CS461x chips | |
6 | * | |
7 | * KNOWN BUGS: | |
8 | * - Sometimes the SPDIF input DSP tasks get's unsynchronized | |
9 | * and the SPDIF get somewhat "distorcionated", or/and left right channel | |
10 | * are swapped. To get around this problem when it happens, mute and unmute | |
11 | * the SPDIF input mixer controll. | |
12 | * - On the Hercules Game Theater XP the amplifier are sometimes turned | |
13 | * off on inadecuate moments which causes distorcions on sound. | |
14 | * | |
15 | * TODO: | |
16 | * - Secondary CODEC on some soundcards | |
17 | * - SPDIF input support for other sample rates then 48khz | |
18 | * - Posibility to mix the SPDIF output with analog sources. | |
19 | * - PCM channels for Center and LFE on secondary codec | |
20 | * | |
21 | * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which | |
22 | * is default configuration), no SPDIF, no secondary codec, no | |
23 | * multi channel PCM. But known to work. | |
24 | * | |
25 | * FINALLY: A credit to the developers Tom and Jordan | |
26 | * at Cirrus for have helping me out with the DSP, however we | |
27 | * still don't have sufficient documentation and technical | |
28 | * references to be able to implement all fancy feutures | |
29 | * supported by the cs46xx DSP's. | |
30 | * Benny <benny@hostmobility.com> | |
31 | * | |
32 | * This program is free software; you can redistribute it and/or modify | |
33 | * it under the terms of the GNU General Public License as published by | |
34 | * the Free Software Foundation; either version 2 of the License, or | |
35 | * (at your option) any later version. | |
36 | * | |
37 | * This program is distributed in the hope that it will be useful, | |
38 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
39 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
40 | * GNU General Public License for more details. | |
41 | * | |
42 | * You should have received a copy of the GNU General Public License | |
43 | * along with this program; if not, write to the Free Software | |
44 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
45 | * | |
46 | */ | |
47 | ||
48 | #include <sound/driver.h> | |
49 | #include <linux/delay.h> | |
50 | #include <linux/pci.h> | |
51 | #include <linux/pm.h> | |
52 | #include <linux/init.h> | |
53 | #include <linux/interrupt.h> | |
54 | #include <linux/slab.h> | |
55 | #include <linux/gameport.h> | |
62932df8 IM |
56 | #include <linux/mutex.h> |
57 | ||
1da177e4 LT |
58 | |
59 | #include <sound/core.h> | |
60 | #include <sound/control.h> | |
61 | #include <sound/info.h> | |
62 | #include <sound/pcm.h> | |
63 | #include <sound/pcm_params.h> | |
64 | #include <sound/cs46xx.h> | |
65 | ||
66 | #include <asm/io.h> | |
67 | ||
68 | #include "cs46xx_lib.h" | |
69 | #include "dsp_spos.h" | |
70 | ||
3d19f804 | 71 | static void amp_voyetra(struct snd_cs46xx *chip, int change); |
1da177e4 LT |
72 | |
73 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 TI |
74 | static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; |
75 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; | |
76 | static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; | |
77 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; | |
78 | static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; | |
79 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; | |
1da177e4 LT |
80 | #endif |
81 | ||
3d19f804 TI |
82 | static struct snd_pcm_ops snd_cs46xx_playback_ops; |
83 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; | |
84 | static struct snd_pcm_ops snd_cs46xx_capture_ops; | |
85 | static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; | |
1da177e4 | 86 | |
3d19f804 | 87 | static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, |
1da177e4 LT |
88 | unsigned short reg, |
89 | int codec_index) | |
90 | { | |
91 | int count; | |
92 | unsigned short result,tmp; | |
93 | u32 offset = 0; | |
94 | snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) || | |
95 | (codec_index == CS46XX_SECONDARY_CODEC_INDEX), | |
96 | return -EINVAL); | |
97 | ||
98 | chip->active_ctrl(chip, 1); | |
99 | ||
100 | if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) | |
101 | offset = CS46XX_SECONDARY_CODEC_OFFSET; | |
102 | ||
103 | /* | |
104 | * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address | |
105 | * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 | |
106 | * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 | |
107 | * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h | |
108 | * 5. if DCV not cleared, break and return error | |
109 | * 6. Read ACSTS = Status Register = 464h, check VSTS bit | |
110 | */ | |
111 | ||
112 | snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); | |
113 | ||
114 | tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); | |
115 | if ((tmp & ACCTL_VFRM) == 0) { | |
116 | snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp); | |
117 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); | |
118 | msleep(50); | |
119 | tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); | |
120 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); | |
121 | ||
122 | } | |
123 | ||
124 | /* | |
125 | * Setup the AC97 control registers on the CS461x to send the | |
126 | * appropriate command to the AC97 to perform the read. | |
127 | * ACCAD = Command Address Register = 46Ch | |
128 | * ACCDA = Command Data Register = 470h | |
129 | * ACCTL = Control Register = 460h | |
130 | * set DCV - will clear when process completed | |
131 | * set CRW - Read command | |
132 | * set VFRM - valid frame enabled | |
133 | * set ESYN - ASYNC generation enabled | |
134 | * set RSTN - ARST# inactive, AC97 codec not reset | |
135 | */ | |
136 | ||
137 | snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); | |
138 | snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); | |
139 | if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { | |
140 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | | |
141 | ACCTL_VFRM | ACCTL_ESYN | | |
142 | ACCTL_RSTN); | |
143 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | | |
144 | ACCTL_VFRM | ACCTL_ESYN | | |
145 | ACCTL_RSTN); | |
146 | } else { | |
147 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | | |
148 | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | | |
149 | ACCTL_RSTN); | |
150 | } | |
151 | ||
152 | /* | |
153 | * Wait for the read to occur. | |
154 | */ | |
155 | for (count = 0; count < 1000; count++) { | |
156 | /* | |
157 | * First, we want to wait for a short time. | |
158 | */ | |
159 | udelay(10); | |
160 | /* | |
161 | * Now, check to see if the read has completed. | |
162 | * ACCTL = 460h, DCV should be reset by now and 460h = 17h | |
163 | */ | |
164 | if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) | |
165 | goto ok1; | |
166 | } | |
167 | ||
99b359ba | 168 | snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); |
1da177e4 LT |
169 | result = 0xffff; |
170 | goto end; | |
171 | ||
172 | ok1: | |
173 | /* | |
174 | * Wait for the valid status bit to go active. | |
175 | */ | |
176 | for (count = 0; count < 100; count++) { | |
177 | /* | |
178 | * Read the AC97 status register. | |
179 | * ACSTS = Status Register = 464h | |
180 | * VSTS - Valid Status | |
181 | */ | |
182 | if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) | |
183 | goto ok2; | |
184 | udelay(10); | |
185 | } | |
186 | ||
99b359ba | 187 | snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg); |
1da177e4 LT |
188 | result = 0xffff; |
189 | goto end; | |
190 | ||
191 | ok2: | |
192 | /* | |
193 | * Read the data returned from the AC97 register. | |
194 | * ACSDA = Status Data Register = 474h | |
195 | */ | |
196 | #if 0 | |
197 | printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, | |
198 | snd_cs46xx_peekBA0(chip, BA0_ACSDA), | |
199 | snd_cs46xx_peekBA0(chip, BA0_ACCAD)); | |
200 | #endif | |
201 | ||
202 | //snd_cs46xx_peekBA0(chip, BA0_ACCAD); | |
203 | result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); | |
204 | end: | |
205 | chip->active_ctrl(chip, -1); | |
206 | return result; | |
207 | } | |
208 | ||
3d19f804 | 209 | static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, |
1da177e4 LT |
210 | unsigned short reg) |
211 | { | |
3d19f804 | 212 | struct snd_cs46xx *chip = ac97->private_data; |
1da177e4 LT |
213 | unsigned short val; |
214 | int codec_index = ac97->num; | |
215 | ||
216 | snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX || | |
217 | codec_index == CS46XX_SECONDARY_CODEC_INDEX, | |
218 | return 0xffff); | |
219 | ||
220 | val = snd_cs46xx_codec_read(chip, reg, codec_index); | |
221 | ||
222 | return val; | |
223 | } | |
224 | ||
225 | ||
3d19f804 | 226 | static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, |
1da177e4 LT |
227 | unsigned short reg, |
228 | unsigned short val, | |
229 | int codec_index) | |
230 | { | |
231 | int count; | |
232 | ||
233 | snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) || | |
234 | (codec_index == CS46XX_SECONDARY_CODEC_INDEX), | |
235 | return); | |
236 | ||
237 | chip->active_ctrl(chip, 1); | |
238 | ||
239 | /* | |
240 | * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address | |
241 | * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 | |
242 | * 3. Write ACCTL = Control Register = 460h for initiating the write | |
243 | * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h | |
244 | * 5. if DCV not cleared, break and return error | |
245 | */ | |
246 | ||
247 | /* | |
248 | * Setup the AC97 control registers on the CS461x to send the | |
249 | * appropriate command to the AC97 to perform the read. | |
250 | * ACCAD = Command Address Register = 46Ch | |
251 | * ACCDA = Command Data Register = 470h | |
252 | * ACCTL = Control Register = 460h | |
253 | * set DCV - will clear when process completed | |
254 | * reset CRW - Write command | |
255 | * set VFRM - valid frame enabled | |
256 | * set ESYN - ASYNC generation enabled | |
257 | * set RSTN - ARST# inactive, AC97 codec not reset | |
258 | */ | |
259 | snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); | |
260 | snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); | |
261 | snd_cs46xx_peekBA0(chip, BA0_ACCTL); | |
262 | ||
263 | if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { | |
264 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | | |
265 | ACCTL_ESYN | ACCTL_RSTN); | |
266 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | | |
267 | ACCTL_ESYN | ACCTL_RSTN); | |
268 | } else { | |
269 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | | |
270 | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); | |
271 | } | |
272 | ||
273 | for (count = 0; count < 4000; count++) { | |
274 | /* | |
275 | * First, we want to wait for a short time. | |
276 | */ | |
277 | udelay(10); | |
278 | /* | |
279 | * Now, check to see if the write has completed. | |
280 | * ACCTL = 460h, DCV should be reset by now and 460h = 07h | |
281 | */ | |
282 | if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { | |
283 | goto end; | |
284 | } | |
285 | } | |
99b359ba | 286 | snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val); |
1da177e4 LT |
287 | end: |
288 | chip->active_ctrl(chip, -1); | |
289 | } | |
290 | ||
3d19f804 | 291 | static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, |
1da177e4 LT |
292 | unsigned short reg, |
293 | unsigned short val) | |
294 | { | |
3d19f804 | 295 | struct snd_cs46xx *chip = ac97->private_data; |
1da177e4 LT |
296 | int codec_index = ac97->num; |
297 | ||
298 | snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX || | |
299 | codec_index == CS46XX_SECONDARY_CODEC_INDEX, | |
300 | return); | |
301 | ||
302 | snd_cs46xx_codec_write(chip, reg, val, codec_index); | |
303 | } | |
304 | ||
305 | ||
306 | /* | |
307 | * Chip initialization | |
308 | */ | |
309 | ||
3d19f804 | 310 | int snd_cs46xx_download(struct snd_cs46xx *chip, |
1da177e4 LT |
311 | u32 *src, |
312 | unsigned long offset, | |
313 | unsigned long len) | |
314 | { | |
315 | void __iomem *dst; | |
316 | unsigned int bank = offset >> 16; | |
317 | offset = offset & 0xffff; | |
318 | ||
319 | snd_assert(!(offset & 3) && !(len & 3), return -EINVAL); | |
320 | dst = chip->region.idx[bank+1].remap_addr + offset; | |
321 | len /= sizeof(u32); | |
322 | ||
323 | /* writel already converts 32-bit value to right endianess */ | |
324 | while (len-- > 0) { | |
325 | writel(*src++, dst); | |
326 | dst += sizeof(u32); | |
327 | } | |
328 | return 0; | |
329 | } | |
330 | ||
331 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
332 | ||
333 | #include "imgs/cwc4630.h" | |
334 | #include "imgs/cwcasync.h" | |
335 | #include "imgs/cwcsnoop.h" | |
336 | #include "imgs/cwcbinhack.h" | |
337 | #include "imgs/cwcdma.h" | |
338 | ||
3d19f804 | 339 | int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, |
1da177e4 LT |
340 | unsigned long offset, |
341 | unsigned long len) | |
342 | { | |
343 | void __iomem *dst; | |
344 | unsigned int bank = offset >> 16; | |
345 | offset = offset & 0xffff; | |
346 | ||
347 | snd_assert(!(offset & 3) && !(len & 3), return -EINVAL); | |
348 | dst = chip->region.idx[bank+1].remap_addr + offset; | |
349 | len /= sizeof(u32); | |
350 | ||
351 | /* writel already converts 32-bit value to right endianess */ | |
352 | while (len-- > 0) { | |
353 | writel(0, dst); | |
354 | dst += sizeof(u32); | |
355 | } | |
356 | return 0; | |
357 | } | |
358 | ||
359 | #else /* old DSP image */ | |
360 | ||
361 | #include "cs46xx_image.h" | |
362 | ||
3d19f804 | 363 | int snd_cs46xx_download_image(struct snd_cs46xx *chip) |
1da177e4 LT |
364 | { |
365 | int idx, err; | |
366 | unsigned long offset = 0; | |
367 | ||
368 | for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { | |
369 | if ((err = snd_cs46xx_download(chip, | |
370 | &BA1Struct.map[offset], | |
371 | BA1Struct.memory[idx].offset, | |
372 | BA1Struct.memory[idx].size)) < 0) | |
373 | return err; | |
374 | offset += BA1Struct.memory[idx].size >> 2; | |
375 | } | |
376 | return 0; | |
377 | } | |
378 | #endif /* CONFIG_SND_CS46XX_NEW_DSP */ | |
379 | ||
380 | /* | |
381 | * Chip reset | |
382 | */ | |
383 | ||
3d19f804 | 384 | static void snd_cs46xx_reset(struct snd_cs46xx *chip) |
1da177e4 LT |
385 | { |
386 | int idx; | |
387 | ||
388 | /* | |
389 | * Write the reset bit of the SP control register. | |
390 | */ | |
391 | snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); | |
392 | ||
393 | /* | |
394 | * Write the control register. | |
395 | */ | |
396 | snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); | |
397 | ||
398 | /* | |
399 | * Clear the trap registers. | |
400 | */ | |
401 | for (idx = 0; idx < 8; idx++) { | |
402 | snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); | |
403 | snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); | |
404 | } | |
405 | snd_cs46xx_poke(chip, BA1_DREG, 0); | |
406 | ||
407 | /* | |
408 | * Set the frame timer to reflect the number of cycles per frame. | |
409 | */ | |
410 | snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); | |
411 | } | |
412 | ||
3d19f804 | 413 | static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) |
1da177e4 LT |
414 | { |
415 | u32 i, status = 0; | |
416 | /* | |
417 | * Make sure the previous FIFO write operation has completed. | |
418 | */ | |
419 | for(i = 0; i < 50; i++){ | |
420 | status = snd_cs46xx_peekBA0(chip, BA0_SERBST); | |
421 | ||
422 | if( !(status & SERBST_WBSY) ) | |
423 | break; | |
424 | ||
425 | mdelay(retry_timeout); | |
426 | } | |
427 | ||
428 | if(status & SERBST_WBSY) { | |
429 | snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n"); | |
430 | ||
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
3d19f804 | 437 | static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) |
1da177e4 LT |
438 | { |
439 | int idx, powerdown = 0; | |
440 | unsigned int tmp; | |
441 | ||
442 | /* | |
443 | * See if the devices are powered down. If so, we must power them up first | |
444 | * or they will not respond. | |
445 | */ | |
446 | tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); | |
447 | if (!(tmp & CLKCR1_SWCE)) { | |
448 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); | |
449 | powerdown = 1; | |
450 | } | |
451 | ||
452 | /* | |
453 | * We want to clear out the serial port FIFOs so we don't end up playing | |
454 | * whatever random garbage happens to be in them. We fill the sample FIFOS | |
455 | * with zero (silence). | |
456 | */ | |
457 | snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); | |
458 | ||
459 | /* | |
460 | * Fill all 256 sample FIFO locations. | |
461 | */ | |
462 | for (idx = 0; idx < 0xFF; idx++) { | |
463 | /* | |
464 | * Make sure the previous FIFO write operation has completed. | |
465 | */ | |
466 | if (cs46xx_wait_for_fifo(chip,1)) { | |
467 | snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx); | |
468 | ||
469 | if (powerdown) | |
470 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); | |
471 | ||
472 | break; | |
473 | } | |
474 | /* | |
475 | * Write the serial port FIFO index. | |
476 | */ | |
477 | snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); | |
478 | /* | |
479 | * Tell the serial port to load the new value into the FIFO location. | |
480 | */ | |
481 | snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); | |
482 | } | |
483 | /* | |
484 | * Now, if we powered up the devices, then power them back down again. | |
485 | * This is kinda ugly, but should never happen. | |
486 | */ | |
487 | if (powerdown) | |
488 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); | |
489 | } | |
490 | ||
3d19f804 | 491 | static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) |
1da177e4 LT |
492 | { |
493 | int cnt; | |
494 | ||
495 | /* | |
496 | * Set the frame timer to reflect the number of cycles per frame. | |
497 | */ | |
498 | snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); | |
499 | /* | |
500 | * Turn on the run, run at frame, and DMA enable bits in the local copy of | |
501 | * the SP control register. | |
502 | */ | |
503 | snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); | |
504 | /* | |
505 | * Wait until the run at frame bit resets itself in the SP control | |
506 | * register. | |
507 | */ | |
508 | for (cnt = 0; cnt < 25; cnt++) { | |
509 | udelay(50); | |
510 | if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) | |
511 | break; | |
512 | } | |
513 | ||
514 | if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) | |
99b359ba | 515 | snd_printk(KERN_ERR "SPCR_RUNFR never reset\n"); |
1da177e4 LT |
516 | } |
517 | ||
3d19f804 | 518 | static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) |
1da177e4 LT |
519 | { |
520 | /* | |
521 | * Turn off the run, run at frame, and DMA enable bits in the local copy of | |
522 | * the SP control register. | |
523 | */ | |
524 | snd_cs46xx_poke(chip, BA1_SPCR, 0); | |
525 | } | |
526 | ||
527 | /* | |
528 | * Sample rate routines | |
529 | */ | |
530 | ||
531 | #define GOF_PER_SEC 200 | |
532 | ||
3d19f804 | 533 | static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) |
1da177e4 LT |
534 | { |
535 | unsigned long flags; | |
536 | unsigned int tmp1, tmp2; | |
537 | unsigned int phiIncr; | |
538 | unsigned int correctionPerGOF, correctionPerSec; | |
539 | ||
540 | /* | |
541 | * Compute the values used to drive the actual sample rate conversion. | |
542 | * The following formulas are being computed, using inline assembly | |
543 | * since we need to use 64 bit arithmetic to compute the values: | |
544 | * | |
545 | * phiIncr = floor((Fs,in * 2^26) / Fs,out) | |
546 | * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / | |
547 | * GOF_PER_SEC) | |
548 | * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M | |
549 | * GOF_PER_SEC * correctionPerGOF | |
550 | * | |
551 | * i.e. | |
552 | * | |
553 | * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) | |
554 | * correctionPerGOF:correctionPerSec = | |
555 | * dividend:remainder(ulOther / GOF_PER_SEC) | |
556 | */ | |
557 | tmp1 = rate << 16; | |
558 | phiIncr = tmp1 / 48000; | |
559 | tmp1 -= phiIncr * 48000; | |
560 | tmp1 <<= 10; | |
561 | phiIncr <<= 10; | |
562 | tmp2 = tmp1 / 48000; | |
563 | phiIncr += tmp2; | |
564 | tmp1 -= tmp2 * 48000; | |
565 | correctionPerGOF = tmp1 / GOF_PER_SEC; | |
566 | tmp1 -= correctionPerGOF * GOF_PER_SEC; | |
567 | correctionPerSec = tmp1; | |
568 | ||
569 | /* | |
570 | * Fill in the SampleRateConverter control block. | |
571 | */ | |
572 | spin_lock_irqsave(&chip->reg_lock, flags); | |
573 | snd_cs46xx_poke(chip, BA1_PSRC, | |
574 | ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); | |
575 | snd_cs46xx_poke(chip, BA1_PPI, phiIncr); | |
576 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
577 | } | |
578 | ||
3d19f804 | 579 | static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) |
1da177e4 LT |
580 | { |
581 | unsigned long flags; | |
582 | unsigned int phiIncr, coeffIncr, tmp1, tmp2; | |
583 | unsigned int correctionPerGOF, correctionPerSec, initialDelay; | |
584 | unsigned int frameGroupLength, cnt; | |
585 | ||
586 | /* | |
587 | * We can only decimate by up to a factor of 1/9th the hardware rate. | |
588 | * Correct the value if an attempt is made to stray outside that limit. | |
589 | */ | |
590 | if ((rate * 9) < 48000) | |
591 | rate = 48000 / 9; | |
592 | ||
593 | /* | |
594 | * We can not capture at at rate greater than the Input Rate (48000). | |
595 | * Return an error if an attempt is made to stray outside that limit. | |
596 | */ | |
597 | if (rate > 48000) | |
598 | rate = 48000; | |
599 | ||
600 | /* | |
601 | * Compute the values used to drive the actual sample rate conversion. | |
602 | * The following formulas are being computed, using inline assembly | |
603 | * since we need to use 64 bit arithmetic to compute the values: | |
604 | * | |
605 | * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) | |
606 | * phiIncr = floor((Fs,in * 2^26) / Fs,out) | |
607 | * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / | |
608 | * GOF_PER_SEC) | |
609 | * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - | |
610 | * GOF_PER_SEC * correctionPerGOF | |
611 | * initialDelay = ceil((24 * Fs,in) / Fs,out) | |
612 | * | |
613 | * i.e. | |
614 | * | |
615 | * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) | |
616 | * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) | |
617 | * correctionPerGOF:correctionPerSec = | |
618 | * dividend:remainder(ulOther / GOF_PER_SEC) | |
619 | * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) | |
620 | */ | |
621 | ||
622 | tmp1 = rate << 16; | |
623 | coeffIncr = tmp1 / 48000; | |
624 | tmp1 -= coeffIncr * 48000; | |
625 | tmp1 <<= 7; | |
626 | coeffIncr <<= 7; | |
627 | coeffIncr += tmp1 / 48000; | |
628 | coeffIncr ^= 0xFFFFFFFF; | |
629 | coeffIncr++; | |
630 | tmp1 = 48000 << 16; | |
631 | phiIncr = tmp1 / rate; | |
632 | tmp1 -= phiIncr * rate; | |
633 | tmp1 <<= 10; | |
634 | phiIncr <<= 10; | |
635 | tmp2 = tmp1 / rate; | |
636 | phiIncr += tmp2; | |
637 | tmp1 -= tmp2 * rate; | |
638 | correctionPerGOF = tmp1 / GOF_PER_SEC; | |
639 | tmp1 -= correctionPerGOF * GOF_PER_SEC; | |
640 | correctionPerSec = tmp1; | |
641 | initialDelay = ((48000 * 24) + rate - 1) / rate; | |
642 | ||
643 | /* | |
644 | * Fill in the VariDecimate control block. | |
645 | */ | |
646 | spin_lock_irqsave(&chip->reg_lock, flags); | |
647 | snd_cs46xx_poke(chip, BA1_CSRC, | |
648 | ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); | |
649 | snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); | |
650 | snd_cs46xx_poke(chip, BA1_CD, | |
651 | (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); | |
652 | snd_cs46xx_poke(chip, BA1_CPI, phiIncr); | |
653 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
654 | ||
655 | /* | |
656 | * Figure out the frame group length for the write back task. Basically, | |
657 | * this is just the factors of 24000 (2^6*3*5^3) that are not present in | |
658 | * the output sample rate. | |
659 | */ | |
660 | frameGroupLength = 1; | |
661 | for (cnt = 2; cnt <= 64; cnt *= 2) { | |
662 | if (((rate / cnt) * cnt) != rate) | |
663 | frameGroupLength *= 2; | |
664 | } | |
665 | if (((rate / 3) * 3) != rate) { | |
666 | frameGroupLength *= 3; | |
667 | } | |
668 | for (cnt = 5; cnt <= 125; cnt *= 5) { | |
669 | if (((rate / cnt) * cnt) != rate) | |
670 | frameGroupLength *= 5; | |
671 | } | |
672 | ||
673 | /* | |
674 | * Fill in the WriteBack control block. | |
675 | */ | |
676 | spin_lock_irqsave(&chip->reg_lock, flags); | |
677 | snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); | |
678 | snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); | |
679 | snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); | |
680 | snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); | |
681 | snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); | |
682 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
683 | } | |
684 | ||
685 | /* | |
686 | * PCM part | |
687 | */ | |
688 | ||
3d19f804 TI |
689 | static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, |
690 | struct snd_pcm_indirect *rec, size_t bytes) | |
1da177e4 | 691 | { |
3d19f804 TI |
692 | struct snd_pcm_runtime *runtime = substream->runtime; |
693 | struct snd_cs46xx_pcm * cpcm = runtime->private_data; | |
1da177e4 LT |
694 | memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); |
695 | } | |
696 | ||
3d19f804 | 697 | static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) |
1da177e4 | 698 | { |
3d19f804 TI |
699 | struct snd_pcm_runtime *runtime = substream->runtime; |
700 | struct snd_cs46xx_pcm * cpcm = runtime->private_data; | |
1da177e4 LT |
701 | snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy); |
702 | return 0; | |
703 | } | |
704 | ||
3d19f804 TI |
705 | static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, |
706 | struct snd_pcm_indirect *rec, size_t bytes) | |
1da177e4 | 707 | { |
3d19f804 TI |
708 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
709 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
710 | memcpy(runtime->dma_area + rec->sw_data, |
711 | chip->capt.hw_buf.area + rec->hw_data, bytes); | |
712 | } | |
713 | ||
3d19f804 | 714 | static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) |
1da177e4 | 715 | { |
3d19f804 | 716 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
717 | snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy); |
718 | return 0; | |
719 | } | |
720 | ||
3d19f804 | 721 | static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 722 | { |
3d19f804 | 723 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 724 | size_t ptr; |
3d19f804 | 725 | struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; |
1da177e4 LT |
726 | snd_assert (cpcm->pcm_channel,return -ENXIO); |
727 | ||
728 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
729 | ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); | |
730 | #else | |
731 | ptr = snd_cs46xx_peek(chip, BA1_PBA); | |
732 | #endif | |
733 | ptr -= cpcm->hw_buf.addr; | |
734 | return ptr >> cpcm->shift; | |
735 | } | |
736 | ||
3d19f804 | 737 | static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 738 | { |
3d19f804 | 739 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 740 | size_t ptr; |
3d19f804 | 741 | struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; |
1da177e4 LT |
742 | |
743 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
744 | snd_assert (cpcm->pcm_channel,return -ENXIO); | |
745 | ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); | |
746 | #else | |
747 | ptr = snd_cs46xx_peek(chip, BA1_PBA); | |
748 | #endif | |
749 | ptr -= cpcm->hw_buf.addr; | |
750 | return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); | |
751 | } | |
752 | ||
3d19f804 | 753 | static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 754 | { |
3d19f804 | 755 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
756 | size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; |
757 | return ptr >> chip->capt.shift; | |
758 | } | |
759 | ||
3d19f804 | 760 | static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 761 | { |
3d19f804 | 762 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
763 | size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; |
764 | return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); | |
765 | } | |
766 | ||
3d19f804 | 767 | static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
768 | int cmd) |
769 | { | |
3d19f804 TI |
770 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
771 | /*struct snd_pcm_runtime *runtime = substream->runtime;*/ | |
1da177e4 LT |
772 | int result = 0; |
773 | ||
774 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 775 | struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; |
1da177e4 LT |
776 | if (! cpcm->pcm_channel) { |
777 | return -ENXIO; | |
778 | } | |
779 | #endif | |
780 | switch (cmd) { | |
781 | case SNDRV_PCM_TRIGGER_START: | |
782 | case SNDRV_PCM_TRIGGER_RESUME: | |
783 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
784 | /* magic value to unmute PCM stream playback volume */ | |
785 | snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + | |
786 | SCBVolumeCtrl) << 2, 0x80008000); | |
787 | ||
788 | if (cpcm->pcm_channel->unlinked) | |
789 | cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); | |
790 | ||
791 | if (substream->runtime->periods != CS46XX_FRAGS) | |
792 | snd_cs46xx_playback_transfer(substream); | |
793 | #else | |
794 | spin_lock(&chip->reg_lock); | |
795 | if (substream->runtime->periods != CS46XX_FRAGS) | |
796 | snd_cs46xx_playback_transfer(substream); | |
797 | { unsigned int tmp; | |
798 | tmp = snd_cs46xx_peek(chip, BA1_PCTL); | |
799 | tmp &= 0x0000ffff; | |
800 | snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); | |
801 | } | |
802 | spin_unlock(&chip->reg_lock); | |
803 | #endif | |
804 | break; | |
805 | case SNDRV_PCM_TRIGGER_STOP: | |
806 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
807 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
808 | /* magic mute channel */ | |
809 | snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + | |
810 | SCBVolumeCtrl) << 2, 0xffffffff); | |
811 | ||
812 | if (!cpcm->pcm_channel->unlinked) | |
813 | cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); | |
814 | #else | |
815 | spin_lock(&chip->reg_lock); | |
816 | { unsigned int tmp; | |
817 | tmp = snd_cs46xx_peek(chip, BA1_PCTL); | |
818 | tmp &= 0x0000ffff; | |
819 | snd_cs46xx_poke(chip, BA1_PCTL, tmp); | |
820 | } | |
821 | spin_unlock(&chip->reg_lock); | |
822 | #endif | |
823 | break; | |
824 | default: | |
825 | result = -EINVAL; | |
826 | break; | |
827 | } | |
828 | ||
829 | return result; | |
830 | } | |
831 | ||
3d19f804 | 832 | static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
833 | int cmd) |
834 | { | |
3d19f804 | 835 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
836 | unsigned int tmp; |
837 | int result = 0; | |
838 | ||
839 | spin_lock(&chip->reg_lock); | |
840 | switch (cmd) { | |
841 | case SNDRV_PCM_TRIGGER_START: | |
842 | case SNDRV_PCM_TRIGGER_RESUME: | |
843 | tmp = snd_cs46xx_peek(chip, BA1_CCTL); | |
844 | tmp &= 0xffff0000; | |
845 | snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); | |
846 | break; | |
847 | case SNDRV_PCM_TRIGGER_STOP: | |
848 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
849 | tmp = snd_cs46xx_peek(chip, BA1_CCTL); | |
850 | tmp &= 0xffff0000; | |
851 | snd_cs46xx_poke(chip, BA1_CCTL, tmp); | |
852 | break; | |
853 | default: | |
854 | result = -EINVAL; | |
855 | break; | |
856 | } | |
857 | spin_unlock(&chip->reg_lock); | |
858 | ||
859 | return result; | |
860 | } | |
861 | ||
862 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 863 | static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, |
1da177e4 LT |
864 | int sample_rate) |
865 | { | |
866 | ||
867 | /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ | |
868 | if ( cpcm->pcm_channel == NULL) { | |
869 | cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, | |
870 | cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); | |
871 | if (cpcm->pcm_channel == NULL) { | |
872 | snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n"); | |
873 | return -ENOMEM; | |
874 | } | |
875 | cpcm->pcm_channel->sample_rate = sample_rate; | |
876 | } else | |
877 | /* if sample rate is changed */ | |
878 | if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { | |
879 | int unlinked = cpcm->pcm_channel->unlinked; | |
880 | cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); | |
881 | ||
882 | if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm, | |
883 | cpcm->hw_buf.addr, | |
884 | cpcm->pcm_channel_id)) == NULL) { | |
885 | snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n"); | |
886 | return -ENOMEM; | |
887 | } | |
888 | ||
889 | if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); | |
890 | cpcm->pcm_channel->sample_rate = sample_rate; | |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
895 | #endif | |
896 | ||
897 | ||
3d19f804 TI |
898 | static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, |
899 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 900 | { |
3d19f804 TI |
901 | struct snd_pcm_runtime *runtime = substream->runtime; |
902 | struct snd_cs46xx_pcm *cpcm; | |
1da177e4 LT |
903 | int err; |
904 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 905 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
906 | int sample_rate = params_rate(hw_params); |
907 | int period_size = params_period_bytes(hw_params); | |
908 | #endif | |
909 | cpcm = runtime->private_data; | |
910 | ||
911 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
912 | snd_assert (sample_rate != 0, return -ENXIO); | |
913 | ||
62932df8 | 914 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
915 | |
916 | if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { | |
62932df8 | 917 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
918 | return -ENXIO; |
919 | } | |
920 | ||
921 | snd_assert (cpcm->pcm_channel != NULL); | |
922 | if (!cpcm->pcm_channel) { | |
62932df8 | 923 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
924 | return -ENXIO; |
925 | } | |
926 | ||
927 | ||
928 | if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { | |
62932df8 | 929 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
930 | return -EINVAL; |
931 | } | |
932 | ||
933 | snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n", | |
934 | period_size, params_periods(hw_params), | |
935 | params_buffer_bytes(hw_params)); | |
936 | #endif | |
937 | ||
938 | if (params_periods(hw_params) == CS46XX_FRAGS) { | |
939 | if (runtime->dma_area != cpcm->hw_buf.area) | |
940 | snd_pcm_lib_free_pages(substream); | |
941 | runtime->dma_area = cpcm->hw_buf.area; | |
942 | runtime->dma_addr = cpcm->hw_buf.addr; | |
943 | runtime->dma_bytes = cpcm->hw_buf.bytes; | |
944 | ||
945 | ||
946 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
947 | if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { | |
948 | substream->ops = &snd_cs46xx_playback_ops; | |
949 | } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { | |
950 | substream->ops = &snd_cs46xx_playback_rear_ops; | |
951 | } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { | |
952 | substream->ops = &snd_cs46xx_playback_clfe_ops; | |
953 | } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { | |
954 | substream->ops = &snd_cs46xx_playback_iec958_ops; | |
955 | } else { | |
956 | snd_assert(0); | |
957 | } | |
958 | #else | |
959 | substream->ops = &snd_cs46xx_playback_ops; | |
960 | #endif | |
961 | ||
962 | } else { | |
963 | if (runtime->dma_area == cpcm->hw_buf.area) { | |
964 | runtime->dma_area = NULL; | |
965 | runtime->dma_addr = 0; | |
966 | runtime->dma_bytes = 0; | |
967 | } | |
968 | if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { | |
969 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
62932df8 | 970 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
971 | #endif |
972 | return err; | |
973 | } | |
974 | ||
975 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
976 | if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { | |
977 | substream->ops = &snd_cs46xx_playback_indirect_ops; | |
978 | } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { | |
979 | substream->ops = &snd_cs46xx_playback_indirect_rear_ops; | |
980 | } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { | |
981 | substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; | |
982 | } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { | |
983 | substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; | |
984 | } else { | |
985 | snd_assert(0); | |
986 | } | |
987 | #else | |
988 | substream->ops = &snd_cs46xx_playback_indirect_ops; | |
989 | #endif | |
990 | ||
991 | } | |
992 | ||
993 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
62932df8 | 994 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
995 | #endif |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
3d19f804 | 1000 | static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1001 | { |
3d19f804 TI |
1002 | /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ |
1003 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1004 | struct snd_cs46xx_pcm *cpcm; | |
1da177e4 LT |
1005 | |
1006 | cpcm = runtime->private_data; | |
1007 | ||
1008 | /* if play_back open fails, then this function | |
1009 | is called and cpcm can actually be NULL here */ | |
1010 | if (!cpcm) return -ENXIO; | |
1011 | ||
1012 | if (runtime->dma_area != cpcm->hw_buf.area) | |
1013 | snd_pcm_lib_free_pages(substream); | |
1014 | ||
1015 | runtime->dma_area = NULL; | |
1016 | runtime->dma_addr = 0; | |
1017 | runtime->dma_bytes = 0; | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
3d19f804 | 1022 | static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1023 | { |
1024 | unsigned int tmp; | |
1025 | unsigned int pfie; | |
3d19f804 TI |
1026 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1027 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1028 | struct snd_cs46xx_pcm *cpcm; | |
1da177e4 LT |
1029 | |
1030 | cpcm = runtime->private_data; | |
1031 | ||
1032 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1033 | snd_assert (cpcm->pcm_channel != NULL, return -ENXIO); | |
1034 | ||
1035 | pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); | |
1036 | pfie &= ~0x0000f03f; | |
1037 | #else | |
1038 | /* old dsp */ | |
1039 | pfie = snd_cs46xx_peek(chip, BA1_PFIE); | |
1040 | pfie &= ~0x0000f03f; | |
1041 | #endif | |
1042 | ||
1043 | cpcm->shift = 2; | |
1044 | /* if to convert from stereo to mono */ | |
1045 | if (runtime->channels == 1) { | |
1046 | cpcm->shift--; | |
1047 | pfie |= 0x00002000; | |
1048 | } | |
1049 | /* if to convert from 8 bit to 16 bit */ | |
1050 | if (snd_pcm_format_width(runtime->format) == 8) { | |
1051 | cpcm->shift--; | |
1052 | pfie |= 0x00001000; | |
1053 | } | |
1054 | /* if to convert to unsigned */ | |
1055 | if (snd_pcm_format_unsigned(runtime->format)) | |
1056 | pfie |= 0x00008000; | |
1057 | ||
1058 | /* Never convert byte order when sample stream is 8 bit */ | |
1059 | if (snd_pcm_format_width(runtime->format) != 8) { | |
1060 | /* convert from big endian to little endian */ | |
1061 | if (snd_pcm_format_big_endian(runtime->format)) | |
1062 | pfie |= 0x00004000; | |
1063 | } | |
1064 | ||
1065 | memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); | |
1066 | cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); | |
1067 | cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; | |
1068 | ||
1069 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1070 | ||
1071 | tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); | |
1072 | tmp &= ~0x000003ff; | |
1073 | tmp |= (4 << cpcm->shift) - 1; | |
1074 | /* playback transaction count register */ | |
1075 | snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); | |
1076 | ||
1077 | /* playback format && interrupt enable */ | |
1078 | snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); | |
1079 | #else | |
1080 | snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); | |
1081 | tmp = snd_cs46xx_peek(chip, BA1_PDTC); | |
1082 | tmp &= ~0x000003ff; | |
1083 | tmp |= (4 << cpcm->shift) - 1; | |
1084 | snd_cs46xx_poke(chip, BA1_PDTC, tmp); | |
1085 | snd_cs46xx_poke(chip, BA1_PFIE, pfie); | |
1086 | snd_cs46xx_set_play_sample_rate(chip, runtime->rate); | |
1087 | #endif | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
3d19f804 TI |
1092 | static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, |
1093 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1094 | { |
3d19f804 TI |
1095 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1096 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1097 | int err; |
1098 | ||
1099 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1100 | cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); | |
1101 | #endif | |
1102 | if (runtime->periods == CS46XX_FRAGS) { | |
1103 | if (runtime->dma_area != chip->capt.hw_buf.area) | |
1104 | snd_pcm_lib_free_pages(substream); | |
1105 | runtime->dma_area = chip->capt.hw_buf.area; | |
1106 | runtime->dma_addr = chip->capt.hw_buf.addr; | |
1107 | runtime->dma_bytes = chip->capt.hw_buf.bytes; | |
1108 | substream->ops = &snd_cs46xx_capture_ops; | |
1109 | } else { | |
1110 | if (runtime->dma_area == chip->capt.hw_buf.area) { | |
1111 | runtime->dma_area = NULL; | |
1112 | runtime->dma_addr = 0; | |
1113 | runtime->dma_bytes = 0; | |
1114 | } | |
1115 | if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) | |
1116 | return err; | |
1117 | substream->ops = &snd_cs46xx_capture_indirect_ops; | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
3d19f804 | 1123 | static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1124 | { |
3d19f804 TI |
1125 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1126 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1127 | |
1128 | if (runtime->dma_area != chip->capt.hw_buf.area) | |
1129 | snd_pcm_lib_free_pages(substream); | |
1130 | runtime->dma_area = NULL; | |
1131 | runtime->dma_addr = 0; | |
1132 | runtime->dma_bytes = 0; | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
3d19f804 | 1137 | static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1138 | { |
3d19f804 TI |
1139 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1140 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1141 | |
1142 | snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); | |
1143 | chip->capt.shift = 2; | |
1144 | memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); | |
1145 | chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); | |
1146 | chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; | |
1147 | snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
7d12e780 | 1152 | static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) |
1da177e4 | 1153 | { |
3d19f804 | 1154 | struct snd_cs46xx *chip = dev_id; |
1da177e4 LT |
1155 | u32 status1; |
1156 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 1157 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; |
1da177e4 LT |
1158 | u32 status2; |
1159 | int i; | |
3d19f804 | 1160 | struct snd_cs46xx_pcm *cpcm = NULL; |
1da177e4 LT |
1161 | #endif |
1162 | ||
1163 | /* | |
1164 | * Read the Interrupt Status Register to clear the interrupt | |
1165 | */ | |
1166 | status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); | |
1167 | if ((status1 & 0x7fffffff) == 0) { | |
1168 | snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); | |
1169 | return IRQ_NONE; | |
1170 | } | |
1171 | ||
1172 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1173 | status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); | |
1174 | ||
1175 | for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { | |
1176 | if (i <= 15) { | |
1177 | if ( status1 & (1 << i) ) { | |
1178 | if (i == CS46XX_DSP_CAPTURE_CHANNEL) { | |
1179 | if (chip->capt.substream) | |
1180 | snd_pcm_period_elapsed(chip->capt.substream); | |
1181 | } else { | |
1182 | if (ins->pcm_channels[i].active && | |
1183 | ins->pcm_channels[i].private_data && | |
1184 | !ins->pcm_channels[i].unlinked) { | |
1185 | cpcm = ins->pcm_channels[i].private_data; | |
1186 | snd_pcm_period_elapsed(cpcm->substream); | |
1187 | } | |
1188 | } | |
1189 | } | |
1190 | } else { | |
1191 | if ( status2 & (1 << (i - 16))) { | |
1192 | if (ins->pcm_channels[i].active && | |
1193 | ins->pcm_channels[i].private_data && | |
1194 | !ins->pcm_channels[i].unlinked) { | |
1195 | cpcm = ins->pcm_channels[i].private_data; | |
1196 | snd_pcm_period_elapsed(cpcm->substream); | |
1197 | } | |
1198 | } | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | #else | |
1203 | /* old dsp */ | |
1204 | if ((status1 & HISR_VC0) && chip->playback_pcm) { | |
1205 | if (chip->playback_pcm->substream) | |
1206 | snd_pcm_period_elapsed(chip->playback_pcm->substream); | |
1207 | } | |
1208 | if ((status1 & HISR_VC1) && chip->pcm) { | |
1209 | if (chip->capt.substream) | |
1210 | snd_pcm_period_elapsed(chip->capt.substream); | |
1211 | } | |
1212 | #endif | |
1213 | ||
1214 | if ((status1 & HISR_MIDI) && chip->rmidi) { | |
1215 | unsigned char c; | |
1216 | ||
1217 | spin_lock(&chip->reg_lock); | |
1218 | while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { | |
1219 | c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); | |
1220 | if ((chip->midcr & MIDCR_RIE) == 0) | |
1221 | continue; | |
1222 | snd_rawmidi_receive(chip->midi_input, &c, 1); | |
1223 | } | |
1224 | while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { | |
1225 | if ((chip->midcr & MIDCR_TIE) == 0) | |
1226 | break; | |
1227 | if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { | |
1228 | chip->midcr &= ~MIDCR_TIE; | |
1229 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
1230 | break; | |
1231 | } | |
1232 | snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); | |
1233 | } | |
1234 | spin_unlock(&chip->reg_lock); | |
1235 | } | |
1236 | /* | |
1237 | * EOI to the PCI part....reenables interrupts | |
1238 | */ | |
1239 | snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); | |
1240 | ||
1241 | return IRQ_HANDLED; | |
1242 | } | |
1243 | ||
3d19f804 | 1244 | static struct snd_pcm_hardware snd_cs46xx_playback = |
1da177e4 LT |
1245 | { |
1246 | .info = (SNDRV_PCM_INFO_MMAP | | |
1247 | SNDRV_PCM_INFO_INTERLEAVED | | |
41e4845c JK |
1248 | SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ |
1249 | /*SNDRV_PCM_INFO_RESUME*/), | |
1da177e4 LT |
1250 | .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | |
1251 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | | |
1252 | SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), | |
1253 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1254 | .rate_min = 5500, | |
1255 | .rate_max = 48000, | |
1256 | .channels_min = 1, | |
1257 | .channels_max = 2, | |
1258 | .buffer_bytes_max = (256 * 1024), | |
1259 | .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, | |
1260 | .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, | |
1261 | .periods_min = CS46XX_FRAGS, | |
1262 | .periods_max = 1024, | |
1263 | .fifo_size = 0, | |
1264 | }; | |
1265 | ||
3d19f804 | 1266 | static struct snd_pcm_hardware snd_cs46xx_capture = |
1da177e4 LT |
1267 | { |
1268 | .info = (SNDRV_PCM_INFO_MMAP | | |
1269 | SNDRV_PCM_INFO_INTERLEAVED | | |
41e4845c JK |
1270 | SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ |
1271 | /*SNDRV_PCM_INFO_RESUME*/), | |
1da177e4 LT |
1272 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1273 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1274 | .rate_min = 5500, | |
1275 | .rate_max = 48000, | |
1276 | .channels_min = 2, | |
1277 | .channels_max = 2, | |
1278 | .buffer_bytes_max = (256 * 1024), | |
1279 | .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, | |
1280 | .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, | |
1281 | .periods_min = CS46XX_FRAGS, | |
1282 | .periods_max = 1024, | |
1283 | .fifo_size = 0, | |
1284 | }; | |
1285 | ||
1286 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1287 | ||
1288 | static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; | |
1289 | ||
3d19f804 | 1290 | static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { |
1da177e4 LT |
1291 | .count = ARRAY_SIZE(period_sizes), |
1292 | .list = period_sizes, | |
1293 | .mask = 0 | |
1294 | }; | |
1295 | ||
1296 | #endif | |
1297 | ||
3d19f804 | 1298 | static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) |
1da177e4 | 1299 | { |
4d572776 | 1300 | kfree(runtime->private_data); |
1da177e4 LT |
1301 | } |
1302 | ||
3d19f804 | 1303 | static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) |
1da177e4 | 1304 | { |
3d19f804 TI |
1305 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1306 | struct snd_cs46xx_pcm * cpcm; | |
1307 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 1308 | |
e560d8d8 | 1309 | cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); |
1da177e4 LT |
1310 | if (cpcm == NULL) |
1311 | return -ENOMEM; | |
1312 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1313 | PAGE_SIZE, &cpcm->hw_buf) < 0) { | |
1314 | kfree(cpcm); | |
1315 | return -ENOMEM; | |
1316 | } | |
1317 | ||
1318 | runtime->hw = snd_cs46xx_playback; | |
1319 | runtime->private_data = cpcm; | |
1320 | runtime->private_free = snd_cs46xx_pcm_free_substream; | |
1321 | ||
1322 | cpcm->substream = substream; | |
1323 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
62932df8 | 1324 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
1325 | cpcm->pcm_channel = NULL; |
1326 | cpcm->pcm_channel_id = pcm_channel_id; | |
1327 | ||
1328 | ||
1329 | snd_pcm_hw_constraint_list(runtime, 0, | |
1330 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
1331 | &hw_constraints_period_sizes); | |
1332 | ||
62932df8 | 1333 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
1334 | #else |
1335 | chip->playback_pcm = cpcm; /* HACK */ | |
1336 | #endif | |
1337 | ||
1338 | if (chip->accept_valid) | |
1339 | substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; | |
1340 | chip->active_ctrl(chip, 1); | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
3d19f804 | 1345 | static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1346 | { |
1347 | snd_printdd("open front channel\n"); | |
1348 | return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); | |
1349 | } | |
1350 | ||
1351 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 1352 | static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) |
1da177e4 LT |
1353 | { |
1354 | snd_printdd("open rear channel\n"); | |
1355 | ||
1356 | return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); | |
1357 | } | |
1358 | ||
3d19f804 | 1359 | static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) |
1da177e4 LT |
1360 | { |
1361 | snd_printdd("open center - LFE channel\n"); | |
1362 | ||
1363 | return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); | |
1364 | } | |
1365 | ||
3d19f804 | 1366 | static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) |
1da177e4 | 1367 | { |
3d19f804 | 1368 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1369 | |
1370 | snd_printdd("open raw iec958 channel\n"); | |
1371 | ||
62932df8 | 1372 | mutex_lock(&chip->spos_mutex); |
1da177e4 | 1373 | cs46xx_iec958_pre_open (chip); |
62932df8 | 1374 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
1375 | |
1376 | return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); | |
1377 | } | |
1378 | ||
3d19f804 | 1379 | static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); |
1da177e4 | 1380 | |
3d19f804 | 1381 | static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) |
1da177e4 LT |
1382 | { |
1383 | int err; | |
3d19f804 | 1384 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1385 | |
1386 | snd_printdd("close raw iec958 channel\n"); | |
1387 | ||
1388 | err = snd_cs46xx_playback_close(substream); | |
1389 | ||
62932df8 | 1390 | mutex_lock(&chip->spos_mutex); |
1da177e4 | 1391 | cs46xx_iec958_post_close (chip); |
62932df8 | 1392 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
1393 | |
1394 | return err; | |
1395 | } | |
1396 | #endif | |
1397 | ||
3d19f804 | 1398 | static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1399 | { |
3d19f804 | 1400 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1401 | |
1402 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1403 | PAGE_SIZE, &chip->capt.hw_buf) < 0) | |
1404 | return -ENOMEM; | |
1405 | chip->capt.substream = substream; | |
1406 | substream->runtime->hw = snd_cs46xx_capture; | |
1407 | ||
1408 | if (chip->accept_valid) | |
1409 | substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; | |
1410 | ||
1411 | chip->active_ctrl(chip, 1); | |
1412 | ||
1413 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1414 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
1415 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
1416 | &hw_constraints_period_sizes); | |
1417 | #endif | |
1418 | return 0; | |
1419 | } | |
1420 | ||
3d19f804 | 1421 | static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1422 | { |
3d19f804 TI |
1423 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1424 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1425 | struct snd_cs46xx_pcm * cpcm; | |
1da177e4 LT |
1426 | |
1427 | cpcm = runtime->private_data; | |
1428 | ||
1429 | /* when playback_open fails, then cpcm can be NULL */ | |
1430 | if (!cpcm) return -ENXIO; | |
1431 | ||
1432 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
62932df8 | 1433 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
1434 | if (cpcm->pcm_channel) { |
1435 | cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); | |
1436 | cpcm->pcm_channel = NULL; | |
1437 | } | |
62932df8 | 1438 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
1439 | #else |
1440 | chip->playback_pcm = NULL; | |
1441 | #endif | |
1442 | ||
1443 | cpcm->substream = NULL; | |
1444 | snd_dma_free_pages(&cpcm->hw_buf); | |
1445 | chip->active_ctrl(chip, -1); | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
3d19f804 | 1450 | static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1451 | { |
3d19f804 | 1452 | struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1453 | |
1454 | chip->capt.substream = NULL; | |
1455 | snd_dma_free_pages(&chip->capt.hw_buf); | |
1456 | chip->active_ctrl(chip, -1); | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 1462 | static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { |
1da177e4 LT |
1463 | .open = snd_cs46xx_playback_open_rear, |
1464 | .close = snd_cs46xx_playback_close, | |
1465 | .ioctl = snd_pcm_lib_ioctl, | |
1466 | .hw_params = snd_cs46xx_playback_hw_params, | |
1467 | .hw_free = snd_cs46xx_playback_hw_free, | |
1468 | .prepare = snd_cs46xx_playback_prepare, | |
1469 | .trigger = snd_cs46xx_playback_trigger, | |
1470 | .pointer = snd_cs46xx_playback_direct_pointer, | |
1471 | }; | |
1472 | ||
3d19f804 | 1473 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { |
1da177e4 LT |
1474 | .open = snd_cs46xx_playback_open_rear, |
1475 | .close = snd_cs46xx_playback_close, | |
1476 | .ioctl = snd_pcm_lib_ioctl, | |
1477 | .hw_params = snd_cs46xx_playback_hw_params, | |
1478 | .hw_free = snd_cs46xx_playback_hw_free, | |
1479 | .prepare = snd_cs46xx_playback_prepare, | |
1480 | .trigger = snd_cs46xx_playback_trigger, | |
1481 | .pointer = snd_cs46xx_playback_indirect_pointer, | |
1482 | .ack = snd_cs46xx_playback_transfer, | |
1483 | }; | |
1484 | ||
3d19f804 | 1485 | static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { |
1da177e4 LT |
1486 | .open = snd_cs46xx_playback_open_clfe, |
1487 | .close = snd_cs46xx_playback_close, | |
1488 | .ioctl = snd_pcm_lib_ioctl, | |
1489 | .hw_params = snd_cs46xx_playback_hw_params, | |
1490 | .hw_free = snd_cs46xx_playback_hw_free, | |
1491 | .prepare = snd_cs46xx_playback_prepare, | |
1492 | .trigger = snd_cs46xx_playback_trigger, | |
1493 | .pointer = snd_cs46xx_playback_direct_pointer, | |
1494 | }; | |
1495 | ||
3d19f804 | 1496 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { |
1da177e4 LT |
1497 | .open = snd_cs46xx_playback_open_clfe, |
1498 | .close = snd_cs46xx_playback_close, | |
1499 | .ioctl = snd_pcm_lib_ioctl, | |
1500 | .hw_params = snd_cs46xx_playback_hw_params, | |
1501 | .hw_free = snd_cs46xx_playback_hw_free, | |
1502 | .prepare = snd_cs46xx_playback_prepare, | |
1503 | .trigger = snd_cs46xx_playback_trigger, | |
1504 | .pointer = snd_cs46xx_playback_indirect_pointer, | |
1505 | .ack = snd_cs46xx_playback_transfer, | |
1506 | }; | |
1507 | ||
3d19f804 | 1508 | static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { |
1da177e4 LT |
1509 | .open = snd_cs46xx_playback_open_iec958, |
1510 | .close = snd_cs46xx_playback_close_iec958, | |
1511 | .ioctl = snd_pcm_lib_ioctl, | |
1512 | .hw_params = snd_cs46xx_playback_hw_params, | |
1513 | .hw_free = snd_cs46xx_playback_hw_free, | |
1514 | .prepare = snd_cs46xx_playback_prepare, | |
1515 | .trigger = snd_cs46xx_playback_trigger, | |
1516 | .pointer = snd_cs46xx_playback_direct_pointer, | |
1517 | }; | |
1518 | ||
3d19f804 | 1519 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { |
1da177e4 LT |
1520 | .open = snd_cs46xx_playback_open_iec958, |
1521 | .close = snd_cs46xx_playback_close_iec958, | |
1522 | .ioctl = snd_pcm_lib_ioctl, | |
1523 | .hw_params = snd_cs46xx_playback_hw_params, | |
1524 | .hw_free = snd_cs46xx_playback_hw_free, | |
1525 | .prepare = snd_cs46xx_playback_prepare, | |
1526 | .trigger = snd_cs46xx_playback_trigger, | |
1527 | .pointer = snd_cs46xx_playback_indirect_pointer, | |
1528 | .ack = snd_cs46xx_playback_transfer, | |
1529 | }; | |
1530 | ||
1531 | #endif | |
1532 | ||
3d19f804 | 1533 | static struct snd_pcm_ops snd_cs46xx_playback_ops = { |
1da177e4 LT |
1534 | .open = snd_cs46xx_playback_open, |
1535 | .close = snd_cs46xx_playback_close, | |
1536 | .ioctl = snd_pcm_lib_ioctl, | |
1537 | .hw_params = snd_cs46xx_playback_hw_params, | |
1538 | .hw_free = snd_cs46xx_playback_hw_free, | |
1539 | .prepare = snd_cs46xx_playback_prepare, | |
1540 | .trigger = snd_cs46xx_playback_trigger, | |
1541 | .pointer = snd_cs46xx_playback_direct_pointer, | |
1542 | }; | |
1543 | ||
3d19f804 | 1544 | static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { |
1da177e4 LT |
1545 | .open = snd_cs46xx_playback_open, |
1546 | .close = snd_cs46xx_playback_close, | |
1547 | .ioctl = snd_pcm_lib_ioctl, | |
1548 | .hw_params = snd_cs46xx_playback_hw_params, | |
1549 | .hw_free = snd_cs46xx_playback_hw_free, | |
1550 | .prepare = snd_cs46xx_playback_prepare, | |
1551 | .trigger = snd_cs46xx_playback_trigger, | |
1552 | .pointer = snd_cs46xx_playback_indirect_pointer, | |
1553 | .ack = snd_cs46xx_playback_transfer, | |
1554 | }; | |
1555 | ||
3d19f804 | 1556 | static struct snd_pcm_ops snd_cs46xx_capture_ops = { |
1da177e4 LT |
1557 | .open = snd_cs46xx_capture_open, |
1558 | .close = snd_cs46xx_capture_close, | |
1559 | .ioctl = snd_pcm_lib_ioctl, | |
1560 | .hw_params = snd_cs46xx_capture_hw_params, | |
1561 | .hw_free = snd_cs46xx_capture_hw_free, | |
1562 | .prepare = snd_cs46xx_capture_prepare, | |
1563 | .trigger = snd_cs46xx_capture_trigger, | |
1564 | .pointer = snd_cs46xx_capture_direct_pointer, | |
1565 | }; | |
1566 | ||
3d19f804 | 1567 | static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { |
1da177e4 LT |
1568 | .open = snd_cs46xx_capture_open, |
1569 | .close = snd_cs46xx_capture_close, | |
1570 | .ioctl = snd_pcm_lib_ioctl, | |
1571 | .hw_params = snd_cs46xx_capture_hw_params, | |
1572 | .hw_free = snd_cs46xx_capture_hw_free, | |
1573 | .prepare = snd_cs46xx_capture_prepare, | |
1574 | .trigger = snd_cs46xx_capture_trigger, | |
1575 | .pointer = snd_cs46xx_capture_indirect_pointer, | |
1576 | .ack = snd_cs46xx_capture_transfer, | |
1577 | }; | |
1578 | ||
1da177e4 | 1579 | #ifdef CONFIG_SND_CS46XX_NEW_DSP |
1da177e4 LT |
1580 | #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) |
1581 | #else | |
1582 | #define MAX_PLAYBACK_CHANNELS 1 | |
1583 | #endif | |
1584 | ||
3d19f804 | 1585 | int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) |
1da177e4 | 1586 | { |
3d19f804 | 1587 | struct snd_pcm *pcm; |
1da177e4 LT |
1588 | int err; |
1589 | ||
1590 | if (rpcm) | |
1591 | *rpcm = NULL; | |
1592 | if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0) | |
1593 | return err; | |
1594 | ||
1595 | pcm->private_data = chip; | |
1da177e4 LT |
1596 | |
1597 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); | |
1598 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); | |
1599 | ||
1600 | /* global setup */ | |
1601 | pcm->info_flags = 0; | |
1602 | strcpy(pcm->name, "CS46xx"); | |
1603 | chip->pcm = pcm; | |
1604 | ||
1605 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1606 | snd_dma_pci_data(chip->pci), 64*1024, 256*1024); | |
1607 | ||
1608 | if (rpcm) | |
1609 | *rpcm = pcm; | |
1610 | ||
1611 | return 0; | |
1612 | } | |
1613 | ||
1614 | ||
1615 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 1616 | int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) |
1da177e4 | 1617 | { |
3d19f804 | 1618 | struct snd_pcm *pcm; |
1da177e4 LT |
1619 | int err; |
1620 | ||
1621 | if (rpcm) | |
1622 | *rpcm = NULL; | |
1623 | ||
1624 | if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) | |
1625 | return err; | |
1626 | ||
1627 | pcm->private_data = chip; | |
1da177e4 LT |
1628 | |
1629 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); | |
1630 | ||
1631 | /* global setup */ | |
1632 | pcm->info_flags = 0; | |
1633 | strcpy(pcm->name, "CS46xx - Rear"); | |
1634 | chip->pcm_rear = pcm; | |
1635 | ||
1636 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1637 | snd_dma_pci_data(chip->pci), 64*1024, 256*1024); | |
1638 | ||
1639 | if (rpcm) | |
1640 | *rpcm = pcm; | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
3d19f804 | 1645 | int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) |
1da177e4 | 1646 | { |
3d19f804 | 1647 | struct snd_pcm *pcm; |
1da177e4 LT |
1648 | int err; |
1649 | ||
1650 | if (rpcm) | |
1651 | *rpcm = NULL; | |
1652 | ||
1653 | if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) | |
1654 | return err; | |
1655 | ||
1656 | pcm->private_data = chip; | |
1da177e4 LT |
1657 | |
1658 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); | |
1659 | ||
1660 | /* global setup */ | |
1661 | pcm->info_flags = 0; | |
1662 | strcpy(pcm->name, "CS46xx - Center LFE"); | |
1663 | chip->pcm_center_lfe = pcm; | |
1664 | ||
1665 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1666 | snd_dma_pci_data(chip->pci), 64*1024, 256*1024); | |
1667 | ||
1668 | if (rpcm) | |
1669 | *rpcm = pcm; | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
3d19f804 | 1674 | int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) |
1da177e4 | 1675 | { |
3d19f804 | 1676 | struct snd_pcm *pcm; |
1da177e4 LT |
1677 | int err; |
1678 | ||
1679 | if (rpcm) | |
1680 | *rpcm = NULL; | |
1681 | ||
1682 | if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0) | |
1683 | return err; | |
1684 | ||
1685 | pcm->private_data = chip; | |
1da177e4 LT |
1686 | |
1687 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); | |
1688 | ||
1689 | /* global setup */ | |
1690 | pcm->info_flags = 0; | |
1691 | strcpy(pcm->name, "CS46xx - IEC958"); | |
1692 | chip->pcm_rear = pcm; | |
1693 | ||
1694 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1695 | snd_dma_pci_data(chip->pci), 64*1024, 256*1024); | |
1696 | ||
1697 | if (rpcm) | |
1698 | *rpcm = pcm; | |
1699 | ||
1700 | return 0; | |
1701 | } | |
1702 | #endif | |
1703 | ||
1704 | /* | |
1705 | * Mixer routines | |
1706 | */ | |
3d19f804 | 1707 | static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) |
1da177e4 | 1708 | { |
3d19f804 | 1709 | struct snd_cs46xx *chip = bus->private_data; |
1da177e4 LT |
1710 | |
1711 | chip->ac97_bus = NULL; | |
1712 | } | |
1713 | ||
3d19f804 | 1714 | static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) |
1da177e4 | 1715 | { |
3d19f804 | 1716 | struct snd_cs46xx *chip = ac97->private_data; |
1da177e4 LT |
1717 | |
1718 | snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) || | |
1719 | (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]), | |
1720 | return); | |
1721 | ||
1722 | if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { | |
1723 | chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; | |
1724 | chip->eapd_switch = NULL; | |
1725 | } | |
1726 | else | |
1727 | chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; | |
1728 | } | |
1729 | ||
3d19f804 TI |
1730 | static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, |
1731 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1732 | { |
1733 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1734 | uinfo->count = 2; | |
1735 | uinfo->value.integer.min = 0; | |
1736 | uinfo->value.integer.max = 0x7fff; | |
1737 | return 0; | |
1738 | } | |
1739 | ||
3d19f804 | 1740 | static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1741 | { |
3d19f804 | 1742 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1743 | int reg = kcontrol->private_value; |
1744 | unsigned int val = snd_cs46xx_peek(chip, reg); | |
1745 | ucontrol->value.integer.value[0] = 0xffff - (val >> 16); | |
1746 | ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); | |
1747 | return 0; | |
1748 | } | |
1749 | ||
3d19f804 | 1750 | static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1751 | { |
3d19f804 | 1752 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1753 | int reg = kcontrol->private_value; |
1754 | unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | | |
1755 | (0xffff - ucontrol->value.integer.value[1])); | |
1756 | unsigned int old = snd_cs46xx_peek(chip, reg); | |
1757 | int change = (old != val); | |
1758 | ||
1759 | if (change) { | |
1760 | snd_cs46xx_poke(chip, reg, val); | |
1761 | } | |
1762 | ||
1763 | return change; | |
1764 | } | |
1765 | ||
1766 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
1767 | ||
3d19f804 | 1768 | static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1769 | { |
3d19f804 | 1770 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1771 | |
1772 | ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; | |
1773 | ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; | |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | ||
3d19f804 | 1778 | static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1779 | { |
3d19f804 | 1780 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1781 | int change = 0; |
1782 | ||
1783 | if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || | |
1784 | chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { | |
1785 | cs46xx_dsp_set_dac_volume(chip, | |
1786 | ucontrol->value.integer.value[0], | |
1787 | ucontrol->value.integer.value[1]); | |
1788 | change = 1; | |
1789 | } | |
1790 | ||
1791 | return change; | |
1792 | } | |
1793 | ||
1794 | #if 0 | |
3d19f804 | 1795 | static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1796 | { |
3d19f804 | 1797 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1798 | |
1799 | ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; | |
1800 | ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; | |
1801 | return 0; | |
1802 | } | |
1803 | ||
3d19f804 | 1804 | static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1805 | { |
3d19f804 | 1806 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1807 | int change = 0; |
1808 | ||
1809 | if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || | |
1810 | chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { | |
1811 | cs46xx_dsp_set_iec958_volume (chip, | |
1812 | ucontrol->value.integer.value[0], | |
1813 | ucontrol->value.integer.value[1]); | |
1814 | change = 1; | |
1815 | } | |
1816 | ||
1817 | return change; | |
1818 | } | |
1819 | #endif | |
1820 | ||
3d19f804 TI |
1821 | static int snd_mixer_boolean_info(struct snd_kcontrol *kcontrol, |
1822 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1823 | { |
1824 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
1825 | uinfo->count = 1; | |
1826 | uinfo->value.integer.min = 0; | |
1827 | uinfo->value.integer.max = 1; | |
1828 | return 0; | |
1829 | } | |
1830 | ||
3d19f804 TI |
1831 | static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, |
1832 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1833 | { |
3d19f804 | 1834 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1835 | int reg = kcontrol->private_value; |
1836 | ||
1837 | if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) | |
1838 | ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); | |
1839 | else | |
1840 | ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; | |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
3d19f804 TI |
1845 | static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, |
1846 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1847 | { |
3d19f804 | 1848 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1849 | int change, res; |
1850 | ||
1851 | switch (kcontrol->private_value) { | |
1852 | case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: | |
62932df8 | 1853 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
1854 | change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); |
1855 | if (ucontrol->value.integer.value[0] && !change) | |
1856 | cs46xx_dsp_enable_spdif_out(chip); | |
1857 | else if (change && !ucontrol->value.integer.value[0]) | |
1858 | cs46xx_dsp_disable_spdif_out(chip); | |
1859 | ||
1860 | res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); | |
62932df8 | 1861 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
1862 | break; |
1863 | case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: | |
1864 | change = chip->dsp_spos_instance->spdif_status_in; | |
1865 | if (ucontrol->value.integer.value[0] && !change) { | |
1866 | cs46xx_dsp_enable_spdif_in(chip); | |
1867 | /* restore volume */ | |
1868 | } | |
1869 | else if (change && !ucontrol->value.integer.value[0]) | |
1870 | cs46xx_dsp_disable_spdif_in(chip); | |
1871 | ||
1872 | res = (change != chip->dsp_spos_instance->spdif_status_in); | |
1873 | break; | |
1874 | default: | |
1875 | res = -EINVAL; | |
1876 | snd_assert(0, (void)0); | |
1877 | } | |
1878 | ||
1879 | return res; | |
1880 | } | |
1881 | ||
3d19f804 TI |
1882 | static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, |
1883 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1884 | { |
3d19f804 TI |
1885 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1886 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
1887 | |
1888 | if (ins->adc_input != NULL) | |
1889 | ucontrol->value.integer.value[0] = 1; | |
1890 | else | |
1891 | ucontrol->value.integer.value[0] = 0; | |
1892 | ||
1893 | return 0; | |
1894 | } | |
1895 | ||
3d19f804 TI |
1896 | static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, |
1897 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1898 | { |
3d19f804 TI |
1899 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1900 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
1901 | int change = 0; |
1902 | ||
1903 | if (ucontrol->value.integer.value[0] && !ins->adc_input) { | |
1904 | cs46xx_dsp_enable_adc_capture(chip); | |
1905 | change = 1; | |
1906 | } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { | |
1907 | cs46xx_dsp_disable_adc_capture(chip); | |
1908 | change = 1; | |
1909 | } | |
1910 | return change; | |
1911 | } | |
1912 | ||
3d19f804 TI |
1913 | static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, |
1914 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1915 | { |
3d19f804 TI |
1916 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1917 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
1918 | |
1919 | if (ins->pcm_input != NULL) | |
1920 | ucontrol->value.integer.value[0] = 1; | |
1921 | else | |
1922 | ucontrol->value.integer.value[0] = 0; | |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
1927 | ||
3d19f804 TI |
1928 | static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, |
1929 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1930 | { |
3d19f804 TI |
1931 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1932 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
1933 | int change = 0; |
1934 | ||
1935 | if (ucontrol->value.integer.value[0] && !ins->pcm_input) { | |
1936 | cs46xx_dsp_enable_pcm_capture(chip); | |
1937 | change = 1; | |
1938 | } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { | |
1939 | cs46xx_dsp_disable_pcm_capture(chip); | |
1940 | change = 1; | |
1941 | } | |
1942 | ||
1943 | return change; | |
1944 | } | |
1945 | ||
3d19f804 TI |
1946 | static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, |
1947 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1948 | { |
3d19f804 | 1949 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1950 | |
1951 | int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); | |
1952 | ||
1953 | if (val1 & EGPIODR_GPOE0) | |
1954 | ucontrol->value.integer.value[0] = 1; | |
1955 | else | |
1956 | ucontrol->value.integer.value[0] = 0; | |
1957 | ||
1958 | return 0; | |
1959 | } | |
1960 | ||
1961 | /* | |
1962 | * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. | |
1963 | */ | |
3d19f804 TI |
1964 | static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, |
1965 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1966 | { |
3d19f804 | 1967 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1968 | int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); |
1969 | int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); | |
1970 | ||
1971 | if (ucontrol->value.integer.value[0]) { | |
1972 | /* optical is default */ | |
1973 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, | |
1974 | EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ | |
1975 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, | |
1976 | EGPIOPTR_GPPT0 | val2); /* open-drain on output */ | |
1977 | } else { | |
1978 | /* coaxial */ | |
1979 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ | |
1980 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ | |
1981 | } | |
1982 | ||
1983 | /* checking diff from the EGPIO direction register | |
1984 | should be enough */ | |
1985 | return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); | |
1986 | } | |
1987 | ||
1988 | ||
3d19f804 | 1989 | static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1990 | { |
1991 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1992 | uinfo->count = 1; | |
1993 | return 0; | |
1994 | } | |
1995 | ||
3d19f804 TI |
1996 | static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, |
1997 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1998 | { |
3d19f804 TI |
1999 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
2000 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 | 2001 | |
62932df8 | 2002 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
2003 | ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); |
2004 | ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); | |
2005 | ucontrol->value.iec958.status[2] = 0; | |
2006 | ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); | |
62932df8 | 2007 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
2008 | |
2009 | return 0; | |
2010 | } | |
2011 | ||
3d19f804 TI |
2012 | static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, |
2013 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2014 | { |
3d19f804 TI |
2015 | struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); |
2016 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
2017 | unsigned int val; |
2018 | int change; | |
2019 | ||
62932df8 | 2020 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
2021 | val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | |
2022 | ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | | |
2023 | ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | | |
2024 | /* left and right validity bit */ | |
2025 | (1 << 13) | (1 << 12); | |
2026 | ||
2027 | ||
2028 | change = (unsigned int)ins->spdif_csuv_default != val; | |
2029 | ins->spdif_csuv_default = val; | |
2030 | ||
2031 | if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) | |
2032 | cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); | |
2033 | ||
62932df8 | 2034 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
2035 | |
2036 | return change; | |
2037 | } | |
2038 | ||
3d19f804 TI |
2039 | static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, |
2040 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
2041 | { |
2042 | ucontrol->value.iec958.status[0] = 0xff; | |
2043 | ucontrol->value.iec958.status[1] = 0xff; | |
2044 | ucontrol->value.iec958.status[2] = 0x00; | |
2045 | ucontrol->value.iec958.status[3] = 0xff; | |
2046 | return 0; | |
2047 | } | |
2048 | ||
3d19f804 TI |
2049 | static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, |
2050 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2051 | { |
3d19f804 TI |
2052 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
2053 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 | 2054 | |
62932df8 | 2055 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
2056 | ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); |
2057 | ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); | |
2058 | ucontrol->value.iec958.status[2] = 0; | |
2059 | ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); | |
62932df8 | 2060 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
2061 | |
2062 | return 0; | |
2063 | } | |
2064 | ||
3d19f804 TI |
2065 | static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, |
2066 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2067 | { |
3d19f804 TI |
2068 | struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); |
2069 | struct dsp_spos_instance * ins = chip->dsp_spos_instance; | |
1da177e4 LT |
2070 | unsigned int val; |
2071 | int change; | |
2072 | ||
62932df8 | 2073 | mutex_lock(&chip->spos_mutex); |
1da177e4 LT |
2074 | val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | |
2075 | ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | | |
2076 | ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | | |
2077 | /* left and right validity bit */ | |
2078 | (1 << 13) | (1 << 12); | |
2079 | ||
2080 | ||
2081 | change = ins->spdif_csuv_stream != val; | |
2082 | ins->spdif_csuv_stream = val; | |
2083 | ||
2084 | if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) | |
2085 | cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); | |
2086 | ||
62932df8 | 2087 | mutex_unlock(&chip->spos_mutex); |
1da177e4 LT |
2088 | |
2089 | return change; | |
2090 | } | |
2091 | ||
2092 | #endif /* CONFIG_SND_CS46XX_NEW_DSP */ | |
2093 | ||
2094 | ||
2095 | #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO | |
3d19f804 TI |
2096 | static int snd_cs46xx_egpio_select_info(struct snd_kcontrol *kcontrol, |
2097 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
2098 | { |
2099 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2100 | uinfo->count = 1; | |
2101 | uinfo->value.integer.min = 0; | |
2102 | uinfo->value.integer.max = 8; | |
2103 | return 0; | |
2104 | } | |
2105 | ||
3d19f804 TI |
2106 | static int snd_cs46xx_egpio_select_get(struct snd_kcontrol *kcontrol, |
2107 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2108 | { |
3d19f804 | 2109 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2110 | ucontrol->value.integer.value[0] = chip->current_gpio; |
2111 | ||
2112 | return 0; | |
2113 | } | |
2114 | ||
3d19f804 TI |
2115 | static int snd_cs46xx_egpio_select_put(struct snd_kcontrol *kcontrol, |
2116 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2117 | { |
3d19f804 | 2118 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2119 | int change = (chip->current_gpio != ucontrol->value.integer.value[0]); |
2120 | chip->current_gpio = ucontrol->value.integer.value[0]; | |
2121 | ||
2122 | return change; | |
2123 | } | |
2124 | ||
2125 | ||
3d19f804 TI |
2126 | static int snd_cs46xx_egpio_get(struct snd_kcontrol *kcontrol, |
2127 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2128 | { |
3d19f804 | 2129 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2130 | int reg = kcontrol->private_value; |
2131 | ||
2132 | snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio); | |
2133 | ucontrol->value.integer.value[0] = | |
2134 | (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0; | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
3d19f804 TI |
2139 | static int snd_cs46xx_egpio_put(struct snd_kcontrol *kcontrol, |
2140 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2141 | { |
3d19f804 | 2142 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2143 | int reg = kcontrol->private_value; |
2144 | int val = snd_cs46xx_peekBA0(chip, reg); | |
2145 | int oldval = val; | |
2146 | snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio); | |
2147 | ||
2148 | if (ucontrol->value.integer.value[0]) | |
2149 | val |= (1 << chip->current_gpio); | |
2150 | else | |
2151 | val &= ~(1 << chip->current_gpio); | |
2152 | ||
2153 | snd_cs46xx_pokeBA0(chip, reg,val); | |
2154 | snd_printdd ("put: val %08x oldval %08x\n",val,oldval); | |
2155 | ||
2156 | return (oldval != val); | |
2157 | } | |
2158 | #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */ | |
2159 | ||
3d19f804 | 2160 | static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = { |
1da177e4 LT |
2161 | { |
2162 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2163 | .name = "DAC Volume", | |
2164 | .info = snd_cs46xx_vol_info, | |
2165 | #ifndef CONFIG_SND_CS46XX_NEW_DSP | |
2166 | .get = snd_cs46xx_vol_get, | |
2167 | .put = snd_cs46xx_vol_put, | |
2168 | .private_value = BA1_PVOL, | |
2169 | #else | |
2170 | .get = snd_cs46xx_vol_dac_get, | |
2171 | .put = snd_cs46xx_vol_dac_put, | |
2172 | #endif | |
2173 | }, | |
2174 | ||
2175 | { | |
2176 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2177 | .name = "ADC Volume", | |
2178 | .info = snd_cs46xx_vol_info, | |
2179 | .get = snd_cs46xx_vol_get, | |
2180 | .put = snd_cs46xx_vol_put, | |
2181 | #ifndef CONFIG_SND_CS46XX_NEW_DSP | |
2182 | .private_value = BA1_CVOL, | |
2183 | #else | |
2184 | .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, | |
2185 | #endif | |
2186 | }, | |
2187 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2188 | { | |
2189 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2190 | .name = "ADC Capture Switch", | |
2191 | .info = snd_mixer_boolean_info, | |
2192 | .get = snd_cs46xx_adc_capture_get, | |
2193 | .put = snd_cs46xx_adc_capture_put | |
2194 | }, | |
2195 | { | |
2196 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2197 | .name = "DAC Capture Switch", | |
2198 | .info = snd_mixer_boolean_info, | |
2199 | .get = snd_cs46xx_pcm_capture_get, | |
2200 | .put = snd_cs46xx_pcm_capture_put | |
2201 | }, | |
2202 | { | |
2203 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
10e8d78a | 2204 | .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), |
1da177e4 LT |
2205 | .info = snd_mixer_boolean_info, |
2206 | .get = snd_cs46xx_iec958_get, | |
2207 | .put = snd_cs46xx_iec958_put, | |
2208 | .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, | |
2209 | }, | |
2210 | { | |
2211 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
10e8d78a | 2212 | .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), |
1da177e4 LT |
2213 | .info = snd_mixer_boolean_info, |
2214 | .get = snd_cs46xx_iec958_get, | |
2215 | .put = snd_cs46xx_iec958_put, | |
2216 | .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, | |
2217 | }, | |
2218 | #if 0 | |
2219 | /* Input IEC958 volume does not work for the moment. (Benny) */ | |
2220 | { | |
2221 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
10e8d78a | 2222 | .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), |
1da177e4 LT |
2223 | .info = snd_cs46xx_vol_info, |
2224 | .get = snd_cs46xx_vol_iec958_get, | |
2225 | .put = snd_cs46xx_vol_iec958_put, | |
2226 | .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, | |
2227 | }, | |
2228 | #endif | |
2229 | { | |
2230 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
2231 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
2232 | .info = snd_cs46xx_spdif_info, | |
2233 | .get = snd_cs46xx_spdif_default_get, | |
2234 | .put = snd_cs46xx_spdif_default_put, | |
2235 | }, | |
2236 | { | |
2237 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
2238 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), | |
2239 | .info = snd_cs46xx_spdif_info, | |
2240 | .get = snd_cs46xx_spdif_mask_get, | |
2241 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
2242 | }, | |
2243 | { | |
2244 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
2245 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
2246 | .info = snd_cs46xx_spdif_info, | |
2247 | .get = snd_cs46xx_spdif_stream_get, | |
2248 | .put = snd_cs46xx_spdif_stream_put | |
2249 | }, | |
2250 | ||
2251 | #endif | |
2252 | #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO | |
2253 | { | |
2254 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2255 | .name = "EGPIO select", | |
2256 | .info = snd_cs46xx_egpio_select_info, | |
2257 | .get = snd_cs46xx_egpio_select_get, | |
2258 | .put = snd_cs46xx_egpio_select_put, | |
2259 | .private_value = 0, | |
2260 | }, | |
2261 | { | |
2262 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2263 | .name = "EGPIO Input/Output", | |
2264 | .info = snd_mixer_boolean_info, | |
2265 | .get = snd_cs46xx_egpio_get, | |
2266 | .put = snd_cs46xx_egpio_put, | |
2267 | .private_value = BA0_EGPIODR, | |
2268 | }, | |
2269 | { | |
2270 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2271 | .name = "EGPIO CMOS/Open drain", | |
2272 | .info = snd_mixer_boolean_info, | |
2273 | .get = snd_cs46xx_egpio_get, | |
2274 | .put = snd_cs46xx_egpio_put, | |
2275 | .private_value = BA0_EGPIOPTR, | |
2276 | }, | |
2277 | { | |
2278 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2279 | .name = "EGPIO On/Off", | |
2280 | .info = snd_mixer_boolean_info, | |
2281 | .get = snd_cs46xx_egpio_get, | |
2282 | .put = snd_cs46xx_egpio_put, | |
2283 | .private_value = BA0_EGPIOSR, | |
2284 | }, | |
2285 | #endif | |
2286 | }; | |
2287 | ||
2288 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2289 | /* set primary cs4294 codec into Extended Audio Mode */ | |
3d19f804 TI |
2290 | static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, |
2291 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2292 | { |
3d19f804 | 2293 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2294 | unsigned short val; |
2295 | val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); | |
2296 | ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; | |
2297 | return 0; | |
2298 | } | |
2299 | ||
3d19f804 TI |
2300 | static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, |
2301 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2302 | { |
3d19f804 | 2303 | struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2304 | return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], |
2305 | AC97_CSR_ACMODE, 0x200, | |
2306 | ucontrol->value.integer.value[0] ? 0 : 0x200); | |
2307 | } | |
2308 | ||
3d19f804 | 2309 | static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { |
1da177e4 LT |
2310 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2311 | .name = "Duplicate Front", | |
2312 | .info = snd_mixer_boolean_info, | |
2313 | .get = snd_cs46xx_front_dup_get, | |
2314 | .put = snd_cs46xx_front_dup_put, | |
2315 | }; | |
2316 | #endif | |
2317 | ||
2318 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2319 | /* Only available on the Hercules Game Theater XP soundcard */ | |
f40b6890 | 2320 | static struct snd_kcontrol_new snd_hercules_controls[] = { |
1da177e4 LT |
2321 | { |
2322 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2323 | .name = "Optical/Coaxial SPDIF Input Switch", | |
2324 | .info = snd_mixer_boolean_info, | |
2325 | .get = snd_herc_spdif_select_get, | |
2326 | .put = snd_herc_spdif_select_put, | |
2327 | }, | |
2328 | }; | |
2329 | ||
2330 | ||
3d19f804 | 2331 | static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) |
1da177e4 LT |
2332 | { |
2333 | unsigned long end_time; | |
2334 | int err; | |
2335 | ||
2336 | /* reset to defaults */ | |
2337 | snd_ac97_write(ac97, AC97_RESET, 0); | |
2338 | ||
2339 | /* set the desired CODEC mode */ | |
2340 | if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { | |
2341 | snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0); | |
2342 | snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0); | |
2343 | } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { | |
2344 | snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3); | |
2345 | snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3); | |
2346 | } else { | |
2347 | snd_assert(0); /* should never happen ... */ | |
2348 | } | |
2349 | ||
2350 | udelay(50); | |
2351 | ||
2352 | /* it's necessary to wait awhile until registers are accessible after RESET */ | |
2353 | /* because the PCM or MASTER volume registers can be modified, */ | |
2354 | /* the REC_GAIN register is used for tests */ | |
2355 | end_time = jiffies + HZ; | |
2356 | do { | |
2357 | unsigned short ext_mid; | |
2358 | ||
2359 | /* use preliminary reads to settle the communication */ | |
2360 | snd_ac97_read(ac97, AC97_RESET); | |
2361 | snd_ac97_read(ac97, AC97_VENDOR_ID1); | |
2362 | snd_ac97_read(ac97, AC97_VENDOR_ID2); | |
2363 | /* modem? */ | |
2364 | ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); | |
2365 | if (ext_mid != 0xffff && (ext_mid & 1) != 0) | |
2366 | return; | |
2367 | ||
2368 | /* test if we can write to the record gain volume register */ | |
2369 | snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05); | |
2370 | if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) | |
2371 | return; | |
2372 | ||
ef21ca24 | 2373 | msleep(10); |
1da177e4 LT |
2374 | } while (time_after_eq(end_time, jiffies)); |
2375 | ||
99b359ba | 2376 | snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n"); |
1da177e4 LT |
2377 | } |
2378 | #endif | |
2379 | ||
3d19f804 | 2380 | static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) |
1da177e4 LT |
2381 | { |
2382 | int idx, err; | |
3d19f804 | 2383 | struct snd_ac97_template ac97; |
1da177e4 LT |
2384 | |
2385 | memset(&ac97, 0, sizeof(ac97)); | |
2386 | ac97.private_data = chip; | |
2387 | ac97.private_free = snd_cs46xx_mixer_free_ac97; | |
2388 | ac97.num = codec; | |
2389 | if (chip->amplifier_ctrl == amp_voyetra) | |
2390 | ac97.scaps = AC97_SCAP_INV_EAPD; | |
2391 | ||
2392 | if (codec == CS46XX_SECONDARY_CODEC_INDEX) { | |
2393 | snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); | |
2394 | udelay(10); | |
2395 | if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { | |
2396 | snd_printdd("snd_cs46xx: seconadry codec not present\n"); | |
2397 | return -ENXIO; | |
2398 | } | |
2399 | } | |
2400 | ||
2401 | snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); | |
2402 | for (idx = 0; idx < 100; ++idx) { | |
2403 | if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { | |
2404 | err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); | |
2405 | return err; | |
2406 | } | |
ef21ca24 | 2407 | msleep(10); |
1da177e4 LT |
2408 | } |
2409 | snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); | |
2410 | return -ENXIO; | |
2411 | } | |
2412 | ||
3d19f804 | 2413 | int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) |
1da177e4 | 2414 | { |
3d19f804 TI |
2415 | struct snd_card *card = chip->card; |
2416 | struct snd_ctl_elem_id id; | |
1da177e4 LT |
2417 | int err; |
2418 | unsigned int idx; | |
3d19f804 | 2419 | static struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
2420 | #ifdef CONFIG_SND_CS46XX_NEW_DSP |
2421 | .reset = snd_cs46xx_codec_reset, | |
2422 | #endif | |
2423 | .write = snd_cs46xx_ac97_write, | |
2424 | .read = snd_cs46xx_ac97_read, | |
2425 | }; | |
2426 | ||
2427 | /* detect primary codec */ | |
2428 | chip->nr_ac97_codecs = 0; | |
2429 | snd_printdd("snd_cs46xx: detecting primary codec\n"); | |
2430 | if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) | |
2431 | return err; | |
2432 | chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus; | |
2433 | ||
2434 | if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) | |
2435 | return -ENXIO; | |
2436 | chip->nr_ac97_codecs = 1; | |
2437 | ||
2438 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2439 | snd_printdd("snd_cs46xx: detecting seconadry codec\n"); | |
2440 | /* try detect a secondary codec */ | |
2441 | if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) | |
2442 | chip->nr_ac97_codecs = 2; | |
2443 | #endif /* CONFIG_SND_CS46XX_NEW_DSP */ | |
2444 | ||
2445 | /* add cs4630 mixer controls */ | |
2446 | for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { | |
3d19f804 | 2447 | struct snd_kcontrol *kctl; |
1da177e4 | 2448 | kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); |
67ed4161 CL |
2449 | if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) |
2450 | kctl->id.device = spdif_device; | |
1da177e4 LT |
2451 | if ((err = snd_ctl_add(card, kctl)) < 0) |
2452 | return err; | |
2453 | } | |
2454 | ||
2455 | /* get EAPD mixer switch (for voyetra hack) */ | |
2456 | memset(&id, 0, sizeof(id)); | |
2457 | id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; | |
2458 | strcpy(id.name, "External Amplifier"); | |
2459 | chip->eapd_switch = snd_ctl_find_id(chip->card, &id); | |
2460 | ||
2461 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2462 | if (chip->nr_ac97_codecs == 1) { | |
2463 | unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; | |
2464 | if (id2 == 0x592b || id2 == 0x592d) { | |
2465 | err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); | |
2466 | if (err < 0) | |
2467 | return err; | |
2468 | snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], | |
2469 | AC97_CSR_ACMODE, 0x200); | |
2470 | } | |
2471 | } | |
2472 | /* do soundcard specific mixer setup */ | |
2473 | if (chip->mixer_init) { | |
2474 | snd_printdd ("calling chip->mixer_init(chip);\n"); | |
2475 | chip->mixer_init(chip); | |
2476 | } | |
2477 | #endif | |
2478 | ||
2479 | /* turn on amplifier */ | |
2480 | chip->amplifier_ctrl(chip, 1); | |
2481 | ||
2482 | return 0; | |
2483 | } | |
2484 | ||
2485 | /* | |
2486 | * RawMIDI interface | |
2487 | */ | |
2488 | ||
3d19f804 | 2489 | static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) |
1da177e4 LT |
2490 | { |
2491 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); | |
2492 | udelay(100); | |
2493 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2494 | } | |
2495 | ||
3d19f804 | 2496 | static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 2497 | { |
3d19f804 | 2498 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2499 | |
2500 | chip->active_ctrl(chip, 1); | |
2501 | spin_lock_irq(&chip->reg_lock); | |
2502 | chip->uartm |= CS46XX_MODE_INPUT; | |
2503 | chip->midcr |= MIDCR_RXE; | |
2504 | chip->midi_input = substream; | |
2505 | if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { | |
2506 | snd_cs46xx_midi_reset(chip); | |
2507 | } else { | |
2508 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2509 | } | |
2510 | spin_unlock_irq(&chip->reg_lock); | |
2511 | return 0; | |
2512 | } | |
2513 | ||
3d19f804 | 2514 | static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 2515 | { |
3d19f804 | 2516 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2517 | |
2518 | spin_lock_irq(&chip->reg_lock); | |
2519 | chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); | |
2520 | chip->midi_input = NULL; | |
2521 | if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { | |
2522 | snd_cs46xx_midi_reset(chip); | |
2523 | } else { | |
2524 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2525 | } | |
2526 | chip->uartm &= ~CS46XX_MODE_INPUT; | |
2527 | spin_unlock_irq(&chip->reg_lock); | |
2528 | chip->active_ctrl(chip, -1); | |
2529 | return 0; | |
2530 | } | |
2531 | ||
3d19f804 | 2532 | static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 2533 | { |
3d19f804 | 2534 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2535 | |
2536 | chip->active_ctrl(chip, 1); | |
2537 | ||
2538 | spin_lock_irq(&chip->reg_lock); | |
2539 | chip->uartm |= CS46XX_MODE_OUTPUT; | |
2540 | chip->midcr |= MIDCR_TXE; | |
2541 | chip->midi_output = substream; | |
2542 | if (!(chip->uartm & CS46XX_MODE_INPUT)) { | |
2543 | snd_cs46xx_midi_reset(chip); | |
2544 | } else { | |
2545 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2546 | } | |
2547 | spin_unlock_irq(&chip->reg_lock); | |
2548 | return 0; | |
2549 | } | |
2550 | ||
3d19f804 | 2551 | static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 2552 | { |
3d19f804 | 2553 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2554 | |
2555 | spin_lock_irq(&chip->reg_lock); | |
2556 | chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); | |
2557 | chip->midi_output = NULL; | |
2558 | if (!(chip->uartm & CS46XX_MODE_INPUT)) { | |
2559 | snd_cs46xx_midi_reset(chip); | |
2560 | } else { | |
2561 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2562 | } | |
2563 | chip->uartm &= ~CS46XX_MODE_OUTPUT; | |
2564 | spin_unlock_irq(&chip->reg_lock); | |
2565 | chip->active_ctrl(chip, -1); | |
2566 | return 0; | |
2567 | } | |
2568 | ||
3d19f804 | 2569 | static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 LT |
2570 | { |
2571 | unsigned long flags; | |
3d19f804 | 2572 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2573 | |
2574 | spin_lock_irqsave(&chip->reg_lock, flags); | |
2575 | if (up) { | |
2576 | if ((chip->midcr & MIDCR_RIE) == 0) { | |
2577 | chip->midcr |= MIDCR_RIE; | |
2578 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2579 | } | |
2580 | } else { | |
2581 | if (chip->midcr & MIDCR_RIE) { | |
2582 | chip->midcr &= ~MIDCR_RIE; | |
2583 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2584 | } | |
2585 | } | |
2586 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
2587 | } | |
2588 | ||
3d19f804 | 2589 | static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 LT |
2590 | { |
2591 | unsigned long flags; | |
3d19f804 | 2592 | struct snd_cs46xx *chip = substream->rmidi->private_data; |
1da177e4 LT |
2593 | unsigned char byte; |
2594 | ||
2595 | spin_lock_irqsave(&chip->reg_lock, flags); | |
2596 | if (up) { | |
2597 | if ((chip->midcr & MIDCR_TIE) == 0) { | |
2598 | chip->midcr |= MIDCR_TIE; | |
2599 | /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ | |
2600 | while ((chip->midcr & MIDCR_TIE) && | |
2601 | (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { | |
2602 | if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { | |
2603 | chip->midcr &= ~MIDCR_TIE; | |
2604 | } else { | |
2605 | snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); | |
2606 | } | |
2607 | } | |
2608 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2609 | } | |
2610 | } else { | |
2611 | if (chip->midcr & MIDCR_TIE) { | |
2612 | chip->midcr &= ~MIDCR_TIE; | |
2613 | snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); | |
2614 | } | |
2615 | } | |
2616 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
2617 | } | |
2618 | ||
3d19f804 | 2619 | static struct snd_rawmidi_ops snd_cs46xx_midi_output = |
1da177e4 LT |
2620 | { |
2621 | .open = snd_cs46xx_midi_output_open, | |
2622 | .close = snd_cs46xx_midi_output_close, | |
2623 | .trigger = snd_cs46xx_midi_output_trigger, | |
2624 | }; | |
2625 | ||
3d19f804 | 2626 | static struct snd_rawmidi_ops snd_cs46xx_midi_input = |
1da177e4 LT |
2627 | { |
2628 | .open = snd_cs46xx_midi_input_open, | |
2629 | .close = snd_cs46xx_midi_input_close, | |
2630 | .trigger = snd_cs46xx_midi_input_trigger, | |
2631 | }; | |
2632 | ||
3d19f804 | 2633 | int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi) |
1da177e4 | 2634 | { |
3d19f804 | 2635 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
2636 | int err; |
2637 | ||
2638 | if (rrawmidi) | |
2639 | *rrawmidi = NULL; | |
2640 | if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0) | |
2641 | return err; | |
2642 | strcpy(rmidi->name, "CS46XX"); | |
2643 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); | |
2644 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); | |
2645 | rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; | |
2646 | rmidi->private_data = chip; | |
2647 | chip->rmidi = rmidi; | |
2648 | if (rrawmidi) | |
2649 | *rrawmidi = NULL; | |
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | ||
2654 | /* | |
2655 | * gameport interface | |
2656 | */ | |
2657 | ||
2658 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) | |
2659 | ||
2660 | static void snd_cs46xx_gameport_trigger(struct gameport *gameport) | |
2661 | { | |
3d19f804 | 2662 | struct snd_cs46xx *chip = gameport_get_port_data(gameport); |
1da177e4 LT |
2663 | |
2664 | snd_assert(chip, return); | |
2665 | snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); | |
2666 | } | |
2667 | ||
2668 | static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) | |
2669 | { | |
3d19f804 | 2670 | struct snd_cs46xx *chip = gameport_get_port_data(gameport); |
1da177e4 LT |
2671 | |
2672 | snd_assert(chip, return 0); | |
2673 | return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); | |
2674 | } | |
2675 | ||
2676 | static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) | |
2677 | { | |
3d19f804 | 2678 | struct snd_cs46xx *chip = gameport_get_port_data(gameport); |
1da177e4 LT |
2679 | unsigned js1, js2, jst; |
2680 | ||
2681 | snd_assert(chip, return 0); | |
2682 | ||
2683 | js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); | |
2684 | js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); | |
2685 | jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); | |
2686 | ||
2687 | *buttons = (~jst >> 4) & 0x0F; | |
2688 | ||
2689 | axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; | |
2690 | axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; | |
2691 | axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; | |
2692 | axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; | |
2693 | ||
2694 | for(jst=0;jst<4;++jst) | |
2695 | if(axes[jst]==0xFFFF) axes[jst] = -1; | |
2696 | return 0; | |
2697 | } | |
2698 | ||
2699 | static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) | |
2700 | { | |
2701 | switch (mode) { | |
2702 | case GAMEPORT_MODE_COOKED: | |
2703 | return 0; | |
2704 | case GAMEPORT_MODE_RAW: | |
2705 | return 0; | |
2706 | default: | |
2707 | return -1; | |
2708 | } | |
2709 | return 0; | |
2710 | } | |
2711 | ||
3d19f804 | 2712 | int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) |
1da177e4 LT |
2713 | { |
2714 | struct gameport *gp; | |
2715 | ||
2716 | chip->gameport = gp = gameport_allocate_port(); | |
2717 | if (!gp) { | |
2718 | printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n"); | |
2719 | return -ENOMEM; | |
2720 | } | |
2721 | ||
2722 | gameport_set_name(gp, "CS46xx Gameport"); | |
2723 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); | |
2724 | gameport_set_dev_parent(gp, &chip->pci->dev); | |
2725 | gameport_set_port_data(gp, chip); | |
2726 | ||
2727 | gp->open = snd_cs46xx_gameport_open; | |
2728 | gp->read = snd_cs46xx_gameport_read; | |
2729 | gp->trigger = snd_cs46xx_gameport_trigger; | |
2730 | gp->cooked_read = snd_cs46xx_gameport_cooked_read; | |
2731 | ||
2732 | snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? | |
2733 | snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); | |
2734 | ||
2735 | gameport_register_port(gp); | |
2736 | ||
2737 | return 0; | |
2738 | } | |
2739 | ||
3d19f804 | 2740 | static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) |
1da177e4 LT |
2741 | { |
2742 | if (chip->gameport) { | |
2743 | gameport_unregister_port(chip->gameport); | |
2744 | chip->gameport = NULL; | |
2745 | } | |
2746 | } | |
2747 | #else | |
3d19f804 TI |
2748 | int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } |
2749 | static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } | |
1da177e4 LT |
2750 | #endif /* CONFIG_GAMEPORT */ |
2751 | ||
adf1b3d2 | 2752 | #ifdef CONFIG_PROC_FS |
1da177e4 LT |
2753 | /* |
2754 | * proc interface | |
2755 | */ | |
2756 | ||
3d19f804 | 2757 | static long snd_cs46xx_io_read(struct snd_info_entry *entry, void *file_private_data, |
1da177e4 LT |
2758 | struct file *file, char __user *buf, |
2759 | unsigned long count, unsigned long pos) | |
2760 | { | |
2761 | long size; | |
3d19f804 | 2762 | struct snd_cs46xx_region *region = entry->private_data; |
1da177e4 LT |
2763 | |
2764 | size = count; | |
2765 | if (pos + (size_t)size > region->size) | |
2766 | size = region->size - pos; | |
2767 | if (size > 0) { | |
2768 | if (copy_to_user_fromio(buf, region->remap_addr + pos, size)) | |
2769 | return -EFAULT; | |
2770 | } | |
2771 | return size; | |
2772 | } | |
2773 | ||
2774 | static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { | |
2775 | .read = snd_cs46xx_io_read, | |
2776 | }; | |
2777 | ||
3d19f804 | 2778 | static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) |
1da177e4 | 2779 | { |
3d19f804 | 2780 | struct snd_info_entry *entry; |
1da177e4 LT |
2781 | int idx; |
2782 | ||
2783 | for (idx = 0; idx < 5; idx++) { | |
3d19f804 | 2784 | struct snd_cs46xx_region *region = &chip->region.idx[idx]; |
1da177e4 LT |
2785 | if (! snd_card_proc_new(card, region->name, &entry)) { |
2786 | entry->content = SNDRV_INFO_CONTENT_DATA; | |
2787 | entry->private_data = chip; | |
2788 | entry->c.ops = &snd_cs46xx_proc_io_ops; | |
2789 | entry->size = region->size; | |
2790 | entry->mode = S_IFREG | S_IRUSR; | |
2791 | } | |
2792 | } | |
2793 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2794 | cs46xx_dsp_proc_init(card, chip); | |
2795 | #endif | |
2796 | return 0; | |
2797 | } | |
2798 | ||
3d19f804 | 2799 | static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) |
1da177e4 LT |
2800 | { |
2801 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2802 | cs46xx_dsp_proc_done(chip); | |
2803 | #endif | |
2804 | return 0; | |
2805 | } | |
adf1b3d2 TI |
2806 | #else /* !CONFIG_PROC_FS */ |
2807 | #define snd_cs46xx_proc_init(card, chip) | |
2808 | #define snd_cs46xx_proc_done(chip) | |
2809 | #endif | |
1da177e4 LT |
2810 | |
2811 | /* | |
2812 | * stop the h/w | |
2813 | */ | |
3d19f804 | 2814 | static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) |
1da177e4 LT |
2815 | { |
2816 | unsigned int tmp; | |
2817 | ||
2818 | tmp = snd_cs46xx_peek(chip, BA1_PFIE); | |
2819 | tmp &= ~0x0000f03f; | |
2820 | tmp |= 0x00000010; | |
2821 | snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ | |
2822 | ||
2823 | tmp = snd_cs46xx_peek(chip, BA1_CIE); | |
2824 | tmp &= ~0x0000003f; | |
2825 | tmp |= 0x00000011; | |
2826 | snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ | |
2827 | ||
2828 | /* | |
2829 | * Stop playback DMA. | |
2830 | */ | |
2831 | tmp = snd_cs46xx_peek(chip, BA1_PCTL); | |
2832 | snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); | |
2833 | ||
2834 | /* | |
2835 | * Stop capture DMA. | |
2836 | */ | |
2837 | tmp = snd_cs46xx_peek(chip, BA1_CCTL); | |
2838 | snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); | |
2839 | ||
2840 | /* | |
2841 | * Reset the processor. | |
2842 | */ | |
2843 | snd_cs46xx_reset(chip); | |
2844 | ||
2845 | snd_cs46xx_proc_stop(chip); | |
2846 | ||
2847 | /* | |
2848 | * Power down the PLL. | |
2849 | */ | |
2850 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); | |
2851 | ||
2852 | /* | |
2853 | * Turn off the Processor by turning off the software clock enable flag in | |
2854 | * the clock control register. | |
2855 | */ | |
2856 | tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; | |
2857 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); | |
2858 | } | |
2859 | ||
2860 | ||
3d19f804 | 2861 | static int snd_cs46xx_free(struct snd_cs46xx *chip) |
1da177e4 LT |
2862 | { |
2863 | int idx; | |
2864 | ||
2865 | snd_assert(chip != NULL, return -EINVAL); | |
2866 | ||
2867 | if (chip->active_ctrl) | |
2868 | chip->active_ctrl(chip, 1); | |
2869 | ||
2870 | snd_cs46xx_remove_gameport(chip); | |
2871 | ||
2872 | if (chip->amplifier_ctrl) | |
2873 | chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ | |
2874 | ||
2875 | snd_cs46xx_proc_done(chip); | |
2876 | ||
2877 | if (chip->region.idx[0].resource) | |
2878 | snd_cs46xx_hw_stop(chip); | |
2879 | ||
0a50d2b2 TI |
2880 | if (chip->irq >= 0) |
2881 | free_irq(chip->irq, chip); | |
2882 | ||
1da177e4 | 2883 | for (idx = 0; idx < 5; idx++) { |
3d19f804 | 2884 | struct snd_cs46xx_region *region = &chip->region.idx[idx]; |
1da177e4 LT |
2885 | if (region->remap_addr) |
2886 | iounmap(region->remap_addr); | |
b1d5776d | 2887 | release_and_free_resource(region->resource); |
1da177e4 | 2888 | } |
1da177e4 LT |
2889 | |
2890 | if (chip->active_ctrl) | |
2891 | chip->active_ctrl(chip, -chip->amplifier); | |
2892 | ||
2893 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2894 | if (chip->dsp_spos_instance) { | |
2895 | cs46xx_dsp_spos_destroy(chip); | |
2896 | chip->dsp_spos_instance = NULL; | |
2897 | } | |
2898 | #endif | |
2899 | ||
2900 | pci_disable_device(chip->pci); | |
2901 | kfree(chip); | |
2902 | return 0; | |
2903 | } | |
2904 | ||
3d19f804 | 2905 | static int snd_cs46xx_dev_free(struct snd_device *device) |
1da177e4 | 2906 | { |
3d19f804 | 2907 | struct snd_cs46xx *chip = device->device_data; |
1da177e4 LT |
2908 | return snd_cs46xx_free(chip); |
2909 | } | |
2910 | ||
2911 | /* | |
2912 | * initialize chip | |
2913 | */ | |
3d19f804 | 2914 | static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) |
1da177e4 LT |
2915 | { |
2916 | int timeout; | |
2917 | ||
2918 | /* | |
2919 | * First, blast the clock control register to zero so that the PLL starts | |
2920 | * out in a known state, and blast the master serial port control register | |
2921 | * to zero so that the serial ports also start out in a known state. | |
2922 | */ | |
2923 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); | |
2924 | snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); | |
2925 | ||
2926 | /* | |
2927 | * If we are in AC97 mode, then we must set the part to a host controlled | |
2928 | * AC-link. Otherwise, we won't be able to bring up the link. | |
2929 | */ | |
2930 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2931 | snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | | |
2932 | SERACC_TWO_CODECS); /* 2.00 dual codecs */ | |
2933 | /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ | |
2934 | #else | |
2935 | snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ | |
2936 | #endif | |
2937 | ||
2938 | /* | |
2939 | * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 | |
2940 | * spec) and then drive it high. This is done for non AC97 modes since | |
2941 | * there might be logic external to the CS461x that uses the ARST# line | |
2942 | * for a reset. | |
2943 | */ | |
2944 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); | |
2945 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2946 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); | |
2947 | #endif | |
2948 | udelay(50); | |
2949 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); | |
2950 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2951 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); | |
2952 | #endif | |
2953 | ||
2954 | /* | |
2955 | * The first thing we do here is to enable sync generation. As soon | |
2956 | * as we start receiving bit clock, we'll start producing the SYNC | |
2957 | * signal. | |
2958 | */ | |
2959 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); | |
2960 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
2961 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); | |
2962 | #endif | |
2963 | ||
2964 | /* | |
2965 | * Now wait for a short while to allow the AC97 part to start | |
2966 | * generating bit clock (so we don't try to start the PLL without an | |
2967 | * input clock). | |
2968 | */ | |
2969 | mdelay(10); | |
2970 | ||
2971 | /* | |
2972 | * Set the serial port timing configuration, so that | |
2973 | * the clock control circuit gets its clock from the correct place. | |
2974 | */ | |
2975 | snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); | |
2976 | ||
2977 | /* | |
2978 | * Write the selected clock control setup to the hardware. Do not turn on | |
2979 | * SWCE yet (if requested), so that the devices clocked by the output of | |
2980 | * PLL are not clocked until the PLL is stable. | |
2981 | */ | |
2982 | snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); | |
2983 | snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); | |
2984 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); | |
2985 | ||
2986 | /* | |
2987 | * Power up the PLL. | |
2988 | */ | |
2989 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); | |
2990 | ||
2991 | /* | |
2992 | * Wait until the PLL has stabilized. | |
2993 | */ | |
ef21ca24 | 2994 | msleep(100); |
1da177e4 LT |
2995 | |
2996 | /* | |
2997 | * Turn on clocking of the core so that we can setup the serial ports. | |
2998 | */ | |
2999 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); | |
3000 | ||
3001 | /* | |
3002 | * Enable FIFO Host Bypass | |
3003 | */ | |
3004 | snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); | |
3005 | ||
3006 | /* | |
3007 | * Fill the serial port FIFOs with silence. | |
3008 | */ | |
3009 | snd_cs46xx_clear_serial_FIFOs(chip); | |
3010 | ||
3011 | /* | |
3012 | * Set the serial port FIFO pointer to the first sample in the FIFO. | |
3013 | */ | |
3014 | /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ | |
3015 | ||
3016 | /* | |
3017 | * Write the serial port configuration to the part. The master | |
3018 | * enable bit is not set until all other values have been written. | |
3019 | */ | |
3020 | snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); | |
3021 | snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); | |
3022 | snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); | |
3023 | ||
3024 | ||
3025 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3026 | snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); | |
3027 | snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); | |
3028 | snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); | |
3029 | snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); | |
3030 | snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); | |
3031 | #endif | |
3032 | ||
3033 | mdelay(5); | |
3034 | ||
3035 | ||
3036 | /* | |
3037 | * Wait for the codec ready signal from the AC97 codec. | |
3038 | */ | |
3039 | timeout = 150; | |
3040 | while (timeout-- > 0) { | |
3041 | /* | |
3042 | * Read the AC97 status register to see if we've seen a CODEC READY | |
3043 | * signal from the AC97 codec. | |
3044 | */ | |
3045 | if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) | |
3046 | goto ok1; | |
ef21ca24 | 3047 | msleep(10); |
1da177e4 LT |
3048 | } |
3049 | ||
3050 | ||
99b359ba TI |
3051 | snd_printk(KERN_ERR "create - never read codec ready from AC'97\n"); |
3052 | snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n"); | |
1da177e4 LT |
3053 | return -EIO; |
3054 | ok1: | |
3055 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3056 | { | |
3057 | int count; | |
3058 | for (count = 0; count < 150; count++) { | |
3059 | /* First, we want to wait for a short time. */ | |
3060 | udelay(25); | |
3061 | ||
3062 | if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) | |
3063 | break; | |
3064 | } | |
3065 | ||
3066 | /* | |
3067 | * Make sure CODEC is READY. | |
3068 | */ | |
3069 | if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) | |
3070 | snd_printdd("cs46xx: never read card ready from secondary AC'97\n"); | |
3071 | } | |
3072 | #endif | |
3073 | ||
3074 | /* | |
3075 | * Assert the vaid frame signal so that we can start sending commands | |
3076 | * to the AC97 codec. | |
3077 | */ | |
3078 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); | |
3079 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3080 | snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); | |
3081 | #endif | |
3082 | ||
3083 | ||
3084 | /* | |
3085 | * Wait until we've sampled input slots 3 and 4 as valid, meaning that | |
3086 | * the codec is pumping ADC data across the AC-link. | |
3087 | */ | |
3088 | timeout = 150; | |
3089 | while (timeout-- > 0) { | |
3090 | /* | |
3091 | * Read the input slot valid register and see if input slots 3 and | |
3092 | * 4 are valid yet. | |
3093 | */ | |
3094 | if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) | |
3095 | goto ok2; | |
ef21ca24 | 3096 | msleep(10); |
1da177e4 LT |
3097 | } |
3098 | ||
3099 | #ifndef CONFIG_SND_CS46XX_NEW_DSP | |
99b359ba | 3100 | snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n"); |
1da177e4 LT |
3101 | return -EIO; |
3102 | #else | |
3103 | /* This may happen on a cold boot with a Terratec SiXPack 5.1. | |
3104 | Reloading the driver may help, if there's other soundcards | |
3105 | with the same problem I would like to know. (Benny) */ | |
3106 | ||
99b359ba TI |
3107 | snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n"); |
3108 | snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n"); | |
3109 | snd_printk(KERN_ERR " broken or not working on your soundcard upon\n"); | |
3110 | snd_printk(KERN_ERR " this message please report to alsa-devel@lists.sourceforge.net\n"); | |
1da177e4 LT |
3111 | |
3112 | return -EIO; | |
3113 | #endif | |
3114 | ok2: | |
3115 | ||
3116 | /* | |
3117 | * Now, assert valid frame and the slot 3 and 4 valid bits. This will | |
3118 | * commense the transfer of digital audio data to the AC97 codec. | |
3119 | */ | |
3120 | ||
3121 | snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); | |
3122 | ||
3123 | ||
3124 | /* | |
3125 | * Power down the DAC and ADC. We will power them up (if) when we need | |
3126 | * them. | |
3127 | */ | |
3128 | /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ | |
3129 | ||
3130 | /* | |
3131 | * Turn off the Processor by turning off the software clock enable flag in | |
3132 | * the clock control register. | |
3133 | */ | |
3134 | /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ | |
3135 | /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ | |
3136 | ||
3137 | return 0; | |
3138 | } | |
3139 | ||
3140 | /* | |
3141 | * start and load DSP | |
3142 | */ | |
3d19f804 | 3143 | int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip) |
1da177e4 LT |
3144 | { |
3145 | unsigned int tmp; | |
3146 | /* | |
3147 | * Reset the processor. | |
3148 | */ | |
3149 | snd_cs46xx_reset(chip); | |
3150 | /* | |
3151 | * Download the image to the processor. | |
3152 | */ | |
3153 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3154 | #if 0 | |
3155 | if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) { | |
3156 | snd_printk(KERN_ERR "image download error\n"); | |
3157 | return -EIO; | |
3158 | } | |
3159 | #endif | |
3160 | ||
3161 | if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) { | |
3162 | snd_printk(KERN_ERR "image download error [cwc4630]\n"); | |
3163 | return -EIO; | |
3164 | } | |
3165 | ||
3166 | if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) { | |
3167 | snd_printk(KERN_ERR "image download error [cwcasync]\n"); | |
3168 | return -EIO; | |
3169 | } | |
3170 | ||
3171 | if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) { | |
3172 | snd_printk(KERN_ERR "image download error [cwcsnoop]\n"); | |
3173 | return -EIO; | |
3174 | } | |
3175 | ||
3176 | if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) { | |
3177 | snd_printk(KERN_ERR "image download error [cwcbinhack]\n"); | |
3178 | return -EIO; | |
3179 | } | |
3180 | ||
3181 | if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) { | |
3182 | snd_printk(KERN_ERR "image download error [cwcdma]\n"); | |
3183 | return -EIO; | |
3184 | } | |
3185 | ||
3186 | if (cs46xx_dsp_scb_and_task_init(chip) < 0) | |
3187 | return -EIO; | |
3188 | #else | |
3189 | /* old image */ | |
3190 | if (snd_cs46xx_download_image(chip) < 0) { | |
99b359ba | 3191 | snd_printk(KERN_ERR "image download error\n"); |
1da177e4 LT |
3192 | return -EIO; |
3193 | } | |
3194 | ||
3195 | /* | |
3196 | * Stop playback DMA. | |
3197 | */ | |
3198 | tmp = snd_cs46xx_peek(chip, BA1_PCTL); | |
3199 | chip->play_ctl = tmp & 0xffff0000; | |
3200 | snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); | |
3201 | #endif | |
3202 | ||
3203 | /* | |
3204 | * Stop capture DMA. | |
3205 | */ | |
3206 | tmp = snd_cs46xx_peek(chip, BA1_CCTL); | |
3207 | chip->capt.ctl = tmp & 0x0000ffff; | |
3208 | snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); | |
3209 | ||
3210 | mdelay(5); | |
3211 | ||
3212 | snd_cs46xx_set_play_sample_rate(chip, 8000); | |
3213 | snd_cs46xx_set_capture_sample_rate(chip, 8000); | |
3214 | ||
3215 | snd_cs46xx_proc_start(chip); | |
3216 | ||
3217 | /* | |
3218 | * Enable interrupts on the part. | |
3219 | */ | |
3220 | snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); | |
3221 | ||
3222 | tmp = snd_cs46xx_peek(chip, BA1_PFIE); | |
3223 | tmp &= ~0x0000f03f; | |
3224 | snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ | |
3225 | ||
3226 | tmp = snd_cs46xx_peek(chip, BA1_CIE); | |
3227 | tmp &= ~0x0000003f; | |
3228 | tmp |= 0x00000001; | |
3229 | snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ | |
3230 | ||
3231 | #ifndef CONFIG_SND_CS46XX_NEW_DSP | |
3232 | /* set the attenuation to 0dB */ | |
3233 | snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); | |
3234 | snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); | |
3235 | #endif | |
3236 | ||
3237 | return 0; | |
3238 | } | |
3239 | ||
3240 | ||
3241 | /* | |
3242 | * AMP control - null AMP | |
3243 | */ | |
3244 | ||
3d19f804 | 3245 | static void amp_none(struct snd_cs46xx *chip, int change) |
1da177e4 LT |
3246 | { |
3247 | } | |
3248 | ||
3249 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3d19f804 | 3250 | static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) |
1da177e4 LT |
3251 | { |
3252 | ||
3253 | u32 idx, valid_slots,tmp,powerdown = 0; | |
3254 | u16 modem_power,pin_config,logic_type; | |
3255 | ||
3256 | snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); | |
3257 | ||
3258 | /* | |
3259 | * See if the devices are powered down. If so, we must power them up first | |
3260 | * or they will not respond. | |
3261 | */ | |
3262 | tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); | |
3263 | ||
3264 | if (!(tmp & CLKCR1_SWCE)) { | |
3265 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); | |
3266 | powerdown = 1; | |
3267 | } | |
3268 | ||
3269 | /* | |
3270 | * Clear PRA. The Bonzo chip will be used for GPIO not for modem | |
3271 | * stuff. | |
3272 | */ | |
3273 | if(chip->nr_ac97_codecs != 2) { | |
3274 | snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); | |
3275 | return -EINVAL; | |
3276 | } | |
3277 | ||
3278 | modem_power = snd_cs46xx_codec_read (chip, | |
3279 | AC97_EXTENDED_MSTATUS, | |
3280 | CS46XX_SECONDARY_CODEC_INDEX); | |
3281 | modem_power &=0xFEFF; | |
3282 | ||
3283 | snd_cs46xx_codec_write(chip, | |
3284 | AC97_EXTENDED_MSTATUS, modem_power, | |
3285 | CS46XX_SECONDARY_CODEC_INDEX); | |
3286 | ||
3287 | /* | |
3288 | * Set GPIO pin's 7 and 8 so that they are configured for output. | |
3289 | */ | |
3290 | pin_config = snd_cs46xx_codec_read (chip, | |
3291 | AC97_GPIO_CFG, | |
3292 | CS46XX_SECONDARY_CODEC_INDEX); | |
3293 | pin_config &=0x27F; | |
3294 | ||
3295 | snd_cs46xx_codec_write(chip, | |
3296 | AC97_GPIO_CFG, pin_config, | |
3297 | CS46XX_SECONDARY_CODEC_INDEX); | |
3298 | ||
3299 | /* | |
3300 | * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. | |
3301 | */ | |
3302 | ||
3303 | logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, | |
3304 | CS46XX_SECONDARY_CODEC_INDEX); | |
3305 | logic_type &=0x27F; | |
3306 | ||
3307 | snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, | |
3308 | CS46XX_SECONDARY_CODEC_INDEX); | |
3309 | ||
3310 | valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); | |
3311 | valid_slots |= 0x200; | |
3312 | snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); | |
3313 | ||
3314 | if ( cs46xx_wait_for_fifo(chip,1) ) { | |
3315 | snd_printdd("FIFO is busy\n"); | |
3316 | ||
3317 | return -EINVAL; | |
3318 | } | |
3319 | ||
3320 | /* | |
3321 | * Fill slots 12 with the correct value for the GPIO pins. | |
3322 | */ | |
3323 | for(idx = 0x90; idx <= 0x9F; idx++) { | |
3324 | /* | |
3325 | * Initialize the fifo so that bits 7 and 8 are on. | |
3326 | * | |
3327 | * Remember that the GPIO pins in bonzo are shifted by 4 bits to | |
3328 | * the left. 0x1800 corresponds to bits 7 and 8. | |
3329 | */ | |
3330 | snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); | |
3331 | ||
3332 | /* | |
3333 | * Wait for command to complete | |
3334 | */ | |
3335 | if ( cs46xx_wait_for_fifo(chip,200) ) { | |
3336 | snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx); | |
3337 | ||
3338 | return -EINVAL; | |
3339 | } | |
3340 | ||
3341 | /* | |
3342 | * Write the serial port FIFO index. | |
3343 | */ | |
3344 | snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); | |
3345 | ||
3346 | /* | |
3347 | * Tell the serial port to load the new value into the FIFO location. | |
3348 | */ | |
3349 | snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); | |
3350 | } | |
3351 | ||
3352 | /* wait for last command to complete */ | |
3353 | cs46xx_wait_for_fifo(chip,200); | |
3354 | ||
3355 | /* | |
3356 | * Now, if we powered up the devices, then power them back down again. | |
3357 | * This is kinda ugly, but should never happen. | |
3358 | */ | |
3359 | if (powerdown) | |
3360 | snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); | |
3361 | ||
3362 | return 0; | |
3363 | } | |
3364 | #endif | |
3365 | ||
3366 | /* | |
3367 | * Crystal EAPD mode | |
3368 | */ | |
3369 | ||
3d19f804 | 3370 | static void amp_voyetra(struct snd_cs46xx *chip, int change) |
1da177e4 LT |
3371 | { |
3372 | /* Manage the EAPD bit on the Crystal 4297 | |
3373 | and the Analog AD1885 */ | |
3374 | ||
3375 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3376 | int old = chip->amplifier; | |
3377 | #endif | |
3378 | int oval, val; | |
3379 | ||
3380 | chip->amplifier += change; | |
3381 | oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, | |
3382 | CS46XX_PRIMARY_CODEC_INDEX); | |
3383 | val = oval; | |
3384 | if (chip->amplifier) { | |
3385 | /* Turn the EAPD amp on */ | |
3386 | val |= 0x8000; | |
3387 | } else { | |
3388 | /* Turn the EAPD amp off */ | |
3389 | val &= ~0x8000; | |
3390 | } | |
3391 | if (val != oval) { | |
3392 | snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, | |
3393 | CS46XX_PRIMARY_CODEC_INDEX); | |
3394 | if (chip->eapd_switch) | |
3395 | snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, | |
3396 | &chip->eapd_switch->id); | |
3397 | } | |
3398 | ||
3399 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3400 | if (chip->amplifier && !old) { | |
3401 | voyetra_setup_eapd_slot(chip); | |
3402 | } | |
3403 | #endif | |
3404 | } | |
3405 | ||
3d19f804 | 3406 | static void hercules_init(struct snd_cs46xx *chip) |
1da177e4 LT |
3407 | { |
3408 | /* default: AMP off, and SPDIF input optical */ | |
3409 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); | |
3410 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); | |
3411 | } | |
3412 | ||
3413 | ||
3414 | /* | |
3415 | * Game Theatre XP card - EGPIO[2] is used to enable the external amp. | |
3416 | */ | |
3d19f804 | 3417 | static void amp_hercules(struct snd_cs46xx *chip, int change) |
1da177e4 LT |
3418 | { |
3419 | int old = chip->amplifier; | |
3420 | int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); | |
3421 | int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); | |
3422 | ||
3423 | chip->amplifier += change; | |
3424 | if (chip->amplifier && !old) { | |
3425 | snd_printdd ("Hercules amplifier ON\n"); | |
3426 | ||
3427 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, | |
3428 | EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ | |
3429 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, | |
3430 | EGPIOPTR_GPPT2 | val2); /* open-drain on output */ | |
3431 | } else if (old && !chip->amplifier) { | |
3432 | snd_printdd ("Hercules amplifier OFF\n"); | |
3433 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ | |
3434 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ | |
3435 | } | |
3436 | } | |
3437 | ||
3d19f804 | 3438 | static void voyetra_mixer_init (struct snd_cs46xx *chip) |
1da177e4 LT |
3439 | { |
3440 | snd_printdd ("initializing Voyetra mixer\n"); | |
3441 | ||
3442 | /* Enable SPDIF out */ | |
3443 | snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); | |
3444 | snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); | |
3445 | } | |
3446 | ||
3d19f804 | 3447 | static void hercules_mixer_init (struct snd_cs46xx *chip) |
1da177e4 LT |
3448 | { |
3449 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3450 | unsigned int idx; | |
3451 | int err; | |
3d19f804 | 3452 | struct snd_card *card = chip->card; |
1da177e4 LT |
3453 | #endif |
3454 | ||
3455 | /* set EGPIO to default */ | |
3456 | hercules_init(chip); | |
3457 | ||
3458 | snd_printdd ("initializing Hercules mixer\n"); | |
3459 | ||
3460 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
f40b6890 TI |
3461 | if (chip->in_suspend) |
3462 | return; | |
3463 | ||
1da177e4 | 3464 | for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { |
3d19f804 | 3465 | struct snd_kcontrol *kctl; |
1da177e4 LT |
3466 | |
3467 | kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); | |
3468 | if ((err = snd_ctl_add(card, kctl)) < 0) { | |
3469 | printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err); | |
3470 | break; | |
3471 | } | |
3472 | } | |
3473 | #endif | |
3474 | } | |
3475 | ||
3476 | ||
3477 | #if 0 | |
3478 | /* | |
3479 | * Untested | |
3480 | */ | |
3481 | ||
3d19f804 | 3482 | static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) |
1da177e4 LT |
3483 | { |
3484 | chip->amplifier += change; | |
3485 | ||
3486 | if (chip->amplifier) { | |
3487 | /* Switch the GPIO pins 7 and 8 to open drain */ | |
3488 | snd_cs46xx_codec_write(chip, 0x4C, | |
3489 | snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); | |
3490 | snd_cs46xx_codec_write(chip, 0x4E, | |
3491 | snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); | |
3492 | /* Now wake the AMP (this might be backwards) */ | |
3493 | snd_cs46xx_codec_write(chip, 0x54, | |
3494 | snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); | |
3495 | } else { | |
3496 | snd_cs46xx_codec_write(chip, 0x54, | |
3497 | snd_cs46xx_codec_read(chip, 0x54) | 0x0180); | |
3498 | } | |
3499 | } | |
3500 | #endif | |
3501 | ||
3502 | ||
1da177e4 LT |
3503 | /* |
3504 | * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support | |
3505 | * whenever we need to beat on the chip. | |
3506 | * | |
3507 | * The original idea and code for this hack comes from David Kaiser at | |
3508 | * Linuxcare. Perhaps one day Crystal will document their chips well | |
3509 | * enough to make them useful. | |
3510 | */ | |
3511 | ||
3d19f804 | 3512 | static void clkrun_hack(struct snd_cs46xx *chip, int change) |
1da177e4 LT |
3513 | { |
3514 | u16 control, nval; | |
3515 | ||
0dd119f7 | 3516 | if (!chip->acpi_port) |
1da177e4 LT |
3517 | return; |
3518 | ||
3519 | chip->amplifier += change; | |
3520 | ||
3521 | /* Read ACPI port */ | |
3522 | nval = control = inw(chip->acpi_port + 0x10); | |
3523 | ||
3524 | /* Flip CLKRUN off while running */ | |
3525 | if (! chip->amplifier) | |
3526 | nval |= 0x2000; | |
3527 | else | |
3528 | nval &= ~0x2000; | |
3529 | if (nval != control) | |
3530 | outw(nval, chip->acpi_port + 0x10); | |
3531 | } | |
3532 | ||
3533 | ||
3534 | /* | |
3535 | * detect intel piix4 | |
3536 | */ | |
3d19f804 | 3537 | static void clkrun_init(struct snd_cs46xx *chip) |
1da177e4 | 3538 | { |
0dd119f7 | 3539 | struct pci_dev *pdev; |
1da177e4 LT |
3540 | u8 pp; |
3541 | ||
0dd119f7 JS |
3542 | chip->acpi_port = 0; |
3543 | ||
3544 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
3545 | PCI_DEVICE_ID_INTEL_82371AB_3, NULL); | |
3546 | if (pdev == NULL) | |
1da177e4 LT |
3547 | return; /* Not a thinkpad thats for sure */ |
3548 | ||
3549 | /* Find the control port */ | |
0dd119f7 | 3550 | pci_read_config_byte(pdev, 0x41, &pp); |
1da177e4 | 3551 | chip->acpi_port = pp << 8; |
0dd119f7 | 3552 | pci_dev_put(pdev); |
1da177e4 LT |
3553 | } |
3554 | ||
3555 | ||
3556 | /* | |
3557 | * Card subid table | |
3558 | */ | |
3559 | ||
3560 | struct cs_card_type | |
3561 | { | |
3562 | u16 vendor; | |
3563 | u16 id; | |
3564 | char *name; | |
3d19f804 TI |
3565 | void (*init)(struct snd_cs46xx *); |
3566 | void (*amp)(struct snd_cs46xx *, int); | |
3567 | void (*active)(struct snd_cs46xx *, int); | |
3568 | void (*mixer_init)(struct snd_cs46xx *); | |
1da177e4 LT |
3569 | }; |
3570 | ||
3571 | static struct cs_card_type __devinitdata cards[] = { | |
3572 | { | |
3573 | .vendor = 0x1489, | |
3574 | .id = 0x7001, | |
3575 | .name = "Genius Soundmaker 128 value", | |
3576 | /* nothing special */ | |
3577 | }, | |
3578 | { | |
3579 | .vendor = 0x5053, | |
3580 | .id = 0x3357, | |
3581 | .name = "Voyetra", | |
3582 | .amp = amp_voyetra, | |
3583 | .mixer_init = voyetra_mixer_init, | |
3584 | }, | |
3585 | { | |
3586 | .vendor = 0x1071, | |
3587 | .id = 0x6003, | |
3588 | .name = "Mitac MI6020/21", | |
3589 | .amp = amp_voyetra, | |
3590 | }, | |
3591 | { | |
3592 | .vendor = 0x14AF, | |
3593 | .id = 0x0050, | |
3594 | .name = "Hercules Game Theatre XP", | |
3595 | .amp = amp_hercules, | |
3596 | .mixer_init = hercules_mixer_init, | |
3597 | }, | |
3598 | { | |
3599 | .vendor = 0x1681, | |
3600 | .id = 0x0050, | |
3601 | .name = "Hercules Game Theatre XP", | |
3602 | .amp = amp_hercules, | |
3603 | .mixer_init = hercules_mixer_init, | |
3604 | }, | |
3605 | { | |
3606 | .vendor = 0x1681, | |
3607 | .id = 0x0051, | |
3608 | .name = "Hercules Game Theatre XP", | |
3609 | .amp = amp_hercules, | |
3610 | .mixer_init = hercules_mixer_init, | |
3611 | ||
3612 | }, | |
3613 | { | |
3614 | .vendor = 0x1681, | |
3615 | .id = 0x0052, | |
3616 | .name = "Hercules Game Theatre XP", | |
3617 | .amp = amp_hercules, | |
3618 | .mixer_init = hercules_mixer_init, | |
3619 | }, | |
3620 | { | |
3621 | .vendor = 0x1681, | |
3622 | .id = 0x0053, | |
3623 | .name = "Hercules Game Theatre XP", | |
3624 | .amp = amp_hercules, | |
3625 | .mixer_init = hercules_mixer_init, | |
3626 | }, | |
3627 | { | |
3628 | .vendor = 0x1681, | |
3629 | .id = 0x0054, | |
3630 | .name = "Hercules Game Theatre XP", | |
3631 | .amp = amp_hercules, | |
3632 | .mixer_init = hercules_mixer_init, | |
3633 | }, | |
3634 | /* Teratec */ | |
3635 | { | |
3636 | .vendor = 0x153b, | |
3637 | .id = 0x1136, | |
3638 | .name = "Terratec SiXPack 5.1", | |
3639 | }, | |
3640 | /* Not sure if the 570 needs the clkrun hack */ | |
3641 | { | |
3642 | .vendor = PCI_VENDOR_ID_IBM, | |
3643 | .id = 0x0132, | |
3644 | .name = "Thinkpad 570", | |
3645 | .init = clkrun_init, | |
3646 | .active = clkrun_hack, | |
3647 | }, | |
3648 | { | |
3649 | .vendor = PCI_VENDOR_ID_IBM, | |
3650 | .id = 0x0153, | |
3651 | .name = "Thinkpad 600X/A20/T20", | |
3652 | .init = clkrun_init, | |
3653 | .active = clkrun_hack, | |
3654 | }, | |
3655 | { | |
3656 | .vendor = PCI_VENDOR_ID_IBM, | |
3657 | .id = 0x1010, | |
3658 | .name = "Thinkpad 600E (unsupported)", | |
3659 | }, | |
3660 | {} /* terminator */ | |
3661 | }; | |
3662 | ||
3663 | ||
3664 | /* | |
3665 | * APM support | |
3666 | */ | |
3667 | #ifdef CONFIG_PM | |
cb28e45b | 3668 | int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 3669 | { |
cb28e45b TI |
3670 | struct snd_card *card = pci_get_drvdata(pci); |
3671 | struct snd_cs46xx *chip = card->private_data; | |
1da177e4 LT |
3672 | int amp_saved; |
3673 | ||
cb28e45b | 3674 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
f40b6890 | 3675 | chip->in_suspend = 1; |
1da177e4 LT |
3676 | snd_pcm_suspend_all(chip->pcm); |
3677 | // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); | |
3678 | // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); | |
3679 | ||
3680 | snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); | |
cb28e45b | 3681 | snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); |
1da177e4 LT |
3682 | |
3683 | amp_saved = chip->amplifier; | |
3684 | /* turn off amp */ | |
3685 | chip->amplifier_ctrl(chip, -chip->amplifier); | |
3686 | snd_cs46xx_hw_stop(chip); | |
3687 | /* disable CLKRUN */ | |
3688 | chip->active_ctrl(chip, -chip->amplifier); | |
3689 | chip->amplifier = amp_saved; /* restore the status */ | |
30b35399 | 3690 | |
cb28e45b TI |
3691 | pci_disable_device(pci); |
3692 | pci_save_state(pci); | |
30b35399 | 3693 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
1da177e4 LT |
3694 | return 0; |
3695 | } | |
3696 | ||
cb28e45b | 3697 | int snd_cs46xx_resume(struct pci_dev *pci) |
1da177e4 | 3698 | { |
cb28e45b TI |
3699 | struct snd_card *card = pci_get_drvdata(pci); |
3700 | struct snd_cs46xx *chip = card->private_data; | |
1da177e4 LT |
3701 | int amp_saved; |
3702 | ||
30b35399 | 3703 | pci_set_power_state(pci, PCI_D0); |
cb28e45b | 3704 | pci_restore_state(pci); |
30b35399 TI |
3705 | if (pci_enable_device(pci) < 0) { |
3706 | printk(KERN_ERR "cs46xx: pci_enable_device failed, " | |
3707 | "disabling device\n"); | |
3708 | snd_card_disconnect(card); | |
3709 | return -EIO; | |
3710 | } | |
cb28e45b | 3711 | pci_set_master(pci); |
30b35399 | 3712 | |
1da177e4 LT |
3713 | amp_saved = chip->amplifier; |
3714 | chip->amplifier = 0; | |
3715 | chip->active_ctrl(chip, 1); /* force to on */ | |
3716 | ||
3717 | snd_cs46xx_chip_init(chip); | |
3718 | ||
3719 | #if 0 | |
3720 | snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, | |
3721 | chip->ac97_general_purpose); | |
3722 | snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, | |
3723 | chip->ac97_powerdown); | |
3724 | mdelay(10); | |
3725 | snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, | |
3726 | chip->ac97_powerdown); | |
3727 | mdelay(5); | |
3728 | #endif | |
3729 | ||
3730 | snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); | |
cb28e45b | 3731 | snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); |
1da177e4 LT |
3732 | |
3733 | if (amp_saved) | |
3734 | chip->amplifier_ctrl(chip, 1); /* turn amp on */ | |
3735 | else | |
3736 | chip->active_ctrl(chip, -1); /* disable CLKRUN */ | |
3737 | chip->amplifier = amp_saved; | |
f40b6890 | 3738 | chip->in_suspend = 0; |
cb28e45b | 3739 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
3740 | return 0; |
3741 | } | |
3742 | #endif /* CONFIG_PM */ | |
3743 | ||
3744 | ||
3745 | /* | |
3746 | */ | |
3747 | ||
3d19f804 | 3748 | int __devinit snd_cs46xx_create(struct snd_card *card, |
1da177e4 LT |
3749 | struct pci_dev * pci, |
3750 | int external_amp, int thinkpad, | |
3d19f804 | 3751 | struct snd_cs46xx ** rchip) |
1da177e4 | 3752 | { |
3d19f804 | 3753 | struct snd_cs46xx *chip; |
1da177e4 | 3754 | int err, idx; |
3d19f804 | 3755 | struct snd_cs46xx_region *region; |
1da177e4 LT |
3756 | struct cs_card_type *cp; |
3757 | u16 ss_card, ss_vendor; | |
3d19f804 | 3758 | static struct snd_device_ops ops = { |
1da177e4 LT |
3759 | .dev_free = snd_cs46xx_dev_free, |
3760 | }; | |
3761 | ||
3762 | *rchip = NULL; | |
3763 | ||
3764 | /* enable PCI device */ | |
3765 | if ((err = pci_enable_device(pci)) < 0) | |
3766 | return err; | |
3767 | ||
e560d8d8 | 3768 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
3769 | if (chip == NULL) { |
3770 | pci_disable_device(pci); | |
3771 | return -ENOMEM; | |
3772 | } | |
3773 | spin_lock_init(&chip->reg_lock); | |
3774 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
62932df8 | 3775 | mutex_init(&chip->spos_mutex); |
1da177e4 LT |
3776 | #endif |
3777 | chip->card = card; | |
3778 | chip->pci = pci; | |
3779 | chip->irq = -1; | |
3780 | chip->ba0_addr = pci_resource_start(pci, 0); | |
3781 | chip->ba1_addr = pci_resource_start(pci, 1); | |
3782 | if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || | |
3783 | chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { | |
3d19f804 TI |
3784 | snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", |
3785 | chip->ba0_addr, chip->ba1_addr); | |
1da177e4 LT |
3786 | snd_cs46xx_free(chip); |
3787 | return -ENOMEM; | |
3788 | } | |
3789 | ||
3790 | region = &chip->region.name.ba0; | |
3791 | strcpy(region->name, "CS46xx_BA0"); | |
3792 | region->base = chip->ba0_addr; | |
3793 | region->size = CS46XX_BA0_SIZE; | |
3794 | ||
3795 | region = &chip->region.name.data0; | |
3796 | strcpy(region->name, "CS46xx_BA1_data0"); | |
3797 | region->base = chip->ba1_addr + BA1_SP_DMEM0; | |
3798 | region->size = CS46XX_BA1_DATA0_SIZE; | |
3799 | ||
3800 | region = &chip->region.name.data1; | |
3801 | strcpy(region->name, "CS46xx_BA1_data1"); | |
3802 | region->base = chip->ba1_addr + BA1_SP_DMEM1; | |
3803 | region->size = CS46XX_BA1_DATA1_SIZE; | |
3804 | ||
3805 | region = &chip->region.name.pmem; | |
3806 | strcpy(region->name, "CS46xx_BA1_pmem"); | |
3807 | region->base = chip->ba1_addr + BA1_SP_PMEM; | |
3808 | region->size = CS46XX_BA1_PRG_SIZE; | |
3809 | ||
3810 | region = &chip->region.name.reg; | |
3811 | strcpy(region->name, "CS46xx_BA1_reg"); | |
3812 | region->base = chip->ba1_addr + BA1_SP_REG; | |
3813 | region->size = CS46XX_BA1_REG_SIZE; | |
3814 | ||
3815 | /* set up amp and clkrun hack */ | |
3816 | pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); | |
3817 | pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); | |
3818 | ||
3819 | for (cp = &cards[0]; cp->name; cp++) { | |
3820 | if (cp->vendor == ss_vendor && cp->id == ss_card) { | |
3821 | snd_printdd ("hack for %s enabled\n", cp->name); | |
3822 | ||
3823 | chip->amplifier_ctrl = cp->amp; | |
3824 | chip->active_ctrl = cp->active; | |
3825 | chip->mixer_init = cp->mixer_init; | |
3826 | ||
3827 | if (cp->init) | |
3828 | cp->init(chip); | |
3829 | break; | |
3830 | } | |
3831 | } | |
3832 | ||
3833 | if (external_amp) { | |
99b359ba | 3834 | snd_printk(KERN_INFO "Crystal EAPD support forced on.\n"); |
1da177e4 LT |
3835 | chip->amplifier_ctrl = amp_voyetra; |
3836 | } | |
3837 | ||
3838 | if (thinkpad) { | |
99b359ba | 3839 | snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n"); |
1da177e4 LT |
3840 | chip->active_ctrl = clkrun_hack; |
3841 | clkrun_init(chip); | |
3842 | } | |
3843 | ||
3844 | if (chip->amplifier_ctrl == NULL) | |
3845 | chip->amplifier_ctrl = amp_none; | |
3846 | if (chip->active_ctrl == NULL) | |
3847 | chip->active_ctrl = amp_none; | |
3848 | ||
3849 | chip->active_ctrl(chip, 1); /* enable CLKRUN */ | |
3850 | ||
3851 | pci_set_master(pci); | |
3852 | ||
3853 | for (idx = 0; idx < 5; idx++) { | |
3854 | region = &chip->region.idx[idx]; | |
3d19f804 TI |
3855 | if ((region->resource = request_mem_region(region->base, region->size, |
3856 | region->name)) == NULL) { | |
3857 | snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n", | |
3858 | region->base, region->base + region->size - 1); | |
1da177e4 LT |
3859 | snd_cs46xx_free(chip); |
3860 | return -EBUSY; | |
3861 | } | |
3862 | region->remap_addr = ioremap_nocache(region->base, region->size); | |
3863 | if (region->remap_addr == NULL) { | |
99b359ba | 3864 | snd_printk(KERN_ERR "%s ioremap problem\n", region->name); |
1da177e4 LT |
3865 | snd_cs46xx_free(chip); |
3866 | return -ENOMEM; | |
3867 | } | |
3868 | } | |
3869 | ||
437a5a46 | 3870 | if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED, |
3d19f804 | 3871 | "CS46XX", chip)) { |
99b359ba | 3872 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
3873 | snd_cs46xx_free(chip); |
3874 | return -EBUSY; | |
3875 | } | |
3876 | chip->irq = pci->irq; | |
3877 | ||
3878 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | |
3879 | chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); | |
3880 | if (chip->dsp_spos_instance == NULL) { | |
3881 | snd_cs46xx_free(chip); | |
3882 | return -ENOMEM; | |
3883 | } | |
3884 | #endif | |
3885 | ||
3886 | err = snd_cs46xx_chip_init(chip); | |
3887 | if (err < 0) { | |
3888 | snd_cs46xx_free(chip); | |
3889 | return err; | |
3890 | } | |
3891 | ||
3892 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { | |
3893 | snd_cs46xx_free(chip); | |
3894 | return err; | |
3895 | } | |
3896 | ||
3897 | snd_cs46xx_proc_init(card, chip); | |
3898 | ||
1da177e4 LT |
3899 | chip->active_ctrl(chip, -1); /* disable CLKRUN */ |
3900 | ||
3901 | snd_card_set_dev(card, &pci->dev); | |
3902 | ||
3903 | *rchip = chip; | |
3904 | return 0; | |
3905 | } |