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[ALSA] sound/: Spelling fixes
[deliverable/linux.git] / sound / pci / cs46xx / cs46xx_lib.c
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1da177e4 1/*
c1017a4c 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 3 * Abramo Bagnara <abramo@alsa-project.org>
4 * Cirrus Logic, Inc.
5 * Routines for control of Cirrus Logic CS461x chips
6 *
7 * KNOWN BUGS:
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
561de31a 11 * the SPDIF input mixer control.
1da177e4
LT		 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
14 *
15 * TODO:
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
20 *
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
24 *
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 *
46 */
47
48#include <sound/driver.h>
49#include <linux/delay.h>
50#include <linux/pci.h>
51#include <linux/pm.h>
52#include <linux/init.h>
53#include <linux/interrupt.h>
54#include <linux/slab.h>
55#include <linux/gameport.h>
62932df8
IM		 56#include <linux/mutex.h>
57
1da177e4
LT		 58
59#include <sound/core.h>
60#include <sound/control.h>
61#include <sound/info.h>
62#include <sound/pcm.h>
63#include <sound/pcm_params.h>
64#include <sound/cs46xx.h>
65
66#include <asm/io.h>
67
68#include "cs46xx_lib.h"
69#include "dsp_spos.h"
70
3d19f804 71static void amp_voyetra(struct snd_cs46xx *chip, int change);
1da177e4
LT		 72
73#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804
TI		 74static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
75static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
76static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
77static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
78static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
79static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
1da177e4
LT		 80#endif
81
3d19f804
TI		 82static struct snd_pcm_ops snd_cs46xx_playback_ops;
83static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
84static struct snd_pcm_ops snd_cs46xx_capture_ops;
85static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
1da177e4 86
3d19f804 87static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
1da177e4
LT		 88 unsigned short reg,
89 int codec_index)
90{
91 int count;
92 unsigned short result,tmp;
93 u32 offset = 0;
94 snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
95 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
96 return -EINVAL);
97
98 chip->active_ctrl(chip, 1);
99
100 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
101 offset = CS46XX_SECONDARY_CODEC_OFFSET;
102
103 /*
104 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
105 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
106 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
107 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
108 * 5. if DCV not cleared, break and return error
109 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
110 */
111
112 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
113
114 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
115 if ((tmp & ACCTL_VFRM) == 0) {
116 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
117 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
118 msleep(50);
119 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
120 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
121
122 }
123
124 /*
125 * Setup the AC97 control registers on the CS461x to send the
126 * appropriate command to the AC97 to perform the read.
127 * ACCAD = Command Address Register = 46Ch
128 * ACCDA = Command Data Register = 470h
129 * ACCTL = Control Register = 460h
130 * set DCV - will clear when process completed
131 * set CRW - Read command
132 * set VFRM - valid frame enabled
133 * set ESYN - ASYNC generation enabled
134 * set RSTN - ARST# inactive, AC97 codec not reset
135 */
136
137 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
138 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
139 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
140 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
141 ACCTL_VFRM | ACCTL_ESYN |
142 ACCTL_RSTN);
143 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
144 ACCTL_VFRM | ACCTL_ESYN |
145 ACCTL_RSTN);
146 } else {
147 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
148 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
149 ACCTL_RSTN);
150 }
151
152 /*
153 * Wait for the read to occur.
154 */
155 for (count = 0; count < 1000; count++) {
156 /*
157 * First, we want to wait for a short time.
158 */
159 udelay(10);
160 /*
161 * Now, check to see if the read has completed.
162 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
163 */
164 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
165 goto ok1;
166 }
167
99b359ba 168 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
1da177e4
LT		 169 result = 0xffff;
170 goto end;
171
172 ok1:
173 /*
174 * Wait for the valid status bit to go active.
175 */
176 for (count = 0; count < 100; count++) {
177 /*
178 * Read the AC97 status register.
179 * ACSTS = Status Register = 464h
180 * VSTS - Valid Status
181 */
182 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
183 goto ok2;
184 udelay(10);
185 }
186
99b359ba 187 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
1da177e4
LT		 188 result = 0xffff;
189 goto end;
190
191 ok2:
192 /*
193 * Read the data returned from the AC97 register.
194 * ACSDA = Status Data Register = 474h
195 */
196#if 0
197 printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
198 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
199 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
200#endif
201
202 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
203 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
204 end:
205 chip->active_ctrl(chip, -1);
206 return result;
207}
208
3d19f804 209static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
1da177e4
LT		 210 unsigned short reg)
211{
3d19f804 212 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 213 unsigned short val;
214 int codec_index = ac97->num;
215
216 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
217 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
218 return 0xffff);
219
220 val = snd_cs46xx_codec_read(chip, reg, codec_index);
221
222 return val;
223}
224
225
3d19f804 226static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
1da177e4
LT		 227 unsigned short reg,
228 unsigned short val,
229 int codec_index)
230{
231 int count;
232
233 snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
234 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
235 return);
236
237 chip->active_ctrl(chip, 1);
238
239 /*
240 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
241 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
242 * 3. Write ACCTL = Control Register = 460h for initiating the write
243 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
244 * 5. if DCV not cleared, break and return error
245 */
246
247 /*
248 * Setup the AC97 control registers on the CS461x to send the
249 * appropriate command to the AC97 to perform the read.
250 * ACCAD = Command Address Register = 46Ch
251 * ACCDA = Command Data Register = 470h
252 * ACCTL = Control Register = 460h
253 * set DCV - will clear when process completed
254 * reset CRW - Write command
255 * set VFRM - valid frame enabled
256 * set ESYN - ASYNC generation enabled
257 * set RSTN - ARST# inactive, AC97 codec not reset
258 */
259 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
260 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
261 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
262
263 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
264 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
265 ACCTL_ESYN | ACCTL_RSTN);
266 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
267 ACCTL_ESYN | ACCTL_RSTN);
268 } else {
269 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
270 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
271 }
272
273 for (count = 0; count < 4000; count++) {
274 /*
275 * First, we want to wait for a short time.
276 */
277 udelay(10);
278 /*
279 * Now, check to see if the write has completed.
280 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
281 */
282 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
283 goto end;
284 }
285 }
99b359ba 286 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
1da177e4
LT		 287 end:
288 chip->active_ctrl(chip, -1);
289}
290
3d19f804 291static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 292 unsigned short reg,
293 unsigned short val)
294{
3d19f804 295 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 296 int codec_index = ac97->num;
297
298 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
299 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
300 return);
301
302 snd_cs46xx_codec_write(chip, reg, val, codec_index);
303}
304
305
306/*
307 * Chip initialization
308 */
309
3d19f804 310int snd_cs46xx_download(struct snd_cs46xx *chip,
1da177e4
LT		 311 u32 *src,
312 unsigned long offset,
313 unsigned long len)
314{
315 void __iomem *dst;
316 unsigned int bank = offset >> 16;
317 offset = offset & 0xffff;
318
319 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
320 dst = chip->region.idx[bank+1].remap_addr + offset;
321 len /= sizeof(u32);
322
323 /* writel already converts 32-bit value to right endianess */
324 while (len-- > 0) {
325 writel(*src++, dst);
326 dst += sizeof(u32);
327 }
328 return 0;
329}
330
331#ifdef CONFIG_SND_CS46XX_NEW_DSP
332
333#include "imgs/cwc4630.h"
334#include "imgs/cwcasync.h"
335#include "imgs/cwcsnoop.h"
336#include "imgs/cwcbinhack.h"
337#include "imgs/cwcdma.h"
338
3d19f804 339int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
1da177e4
LT		 340 unsigned long offset,
341 unsigned long len)
342{
343 void __iomem *dst;
344 unsigned int bank = offset >> 16;
345 offset = offset & 0xffff;
346
347 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
348 dst = chip->region.idx[bank+1].remap_addr + offset;
349 len /= sizeof(u32);
350
351 /* writel already converts 32-bit value to right endianess */
352 while (len-- > 0) {
353 writel(0, dst);
354 dst += sizeof(u32);
355 }
356 return 0;
357}
358
359#else /* old DSP image */
360
361#include "cs46xx_image.h"
362
3d19f804 363int snd_cs46xx_download_image(struct snd_cs46xx *chip)
1da177e4
LT		 364{
365 int idx, err;
366 unsigned long offset = 0;
367
368 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
369 if ((err = snd_cs46xx_download(chip,
370 &BA1Struct.map[offset],
371 BA1Struct.memory[idx].offset,
372 BA1Struct.memory[idx].size)) < 0)
373 return err;
374 offset += BA1Struct.memory[idx].size >> 2;
375 }
376 return 0;
377}
378#endif /* CONFIG_SND_CS46XX_NEW_DSP */
379
380/*
381 * Chip reset
382 */
383
3d19f804 384static void snd_cs46xx_reset(struct snd_cs46xx *chip)
1da177e4
LT		 385{
386 int idx;
387
388 /*
389 * Write the reset bit of the SP control register.
390 */
391 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
392
393 /*
394 * Write the control register.
395 */
396 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
397
398 /*
399 * Clear the trap registers.
400 */
401 for (idx = 0; idx < 8; idx++) {
402 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
403 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
404 }
405 snd_cs46xx_poke(chip, BA1_DREG, 0);
406
407 /*
408 * Set the frame timer to reflect the number of cycles per frame.
409 */
410 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
411}
412
3d19f804 413static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
1da177e4
LT		 414{
415 u32 i, status = 0;
416 /*
417 * Make sure the previous FIFO write operation has completed.
418 */
419 for(i = 0; i < 50; i++){
420 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
421
422 if( !(status & SERBST_WBSY) )
423 break;
424
425 mdelay(retry_timeout);
426 }
427
428 if(status & SERBST_WBSY) {
429 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
430
431 return -EINVAL;
432 }
433
434 return 0;
435}
436
3d19f804 437static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
1da177e4
LT		 438{
439 int idx, powerdown = 0;
440 unsigned int tmp;
441
442 /*
443 * See if the devices are powered down. If so, we must power them up first
444 * or they will not respond.
445 */
446 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
447 if (!(tmp & CLKCR1_SWCE)) {
448 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
449 powerdown = 1;
450 }
451
452 /*
453 * We want to clear out the serial port FIFOs so we don't end up playing
454 * whatever random garbage happens to be in them. We fill the sample FIFOS
455 * with zero (silence).
456 */
457 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
458
459 /*
460 * Fill all 256 sample FIFO locations.
461 */
462 for (idx = 0; idx < 0xFF; idx++) {
463 /*
464 * Make sure the previous FIFO write operation has completed.
465 */
466 if (cs46xx_wait_for_fifo(chip,1)) {
467 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
468
469 if (powerdown)
470 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
471
472 break;
473 }
474 /*
475 * Write the serial port FIFO index.
476 */
477 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
478 /*
479 * Tell the serial port to load the new value into the FIFO location.
480 */
481 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
482 }
483 /*
484 * Now, if we powered up the devices, then power them back down again.
485 * This is kinda ugly, but should never happen.
486 */
487 if (powerdown)
488 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
489}
490
3d19f804 491static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
1da177e4
LT		 492{
493 int cnt;
494
495 /*
496 * Set the frame timer to reflect the number of cycles per frame.
497 */
498 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
499 /*
500 * Turn on the run, run at frame, and DMA enable bits in the local copy of
501 * the SP control register.
502 */
503 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
504 /*
505 * Wait until the run at frame bit resets itself in the SP control
506 * register.
507 */
508 for (cnt = 0; cnt < 25; cnt++) {
509 udelay(50);
510 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
511 break;
512 }
513
514 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
99b359ba 515 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
1da177e4
LT		 516}
517
3d19f804 518static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
1da177e4
LT		 519{
520 /*
521 * Turn off the run, run at frame, and DMA enable bits in the local copy of
522 * the SP control register.
523 */
524 snd_cs46xx_poke(chip, BA1_SPCR, 0);
525}
526
527/*
528 * Sample rate routines
529 */
530
531#define GOF_PER_SEC 200
532
3d19f804 533static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 534{
535 unsigned long flags;
536 unsigned int tmp1, tmp2;
537 unsigned int phiIncr;
538 unsigned int correctionPerGOF, correctionPerSec;
539
540 /*
541 * Compute the values used to drive the actual sample rate conversion.
542 * The following formulas are being computed, using inline assembly
543 * since we need to use 64 bit arithmetic to compute the values:
544 *
545 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
546 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
547 * GOF_PER_SEC)
548 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
549 * GOF_PER_SEC * correctionPerGOF
550 *
551 * i.e.
552 *
553 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
554 * correctionPerGOF:correctionPerSec =
555 * dividend:remainder(ulOther / GOF_PER_SEC)
556 */
557 tmp1 = rate << 16;
558 phiIncr = tmp1 / 48000;
559 tmp1 -= phiIncr * 48000;
560 tmp1 <<= 10;
561 phiIncr <<= 10;
562 tmp2 = tmp1 / 48000;
563 phiIncr += tmp2;
564 tmp1 -= tmp2 * 48000;
565 correctionPerGOF = tmp1 / GOF_PER_SEC;
566 tmp1 -= correctionPerGOF * GOF_PER_SEC;
567 correctionPerSec = tmp1;
568
569 /*
570 * Fill in the SampleRateConverter control block.
571 */
572 spin_lock_irqsave(&chip->reg_lock, flags);
573 snd_cs46xx_poke(chip, BA1_PSRC,
574 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
575 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
576 spin_unlock_irqrestore(&chip->reg_lock, flags);
577}
578
3d19f804 579static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 580{
581 unsigned long flags;
582 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
583 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
584 unsigned int frameGroupLength, cnt;
585
586 /*
587 * We can only decimate by up to a factor of 1/9th the hardware rate.
588 * Correct the value if an attempt is made to stray outside that limit.
589 */
590 if ((rate * 9) < 48000)
591 rate = 48000 / 9;
592
593 /*
594 * We can not capture at at rate greater than the Input Rate (48000).
595 * Return an error if an attempt is made to stray outside that limit.
596 */
597 if (rate > 48000)
598 rate = 48000;
599
600 /*
601 * Compute the values used to drive the actual sample rate conversion.
602 * The following formulas are being computed, using inline assembly
603 * since we need to use 64 bit arithmetic to compute the values:
604 *
605 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
606 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
607 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
608 * GOF_PER_SEC)
609 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
610 * GOF_PER_SEC * correctionPerGOF
611 * initialDelay = ceil((24 * Fs,in) / Fs,out)
612 *
613 * i.e.
614 *
615 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
616 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
617 * correctionPerGOF:correctionPerSec =
618 * dividend:remainder(ulOther / GOF_PER_SEC)
619 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
620 */
621
622 tmp1 = rate << 16;
623 coeffIncr = tmp1 / 48000;
624 tmp1 -= coeffIncr * 48000;
625 tmp1 <<= 7;
626 coeffIncr <<= 7;
627 coeffIncr += tmp1 / 48000;
628 coeffIncr ^= 0xFFFFFFFF;
629 coeffIncr++;
630 tmp1 = 48000 << 16;
631 phiIncr = tmp1 / rate;
632 tmp1 -= phiIncr * rate;
633 tmp1 <<= 10;
634 phiIncr <<= 10;
635 tmp2 = tmp1 / rate;
636 phiIncr += tmp2;
637 tmp1 -= tmp2 * rate;
638 correctionPerGOF = tmp1 / GOF_PER_SEC;
639 tmp1 -= correctionPerGOF * GOF_PER_SEC;
640 correctionPerSec = tmp1;
641 initialDelay = ((48000 * 24) + rate - 1) / rate;
642
643 /*
644 * Fill in the VariDecimate control block.
645 */
646 spin_lock_irqsave(&chip->reg_lock, flags);
647 snd_cs46xx_poke(chip, BA1_CSRC,
648 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
649 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
650 snd_cs46xx_poke(chip, BA1_CD,
651 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
652 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
653 spin_unlock_irqrestore(&chip->reg_lock, flags);
654
655 /*
656 * Figure out the frame group length for the write back task. Basically,
657 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
658 * the output sample rate.
659 */
660 frameGroupLength = 1;
661 for (cnt = 2; cnt <= 64; cnt *= 2) {
662 if (((rate / cnt) * cnt) != rate)
663 frameGroupLength *= 2;
664 }
665 if (((rate / 3) * 3) != rate) {
666 frameGroupLength *= 3;
667 }
668 for (cnt = 5; cnt <= 125; cnt *= 5) {
669 if (((rate / cnt) * cnt) != rate)
670 frameGroupLength *= 5;
671 }
672
673 /*
674 * Fill in the WriteBack control block.
675 */
676 spin_lock_irqsave(&chip->reg_lock, flags);
677 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
678 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
679 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
680 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
681 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
682 spin_unlock_irqrestore(&chip->reg_lock, flags);
683}
684
685/*
686 * PCM part
687 */
688
3d19f804
TI		 689static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
690 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 691{
3d19f804
TI		 692 struct snd_pcm_runtime *runtime = substream->runtime;
693 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 694 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
695}
696
3d19f804 697static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
1da177e4 698{
3d19f804
TI		 699 struct snd_pcm_runtime *runtime = substream->runtime;
700 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 701 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
702 return 0;
703}
704
3d19f804
TI		 705static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
706 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 707{
3d19f804
TI		 708 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
709 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 710 memcpy(runtime->dma_area + rec->sw_data,
711 chip->capt.hw_buf.area + rec->hw_data, bytes);
712}
713
3d19f804 714static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
1da177e4 715{
3d19f804 716 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 717 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
718 return 0;
719}
720
3d19f804 721static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 722{
3d19f804 723 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 724 size_t ptr;
3d19f804 725 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 726 snd_assert (cpcm->pcm_channel,return -ENXIO);
727
728#ifdef CONFIG_SND_CS46XX_NEW_DSP
729 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
730#else
731 ptr = snd_cs46xx_peek(chip, BA1_PBA);
732#endif
733 ptr -= cpcm->hw_buf.addr;
734 return ptr >> cpcm->shift;
735}
736
3d19f804 737static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 738{
3d19f804 739 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 740 size_t ptr;
3d19f804 741 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 742
743#ifdef CONFIG_SND_CS46XX_NEW_DSP
744 snd_assert (cpcm->pcm_channel,return -ENXIO);
745 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
746#else
747 ptr = snd_cs46xx_peek(chip, BA1_PBA);
748#endif
749 ptr -= cpcm->hw_buf.addr;
750 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
751}
752
3d19f804 753static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 754{
3d19f804 755 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 756 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
757 return ptr >> chip->capt.shift;
758}
759
3d19f804 760static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 761{
3d19f804 762 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 763 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
764 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
765}
766
3d19f804 767static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 768 int cmd)
769{
3d19f804
TI		 770 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
771 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
1da177e4
LT		 772 int result = 0;
773
774#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 775 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 776 if (! cpcm->pcm_channel) {
777 return -ENXIO;
778 }
779#endif
780 switch (cmd) {
781 case SNDRV_PCM_TRIGGER_START:
782 case SNDRV_PCM_TRIGGER_RESUME:
783#ifdef CONFIG_SND_CS46XX_NEW_DSP
784 /* magic value to unmute PCM stream playback volume */
785 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
786 SCBVolumeCtrl) << 2, 0x80008000);
787
788 if (cpcm->pcm_channel->unlinked)
789 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
790
791 if (substream->runtime->periods != CS46XX_FRAGS)
792 snd_cs46xx_playback_transfer(substream);
793#else
794 spin_lock(&chip->reg_lock);
795 if (substream->runtime->periods != CS46XX_FRAGS)
796 snd_cs46xx_playback_transfer(substream);
797 { unsigned int tmp;
798 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
799 tmp &= 0x0000ffff;
800 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
801 }
802 spin_unlock(&chip->reg_lock);
803#endif
804 break;
805 case SNDRV_PCM_TRIGGER_STOP:
806 case SNDRV_PCM_TRIGGER_SUSPEND:
807#ifdef CONFIG_SND_CS46XX_NEW_DSP
808 /* magic mute channel */
809 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
810 SCBVolumeCtrl) << 2, 0xffffffff);
811
812 if (!cpcm->pcm_channel->unlinked)
813 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
814#else
815 spin_lock(&chip->reg_lock);
816 { unsigned int tmp;
817 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
818 tmp &= 0x0000ffff;
819 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
820 }
821 spin_unlock(&chip->reg_lock);
822#endif
823 break;
824 default:
825 result = -EINVAL;
826 break;
827 }
828
829 return result;
830}
831
3d19f804 832static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 833 int cmd)
834{
3d19f804 835 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 836 unsigned int tmp;
837 int result = 0;
838
839 spin_lock(&chip->reg_lock);
840 switch (cmd) {
841 case SNDRV_PCM_TRIGGER_START:
842 case SNDRV_PCM_TRIGGER_RESUME:
843 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
844 tmp &= 0xffff0000;
845 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
846 break;
847 case SNDRV_PCM_TRIGGER_STOP:
848 case SNDRV_PCM_TRIGGER_SUSPEND:
849 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
850 tmp &= 0xffff0000;
851 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
852 break;
853 default:
854 result = -EINVAL;
855 break;
856 }
857 spin_unlock(&chip->reg_lock);
858
859 return result;
860}
861
862#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 863static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1da177e4
LT		 864 int sample_rate)
865{
866
867 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
868 if ( cpcm->pcm_channel == NULL) {
869 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
870 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
871 if (cpcm->pcm_channel == NULL) {
872 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
873 return -ENOMEM;
874 }
875 cpcm->pcm_channel->sample_rate = sample_rate;
876 } else
877 /* if sample rate is changed */
878 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
879 int unlinked = cpcm->pcm_channel->unlinked;
880 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
881
882 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
883 cpcm->hw_buf.addr,
884 cpcm->pcm_channel_id)) == NULL) {
885 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
886 return -ENOMEM;
887 }
888
889 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
890 cpcm->pcm_channel->sample_rate = sample_rate;
891 }
892
893 return 0;
894}
895#endif
896
897
3d19f804
TI		 898static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
899 struct snd_pcm_hw_params *hw_params)
1da177e4 900{
3d19f804
TI		 901 struct snd_pcm_runtime *runtime = substream->runtime;
902 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 903 int err;
904#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 905 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 906 int sample_rate = params_rate(hw_params);
907 int period_size = params_period_bytes(hw_params);
908#endif
909 cpcm = runtime->private_data;
910
911#ifdef CONFIG_SND_CS46XX_NEW_DSP
912 snd_assert (sample_rate != 0, return -ENXIO);
913
62932df8 914 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 915
916 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
62932df8 917 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 918 return -ENXIO;
919 }
920
921 snd_assert (cpcm->pcm_channel != NULL);
922 if (!cpcm->pcm_channel) {
62932df8 923 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 924 return -ENXIO;
925 }
926
927
928 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
62932df8 929 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 930 return -EINVAL;
931 }
932
933 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
934 period_size, params_periods(hw_params),
935 params_buffer_bytes(hw_params));
936#endif
937
938 if (params_periods(hw_params) == CS46XX_FRAGS) {
939 if (runtime->dma_area != cpcm->hw_buf.area)
940 snd_pcm_lib_free_pages(substream);
941 runtime->dma_area = cpcm->hw_buf.area;
942 runtime->dma_addr = cpcm->hw_buf.addr;
943 runtime->dma_bytes = cpcm->hw_buf.bytes;
944
945
946#ifdef CONFIG_SND_CS46XX_NEW_DSP
947 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
948 substream->ops = &snd_cs46xx_playback_ops;
949 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
950 substream->ops = &snd_cs46xx_playback_rear_ops;
951 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
952 substream->ops = &snd_cs46xx_playback_clfe_ops;
953 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
954 substream->ops = &snd_cs46xx_playback_iec958_ops;
955 } else {
956 snd_assert(0);
957 }
958#else
959 substream->ops = &snd_cs46xx_playback_ops;
960#endif
961
962 } else {
963 if (runtime->dma_area == cpcm->hw_buf.area) {
964 runtime->dma_area = NULL;
965 runtime->dma_addr = 0;
966 runtime->dma_bytes = 0;
967 }
968 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
969#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 970 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 971#endif
972 return err;
973 }
974
975#ifdef CONFIG_SND_CS46XX_NEW_DSP
976 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
977 substream->ops = &snd_cs46xx_playback_indirect_ops;
978 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
979 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
980 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
981 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
982 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
983 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
984 } else {
985 snd_assert(0);
986 }
987#else
988 substream->ops = &snd_cs46xx_playback_indirect_ops;
989#endif
990
991 }
992
993#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 994 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 995#endif
996
997 return 0;
998}
999
3d19f804 1000static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4 1001{
3d19f804
TI		 1002 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1003 struct snd_pcm_runtime *runtime = substream->runtime;
1004 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1005
1006 cpcm = runtime->private_data;
1007
1008 /* if play_back open fails, then this function
1009 is called and cpcm can actually be NULL here */
1010 if (!cpcm) return -ENXIO;
1011
1012 if (runtime->dma_area != cpcm->hw_buf.area)
1013 snd_pcm_lib_free_pages(substream);
1014
1015 runtime->dma_area = NULL;
1016 runtime->dma_addr = 0;
1017 runtime->dma_bytes = 0;
1018
1019 return 0;
1020}
1021
3d19f804 1022static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1023{
1024 unsigned int tmp;
1025 unsigned int pfie;
3d19f804
TI		 1026 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1027 struct snd_pcm_runtime *runtime = substream->runtime;
1028 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1029
1030 cpcm = runtime->private_data;
1031
1032#ifdef CONFIG_SND_CS46XX_NEW_DSP
1033 snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1034
1035 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1036 pfie &= ~0x0000f03f;
1037#else
1038 /* old dsp */
1039 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1040 pfie &= ~0x0000f03f;
1041#endif
1042
1043 cpcm->shift = 2;
1044 /* if to convert from stereo to mono */
1045 if (runtime->channels == 1) {
1046 cpcm->shift--;
1047 pfie |= 0x00002000;
1048 }
1049 /* if to convert from 8 bit to 16 bit */
1050 if (snd_pcm_format_width(runtime->format) == 8) {
1051 cpcm->shift--;
1052 pfie |= 0x00001000;
1053 }
1054 /* if to convert to unsigned */
1055 if (snd_pcm_format_unsigned(runtime->format))
1056 pfie |= 0x00008000;
1057
1058 /* Never convert byte order when sample stream is 8 bit */
1059 if (snd_pcm_format_width(runtime->format) != 8) {
1060 /* convert from big endian to little endian */
1061 if (snd_pcm_format_big_endian(runtime->format))
1062 pfie |= 0x00004000;
1063 }
1064
1065 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1066 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1067 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1068
1069#ifdef CONFIG_SND_CS46XX_NEW_DSP
1070
1071 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1072 tmp &= ~0x000003ff;
1073 tmp |= (4 << cpcm->shift) - 1;
1074 /* playback transaction count register */
1075 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1076
1077 /* playback format && interrupt enable */
1078 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1079#else
1080 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1081 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1082 tmp &= ~0x000003ff;
1083 tmp |= (4 << cpcm->shift) - 1;
1084 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1085 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1086 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1087#endif
1088
1089 return 0;
1090}
1091
3d19f804
TI		 1092static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1093 struct snd_pcm_hw_params *hw_params)
1da177e4 1094{
3d19f804
TI		 1095 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1096 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1097 int err;
1098
1099#ifdef CONFIG_SND_CS46XX_NEW_DSP
1100 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1101#endif
1102 if (runtime->periods == CS46XX_FRAGS) {
1103 if (runtime->dma_area != chip->capt.hw_buf.area)
1104 snd_pcm_lib_free_pages(substream);
1105 runtime->dma_area = chip->capt.hw_buf.area;
1106 runtime->dma_addr = chip->capt.hw_buf.addr;
1107 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1108 substream->ops = &snd_cs46xx_capture_ops;
1109 } else {
1110 if (runtime->dma_area == chip->capt.hw_buf.area) {
1111 runtime->dma_area = NULL;
1112 runtime->dma_addr = 0;
1113 runtime->dma_bytes = 0;
1114 }
1115 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1116 return err;
1117 substream->ops = &snd_cs46xx_capture_indirect_ops;
1118 }
1119
1120 return 0;
1121}
1122
3d19f804 1123static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4 1124{
3d19f804
TI		 1125 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1126 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1127
1128 if (runtime->dma_area != chip->capt.hw_buf.area)
1129 snd_pcm_lib_free_pages(substream);
1130 runtime->dma_area = NULL;
1131 runtime->dma_addr = 0;
1132 runtime->dma_bytes = 0;
1133
1134 return 0;
1135}
1136
3d19f804 1137static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1138{
3d19f804
TI		 1139 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1140 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1141
1142 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1143 chip->capt.shift = 2;
1144 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1145 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1146 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1147 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1148
1149 return 0;
1150}
1151
7d12e780 1152static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1da177e4 1153{
3d19f804 1154 struct snd_cs46xx *chip = dev_id;
1da177e4
LT		 1155 u32 status1;
1156#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1157 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1158 u32 status2;
1159 int i;
3d19f804 1160 struct snd_cs46xx_pcm *cpcm = NULL;
1da177e4
LT		 1161#endif
1162
1163 /*
1164 * Read the Interrupt Status Register to clear the interrupt
1165 */
1166 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1167 if ((status1 & 0x7fffffff) == 0) {
1168 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1169 return IRQ_NONE;
1170 }
1171
1172#ifdef CONFIG_SND_CS46XX_NEW_DSP
1173 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1174
1175 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1176 if (i <= 15) {
1177 if ( status1 & (1 << i) ) {
1178 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1179 if (chip->capt.substream)
1180 snd_pcm_period_elapsed(chip->capt.substream);
1181 } else {
1182 if (ins->pcm_channels[i].active &&
1183 ins->pcm_channels[i].private_data &&
1184 !ins->pcm_channels[i].unlinked) {
1185 cpcm = ins->pcm_channels[i].private_data;
1186 snd_pcm_period_elapsed(cpcm->substream);
1187 }
1188 }
1189 }
1190 } else {
1191 if ( status2 & (1 << (i - 16))) {
1192 if (ins->pcm_channels[i].active &&
1193 ins->pcm_channels[i].private_data &&
1194 !ins->pcm_channels[i].unlinked) {
1195 cpcm = ins->pcm_channels[i].private_data;
1196 snd_pcm_period_elapsed(cpcm->substream);
1197 }
1198 }
1199 }
1200 }
1201
1202#else
1203 /* old dsp */
1204 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1205 if (chip->playback_pcm->substream)
1206 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1207 }
1208 if ((status1 & HISR_VC1) && chip->pcm) {
1209 if (chip->capt.substream)
1210 snd_pcm_period_elapsed(chip->capt.substream);
1211 }
1212#endif
1213
1214 if ((status1 & HISR_MIDI) && chip->rmidi) {
1215 unsigned char c;
1216
1217 spin_lock(&chip->reg_lock);
1218 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1219 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1220 if ((chip->midcr & MIDCR_RIE) == 0)
1221 continue;
1222 snd_rawmidi_receive(chip->midi_input, &c, 1);
1223 }
1224 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1225 if ((chip->midcr & MIDCR_TIE) == 0)
1226 break;
1227 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1228 chip->midcr &= ~MIDCR_TIE;
1229 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1230 break;
1231 }
1232 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1233 }
1234 spin_unlock(&chip->reg_lock);
1235 }
1236 /*
1237 * EOI to the PCI part....reenables interrupts
1238 */
1239 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1240
1241 return IRQ_HANDLED;
1242}
1243
3d19f804 1244static struct snd_pcm_hardware snd_cs46xx_playback =
1da177e4
LT		 1245{
1246 .info = (SNDRV_PCM_INFO_MMAP |
1247 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1248 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1249 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1250 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1251 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1252 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1253 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1254 .rate_min = 5500,
1255 .rate_max = 48000,
1256 .channels_min = 1,
1257 .channels_max = 2,
1258 .buffer_bytes_max = (256 * 1024),
1259 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1260 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1261 .periods_min = CS46XX_FRAGS,
1262 .periods_max = 1024,
1263 .fifo_size = 0,
1264};
1265
3d19f804 1266static struct snd_pcm_hardware snd_cs46xx_capture =
1da177e4
LT		 1267{
1268 .info = (SNDRV_PCM_INFO_MMAP |
1269 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1270 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1271 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1272 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1273 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1274 .rate_min = 5500,
1275 .rate_max = 48000,
1276 .channels_min = 2,
1277 .channels_max = 2,
1278 .buffer_bytes_max = (256 * 1024),
1279 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1280 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1281 .periods_min = CS46XX_FRAGS,
1282 .periods_max = 1024,
1283 .fifo_size = 0,
1284};
1285
1286#ifdef CONFIG_SND_CS46XX_NEW_DSP
1287
1288static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1289
3d19f804 1290static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1da177e4
LT		 1291 .count = ARRAY_SIZE(period_sizes),
1292 .list = period_sizes,
1293 .mask = 0
1294};
1295
1296#endif
1297
3d19f804 1298static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1da177e4 1299{
4d572776 1300 kfree(runtime->private_data);
1da177e4
LT		 1301}
1302
3d19f804 1303static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1da177e4 1304{
3d19f804
TI		 1305 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1306 struct snd_cs46xx_pcm * cpcm;
1307 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1308
e560d8d8 1309 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1da177e4
LT		 1310 if (cpcm == NULL)
1311 return -ENOMEM;
1312 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1313 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1314 kfree(cpcm);
1315 return -ENOMEM;
1316 }
1317
1318 runtime->hw = snd_cs46xx_playback;
1319 runtime->private_data = cpcm;
1320 runtime->private_free = snd_cs46xx_pcm_free_substream;
1321
1322 cpcm->substream = substream;
1323#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1324 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1325 cpcm->pcm_channel = NULL;
1326 cpcm->pcm_channel_id = pcm_channel_id;
1327
1328
1329 snd_pcm_hw_constraint_list(runtime, 0,
1330 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1331 &hw_constraints_period_sizes);
1332
62932df8 1333 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1334#else
1335 chip->playback_pcm = cpcm; /* HACK */
1336#endif
1337
1338 if (chip->accept_valid)
1339 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1340 chip->active_ctrl(chip, 1);
1341
1342 return 0;
1343}
1344
3d19f804 1345static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1346{
1347 snd_printdd("open front channel\n");
1348 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1349}
1350
1351#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1352static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1da177e4
LT		 1353{
1354 snd_printdd("open rear channel\n");
1355
1356 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1357}
1358
3d19f804 1359static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1da177e4
LT		 1360{
1361 snd_printdd("open center - LFE channel\n");
1362
1363 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1364}
1365
3d19f804 1366static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1da177e4 1367{
3d19f804 1368 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1369
1370 snd_printdd("open raw iec958 channel\n");
1371
62932df8 1372 mutex_lock(&chip->spos_mutex);
1da177e4 1373 cs46xx_iec958_pre_open (chip);
62932df8 1374 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1375
1376 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1377}
1378
3d19f804 1379static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1da177e4 1380
3d19f804 1381static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1da177e4
LT		 1382{
1383 int err;
3d19f804 1384 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1385
1386 snd_printdd("close raw iec958 channel\n");
1387
1388 err = snd_cs46xx_playback_close(substream);
1389
62932df8 1390 mutex_lock(&chip->spos_mutex);
1da177e4 1391 cs46xx_iec958_post_close (chip);
62932df8 1392 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1393
1394 return err;
1395}
1396#endif
1397
3d19f804 1398static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1da177e4 1399{
3d19f804 1400 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1401
1402 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1403 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1404 return -ENOMEM;
1405 chip->capt.substream = substream;
1406 substream->runtime->hw = snd_cs46xx_capture;
1407
1408 if (chip->accept_valid)
1409 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1410
1411 chip->active_ctrl(chip, 1);
1412
1413#ifdef CONFIG_SND_CS46XX_NEW_DSP
1414 snd_pcm_hw_constraint_list(substream->runtime, 0,
1415 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1416 &hw_constraints_period_sizes);
1417#endif
1418 return 0;
1419}
1420
3d19f804 1421static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1da177e4 1422{
3d19f804
TI		 1423 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1424 struct snd_pcm_runtime *runtime = substream->runtime;
1425 struct snd_cs46xx_pcm * cpcm;
1da177e4
LT		 1426
1427 cpcm = runtime->private_data;
1428
1429 /* when playback_open fails, then cpcm can be NULL */
1430 if (!cpcm) return -ENXIO;
1431
1432#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1433 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1434 if (cpcm->pcm_channel) {
1435 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1436 cpcm->pcm_channel = NULL;
1437 }
62932df8 1438 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1439#else
1440 chip->playback_pcm = NULL;
1441#endif
1442
1443 cpcm->substream = NULL;
1444 snd_dma_free_pages(&cpcm->hw_buf);
1445 chip->active_ctrl(chip, -1);
1446
1447 return 0;
1448}
1449
3d19f804 1450static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1da177e4 1451{
3d19f804 1452 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1453
1454 chip->capt.substream = NULL;
1455 snd_dma_free_pages(&chip->capt.hw_buf);
1456 chip->active_ctrl(chip, -1);
1457
1458 return 0;
1459}
1460
1461#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1462static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1da177e4
LT		 1463 .open = snd_cs46xx_playback_open_rear,
1464 .close = snd_cs46xx_playback_close,
1465 .ioctl = snd_pcm_lib_ioctl,
1466 .hw_params = snd_cs46xx_playback_hw_params,
1467 .hw_free = snd_cs46xx_playback_hw_free,
1468 .prepare = snd_cs46xx_playback_prepare,
1469 .trigger = snd_cs46xx_playback_trigger,
1470 .pointer = snd_cs46xx_playback_direct_pointer,
1471};
1472
3d19f804 1473static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1da177e4
LT		 1474 .open = snd_cs46xx_playback_open_rear,
1475 .close = snd_cs46xx_playback_close,
1476 .ioctl = snd_pcm_lib_ioctl,
1477 .hw_params = snd_cs46xx_playback_hw_params,
1478 .hw_free = snd_cs46xx_playback_hw_free,
1479 .prepare = snd_cs46xx_playback_prepare,
1480 .trigger = snd_cs46xx_playback_trigger,
1481 .pointer = snd_cs46xx_playback_indirect_pointer,
1482 .ack = snd_cs46xx_playback_transfer,
1483};
1484
3d19f804 1485static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1da177e4
LT		 1486 .open = snd_cs46xx_playback_open_clfe,
1487 .close = snd_cs46xx_playback_close,
1488 .ioctl = snd_pcm_lib_ioctl,
1489 .hw_params = snd_cs46xx_playback_hw_params,
1490 .hw_free = snd_cs46xx_playback_hw_free,
1491 .prepare = snd_cs46xx_playback_prepare,
1492 .trigger = snd_cs46xx_playback_trigger,
1493 .pointer = snd_cs46xx_playback_direct_pointer,
1494};
1495
3d19f804 1496static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1da177e4
LT		 1497 .open = snd_cs46xx_playback_open_clfe,
1498 .close = snd_cs46xx_playback_close,
1499 .ioctl = snd_pcm_lib_ioctl,
1500 .hw_params = snd_cs46xx_playback_hw_params,
1501 .hw_free = snd_cs46xx_playback_hw_free,
1502 .prepare = snd_cs46xx_playback_prepare,
1503 .trigger = snd_cs46xx_playback_trigger,
1504 .pointer = snd_cs46xx_playback_indirect_pointer,
1505 .ack = snd_cs46xx_playback_transfer,
1506};
1507
3d19f804 1508static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1da177e4
LT		 1509 .open = snd_cs46xx_playback_open_iec958,
1510 .close = snd_cs46xx_playback_close_iec958,
1511 .ioctl = snd_pcm_lib_ioctl,
1512 .hw_params = snd_cs46xx_playback_hw_params,
1513 .hw_free = snd_cs46xx_playback_hw_free,
1514 .prepare = snd_cs46xx_playback_prepare,
1515 .trigger = snd_cs46xx_playback_trigger,
1516 .pointer = snd_cs46xx_playback_direct_pointer,
1517};
1518
3d19f804 1519static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1da177e4
LT		 1520 .open = snd_cs46xx_playback_open_iec958,
1521 .close = snd_cs46xx_playback_close_iec958,
1522 .ioctl = snd_pcm_lib_ioctl,
1523 .hw_params = snd_cs46xx_playback_hw_params,
1524 .hw_free = snd_cs46xx_playback_hw_free,
1525 .prepare = snd_cs46xx_playback_prepare,
1526 .trigger = snd_cs46xx_playback_trigger,
1527 .pointer = snd_cs46xx_playback_indirect_pointer,
1528 .ack = snd_cs46xx_playback_transfer,
1529};
1530
1531#endif
1532
3d19f804 1533static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1da177e4
LT		 1534 .open = snd_cs46xx_playback_open,
1535 .close = snd_cs46xx_playback_close,
1536 .ioctl = snd_pcm_lib_ioctl,
1537 .hw_params = snd_cs46xx_playback_hw_params,
1538 .hw_free = snd_cs46xx_playback_hw_free,
1539 .prepare = snd_cs46xx_playback_prepare,
1540 .trigger = snd_cs46xx_playback_trigger,
1541 .pointer = snd_cs46xx_playback_direct_pointer,
1542};
1543
3d19f804 1544static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1da177e4
LT		 1545 .open = snd_cs46xx_playback_open,
1546 .close = snd_cs46xx_playback_close,
1547 .ioctl = snd_pcm_lib_ioctl,
1548 .hw_params = snd_cs46xx_playback_hw_params,
1549 .hw_free = snd_cs46xx_playback_hw_free,
1550 .prepare = snd_cs46xx_playback_prepare,
1551 .trigger = snd_cs46xx_playback_trigger,
1552 .pointer = snd_cs46xx_playback_indirect_pointer,
1553 .ack = snd_cs46xx_playback_transfer,
1554};
1555
3d19f804 1556static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1da177e4
LT		 1557 .open = snd_cs46xx_capture_open,
1558 .close = snd_cs46xx_capture_close,
1559 .ioctl = snd_pcm_lib_ioctl,
1560 .hw_params = snd_cs46xx_capture_hw_params,
1561 .hw_free = snd_cs46xx_capture_hw_free,
1562 .prepare = snd_cs46xx_capture_prepare,
1563 .trigger = snd_cs46xx_capture_trigger,
1564 .pointer = snd_cs46xx_capture_direct_pointer,
1565};
1566
3d19f804 1567static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1da177e4
LT		 1568 .open = snd_cs46xx_capture_open,
1569 .close = snd_cs46xx_capture_close,
1570 .ioctl = snd_pcm_lib_ioctl,
1571 .hw_params = snd_cs46xx_capture_hw_params,
1572 .hw_free = snd_cs46xx_capture_hw_free,
1573 .prepare = snd_cs46xx_capture_prepare,
1574 .trigger = snd_cs46xx_capture_trigger,
1575 .pointer = snd_cs46xx_capture_indirect_pointer,
1576 .ack = snd_cs46xx_capture_transfer,
1577};
1578
1da177e4 1579#ifdef CONFIG_SND_CS46XX_NEW_DSP
1da177e4
LT		 1580#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1581#else
1582#define MAX_PLAYBACK_CHANNELS 1
1583#endif
1584
3d19f804 1585int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1586{
3d19f804 1587 struct snd_pcm *pcm;
1da177e4
LT		 1588 int err;
1589
1590 if (rpcm)
1591 *rpcm = NULL;
1592 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1593 return err;
1594
1595 pcm->private_data = chip;
1da177e4
LT		 1596
1597 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1598 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1599
1600 /* global setup */
1601 pcm->info_flags = 0;
1602 strcpy(pcm->name, "CS46xx");
1603 chip->pcm = pcm;
1604
1605 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1606 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1607
1608 if (rpcm)
1609 *rpcm = pcm;
1610
1611 return 0;
1612}
1613
1614
1615#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1616int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1617{
3d19f804 1618 struct snd_pcm *pcm;
1da177e4
LT		 1619 int err;
1620
1621 if (rpcm)
1622 *rpcm = NULL;
1623
1624 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1625 return err;
1626
1627 pcm->private_data = chip;
1da177e4
LT		 1628
1629 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1630
1631 /* global setup */
1632 pcm->info_flags = 0;
1633 strcpy(pcm->name, "CS46xx - Rear");
1634 chip->pcm_rear = pcm;
1635
1636 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1637 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1638
1639 if (rpcm)
1640 *rpcm = pcm;
1641
1642 return 0;
1643}
1644
3d19f804 1645int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1646{
3d19f804 1647 struct snd_pcm *pcm;
1da177e4
LT		 1648 int err;
1649
1650 if (rpcm)
1651 *rpcm = NULL;
1652
1653 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1654 return err;
1655
1656 pcm->private_data = chip;
1da177e4
LT		 1657
1658 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1659
1660 /* global setup */
1661 pcm->info_flags = 0;
1662 strcpy(pcm->name, "CS46xx - Center LFE");
1663 chip->pcm_center_lfe = pcm;
1664
1665 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1666 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1667
1668 if (rpcm)
1669 *rpcm = pcm;
1670
1671 return 0;
1672}
1673
3d19f804 1674int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1675{
3d19f804 1676 struct snd_pcm *pcm;
1da177e4
LT		 1677 int err;
1678
1679 if (rpcm)
1680 *rpcm = NULL;
1681
1682 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1683 return err;
1684
1685 pcm->private_data = chip;
1da177e4
LT		 1686
1687 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1688
1689 /* global setup */
1690 pcm->info_flags = 0;
1691 strcpy(pcm->name, "CS46xx - IEC958");
1692 chip->pcm_rear = pcm;
1693
1694 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1695 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1696
1697 if (rpcm)
1698 *rpcm = pcm;
1699
1700 return 0;
1701}
1702#endif
1703
1704/*
1705 * Mixer routines
1706 */
3d19f804 1707static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1708{
3d19f804 1709 struct snd_cs46xx *chip = bus->private_data;
1da177e4
LT		 1710
1711 chip->ac97_bus = NULL;
1712}
1713
3d19f804 1714static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1715{
3d19f804 1716 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 1717
1718 snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1719 (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1720 return);
1721
1722 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1723 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1724 chip->eapd_switch = NULL;
1725 }
1726 else
1727 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1728}
1729
3d19f804
TI		 1730static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1731 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1732{
1733 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1734 uinfo->count = 2;
1735 uinfo->value.integer.min = 0;
1736 uinfo->value.integer.max = 0x7fff;
1737 return 0;
1738}
1739
3d19f804 1740static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1741{
3d19f804 1742 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1743 int reg = kcontrol->private_value;
1744 unsigned int val = snd_cs46xx_peek(chip, reg);
1745 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1746 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1747 return 0;
1748}
1749
3d19f804 1750static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1751{
3d19f804 1752 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1753 int reg = kcontrol->private_value;
1754 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1755 (0xffff - ucontrol->value.integer.value[1]));
1756 unsigned int old = snd_cs46xx_peek(chip, reg);
1757 int change = (old != val);
1758
1759 if (change) {
1760 snd_cs46xx_poke(chip, reg, val);
1761 }
1762
1763 return change;
1764}
1765
1766#ifdef CONFIG_SND_CS46XX_NEW_DSP
1767
3d19f804 1768static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1769{
3d19f804 1770 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1771
1772 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1773 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1774
1775 return 0;
1776}
1777
3d19f804 1778static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1779{
3d19f804 1780 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1781 int change = 0;
1782
1783 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1784 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1785 cs46xx_dsp_set_dac_volume(chip,
1786 ucontrol->value.integer.value[0],
1787 ucontrol->value.integer.value[1]);
1788 change = 1;
1789 }
1790
1791 return change;
1792}
1793
1794#if 0
3d19f804 1795static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1796{
3d19f804 1797 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1798
1799 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1800 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1801 return 0;
1802}
1803
3d19f804 1804static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1805{
3d19f804 1806 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1807 int change = 0;
1808
1809 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1810 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1811 cs46xx_dsp_set_iec958_volume (chip,
1812 ucontrol->value.integer.value[0],
1813 ucontrol->value.integer.value[1]);
1814 change = 1;
1815 }
1816
1817 return change;
1818}
1819#endif
1820
a5ce8890 1821#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1da177e4 1822
3d19f804
TI		 1823static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1824 struct snd_ctl_elem_value *ucontrol)
1da177e4 1825{
3d19f804 1826 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1827 int reg = kcontrol->private_value;
1828
1829 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1830 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1831 else
1832 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1833
1834 return 0;
1835}
1836
3d19f804
TI		 1837static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1838 struct snd_ctl_elem_value *ucontrol)
1da177e4 1839{
3d19f804 1840 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1841 int change, res;
1842
1843 switch (kcontrol->private_value) {
1844 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
62932df8 1845 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1846 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1847 if (ucontrol->value.integer.value[0] && !change)
1848 cs46xx_dsp_enable_spdif_out(chip);
1849 else if (change && !ucontrol->value.integer.value[0])
1850 cs46xx_dsp_disable_spdif_out(chip);
1851
1852 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
62932df8 1853 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1854 break;
1855 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1856 change = chip->dsp_spos_instance->spdif_status_in;
1857 if (ucontrol->value.integer.value[0] && !change) {
1858 cs46xx_dsp_enable_spdif_in(chip);
1859 /* restore volume */
1860 }
1861 else if (change && !ucontrol->value.integer.value[0])
1862 cs46xx_dsp_disable_spdif_in(chip);
1863
1864 res = (change != chip->dsp_spos_instance->spdif_status_in);
1865 break;
1866 default:
1867 res = -EINVAL;
1868 snd_assert(0, (void)0);
1869 }
1870
1871 return res;
1872}
1873
3d19f804
TI		 1874static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
1875 struct snd_ctl_elem_value *ucontrol)
1da177e4 1876{
3d19f804
TI		 1877 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1878 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1879
1880 if (ins->adc_input != NULL)
1881 ucontrol->value.integer.value[0] = 1;
1882 else
1883 ucontrol->value.integer.value[0] = 0;
1884
1885 return 0;
1886}
1887
3d19f804
TI		 1888static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
1889 struct snd_ctl_elem_value *ucontrol)
1da177e4 1890{
3d19f804
TI		 1891 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1892 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1893 int change = 0;
1894
1895 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1896 cs46xx_dsp_enable_adc_capture(chip);
1897 change = 1;
1898 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1899 cs46xx_dsp_disable_adc_capture(chip);
1900 change = 1;
1901 }
1902 return change;
1903}
1904
3d19f804
TI		 1905static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
1906 struct snd_ctl_elem_value *ucontrol)
1da177e4 1907{
3d19f804
TI		 1908 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1909 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1910
1911 if (ins->pcm_input != NULL)
1912 ucontrol->value.integer.value[0] = 1;
1913 else
1914 ucontrol->value.integer.value[0] = 0;
1915
1916 return 0;
1917}
1918
1919
3d19f804
TI		 1920static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
1921 struct snd_ctl_elem_value *ucontrol)
1da177e4 1922{
3d19f804
TI		 1923 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1924 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1925 int change = 0;
1926
1927 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1928 cs46xx_dsp_enable_pcm_capture(chip);
1929 change = 1;
1930 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1931 cs46xx_dsp_disable_pcm_capture(chip);
1932 change = 1;
1933 }
1934
1935 return change;
1936}
1937
3d19f804
TI		 1938static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
1939 struct snd_ctl_elem_value *ucontrol)
1da177e4 1940{
3d19f804 1941 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1942
1943 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1944
1945 if (val1 & EGPIODR_GPOE0)
1946 ucontrol->value.integer.value[0] = 1;
1947 else
1948 ucontrol->value.integer.value[0] = 0;
1949
1950 return 0;
1951}
1952
1953/*
1954 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1955 */
3d19f804
TI		 1956static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
1957 struct snd_ctl_elem_value *ucontrol)
1da177e4 1958{
3d19f804 1959 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1960 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1961 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1962
1963 if (ucontrol->value.integer.value[0]) {
1964 /* optical is default */
1965 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1966 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
1967 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1968 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1969 } else {
1970 /* coaxial */
1971 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
1972 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
1973 }
1974
1975 /* checking diff from the EGPIO direction register
1976 should be enough */
1977 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
1978}
1979
1980
3d19f804 1981static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1982{
1983 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1984 uinfo->count = 1;
1985 return 0;
1986}
1987
3d19f804
TI		 1988static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
1989 struct snd_ctl_elem_value *ucontrol)
1da177e4 1990{
3d19f804
TI		 1991 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1992 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 1993
62932df8 1994 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1995 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
1996 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
1997 ucontrol->value.iec958.status[2] = 0;
1998 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
62932df8 1999 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2000
2001 return 0;
2002}
2003
3d19f804
TI		 2004static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
1da177e4 2006{
3d19f804
TI		 2007 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2008 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2009 unsigned int val;
2010 int change;
2011
62932df8 2012 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2013 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2014 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2015 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2016 /* left and right validity bit */
2017 (1 << 13) | (1 << 12);
2018
2019
2020 change = (unsigned int)ins->spdif_csuv_default != val;
2021 ins->spdif_csuv_default = val;
2022
2023 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2024 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2025
62932df8 2026 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2027
2028 return change;
2029}
2030
3d19f804
TI		 2031static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2032 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2033{
2034 ucontrol->value.iec958.status[0] = 0xff;
2035 ucontrol->value.iec958.status[1] = 0xff;
2036 ucontrol->value.iec958.status[2] = 0x00;
2037 ucontrol->value.iec958.status[3] = 0xff;
2038 return 0;
2039}
2040
3d19f804
TI		 2041static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2042 struct snd_ctl_elem_value *ucontrol)
1da177e4 2043{
3d19f804
TI		 2044 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2045 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 2046
62932df8 2047 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2048 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2049 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2050 ucontrol->value.iec958.status[2] = 0;
2051 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
62932df8 2052 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2053
2054 return 0;
2055}
2056
3d19f804
TI		 2057static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2058 struct snd_ctl_elem_value *ucontrol)
1da177e4 2059{
3d19f804
TI		 2060 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2061 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2062 unsigned int val;
2063 int change;
2064
62932df8 2065 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2066 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2067 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2068 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2069 /* left and right validity bit */
2070 (1 << 13) | (1 << 12);
2071
2072
2073 change = ins->spdif_csuv_stream != val;
2074 ins->spdif_csuv_stream = val;
2075
2076 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2077 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2078
62932df8 2079 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2080
2081 return change;
2082}
2083
2084#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2085
2086
3d19f804 2087static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = {
1da177e4
LT		 2088{
2089 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2090 .name = "DAC Volume",
2091 .info = snd_cs46xx_vol_info,
2092#ifndef CONFIG_SND_CS46XX_NEW_DSP
2093 .get = snd_cs46xx_vol_get,
2094 .put = snd_cs46xx_vol_put,
2095 .private_value = BA1_PVOL,
2096#else
2097 .get = snd_cs46xx_vol_dac_get,
2098 .put = snd_cs46xx_vol_dac_put,
2099#endif
2100},
2101
2102{
2103 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2104 .name = "ADC Volume",
2105 .info = snd_cs46xx_vol_info,
2106 .get = snd_cs46xx_vol_get,
2107 .put = snd_cs46xx_vol_put,
2108#ifndef CONFIG_SND_CS46XX_NEW_DSP
2109 .private_value = BA1_CVOL,
2110#else
2111 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2112#endif
2113},
2114#ifdef CONFIG_SND_CS46XX_NEW_DSP
2115{
2116 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2117 .name = "ADC Capture Switch",
2118 .info = snd_mixer_boolean_info,
2119 .get = snd_cs46xx_adc_capture_get,
2120 .put = snd_cs46xx_adc_capture_put
2121},
2122{
2123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2124 .name = "DAC Capture Switch",
2125 .info = snd_mixer_boolean_info,
2126 .get = snd_cs46xx_pcm_capture_get,
2127 .put = snd_cs46xx_pcm_capture_put
2128},
2129{
2130 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2131 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
1da177e4
LT		 2132 .info = snd_mixer_boolean_info,
2133 .get = snd_cs46xx_iec958_get,
2134 .put = snd_cs46xx_iec958_put,
2135 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2136},
2137{
2138 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2139 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
1da177e4
LT		 2140 .info = snd_mixer_boolean_info,
2141 .get = snd_cs46xx_iec958_get,
2142 .put = snd_cs46xx_iec958_put,
2143 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2144},
2145#if 0
2146/* Input IEC958 volume does not work for the moment. (Benny) */
2147{
2148 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2149 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
1da177e4
LT		 2150 .info = snd_cs46xx_vol_info,
2151 .get = snd_cs46xx_vol_iec958_get,
2152 .put = snd_cs46xx_vol_iec958_put,
2153 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2154},
2155#endif
2156{
2157 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2158 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2159 .info = snd_cs46xx_spdif_info,
2160 .get = snd_cs46xx_spdif_default_get,
2161 .put = snd_cs46xx_spdif_default_put,
2162},
2163{
2164 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2165 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2166 .info = snd_cs46xx_spdif_info,
2167 .get = snd_cs46xx_spdif_mask_get,
2168 .access = SNDRV_CTL_ELEM_ACCESS_READ
2169},
2170{
2171 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2172 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2173 .info = snd_cs46xx_spdif_info,
2174 .get = snd_cs46xx_spdif_stream_get,
2175 .put = snd_cs46xx_spdif_stream_put
2176},
2177
1da177e4
LT		 2178#endif
2179};
2180
2181#ifdef CONFIG_SND_CS46XX_NEW_DSP
2182/* set primary cs4294 codec into Extended Audio Mode */
3d19f804
TI		 2183static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2184 struct snd_ctl_elem_value *ucontrol)
1da177e4 2185{
3d19f804 2186 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2187 unsigned short val;
2188 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2189 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2190 return 0;
2191}
2192
3d19f804
TI		 2193static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2194 struct snd_ctl_elem_value *ucontrol)
1da177e4 2195{
3d19f804 2196 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2197 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2198 AC97_CSR_ACMODE, 0x200,
2199 ucontrol->value.integer.value[0] ? 0 : 0x200);
2200}
2201
3d19f804 2202static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
1da177e4
LT		 2203 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2204 .name = "Duplicate Front",
2205 .info = snd_mixer_boolean_info,
2206 .get = snd_cs46xx_front_dup_get,
2207 .put = snd_cs46xx_front_dup_put,
2208};
2209#endif
2210
2211#ifdef CONFIG_SND_CS46XX_NEW_DSP
2212/* Only available on the Hercules Game Theater XP soundcard */
f40b6890 2213static struct snd_kcontrol_new snd_hercules_controls[] = {
1da177e4
LT		 2214{
2215 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2216 .name = "Optical/Coaxial SPDIF Input Switch",
2217 .info = snd_mixer_boolean_info,
2218 .get = snd_herc_spdif_select_get,
2219 .put = snd_herc_spdif_select_put,
2220},
2221};
2222
2223
3d19f804 2224static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
1da177e4
LT		 2225{
2226 unsigned long end_time;
2227 int err;
2228
2229 /* reset to defaults */
2230 snd_ac97_write(ac97, AC97_RESET, 0);
2231
2232 /* set the desired CODEC mode */
2233 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2234 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2235 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2236 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2237 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2238 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2239 } else {
2240 snd_assert(0); /* should never happen ... */
2241 }
2242
2243 udelay(50);
2244
2245 /* it's necessary to wait awhile until registers are accessible after RESET */
2246 /* because the PCM or MASTER volume registers can be modified, */
2247 /* the REC_GAIN register is used for tests */
2248 end_time = jiffies + HZ;
2249 do {
2250 unsigned short ext_mid;
2251
2252 /* use preliminary reads to settle the communication */
2253 snd_ac97_read(ac97, AC97_RESET);
2254 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2255 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2256 /* modem? */
2257 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2258 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2259 return;
2260
2261 /* test if we can write to the record gain volume register */
2262 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2263 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2264 return;
2265
ef21ca24 2266 msleep(10);
1da177e4
LT		 2267 } while (time_after_eq(end_time, jiffies));
2268
99b359ba 2269 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
1da177e4
LT		 2270}
2271#endif
2272
3d19f804 2273static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
1da177e4
LT		 2274{
2275 int idx, err;
3d19f804 2276 struct snd_ac97_template ac97;
1da177e4
LT		 2277
2278 memset(&ac97, 0, sizeof(ac97));
2279 ac97.private_data = chip;
2280 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2281 ac97.num = codec;
2282 if (chip->amplifier_ctrl == amp_voyetra)
2283 ac97.scaps = AC97_SCAP_INV_EAPD;
2284
2285 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2286 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2287 udelay(10);
2288 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2289 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2290 return -ENXIO;
2291 }
2292 }
2293
2294 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2295 for (idx = 0; idx < 100; ++idx) {
2296 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2297 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2298 return err;
2299 }
ef21ca24 2300 msleep(10);
1da177e4
LT		 2301 }
2302 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2303 return -ENXIO;
2304}
2305
3d19f804 2306int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
1da177e4 2307{
3d19f804
TI		 2308 struct snd_card *card = chip->card;
2309 struct snd_ctl_elem_id id;
1da177e4
LT		 2310 int err;
2311 unsigned int idx;
3d19f804 2312 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 2313#ifdef CONFIG_SND_CS46XX_NEW_DSP
2314 .reset = snd_cs46xx_codec_reset,
2315#endif
2316 .write = snd_cs46xx_ac97_write,
2317 .read = snd_cs46xx_ac97_read,
2318 };
2319
2320 /* detect primary codec */
2321 chip->nr_ac97_codecs = 0;
2322 snd_printdd("snd_cs46xx: detecting primary codec\n");
2323 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2324 return err;
2325 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2326
2327 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2328 return -ENXIO;
2329 chip->nr_ac97_codecs = 1;
2330
2331#ifdef CONFIG_SND_CS46XX_NEW_DSP
2332 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2333 /* try detect a secondary codec */
2334 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2335 chip->nr_ac97_codecs = 2;
2336#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2337
2338 /* add cs4630 mixer controls */
2339 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
3d19f804 2340 struct snd_kcontrol *kctl;
1da177e4 2341 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
67ed4161
CL		 2342 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2343 kctl->id.device = spdif_device;
1da177e4
LT		 2344 if ((err = snd_ctl_add(card, kctl)) < 0)
2345 return err;
2346 }
2347
2348 /* get EAPD mixer switch (for voyetra hack) */
2349 memset(&id, 0, sizeof(id));
2350 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2351 strcpy(id.name, "External Amplifier");
2352 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2353
2354#ifdef CONFIG_SND_CS46XX_NEW_DSP
2355 if (chip->nr_ac97_codecs == 1) {
2356 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2357 if (id2 == 0x592b || id2 == 0x592d) {
2358 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2359 if (err < 0)
2360 return err;
2361 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2362 AC97_CSR_ACMODE, 0x200);
2363 }
2364 }
2365 /* do soundcard specific mixer setup */
2366 if (chip->mixer_init) {
2367 snd_printdd ("calling chip->mixer_init(chip);\n");
2368 chip->mixer_init(chip);
2369 }
2370#endif
2371
2372 /* turn on amplifier */
2373 chip->amplifier_ctrl(chip, 1);
2374
2375 return 0;
2376}
2377
2378/*
2379 * RawMIDI interface
2380 */
2381
3d19f804 2382static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
1da177e4
LT		 2383{
2384 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2385 udelay(100);
2386 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2387}
2388
3d19f804 2389static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2390{
3d19f804 2391 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2392
2393 chip->active_ctrl(chip, 1);
2394 spin_lock_irq(&chip->reg_lock);
2395 chip->uartm |= CS46XX_MODE_INPUT;
2396 chip->midcr |= MIDCR_RXE;
2397 chip->midi_input = substream;
2398 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2399 snd_cs46xx_midi_reset(chip);
2400 } else {
2401 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2402 }
2403 spin_unlock_irq(&chip->reg_lock);
2404 return 0;
2405}
2406
3d19f804 2407static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2408{
3d19f804 2409 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2410
2411 spin_lock_irq(&chip->reg_lock);
2412 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2413 chip->midi_input = NULL;
2414 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2415 snd_cs46xx_midi_reset(chip);
2416 } else {
2417 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2418 }
2419 chip->uartm &= ~CS46XX_MODE_INPUT;
2420 spin_unlock_irq(&chip->reg_lock);
2421 chip->active_ctrl(chip, -1);
2422 return 0;
2423}
2424
3d19f804 2425static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2426{
3d19f804 2427 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2428
2429 chip->active_ctrl(chip, 1);
2430
2431 spin_lock_irq(&chip->reg_lock);
2432 chip->uartm |= CS46XX_MODE_OUTPUT;
2433 chip->midcr |= MIDCR_TXE;
2434 chip->midi_output = substream;
2435 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2436 snd_cs46xx_midi_reset(chip);
2437 } else {
2438 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2439 }
2440 spin_unlock_irq(&chip->reg_lock);
2441 return 0;
2442}
2443
3d19f804 2444static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2445{
3d19f804 2446 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2447
2448 spin_lock_irq(&chip->reg_lock);
2449 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2450 chip->midi_output = NULL;
2451 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2452 snd_cs46xx_midi_reset(chip);
2453 } else {
2454 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2455 }
2456 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2457 spin_unlock_irq(&chip->reg_lock);
2458 chip->active_ctrl(chip, -1);
2459 return 0;
2460}
2461
3d19f804 2462static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2463{
2464 unsigned long flags;
3d19f804 2465 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2466
2467 spin_lock_irqsave(&chip->reg_lock, flags);
2468 if (up) {
2469 if ((chip->midcr & MIDCR_RIE) == 0) {
2470 chip->midcr |= MIDCR_RIE;
2471 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2472 }
2473 } else {
2474 if (chip->midcr & MIDCR_RIE) {
2475 chip->midcr &= ~MIDCR_RIE;
2476 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2477 }
2478 }
2479 spin_unlock_irqrestore(&chip->reg_lock, flags);
2480}
2481
3d19f804 2482static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2483{
2484 unsigned long flags;
3d19f804 2485 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2486 unsigned char byte;
2487
2488 spin_lock_irqsave(&chip->reg_lock, flags);
2489 if (up) {
2490 if ((chip->midcr & MIDCR_TIE) == 0) {
2491 chip->midcr |= MIDCR_TIE;
2492 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2493 while ((chip->midcr & MIDCR_TIE) &&
2494 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2495 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2496 chip->midcr &= ~MIDCR_TIE;
2497 } else {
2498 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2499 }
2500 }
2501 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2502 }
2503 } else {
2504 if (chip->midcr & MIDCR_TIE) {
2505 chip->midcr &= ~MIDCR_TIE;
2506 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2507 }
2508 }
2509 spin_unlock_irqrestore(&chip->reg_lock, flags);
2510}
2511
3d19f804 2512static struct snd_rawmidi_ops snd_cs46xx_midi_output =
1da177e4
LT		 2513{
2514 .open = snd_cs46xx_midi_output_open,
2515 .close = snd_cs46xx_midi_output_close,
2516 .trigger = snd_cs46xx_midi_output_trigger,
2517};
2518
3d19f804 2519static struct snd_rawmidi_ops snd_cs46xx_midi_input =
1da177e4
LT		 2520{
2521 .open = snd_cs46xx_midi_input_open,
2522 .close = snd_cs46xx_midi_input_close,
2523 .trigger = snd_cs46xx_midi_input_trigger,
2524};
2525
3d19f804 2526int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
1da177e4 2527{
3d19f804 2528 struct snd_rawmidi *rmidi;
1da177e4
LT		 2529 int err;
2530
2531 if (rrawmidi)
2532 *rrawmidi = NULL;
2533 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2534 return err;
2535 strcpy(rmidi->name, "CS46XX");
2536 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2537 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2538 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2539 rmidi->private_data = chip;
2540 chip->rmidi = rmidi;
2541 if (rrawmidi)
2542 *rrawmidi = NULL;
2543 return 0;
2544}
2545
2546
2547/*
2548 * gameport interface
2549 */
2550
2551#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2552
2553static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2554{
3d19f804 2555 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2556
2557 snd_assert(chip, return);
2558 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2559}
2560
2561static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2562{
3d19f804 2563 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2564
2565 snd_assert(chip, return 0);
2566 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2567}
2568
2569static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2570{
3d19f804 2571 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2572 unsigned js1, js2, jst;
2573
2574 snd_assert(chip, return 0);
2575
2576 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2577 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2578 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2579
2580 *buttons = (~jst >> 4) & 0x0F;
2581
2582 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2583 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2584 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2585 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2586
2587 for(jst=0;jst<4;++jst)
2588 if(axes[jst]==0xFFFF) axes[jst] = -1;
2589 return 0;
2590}
2591
2592static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2593{
2594 switch (mode) {
2595 case GAMEPORT_MODE_COOKED:
2596 return 0;
2597 case GAMEPORT_MODE_RAW:
2598 return 0;
2599 default:
2600 return -1;
2601 }
2602 return 0;
2603}
2604
3d19f804 2605int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2606{
2607 struct gameport *gp;
2608
2609 chip->gameport = gp = gameport_allocate_port();
2610 if (!gp) {
2611 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2612 return -ENOMEM;
2613 }
2614
2615 gameport_set_name(gp, "CS46xx Gameport");
2616 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2617 gameport_set_dev_parent(gp, &chip->pci->dev);
2618 gameport_set_port_data(gp, chip);
2619
2620 gp->open = snd_cs46xx_gameport_open;
2621 gp->read = snd_cs46xx_gameport_read;
2622 gp->trigger = snd_cs46xx_gameport_trigger;
2623 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2624
2625 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2626 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2627
2628 gameport_register_port(gp);
2629
2630 return 0;
2631}
2632
3d19f804 2633static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2634{
2635 if (chip->gameport) {
2636 gameport_unregister_port(chip->gameport);
2637 chip->gameport = NULL;
2638 }
2639}
2640#else
3d19f804
TI		 2641int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2642static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
1da177e4
LT		 2643#endif /* CONFIG_GAMEPORT */
2644
adf1b3d2 2645#ifdef CONFIG_PROC_FS
1da177e4
LT		 2646/*
2647 * proc interface
2648 */
2649
3d19f804 2650static long snd_cs46xx_io_read(struct snd_info_entry *entry, void *file_private_data,
1da177e4
LT		 2651 struct file *file, char __user *buf,
2652 unsigned long count, unsigned long pos)
2653{
2654 long size;
3d19f804 2655 struct snd_cs46xx_region *region = entry->private_data;
1da177e4
LT		 2656
2657 size = count;
2658 if (pos + (size_t)size > region->size)
2659 size = region->size - pos;
2660 if (size > 0) {
2661 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2662 return -EFAULT;
2663 }
2664 return size;
2665}
2666
2667static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2668 .read = snd_cs46xx_io_read,
2669};
2670
3d19f804 2671static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
1da177e4 2672{
3d19f804 2673 struct snd_info_entry *entry;
1da177e4
LT		 2674 int idx;
2675
2676 for (idx = 0; idx < 5; idx++) {
3d19f804 2677 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2678 if (! snd_card_proc_new(card, region->name, &entry)) {
2679 entry->content = SNDRV_INFO_CONTENT_DATA;
2680 entry->private_data = chip;
2681 entry->c.ops = &snd_cs46xx_proc_io_ops;
2682 entry->size = region->size;
2683 entry->mode = S_IFREG | S_IRUSR;
2684 }
2685 }
2686#ifdef CONFIG_SND_CS46XX_NEW_DSP
2687 cs46xx_dsp_proc_init(card, chip);
2688#endif
2689 return 0;
2690}
2691
3d19f804 2692static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
1da177e4
LT		 2693{
2694#ifdef CONFIG_SND_CS46XX_NEW_DSP
2695 cs46xx_dsp_proc_done(chip);
2696#endif
2697 return 0;
2698}
adf1b3d2
TI		 2699#else /* !CONFIG_PROC_FS */
2700#define snd_cs46xx_proc_init(card, chip)
2701#define snd_cs46xx_proc_done(chip)
2702#endif
1da177e4
LT		 2703
2704/*
2705 * stop the h/w
2706 */
3d19f804 2707static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
1da177e4
LT		 2708{
2709 unsigned int tmp;
2710
2711 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2712 tmp &= ~0x0000f03f;
2713 tmp |= 0x00000010;
2714 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2715
2716 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2717 tmp &= ~0x0000003f;
2718 tmp |= 0x00000011;
2719 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2720
2721 /*
2722 * Stop playback DMA.
2723 */
2724 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2725 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2726
2727 /*
2728 * Stop capture DMA.
2729 */
2730 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2731 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2732
2733 /*
2734 * Reset the processor.
2735 */
2736 snd_cs46xx_reset(chip);
2737
2738 snd_cs46xx_proc_stop(chip);
2739
2740 /*
2741 * Power down the PLL.
2742 */
2743 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2744
2745 /*
2746 * Turn off the Processor by turning off the software clock enable flag in
2747 * the clock control register.
2748 */
2749 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2750 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2751}
2752
2753
3d19f804 2754static int snd_cs46xx_free(struct snd_cs46xx *chip)
1da177e4
LT		 2755{
2756 int idx;
2757
2758 snd_assert(chip != NULL, return -EINVAL);
2759
2760 if (chip->active_ctrl)
2761 chip->active_ctrl(chip, 1);
2762
2763 snd_cs46xx_remove_gameport(chip);
2764
2765 if (chip->amplifier_ctrl)
2766 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2767
2768 snd_cs46xx_proc_done(chip);
2769
2770 if (chip->region.idx[0].resource)
2771 snd_cs46xx_hw_stop(chip);
2772
0a50d2b2
TI		 2773 if (chip->irq >= 0)
2774 free_irq(chip->irq, chip);
2775
1da177e4 2776 for (idx = 0; idx < 5; idx++) {
3d19f804 2777 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2778 if (region->remap_addr)
2779 iounmap(region->remap_addr);
b1d5776d 2780 release_and_free_resource(region->resource);
1da177e4 2781 }
1da177e4
LT		 2782
2783 if (chip->active_ctrl)
2784 chip->active_ctrl(chip, -chip->amplifier);
2785
2786#ifdef CONFIG_SND_CS46XX_NEW_DSP
2787 if (chip->dsp_spos_instance) {
2788 cs46xx_dsp_spos_destroy(chip);
2789 chip->dsp_spos_instance = NULL;
2790 }
2791#endif
2792
89f157d9
TI		 2793#ifdef CONFIG_PM
2794 kfree(chip->saved_regs);
2795#endif
2796
1da177e4
LT		 2797 pci_disable_device(chip->pci);
2798 kfree(chip);
2799 return 0;
2800}
2801
3d19f804 2802static int snd_cs46xx_dev_free(struct snd_device *device)
1da177e4 2803{
3d19f804 2804 struct snd_cs46xx *chip = device->device_data;
1da177e4
LT		 2805 return snd_cs46xx_free(chip);
2806}
2807
2808/*
2809 * initialize chip
2810 */
3d19f804 2811static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
1da177e4
LT		 2812{
2813 int timeout;
2814
2815 /*
2816 * First, blast the clock control register to zero so that the PLL starts
2817 * out in a known state, and blast the master serial port control register
2818 * to zero so that the serial ports also start out in a known state.
2819 */
2820 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2821 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2822
2823 /*
2824 * If we are in AC97 mode, then we must set the part to a host controlled
2825 * AC-link. Otherwise, we won't be able to bring up the link.
2826 */
2827#ifdef CONFIG_SND_CS46XX_NEW_DSP
2828 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2829 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2830 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2831#else
2832 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2833#endif
2834
2835 /*
2836 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2837 * spec) and then drive it high. This is done for non AC97 modes since
2838 * there might be logic external to the CS461x that uses the ARST# line
2839 * for a reset.
2840 */
2841 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2842#ifdef CONFIG_SND_CS46XX_NEW_DSP
2843 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2844#endif
2845 udelay(50);
2846 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2847#ifdef CONFIG_SND_CS46XX_NEW_DSP
2848 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2849#endif
2850
2851 /*
2852 * The first thing we do here is to enable sync generation. As soon
2853 * as we start receiving bit clock, we'll start producing the SYNC
2854 * signal.
2855 */
2856 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2857#ifdef CONFIG_SND_CS46XX_NEW_DSP
2858 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2859#endif
2860
2861 /*
2862 * Now wait for a short while to allow the AC97 part to start
2863 * generating bit clock (so we don't try to start the PLL without an
2864 * input clock).
2865 */
2866 mdelay(10);
2867
2868 /*
2869 * Set the serial port timing configuration, so that
2870 * the clock control circuit gets its clock from the correct place.
2871 */
2872 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2873
2874 /*
2875 * Write the selected clock control setup to the hardware. Do not turn on
2876 * SWCE yet (if requested), so that the devices clocked by the output of
2877 * PLL are not clocked until the PLL is stable.
2878 */
2879 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2880 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2881 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2882
2883 /*
2884 * Power up the PLL.
2885 */
2886 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2887
2888 /*
2889 * Wait until the PLL has stabilized.
2890 */
ef21ca24 2891 msleep(100);
1da177e4
LT		 2892
2893 /*
2894 * Turn on clocking of the core so that we can setup the serial ports.
2895 */
2896 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2897
2898 /*
2899 * Enable FIFO Host Bypass
2900 */
2901 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2902
2903 /*
2904 * Fill the serial port FIFOs with silence.
2905 */
2906 snd_cs46xx_clear_serial_FIFOs(chip);
2907
2908 /*
2909 * Set the serial port FIFO pointer to the first sample in the FIFO.
2910 */
2911 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
2912
2913 /*
2914 * Write the serial port configuration to the part. The master
2915 * enable bit is not set until all other values have been written.
2916 */
2917 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
2918 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
2919 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
2920
2921
2922#ifdef CONFIG_SND_CS46XX_NEW_DSP
2923 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
2924 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
2925 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
2926 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
2927 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
2928#endif
2929
2930 mdelay(5);
2931
2932
2933 /*
2934 * Wait for the codec ready signal from the AC97 codec.
2935 */
2936 timeout = 150;
2937 while (timeout-- > 0) {
2938 /*
2939 * Read the AC97 status register to see if we've seen a CODEC READY
2940 * signal from the AC97 codec.
2941 */
2942 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
2943 goto ok1;
ef21ca24 2944 msleep(10);
1da177e4
LT		 2945 }
2946
2947
99b359ba
TI		 2948 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
2949 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
1da177e4
LT		 2950 return -EIO;
2951 ok1:
2952#ifdef CONFIG_SND_CS46XX_NEW_DSP
2953 {
2954 int count;
2955 for (count = 0; count < 150; count++) {
2956 /* First, we want to wait for a short time. */
2957 udelay(25);
2958
2959 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
2960 break;
2961 }
2962
2963 /*
2964 * Make sure CODEC is READY.
2965 */
2966 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
2967 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
2968 }
2969#endif
2970
2971 /*
2972 * Assert the vaid frame signal so that we can start sending commands
2973 * to the AC97 codec.
2974 */
2975 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
2976#ifdef CONFIG_SND_CS46XX_NEW_DSP
2977 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
2978#endif
2979
2980
2981 /*
2982 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
2983 * the codec is pumping ADC data across the AC-link.
2984 */
2985 timeout = 150;
2986 while (timeout-- > 0) {
2987 /*
2988 * Read the input slot valid register and see if input slots 3 and
2989 * 4 are valid yet.
2990 */
2991 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
2992 goto ok2;
ef21ca24 2993 msleep(10);
1da177e4
LT		 2994 }
2995
2996#ifndef CONFIG_SND_CS46XX_NEW_DSP
99b359ba 2997 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
1da177e4
LT		 2998 return -EIO;
2999#else
3000 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3001 Reloading the driver may help, if there's other soundcards
3002 with the same problem I would like to know. (Benny) */
3003
99b359ba
TI		 3004 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3005 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n");
3006 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n");
4505179c 3007 snd_printk(KERN_ERR " this message please report to alsa-devel@alsa-project.org\n");
1da177e4
LT		 3008
3009 return -EIO;
3010#endif
3011 ok2:
3012
3013 /*
3014 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3015 * commense the transfer of digital audio data to the AC97 codec.
3016 */
3017
3018 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3019
3020
3021 /*
3022 * Power down the DAC and ADC. We will power them up (if) when we need
3023 * them.
3024 */
3025 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3026
3027 /*
3028 * Turn off the Processor by turning off the software clock enable flag in
3029 * the clock control register.
3030 */
3031 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3032 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3033
3034 return 0;
3035}
3036
3037/*
3038 * start and load DSP
3039 */
89f157d9
TI		 3040
3041static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3042{
3043 unsigned int tmp;
3044
3045 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3046
3047 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3048 tmp &= ~0x0000f03f;
3049 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3050
3051 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3052 tmp &= ~0x0000003f;
3053 tmp |= 0x00000001;
3054 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3055}
3056
3d19f804 3057int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
1da177e4
LT		 3058{
3059 unsigned int tmp;
3060 /*
3061 * Reset the processor.
3062 */
3063 snd_cs46xx_reset(chip);
3064 /*
3065 * Download the image to the processor.
3066 */
3067#ifdef CONFIG_SND_CS46XX_NEW_DSP
3068#if 0
3069 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3070 snd_printk(KERN_ERR "image download error\n");
3071 return -EIO;
3072 }
3073#endif
3074
3075 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3076 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3077 return -EIO;
3078 }
3079
3080 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3081 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3082 return -EIO;
3083 }
3084
3085 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3086 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3087 return -EIO;
3088 }
3089
3090 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3091 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3092 return -EIO;
3093 }
3094
3095 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3096 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3097 return -EIO;
3098 }
3099
3100 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3101 return -EIO;
3102#else
3103 /* old image */
3104 if (snd_cs46xx_download_image(chip) < 0) {
99b359ba 3105 snd_printk(KERN_ERR "image download error\n");
1da177e4
LT		 3106 return -EIO;
3107 }
3108
3109 /*
3110 * Stop playback DMA.
3111 */
3112 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3113 chip->play_ctl = tmp & 0xffff0000;
3114 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3115#endif
3116
3117 /*
3118 * Stop capture DMA.
3119 */
3120 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3121 chip->capt.ctl = tmp & 0x0000ffff;
3122 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3123
3124 mdelay(5);
3125
3126 snd_cs46xx_set_play_sample_rate(chip, 8000);
3127 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3128
3129 snd_cs46xx_proc_start(chip);
3130
89f157d9 3131 cs46xx_enable_stream_irqs(chip);
1da177e4
LT		 3132
3133#ifndef CONFIG_SND_CS46XX_NEW_DSP
3134 /* set the attenuation to 0dB */
3135 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3136 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3137#endif
3138
3139 return 0;
3140}
3141
3142
3143/*
3144 * AMP control - null AMP
3145 */
3146
3d19f804 3147static void amp_none(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3148{
3149}
3150
3151#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 3152static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
1da177e4
LT		 3153{
3154
3155 u32 idx, valid_slots,tmp,powerdown = 0;
3156 u16 modem_power,pin_config,logic_type;
3157
3158 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3159
3160 /*
3161 * See if the devices are powered down. If so, we must power them up first
3162 * or they will not respond.
3163 */
3164 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3165
3166 if (!(tmp & CLKCR1_SWCE)) {
3167 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3168 powerdown = 1;
3169 }
3170
3171 /*
3172 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3173 * stuff.
3174 */
3175 if(chip->nr_ac97_codecs != 2) {
3176 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3177 return -EINVAL;
3178 }
3179
3180 modem_power = snd_cs46xx_codec_read (chip,
3181 AC97_EXTENDED_MSTATUS,
3182 CS46XX_SECONDARY_CODEC_INDEX);
3183 modem_power &=0xFEFF;
3184
3185 snd_cs46xx_codec_write(chip,
3186 AC97_EXTENDED_MSTATUS, modem_power,
3187 CS46XX_SECONDARY_CODEC_INDEX);
3188
3189 /*
3190 * Set GPIO pin's 7 and 8 so that they are configured for output.
3191 */
3192 pin_config = snd_cs46xx_codec_read (chip,
3193 AC97_GPIO_CFG,
3194 CS46XX_SECONDARY_CODEC_INDEX);
3195 pin_config &=0x27F;
3196
3197 snd_cs46xx_codec_write(chip,
3198 AC97_GPIO_CFG, pin_config,
3199 CS46XX_SECONDARY_CODEC_INDEX);
3200
3201 /*
3202 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3203 */
3204
3205 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3206 CS46XX_SECONDARY_CODEC_INDEX);
3207 logic_type &=0x27F;
3208
3209 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3210 CS46XX_SECONDARY_CODEC_INDEX);
3211
3212 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3213 valid_slots |= 0x200;
3214 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3215
3216 if ( cs46xx_wait_for_fifo(chip,1) ) {
3217 snd_printdd("FIFO is busy\n");
3218
3219 return -EINVAL;
3220 }
3221
3222 /*
3223 * Fill slots 12 with the correct value for the GPIO pins.
3224 */
3225 for(idx = 0x90; idx <= 0x9F; idx++) {
3226 /*
3227 * Initialize the fifo so that bits 7 and 8 are on.
3228 *
3229 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3230 * the left. 0x1800 corresponds to bits 7 and 8.
3231 */
3232 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3233
3234 /*
3235 * Wait for command to complete
3236 */
3237 if ( cs46xx_wait_for_fifo(chip,200) ) {
3238 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3239
3240 return -EINVAL;
3241 }
3242
3243 /*
3244 * Write the serial port FIFO index.
3245 */
3246 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3247
3248 /*
3249 * Tell the serial port to load the new value into the FIFO location.
3250 */
3251 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3252 }
3253
3254 /* wait for last command to complete */
3255 cs46xx_wait_for_fifo(chip,200);
3256
3257 /*
3258 * Now, if we powered up the devices, then power them back down again.
3259 * This is kinda ugly, but should never happen.
3260 */
3261 if (powerdown)
3262 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3263
3264 return 0;
3265}
3266#endif
3267
3268/*
3269 * Crystal EAPD mode
3270 */
3271
3d19f804 3272static void amp_voyetra(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3273{
3274 /* Manage the EAPD bit on the Crystal 4297
3275 and the Analog AD1885 */
3276
3277#ifdef CONFIG_SND_CS46XX_NEW_DSP
3278 int old = chip->amplifier;
3279#endif
3280 int oval, val;
3281
3282 chip->amplifier += change;
3283 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3284 CS46XX_PRIMARY_CODEC_INDEX);
3285 val = oval;
3286 if (chip->amplifier) {
3287 /* Turn the EAPD amp on */
3288 val |= 0x8000;
3289 } else {
3290 /* Turn the EAPD amp off */
3291 val &= ~0x8000;
3292 }
3293 if (val != oval) {
3294 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3295 CS46XX_PRIMARY_CODEC_INDEX);
3296 if (chip->eapd_switch)
3297 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3298 &chip->eapd_switch->id);
3299 }
3300
3301#ifdef CONFIG_SND_CS46XX_NEW_DSP
3302 if (chip->amplifier && !old) {
3303 voyetra_setup_eapd_slot(chip);
3304 }
3305#endif
3306}
3307
3d19f804 3308static void hercules_init(struct snd_cs46xx *chip)
1da177e4
LT		 3309{
3310 /* default: AMP off, and SPDIF input optical */
3311 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3312 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3313}
3314
3315
3316/*
3317 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3318 */
3d19f804 3319static void amp_hercules(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3320{
3321 int old = chip->amplifier;
3322 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3323 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3324
3325 chip->amplifier += change;
3326 if (chip->amplifier && !old) {
3327 snd_printdd ("Hercules amplifier ON\n");
3328
3329 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3330 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3331 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3332 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3333 } else if (old && !chip->amplifier) {
3334 snd_printdd ("Hercules amplifier OFF\n");
3335 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3336 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3337 }
3338}
3339
3d19f804 3340static void voyetra_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3341{
3342 snd_printdd ("initializing Voyetra mixer\n");
3343
3344 /* Enable SPDIF out */
3345 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3346 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3347}
3348
3d19f804 3349static void hercules_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3350{
3351#ifdef CONFIG_SND_CS46XX_NEW_DSP
3352 unsigned int idx;
3353 int err;
3d19f804 3354 struct snd_card *card = chip->card;
1da177e4
LT		 3355#endif
3356
3357 /* set EGPIO to default */
3358 hercules_init(chip);
3359
3360 snd_printdd ("initializing Hercules mixer\n");
3361
3362#ifdef CONFIG_SND_CS46XX_NEW_DSP
f40b6890
TI		 3363 if (chip->in_suspend)
3364 return;
3365
1da177e4 3366 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3d19f804 3367 struct snd_kcontrol *kctl;
1da177e4
LT		 3368
3369 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3370 if ((err = snd_ctl_add(card, kctl)) < 0) {
3371 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3372 break;
3373 }
3374 }
3375#endif
3376}
3377
3378
3379#if 0
3380/*
3381 * Untested
3382 */
3383
3d19f804 3384static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3385{
3386 chip->amplifier += change;
3387
3388 if (chip->amplifier) {
3389 /* Switch the GPIO pins 7 and 8 to open drain */
3390 snd_cs46xx_codec_write(chip, 0x4C,
3391 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3392 snd_cs46xx_codec_write(chip, 0x4E,
3393 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3394 /* Now wake the AMP (this might be backwards) */
3395 snd_cs46xx_codec_write(chip, 0x54,
3396 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3397 } else {
3398 snd_cs46xx_codec_write(chip, 0x54,
3399 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3400 }
3401}
3402#endif
3403
3404
1da177e4
LT		 3405/*
3406 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3407 * whenever we need to beat on the chip.
3408 *
3409 * The original idea and code for this hack comes from David Kaiser at
3410 * Linuxcare. Perhaps one day Crystal will document their chips well
3411 * enough to make them useful.
3412 */
3413
3d19f804 3414static void clkrun_hack(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3415{
3416 u16 control, nval;
3417
0dd119f7 3418 if (!chip->acpi_port)
1da177e4
LT		 3419 return;
3420
3421 chip->amplifier += change;
3422
3423 /* Read ACPI port */
3424 nval = control = inw(chip->acpi_port + 0x10);
3425
3426 /* Flip CLKRUN off while running */
3427 if (! chip->amplifier)
3428 nval |= 0x2000;
3429 else
3430 nval &= ~0x2000;
3431 if (nval != control)
3432 outw(nval, chip->acpi_port + 0x10);
3433}
3434
3435
3436/*
3437 * detect intel piix4
3438 */
3d19f804 3439static void clkrun_init(struct snd_cs46xx *chip)
1da177e4 3440{
0dd119f7 3441 struct pci_dev *pdev;
1da177e4
LT		 3442 u8 pp;
3443
0dd119f7
JS		 3444 chip->acpi_port = 0;
3445
3446 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3447 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3448 if (pdev == NULL)
1da177e4
LT		 3449 return; /* Not a thinkpad thats for sure */
3450
3451 /* Find the control port */
0dd119f7 3452 pci_read_config_byte(pdev, 0x41, &pp);
1da177e4 3453 chip->acpi_port = pp << 8;
0dd119f7 3454 pci_dev_put(pdev);
1da177e4
LT		 3455}
3456
3457
3458/*
3459 * Card subid table
3460 */
3461
3462struct cs_card_type
3463{
3464 u16 vendor;
3465 u16 id;
3466 char *name;
3d19f804
TI		 3467 void (*init)(struct snd_cs46xx *);
3468 void (*amp)(struct snd_cs46xx *, int);
3469 void (*active)(struct snd_cs46xx *, int);
3470 void (*mixer_init)(struct snd_cs46xx *);
1da177e4
LT		 3471};
3472
3473static struct cs_card_type __devinitdata cards[] = {
3474 {
3475 .vendor = 0x1489,
3476 .id = 0x7001,
3477 .name = "Genius Soundmaker 128 value",
3478 /* nothing special */
3479 },
3480 {
3481 .vendor = 0x5053,
3482 .id = 0x3357,
3483 .name = "Voyetra",
3484 .amp = amp_voyetra,
3485 .mixer_init = voyetra_mixer_init,
3486 },
3487 {
3488 .vendor = 0x1071,
3489 .id = 0x6003,
3490 .name = "Mitac MI6020/21",
3491 .amp = amp_voyetra,
3492 },
3493 {
3494 .vendor = 0x14AF,
3495 .id = 0x0050,
3496 .name = "Hercules Game Theatre XP",
3497 .amp = amp_hercules,
3498 .mixer_init = hercules_mixer_init,
3499 },
3500 {
3501 .vendor = 0x1681,
3502 .id = 0x0050,
3503 .name = "Hercules Game Theatre XP",
3504 .amp = amp_hercules,
3505 .mixer_init = hercules_mixer_init,
3506 },
3507 {
3508 .vendor = 0x1681,
3509 .id = 0x0051,
3510 .name = "Hercules Game Theatre XP",
3511 .amp = amp_hercules,
3512 .mixer_init = hercules_mixer_init,
3513
3514 },
3515 {
3516 .vendor = 0x1681,
3517 .id = 0x0052,
3518 .name = "Hercules Game Theatre XP",
3519 .amp = amp_hercules,
3520 .mixer_init = hercules_mixer_init,
3521 },
3522 {
3523 .vendor = 0x1681,
3524 .id = 0x0053,
3525 .name = "Hercules Game Theatre XP",
3526 .amp = amp_hercules,
3527 .mixer_init = hercules_mixer_init,
3528 },
3529 {
3530 .vendor = 0x1681,
3531 .id = 0x0054,
3532 .name = "Hercules Game Theatre XP",
3533 .amp = amp_hercules,
3534 .mixer_init = hercules_mixer_init,
3535 },
3536 /* Teratec */
3537 {
3538 .vendor = 0x153b,
3539 .id = 0x1136,
3540 .name = "Terratec SiXPack 5.1",
3541 },
3542 /* Not sure if the 570 needs the clkrun hack */
3543 {
3544 .vendor = PCI_VENDOR_ID_IBM,
3545 .id = 0x0132,
3546 .name = "Thinkpad 570",
3547 .init = clkrun_init,
3548 .active = clkrun_hack,
3549 },
3550 {
3551 .vendor = PCI_VENDOR_ID_IBM,
3552 .id = 0x0153,
3553 .name = "Thinkpad 600X/A20/T20",
3554 .init = clkrun_init,
3555 .active = clkrun_hack,
3556 },
3557 {
3558 .vendor = PCI_VENDOR_ID_IBM,
3559 .id = 0x1010,
3560 .name = "Thinkpad 600E (unsupported)",
3561 },
3562 {} /* terminator */
3563};
3564
3565
3566/*
3567 * APM support
3568 */
3569#ifdef CONFIG_PM
89f157d9
TI		 3570static unsigned int saved_regs[] = {
3571 BA0_ACOSV,
3572 BA0_ASER_FADDR,
3573 BA0_ASER_MASTER,
3574 BA1_PVOL,
3575 BA1_CVOL,
3576};
3577
cb28e45b 3578int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 3579{
cb28e45b
TI		 3580 struct snd_card *card = pci_get_drvdata(pci);
3581 struct snd_cs46xx *chip = card->private_data;
89f157d9 3582 int i, amp_saved;
1da177e4 3583
cb28e45b 3584 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f40b6890 3585 chip->in_suspend = 1;
1da177e4
LT		 3586 snd_pcm_suspend_all(chip->pcm);
3587 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3588 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3589
3590 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3591 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3592
89f157d9
TI		 3593 /* save some registers */
3594 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3595 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3596
1da177e4
LT		 3597 amp_saved = chip->amplifier;
3598 /* turn off amp */
3599 chip->amplifier_ctrl(chip, -chip->amplifier);
3600 snd_cs46xx_hw_stop(chip);
3601 /* disable CLKRUN */
3602 chip->active_ctrl(chip, -chip->amplifier);
3603 chip->amplifier = amp_saved; /* restore the status */
30b35399 3604
cb28e45b
TI		 3605 pci_disable_device(pci);
3606 pci_save_state(pci);
30b35399 3607 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 3608 return 0;
3609}
3610
cb28e45b 3611int snd_cs46xx_resume(struct pci_dev *pci)
1da177e4 3612{
cb28e45b
TI		 3613 struct snd_card *card = pci_get_drvdata(pci);
3614 struct snd_cs46xx *chip = card->private_data;
89f157d9 3615 int i, amp_saved;
1da177e4 3616
30b35399 3617 pci_set_power_state(pci, PCI_D0);
cb28e45b 3618 pci_restore_state(pci);
30b35399
TI		 3619 if (pci_enable_device(pci) < 0) {
3620 printk(KERN_ERR "cs46xx: pci_enable_device failed, "
3621 "disabling device\n");
3622 snd_card_disconnect(card);
3623 return -EIO;
3624 }
cb28e45b 3625 pci_set_master(pci);
30b35399 3626
1da177e4
LT		 3627 amp_saved = chip->amplifier;
3628 chip->amplifier = 0;
3629 chip->active_ctrl(chip, 1); /* force to on */
3630
3631 snd_cs46xx_chip_init(chip);
3632
89f157d9
TI		 3633 snd_cs46xx_reset(chip);
3634#ifdef CONFIG_SND_CS46XX_NEW_DSP
3635 cs46xx_dsp_resume(chip);
3636 /* restore some registers */
3637 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3638 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3639#else
3640 snd_cs46xx_download_image(chip);
3641#endif
3642
1da177e4
LT		 3643#if 0
3644 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3645 chip->ac97_general_purpose);
3646 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3647 chip->ac97_powerdown);
3648 mdelay(10);
3649 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3650 chip->ac97_powerdown);
3651 mdelay(5);
3652#endif
3653
3654 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3655 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3656
89f157d9
TI		 3657 /* reset playback/capture */
3658 snd_cs46xx_set_play_sample_rate(chip, 8000);
3659 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3660 snd_cs46xx_proc_start(chip);
3661
3662 cs46xx_enable_stream_irqs(chip);
3663
1da177e4
LT		 3664 if (amp_saved)
3665 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3666 else
3667 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3668 chip->amplifier = amp_saved;
f40b6890 3669 chip->in_suspend = 0;
cb28e45b 3670 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 3671 return 0;
3672}
3673#endif /* CONFIG_PM */
3674
3675
3676/*
3677 */
3678
3d19f804 3679int __devinit snd_cs46xx_create(struct snd_card *card,
1da177e4
LT		 3680 struct pci_dev * pci,
3681 int external_amp, int thinkpad,
3d19f804 3682 struct snd_cs46xx ** rchip)
1da177e4 3683{
3d19f804 3684 struct snd_cs46xx *chip;
1da177e4 3685 int err, idx;
3d19f804 3686 struct snd_cs46xx_region *region;
1da177e4
LT		 3687 struct cs_card_type *cp;
3688 u16 ss_card, ss_vendor;
3d19f804 3689 static struct snd_device_ops ops = {
1da177e4
LT		 3690 .dev_free = snd_cs46xx_dev_free,
3691 };
3692
3693 *rchip = NULL;
3694
3695 /* enable PCI device */
3696 if ((err = pci_enable_device(pci)) < 0)
3697 return err;
3698
e560d8d8 3699 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 3700 if (chip == NULL) {
3701 pci_disable_device(pci);
3702 return -ENOMEM;
3703 }
3704 spin_lock_init(&chip->reg_lock);
3705#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 3706 mutex_init(&chip->spos_mutex);
1da177e4
LT		 3707#endif
3708 chip->card = card;
3709 chip->pci = pci;
3710 chip->irq = -1;
3711 chip->ba0_addr = pci_resource_start(pci, 0);
3712 chip->ba1_addr = pci_resource_start(pci, 1);
3713 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3714 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3d19f804
TI		 3715 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3716 chip->ba0_addr, chip->ba1_addr);
1da177e4
LT		 3717 snd_cs46xx_free(chip);
3718 return -ENOMEM;
3719 }
3720
3721 region = &chip->region.name.ba0;
3722 strcpy(region->name, "CS46xx_BA0");
3723 region->base = chip->ba0_addr;
3724 region->size = CS46XX_BA0_SIZE;
3725
3726 region = &chip->region.name.data0;
3727 strcpy(region->name, "CS46xx_BA1_data0");
3728 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3729 region->size = CS46XX_BA1_DATA0_SIZE;
3730
3731 region = &chip->region.name.data1;
3732 strcpy(region->name, "CS46xx_BA1_data1");
3733 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3734 region->size = CS46XX_BA1_DATA1_SIZE;
3735
3736 region = &chip->region.name.pmem;
3737 strcpy(region->name, "CS46xx_BA1_pmem");
3738 region->base = chip->ba1_addr + BA1_SP_PMEM;
3739 region->size = CS46XX_BA1_PRG_SIZE;
3740
3741 region = &chip->region.name.reg;
3742 strcpy(region->name, "CS46xx_BA1_reg");
3743 region->base = chip->ba1_addr + BA1_SP_REG;
3744 region->size = CS46XX_BA1_REG_SIZE;
3745
3746 /* set up amp and clkrun hack */
3747 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3748 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3749
3750 for (cp = &cards[0]; cp->name; cp++) {
3751 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3752 snd_printdd ("hack for %s enabled\n", cp->name);
3753
3754 chip->amplifier_ctrl = cp->amp;
3755 chip->active_ctrl = cp->active;
3756 chip->mixer_init = cp->mixer_init;
3757
3758 if (cp->init)
3759 cp->init(chip);
3760 break;
3761 }
3762 }
3763
3764 if (external_amp) {
99b359ba 3765 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
1da177e4
LT		 3766 chip->amplifier_ctrl = amp_voyetra;
3767 }
3768
3769 if (thinkpad) {
99b359ba 3770 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
1da177e4
LT		 3771 chip->active_ctrl = clkrun_hack;
3772 clkrun_init(chip);
3773 }
3774
3775 if (chip->amplifier_ctrl == NULL)
3776 chip->amplifier_ctrl = amp_none;
3777 if (chip->active_ctrl == NULL)
3778 chip->active_ctrl = amp_none;
3779
3780 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3781
3782 pci_set_master(pci);
3783
3784 for (idx = 0; idx < 5; idx++) {
3785 region = &chip->region.idx[idx];
3d19f804
TI		 3786 if ((region->resource = request_mem_region(region->base, region->size,
3787 region->name)) == NULL) {
3788 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
3789 region->base, region->base + region->size - 1);
1da177e4
LT		 3790 snd_cs46xx_free(chip);
3791 return -EBUSY;
3792 }
3793 region->remap_addr = ioremap_nocache(region->base, region->size);
3794 if (region->remap_addr == NULL) {
99b359ba 3795 snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
1da177e4
LT		 3796 snd_cs46xx_free(chip);
3797 return -ENOMEM;
3798 }
3799 }
3800
437a5a46 3801 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3d19f804 3802 "CS46XX", chip)) {
99b359ba 3803 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 3804 snd_cs46xx_free(chip);
3805 return -EBUSY;
3806 }
3807 chip->irq = pci->irq;
3808
3809#ifdef CONFIG_SND_CS46XX_NEW_DSP
3810 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3811 if (chip->dsp_spos_instance == NULL) {
3812 snd_cs46xx_free(chip);
3813 return -ENOMEM;
3814 }
3815#endif
3816
3817 err = snd_cs46xx_chip_init(chip);
3818 if (err < 0) {
3819 snd_cs46xx_free(chip);
3820 return err;
3821 }
3822
3823 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3824 snd_cs46xx_free(chip);
3825 return err;
3826 }
3827
3828 snd_cs46xx_proc_init(card, chip);
3829
89f157d9
TI		 3830#ifdef CONFIG_PM
3831 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) *
3832 ARRAY_SIZE(saved_regs), GFP_KERNEL);
3833 if (!chip->saved_regs) {
3834 snd_cs46xx_free(chip);
3835 return -ENOMEM;
3836 }
3837#endif
3838
1da177e4
LT		 3839 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3840
3841 snd_card_set_dev(card, &pci->dev);
3842
3843 *rchip = chip;
3844 return 0;
3845}
Linux kernel - Deliverables
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