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ALSA: Deletion of checks before the function call "iounmap"
[deliverable/linux.git] / sound / pci / cs46xx / cs46xx_lib.c
CommitLineData
1da177e4 1/*
c1017a4c 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 3 * Abramo Bagnara <abramo@alsa-project.org>
4 * Cirrus Logic, Inc.
5 * Routines for control of Cirrus Logic CS461x chips
6 *
7 * KNOWN BUGS:
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
561de31a 11 * the SPDIF input mixer control.
1da177e4
LT		 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
14 *
15 * TODO:
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
20 *
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
24 *
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 *
46 */
47
1da177e4
LT		 48#include <linux/delay.h>
49#include <linux/pci.h>
50#include <linux/pm.h>
51#include <linux/init.h>
52#include <linux/interrupt.h>
53#include <linux/slab.h>
54#include <linux/gameport.h>
62932df8 55#include <linux/mutex.h>
d81a6d71 56#include <linux/export.h>
ad233a5f
TI		 57#include <linux/module.h>
58#include <linux/firmware.h>
59#include <linux/vmalloc.h>
1da177e4
LT		 60
61#include <sound/core.h>
62#include <sound/control.h>
63#include <sound/info.h>
64#include <sound/pcm.h>
65#include <sound/pcm_params.h>
81fcb170 66#include "cs46xx.h"
1da177e4
LT		 67
68#include <asm/io.h>
69
70#include "cs46xx_lib.h"
71#include "dsp_spos.h"
72
3d19f804 73static void amp_voyetra(struct snd_cs46xx *chip, int change);
1da177e4
LT		 74
75#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804
TI		 76static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
77static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
78static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
79static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
80static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
81static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
1da177e4
LT		 82#endif
83
3d19f804
TI		 84static struct snd_pcm_ops snd_cs46xx_playback_ops;
85static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
86static struct snd_pcm_ops snd_cs46xx_capture_ops;
87static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
1da177e4 88
3d19f804 89static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
1da177e4
LT		 90 unsigned short reg,
91 int codec_index)
92{
93 int count;
94 unsigned short result,tmp;
95 u32 offset = 0;
da3cec35
TI		 96
97 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
98 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
de64c0ee 99 return 0xffff;
1da177e4
LT		 100
101 chip->active_ctrl(chip, 1);
102
103 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
104 offset = CS46XX_SECONDARY_CODEC_OFFSET;
105
106 /*
107 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
108 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
109 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
110 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
111 * 5. if DCV not cleared, break and return error
112 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
113 */
114
115 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
116
117 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
118 if ((tmp & ACCTL_VFRM) == 0) {
2b96a7f1 119 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
1da177e4
LT		 120 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
121 msleep(50);
122 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
123 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
124
125 }
126
127 /*
128 * Setup the AC97 control registers on the CS461x to send the
129 * appropriate command to the AC97 to perform the read.
130 * ACCAD = Command Address Register = 46Ch
131 * ACCDA = Command Data Register = 470h
132 * ACCTL = Control Register = 460h
133 * set DCV - will clear when process completed
134 * set CRW - Read command
135 * set VFRM - valid frame enabled
136 * set ESYN - ASYNC generation enabled
137 * set RSTN - ARST# inactive, AC97 codec not reset
138 */
139
140 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
141 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
142 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
143 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
144 ACCTL_VFRM | ACCTL_ESYN |
145 ACCTL_RSTN);
146 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
147 ACCTL_VFRM | ACCTL_ESYN |
148 ACCTL_RSTN);
149 } else {
150 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
151 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
152 ACCTL_RSTN);
153 }
154
155 /*
156 * Wait for the read to occur.
157 */
158 for (count = 0; count < 1000; count++) {
159 /*
160 * First, we want to wait for a short time.
161 */
162 udelay(10);
163 /*
164 * Now, check to see if the read has completed.
165 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
166 */
167 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
168 goto ok1;
169 }
170
2b96a7f1
TI		 171 dev_err(chip->card->dev,
172 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
1da177e4
LT		 173 result = 0xffff;
174 goto end;
175
176 ok1:
177 /*
178 * Wait for the valid status bit to go active.
179 */
180 for (count = 0; count < 100; count++) {
181 /*
182 * Read the AC97 status register.
183 * ACSTS = Status Register = 464h
184 * VSTS - Valid Status
185 */
186 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
187 goto ok2;
188 udelay(10);
189 }
190
2b96a7f1
TI		 191 dev_err(chip->card->dev,
192 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
193 codec_index, reg);
1da177e4
LT		 194 result = 0xffff;
195 goto end;
196
197 ok2:
198 /*
199 * Read the data returned from the AC97 register.
200 * ACSDA = Status Data Register = 474h
201 */
202#if 0
2b96a7f1
TI		 203 dev_dbg(chip->card->dev,
204 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
1da177e4
LT		 205 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
206 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
207#endif
208
209 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
210 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
211 end:
212 chip->active_ctrl(chip, -1);
213 return result;
214}
215
3d19f804 216static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
1da177e4
LT		 217 unsigned short reg)
218{
3d19f804 219 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 220 unsigned short val;
221 int codec_index = ac97->num;
222
da3cec35
TI		 223 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
224 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
225 return 0xffff;
1da177e4
LT		 226
227 val = snd_cs46xx_codec_read(chip, reg, codec_index);
228
229 return val;
230}
231
232
3d19f804 233static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
1da177e4
LT		 234 unsigned short reg,
235 unsigned short val,
236 int codec_index)
237{
238 int count;
239
da3cec35
TI		 240 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
241 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
242 return;
1da177e4
LT		 243
244 chip->active_ctrl(chip, 1);
245
246 /*
247 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
248 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
249 * 3. Write ACCTL = Control Register = 460h for initiating the write
250 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
251 * 5. if DCV not cleared, break and return error
252 */
253
254 /*
255 * Setup the AC97 control registers on the CS461x to send the
256 * appropriate command to the AC97 to perform the read.
257 * ACCAD = Command Address Register = 46Ch
258 * ACCDA = Command Data Register = 470h
259 * ACCTL = Control Register = 460h
260 * set DCV - will clear when process completed
261 * reset CRW - Write command
262 * set VFRM - valid frame enabled
263 * set ESYN - ASYNC generation enabled
264 * set RSTN - ARST# inactive, AC97 codec not reset
265 */
266 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
267 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
268 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
269
270 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
271 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
272 ACCTL_ESYN | ACCTL_RSTN);
273 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
274 ACCTL_ESYN | ACCTL_RSTN);
275 } else {
276 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
277 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
278 }
279
280 for (count = 0; count < 4000; count++) {
281 /*
282 * First, we want to wait for a short time.
283 */
284 udelay(10);
285 /*
286 * Now, check to see if the write has completed.
287 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
288 */
289 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
290 goto end;
291 }
292 }
2b96a7f1
TI		 293 dev_err(chip->card->dev,
294 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
295 codec_index, reg, val);
1da177e4
LT		 296 end:
297 chip->active_ctrl(chip, -1);
298}
299
3d19f804 300static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 301 unsigned short reg,
302 unsigned short val)
303{
3d19f804 304 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 305 int codec_index = ac97->num;
306
da3cec35
TI		 307 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
308 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
309 return;
1da177e4
LT		 310
311 snd_cs46xx_codec_write(chip, reg, val, codec_index);
312}
313
314
315/*
316 * Chip initialization
317 */
318
3d19f804 319int snd_cs46xx_download(struct snd_cs46xx *chip,
1da177e4
LT		 320 u32 *src,
321 unsigned long offset,
322 unsigned long len)
323{
324 void __iomem *dst;
325 unsigned int bank = offset >> 16;
326 offset = offset & 0xffff;
327
da3cec35
TI		 328 if (snd_BUG_ON((offset & 3) || (len & 3)))
329 return -EINVAL;
1da177e4
LT		 330 dst = chip->region.idx[bank+1].remap_addr + offset;
331 len /= sizeof(u32);
332
333 /* writel already converts 32-bit value to right endianess */
334 while (len-- > 0) {
335 writel(*src++, dst);
336 dst += sizeof(u32);
337 }
338 return 0;
339}
340
ad233a5f
TI		 341static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
342{
343#ifdef __LITTLE_ENDIAN
344 memcpy(dst, src, len);
345#else
346 u32 *_dst = dst;
347 const __le32 *_src = src;
348 len /= 4;
349 while (len-- > 0)
350 *_dst++ = le32_to_cpu(*_src++);
351#endif
352}
353
1da177e4
LT		 354#ifdef CONFIG_SND_CS46XX_NEW_DSP
355
ad233a5f
TI		 356static const char *module_names[CS46XX_DSP_MODULES] = {
357 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
358};
359
360MODULE_FIRMWARE("cs46xx/cwc4630");
361MODULE_FIRMWARE("cs46xx/cwcasync");
362MODULE_FIRMWARE("cs46xx/cwcsnoop");
363MODULE_FIRMWARE("cs46xx/cwcbinhack");
364MODULE_FIRMWARE("cs46xx/cwcdma");
365
366static void free_module_desc(struct dsp_module_desc *module)
367{
368 if (!module)
369 return;
370 kfree(module->module_name);
371 kfree(module->symbol_table.symbols);
372 if (module->segments) {
373 int i;
374 for (i = 0; i < module->nsegments; i++)
375 kfree(module->segments[i].data);
376 kfree(module->segments);
377 }
b75b1518 378 kfree(module);
ad233a5f
TI		 379}
380
381/* firmware binary format:
382 * le32 nsymbols;
383 * struct {
384 * le32 address;
385 * char symbol_name[DSP_MAX_SYMBOL_NAME];
386 * le32 symbol_type;
387 * } symbols[nsymbols];
388 * le32 nsegments;
389 * struct {
390 * le32 segment_type;
391 * le32 offset;
392 * le32 size;
393 * le32 data[size];
394 * } segments[nsegments];
395 */
396
397static int load_firmware(struct snd_cs46xx *chip,
398 struct dsp_module_desc **module_ret,
399 const char *fw_name)
400{
401 int i, err;
402 unsigned int nums, fwlen, fwsize;
403 const __le32 *fwdat;
404 struct dsp_module_desc *module = NULL;
405 const struct firmware *fw;
406 char fw_path[32];
407
408 sprintf(fw_path, "cs46xx/%s", fw_name);
409 err = request_firmware(&fw, fw_path, &chip->pci->dev);
410 if (err < 0)
411 return err;
412 fwsize = fw->size / 4;
413 if (fwsize < 2) {
414 err = -EINVAL;
415 goto error;
416 }
417
418 err = -ENOMEM;
419 module = kzalloc(sizeof(*module), GFP_KERNEL);
420 if (!module)
421 goto error;
422 module->module_name = kstrdup(fw_name, GFP_KERNEL);
423 if (!module->module_name)
424 goto error;
425
426 fwlen = 0;
427 fwdat = (const __le32 *)fw->data;
428 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
429 if (nums >= 40)
430 goto error_inval;
431 module->symbol_table.symbols =
432 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
433 if (!module->symbol_table.symbols)
434 goto error;
435 for (i = 0; i < nums; i++) {
436 struct dsp_symbol_entry *entry =
437 &module->symbol_table.symbols[i];
438 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
439 goto error_inval;
440 entry->address = le32_to_cpu(fwdat[fwlen++]);
441 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
442 fwlen += DSP_MAX_SYMBOL_NAME / 4;
443 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
444 }
445
446 if (fwlen >= fwsize)
447 goto error_inval;
448 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
449 if (nums > 10)
450 goto error_inval;
451 module->segments =
452 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
453 if (!module->segments)
454 goto error;
455 for (i = 0; i < nums; i++) {
456 struct dsp_segment_desc *entry = &module->segments[i];
457 if (fwlen + 3 > fwsize)
458 goto error_inval;
459 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
460 entry->offset = le32_to_cpu(fwdat[fwlen++]);
461 entry->size = le32_to_cpu(fwdat[fwlen++]);
462 if (fwlen + entry->size > fwsize)
463 goto error_inval;
464 entry->data = kmalloc(entry->size * 4, GFP_KERNEL);
465 if (!entry->data)
466 goto error;
467 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
468 fwlen += entry->size;
469 }
470
471 *module_ret = module;
472 release_firmware(fw);
473 return 0;
474
475 error_inval:
476 err = -EINVAL;
477 error:
478 free_module_desc(module);
479 release_firmware(fw);
480 return err;
481}
1da177e4 482
3d19f804 483int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
1da177e4
LT		 484 unsigned long offset,
485 unsigned long len)
486{
487 void __iomem *dst;
488 unsigned int bank = offset >> 16;
489 offset = offset & 0xffff;
490
da3cec35
TI		 491 if (snd_BUG_ON((offset & 3) || (len & 3)))
492 return -EINVAL;
1da177e4
LT		 493 dst = chip->region.idx[bank+1].remap_addr + offset;
494 len /= sizeof(u32);
495
496 /* writel already converts 32-bit value to right endianess */
497 while (len-- > 0) {
498 writel(0, dst);
499 dst += sizeof(u32);
500 }
501 return 0;
502}
503
504#else /* old DSP image */
505
ad233a5f
TI		 506struct ba1_struct {
507 struct {
508 u32 offset;
509 u32 size;
510 } memory[BA1_MEMORY_COUNT];
511 u32 map[BA1_DWORD_SIZE];
512};
513
514MODULE_FIRMWARE("cs46xx/ba1");
515
516static int load_firmware(struct snd_cs46xx *chip)
517{
518 const struct firmware *fw;
519 int i, size, err;
520
521 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
522 if (err < 0)
523 return err;
524 if (fw->size != sizeof(*chip->ba1)) {
525 err = -EINVAL;
526 goto error;
527 }
528
529 chip->ba1 = vmalloc(sizeof(*chip->ba1));
530 if (!chip->ba1) {
531 err = -ENOMEM;
532 goto error;
533 }
534
535 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
536
537 /* sanity check */
538 size = 0;
539 for (i = 0; i < BA1_MEMORY_COUNT; i++)
540 size += chip->ba1->memory[i].size;
541 if (size > BA1_DWORD_SIZE * 4)
542 err = -EINVAL;
543
544 error:
545 release_firmware(fw);
546 return err;
547}
1da177e4 548
3d19f804 549int snd_cs46xx_download_image(struct snd_cs46xx *chip)
1da177e4
LT		 550{
551 int idx, err;
ad233a5f
TI		 552 unsigned int offset = 0;
553 struct ba1_struct *ba1 = chip->ba1;
1da177e4
LT		 554
555 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
ad233a5f
TI		 556 err = snd_cs46xx_download(chip,
557 &ba1->map[offset],
558 ba1->memory[idx].offset,
559 ba1->memory[idx].size);
560 if (err < 0)
1da177e4 561 return err;
ad233a5f 562 offset += ba1->memory[idx].size >> 2;
1da177e4
LT		 563 }
564 return 0;
565}
566#endif /* CONFIG_SND_CS46XX_NEW_DSP */
567
568/*
569 * Chip reset
570 */
571
3d19f804 572static void snd_cs46xx_reset(struct snd_cs46xx *chip)
1da177e4
LT		 573{
574 int idx;
575
576 /*
577 * Write the reset bit of the SP control register.
578 */
579 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
580
581 /*
582 * Write the control register.
583 */
584 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
585
586 /*
587 * Clear the trap registers.
588 */
589 for (idx = 0; idx < 8; idx++) {
590 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
591 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
592 }
593 snd_cs46xx_poke(chip, BA1_DREG, 0);
594
595 /*
596 * Set the frame timer to reflect the number of cycles per frame.
597 */
598 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
599}
600
3d19f804 601static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
1da177e4
LT		 602{
603 u32 i, status = 0;
604 /*
605 * Make sure the previous FIFO write operation has completed.
606 */
607 for(i = 0; i < 50; i++){
608 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
609
610 if( !(status & SERBST_WBSY) )
611 break;
612
613 mdelay(retry_timeout);
614 }
615
616 if(status & SERBST_WBSY) {
2b96a7f1
TI		 617 dev_err(chip->card->dev,
618 "failure waiting for FIFO command to complete\n");
1da177e4
LT		 619 return -EINVAL;
620 }
621
622 return 0;
623}
624
3d19f804 625static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
1da177e4
LT		 626{
627 int idx, powerdown = 0;
628 unsigned int tmp;
629
630 /*
631 * See if the devices are powered down. If so, we must power them up first
632 * or they will not respond.
633 */
634 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
635 if (!(tmp & CLKCR1_SWCE)) {
636 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
637 powerdown = 1;
638 }
639
640 /*
641 * We want to clear out the serial port FIFOs so we don't end up playing
642 * whatever random garbage happens to be in them. We fill the sample FIFOS
643 * with zero (silence).
644 */
645 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
646
647 /*
648 * Fill all 256 sample FIFO locations.
649 */
650 for (idx = 0; idx < 0xFF; idx++) {
651 /*
652 * Make sure the previous FIFO write operation has completed.
653 */
654 if (cs46xx_wait_for_fifo(chip,1)) {
2b96a7f1
TI		 655 dev_dbg(chip->card->dev,
656 "failed waiting for FIFO at addr (%02X)\n",
657 idx);
1da177e4
LT		 658
659 if (powerdown)
660 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
661
662 break;
663 }
664 /*
665 * Write the serial port FIFO index.
666 */
667 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
668 /*
669 * Tell the serial port to load the new value into the FIFO location.
670 */
671 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
672 }
673 /*
674 * Now, if we powered up the devices, then power them back down again.
675 * This is kinda ugly, but should never happen.
676 */
677 if (powerdown)
678 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
679}
680
3d19f804 681static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
1da177e4
LT		 682{
683 int cnt;
684
685 /*
686 * Set the frame timer to reflect the number of cycles per frame.
687 */
688 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
689 /*
690 * Turn on the run, run at frame, and DMA enable bits in the local copy of
691 * the SP control register.
692 */
693 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
694 /*
695 * Wait until the run at frame bit resets itself in the SP control
696 * register.
697 */
698 for (cnt = 0; cnt < 25; cnt++) {
699 udelay(50);
700 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
701 break;
702 }
703
704 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
2b96a7f1 705 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
1da177e4
LT		 706}
707
3d19f804 708static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
1da177e4
LT		 709{
710 /*
711 * Turn off the run, run at frame, and DMA enable bits in the local copy of
712 * the SP control register.
713 */
714 snd_cs46xx_poke(chip, BA1_SPCR, 0);
715}
716
717/*
718 * Sample rate routines
719 */
720
721#define GOF_PER_SEC 200
722
3d19f804 723static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 724{
725 unsigned long flags;
726 unsigned int tmp1, tmp2;
727 unsigned int phiIncr;
728 unsigned int correctionPerGOF, correctionPerSec;
729
730 /*
731 * Compute the values used to drive the actual sample rate conversion.
732 * The following formulas are being computed, using inline assembly
733 * since we need to use 64 bit arithmetic to compute the values:
734 *
735 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
736 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
737 * GOF_PER_SEC)
738 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
739 * GOF_PER_SEC * correctionPerGOF
740 *
741 * i.e.
742 *
743 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
744 * correctionPerGOF:correctionPerSec =
745 * dividend:remainder(ulOther / GOF_PER_SEC)
746 */
747 tmp1 = rate << 16;
748 phiIncr = tmp1 / 48000;
749 tmp1 -= phiIncr * 48000;
750 tmp1 <<= 10;
751 phiIncr <<= 10;
752 tmp2 = tmp1 / 48000;
753 phiIncr += tmp2;
754 tmp1 -= tmp2 * 48000;
755 correctionPerGOF = tmp1 / GOF_PER_SEC;
756 tmp1 -= correctionPerGOF * GOF_PER_SEC;
757 correctionPerSec = tmp1;
758
759 /*
760 * Fill in the SampleRateConverter control block.
761 */
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 snd_cs46xx_poke(chip, BA1_PSRC,
764 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
765 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
766 spin_unlock_irqrestore(&chip->reg_lock, flags);
767}
768
3d19f804 769static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 770{
771 unsigned long flags;
772 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
773 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
774 unsigned int frameGroupLength, cnt;
775
776 /*
777 * We can only decimate by up to a factor of 1/9th the hardware rate.
778 * Correct the value if an attempt is made to stray outside that limit.
779 */
780 if ((rate * 9) < 48000)
781 rate = 48000 / 9;
782
783 /*
784 * We can not capture at at rate greater than the Input Rate (48000).
785 * Return an error if an attempt is made to stray outside that limit.
786 */
787 if (rate > 48000)
788 rate = 48000;
789
790 /*
791 * Compute the values used to drive the actual sample rate conversion.
792 * The following formulas are being computed, using inline assembly
793 * since we need to use 64 bit arithmetic to compute the values:
794 *
795 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
796 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
797 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
798 * GOF_PER_SEC)
799 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
800 * GOF_PER_SEC * correctionPerGOF
801 * initialDelay = ceil((24 * Fs,in) / Fs,out)
802 *
803 * i.e.
804 *
805 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
806 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
807 * correctionPerGOF:correctionPerSec =
808 * dividend:remainder(ulOther / GOF_PER_SEC)
809 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
810 */
811
812 tmp1 = rate << 16;
813 coeffIncr = tmp1 / 48000;
814 tmp1 -= coeffIncr * 48000;
815 tmp1 <<= 7;
816 coeffIncr <<= 7;
817 coeffIncr += tmp1 / 48000;
818 coeffIncr ^= 0xFFFFFFFF;
819 coeffIncr++;
820 tmp1 = 48000 << 16;
821 phiIncr = tmp1 / rate;
822 tmp1 -= phiIncr * rate;
823 tmp1 <<= 10;
824 phiIncr <<= 10;
825 tmp2 = tmp1 / rate;
826 phiIncr += tmp2;
827 tmp1 -= tmp2 * rate;
828 correctionPerGOF = tmp1 / GOF_PER_SEC;
829 tmp1 -= correctionPerGOF * GOF_PER_SEC;
830 correctionPerSec = tmp1;
831 initialDelay = ((48000 * 24) + rate - 1) / rate;
832
833 /*
834 * Fill in the VariDecimate control block.
835 */
836 spin_lock_irqsave(&chip->reg_lock, flags);
837 snd_cs46xx_poke(chip, BA1_CSRC,
838 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
839 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
840 snd_cs46xx_poke(chip, BA1_CD,
841 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
842 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
843 spin_unlock_irqrestore(&chip->reg_lock, flags);
844
845 /*
846 * Figure out the frame group length for the write back task. Basically,
847 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
848 * the output sample rate.
849 */
850 frameGroupLength = 1;
851 for (cnt = 2; cnt <= 64; cnt *= 2) {
852 if (((rate / cnt) * cnt) != rate)
853 frameGroupLength *= 2;
854 }
855 if (((rate / 3) * 3) != rate) {
856 frameGroupLength *= 3;
857 }
858 for (cnt = 5; cnt <= 125; cnt *= 5) {
859 if (((rate / cnt) * cnt) != rate)
860 frameGroupLength *= 5;
861 }
862
863 /*
864 * Fill in the WriteBack control block.
865 */
866 spin_lock_irqsave(&chip->reg_lock, flags);
867 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
868 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
869 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
870 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
871 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
872 spin_unlock_irqrestore(&chip->reg_lock, flags);
873}
874
875/*
876 * PCM part
877 */
878
3d19f804
TI		 879static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
880 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 881{
3d19f804
TI		 882 struct snd_pcm_runtime *runtime = substream->runtime;
883 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 884 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
885}
886
3d19f804 887static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
1da177e4 888{
3d19f804
TI		 889 struct snd_pcm_runtime *runtime = substream->runtime;
890 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 891 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
892 return 0;
893}
894
3d19f804
TI		 895static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
896 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 897{
3d19f804
TI		 898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
899 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 900 memcpy(runtime->dma_area + rec->sw_data,
901 chip->capt.hw_buf.area + rec->hw_data, bytes);
902}
903
3d19f804 904static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
1da177e4 905{
3d19f804 906 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 907 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
908 return 0;
909}
910
3d19f804 911static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 912{
3d19f804 913 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 914 size_t ptr;
3d19f804 915 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
da3cec35
TI		 916
917 if (snd_BUG_ON(!cpcm->pcm_channel))
918 return -ENXIO;
1da177e4
LT		 919
920#ifdef CONFIG_SND_CS46XX_NEW_DSP
921 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
922#else
923 ptr = snd_cs46xx_peek(chip, BA1_PBA);
924#endif
925 ptr -= cpcm->hw_buf.addr;
926 return ptr >> cpcm->shift;
927}
928
3d19f804 929static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 930{
3d19f804 931 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 932 size_t ptr;
3d19f804 933 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 934
935#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 936 if (snd_BUG_ON(!cpcm->pcm_channel))
937 return -ENXIO;
1da177e4
LT		 938 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
939#else
940 ptr = snd_cs46xx_peek(chip, BA1_PBA);
941#endif
942 ptr -= cpcm->hw_buf.addr;
943 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
944}
945
3d19f804 946static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 947{
3d19f804 948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 949 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
950 return ptr >> chip->capt.shift;
951}
952
3d19f804 953static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 954{
3d19f804 955 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 956 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
957 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
958}
959
3d19f804 960static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 961 int cmd)
962{
3d19f804
TI		 963 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
964 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
1da177e4
LT		 965 int result = 0;
966
967#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 968 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 969 if (! cpcm->pcm_channel) {
970 return -ENXIO;
971 }
972#endif
973 switch (cmd) {
974 case SNDRV_PCM_TRIGGER_START:
975 case SNDRV_PCM_TRIGGER_RESUME:
976#ifdef CONFIG_SND_CS46XX_NEW_DSP
977 /* magic value to unmute PCM stream playback volume */
978 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
979 SCBVolumeCtrl) << 2, 0x80008000);
980
981 if (cpcm->pcm_channel->unlinked)
982 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
983
984 if (substream->runtime->periods != CS46XX_FRAGS)
985 snd_cs46xx_playback_transfer(substream);
986#else
987 spin_lock(&chip->reg_lock);
988 if (substream->runtime->periods != CS46XX_FRAGS)
989 snd_cs46xx_playback_transfer(substream);
990 { unsigned int tmp;
991 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
992 tmp &= 0x0000ffff;
993 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
994 }
995 spin_unlock(&chip->reg_lock);
996#endif
997 break;
998 case SNDRV_PCM_TRIGGER_STOP:
999 case SNDRV_PCM_TRIGGER_SUSPEND:
1000#ifdef CONFIG_SND_CS46XX_NEW_DSP
1001 /* magic mute channel */
1002 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
1003 SCBVolumeCtrl) << 2, 0xffffffff);
1004
1005 if (!cpcm->pcm_channel->unlinked)
1006 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
1007#else
1008 spin_lock(&chip->reg_lock);
1009 { unsigned int tmp;
1010 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
1011 tmp &= 0x0000ffff;
1012 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1013 }
1014 spin_unlock(&chip->reg_lock);
1015#endif
1016 break;
1017 default:
1018 result = -EINVAL;
1019 break;
1020 }
1021
1022 return result;
1023}
1024
3d19f804 1025static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1026 int cmd)
1027{
3d19f804 1028 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1029 unsigned int tmp;
1030 int result = 0;
1031
1032 spin_lock(&chip->reg_lock);
1033 switch (cmd) {
1034 case SNDRV_PCM_TRIGGER_START:
1035 case SNDRV_PCM_TRIGGER_RESUME:
1036 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1037 tmp &= 0xffff0000;
1038 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1039 break;
1040 case SNDRV_PCM_TRIGGER_STOP:
1041 case SNDRV_PCM_TRIGGER_SUSPEND:
1042 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1043 tmp &= 0xffff0000;
1044 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1045 break;
1046 default:
1047 result = -EINVAL;
1048 break;
1049 }
1050 spin_unlock(&chip->reg_lock);
1051
1052 return result;
1053}
1054
1055#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1056static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1da177e4
LT		 1057 int sample_rate)
1058{
1059
1060 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1061 if ( cpcm->pcm_channel == NULL) {
1062 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1063 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1064 if (cpcm->pcm_channel == NULL) {
2b96a7f1
TI		 1065 dev_err(chip->card->dev,
1066 "failed to create virtual PCM channel\n");
1da177e4
LT		 1067 return -ENOMEM;
1068 }
1069 cpcm->pcm_channel->sample_rate = sample_rate;
1070 } else
1071 /* if sample rate is changed */
1072 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1073 int unlinked = cpcm->pcm_channel->unlinked;
1074 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1075
1076 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1077 cpcm->hw_buf.addr,
1078 cpcm->pcm_channel_id)) == NULL) {
2b96a7f1
TI		 1079 dev_err(chip->card->dev,
1080 "failed to re-create virtual PCM channel\n");
1da177e4
LT		 1081 return -ENOMEM;
1082 }
1083
1084 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1085 cpcm->pcm_channel->sample_rate = sample_rate;
1086 }
1087
1088 return 0;
1089}
1090#endif
1091
1092
3d19f804
TI		 1093static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1094 struct snd_pcm_hw_params *hw_params)
1da177e4 1095{
3d19f804
TI		 1096 struct snd_pcm_runtime *runtime = substream->runtime;
1097 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1098 int err;
1099#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1100 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1101 int sample_rate = params_rate(hw_params);
1102 int period_size = params_period_bytes(hw_params);
1103#endif
1104 cpcm = runtime->private_data;
1105
1106#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 1107 if (snd_BUG_ON(!sample_rate))
1108 return -ENXIO;
1da177e4 1109
62932df8 1110 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1111
1112 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
62932df8 1113 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1114 return -ENXIO;
1115 }
1116
da3cec35 1117 snd_BUG_ON(!cpcm->pcm_channel);
1da177e4 1118 if (!cpcm->pcm_channel) {
62932df8 1119 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1120 return -ENXIO;
1121 }
1122
1123
1124 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
62932df8 1125 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1126 return -EINVAL;
1127 }
1128
2b96a7f1
TI		 1129 dev_dbg(chip->card->dev,
1130 "period_size (%d), periods (%d) buffer_size(%d)\n",
1da177e4
LT		 1131 period_size, params_periods(hw_params),
1132 params_buffer_bytes(hw_params));
1133#endif
1134
1135 if (params_periods(hw_params) == CS46XX_FRAGS) {
1136 if (runtime->dma_area != cpcm->hw_buf.area)
1137 snd_pcm_lib_free_pages(substream);
1138 runtime->dma_area = cpcm->hw_buf.area;
1139 runtime->dma_addr = cpcm->hw_buf.addr;
1140 runtime->dma_bytes = cpcm->hw_buf.bytes;
1141
1142
1143#ifdef CONFIG_SND_CS46XX_NEW_DSP
1144 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1145 substream->ops = &snd_cs46xx_playback_ops;
1146 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1147 substream->ops = &snd_cs46xx_playback_rear_ops;
1148 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1149 substream->ops = &snd_cs46xx_playback_clfe_ops;
1150 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1151 substream->ops = &snd_cs46xx_playback_iec958_ops;
1152 } else {
da3cec35 1153 snd_BUG();
1da177e4
LT		 1154 }
1155#else
1156 substream->ops = &snd_cs46xx_playback_ops;
1157#endif
1158
1159 } else {
1160 if (runtime->dma_area == cpcm->hw_buf.area) {
1161 runtime->dma_area = NULL;
1162 runtime->dma_addr = 0;
1163 runtime->dma_bytes = 0;
1164 }
1165 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1166#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1167 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1168#endif
1169 return err;
1170 }
1171
1172#ifdef CONFIG_SND_CS46XX_NEW_DSP
1173 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1174 substream->ops = &snd_cs46xx_playback_indirect_ops;
1175 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1176 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1177 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1178 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1179 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1180 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1181 } else {
da3cec35 1182 snd_BUG();
1da177e4
LT		 1183 }
1184#else
1185 substream->ops = &snd_cs46xx_playback_indirect_ops;
1186#endif
1187
1188 }
1189
1190#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1191 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1192#endif
1193
1194 return 0;
1195}
1196
3d19f804 1197static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4 1198{
3d19f804
TI		 1199 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1200 struct snd_pcm_runtime *runtime = substream->runtime;
1201 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1202
1203 cpcm = runtime->private_data;
1204
1205 /* if play_back open fails, then this function
1206 is called and cpcm can actually be NULL here */
1207 if (!cpcm) return -ENXIO;
1208
1209 if (runtime->dma_area != cpcm->hw_buf.area)
1210 snd_pcm_lib_free_pages(substream);
1211
1212 runtime->dma_area = NULL;
1213 runtime->dma_addr = 0;
1214 runtime->dma_bytes = 0;
1215
1216 return 0;
1217}
1218
3d19f804 1219static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1220{
1221 unsigned int tmp;
1222 unsigned int pfie;
3d19f804
TI		 1223 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1224 struct snd_pcm_runtime *runtime = substream->runtime;
1225 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1226
1227 cpcm = runtime->private_data;
1228
1229#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 1230 if (snd_BUG_ON(!cpcm->pcm_channel))
1231 return -ENXIO;
1da177e4
LT		 1232
1233 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1234 pfie &= ~0x0000f03f;
1235#else
1236 /* old dsp */
1237 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1238 pfie &= ~0x0000f03f;
1239#endif
1240
1241 cpcm->shift = 2;
1242 /* if to convert from stereo to mono */
1243 if (runtime->channels == 1) {
1244 cpcm->shift--;
1245 pfie |= 0x00002000;
1246 }
1247 /* if to convert from 8 bit to 16 bit */
1248 if (snd_pcm_format_width(runtime->format) == 8) {
1249 cpcm->shift--;
1250 pfie |= 0x00001000;
1251 }
1252 /* if to convert to unsigned */
1253 if (snd_pcm_format_unsigned(runtime->format))
1254 pfie |= 0x00008000;
1255
1256 /* Never convert byte order when sample stream is 8 bit */
1257 if (snd_pcm_format_width(runtime->format) != 8) {
1258 /* convert from big endian to little endian */
1259 if (snd_pcm_format_big_endian(runtime->format))
1260 pfie |= 0x00004000;
1261 }
1262
1263 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1264 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1265 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1266
1267#ifdef CONFIG_SND_CS46XX_NEW_DSP
1268
1269 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1270 tmp &= ~0x000003ff;
1271 tmp |= (4 << cpcm->shift) - 1;
1272 /* playback transaction count register */
1273 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1274
1275 /* playback format && interrupt enable */
1276 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1277#else
1278 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1279 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1280 tmp &= ~0x000003ff;
1281 tmp |= (4 << cpcm->shift) - 1;
1282 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1283 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1284 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1285#endif
1286
1287 return 0;
1288}
1289
3d19f804
TI		 1290static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1291 struct snd_pcm_hw_params *hw_params)
1da177e4 1292{
3d19f804
TI		 1293 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1294 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1295 int err;
1296
1297#ifdef CONFIG_SND_CS46XX_NEW_DSP
1298 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1299#endif
1300 if (runtime->periods == CS46XX_FRAGS) {
1301 if (runtime->dma_area != chip->capt.hw_buf.area)
1302 snd_pcm_lib_free_pages(substream);
1303 runtime->dma_area = chip->capt.hw_buf.area;
1304 runtime->dma_addr = chip->capt.hw_buf.addr;
1305 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1306 substream->ops = &snd_cs46xx_capture_ops;
1307 } else {
1308 if (runtime->dma_area == chip->capt.hw_buf.area) {
1309 runtime->dma_area = NULL;
1310 runtime->dma_addr = 0;
1311 runtime->dma_bytes = 0;
1312 }
1313 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1314 return err;
1315 substream->ops = &snd_cs46xx_capture_indirect_ops;
1316 }
1317
1318 return 0;
1319}
1320
3d19f804 1321static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4 1322{
3d19f804
TI		 1323 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1324 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1325
1326 if (runtime->dma_area != chip->capt.hw_buf.area)
1327 snd_pcm_lib_free_pages(substream);
1328 runtime->dma_area = NULL;
1329 runtime->dma_addr = 0;
1330 runtime->dma_bytes = 0;
1331
1332 return 0;
1333}
1334
3d19f804 1335static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1336{
3d19f804
TI		 1337 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1338 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1339
1340 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1341 chip->capt.shift = 2;
1342 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1343 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1344 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1345 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1346
1347 return 0;
1348}
1349
7d12e780 1350static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1da177e4 1351{
3d19f804 1352 struct snd_cs46xx *chip = dev_id;
1da177e4
LT		 1353 u32 status1;
1354#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1355 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1356 u32 status2;
1357 int i;
3d19f804 1358 struct snd_cs46xx_pcm *cpcm = NULL;
1da177e4
LT		 1359#endif
1360
1361 /*
1362 * Read the Interrupt Status Register to clear the interrupt
1363 */
1364 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1365 if ((status1 & 0x7fffffff) == 0) {
1366 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1367 return IRQ_NONE;
1368 }
1369
1370#ifdef CONFIG_SND_CS46XX_NEW_DSP
1371 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1372
1373 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1374 if (i <= 15) {
1375 if ( status1 & (1 << i) ) {
1376 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1377 if (chip->capt.substream)
1378 snd_pcm_period_elapsed(chip->capt.substream);
1379 } else {
1380 if (ins->pcm_channels[i].active &&
1381 ins->pcm_channels[i].private_data &&
1382 !ins->pcm_channels[i].unlinked) {
1383 cpcm = ins->pcm_channels[i].private_data;
1384 snd_pcm_period_elapsed(cpcm->substream);
1385 }
1386 }
1387 }
1388 } else {
1389 if ( status2 & (1 << (i - 16))) {
1390 if (ins->pcm_channels[i].active &&
1391 ins->pcm_channels[i].private_data &&
1392 !ins->pcm_channels[i].unlinked) {
1393 cpcm = ins->pcm_channels[i].private_data;
1394 snd_pcm_period_elapsed(cpcm->substream);
1395 }
1396 }
1397 }
1398 }
1399
1400#else
1401 /* old dsp */
1402 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1403 if (chip->playback_pcm->substream)
1404 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1405 }
1406 if ((status1 & HISR_VC1) && chip->pcm) {
1407 if (chip->capt.substream)
1408 snd_pcm_period_elapsed(chip->capt.substream);
1409 }
1410#endif
1411
1412 if ((status1 & HISR_MIDI) && chip->rmidi) {
1413 unsigned char c;
1414
1415 spin_lock(&chip->reg_lock);
1416 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1417 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1418 if ((chip->midcr & MIDCR_RIE) == 0)
1419 continue;
1420 snd_rawmidi_receive(chip->midi_input, &c, 1);
1421 }
1422 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1423 if ((chip->midcr & MIDCR_TIE) == 0)
1424 break;
1425 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1426 chip->midcr &= ~MIDCR_TIE;
1427 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1428 break;
1429 }
1430 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1431 }
1432 spin_unlock(&chip->reg_lock);
1433 }
1434 /*
1435 * EOI to the PCI part....reenables interrupts
1436 */
1437 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1438
1439 return IRQ_HANDLED;
1440}
1441
3d19f804 1442static struct snd_pcm_hardware snd_cs46xx_playback =
1da177e4
LT		 1443{
1444 .info = (SNDRV_PCM_INFO_MMAP |
1445 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1446 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1447 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1448 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1449 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1450 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1451 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1452 .rate_min = 5500,
1453 .rate_max = 48000,
1454 .channels_min = 1,
1455 .channels_max = 2,
1456 .buffer_bytes_max = (256 * 1024),
1457 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1458 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1459 .periods_min = CS46XX_FRAGS,
1460 .periods_max = 1024,
1461 .fifo_size = 0,
1462};
1463
3d19f804 1464static struct snd_pcm_hardware snd_cs46xx_capture =
1da177e4
LT		 1465{
1466 .info = (SNDRV_PCM_INFO_MMAP |
1467 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1468 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1469 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1470 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1471 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1472 .rate_min = 5500,
1473 .rate_max = 48000,
1474 .channels_min = 2,
1475 .channels_max = 2,
1476 .buffer_bytes_max = (256 * 1024),
1477 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1478 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1479 .periods_min = CS46XX_FRAGS,
1480 .periods_max = 1024,
1481 .fifo_size = 0,
1482};
1483
1484#ifdef CONFIG_SND_CS46XX_NEW_DSP
1485
1486static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1487
3d19f804 1488static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1da177e4
LT		 1489 .count = ARRAY_SIZE(period_sizes),
1490 .list = period_sizes,
1491 .mask = 0
1492};
1493
1494#endif
1495
3d19f804 1496static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1da177e4 1497{
4d572776 1498 kfree(runtime->private_data);
1da177e4
LT		 1499}
1500
3d19f804 1501static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1da177e4 1502{
3d19f804
TI		 1503 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1504 struct snd_cs46xx_pcm * cpcm;
1505 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1506
e560d8d8 1507 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1da177e4
LT		 1508 if (cpcm == NULL)
1509 return -ENOMEM;
1510 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1511 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1512 kfree(cpcm);
1513 return -ENOMEM;
1514 }
1515
1516 runtime->hw = snd_cs46xx_playback;
1517 runtime->private_data = cpcm;
1518 runtime->private_free = snd_cs46xx_pcm_free_substream;
1519
1520 cpcm->substream = substream;
1521#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1522 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1523 cpcm->pcm_channel = NULL;
1524 cpcm->pcm_channel_id = pcm_channel_id;
1525
1526
1527 snd_pcm_hw_constraint_list(runtime, 0,
1528 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1529 &hw_constraints_period_sizes);
1530
62932df8 1531 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1532#else
1533 chip->playback_pcm = cpcm; /* HACK */
1534#endif
1535
1536 if (chip->accept_valid)
1537 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1538 chip->active_ctrl(chip, 1);
1539
1540 return 0;
1541}
1542
3d19f804 1543static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1da177e4 1544{
2b96a7f1 1545 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1da177e4
LT		 1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1547}
1548
1549#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1550static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1da177e4 1551{
2b96a7f1 1552 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1da177e4
LT		 1553 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1554}
1555
3d19f804 1556static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1da177e4 1557{
2b96a7f1 1558 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1da177e4
LT		 1559 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1560}
1561
3d19f804 1562static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1da177e4 1563{
3d19f804 1564 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 1565
2b96a7f1 1566 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1da177e4 1567
62932df8 1568 mutex_lock(&chip->spos_mutex);
1da177e4 1569 cs46xx_iec958_pre_open (chip);
62932df8 1570 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1571
1572 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1573}
1574
3d19f804 1575static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1da177e4 1576
3d19f804 1577static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1da177e4
LT		 1578{
1579 int err;
3d19f804 1580 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 1581
2b96a7f1 1582 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1da177e4
LT		 1583
1584 err = snd_cs46xx_playback_close(substream);
1585
62932df8 1586 mutex_lock(&chip->spos_mutex);
1da177e4 1587 cs46xx_iec958_post_close (chip);
62932df8 1588 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1589
1590 return err;
1591}
1592#endif
1593
3d19f804 1594static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1da177e4 1595{
3d19f804 1596 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1597
1598 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1599 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1600 return -ENOMEM;
1601 chip->capt.substream = substream;
1602 substream->runtime->hw = snd_cs46xx_capture;
1603
1604 if (chip->accept_valid)
1605 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1606
1607 chip->active_ctrl(chip, 1);
1608
1609#ifdef CONFIG_SND_CS46XX_NEW_DSP
1610 snd_pcm_hw_constraint_list(substream->runtime, 0,
1611 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1612 &hw_constraints_period_sizes);
1613#endif
1614 return 0;
1615}
1616
3d19f804 1617static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1da177e4 1618{
3d19f804
TI		 1619 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1620 struct snd_pcm_runtime *runtime = substream->runtime;
1621 struct snd_cs46xx_pcm * cpcm;
1da177e4
LT		 1622
1623 cpcm = runtime->private_data;
1624
1625 /* when playback_open fails, then cpcm can be NULL */
1626 if (!cpcm) return -ENXIO;
1627
1628#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1629 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1630 if (cpcm->pcm_channel) {
1631 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1632 cpcm->pcm_channel = NULL;
1633 }
62932df8 1634 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1635#else
1636 chip->playback_pcm = NULL;
1637#endif
1638
1639 cpcm->substream = NULL;
1640 snd_dma_free_pages(&cpcm->hw_buf);
1641 chip->active_ctrl(chip, -1);
1642
1643 return 0;
1644}
1645
3d19f804 1646static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1da177e4 1647{
3d19f804 1648 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1649
1650 chip->capt.substream = NULL;
1651 snd_dma_free_pages(&chip->capt.hw_buf);
1652 chip->active_ctrl(chip, -1);
1653
1654 return 0;
1655}
1656
1657#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1658static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1da177e4
LT		 1659 .open = snd_cs46xx_playback_open_rear,
1660 .close = snd_cs46xx_playback_close,
1661 .ioctl = snd_pcm_lib_ioctl,
1662 .hw_params = snd_cs46xx_playback_hw_params,
1663 .hw_free = snd_cs46xx_playback_hw_free,
1664 .prepare = snd_cs46xx_playback_prepare,
1665 .trigger = snd_cs46xx_playback_trigger,
1666 .pointer = snd_cs46xx_playback_direct_pointer,
1667};
1668
3d19f804 1669static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1da177e4
LT		 1670 .open = snd_cs46xx_playback_open_rear,
1671 .close = snd_cs46xx_playback_close,
1672 .ioctl = snd_pcm_lib_ioctl,
1673 .hw_params = snd_cs46xx_playback_hw_params,
1674 .hw_free = snd_cs46xx_playback_hw_free,
1675 .prepare = snd_cs46xx_playback_prepare,
1676 .trigger = snd_cs46xx_playback_trigger,
1677 .pointer = snd_cs46xx_playback_indirect_pointer,
1678 .ack = snd_cs46xx_playback_transfer,
1679};
1680
3d19f804 1681static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1da177e4
LT		 1682 .open = snd_cs46xx_playback_open_clfe,
1683 .close = snd_cs46xx_playback_close,
1684 .ioctl = snd_pcm_lib_ioctl,
1685 .hw_params = snd_cs46xx_playback_hw_params,
1686 .hw_free = snd_cs46xx_playback_hw_free,
1687 .prepare = snd_cs46xx_playback_prepare,
1688 .trigger = snd_cs46xx_playback_trigger,
1689 .pointer = snd_cs46xx_playback_direct_pointer,
1690};
1691
3d19f804 1692static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1da177e4
LT		 1693 .open = snd_cs46xx_playback_open_clfe,
1694 .close = snd_cs46xx_playback_close,
1695 .ioctl = snd_pcm_lib_ioctl,
1696 .hw_params = snd_cs46xx_playback_hw_params,
1697 .hw_free = snd_cs46xx_playback_hw_free,
1698 .prepare = snd_cs46xx_playback_prepare,
1699 .trigger = snd_cs46xx_playback_trigger,
1700 .pointer = snd_cs46xx_playback_indirect_pointer,
1701 .ack = snd_cs46xx_playback_transfer,
1702};
1703
3d19f804 1704static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1da177e4
LT		 1705 .open = snd_cs46xx_playback_open_iec958,
1706 .close = snd_cs46xx_playback_close_iec958,
1707 .ioctl = snd_pcm_lib_ioctl,
1708 .hw_params = snd_cs46xx_playback_hw_params,
1709 .hw_free = snd_cs46xx_playback_hw_free,
1710 .prepare = snd_cs46xx_playback_prepare,
1711 .trigger = snd_cs46xx_playback_trigger,
1712 .pointer = snd_cs46xx_playback_direct_pointer,
1713};
1714
3d19f804 1715static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1da177e4
LT		 1716 .open = snd_cs46xx_playback_open_iec958,
1717 .close = snd_cs46xx_playback_close_iec958,
1718 .ioctl = snd_pcm_lib_ioctl,
1719 .hw_params = snd_cs46xx_playback_hw_params,
1720 .hw_free = snd_cs46xx_playback_hw_free,
1721 .prepare = snd_cs46xx_playback_prepare,
1722 .trigger = snd_cs46xx_playback_trigger,
1723 .pointer = snd_cs46xx_playback_indirect_pointer,
1724 .ack = snd_cs46xx_playback_transfer,
1725};
1726
1727#endif
1728
3d19f804 1729static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1da177e4
LT		 1730 .open = snd_cs46xx_playback_open,
1731 .close = snd_cs46xx_playback_close,
1732 .ioctl = snd_pcm_lib_ioctl,
1733 .hw_params = snd_cs46xx_playback_hw_params,
1734 .hw_free = snd_cs46xx_playback_hw_free,
1735 .prepare = snd_cs46xx_playback_prepare,
1736 .trigger = snd_cs46xx_playback_trigger,
1737 .pointer = snd_cs46xx_playback_direct_pointer,
1738};
1739
3d19f804 1740static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1da177e4
LT		 1741 .open = snd_cs46xx_playback_open,
1742 .close = snd_cs46xx_playback_close,
1743 .ioctl = snd_pcm_lib_ioctl,
1744 .hw_params = snd_cs46xx_playback_hw_params,
1745 .hw_free = snd_cs46xx_playback_hw_free,
1746 .prepare = snd_cs46xx_playback_prepare,
1747 .trigger = snd_cs46xx_playback_trigger,
1748 .pointer = snd_cs46xx_playback_indirect_pointer,
1749 .ack = snd_cs46xx_playback_transfer,
1750};
1751
3d19f804 1752static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1da177e4
LT		 1753 .open = snd_cs46xx_capture_open,
1754 .close = snd_cs46xx_capture_close,
1755 .ioctl = snd_pcm_lib_ioctl,
1756 .hw_params = snd_cs46xx_capture_hw_params,
1757 .hw_free = snd_cs46xx_capture_hw_free,
1758 .prepare = snd_cs46xx_capture_prepare,
1759 .trigger = snd_cs46xx_capture_trigger,
1760 .pointer = snd_cs46xx_capture_direct_pointer,
1761};
1762
3d19f804 1763static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1da177e4
LT		 1764 .open = snd_cs46xx_capture_open,
1765 .close = snd_cs46xx_capture_close,
1766 .ioctl = snd_pcm_lib_ioctl,
1767 .hw_params = snd_cs46xx_capture_hw_params,
1768 .hw_free = snd_cs46xx_capture_hw_free,
1769 .prepare = snd_cs46xx_capture_prepare,
1770 .trigger = snd_cs46xx_capture_trigger,
1771 .pointer = snd_cs46xx_capture_indirect_pointer,
1772 .ack = snd_cs46xx_capture_transfer,
1773};
1774
1da177e4 1775#ifdef CONFIG_SND_CS46XX_NEW_DSP
1da177e4
LT		 1776#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1777#else
1778#define MAX_PLAYBACK_CHANNELS 1
1779#endif
1780
72134c4d 1781int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1da177e4 1782{
3d19f804 1783 struct snd_pcm *pcm;
1da177e4
LT		 1784 int err;
1785
1da177e4
LT		 1786 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1787 return err;
1788
1789 pcm->private_data = chip;
1da177e4
LT		 1790
1791 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1792 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1793
1794 /* global setup */
1795 pcm->info_flags = 0;
1796 strcpy(pcm->name, "CS46xx");
1797 chip->pcm = pcm;
1798
1799 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1800 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1801
1da177e4
LT		 1802 return 0;
1803}
1804
1805
1806#ifdef CONFIG_SND_CS46XX_NEW_DSP
72134c4d 1807int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1da177e4 1808{
3d19f804 1809 struct snd_pcm *pcm;
1da177e4
LT		 1810 int err;
1811
1da177e4
LT		 1812 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1813 return err;
1814
1815 pcm->private_data = chip;
1da177e4
LT		 1816
1817 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1818
1819 /* global setup */
1820 pcm->info_flags = 0;
1821 strcpy(pcm->name, "CS46xx - Rear");
1822 chip->pcm_rear = pcm;
1823
1824 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1825 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1826
1da177e4
LT		 1827 return 0;
1828}
1829
72134c4d 1830int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1da177e4 1831{
3d19f804 1832 struct snd_pcm *pcm;
1da177e4
LT		 1833 int err;
1834
1da177e4
LT		 1835 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1836 return err;
1837
1838 pcm->private_data = chip;
1da177e4
LT		 1839
1840 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1841
1842 /* global setup */
1843 pcm->info_flags = 0;
1844 strcpy(pcm->name, "CS46xx - Center LFE");
1845 chip->pcm_center_lfe = pcm;
1846
1847 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1848 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1849
1da177e4
LT		 1850 return 0;
1851}
1852
72134c4d 1853int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1da177e4 1854{
3d19f804 1855 struct snd_pcm *pcm;
1da177e4
LT		 1856 int err;
1857
1da177e4
LT		 1858 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1859 return err;
1860
1861 pcm->private_data = chip;
1da177e4
LT		 1862
1863 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1864
1865 /* global setup */
1866 pcm->info_flags = 0;
1867 strcpy(pcm->name, "CS46xx - IEC958");
1868 chip->pcm_rear = pcm;
1869
1870 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1871 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1872
1da177e4
LT		 1873 return 0;
1874}
1875#endif
1876
1877/*
1878 * Mixer routines
1879 */
3d19f804 1880static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1881{
3d19f804 1882 struct snd_cs46xx *chip = bus->private_data;
1da177e4
LT		 1883
1884 chip->ac97_bus = NULL;
1885}
1886
3d19f804 1887static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1888{
3d19f804 1889 struct snd_cs46xx *chip = ac97->private_data;
1da177e4 1890
da3cec35
TI		 1891 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1892 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1893 return;
1da177e4
LT		 1894
1895 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1896 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1897 chip->eapd_switch = NULL;
1898 }
1899 else
1900 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1901}
1902
3d19f804
TI		 1903static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1904 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1905{
1906 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1907 uinfo->count = 2;
1908 uinfo->value.integer.min = 0;
1909 uinfo->value.integer.max = 0x7fff;
1910 return 0;
1911}
1912
3d19f804 1913static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1914{
3d19f804 1915 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1916 int reg = kcontrol->private_value;
1917 unsigned int val = snd_cs46xx_peek(chip, reg);
1918 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1919 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1920 return 0;
1921}
1922
3d19f804 1923static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1924{
3d19f804 1925 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1926 int reg = kcontrol->private_value;
1927 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1928 (0xffff - ucontrol->value.integer.value[1]));
1929 unsigned int old = snd_cs46xx_peek(chip, reg);
1930 int change = (old != val);
1931
1932 if (change) {
1933 snd_cs46xx_poke(chip, reg, val);
1934 }
1935
1936 return change;
1937}
1938
1939#ifdef CONFIG_SND_CS46XX_NEW_DSP
1940
3d19f804 1941static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1942{
3d19f804 1943 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1944
1945 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1946 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1947
1948 return 0;
1949}
1950
3d19f804 1951static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1952{
3d19f804 1953 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1954 int change = 0;
1955
1956 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1957 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1958 cs46xx_dsp_set_dac_volume(chip,
1959 ucontrol->value.integer.value[0],
1960 ucontrol->value.integer.value[1]);
1961 change = 1;
1962 }
1963
1964 return change;
1965}
1966
1967#if 0
3d19f804 1968static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1969{
3d19f804 1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1971
1972 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1973 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1974 return 0;
1975}
1976
3d19f804 1977static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1978{
3d19f804 1979 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1980 int change = 0;
1981
1982 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1983 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1984 cs46xx_dsp_set_iec958_volume (chip,
1985 ucontrol->value.integer.value[0],
1986 ucontrol->value.integer.value[1]);
1987 change = 1;
1988 }
1989
1990 return change;
1991}
1992#endif
1993
a5ce8890 1994#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1da177e4 1995
3d19f804
TI		 1996static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1997 struct snd_ctl_elem_value *ucontrol)
1da177e4 1998{
3d19f804 1999 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2000 int reg = kcontrol->private_value;
2001
2002 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
2003 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2004 else
2005 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
2006
2007 return 0;
2008}
2009
3d19f804
TI		 2010static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
1da177e4 2012{
3d19f804 2013 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2014 int change, res;
2015
2016 switch (kcontrol->private_value) {
2017 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
62932df8 2018 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2019 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2020 if (ucontrol->value.integer.value[0] && !change)
2021 cs46xx_dsp_enable_spdif_out(chip);
2022 else if (change && !ucontrol->value.integer.value[0])
2023 cs46xx_dsp_disable_spdif_out(chip);
2024
2025 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
62932df8 2026 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2027 break;
2028 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2029 change = chip->dsp_spos_instance->spdif_status_in;
2030 if (ucontrol->value.integer.value[0] && !change) {
2031 cs46xx_dsp_enable_spdif_in(chip);
2032 /* restore volume */
2033 }
2034 else if (change && !ucontrol->value.integer.value[0])
2035 cs46xx_dsp_disable_spdif_in(chip);
2036
2037 res = (change != chip->dsp_spos_instance->spdif_status_in);
2038 break;
2039 default:
2040 res = -EINVAL;
da3cec35 2041 snd_BUG(); /* should never happen ... */
1da177e4
LT		 2042 }
2043
2044 return res;
2045}
2046
3d19f804
TI		 2047static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2048 struct snd_ctl_elem_value *ucontrol)
1da177e4 2049{
3d19f804
TI		 2050 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2051 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2052
2053 if (ins->adc_input != NULL)
2054 ucontrol->value.integer.value[0] = 1;
2055 else
2056 ucontrol->value.integer.value[0] = 0;
2057
2058 return 0;
2059}
2060
3d19f804
TI		 2061static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2062 struct snd_ctl_elem_value *ucontrol)
1da177e4 2063{
3d19f804
TI		 2064 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2065 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2066 int change = 0;
2067
2068 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2069 cs46xx_dsp_enable_adc_capture(chip);
2070 change = 1;
2071 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2072 cs46xx_dsp_disable_adc_capture(chip);
2073 change = 1;
2074 }
2075 return change;
2076}
2077
3d19f804
TI		 2078static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *ucontrol)
1da177e4 2080{
3d19f804
TI		 2081 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2082 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2083
2084 if (ins->pcm_input != NULL)
2085 ucontrol->value.integer.value[0] = 1;
2086 else
2087 ucontrol->value.integer.value[0] = 0;
2088
2089 return 0;
2090}
2091
2092
3d19f804
TI		 2093static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2094 struct snd_ctl_elem_value *ucontrol)
1da177e4 2095{
3d19f804
TI		 2096 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2097 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2098 int change = 0;
2099
2100 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2101 cs46xx_dsp_enable_pcm_capture(chip);
2102 change = 1;
2103 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2104 cs46xx_dsp_disable_pcm_capture(chip);
2105 change = 1;
2106 }
2107
2108 return change;
2109}
2110
3d19f804
TI		 2111static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2112 struct snd_ctl_elem_value *ucontrol)
1da177e4 2113{
3d19f804 2114 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2115
2116 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2117
2118 if (val1 & EGPIODR_GPOE0)
2119 ucontrol->value.integer.value[0] = 1;
2120 else
2121 ucontrol->value.integer.value[0] = 0;
2122
2123 return 0;
2124}
2125
2126/*
2127 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2128 */
3d19f804
TI		 2129static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_value *ucontrol)
1da177e4 2131{
3d19f804 2132 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2133 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2134 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2135
2136 if (ucontrol->value.integer.value[0]) {
2137 /* optical is default */
2138 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2139 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2140 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2141 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2142 } else {
2143 /* coaxial */
2144 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2145 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2146 }
2147
2148 /* checking diff from the EGPIO direction register
2149 should be enough */
2150 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2151}
2152
2153
3d19f804 2154static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2155{
2156 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2157 uinfo->count = 1;
2158 return 0;
2159}
2160
3d19f804
TI		 2161static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2162 struct snd_ctl_elem_value *ucontrol)
1da177e4 2163{
3d19f804
TI		 2164 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2165 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 2166
62932df8 2167 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2168 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2169 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2170 ucontrol->value.iec958.status[2] = 0;
2171 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
62932df8 2172 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2173
2174 return 0;
2175}
2176
3d19f804
TI		 2177static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2178 struct snd_ctl_elem_value *ucontrol)
1da177e4 2179{
3d19f804
TI		 2180 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2181 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2182 unsigned int val;
2183 int change;
2184
62932df8 2185 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2186 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2187 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2188 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2189 /* left and right validity bit */
2190 (1 << 13) | (1 << 12);
2191
2192
2193 change = (unsigned int)ins->spdif_csuv_default != val;
2194 ins->spdif_csuv_default = val;
2195
2196 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2197 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2198
62932df8 2199 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2200
2201 return change;
2202}
2203
3d19f804
TI		 2204static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2205 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2206{
2207 ucontrol->value.iec958.status[0] = 0xff;
2208 ucontrol->value.iec958.status[1] = 0xff;
2209 ucontrol->value.iec958.status[2] = 0x00;
2210 ucontrol->value.iec958.status[3] = 0xff;
2211 return 0;
2212}
2213
3d19f804
TI		 2214static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2215 struct snd_ctl_elem_value *ucontrol)
1da177e4 2216{
3d19f804
TI		 2217 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2218 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 2219
62932df8 2220 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2221 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2222 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2223 ucontrol->value.iec958.status[2] = 0;
2224 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
62932df8 2225 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2226
2227 return 0;
2228}
2229
3d19f804
TI		 2230static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2231 struct snd_ctl_elem_value *ucontrol)
1da177e4 2232{
3d19f804
TI		 2233 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2234 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2235 unsigned int val;
2236 int change;
2237
62932df8 2238 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2239 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2240 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2241 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2242 /* left and right validity bit */
2243 (1 << 13) | (1 << 12);
2244
2245
2246 change = ins->spdif_csuv_stream != val;
2247 ins->spdif_csuv_stream = val;
2248
2249 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2250 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2251
62932df8 2252 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2253
2254 return change;
2255}
2256
2257#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2258
2259
e23e7a14 2260static struct snd_kcontrol_new snd_cs46xx_controls[] = {
1da177e4
LT		 2261{
2262 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2263 .name = "DAC Volume",
2264 .info = snd_cs46xx_vol_info,
2265#ifndef CONFIG_SND_CS46XX_NEW_DSP
2266 .get = snd_cs46xx_vol_get,
2267 .put = snd_cs46xx_vol_put,
2268 .private_value = BA1_PVOL,
2269#else
2270 .get = snd_cs46xx_vol_dac_get,
2271 .put = snd_cs46xx_vol_dac_put,
2272#endif
2273},
2274
2275{
2276 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2277 .name = "ADC Volume",
2278 .info = snd_cs46xx_vol_info,
2279 .get = snd_cs46xx_vol_get,
2280 .put = snd_cs46xx_vol_put,
2281#ifndef CONFIG_SND_CS46XX_NEW_DSP
2282 .private_value = BA1_CVOL,
2283#else
2284 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2285#endif
2286},
2287#ifdef CONFIG_SND_CS46XX_NEW_DSP
2288{
2289 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2290 .name = "ADC Capture Switch",
2291 .info = snd_mixer_boolean_info,
2292 .get = snd_cs46xx_adc_capture_get,
2293 .put = snd_cs46xx_adc_capture_put
2294},
2295{
2296 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2297 .name = "DAC Capture Switch",
2298 .info = snd_mixer_boolean_info,
2299 .get = snd_cs46xx_pcm_capture_get,
2300 .put = snd_cs46xx_pcm_capture_put
2301},
2302{
2303 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2304 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
1da177e4
LT		 2305 .info = snd_mixer_boolean_info,
2306 .get = snd_cs46xx_iec958_get,
2307 .put = snd_cs46xx_iec958_put,
2308 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2309},
2310{
2311 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2312 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
1da177e4
LT		 2313 .info = snd_mixer_boolean_info,
2314 .get = snd_cs46xx_iec958_get,
2315 .put = snd_cs46xx_iec958_put,
2316 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2317},
2318#if 0
2319/* Input IEC958 volume does not work for the moment. (Benny) */
2320{
2321 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2322 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
1da177e4
LT		 2323 .info = snd_cs46xx_vol_info,
2324 .get = snd_cs46xx_vol_iec958_get,
2325 .put = snd_cs46xx_vol_iec958_put,
2326 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2327},
2328#endif
2329{
2330 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2331 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2332 .info = snd_cs46xx_spdif_info,
2333 .get = snd_cs46xx_spdif_default_get,
2334 .put = snd_cs46xx_spdif_default_put,
2335},
2336{
2337 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2338 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2339 .info = snd_cs46xx_spdif_info,
2340 .get = snd_cs46xx_spdif_mask_get,
2341 .access = SNDRV_CTL_ELEM_ACCESS_READ
2342},
2343{
2344 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2345 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2346 .info = snd_cs46xx_spdif_info,
2347 .get = snd_cs46xx_spdif_stream_get,
2348 .put = snd_cs46xx_spdif_stream_put
2349},
2350
1da177e4
LT		 2351#endif
2352};
2353
2354#ifdef CONFIG_SND_CS46XX_NEW_DSP
2355/* set primary cs4294 codec into Extended Audio Mode */
3d19f804
TI		 2356static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2357 struct snd_ctl_elem_value *ucontrol)
1da177e4 2358{
3d19f804 2359 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2360 unsigned short val;
2361 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2362 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2363 return 0;
2364}
2365
3d19f804
TI		 2366static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2367 struct snd_ctl_elem_value *ucontrol)
1da177e4 2368{
3d19f804 2369 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2370 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2371 AC97_CSR_ACMODE, 0x200,
2372 ucontrol->value.integer.value[0] ? 0 : 0x200);
2373}
2374
3d19f804 2375static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
1da177e4
LT		 2376 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2377 .name = "Duplicate Front",
2378 .info = snd_mixer_boolean_info,
2379 .get = snd_cs46xx_front_dup_get,
2380 .put = snd_cs46xx_front_dup_put,
2381};
2382#endif
2383
2384#ifdef CONFIG_SND_CS46XX_NEW_DSP
2385/* Only available on the Hercules Game Theater XP soundcard */
f40b6890 2386static struct snd_kcontrol_new snd_hercules_controls[] = {
1da177e4
LT		 2387{
2388 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2389 .name = "Optical/Coaxial SPDIF Input Switch",
2390 .info = snd_mixer_boolean_info,
2391 .get = snd_herc_spdif_select_get,
2392 .put = snd_herc_spdif_select_put,
2393},
2394};
2395
2396
3d19f804 2397static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
1da177e4
LT		 2398{
2399 unsigned long end_time;
2400 int err;
2401
2402 /* reset to defaults */
2403 snd_ac97_write(ac97, AC97_RESET, 0);
2404
2405 /* set the desired CODEC mode */
2406 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2b96a7f1 2407 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
04510a74 2408 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
1da177e4 2409 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2b96a7f1 2410 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
04510a74 2411 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
1da177e4 2412 } else {
da3cec35 2413 snd_BUG(); /* should never happen ... */
1da177e4
LT		 2414 }
2415
2416 udelay(50);
2417
2418 /* it's necessary to wait awhile until registers are accessible after RESET */
2419 /* because the PCM or MASTER volume registers can be modified, */
2420 /* the REC_GAIN register is used for tests */
2421 end_time = jiffies + HZ;
2422 do {
2423 unsigned short ext_mid;
2424
2425 /* use preliminary reads to settle the communication */
2426 snd_ac97_read(ac97, AC97_RESET);
2427 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2428 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2429 /* modem? */
2430 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2431 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2432 return;
2433
2434 /* test if we can write to the record gain volume register */
7fb2d723 2435 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
1da177e4
LT		 2436 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2437 return;
2438
ef21ca24 2439 msleep(10);
1da177e4
LT		 2440 } while (time_after_eq(end_time, jiffies));
2441
2b96a7f1
TI		 2442 dev_err(ac97->bus->card->dev,
2443 "CS46xx secondary codec doesn't respond!\n");
1da177e4
LT		 2444}
2445#endif
2446
e23e7a14 2447static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
1da177e4
LT		 2448{
2449 int idx, err;
3d19f804 2450 struct snd_ac97_template ac97;
1da177e4
LT		 2451
2452 memset(&ac97, 0, sizeof(ac97));
2453 ac97.private_data = chip;
2454 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2455 ac97.num = codec;
2456 if (chip->amplifier_ctrl == amp_voyetra)
2457 ac97.scaps = AC97_SCAP_INV_EAPD;
2458
2459 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2460 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2461 udelay(10);
2462 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2b96a7f1
TI		 2463 dev_dbg(chip->card->dev,
2464 "seconadry codec not present\n");
1da177e4
LT		 2465 return -ENXIO;
2466 }
2467 }
2468
2469 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2470 for (idx = 0; idx < 100; ++idx) {
2471 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2472 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2473 return err;
2474 }
ef21ca24 2475 msleep(10);
1da177e4 2476 }
2b96a7f1 2477 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
1da177e4
LT		 2478 return -ENXIO;
2479}
2480
e23e7a14 2481int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
1da177e4 2482{
3d19f804
TI		 2483 struct snd_card *card = chip->card;
2484 struct snd_ctl_elem_id id;
1da177e4
LT		 2485 int err;
2486 unsigned int idx;
3d19f804 2487 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 2488#ifdef CONFIG_SND_CS46XX_NEW_DSP
2489 .reset = snd_cs46xx_codec_reset,
2490#endif
2491 .write = snd_cs46xx_ac97_write,
2492 .read = snd_cs46xx_ac97_read,
2493 };
2494
2495 /* detect primary codec */
2496 chip->nr_ac97_codecs = 0;
2b96a7f1 2497 dev_dbg(chip->card->dev, "detecting primary codec\n");
1da177e4
LT		 2498 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2499 return err;
2500 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2501
2502 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2503 return -ENXIO;
2504 chip->nr_ac97_codecs = 1;
2505
2506#ifdef CONFIG_SND_CS46XX_NEW_DSP
2b96a7f1 2507 dev_dbg(chip->card->dev, "detecting seconadry codec\n");
1da177e4
LT		 2508 /* try detect a secondary codec */
2509 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2510 chip->nr_ac97_codecs = 2;
2511#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2512
2513 /* add cs4630 mixer controls */
2514 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
3d19f804 2515 struct snd_kcontrol *kctl;
1da177e4 2516 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
67ed4161
CL		 2517 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2518 kctl->id.device = spdif_device;
1da177e4
LT		 2519 if ((err = snd_ctl_add(card, kctl)) < 0)
2520 return err;
2521 }
2522
2523 /* get EAPD mixer switch (for voyetra hack) */
2524 memset(&id, 0, sizeof(id));
2525 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2526 strcpy(id.name, "External Amplifier");
2527 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2528
2529#ifdef CONFIG_SND_CS46XX_NEW_DSP
2530 if (chip->nr_ac97_codecs == 1) {
2531 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2532 if (id2 == 0x592b || id2 == 0x592d) {
2533 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2534 if (err < 0)
2535 return err;
2536 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2537 AC97_CSR_ACMODE, 0x200);
2538 }
2539 }
2540 /* do soundcard specific mixer setup */
2541 if (chip->mixer_init) {
2b96a7f1 2542 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
1da177e4
LT		 2543 chip->mixer_init(chip);
2544 }
2545#endif
2546
2547 /* turn on amplifier */
2548 chip->amplifier_ctrl(chip, 1);
2549
2550 return 0;
2551}
2552
2553/*
2554 * RawMIDI interface
2555 */
2556
3d19f804 2557static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
1da177e4
LT		 2558{
2559 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2560 udelay(100);
2561 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2562}
2563
3d19f804 2564static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2565{
3d19f804 2566 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2567
2568 chip->active_ctrl(chip, 1);
2569 spin_lock_irq(&chip->reg_lock);
2570 chip->uartm |= CS46XX_MODE_INPUT;
2571 chip->midcr |= MIDCR_RXE;
2572 chip->midi_input = substream;
2573 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2574 snd_cs46xx_midi_reset(chip);
2575 } else {
2576 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2577 }
2578 spin_unlock_irq(&chip->reg_lock);
2579 return 0;
2580}
2581
3d19f804 2582static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2583{
3d19f804 2584 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2585
2586 spin_lock_irq(&chip->reg_lock);
2587 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2588 chip->midi_input = NULL;
2589 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2590 snd_cs46xx_midi_reset(chip);
2591 } else {
2592 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2593 }
2594 chip->uartm &= ~CS46XX_MODE_INPUT;
2595 spin_unlock_irq(&chip->reg_lock);
2596 chip->active_ctrl(chip, -1);
2597 return 0;
2598}
2599
3d19f804 2600static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2601{
3d19f804 2602 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2603
2604 chip->active_ctrl(chip, 1);
2605
2606 spin_lock_irq(&chip->reg_lock);
2607 chip->uartm |= CS46XX_MODE_OUTPUT;
2608 chip->midcr |= MIDCR_TXE;
2609 chip->midi_output = substream;
2610 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2611 snd_cs46xx_midi_reset(chip);
2612 } else {
2613 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2614 }
2615 spin_unlock_irq(&chip->reg_lock);
2616 return 0;
2617}
2618
3d19f804 2619static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2620{
3d19f804 2621 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2622
2623 spin_lock_irq(&chip->reg_lock);
2624 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2625 chip->midi_output = NULL;
2626 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2627 snd_cs46xx_midi_reset(chip);
2628 } else {
2629 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2630 }
2631 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2632 spin_unlock_irq(&chip->reg_lock);
2633 chip->active_ctrl(chip, -1);
2634 return 0;
2635}
2636
3d19f804 2637static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2638{
2639 unsigned long flags;
3d19f804 2640 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2641
2642 spin_lock_irqsave(&chip->reg_lock, flags);
2643 if (up) {
2644 if ((chip->midcr & MIDCR_RIE) == 0) {
2645 chip->midcr |= MIDCR_RIE;
2646 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2647 }
2648 } else {
2649 if (chip->midcr & MIDCR_RIE) {
2650 chip->midcr &= ~MIDCR_RIE;
2651 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2652 }
2653 }
2654 spin_unlock_irqrestore(&chip->reg_lock, flags);
2655}
2656
3d19f804 2657static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2658{
2659 unsigned long flags;
3d19f804 2660 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2661 unsigned char byte;
2662
2663 spin_lock_irqsave(&chip->reg_lock, flags);
2664 if (up) {
2665 if ((chip->midcr & MIDCR_TIE) == 0) {
2666 chip->midcr |= MIDCR_TIE;
2667 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2668 while ((chip->midcr & MIDCR_TIE) &&
2669 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2670 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2671 chip->midcr &= ~MIDCR_TIE;
2672 } else {
2673 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2674 }
2675 }
2676 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2677 }
2678 } else {
2679 if (chip->midcr & MIDCR_TIE) {
2680 chip->midcr &= ~MIDCR_TIE;
2681 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2682 }
2683 }
2684 spin_unlock_irqrestore(&chip->reg_lock, flags);
2685}
2686
3d19f804 2687static struct snd_rawmidi_ops snd_cs46xx_midi_output =
1da177e4
LT		 2688{
2689 .open = snd_cs46xx_midi_output_open,
2690 .close = snd_cs46xx_midi_output_close,
2691 .trigger = snd_cs46xx_midi_output_trigger,
2692};
2693
3d19f804 2694static struct snd_rawmidi_ops snd_cs46xx_midi_input =
1da177e4
LT		 2695{
2696 .open = snd_cs46xx_midi_input_open,
2697 .close = snd_cs46xx_midi_input_close,
2698 .trigger = snd_cs46xx_midi_input_trigger,
2699};
2700
72134c4d 2701int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
1da177e4 2702{
3d19f804 2703 struct snd_rawmidi *rmidi;
1da177e4
LT		 2704 int err;
2705
1da177e4
LT		 2706 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2707 return err;
2708 strcpy(rmidi->name, "CS46XX");
2709 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2710 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2711 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2712 rmidi->private_data = chip;
2713 chip->rmidi = rmidi;
1da177e4
LT		 2714 return 0;
2715}
2716
2717
2718/*
2719 * gameport interface
2720 */
2721
2722#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2723
2724static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2725{
3d19f804 2726 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4 2727
da3cec35
TI		 2728 if (snd_BUG_ON(!chip))
2729 return;
1da177e4
LT		 2730 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2731}
2732
2733static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2734{
3d19f804 2735 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4 2736
da3cec35
TI		 2737 if (snd_BUG_ON(!chip))
2738 return 0;
1da177e4
LT		 2739 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2740}
2741
2742static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2743{
3d19f804 2744 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2745 unsigned js1, js2, jst;
2746
da3cec35
TI		 2747 if (snd_BUG_ON(!chip))
2748 return 0;
1da177e4
LT		 2749
2750 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2751 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2752 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2753
2754 *buttons = (~jst >> 4) & 0x0F;
2755
2756 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2757 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2758 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2759 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2760
2761 for(jst=0;jst<4;++jst)
2762 if(axes[jst]==0xFFFF) axes[jst] = -1;
2763 return 0;
2764}
2765
2766static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2767{
2768 switch (mode) {
2769 case GAMEPORT_MODE_COOKED:
2770 return 0;
2771 case GAMEPORT_MODE_RAW:
2772 return 0;
2773 default:
2774 return -1;
2775 }
2776 return 0;
2777}
2778
e23e7a14 2779int snd_cs46xx_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2780{
2781 struct gameport *gp;
2782
2783 chip->gameport = gp = gameport_allocate_port();
2784 if (!gp) {
2b96a7f1
TI		 2785 dev_err(chip->card->dev,
2786 "cannot allocate memory for gameport\n");
1da177e4
LT		 2787 return -ENOMEM;
2788 }
2789
2790 gameport_set_name(gp, "CS46xx Gameport");
2791 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2792 gameport_set_dev_parent(gp, &chip->pci->dev);
2793 gameport_set_port_data(gp, chip);
2794
2795 gp->open = snd_cs46xx_gameport_open;
2796 gp->read = snd_cs46xx_gameport_read;
2797 gp->trigger = snd_cs46xx_gameport_trigger;
2798 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2799
2800 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2801 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2802
2803 gameport_register_port(gp);
2804
2805 return 0;
2806}
2807
3d19f804 2808static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2809{
2810 if (chip->gameport) {
2811 gameport_unregister_port(chip->gameport);
2812 chip->gameport = NULL;
2813 }
2814}
2815#else
e23e7a14 2816int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
3d19f804 2817static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
1da177e4
LT		 2818#endif /* CONFIG_GAMEPORT */
2819
adf1b3d2 2820#ifdef CONFIG_PROC_FS
1da177e4
LT		 2821/*
2822 * proc interface
2823 */
2824
24e4a121
TI		 2825static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2826 void *file_private_data,
2827 struct file *file, char __user *buf,
2828 size_t count, loff_t pos)
1da177e4 2829{
3d19f804 2830 struct snd_cs46xx_region *region = entry->private_data;
1da177e4 2831
d97e1b78
TI		 2832 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2833 return -EFAULT;
2834 return count;
1da177e4
LT		 2835}
2836
2837static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2838 .read = snd_cs46xx_io_read,
2839};
2840
e23e7a14 2841static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
1da177e4 2842{
3d19f804 2843 struct snd_info_entry *entry;
1da177e4
LT		 2844 int idx;
2845
2846 for (idx = 0; idx < 5; idx++) {
3d19f804 2847 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2848 if (! snd_card_proc_new(card, region->name, &entry)) {
2849 entry->content = SNDRV_INFO_CONTENT_DATA;
2850 entry->private_data = chip;
2851 entry->c.ops = &snd_cs46xx_proc_io_ops;
2852 entry->size = region->size;
2853 entry->mode = S_IFREG | S_IRUSR;
2854 }
2855 }
2856#ifdef CONFIG_SND_CS46XX_NEW_DSP
2857 cs46xx_dsp_proc_init(card, chip);
2858#endif
2859 return 0;
2860}
2861
3d19f804 2862static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
1da177e4
LT		 2863{
2864#ifdef CONFIG_SND_CS46XX_NEW_DSP
2865 cs46xx_dsp_proc_done(chip);
2866#endif
2867 return 0;
2868}
adf1b3d2
TI		 2869#else /* !CONFIG_PROC_FS */
2870#define snd_cs46xx_proc_init(card, chip)
2871#define snd_cs46xx_proc_done(chip)
2872#endif
1da177e4
LT		 2873
2874/*
2875 * stop the h/w
2876 */
3d19f804 2877static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
1da177e4
LT		 2878{
2879 unsigned int tmp;
2880
2881 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2882 tmp &= ~0x0000f03f;
2883 tmp |= 0x00000010;
2884 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2885
2886 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2887 tmp &= ~0x0000003f;
2888 tmp |= 0x00000011;
2889 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2890
2891 /*
2892 * Stop playback DMA.
2893 */
2894 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2895 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2896
2897 /*
2898 * Stop capture DMA.
2899 */
2900 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2901 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2902
2903 /*
2904 * Reset the processor.
2905 */
2906 snd_cs46xx_reset(chip);
2907
2908 snd_cs46xx_proc_stop(chip);
2909
2910 /*
2911 * Power down the PLL.
2912 */
2913 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2914
2915 /*
2916 * Turn off the Processor by turning off the software clock enable flag in
2917 * the clock control register.
2918 */
2919 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2920 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2921}
2922
2923
3d19f804 2924static int snd_cs46xx_free(struct snd_cs46xx *chip)
1da177e4
LT		 2925{
2926 int idx;
2927
da3cec35
TI		 2928 if (snd_BUG_ON(!chip))
2929 return -EINVAL;
1da177e4
LT		 2930
2931 if (chip->active_ctrl)
2932 chip->active_ctrl(chip, 1);
2933
2934 snd_cs46xx_remove_gameport(chip);
2935
2936 if (chip->amplifier_ctrl)
2937 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2938
2939 snd_cs46xx_proc_done(chip);
2940
2941 if (chip->region.idx[0].resource)
2942 snd_cs46xx_hw_stop(chip);
2943
0a50d2b2
TI		 2944 if (chip->irq >= 0)
2945 free_irq(chip->irq, chip);
2946
ebf029da
TI		 2947 if (chip->active_ctrl)
2948 chip->active_ctrl(chip, -chip->amplifier);
2949
1da177e4 2950 for (idx = 0; idx < 5; idx++) {
3d19f804 2951 struct snd_cs46xx_region *region = &chip->region.idx[idx];
ff6defa6
ME		 2952
2953 iounmap(region->remap_addr);
b1d5776d 2954 release_and_free_resource(region->resource);
1da177e4 2955 }
1da177e4 2956
1da177e4
LT		 2957#ifdef CONFIG_SND_CS46XX_NEW_DSP
2958 if (chip->dsp_spos_instance) {
2959 cs46xx_dsp_spos_destroy(chip);
2960 chip->dsp_spos_instance = NULL;
2961 }
ad233a5f
TI		 2962 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2963 free_module_desc(chip->modules[idx]);
2964#else
2965 vfree(chip->ba1);
1da177e4
LT		 2966#endif
2967
c7561cd8 2968#ifdef CONFIG_PM_SLEEP
89f157d9
TI		 2969 kfree(chip->saved_regs);
2970#endif
2971
1da177e4
LT		 2972 pci_disable_device(chip->pci);
2973 kfree(chip);
2974 return 0;
2975}
2976
3d19f804 2977static int snd_cs46xx_dev_free(struct snd_device *device)
1da177e4 2978{
3d19f804 2979 struct snd_cs46xx *chip = device->device_data;
1da177e4
LT		 2980 return snd_cs46xx_free(chip);
2981}
2982
2983/*
2984 * initialize chip
2985 */
3d19f804 2986static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
1da177e4
LT		 2987{
2988 int timeout;
2989
2990 /*
2991 * First, blast the clock control register to zero so that the PLL starts
2992 * out in a known state, and blast the master serial port control register
2993 * to zero so that the serial ports also start out in a known state.
2994 */
2995 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2996 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2997
2998 /*
2999 * If we are in AC97 mode, then we must set the part to a host controlled
3000 * AC-link. Otherwise, we won't be able to bring up the link.
3001 */
3002#ifdef CONFIG_SND_CS46XX_NEW_DSP
3003 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
3004 SERACC_TWO_CODECS); /* 2.00 dual codecs */
3005 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3006#else
3007 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3008#endif
3009
3010 /*
3011 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3012 * spec) and then drive it high. This is done for non AC97 modes since
3013 * there might be logic external to the CS461x that uses the ARST# line
3014 * for a reset.
3015 */
3016 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3017#ifdef CONFIG_SND_CS46XX_NEW_DSP
3018 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3019#endif
3020 udelay(50);
3021 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3022#ifdef CONFIG_SND_CS46XX_NEW_DSP
3023 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3024#endif
3025
3026 /*
3027 * The first thing we do here is to enable sync generation. As soon
3028 * as we start receiving bit clock, we'll start producing the SYNC
3029 * signal.
3030 */
3031 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3032#ifdef CONFIG_SND_CS46XX_NEW_DSP
3033 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3034#endif
3035
3036 /*
3037 * Now wait for a short while to allow the AC97 part to start
3038 * generating bit clock (so we don't try to start the PLL without an
3039 * input clock).
3040 */
3041 mdelay(10);
3042
3043 /*
3044 * Set the serial port timing configuration, so that
3045 * the clock control circuit gets its clock from the correct place.
3046 */
3047 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3048
3049 /*
3050 * Write the selected clock control setup to the hardware. Do not turn on
3051 * SWCE yet (if requested), so that the devices clocked by the output of
3052 * PLL are not clocked until the PLL is stable.
3053 */
3054 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3055 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3056 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3057
3058 /*
3059 * Power up the PLL.
3060 */
3061 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3062
3063 /*
3064 * Wait until the PLL has stabilized.
3065 */
ef21ca24 3066 msleep(100);
1da177e4
LT		 3067
3068 /*
3069 * Turn on clocking of the core so that we can setup the serial ports.
3070 */
3071 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3072
3073 /*
3074 * Enable FIFO Host Bypass
3075 */
3076 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3077
3078 /*
3079 * Fill the serial port FIFOs with silence.
3080 */
3081 snd_cs46xx_clear_serial_FIFOs(chip);
3082
3083 /*
3084 * Set the serial port FIFO pointer to the first sample in the FIFO.
3085 */
3086 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3087
3088 /*
3089 * Write the serial port configuration to the part. The master
3090 * enable bit is not set until all other values have been written.
3091 */
3092 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3093 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3094 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3095
3096
3097#ifdef CONFIG_SND_CS46XX_NEW_DSP
3098 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3099 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3100 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3101 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3102 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3103#endif
3104
3105 mdelay(5);
3106
3107
3108 /*
3109 * Wait for the codec ready signal from the AC97 codec.
3110 */
3111 timeout = 150;
3112 while (timeout-- > 0) {
3113 /*
3114 * Read the AC97 status register to see if we've seen a CODEC READY
3115 * signal from the AC97 codec.
3116 */
3117 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3118 goto ok1;
ef21ca24 3119 msleep(10);
1da177e4
LT		 3120 }
3121
3122
2b96a7f1
TI		 3123 dev_err(chip->card->dev,
3124 "create - never read codec ready from AC'97\n");
3125 dev_err(chip->card->dev,
3126 "it is not probably bug, try to use CS4236 driver\n");
1da177e4
LT		 3127 return -EIO;
3128 ok1:
3129#ifdef CONFIG_SND_CS46XX_NEW_DSP
3130 {
3131 int count;
3132 for (count = 0; count < 150; count++) {
3133 /* First, we want to wait for a short time. */
3134 udelay(25);
3135
3136 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3137 break;
3138 }
3139
3140 /*
3141 * Make sure CODEC is READY.
3142 */
3143 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
2b96a7f1
TI		 3144 dev_dbg(chip->card->dev,
3145 "never read card ready from secondary AC'97\n");
1da177e4
LT		 3146 }
3147#endif
3148
3149 /*
3150 * Assert the vaid frame signal so that we can start sending commands
3151 * to the AC97 codec.
3152 */
3153 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3154#ifdef CONFIG_SND_CS46XX_NEW_DSP
3155 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3156#endif
3157
3158
3159 /*
3160 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3161 * the codec is pumping ADC data across the AC-link.
3162 */
3163 timeout = 150;
3164 while (timeout-- > 0) {
3165 /*
3166 * Read the input slot valid register and see if input slots 3 and
3167 * 4 are valid yet.
3168 */
3169 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3170 goto ok2;
ef21ca24 3171 msleep(10);
1da177e4
LT		 3172 }
3173
3174#ifndef CONFIG_SND_CS46XX_NEW_DSP
2b96a7f1
TI		 3175 dev_err(chip->card->dev,
3176 "create - never read ISV3 & ISV4 from AC'97\n");
1da177e4
LT		 3177 return -EIO;
3178#else
3179 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3180 Reloading the driver may help, if there's other soundcards
3181 with the same problem I would like to know. (Benny) */
3182
2b96a7f1
TI		 3183 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3184 dev_err(chip->card->dev,
3185 "Try reloading the ALSA driver, if you find something\n");
3186 dev_err(chip->card->dev,
3187 "broken or not working on your soundcard upon\n");
3188 dev_err(chip->card->dev,
3189 "this message please report to alsa-devel@alsa-project.org\n");
1da177e4
LT		 3190
3191 return -EIO;
3192#endif
3193 ok2:
3194
3195 /*
3196 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3197 * commense the transfer of digital audio data to the AC97 codec.
3198 */
3199
3200 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3201
3202
3203 /*
3204 * Power down the DAC and ADC. We will power them up (if) when we need
3205 * them.
3206 */
3207 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3208
3209 /*
3210 * Turn off the Processor by turning off the software clock enable flag in
3211 * the clock control register.
3212 */
3213 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3214 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3215
3216 return 0;
3217}
3218
3219/*
3220 * start and load DSP
3221 */
89f157d9
TI		 3222
3223static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3224{
3225 unsigned int tmp;
3226
3227 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3228
3229 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3230 tmp &= ~0x0000f03f;
3231 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3232
3233 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3234 tmp &= ~0x0000003f;
3235 tmp |= 0x00000001;
3236 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3237}
3238
e23e7a14 3239int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
1da177e4
LT		 3240{
3241 unsigned int tmp;
ad233a5f
TI		 3242#ifdef CONFIG_SND_CS46XX_NEW_DSP
3243 int i;
3244#endif
3245 int err;
3246
1da177e4
LT		 3247 /*
3248 * Reset the processor.
3249 */
3250 snd_cs46xx_reset(chip);
3251 /*
3252 * Download the image to the processor.
3253 */
3254#ifdef CONFIG_SND_CS46XX_NEW_DSP
ad233a5f
TI		 3255 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3256 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3257 if (err < 0) {
2b96a7f1 3258 dev_err(chip->card->dev, "firmware load error [%s]\n",
ad233a5f
TI		 3259 module_names[i]);
3260 return err;
3261 }
3262 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3263 if (err < 0) {
2b96a7f1 3264 dev_err(chip->card->dev, "image download error [%s]\n",
ad233a5f
TI		 3265 module_names[i]);
3266 return err;
3267 }
1da177e4
LT		 3268 }
3269
3270 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3271 return -EIO;
3272#else
ad233a5f
TI		 3273 err = load_firmware(chip);
3274 if (err < 0)
3275 return err;
3276
1da177e4 3277 /* old image */
ad233a5f
TI		 3278 err = snd_cs46xx_download_image(chip);
3279 if (err < 0) {
2b96a7f1 3280 dev_err(chip->card->dev, "image download error\n");
ad233a5f 3281 return err;
1da177e4
LT		 3282 }
3283
3284 /*
3285 * Stop playback DMA.
3286 */
3287 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3288 chip->play_ctl = tmp & 0xffff0000;
3289 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3290#endif
3291
3292 /*
3293 * Stop capture DMA.
3294 */
3295 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3296 chip->capt.ctl = tmp & 0x0000ffff;
3297 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3298
3299 mdelay(5);
3300
3301 snd_cs46xx_set_play_sample_rate(chip, 8000);
3302 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3303
3304 snd_cs46xx_proc_start(chip);
3305
89f157d9 3306 cs46xx_enable_stream_irqs(chip);
1da177e4
LT		 3307
3308#ifndef CONFIG_SND_CS46XX_NEW_DSP
3309 /* set the attenuation to 0dB */
3310 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3311 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3312#endif
3313
3314 return 0;
3315}
3316
3317
3318/*
3319 * AMP control - null AMP
3320 */
3321
3d19f804 3322static void amp_none(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3323{
3324}
3325
3326#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 3327static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
1da177e4
LT		 3328{
3329
3330 u32 idx, valid_slots,tmp,powerdown = 0;
3331 u16 modem_power,pin_config,logic_type;
3332
2b96a7f1 3333 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
1da177e4
LT		 3334
3335 /*
3336 * See if the devices are powered down. If so, we must power them up first
3337 * or they will not respond.
3338 */
3339 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3340
3341 if (!(tmp & CLKCR1_SWCE)) {
3342 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3343 powerdown = 1;
3344 }
3345
3346 /*
3347 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3348 * stuff.
3349 */
3350 if(chip->nr_ac97_codecs != 2) {
2b96a7f1
TI		 3351 dev_err(chip->card->dev,
3352 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
1da177e4
LT		 3353 return -EINVAL;
3354 }
3355
3356 modem_power = snd_cs46xx_codec_read (chip,
3357 AC97_EXTENDED_MSTATUS,
3358 CS46XX_SECONDARY_CODEC_INDEX);
3359 modem_power &=0xFEFF;
3360
3361 snd_cs46xx_codec_write(chip,
3362 AC97_EXTENDED_MSTATUS, modem_power,
3363 CS46XX_SECONDARY_CODEC_INDEX);
3364
3365 /*
3366 * Set GPIO pin's 7 and 8 so that they are configured for output.
3367 */
3368 pin_config = snd_cs46xx_codec_read (chip,
3369 AC97_GPIO_CFG,
3370 CS46XX_SECONDARY_CODEC_INDEX);
3371 pin_config &=0x27F;
3372
3373 snd_cs46xx_codec_write(chip,
3374 AC97_GPIO_CFG, pin_config,
3375 CS46XX_SECONDARY_CODEC_INDEX);
3376
3377 /*
3378 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3379 */
3380
3381 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3382 CS46XX_SECONDARY_CODEC_INDEX);
3383 logic_type &=0x27F;
3384
3385 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3386 CS46XX_SECONDARY_CODEC_INDEX);
3387
3388 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3389 valid_slots |= 0x200;
3390 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3391
3392 if ( cs46xx_wait_for_fifo(chip,1) ) {
2b96a7f1 3393 dev_dbg(chip->card->dev, "FIFO is busy\n");
1da177e4
LT		 3394
3395 return -EINVAL;
3396 }
3397
3398 /*
3399 * Fill slots 12 with the correct value for the GPIO pins.
3400 */
3401 for(idx = 0x90; idx <= 0x9F; idx++) {
3402 /*
3403 * Initialize the fifo so that bits 7 and 8 are on.
3404 *
3405 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3406 * the left. 0x1800 corresponds to bits 7 and 8.
3407 */
3408 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3409
3410 /*
3411 * Wait for command to complete
3412 */
3413 if ( cs46xx_wait_for_fifo(chip,200) ) {
2b96a7f1
TI		 3414 dev_dbg(chip->card->dev,
3415 "failed waiting for FIFO at addr (%02X)\n",
3416 idx);
1da177e4
LT		 3417
3418 return -EINVAL;
3419 }
3420
3421 /*
3422 * Write the serial port FIFO index.
3423 */
3424 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3425
3426 /*
3427 * Tell the serial port to load the new value into the FIFO location.
3428 */
3429 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3430 }
3431
3432 /* wait for last command to complete */
3433 cs46xx_wait_for_fifo(chip,200);
3434
3435 /*
3436 * Now, if we powered up the devices, then power them back down again.
3437 * This is kinda ugly, but should never happen.
3438 */
3439 if (powerdown)
3440 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3441
3442 return 0;
3443}
3444#endif
3445
3446/*
3447 * Crystal EAPD mode
3448 */
3449
3d19f804 3450static void amp_voyetra(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3451{
3452 /* Manage the EAPD bit on the Crystal 4297
3453 and the Analog AD1885 */
3454
3455#ifdef CONFIG_SND_CS46XX_NEW_DSP
3456 int old = chip->amplifier;
3457#endif
3458 int oval, val;
3459
3460 chip->amplifier += change;
3461 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3462 CS46XX_PRIMARY_CODEC_INDEX);
3463 val = oval;
3464 if (chip->amplifier) {
3465 /* Turn the EAPD amp on */
3466 val |= 0x8000;
3467 } else {
3468 /* Turn the EAPD amp off */
3469 val &= ~0x8000;
3470 }
3471 if (val != oval) {
3472 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3473 CS46XX_PRIMARY_CODEC_INDEX);
3474 if (chip->eapd_switch)
3475 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3476 &chip->eapd_switch->id);
3477 }
3478
3479#ifdef CONFIG_SND_CS46XX_NEW_DSP
3480 if (chip->amplifier && !old) {
3481 voyetra_setup_eapd_slot(chip);
3482 }
3483#endif
3484}
3485
3d19f804 3486static void hercules_init(struct snd_cs46xx *chip)
1da177e4
LT		 3487{
3488 /* default: AMP off, and SPDIF input optical */
3489 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3490 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3491}
3492
3493
3494/*
3495 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3496 */
3d19f804 3497static void amp_hercules(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3498{
3499 int old = chip->amplifier;
3500 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3501 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3502
3503 chip->amplifier += change;
3504 if (chip->amplifier && !old) {
2b96a7f1 3505 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
1da177e4
LT		 3506
3507 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3508 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3509 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3510 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3511 } else if (old && !chip->amplifier) {
2b96a7f1 3512 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
1da177e4
LT		 3513 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3514 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3515 }
3516}
3517
3d19f804 3518static void voyetra_mixer_init (struct snd_cs46xx *chip)
1da177e4 3519{
2b96a7f1 3520 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
1da177e4
LT		 3521
3522 /* Enable SPDIF out */
3523 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3524 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3525}
3526
3d19f804 3527static void hercules_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3528{
3529#ifdef CONFIG_SND_CS46XX_NEW_DSP
3530 unsigned int idx;
3531 int err;
3d19f804 3532 struct snd_card *card = chip->card;
1da177e4
LT		 3533#endif
3534
3535 /* set EGPIO to default */
3536 hercules_init(chip);
3537
2b96a7f1 3538 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
1da177e4
LT		 3539
3540#ifdef CONFIG_SND_CS46XX_NEW_DSP
f40b6890
TI		 3541 if (chip->in_suspend)
3542 return;
3543
1da177e4 3544 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3d19f804 3545 struct snd_kcontrol *kctl;
1da177e4
LT		 3546
3547 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3548 if ((err = snd_ctl_add(card, kctl)) < 0) {
2b96a7f1
TI		 3549 dev_err(card->dev,
3550 "failed to initialize Hercules mixer (%d)\n",
3551 err);
1da177e4
LT		 3552 break;
3553 }
3554 }
3555#endif
3556}
3557
3558
3559#if 0
3560/*
3561 * Untested
3562 */
3563
3d19f804 3564static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3565{
3566 chip->amplifier += change;
3567
3568 if (chip->amplifier) {
3569 /* Switch the GPIO pins 7 and 8 to open drain */
3570 snd_cs46xx_codec_write(chip, 0x4C,
3571 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3572 snd_cs46xx_codec_write(chip, 0x4E,
3573 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3574 /* Now wake the AMP (this might be backwards) */
3575 snd_cs46xx_codec_write(chip, 0x54,
3576 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3577 } else {
3578 snd_cs46xx_codec_write(chip, 0x54,
3579 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3580 }
3581}
3582#endif
3583
3584
1da177e4
LT		 3585/*
3586 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3587 * whenever we need to beat on the chip.
3588 *
3589 * The original idea and code for this hack comes from David Kaiser at
3590 * Linuxcare. Perhaps one day Crystal will document their chips well
3591 * enough to make them useful.
3592 */
3593
3d19f804 3594static void clkrun_hack(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3595{
3596 u16 control, nval;
3597
0dd119f7 3598 if (!chip->acpi_port)
1da177e4
LT		 3599 return;
3600
3601 chip->amplifier += change;
3602
3603 /* Read ACPI port */
3604 nval = control = inw(chip->acpi_port + 0x10);
3605
3606 /* Flip CLKRUN off while running */
3607 if (! chip->amplifier)
3608 nval |= 0x2000;
3609 else
3610 nval &= ~0x2000;
3611 if (nval != control)
3612 outw(nval, chip->acpi_port + 0x10);
3613}
3614
3615
3616/*
3617 * detect intel piix4
3618 */
3d19f804 3619static void clkrun_init(struct snd_cs46xx *chip)
1da177e4 3620{
0dd119f7 3621 struct pci_dev *pdev;
1da177e4
LT		 3622 u8 pp;
3623
0dd119f7
JS		 3624 chip->acpi_port = 0;
3625
3626 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3627 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3628 if (pdev == NULL)
1da177e4
LT		 3629 return; /* Not a thinkpad thats for sure */
3630
3631 /* Find the control port */
0dd119f7 3632 pci_read_config_byte(pdev, 0x41, &pp);
1da177e4 3633 chip->acpi_port = pp << 8;
0dd119f7 3634 pci_dev_put(pdev);
1da177e4
LT		 3635}
3636
3637
3638/*
3639 * Card subid table
3640 */
3641
3642struct cs_card_type
3643{
3644 u16 vendor;
3645 u16 id;
3646 char *name;
3d19f804
TI		 3647 void (*init)(struct snd_cs46xx *);
3648 void (*amp)(struct snd_cs46xx *, int);
3649 void (*active)(struct snd_cs46xx *, int);
3650 void (*mixer_init)(struct snd_cs46xx *);
1da177e4
LT		 3651};
3652
e23e7a14 3653static struct cs_card_type cards[] = {
1da177e4
LT		 3654 {
3655 .vendor = 0x1489,
3656 .id = 0x7001,
3657 .name = "Genius Soundmaker 128 value",
3658 /* nothing special */
3659 },
3660 {
3661 .vendor = 0x5053,
3662 .id = 0x3357,
3663 .name = "Voyetra",
3664 .amp = amp_voyetra,
3665 .mixer_init = voyetra_mixer_init,
3666 },
3667 {
3668 .vendor = 0x1071,
3669 .id = 0x6003,
3670 .name = "Mitac MI6020/21",
3671 .amp = amp_voyetra,
3672 },
b636a1d9 3673 /* Hercules Game Theatre XP */
1da177e4 3674 {
b636a1d9 3675 .vendor = 0x14af, /* Guillemot Corporation */
1da177e4
LT		 3676 .id = 0x0050,
3677 .name = "Hercules Game Theatre XP",
3678 .amp = amp_hercules,
3679 .mixer_init = hercules_mixer_init,
3680 },
3681 {
3682 .vendor = 0x1681,
3683 .id = 0x0050,
3684 .name = "Hercules Game Theatre XP",
3685 .amp = amp_hercules,
3686 .mixer_init = hercules_mixer_init,
3687 },
3688 {
3689 .vendor = 0x1681,
3690 .id = 0x0051,
3691 .name = "Hercules Game Theatre XP",
3692 .amp = amp_hercules,
3693 .mixer_init = hercules_mixer_init,
3694
3695 },
3696 {
3697 .vendor = 0x1681,
3698 .id = 0x0052,
3699 .name = "Hercules Game Theatre XP",
3700 .amp = amp_hercules,
3701 .mixer_init = hercules_mixer_init,
3702 },
3703 {
3704 .vendor = 0x1681,
3705 .id = 0x0053,
3706 .name = "Hercules Game Theatre XP",
3707 .amp = amp_hercules,
3708 .mixer_init = hercules_mixer_init,
3709 },
3710 {
3711 .vendor = 0x1681,
3712 .id = 0x0054,
3713 .name = "Hercules Game Theatre XP",
3714 .amp = amp_hercules,
3715 .mixer_init = hercules_mixer_init,
3716 },
b636a1d9
VM		 3717 /* Herculess Fortissimo */
3718 {
3719 .vendor = 0x1681,
3720 .id = 0xa010,
3721 .name = "Hercules Gamesurround Fortissimo II",
3722 },
3723 {
3724 .vendor = 0x1681,
3725 .id = 0xa011,
3726 .name = "Hercules Gamesurround Fortissimo III 7.1",
3727 },
1da177e4 3728 /* Teratec */
b636a1d9
VM		 3729 {
3730 .vendor = 0x153b,
3731 .id = 0x112e,
3732 .name = "Terratec DMX XFire 1024",
3733 },
1da177e4
LT		 3734 {
3735 .vendor = 0x153b,
3736 .id = 0x1136,
3737 .name = "Terratec SiXPack 5.1",
3738 },
3739 /* Not sure if the 570 needs the clkrun hack */
3740 {
3741 .vendor = PCI_VENDOR_ID_IBM,
3742 .id = 0x0132,
3743 .name = "Thinkpad 570",
3744 .init = clkrun_init,
3745 .active = clkrun_hack,
3746 },
3747 {
3748 .vendor = PCI_VENDOR_ID_IBM,
3749 .id = 0x0153,
3750 .name = "Thinkpad 600X/A20/T20",
3751 .init = clkrun_init,
3752 .active = clkrun_hack,
3753 },
3754 {
3755 .vendor = PCI_VENDOR_ID_IBM,
3756 .id = 0x1010,
3757 .name = "Thinkpad 600E (unsupported)",
3758 },
3759 {} /* terminator */
3760};
3761
3762
3763/*
3764 * APM support
3765 */
c7561cd8 3766#ifdef CONFIG_PM_SLEEP
89f157d9
TI		 3767static unsigned int saved_regs[] = {
3768 BA0_ACOSV,
41116e92 3769 /*BA0_ASER_FADDR,*/
89f157d9
TI		 3770 BA0_ASER_MASTER,
3771 BA1_PVOL,
3772 BA1_CVOL,
3773};
3774
68cb2b55 3775static int snd_cs46xx_suspend(struct device *dev)
1da177e4 3776{
68cb2b55
TI		 3777 struct pci_dev *pci = to_pci_dev(dev);
3778 struct snd_card *card = dev_get_drvdata(dev);
cb28e45b 3779 struct snd_cs46xx *chip = card->private_data;
89f157d9 3780 int i, amp_saved;
1da177e4 3781
cb28e45b 3782 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f40b6890 3783 chip->in_suspend = 1;
1da177e4
LT		 3784 snd_pcm_suspend_all(chip->pcm);
3785 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3786 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3787
3788 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3789 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3790
89f157d9
TI		 3791 /* save some registers */
3792 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3793 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3794
1da177e4
LT		 3795 amp_saved = chip->amplifier;
3796 /* turn off amp */
3797 chip->amplifier_ctrl(chip, -chip->amplifier);
3798 snd_cs46xx_hw_stop(chip);
3799 /* disable CLKRUN */
3800 chip->active_ctrl(chip, -chip->amplifier);
3801 chip->amplifier = amp_saved; /* restore the status */
30b35399 3802
cb28e45b
TI		 3803 pci_disable_device(pci);
3804 pci_save_state(pci);
68cb2b55 3805 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 3806 return 0;
3807}
3808
68cb2b55 3809static int snd_cs46xx_resume(struct device *dev)
1da177e4 3810{
68cb2b55
TI		 3811 struct pci_dev *pci = to_pci_dev(dev);
3812 struct snd_card *card = dev_get_drvdata(dev);
cb28e45b 3813 struct snd_cs46xx *chip = card->private_data;
480cf663
TI		 3814 int amp_saved;
3815#ifdef CONFIG_SND_CS46XX_NEW_DSP
3816 int i;
3817#endif
cf944ee5 3818 unsigned int tmp;
1da177e4 3819
30b35399 3820 pci_set_power_state(pci, PCI_D0);
cb28e45b 3821 pci_restore_state(pci);
30b35399 3822 if (pci_enable_device(pci) < 0) {
2b96a7f1 3823 dev_err(dev, "pci_enable_device failed, disabling device\n");
30b35399
TI		 3824 snd_card_disconnect(card);
3825 return -EIO;
3826 }
cb28e45b 3827 pci_set_master(pci);
30b35399 3828
1da177e4
LT		 3829 amp_saved = chip->amplifier;
3830 chip->amplifier = 0;
3831 chip->active_ctrl(chip, 1); /* force to on */
3832
3833 snd_cs46xx_chip_init(chip);
3834
89f157d9
TI		 3835 snd_cs46xx_reset(chip);
3836#ifdef CONFIG_SND_CS46XX_NEW_DSP
3837 cs46xx_dsp_resume(chip);
3838 /* restore some registers */
3839 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3840 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3841#else
3842 snd_cs46xx_download_image(chip);
3843#endif
3844
1da177e4
LT		 3845#if 0
3846 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3847 chip->ac97_general_purpose);
3848 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3849 chip->ac97_powerdown);
3850 mdelay(10);
3851 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3852 chip->ac97_powerdown);
3853 mdelay(5);
3854#endif
3855
3856 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3857 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3858
cf944ee5
FZ		 3859 /*
3860 * Stop capture DMA.
3861 */
3862 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3863 chip->capt.ctl = tmp & 0x0000ffff;
3864 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3865
3866 mdelay(5);
3867
89f157d9
TI		 3868 /* reset playback/capture */
3869 snd_cs46xx_set_play_sample_rate(chip, 8000);
3870 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3871 snd_cs46xx_proc_start(chip);
3872
3873 cs46xx_enable_stream_irqs(chip);
3874
1da177e4
LT		 3875 if (amp_saved)
3876 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3877 else
3878 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3879 chip->amplifier = amp_saved;
f40b6890 3880 chip->in_suspend = 0;
cb28e45b 3881 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 3882 return 0;
3883}
68cb2b55
TI		 3884
3885SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
c7561cd8 3886#endif /* CONFIG_PM_SLEEP */
1da177e4
LT		 3887
3888
3889/*
3890 */
3891
e23e7a14
BP		 3892int snd_cs46xx_create(struct snd_card *card,
3893 struct pci_dev *pci,
1da177e4 3894 int external_amp, int thinkpad,
e23e7a14 3895 struct snd_cs46xx **rchip)
1da177e4 3896{
3d19f804 3897 struct snd_cs46xx *chip;
1da177e4 3898 int err, idx;
3d19f804 3899 struct snd_cs46xx_region *region;
1da177e4
LT		 3900 struct cs_card_type *cp;
3901 u16 ss_card, ss_vendor;
3d19f804 3902 static struct snd_device_ops ops = {
1da177e4
LT		 3903 .dev_free = snd_cs46xx_dev_free,
3904 };
3905
3906 *rchip = NULL;
3907
3908 /* enable PCI device */
3909 if ((err = pci_enable_device(pci)) < 0)
3910 return err;
3911
e560d8d8 3912 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 3913 if (chip == NULL) {
3914 pci_disable_device(pci);
3915 return -ENOMEM;
3916 }
3917 spin_lock_init(&chip->reg_lock);
3918#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 3919 mutex_init(&chip->spos_mutex);
1da177e4
LT		 3920#endif
3921 chip->card = card;
3922 chip->pci = pci;
3923 chip->irq = -1;
3924 chip->ba0_addr = pci_resource_start(pci, 0);
3925 chip->ba1_addr = pci_resource_start(pci, 1);
3926 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3927 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
2b96a7f1
TI		 3928 dev_err(chip->card->dev,
3929 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3d19f804 3930 chip->ba0_addr, chip->ba1_addr);
1da177e4
LT		 3931 snd_cs46xx_free(chip);
3932 return -ENOMEM;
3933 }
3934
3935 region = &chip->region.name.ba0;
3936 strcpy(region->name, "CS46xx_BA0");
3937 region->base = chip->ba0_addr;
3938 region->size = CS46XX_BA0_SIZE;
3939
3940 region = &chip->region.name.data0;
3941 strcpy(region->name, "CS46xx_BA1_data0");
3942 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3943 region->size = CS46XX_BA1_DATA0_SIZE;
3944
3945 region = &chip->region.name.data1;
3946 strcpy(region->name, "CS46xx_BA1_data1");
3947 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3948 region->size = CS46XX_BA1_DATA1_SIZE;
3949
3950 region = &chip->region.name.pmem;
3951 strcpy(region->name, "CS46xx_BA1_pmem");
3952 region->base = chip->ba1_addr + BA1_SP_PMEM;
3953 region->size = CS46XX_BA1_PRG_SIZE;
3954
3955 region = &chip->region.name.reg;
3956 strcpy(region->name, "CS46xx_BA1_reg");
3957 region->base = chip->ba1_addr + BA1_SP_REG;
3958 region->size = CS46XX_BA1_REG_SIZE;
3959
3960 /* set up amp and clkrun hack */
3961 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3962 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3963
3964 for (cp = &cards[0]; cp->name; cp++) {
3965 if (cp->vendor == ss_vendor && cp->id == ss_card) {
2b96a7f1
TI		 3966 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3967 cp->name);
1da177e4
LT		 3968
3969 chip->amplifier_ctrl = cp->amp;
3970 chip->active_ctrl = cp->active;
3971 chip->mixer_init = cp->mixer_init;
3972
3973 if (cp->init)
3974 cp->init(chip);
3975 break;
3976 }
3977 }
3978
3979 if (external_amp) {
2b96a7f1
TI		 3980 dev_info(chip->card->dev,
3981 "Crystal EAPD support forced on.\n");
1da177e4
LT		 3982 chip->amplifier_ctrl = amp_voyetra;
3983 }
3984
3985 if (thinkpad) {
2b96a7f1
TI		 3986 dev_info(chip->card->dev,
3987 "Activating CLKRUN hack for Thinkpad.\n");
1da177e4
LT		 3988 chip->active_ctrl = clkrun_hack;
3989 clkrun_init(chip);
3990 }
3991
3992 if (chip->amplifier_ctrl == NULL)
3993 chip->amplifier_ctrl = amp_none;
3994 if (chip->active_ctrl == NULL)
3995 chip->active_ctrl = amp_none;
3996
3997 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3998
3999 pci_set_master(pci);
4000
4001 for (idx = 0; idx < 5; idx++) {
4002 region = &chip->region.idx[idx];
3d19f804
TI		 4003 if ((region->resource = request_mem_region(region->base, region->size,
4004 region->name)) == NULL) {
2b96a7f1
TI		 4005 dev_err(chip->card->dev,
4006 "unable to request memory region 0x%lx-0x%lx\n",
3d19f804 4007 region->base, region->base + region->size - 1);
1da177e4
LT		 4008 snd_cs46xx_free(chip);
4009 return -EBUSY;
4010 }
4011 region->remap_addr = ioremap_nocache(region->base, region->size);
4012 if (region->remap_addr == NULL) {
2b96a7f1
TI		 4013 dev_err(chip->card->dev,
4014 "%s ioremap problem\n", region->name);
1da177e4
LT		 4015 snd_cs46xx_free(chip);
4016 return -ENOMEM;
4017 }
4018 }
4019
437a5a46 4020 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
934c2b6d 4021 KBUILD_MODNAME, chip)) {
2b96a7f1 4022 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 4023 snd_cs46xx_free(chip);
4024 return -EBUSY;
4025 }
4026 chip->irq = pci->irq;
4027
4028#ifdef CONFIG_SND_CS46XX_NEW_DSP
4029 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4030 if (chip->dsp_spos_instance == NULL) {
4031 snd_cs46xx_free(chip);
4032 return -ENOMEM;
4033 }
4034#endif
4035
4036 err = snd_cs46xx_chip_init(chip);
4037 if (err < 0) {
4038 snd_cs46xx_free(chip);
4039 return err;
4040 }
4041
4042 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4043 snd_cs46xx_free(chip);
4044 return err;
4045 }
4046
4047 snd_cs46xx_proc_init(card, chip);
4048
c7561cd8 4049#ifdef CONFIG_PM_SLEEP
89f157d9
TI		 4050 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) *
4051 ARRAY_SIZE(saved_regs), GFP_KERNEL);
4052 if (!chip->saved_regs) {
4053 snd_cs46xx_free(chip);
4054 return -ENOMEM;
4055 }
4056#endif
4057
1da177e4
LT		 4058 chip->active_ctrl(chip, -1); /* disable CLKRUN */
4059
1da177e4
LT		 4060 *rchip = chip;
4061 return 0;
4062}
Linux kernel - Deliverables
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