Commit | Line | Data |
---|---|---|
05e84878 DR |
1 | /* |
2 | * | |
3 | * Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clocksource.h> | |
24 | #include <linux/delay.h> | |
f0b1df88 | 25 | #include <linux/interrupt.h> |
05e84878 DR |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
154867cf | 28 | #include <linux/pm_runtime.h> |
05e84878 DR |
29 | #include <linux/slab.h> |
30 | #include <sound/core.h> | |
31 | #include <sound/initval.h> | |
05e84878 DR |
32 | #include "hda_controller.h" |
33 | ||
43db4a59 | 34 | #define CREATE_TRACE_POINTS |
18486508 | 35 | #include "hda_controller_trace.h" |
43db4a59 | 36 | |
2b5fd6c2 | 37 | /* DSP lock helpers */ |
7833c3f8 TI |
38 | #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev)) |
39 | #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev)) | |
40 | #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev)) | |
2b5fd6c2 | 41 | |
05e84878 DR |
42 | /* assign a stream for the PCM */ |
43 | static inline struct azx_dev * | |
44 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
45 | { | |
7833c3f8 TI |
46 | struct hdac_stream *s; |
47 | ||
48 | s = snd_hdac_stream_assign(azx_bus(chip), substream); | |
49 | if (!s) | |
50 | return NULL; | |
51 | return stream_to_azx_dev(s); | |
05e84878 DR |
52 | } |
53 | ||
54 | /* release the assigned stream */ | |
55 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
56 | { | |
7833c3f8 | 57 | snd_hdac_stream_release(azx_stream(azx_dev)); |
05e84878 DR |
58 | } |
59 | ||
820cc6cf TI |
60 | static inline struct hda_pcm_stream * |
61 | to_hda_pcm_stream(struct snd_pcm_substream *substream) | |
62 | { | |
63 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
64 | return &apcm->info->stream[substream->stream]; | |
65 | } | |
66 | ||
05e84878 DR |
67 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
68 | u64 nsec) | |
69 | { | |
70 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 71 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
72 | u64 codec_frames, codec_nsecs; |
73 | ||
74 | if (!hinfo->ops.get_delay) | |
75 | return nsec; | |
76 | ||
77 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
78 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
79 | substream->runtime->rate); | |
80 | ||
81 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
82 | return nsec + codec_nsecs; | |
83 | ||
84 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
85 | } | |
86 | ||
05e84878 DR |
87 | /* |
88 | * PCM ops | |
89 | */ | |
90 | ||
91 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
92 | { | |
93 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 94 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
95 | struct azx *chip = apcm->chip; |
96 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
05e84878 | 97 | |
18486508 | 98 | trace_azx_pcm_close(chip, azx_dev); |
05e84878 | 99 | mutex_lock(&chip->open_mutex); |
05e84878 | 100 | azx_release_device(azx_dev); |
61ca4107 TI |
101 | if (hinfo->ops.close) |
102 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
05e84878 DR |
103 | snd_hda_power_down(apcm->codec); |
104 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 105 | snd_hda_codec_pcm_put(apcm->info); |
05e84878 DR |
106 | return 0; |
107 | } | |
108 | ||
109 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | |
110 | struct snd_pcm_hw_params *hw_params) | |
111 | { | |
112 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
113 | struct azx *chip = apcm->chip; | |
602518a2 | 114 | struct azx_dev *azx_dev = get_azx_dev(substream); |
05e84878 DR |
115 | int ret; |
116 | ||
18486508 | 117 | trace_azx_pcm_hw_params(chip, azx_dev); |
602518a2 TI |
118 | dsp_lock(azx_dev); |
119 | if (dsp_is_locked(azx_dev)) { | |
05e84878 DR |
120 | ret = -EBUSY; |
121 | goto unlock; | |
122 | } | |
123 | ||
602518a2 TI |
124 | azx_dev->core.bufsize = 0; |
125 | azx_dev->core.period_bytes = 0; | |
126 | azx_dev->core.format_val = 0; | |
05e84878 DR |
127 | ret = chip->ops->substream_alloc_pages(chip, substream, |
128 | params_buffer_bytes(hw_params)); | |
129 | unlock: | |
602518a2 | 130 | dsp_unlock(azx_dev); |
05e84878 DR |
131 | return ret; |
132 | } | |
133 | ||
134 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
135 | { | |
136 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
137 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
138 | struct azx *chip = apcm->chip; | |
820cc6cf | 139 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
140 | int err; |
141 | ||
142 | /* reset BDL address */ | |
143 | dsp_lock(azx_dev); | |
ccc98865 TI |
144 | if (!dsp_is_locked(azx_dev)) |
145 | snd_hdac_stream_cleanup(azx_stream(azx_dev)); | |
05e84878 DR |
146 | |
147 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | |
148 | ||
149 | err = chip->ops->substream_free_pages(chip, substream); | |
6d23c8f5 | 150 | azx_stream(azx_dev)->prepared = 0; |
05e84878 DR |
151 | dsp_unlock(azx_dev); |
152 | return err; | |
153 | } | |
154 | ||
155 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
156 | { | |
157 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
158 | struct azx *chip = apcm->chip; | |
159 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
820cc6cf | 160 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 | 161 | struct snd_pcm_runtime *runtime = substream->runtime; |
0dd76f36 | 162 | unsigned int format_val, stream_tag; |
05e84878 DR |
163 | int err; |
164 | struct hda_spdif_out *spdif = | |
165 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
166 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
167 | ||
18486508 | 168 | trace_azx_pcm_prepare(chip, azx_dev); |
05e84878 DR |
169 | dsp_lock(azx_dev); |
170 | if (dsp_is_locked(azx_dev)) { | |
171 | err = -EBUSY; | |
172 | goto unlock; | |
173 | } | |
174 | ||
7833c3f8 | 175 | snd_hdac_stream_reset(azx_stream(azx_dev)); |
b7d023e1 | 176 | format_val = snd_hdac_calc_stream_format(runtime->rate, |
05e84878 DR |
177 | runtime->channels, |
178 | runtime->format, | |
179 | hinfo->maxbps, | |
180 | ctls); | |
181 | if (!format_val) { | |
182 | dev_err(chip->card->dev, | |
183 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
184 | runtime->rate, runtime->channels, runtime->format); | |
185 | err = -EINVAL; | |
186 | goto unlock; | |
187 | } | |
188 | ||
0dd76f36 TI |
189 | err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val); |
190 | if (err < 0) | |
191 | goto unlock; | |
05e84878 | 192 | |
ccc98865 | 193 | snd_hdac_stream_setup(azx_stream(azx_dev)); |
05e84878 | 194 | |
7833c3f8 | 195 | stream_tag = azx_dev->core.stream_tag; |
05e84878 DR |
196 | /* CA-IBG chips need the playback stream starting from 1 */ |
197 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | |
198 | stream_tag > chip->capture_streams) | |
199 | stream_tag -= chip->capture_streams; | |
200 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | |
7833c3f8 | 201 | azx_dev->core.format_val, substream); |
05e84878 DR |
202 | |
203 | unlock: | |
204 | if (!err) | |
6d23c8f5 | 205 | azx_stream(azx_dev)->prepared = 1; |
05e84878 DR |
206 | dsp_unlock(azx_dev); |
207 | return err; | |
208 | } | |
209 | ||
210 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
211 | { | |
212 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
213 | struct azx *chip = apcm->chip; | |
a41d1224 | 214 | struct hdac_bus *bus = azx_bus(chip); |
05e84878 DR |
215 | struct azx_dev *azx_dev; |
216 | struct snd_pcm_substream *s; | |
ccc98865 TI |
217 | struct hdac_stream *hstr; |
218 | bool start; | |
219 | int sbits = 0; | |
220 | int sync_reg; | |
05e84878 DR |
221 | |
222 | azx_dev = get_azx_dev(substream); | |
43db4a59 TI |
223 | trace_azx_pcm_trigger(chip, azx_dev, cmd); |
224 | ||
ccc98865 TI |
225 | hstr = azx_stream(azx_dev); |
226 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
227 | sync_reg = AZX_REG_OLD_SSYNC; | |
228 | else | |
229 | sync_reg = AZX_REG_SSYNC; | |
05e84878 | 230 | |
6d23c8f5 | 231 | if (dsp_is_locked(azx_dev) || !hstr->prepared) |
05e84878 DR |
232 | return -EPIPE; |
233 | ||
234 | switch (cmd) { | |
235 | case SNDRV_PCM_TRIGGER_START: | |
05e84878 DR |
236 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
237 | case SNDRV_PCM_TRIGGER_RESUME: | |
ccc98865 | 238 | start = true; |
05e84878 DR |
239 | break; |
240 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
241 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
242 | case SNDRV_PCM_TRIGGER_STOP: | |
ccc98865 | 243 | start = false; |
05e84878 DR |
244 | break; |
245 | default: | |
246 | return -EINVAL; | |
247 | } | |
248 | ||
249 | snd_pcm_group_for_each_entry(s, substream) { | |
250 | if (s->pcm->card != substream->pcm->card) | |
251 | continue; | |
252 | azx_dev = get_azx_dev(s); | |
7833c3f8 | 253 | sbits |= 1 << azx_dev->core.index; |
05e84878 DR |
254 | snd_pcm_trigger_done(s, substream); |
255 | } | |
256 | ||
a41d1224 | 257 | spin_lock(&bus->reg_lock); |
05e84878 DR |
258 | |
259 | /* first, set SYNC bits of corresponding streams */ | |
ccc98865 | 260 | snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg); |
05e84878 DR |
261 | |
262 | snd_pcm_group_for_each_entry(s, substream) { | |
263 | if (s->pcm->card != substream->pcm->card) | |
264 | continue; | |
265 | azx_dev = get_azx_dev(s); | |
266 | if (start) { | |
7833c3f8 TI |
267 | azx_dev->insufficient = 1; |
268 | snd_hdac_stream_start(azx_stream(azx_dev), true); | |
05e84878 | 269 | } else { |
7833c3f8 | 270 | snd_hdac_stream_stop(azx_stream(azx_dev)); |
05e84878 | 271 | } |
05e84878 | 272 | } |
a41d1224 | 273 | spin_unlock(&bus->reg_lock); |
ccc98865 TI |
274 | |
275 | snd_hdac_stream_sync(hstr, start, sbits); | |
276 | ||
a41d1224 | 277 | spin_lock(&bus->reg_lock); |
05e84878 | 278 | /* reset SYNC bits */ |
ccc98865 TI |
279 | snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg); |
280 | if (start) | |
281 | snd_hdac_stream_timecounter_init(hstr, sbits); | |
a41d1224 | 282 | spin_unlock(&bus->reg_lock); |
05e84878 DR |
283 | return 0; |
284 | } | |
285 | ||
b6050ef6 | 286 | unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 | 287 | { |
7833c3f8 | 288 | return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
b6050ef6 TI |
289 | } |
290 | EXPORT_SYMBOL_GPL(azx_get_pos_lpib); | |
05e84878 | 291 | |
b6050ef6 TI |
292 | unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) |
293 | { | |
7833c3f8 | 294 | return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev)); |
05e84878 | 295 | } |
b6050ef6 | 296 | EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); |
05e84878 DR |
297 | |
298 | unsigned int azx_get_position(struct azx *chip, | |
b6050ef6 | 299 | struct azx_dev *azx_dev) |
05e84878 | 300 | { |
7833c3f8 | 301 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
05e84878 DR |
302 | unsigned int pos; |
303 | int stream = substream->stream; | |
05e84878 DR |
304 | int delay = 0; |
305 | ||
b6050ef6 TI |
306 | if (chip->get_position[stream]) |
307 | pos = chip->get_position[stream](chip, azx_dev); | |
308 | else /* use the position buffer as default */ | |
309 | pos = azx_get_pos_posbuf(chip, azx_dev); | |
05e84878 | 310 | |
7833c3f8 | 311 | if (pos >= azx_dev->core.bufsize) |
05e84878 DR |
312 | pos = 0; |
313 | ||
05e84878 | 314 | if (substream->runtime) { |
b6050ef6 | 315 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
820cc6cf | 316 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
b6050ef6 TI |
317 | |
318 | if (chip->get_delay[stream]) | |
319 | delay += chip->get_delay[stream](chip, azx_dev, pos); | |
05e84878 DR |
320 | if (hinfo->ops.get_delay) |
321 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
322 | substream); | |
323 | substream->runtime->delay = delay; | |
324 | } | |
325 | ||
43db4a59 | 326 | trace_azx_get_position(chip, azx_dev, pos, delay); |
05e84878 DR |
327 | return pos; |
328 | } | |
329 | EXPORT_SYMBOL_GPL(azx_get_position); | |
330 | ||
331 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
332 | { | |
333 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
334 | struct azx *chip = apcm->chip; | |
335 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
336 | return bytes_to_frames(substream->runtime, | |
b6050ef6 | 337 | azx_get_position(chip, azx_dev)); |
05e84878 DR |
338 | } |
339 | ||
9e94df3a PLB |
340 | static int azx_get_time_info(struct snd_pcm_substream *substream, |
341 | struct timespec *system_ts, struct timespec *audio_ts, | |
342 | struct snd_pcm_audio_tstamp_config *audio_tstamp_config, | |
343 | struct snd_pcm_audio_tstamp_report *audio_tstamp_report) | |
05e84878 DR |
344 | { |
345 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
346 | u64 nsec; | |
347 | ||
9e94df3a PLB |
348 | if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && |
349 | (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { | |
05e84878 | 350 | |
9e94df3a PLB |
351 | snd_pcm_gettime(substream->runtime, system_ts); |
352 | ||
7833c3f8 | 353 | nsec = timecounter_read(&azx_dev->core.tc); |
9e94df3a PLB |
354 | nsec = div_u64(nsec, 3); /* can be optimized */ |
355 | if (audio_tstamp_config->report_delay) | |
356 | nsec = azx_adjust_codec_delay(substream, nsec); | |
357 | ||
358 | *audio_ts = ns_to_timespec(nsec); | |
359 | ||
360 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; | |
361 | audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ | |
362 | audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ | |
363 | ||
364 | } else | |
365 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; | |
05e84878 DR |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
370 | static struct snd_pcm_hardware azx_pcm_hw = { | |
371 | .info = (SNDRV_PCM_INFO_MMAP | | |
372 | SNDRV_PCM_INFO_INTERLEAVED | | |
373 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
374 | SNDRV_PCM_INFO_MMAP_VALID | | |
375 | /* No full-resume yet implemented */ | |
376 | /* SNDRV_PCM_INFO_RESUME |*/ | |
377 | SNDRV_PCM_INFO_PAUSE | | |
378 | SNDRV_PCM_INFO_SYNC_START | | |
9e94df3a PLB |
379 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ |
380 | SNDRV_PCM_INFO_HAS_LINK_ATIME | | |
05e84878 DR |
381 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
382 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
383 | .rates = SNDRV_PCM_RATE_48000, | |
384 | .rate_min = 48000, | |
385 | .rate_max = 48000, | |
386 | .channels_min = 2, | |
387 | .channels_max = 2, | |
388 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
389 | .period_bytes_min = 128, | |
390 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
391 | .periods_min = 2, | |
392 | .periods_max = AZX_MAX_FRAG, | |
393 | .fifo_size = 0, | |
394 | }; | |
395 | ||
396 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
397 | { | |
398 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 399 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
400 | struct azx *chip = apcm->chip; |
401 | struct azx_dev *azx_dev; | |
402 | struct snd_pcm_runtime *runtime = substream->runtime; | |
05e84878 DR |
403 | int err; |
404 | int buff_step; | |
405 | ||
9a6246ff | 406 | snd_hda_codec_pcm_get(apcm->info); |
05e84878 DR |
407 | mutex_lock(&chip->open_mutex); |
408 | azx_dev = azx_assign_device(chip, substream); | |
18486508 | 409 | trace_azx_pcm_open(chip, azx_dev); |
05e84878 | 410 | if (azx_dev == NULL) { |
61ca4107 TI |
411 | err = -EBUSY; |
412 | goto unlock; | |
05e84878 | 413 | } |
ccc98865 | 414 | runtime->private_data = azx_dev; |
05e84878 DR |
415 | runtime->hw = azx_pcm_hw; |
416 | runtime->hw.channels_min = hinfo->channels_min; | |
417 | runtime->hw.channels_max = hinfo->channels_max; | |
418 | runtime->hw.formats = hinfo->formats; | |
419 | runtime->hw.rates = hinfo->rates; | |
420 | snd_pcm_limit_hw_rates(runtime); | |
421 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
422 | ||
423 | /* avoid wrap-around with wall-clock */ | |
424 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
425 | 20, | |
426 | 178000000); | |
427 | ||
428 | if (chip->align_buffer_size) | |
429 | /* constrain buffer sizes to be multiple of 128 | |
430 | bytes. This is more efficient in terms of memory | |
431 | access but isn't required by the HDA spec and | |
432 | prevents users from specifying exact period/buffer | |
433 | sizes. For example for 44.1kHz, a period size set | |
434 | to 20ms will be rounded to 19.59ms. */ | |
435 | buff_step = 128; | |
436 | else | |
437 | /* Don't enforce steps on buffer sizes, still need to | |
438 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
439 | HDA controllers, may not work on all devices where | |
440 | option needs to be disabled */ | |
441 | buff_step = 4; | |
442 | ||
443 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
444 | buff_step); | |
445 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
446 | buff_step); | |
cc72da7d | 447 | snd_hda_power_up(apcm->codec); |
61ca4107 TI |
448 | if (hinfo->ops.open) |
449 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | |
450 | else | |
451 | err = -ENODEV; | |
05e84878 DR |
452 | if (err < 0) { |
453 | azx_release_device(azx_dev); | |
61ca4107 | 454 | goto powerdown; |
05e84878 DR |
455 | } |
456 | snd_pcm_limit_hw_rates(runtime); | |
457 | /* sanity check */ | |
458 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
459 | snd_BUG_ON(!runtime->hw.channels_max) || | |
460 | snd_BUG_ON(!runtime->hw.formats) || | |
461 | snd_BUG_ON(!runtime->hw.rates)) { | |
462 | azx_release_device(azx_dev); | |
61ca4107 TI |
463 | if (hinfo->ops.close) |
464 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
465 | err = -EINVAL; | |
466 | goto powerdown; | |
05e84878 DR |
467 | } |
468 | ||
9e94df3a | 469 | /* disable LINK_ATIME timestamps for capture streams |
05e84878 | 470 | until we figure out how to handle digital inputs */ |
9e94df3a PLB |
471 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
472 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ | |
473 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; | |
474 | } | |
05e84878 | 475 | |
05e84878 DR |
476 | snd_pcm_set_sync(substream); |
477 | mutex_unlock(&chip->open_mutex); | |
478 | return 0; | |
61ca4107 TI |
479 | |
480 | powerdown: | |
481 | snd_hda_power_down(apcm->codec); | |
482 | unlock: | |
483 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 484 | snd_hda_codec_pcm_put(apcm->info); |
61ca4107 | 485 | return err; |
05e84878 DR |
486 | } |
487 | ||
488 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
489 | struct vm_area_struct *area) | |
490 | { | |
491 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
492 | struct azx *chip = apcm->chip; | |
493 | if (chip->ops->pcm_mmap_prepare) | |
494 | chip->ops->pcm_mmap_prepare(substream, area); | |
495 | return snd_pcm_lib_default_mmap(substream, area); | |
496 | } | |
497 | ||
498 | static struct snd_pcm_ops azx_pcm_ops = { | |
499 | .open = azx_pcm_open, | |
500 | .close = azx_pcm_close, | |
501 | .ioctl = snd_pcm_lib_ioctl, | |
502 | .hw_params = azx_pcm_hw_params, | |
503 | .hw_free = azx_pcm_hw_free, | |
504 | .prepare = azx_pcm_prepare, | |
505 | .trigger = azx_pcm_trigger, | |
506 | .pointer = azx_pcm_pointer, | |
9e94df3a | 507 | .get_time_info = azx_get_time_info, |
05e84878 DR |
508 | .mmap = azx_pcm_mmap, |
509 | .page = snd_pcm_sgbuf_ops_page, | |
510 | }; | |
511 | ||
512 | static void azx_pcm_free(struct snd_pcm *pcm) | |
513 | { | |
514 | struct azx_pcm *apcm = pcm->private_data; | |
515 | if (apcm) { | |
516 | list_del(&apcm->list); | |
820cc6cf | 517 | apcm->info->pcm = NULL; |
05e84878 DR |
518 | kfree(apcm); |
519 | } | |
520 | } | |
521 | ||
522 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
523 | ||
0a50575b TI |
524 | int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, |
525 | struct hda_pcm *cpcm) | |
05e84878 | 526 | { |
a41d1224 TI |
527 | struct hdac_bus *bus = &_bus->core; |
528 | struct azx *chip = bus_to_azx(bus); | |
05e84878 DR |
529 | struct snd_pcm *pcm; |
530 | struct azx_pcm *apcm; | |
531 | int pcm_dev = cpcm->device; | |
532 | unsigned int size; | |
533 | int s, err; | |
534 | ||
535 | list_for_each_entry(apcm, &chip->pcm_list, list) { | |
536 | if (apcm->pcm->device == pcm_dev) { | |
537 | dev_err(chip->card->dev, "PCM %d already exists\n", | |
538 | pcm_dev); | |
539 | return -EBUSY; | |
540 | } | |
541 | } | |
542 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
543 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
544 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
545 | &pcm); | |
546 | if (err < 0) | |
547 | return err; | |
548 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); | |
549 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); | |
550 | if (apcm == NULL) | |
551 | return -ENOMEM; | |
552 | apcm->chip = chip; | |
553 | apcm->pcm = pcm; | |
554 | apcm->codec = codec; | |
820cc6cf | 555 | apcm->info = cpcm; |
05e84878 DR |
556 | pcm->private_data = apcm; |
557 | pcm->private_free = azx_pcm_free; | |
558 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | |
559 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
560 | list_add_tail(&apcm->list, &chip->pcm_list); | |
561 | cpcm->pcm = pcm; | |
562 | for (s = 0; s < 2; s++) { | |
05e84878 DR |
563 | if (cpcm->stream[s].substreams) |
564 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
565 | } | |
566 | /* buffer pre-allocation */ | |
567 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
568 | if (size > MAX_PREALLOC_SIZE) | |
569 | size = MAX_PREALLOC_SIZE; | |
570 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, | |
571 | chip->card->dev, | |
572 | size, MAX_PREALLOC_SIZE); | |
05e84878 DR |
573 | return 0; |
574 | } | |
05e84878 | 575 | |
6e85dddc DR |
576 | static unsigned int azx_command_addr(u32 cmd) |
577 | { | |
578 | unsigned int addr = cmd >> 28; | |
579 | ||
580 | if (addr >= AZX_MAX_CODECS) { | |
581 | snd_BUG(); | |
582 | addr = 0; | |
583 | } | |
584 | ||
585 | return addr; | |
586 | } | |
587 | ||
6e85dddc | 588 | /* receive a response */ |
a41d1224 | 589 | static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 590 | unsigned int *res) |
6e85dddc | 591 | { |
a41d1224 TI |
592 | struct azx *chip = bus_to_azx(bus); |
593 | struct hda_bus *hbus = &chip->bus; | |
6e85dddc DR |
594 | unsigned long timeout; |
595 | unsigned long loopcounter; | |
596 | int do_poll = 0; | |
597 | ||
598 | again: | |
599 | timeout = jiffies + msecs_to_jiffies(1000); | |
600 | ||
601 | for (loopcounter = 0;; loopcounter++) { | |
a41d1224 TI |
602 | spin_lock_irq(&bus->reg_lock); |
603 | if (chip->polling_mode || do_poll) | |
604 | snd_hdac_bus_update_rirb(bus); | |
605 | if (!bus->rirb.cmds[addr]) { | |
6e85dddc DR |
606 | if (!do_poll) |
607 | chip->poll_count = 0; | |
cad372f1 | 608 | if (res) |
a41d1224 TI |
609 | *res = bus->rirb.res[addr]; /* the last value */ |
610 | spin_unlock_irq(&bus->reg_lock); | |
cad372f1 | 611 | return 0; |
6e85dddc | 612 | } |
a41d1224 | 613 | spin_unlock_irq(&bus->reg_lock); |
6e85dddc DR |
614 | if (time_after(jiffies, timeout)) |
615 | break; | |
a41d1224 | 616 | if (hbus->needs_damn_long_delay || loopcounter > 3000) |
6e85dddc DR |
617 | msleep(2); /* temporary workaround */ |
618 | else { | |
619 | udelay(10); | |
620 | cond_resched(); | |
621 | } | |
622 | } | |
623 | ||
a41d1224 | 624 | if (hbus->no_response_fallback) |
cad372f1 | 625 | return -EIO; |
6e85dddc DR |
626 | |
627 | if (!chip->polling_mode && chip->poll_count < 2) { | |
628 | dev_dbg(chip->card->dev, | |
629 | "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n", | |
a41d1224 | 630 | bus->last_cmd[addr]); |
6e85dddc DR |
631 | do_poll = 1; |
632 | chip->poll_count++; | |
633 | goto again; | |
634 | } | |
635 | ||
636 | ||
637 | if (!chip->polling_mode) { | |
638 | dev_warn(chip->card->dev, | |
639 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", | |
a41d1224 | 640 | bus->last_cmd[addr]); |
6e85dddc DR |
641 | chip->polling_mode = 1; |
642 | goto again; | |
643 | } | |
644 | ||
645 | if (chip->msi) { | |
646 | dev_warn(chip->card->dev, | |
647 | "No response from codec, disabling MSI: last cmd=0x%08x\n", | |
a41d1224 TI |
648 | bus->last_cmd[addr]); |
649 | if (chip->ops->disable_msi_reset_irq && | |
cad372f1 TI |
650 | chip->ops->disable_msi_reset_irq(chip) < 0) |
651 | return -EIO; | |
6e85dddc DR |
652 | goto again; |
653 | } | |
654 | ||
655 | if (chip->probing) { | |
656 | /* If this critical timeout happens during the codec probing | |
657 | * phase, this is likely an access to a non-existing codec | |
658 | * slot. Better to return an error and reset the system. | |
659 | */ | |
cad372f1 | 660 | return -EIO; |
6e85dddc DR |
661 | } |
662 | ||
663 | /* a fatal communication error; need either to reset or to fallback | |
664 | * to the single_cmd mode | |
665 | */ | |
a41d1224 TI |
666 | if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) { |
667 | hbus->response_reset = 1; | |
cad372f1 | 668 | return -EAGAIN; /* give a chance to retry */ |
6e85dddc DR |
669 | } |
670 | ||
671 | dev_err(chip->card->dev, | |
672 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", | |
a41d1224 | 673 | bus->last_cmd[addr]); |
6e85dddc | 674 | chip->single_cmd = 1; |
a41d1224 TI |
675 | hbus->response_reset = 0; |
676 | snd_hdac_bus_stop_cmd_io(bus); | |
cad372f1 | 677 | return -EIO; |
6e85dddc DR |
678 | } |
679 | ||
680 | /* | |
681 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
682 | * | |
683 | * Note: according to Intel, this is not preferred use. The command was | |
684 | * intended for the BIOS only, and may get confused with unsolicited | |
685 | * responses. So, we shouldn't use it for normal operation from the | |
686 | * driver. | |
687 | * I left the codes, however, for debugging/testing purposes. | |
688 | */ | |
689 | ||
690 | /* receive a response */ | |
691 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) | |
692 | { | |
693 | int timeout = 50; | |
694 | ||
695 | while (timeout--) { | |
696 | /* check IRV busy bit */ | |
fb1d8ac2 | 697 | if (azx_readw(chip, IRS) & AZX_IRS_VALID) { |
6e85dddc | 698 | /* reuse rirb.res as the response return value */ |
a41d1224 | 699 | azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR); |
6e85dddc DR |
700 | return 0; |
701 | } | |
702 | udelay(1); | |
703 | } | |
704 | if (printk_ratelimit()) | |
705 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", | |
706 | azx_readw(chip, IRS)); | |
a41d1224 | 707 | azx_bus(chip)->rirb.res[addr] = -1; |
6e85dddc DR |
708 | return -EIO; |
709 | } | |
710 | ||
711 | /* send a command */ | |
a41d1224 | 712 | static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) |
6e85dddc | 713 | { |
a41d1224 | 714 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
715 | unsigned int addr = azx_command_addr(val); |
716 | int timeout = 50; | |
717 | ||
a41d1224 | 718 | bus->last_cmd[azx_command_addr(val)] = val; |
6e85dddc DR |
719 | while (timeout--) { |
720 | /* check ICB busy bit */ | |
fb1d8ac2 | 721 | if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { |
6e85dddc DR |
722 | /* Clear IRV valid bit */ |
723 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 724 | AZX_IRS_VALID); |
6e85dddc DR |
725 | azx_writel(chip, IC, val); |
726 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 727 | AZX_IRS_BUSY); |
6e85dddc DR |
728 | return azx_single_wait_for_response(chip, addr); |
729 | } | |
730 | udelay(1); | |
731 | } | |
732 | if (printk_ratelimit()) | |
733 | dev_dbg(chip->card->dev, | |
734 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
735 | azx_readw(chip, IRS), val); | |
736 | return -EIO; | |
737 | } | |
738 | ||
739 | /* receive a response */ | |
a41d1224 | 740 | static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 741 | unsigned int *res) |
6e85dddc | 742 | { |
cad372f1 | 743 | if (res) |
a41d1224 | 744 | *res = bus->rirb.res[addr]; |
cad372f1 | 745 | return 0; |
6e85dddc DR |
746 | } |
747 | ||
748 | /* | |
749 | * The below are the main callbacks from hda_codec. | |
750 | * | |
751 | * They are just the skeleton to call sub-callbacks according to the | |
752 | * current setting of chip->single_cmd. | |
753 | */ | |
754 | ||
755 | /* send a command */ | |
a41d1224 | 756 | static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) |
6e85dddc | 757 | { |
a41d1224 | 758 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
759 | |
760 | if (chip->disabled) | |
761 | return 0; | |
6e85dddc DR |
762 | if (chip->single_cmd) |
763 | return azx_single_send_cmd(bus, val); | |
764 | else | |
a41d1224 | 765 | return snd_hdac_bus_send_cmd(bus, val); |
6e85dddc | 766 | } |
6e85dddc DR |
767 | |
768 | /* get a response */ | |
a41d1224 | 769 | static int azx_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 770 | unsigned int *res) |
6e85dddc | 771 | { |
a41d1224 TI |
772 | struct azx *chip = bus_to_azx(bus); |
773 | ||
6e85dddc DR |
774 | if (chip->disabled) |
775 | return 0; | |
776 | if (chip->single_cmd) | |
cad372f1 | 777 | return azx_single_get_response(bus, addr, res); |
6e85dddc | 778 | else |
cad372f1 | 779 | return azx_rirb_get_response(bus, addr, res); |
6e85dddc | 780 | } |
6e85dddc | 781 | |
17eccb27 ML |
782 | static int azx_link_power(struct hdac_bus *bus, bool enable) |
783 | { | |
784 | struct azx *chip = bus_to_azx(bus); | |
785 | ||
786 | if (chip->ops->link_power) | |
787 | return chip->ops->link_power(chip, enable); | |
788 | else | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
7e8be1b3 TI |
792 | static const struct hdac_bus_ops bus_core_ops = { |
793 | .command = azx_send_cmd, | |
794 | .get_response = azx_get_response, | |
17eccb27 | 795 | .link_power = azx_link_power, |
7e8be1b3 TI |
796 | }; |
797 | ||
2b5fd6c2 DR |
798 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
799 | /* | |
800 | * DSP loading code (e.g. for CA0132) | |
801 | */ | |
802 | ||
803 | /* use the first stream for loading DSP */ | |
804 | static struct azx_dev * | |
805 | azx_get_dsp_loader_dev(struct azx *chip) | |
806 | { | |
7833c3f8 TI |
807 | struct hdac_bus *bus = azx_bus(chip); |
808 | struct hdac_stream *s; | |
809 | ||
810 | list_for_each_entry(s, &bus->stream_list, list) | |
811 | if (s->index == chip->playback_index_offset) | |
812 | return stream_to_azx_dev(s); | |
813 | ||
814 | return NULL; | |
2b5fd6c2 DR |
815 | } |
816 | ||
0a50575b TI |
817 | int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, |
818 | unsigned int byte_size, | |
819 | struct snd_dma_buffer *bufp) | |
2b5fd6c2 | 820 | { |
0a50575b | 821 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 822 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 823 | struct azx_dev *azx_dev; |
ccc98865 TI |
824 | struct hdac_stream *hstr; |
825 | bool saved = false; | |
2b5fd6c2 DR |
826 | int err; |
827 | ||
828 | azx_dev = azx_get_dsp_loader_dev(chip); | |
ccc98865 | 829 | hstr = azx_stream(azx_dev); |
a41d1224 | 830 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
831 | if (hstr->opened) { |
832 | chip->saved_azx_dev = *azx_dev; | |
833 | saved = true; | |
2b5fd6c2 | 834 | } |
a41d1224 | 835 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 836 | |
ccc98865 TI |
837 | err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp); |
838 | if (err < 0) { | |
a41d1224 | 839 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
840 | if (saved) |
841 | *azx_dev = chip->saved_azx_dev; | |
a41d1224 | 842 | spin_unlock_irq(&bus->reg_lock); |
ccc98865 TI |
843 | return err; |
844 | } | |
2b5fd6c2 | 845 | |
6d23c8f5 | 846 | hstr->prepared = 0; |
2b5fd6c2 DR |
847 | return err; |
848 | } | |
0a50575b | 849 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare); |
2b5fd6c2 | 850 | |
0a50575b | 851 | void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) |
2b5fd6c2 | 852 | { |
0a50575b | 853 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 854 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 DR |
855 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
856 | ||
ccc98865 | 857 | snd_hdac_dsp_trigger(azx_stream(azx_dev), start); |
2b5fd6c2 | 858 | } |
0a50575b | 859 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger); |
2b5fd6c2 | 860 | |
0a50575b TI |
861 | void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, |
862 | struct snd_dma_buffer *dmab) | |
2b5fd6c2 | 863 | { |
0a50575b | 864 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 865 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 866 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
ccc98865 | 867 | struct hdac_stream *hstr = azx_stream(azx_dev); |
2b5fd6c2 | 868 | |
0a50575b | 869 | if (!dmab->area || !hstr->locked) |
2b5fd6c2 DR |
870 | return; |
871 | ||
ccc98865 | 872 | snd_hdac_dsp_cleanup(hstr, dmab); |
a41d1224 | 873 | spin_lock_irq(&bus->reg_lock); |
ccc98865 | 874 | if (hstr->opened) |
2b5fd6c2 | 875 | *azx_dev = chip->saved_azx_dev; |
ccc98865 | 876 | hstr->locked = false; |
a41d1224 | 877 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 878 | } |
0a50575b | 879 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup); |
2b5fd6c2 DR |
880 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |
881 | ||
f43923ff DR |
882 | /* |
883 | * reset and start the controller registers | |
884 | */ | |
17c3ad03 | 885 | void azx_init_chip(struct azx *chip, bool full_reset) |
f43923ff | 886 | { |
a41d1224 TI |
887 | if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) { |
888 | /* correct RINTCNT for CXT */ | |
889 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
890 | azx_writew(chip, RINTCNT, 0xc0); | |
891 | } | |
f43923ff DR |
892 | } |
893 | EXPORT_SYMBOL_GPL(azx_init_chip); | |
894 | ||
7833c3f8 TI |
895 | void azx_stop_all_streams(struct azx *chip) |
896 | { | |
897 | struct hdac_bus *bus = azx_bus(chip); | |
898 | struct hdac_stream *s; | |
899 | ||
900 | list_for_each_entry(s, &bus->stream_list, list) | |
901 | snd_hdac_stream_stop(s); | |
902 | } | |
903 | EXPORT_SYMBOL_GPL(azx_stop_all_streams); | |
904 | ||
f43923ff DR |
905 | void azx_stop_chip(struct azx *chip) |
906 | { | |
a41d1224 | 907 | snd_hdac_bus_stop_chip(azx_bus(chip)); |
f43923ff | 908 | } |
154867cf | 909 | EXPORT_SYMBOL_GPL(azx_stop_chip); |
f43923ff | 910 | |
f0b1df88 DR |
911 | /* |
912 | * interrupt handler | |
913 | */ | |
7833c3f8 TI |
914 | static void stream_update(struct hdac_bus *bus, struct hdac_stream *s) |
915 | { | |
a41d1224 | 916 | struct azx *chip = bus_to_azx(bus); |
7833c3f8 TI |
917 | struct azx_dev *azx_dev = stream_to_azx_dev(s); |
918 | ||
919 | /* check whether this IRQ is really acceptable */ | |
920 | if (!chip->ops->position_check || | |
921 | chip->ops->position_check(chip, azx_dev)) { | |
a41d1224 TI |
922 | spin_unlock(&bus->reg_lock); |
923 | snd_pcm_period_elapsed(azx_stream(azx_dev)->substream); | |
924 | spin_lock(&bus->reg_lock); | |
7833c3f8 TI |
925 | } |
926 | } | |
927 | ||
f0b1df88 DR |
928 | irqreturn_t azx_interrupt(int irq, void *dev_id) |
929 | { | |
930 | struct azx *chip = dev_id; | |
7833c3f8 | 931 | struct hdac_bus *bus = azx_bus(chip); |
f0b1df88 | 932 | u32 status; |
473f4145 TI |
933 | bool active, handled = false; |
934 | int repeat = 0; /* count for avoiding endless loop */ | |
f0b1df88 | 935 | |
641d334b | 936 | #ifdef CONFIG_PM |
364aa716 | 937 | if (azx_has_pm_runtime(chip)) |
7b0a48f3 | 938 | if (!pm_runtime_active(chip->card->dev)) |
f0b1df88 DR |
939 | return IRQ_NONE; |
940 | #endif | |
941 | ||
a41d1224 | 942 | spin_lock(&bus->reg_lock); |
f0b1df88 | 943 | |
473f4145 TI |
944 | if (chip->disabled) |
945 | goto unlock; | |
f0b1df88 | 946 | |
473f4145 TI |
947 | do { |
948 | status = azx_readl(chip, INTSTS); | |
949 | if (status == 0 || status == 0xffffffff) | |
950 | break; | |
f0b1df88 | 951 | |
473f4145 TI |
952 | handled = true; |
953 | active = false; | |
954 | if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) | |
955 | active = true; | |
956 | ||
957 | /* clear rirb int */ | |
958 | status = azx_readb(chip, RIRBSTS); | |
959 | if (status & RIRB_INT_MASK) { | |
960 | active = true; | |
961 | if (status & RIRB_INT_RESPONSE) { | |
962 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
963 | udelay(80); | |
964 | snd_hdac_bus_update_rirb(bus); | |
965 | } | |
966 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
f0b1df88 | 967 | } |
473f4145 | 968 | } while (active && ++repeat < 10); |
f0b1df88 | 969 | |
473f4145 | 970 | unlock: |
a41d1224 | 971 | spin_unlock(&bus->reg_lock); |
f0b1df88 | 972 | |
473f4145 | 973 | return IRQ_RETVAL(handled); |
f0b1df88 DR |
974 | } |
975 | EXPORT_SYMBOL_GPL(azx_interrupt); | |
976 | ||
154867cf DR |
977 | /* |
978 | * Codec initerface | |
979 | */ | |
980 | ||
981 | /* | |
982 | * Probe the given codec address | |
983 | */ | |
984 | static int probe_codec(struct azx *chip, int addr) | |
985 | { | |
986 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
987 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
7833c3f8 | 988 | struct hdac_bus *bus = azx_bus(chip); |
cad372f1 | 989 | int err; |
a41d1224 | 990 | unsigned int res = -1; |
154867cf | 991 | |
7e8be1b3 | 992 | mutex_lock(&bus->cmd_mutex); |
154867cf | 993 | chip->probing = 1; |
7e8be1b3 TI |
994 | azx_send_cmd(bus, cmd); |
995 | err = azx_get_response(bus, addr, &res); | |
154867cf | 996 | chip->probing = 0; |
7e8be1b3 | 997 | mutex_unlock(&bus->cmd_mutex); |
cad372f1 | 998 | if (err < 0 || res == -1) |
154867cf DR |
999 | return -EIO; |
1000 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); | |
1001 | return 0; | |
1002 | } | |
1003 | ||
0a50575b | 1004 | void snd_hda_bus_reset(struct hda_bus *bus) |
154867cf | 1005 | { |
a41d1224 | 1006 | struct azx *chip = bus_to_azx(&bus->core); |
154867cf DR |
1007 | |
1008 | bus->in_reset = 1; | |
1009 | azx_stop_chip(chip); | |
17c3ad03 | 1010 | azx_init_chip(chip, true); |
a41d1224 | 1011 | if (bus->core.chip_init) |
0a50575b | 1012 | snd_hda_bus_reset_codecs(bus); |
154867cf DR |
1013 | bus->in_reset = 0; |
1014 | } | |
1015 | ||
154867cf DR |
1016 | static int get_jackpoll_interval(struct azx *chip) |
1017 | { | |
1018 | int i; | |
1019 | unsigned int j; | |
1020 | ||
1021 | if (!chip->jackpoll_ms) | |
1022 | return 0; | |
1023 | ||
1024 | i = chip->jackpoll_ms[chip->dev_index]; | |
1025 | if (i == 0) | |
1026 | return 0; | |
1027 | if (i < 50 || i > 60000) | |
1028 | j = 0; | |
1029 | else | |
1030 | j = msecs_to_jiffies(i); | |
1031 | if (j == 0) | |
1032 | dev_warn(chip->card->dev, | |
1033 | "jackpoll_ms value out of range: %d\n", i); | |
1034 | return j; | |
1035 | } | |
1036 | ||
96d2bd6e | 1037 | /* HD-audio bus initialization */ |
a41d1224 TI |
1038 | int azx_bus_init(struct azx *chip, const char *model, |
1039 | const struct hdac_io_ops *io_ops) | |
154867cf | 1040 | { |
a41d1224 | 1041 | struct hda_bus *bus = &chip->bus; |
96d2bd6e | 1042 | int err; |
154867cf | 1043 | |
a41d1224 TI |
1044 | err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops, |
1045 | io_ops); | |
154867cf DR |
1046 | if (err < 0) |
1047 | return err; | |
1048 | ||
a41d1224 TI |
1049 | bus->card = chip->card; |
1050 | mutex_init(&bus->prepare_mutex); | |
ef744978 TI |
1051 | bus->pci = chip->pci; |
1052 | bus->modelname = model; | |
2f0eaad9 | 1053 | bus->mixer_assigned = -1; |
ccc98865 TI |
1054 | bus->core.snoop = azx_snoop(chip); |
1055 | if (chip->get_position[0] != azx_get_pos_lpib || | |
1056 | chip->get_position[1] != azx_get_pos_lpib) | |
1057 | bus->core.use_posbuf = true; | |
4f0189be | 1058 | bus->core.bdl_pos_adj = chip->bdl_pos_adj; |
a41d1224 TI |
1059 | if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) |
1060 | bus->core.corbrp_self_clear = true; | |
ef744978 | 1061 | |
de1ab6af TI |
1062 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) |
1063 | bus->core.align_bdle_4k = true; | |
1064 | ||
96d2bd6e TI |
1065 | /* AMD chipsets often cause the communication stalls upon certain |
1066 | * sequence like the pin-detection. It seems that forcing the synced | |
1067 | * access works around the stall. Grrr... | |
1068 | */ | |
1069 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { | |
1070 | dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); | |
d068ebc2 | 1071 | bus->core.sync_write = 1; |
96d2bd6e TI |
1072 | bus->allow_bus_reset = 1; |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
a41d1224 | 1077 | EXPORT_SYMBOL_GPL(azx_bus_init); |
96d2bd6e TI |
1078 | |
1079 | /* Probe codecs */ | |
1080 | int azx_probe_codecs(struct azx *chip, unsigned int max_slots) | |
1081 | { | |
a41d1224 | 1082 | struct hdac_bus *bus = azx_bus(chip); |
96d2bd6e TI |
1083 | int c, codecs, err; |
1084 | ||
154867cf DR |
1085 | codecs = 0; |
1086 | if (!max_slots) | |
1087 | max_slots = AZX_DEFAULT_CODECS; | |
1088 | ||
1089 | /* First try to probe all given codec slots */ | |
1090 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1091 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf DR |
1092 | if (probe_codec(chip, c) < 0) { |
1093 | /* Some BIOSen give you wrong codec addresses | |
1094 | * that don't exist | |
1095 | */ | |
1096 | dev_warn(chip->card->dev, | |
1097 | "Codec #%d probe error; disabling it...\n", c); | |
a41d1224 | 1098 | bus->codec_mask &= ~(1 << c); |
154867cf DR |
1099 | /* More badly, accessing to a non-existing |
1100 | * codec often screws up the controller chip, | |
1101 | * and disturbs the further communications. | |
1102 | * Thus if an error occurs during probing, | |
1103 | * better to reset the controller chip to | |
1104 | * get back to the sanity state. | |
1105 | */ | |
1106 | azx_stop_chip(chip); | |
17c3ad03 | 1107 | azx_init_chip(chip, true); |
154867cf DR |
1108 | } |
1109 | } | |
1110 | } | |
1111 | ||
154867cf DR |
1112 | /* Then create codec instances */ |
1113 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1114 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf | 1115 | struct hda_codec *codec; |
a41d1224 | 1116 | err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec); |
154867cf DR |
1117 | if (err < 0) |
1118 | continue; | |
1119 | codec->jackpoll_interval = get_jackpoll_interval(chip); | |
1120 | codec->beep_mode = chip->beep_mode; | |
1121 | codecs++; | |
1122 | } | |
1123 | } | |
1124 | if (!codecs) { | |
1125 | dev_err(chip->card->dev, "no codecs initialized\n"); | |
1126 | return -ENXIO; | |
1127 | } | |
1128 | return 0; | |
1129 | } | |
96d2bd6e | 1130 | EXPORT_SYMBOL_GPL(azx_probe_codecs); |
154867cf DR |
1131 | |
1132 | /* configure each codec instance */ | |
1133 | int azx_codec_configure(struct azx *chip) | |
1134 | { | |
1135 | struct hda_codec *codec; | |
a41d1224 | 1136 | list_for_each_codec(codec, &chip->bus) { |
154867cf DR |
1137 | snd_hda_codec_configure(codec); |
1138 | } | |
1139 | return 0; | |
1140 | } | |
1141 | EXPORT_SYMBOL_GPL(azx_codec_configure); | |
1142 | ||
7833c3f8 | 1143 | static int stream_direction(struct azx *chip, unsigned char index) |
93e3423e | 1144 | { |
7833c3f8 TI |
1145 | if (index >= chip->capture_index_offset && |
1146 | index < chip->capture_index_offset + chip->capture_streams) | |
1147 | return SNDRV_PCM_STREAM_CAPTURE; | |
1148 | return SNDRV_PCM_STREAM_PLAYBACK; | |
93e3423e RR |
1149 | } |
1150 | ||
154867cf | 1151 | /* initialize SD streams */ |
a41d1224 | 1152 | int azx_init_streams(struct azx *chip) |
154867cf DR |
1153 | { |
1154 | int i; | |
7833c3f8 | 1155 | int stream_tags[2] = { 0, 0 }; |
154867cf DR |
1156 | |
1157 | /* initialize each stream (aka device) | |
1158 | * assign the starting bdl address to each stream (device) | |
1159 | * and initialize | |
1160 | */ | |
1161 | for (i = 0; i < chip->num_streams; i++) { | |
7833c3f8 TI |
1162 | struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL); |
1163 | int dir, tag; | |
1164 | ||
1165 | if (!azx_dev) | |
1166 | return -ENOMEM; | |
93e3423e | 1167 | |
7833c3f8 | 1168 | dir = stream_direction(chip, i); |
93e3423e RR |
1169 | /* stream tag must be unique throughout |
1170 | * the stream direction group, | |
1171 | * valid values 1...15 | |
1172 | * use separate stream tag if the flag | |
1173 | * AZX_DCAPS_SEPARATE_STREAM_TAG is used | |
1174 | */ | |
1175 | if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) | |
7833c3f8 | 1176 | tag = ++stream_tags[dir]; |
93e3423e | 1177 | else |
7833c3f8 TI |
1178 | tag = i + 1; |
1179 | snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), | |
1180 | i, dir, tag); | |
154867cf DR |
1181 | } |
1182 | ||
1183 | return 0; | |
1184 | } | |
a41d1224 TI |
1185 | EXPORT_SYMBOL_GPL(azx_init_streams); |
1186 | ||
1187 | void azx_free_streams(struct azx *chip) | |
1188 | { | |
1189 | struct hdac_bus *bus = azx_bus(chip); | |
1190 | struct hdac_stream *s; | |
1191 | ||
1192 | while (!list_empty(&bus->stream_list)) { | |
1193 | s = list_first_entry(&bus->stream_list, struct hdac_stream, list); | |
1194 | list_del(&s->list); | |
1195 | kfree(stream_to_azx_dev(s)); | |
1196 | } | |
1197 | } | |
1198 | EXPORT_SYMBOL_GPL(azx_free_streams); |