Commit | Line | Data |
---|---|---|
05e84878 DR |
1 | /* |
2 | * | |
3 | * Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clocksource.h> | |
24 | #include <linux/delay.h> | |
f0b1df88 | 25 | #include <linux/interrupt.h> |
05e84878 DR |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
154867cf | 28 | #include <linux/pm_runtime.h> |
05e84878 DR |
29 | #include <linux/slab.h> |
30 | #include <sound/core.h> | |
31 | #include <sound/initval.h> | |
32 | #include "hda_priv.h" | |
33 | #include "hda_controller.h" | |
34 | ||
35 | #define CREATE_TRACE_POINTS | |
36 | #include "hda_intel_trace.h" | |
37 | ||
2b5fd6c2 DR |
38 | /* DSP lock helpers */ |
39 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
40 | #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
41 | #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
42 | #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
43 | #define dsp_is_locked(dev) ((dev)->locked) | |
44 | #else | |
45 | #define dsp_lock_init(dev) do {} while (0) | |
46 | #define dsp_lock(dev) do {} while (0) | |
47 | #define dsp_unlock(dev) do {} while (0) | |
48 | #define dsp_is_locked(dev) 0 | |
49 | #endif | |
50 | ||
05e84878 DR |
51 | /* |
52 | * AZX stream operations. | |
53 | */ | |
54 | ||
55 | /* start a stream */ | |
2b5fd6c2 | 56 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 DR |
57 | { |
58 | /* | |
59 | * Before stream start, initialize parameter | |
60 | */ | |
61 | azx_dev->insufficient = 1; | |
62 | ||
63 | /* enable SIE */ | |
64 | azx_writel(chip, INTCTL, | |
65 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | |
66 | /* set DMA start and interrupt mask */ | |
67 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
68 | azx_sd_readb(chip, azx_dev, SD_CTL) | | |
69 | SD_CTL_DMA_START | SD_INT_MASK); | |
70 | } | |
05e84878 DR |
71 | |
72 | /* stop DMA */ | |
73 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | |
74 | { | |
75 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
76 | azx_sd_readb(chip, azx_dev, SD_CTL) & | |
77 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
78 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
79 | } | |
80 | ||
81 | /* stop a stream */ | |
82 | void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
83 | { | |
84 | azx_stream_clear(chip, azx_dev); | |
85 | /* disable SIE */ | |
86 | azx_writel(chip, INTCTL, | |
87 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | |
88 | } | |
89 | EXPORT_SYMBOL_GPL(azx_stream_stop); | |
90 | ||
91 | /* reset stream */ | |
2b5fd6c2 | 92 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 DR |
93 | { |
94 | unsigned char val; | |
95 | int timeout; | |
96 | ||
97 | azx_stream_clear(chip, azx_dev); | |
98 | ||
99 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
100 | azx_sd_readb(chip, azx_dev, SD_CTL) | | |
101 | SD_CTL_STREAM_RESET); | |
102 | udelay(3); | |
103 | timeout = 300; | |
104 | while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | |
105 | SD_CTL_STREAM_RESET) && --timeout) | |
106 | ; | |
107 | val &= ~SD_CTL_STREAM_RESET; | |
108 | azx_sd_writeb(chip, azx_dev, SD_CTL, val); | |
109 | udelay(3); | |
110 | ||
111 | timeout = 300; | |
112 | /* waiting for hardware to report that the stream is out of reset */ | |
113 | while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | |
114 | SD_CTL_STREAM_RESET) && --timeout) | |
115 | ; | |
116 | ||
117 | /* reset first position - may not be synced with hw at this time */ | |
118 | *azx_dev->posbuf = 0; | |
119 | } | |
05e84878 DR |
120 | |
121 | /* | |
122 | * set up the SD for streaming | |
123 | */ | |
2b5fd6c2 | 124 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 DR |
125 | { |
126 | unsigned int val; | |
127 | /* make sure the run bit is zero for SD */ | |
128 | azx_stream_clear(chip, azx_dev); | |
129 | /* program the stream_tag */ | |
130 | val = azx_sd_readl(chip, azx_dev, SD_CTL); | |
131 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
132 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
133 | if (!azx_snoop(chip)) | |
134 | val |= SD_CTL_TRAFFIC_PRIO; | |
135 | azx_sd_writel(chip, azx_dev, SD_CTL, val); | |
136 | ||
137 | /* program the length of samples in cyclic buffer */ | |
138 | azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); | |
139 | ||
140 | /* program the stream format */ | |
141 | /* this value needs to be the same as the one programmed */ | |
142 | azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); | |
143 | ||
144 | /* program the stream LVI (last valid index) of the BDL */ | |
145 | azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); | |
146 | ||
147 | /* program the BDL address */ | |
148 | /* lower BDL address */ | |
149 | azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
150 | /* upper BDL address */ | |
151 | azx_sd_writel(chip, azx_dev, SD_BDLPU, | |
152 | upper_32_bits(azx_dev->bdl.addr)); | |
153 | ||
154 | /* enable the position buffer */ | |
b6050ef6 TI |
155 | if (chip->get_position[0] != azx_get_pos_lpib || |
156 | chip->get_position[1] != azx_get_pos_lpib) { | |
05e84878 DR |
157 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
158 | azx_writel(chip, DPLBASE, | |
159 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
160 | } | |
161 | ||
162 | /* set the interrupt enable bits in the descriptor control register */ | |
163 | azx_sd_writel(chip, azx_dev, SD_CTL, | |
164 | azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); | |
165 | ||
166 | return 0; | |
167 | } | |
05e84878 DR |
168 | |
169 | /* assign a stream for the PCM */ | |
170 | static inline struct azx_dev * | |
171 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
172 | { | |
173 | int dev, i, nums; | |
174 | struct azx_dev *res = NULL; | |
175 | /* make a non-zero unique key for the substream */ | |
176 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
177 | (substream->stream + 1); | |
178 | ||
179 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
180 | dev = chip->playback_index_offset; | |
181 | nums = chip->playback_streams; | |
182 | } else { | |
183 | dev = chip->capture_index_offset; | |
184 | nums = chip->capture_streams; | |
185 | } | |
186 | for (i = 0; i < nums; i++, dev++) { | |
187 | struct azx_dev *azx_dev = &chip->azx_dev[dev]; | |
188 | dsp_lock(azx_dev); | |
189 | if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { | |
dcb32ecd AH |
190 | if (azx_dev->assigned_key == key) { |
191 | azx_dev->opened = 1; | |
192 | azx_dev->assigned_key = key; | |
05e84878 DR |
193 | dsp_unlock(azx_dev); |
194 | return azx_dev; | |
195 | } | |
dcb32ecd AH |
196 | if (!res) |
197 | res = azx_dev; | |
05e84878 DR |
198 | } |
199 | dsp_unlock(azx_dev); | |
200 | } | |
201 | if (res) { | |
202 | dsp_lock(res); | |
203 | res->opened = 1; | |
204 | res->assigned_key = key; | |
205 | dsp_unlock(res); | |
206 | } | |
207 | return res; | |
208 | } | |
209 | ||
210 | /* release the assigned stream */ | |
211 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
212 | { | |
213 | azx_dev->opened = 0; | |
214 | } | |
215 | ||
216 | static cycle_t azx_cc_read(const struct cyclecounter *cc) | |
217 | { | |
218 | struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); | |
219 | struct snd_pcm_substream *substream = azx_dev->substream; | |
220 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
221 | struct azx *chip = apcm->chip; | |
222 | ||
223 | return azx_readl(chip, WALLCLK); | |
224 | } | |
225 | ||
226 | static void azx_timecounter_init(struct snd_pcm_substream *substream, | |
227 | bool force, cycle_t last) | |
228 | { | |
229 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
230 | struct timecounter *tc = &azx_dev->azx_tc; | |
231 | struct cyclecounter *cc = &azx_dev->azx_cc; | |
232 | u64 nsec; | |
233 | ||
234 | cc->read = azx_cc_read; | |
235 | cc->mask = CLOCKSOURCE_MASK(32); | |
236 | ||
237 | /* | |
238 | * Converting from 24 MHz to ns means applying a 125/3 factor. | |
239 | * To avoid any saturation issues in intermediate operations, | |
240 | * the 125 factor is applied first. The division is applied | |
241 | * last after reading the timecounter value. | |
242 | * Applying the 1/3 factor as part of the multiplication | |
243 | * requires at least 20 bits for a decent precision, however | |
244 | * overflows occur after about 4 hours or less, not a option. | |
245 | */ | |
246 | ||
247 | cc->mult = 125; /* saturation after 195 years */ | |
248 | cc->shift = 0; | |
249 | ||
250 | nsec = 0; /* audio time is elapsed time since trigger */ | |
251 | timecounter_init(tc, cc, nsec); | |
252 | if (force) | |
253 | /* | |
254 | * force timecounter to use predefined value, | |
255 | * used for synchronized starts | |
256 | */ | |
257 | tc->cycle_last = last; | |
258 | } | |
259 | ||
260 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, | |
261 | u64 nsec) | |
262 | { | |
263 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
264 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
265 | u64 codec_frames, codec_nsecs; | |
266 | ||
267 | if (!hinfo->ops.get_delay) | |
268 | return nsec; | |
269 | ||
270 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
271 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
272 | substream->runtime->rate); | |
273 | ||
274 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
275 | return nsec + codec_nsecs; | |
276 | ||
277 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
278 | } | |
279 | ||
280 | /* | |
281 | * set up a BDL entry | |
282 | */ | |
2b5fd6c2 DR |
283 | static int setup_bdle(struct azx *chip, |
284 | struct snd_dma_buffer *dmab, | |
285 | struct azx_dev *azx_dev, u32 **bdlp, | |
286 | int ofs, int size, int with_ioc) | |
05e84878 DR |
287 | { |
288 | u32 *bdl = *bdlp; | |
289 | ||
290 | while (size > 0) { | |
291 | dma_addr_t addr; | |
292 | int chunk; | |
293 | ||
294 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
295 | return -EINVAL; | |
296 | ||
297 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
298 | /* program the address field of the BDL entry */ | |
299 | bdl[0] = cpu_to_le32((u32)addr); | |
300 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
301 | /* program the size field of the BDL entry */ | |
302 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
303 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
304 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { | |
305 | u32 remain = 0x1000 - (ofs & 0xfff); | |
306 | if (chunk > remain) | |
307 | chunk = remain; | |
308 | } | |
309 | bdl[2] = cpu_to_le32(chunk); | |
310 | /* program the IOC to enable interrupt | |
311 | * only when the whole fragment is processed | |
312 | */ | |
313 | size -= chunk; | |
314 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
315 | bdl += 4; | |
316 | azx_dev->frags++; | |
317 | ofs += chunk; | |
318 | } | |
319 | *bdlp = bdl; | |
320 | return ofs; | |
321 | } | |
05e84878 DR |
322 | |
323 | /* | |
324 | * set up BDL entries | |
325 | */ | |
326 | static int azx_setup_periods(struct azx *chip, | |
327 | struct snd_pcm_substream *substream, | |
328 | struct azx_dev *azx_dev) | |
329 | { | |
330 | u32 *bdl; | |
331 | int i, ofs, periods, period_bytes; | |
332 | int pos_adj = 0; | |
333 | ||
334 | /* reset BDL address */ | |
335 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
336 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
337 | ||
338 | period_bytes = azx_dev->period_bytes; | |
339 | periods = azx_dev->bufsize / period_bytes; | |
340 | ||
341 | /* program the initial BDL entries */ | |
342 | bdl = (u32 *)azx_dev->bdl.area; | |
343 | ofs = 0; | |
344 | azx_dev->frags = 0; | |
345 | ||
346 | if (chip->bdl_pos_adj) | |
347 | pos_adj = chip->bdl_pos_adj[chip->dev_index]; | |
348 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { | |
349 | struct snd_pcm_runtime *runtime = substream->runtime; | |
350 | int pos_align = pos_adj; | |
351 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; | |
352 | if (!pos_adj) | |
353 | pos_adj = pos_align; | |
354 | else | |
355 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
356 | pos_align; | |
357 | pos_adj = frames_to_bytes(runtime, pos_adj); | |
358 | if (pos_adj >= period_bytes) { | |
359 | dev_warn(chip->card->dev,"Too big adjustment %d\n", | |
360 | pos_adj); | |
361 | pos_adj = 0; | |
362 | } else { | |
363 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
364 | azx_dev, | |
365 | &bdl, ofs, pos_adj, true); | |
366 | if (ofs < 0) | |
367 | goto error; | |
368 | } | |
369 | } else | |
370 | pos_adj = 0; | |
371 | ||
372 | for (i = 0; i < periods; i++) { | |
373 | if (i == periods - 1 && pos_adj) | |
374 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
375 | azx_dev, &bdl, ofs, | |
376 | period_bytes - pos_adj, 0); | |
377 | else | |
378 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
379 | azx_dev, &bdl, ofs, | |
380 | period_bytes, | |
381 | !azx_dev->no_period_wakeup); | |
382 | if (ofs < 0) | |
383 | goto error; | |
384 | } | |
385 | return 0; | |
386 | ||
387 | error: | |
388 | dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n", | |
389 | azx_dev->bufsize, period_bytes); | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
393 | /* | |
394 | * PCM ops | |
395 | */ | |
396 | ||
397 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
398 | { | |
399 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
400 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
401 | struct azx *chip = apcm->chip; | |
402 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
403 | unsigned long flags; | |
404 | ||
405 | mutex_lock(&chip->open_mutex); | |
406 | spin_lock_irqsave(&chip->reg_lock, flags); | |
407 | azx_dev->substream = NULL; | |
408 | azx_dev->running = 0; | |
409 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
410 | azx_release_device(azx_dev); | |
411 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
412 | snd_hda_power_down(apcm->codec); | |
413 | mutex_unlock(&chip->open_mutex); | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | |
418 | struct snd_pcm_hw_params *hw_params) | |
419 | { | |
420 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
421 | struct azx *chip = apcm->chip; | |
422 | int ret; | |
423 | ||
424 | dsp_lock(get_azx_dev(substream)); | |
425 | if (dsp_is_locked(get_azx_dev(substream))) { | |
426 | ret = -EBUSY; | |
427 | goto unlock; | |
428 | } | |
429 | ||
430 | ret = chip->ops->substream_alloc_pages(chip, substream, | |
431 | params_buffer_bytes(hw_params)); | |
432 | unlock: | |
433 | dsp_unlock(get_azx_dev(substream)); | |
434 | return ret; | |
435 | } | |
436 | ||
437 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
438 | { | |
439 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
440 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
441 | struct azx *chip = apcm->chip; | |
442 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
443 | int err; | |
444 | ||
445 | /* reset BDL address */ | |
446 | dsp_lock(azx_dev); | |
447 | if (!dsp_is_locked(azx_dev)) { | |
448 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
449 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
450 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); | |
451 | azx_dev->bufsize = 0; | |
452 | azx_dev->period_bytes = 0; | |
453 | azx_dev->format_val = 0; | |
454 | } | |
455 | ||
456 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | |
457 | ||
458 | err = chip->ops->substream_free_pages(chip, substream); | |
459 | azx_dev->prepared = 0; | |
460 | dsp_unlock(azx_dev); | |
461 | return err; | |
462 | } | |
463 | ||
464 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
465 | { | |
466 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
467 | struct azx *chip = apcm->chip; | |
468 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
469 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
470 | struct snd_pcm_runtime *runtime = substream->runtime; | |
471 | unsigned int bufsize, period_bytes, format_val, stream_tag; | |
472 | int err; | |
473 | struct hda_spdif_out *spdif = | |
474 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
475 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
476 | ||
477 | dsp_lock(azx_dev); | |
478 | if (dsp_is_locked(azx_dev)) { | |
479 | err = -EBUSY; | |
480 | goto unlock; | |
481 | } | |
482 | ||
483 | azx_stream_reset(chip, azx_dev); | |
6194b99d TI |
484 | format_val = snd_hda_calc_stream_format(apcm->codec, |
485 | runtime->rate, | |
05e84878 DR |
486 | runtime->channels, |
487 | runtime->format, | |
488 | hinfo->maxbps, | |
489 | ctls); | |
490 | if (!format_val) { | |
491 | dev_err(chip->card->dev, | |
492 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
493 | runtime->rate, runtime->channels, runtime->format); | |
494 | err = -EINVAL; | |
495 | goto unlock; | |
496 | } | |
497 | ||
498 | bufsize = snd_pcm_lib_buffer_bytes(substream); | |
499 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
500 | ||
501 | dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", | |
502 | bufsize, format_val); | |
503 | ||
504 | if (bufsize != azx_dev->bufsize || | |
505 | period_bytes != azx_dev->period_bytes || | |
506 | format_val != azx_dev->format_val || | |
507 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { | |
508 | azx_dev->bufsize = bufsize; | |
509 | azx_dev->period_bytes = period_bytes; | |
510 | azx_dev->format_val = format_val; | |
511 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; | |
512 | err = azx_setup_periods(chip, substream, azx_dev); | |
513 | if (err < 0) | |
514 | goto unlock; | |
515 | } | |
516 | ||
517 | /* when LPIB delay correction gives a small negative value, | |
518 | * we ignore it; currently set the threshold statically to | |
519 | * 64 frames | |
520 | */ | |
521 | if (runtime->period_size > 64) | |
522 | azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); | |
523 | else | |
524 | azx_dev->delay_negative_threshold = 0; | |
525 | ||
526 | /* wallclk has 24Mhz clock source */ | |
527 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
528 | runtime->rate) * 1000); | |
529 | azx_setup_controller(chip, azx_dev); | |
530 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
531 | azx_dev->fifo_size = | |
532 | azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; | |
533 | else | |
534 | azx_dev->fifo_size = 0; | |
535 | ||
536 | stream_tag = azx_dev->stream_tag; | |
537 | /* CA-IBG chips need the playback stream starting from 1 */ | |
538 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | |
539 | stream_tag > chip->capture_streams) | |
540 | stream_tag -= chip->capture_streams; | |
541 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | |
542 | azx_dev->format_val, substream); | |
543 | ||
544 | unlock: | |
545 | if (!err) | |
546 | azx_dev->prepared = 1; | |
547 | dsp_unlock(azx_dev); | |
548 | return err; | |
549 | } | |
550 | ||
551 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
552 | { | |
553 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
554 | struct azx *chip = apcm->chip; | |
555 | struct azx_dev *azx_dev; | |
556 | struct snd_pcm_substream *s; | |
557 | int rstart = 0, start, nsync = 0, sbits = 0; | |
558 | int nwait, timeout; | |
559 | ||
560 | azx_dev = get_azx_dev(substream); | |
561 | trace_azx_pcm_trigger(chip, azx_dev, cmd); | |
562 | ||
563 | if (dsp_is_locked(azx_dev) || !azx_dev->prepared) | |
564 | return -EPIPE; | |
565 | ||
566 | switch (cmd) { | |
567 | case SNDRV_PCM_TRIGGER_START: | |
568 | rstart = 1; | |
569 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
570 | case SNDRV_PCM_TRIGGER_RESUME: | |
571 | start = 1; | |
572 | break; | |
573 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
574 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
575 | case SNDRV_PCM_TRIGGER_STOP: | |
576 | start = 0; | |
577 | break; | |
578 | default: | |
579 | return -EINVAL; | |
580 | } | |
581 | ||
582 | snd_pcm_group_for_each_entry(s, substream) { | |
583 | if (s->pcm->card != substream->pcm->card) | |
584 | continue; | |
585 | azx_dev = get_azx_dev(s); | |
586 | sbits |= 1 << azx_dev->index; | |
587 | nsync++; | |
588 | snd_pcm_trigger_done(s, substream); | |
589 | } | |
590 | ||
591 | spin_lock(&chip->reg_lock); | |
592 | ||
593 | /* first, set SYNC bits of corresponding streams */ | |
594 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
595 | azx_writel(chip, OLD_SSYNC, | |
596 | azx_readl(chip, OLD_SSYNC) | sbits); | |
597 | else | |
598 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); | |
599 | ||
600 | snd_pcm_group_for_each_entry(s, substream) { | |
601 | if (s->pcm->card != substream->pcm->card) | |
602 | continue; | |
603 | azx_dev = get_azx_dev(s); | |
604 | if (start) { | |
605 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | |
606 | if (!rstart) | |
607 | azx_dev->start_wallclk -= | |
608 | azx_dev->period_wallclk; | |
609 | azx_stream_start(chip, azx_dev); | |
610 | } else { | |
611 | azx_stream_stop(chip, azx_dev); | |
612 | } | |
613 | azx_dev->running = start; | |
614 | } | |
615 | spin_unlock(&chip->reg_lock); | |
616 | if (start) { | |
617 | /* wait until all FIFOs get ready */ | |
618 | for (timeout = 5000; timeout; timeout--) { | |
619 | nwait = 0; | |
620 | snd_pcm_group_for_each_entry(s, substream) { | |
621 | if (s->pcm->card != substream->pcm->card) | |
622 | continue; | |
623 | azx_dev = get_azx_dev(s); | |
624 | if (!(azx_sd_readb(chip, azx_dev, SD_STS) & | |
625 | SD_STS_FIFO_READY)) | |
626 | nwait++; | |
627 | } | |
628 | if (!nwait) | |
629 | break; | |
630 | cpu_relax(); | |
631 | } | |
632 | } else { | |
633 | /* wait until all RUN bits are cleared */ | |
634 | for (timeout = 5000; timeout; timeout--) { | |
635 | nwait = 0; | |
636 | snd_pcm_group_for_each_entry(s, substream) { | |
637 | if (s->pcm->card != substream->pcm->card) | |
638 | continue; | |
639 | azx_dev = get_azx_dev(s); | |
640 | if (azx_sd_readb(chip, azx_dev, SD_CTL) & | |
641 | SD_CTL_DMA_START) | |
642 | nwait++; | |
643 | } | |
644 | if (!nwait) | |
645 | break; | |
646 | cpu_relax(); | |
647 | } | |
648 | } | |
649 | spin_lock(&chip->reg_lock); | |
650 | /* reset SYNC bits */ | |
651 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
652 | azx_writel(chip, OLD_SSYNC, | |
653 | azx_readl(chip, OLD_SSYNC) & ~sbits); | |
654 | else | |
655 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); | |
656 | if (start) { | |
657 | azx_timecounter_init(substream, 0, 0); | |
658 | if (nsync > 1) { | |
659 | cycle_t cycle_last; | |
660 | ||
661 | /* same start cycle for master and group */ | |
662 | azx_dev = get_azx_dev(substream); | |
663 | cycle_last = azx_dev->azx_tc.cycle_last; | |
664 | ||
665 | snd_pcm_group_for_each_entry(s, substream) { | |
666 | if (s->pcm->card != substream->pcm->card) | |
667 | continue; | |
668 | azx_timecounter_init(s, 1, cycle_last); | |
669 | } | |
670 | } | |
671 | } | |
672 | spin_unlock(&chip->reg_lock); | |
673 | return 0; | |
674 | } | |
675 | ||
b6050ef6 | 676 | unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 | 677 | { |
b6050ef6 TI |
678 | return azx_sd_readl(chip, azx_dev, SD_LPIB); |
679 | } | |
680 | EXPORT_SYMBOL_GPL(azx_get_pos_lpib); | |
05e84878 | 681 | |
b6050ef6 TI |
682 | unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) |
683 | { | |
684 | return le32_to_cpu(*azx_dev->posbuf); | |
05e84878 | 685 | } |
b6050ef6 | 686 | EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); |
05e84878 DR |
687 | |
688 | unsigned int azx_get_position(struct azx *chip, | |
b6050ef6 | 689 | struct azx_dev *azx_dev) |
05e84878 DR |
690 | { |
691 | struct snd_pcm_substream *substream = azx_dev->substream; | |
05e84878 DR |
692 | unsigned int pos; |
693 | int stream = substream->stream; | |
05e84878 DR |
694 | int delay = 0; |
695 | ||
b6050ef6 TI |
696 | if (chip->get_position[stream]) |
697 | pos = chip->get_position[stream](chip, azx_dev); | |
698 | else /* use the position buffer as default */ | |
699 | pos = azx_get_pos_posbuf(chip, azx_dev); | |
05e84878 DR |
700 | |
701 | if (pos >= azx_dev->bufsize) | |
702 | pos = 0; | |
703 | ||
05e84878 | 704 | if (substream->runtime) { |
b6050ef6 TI |
705 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
706 | struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; | |
707 | ||
708 | if (chip->get_delay[stream]) | |
709 | delay += chip->get_delay[stream](chip, azx_dev, pos); | |
05e84878 DR |
710 | if (hinfo->ops.get_delay) |
711 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
712 | substream); | |
713 | substream->runtime->delay = delay; | |
714 | } | |
715 | ||
716 | trace_azx_get_position(chip, azx_dev, pos, delay); | |
717 | return pos; | |
718 | } | |
719 | EXPORT_SYMBOL_GPL(azx_get_position); | |
720 | ||
721 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
722 | { | |
723 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
724 | struct azx *chip = apcm->chip; | |
725 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
726 | return bytes_to_frames(substream->runtime, | |
b6050ef6 | 727 | azx_get_position(chip, azx_dev)); |
05e84878 DR |
728 | } |
729 | ||
730 | static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, | |
731 | struct timespec *ts) | |
732 | { | |
733 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
734 | u64 nsec; | |
735 | ||
736 | nsec = timecounter_read(&azx_dev->azx_tc); | |
737 | nsec = div_u64(nsec, 3); /* can be optimized */ | |
738 | nsec = azx_adjust_codec_delay(substream, nsec); | |
739 | ||
740 | *ts = ns_to_timespec(nsec); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | static struct snd_pcm_hardware azx_pcm_hw = { | |
746 | .info = (SNDRV_PCM_INFO_MMAP | | |
747 | SNDRV_PCM_INFO_INTERLEAVED | | |
748 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
749 | SNDRV_PCM_INFO_MMAP_VALID | | |
750 | /* No full-resume yet implemented */ | |
751 | /* SNDRV_PCM_INFO_RESUME |*/ | |
752 | SNDRV_PCM_INFO_PAUSE | | |
753 | SNDRV_PCM_INFO_SYNC_START | | |
754 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | | |
755 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), | |
756 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
757 | .rates = SNDRV_PCM_RATE_48000, | |
758 | .rate_min = 48000, | |
759 | .rate_max = 48000, | |
760 | .channels_min = 2, | |
761 | .channels_max = 2, | |
762 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
763 | .period_bytes_min = 128, | |
764 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
765 | .periods_min = 2, | |
766 | .periods_max = AZX_MAX_FRAG, | |
767 | .fifo_size = 0, | |
768 | }; | |
769 | ||
770 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
771 | { | |
772 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
773 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
774 | struct azx *chip = apcm->chip; | |
775 | struct azx_dev *azx_dev; | |
776 | struct snd_pcm_runtime *runtime = substream->runtime; | |
777 | unsigned long flags; | |
778 | int err; | |
779 | int buff_step; | |
780 | ||
781 | mutex_lock(&chip->open_mutex); | |
782 | azx_dev = azx_assign_device(chip, substream); | |
783 | if (azx_dev == NULL) { | |
784 | mutex_unlock(&chip->open_mutex); | |
785 | return -EBUSY; | |
786 | } | |
787 | runtime->hw = azx_pcm_hw; | |
788 | runtime->hw.channels_min = hinfo->channels_min; | |
789 | runtime->hw.channels_max = hinfo->channels_max; | |
790 | runtime->hw.formats = hinfo->formats; | |
791 | runtime->hw.rates = hinfo->rates; | |
792 | snd_pcm_limit_hw_rates(runtime); | |
793 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
794 | ||
795 | /* avoid wrap-around with wall-clock */ | |
796 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
797 | 20, | |
798 | 178000000); | |
799 | ||
800 | if (chip->align_buffer_size) | |
801 | /* constrain buffer sizes to be multiple of 128 | |
802 | bytes. This is more efficient in terms of memory | |
803 | access but isn't required by the HDA spec and | |
804 | prevents users from specifying exact period/buffer | |
805 | sizes. For example for 44.1kHz, a period size set | |
806 | to 20ms will be rounded to 19.59ms. */ | |
807 | buff_step = 128; | |
808 | else | |
809 | /* Don't enforce steps on buffer sizes, still need to | |
810 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
811 | HDA controllers, may not work on all devices where | |
812 | option needs to be disabled */ | |
813 | buff_step = 4; | |
814 | ||
815 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
816 | buff_step); | |
817 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
818 | buff_step); | |
819 | snd_hda_power_up_d3wait(apcm->codec); | |
820 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | |
821 | if (err < 0) { | |
822 | azx_release_device(azx_dev); | |
823 | snd_hda_power_down(apcm->codec); | |
824 | mutex_unlock(&chip->open_mutex); | |
825 | return err; | |
826 | } | |
827 | snd_pcm_limit_hw_rates(runtime); | |
828 | /* sanity check */ | |
829 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
830 | snd_BUG_ON(!runtime->hw.channels_max) || | |
831 | snd_BUG_ON(!runtime->hw.formats) || | |
832 | snd_BUG_ON(!runtime->hw.rates)) { | |
833 | azx_release_device(azx_dev); | |
834 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
835 | snd_hda_power_down(apcm->codec); | |
836 | mutex_unlock(&chip->open_mutex); | |
837 | return -EINVAL; | |
838 | } | |
839 | ||
840 | /* disable WALLCLOCK timestamps for capture streams | |
841 | until we figure out how to handle digital inputs */ | |
842 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
843 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; | |
844 | ||
845 | spin_lock_irqsave(&chip->reg_lock, flags); | |
846 | azx_dev->substream = substream; | |
847 | azx_dev->running = 0; | |
848 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
849 | ||
850 | runtime->private_data = azx_dev; | |
851 | snd_pcm_set_sync(substream); | |
852 | mutex_unlock(&chip->open_mutex); | |
853 | return 0; | |
854 | } | |
855 | ||
856 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
857 | struct vm_area_struct *area) | |
858 | { | |
859 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
860 | struct azx *chip = apcm->chip; | |
861 | if (chip->ops->pcm_mmap_prepare) | |
862 | chip->ops->pcm_mmap_prepare(substream, area); | |
863 | return snd_pcm_lib_default_mmap(substream, area); | |
864 | } | |
865 | ||
866 | static struct snd_pcm_ops azx_pcm_ops = { | |
867 | .open = azx_pcm_open, | |
868 | .close = azx_pcm_close, | |
869 | .ioctl = snd_pcm_lib_ioctl, | |
870 | .hw_params = azx_pcm_hw_params, | |
871 | .hw_free = azx_pcm_hw_free, | |
872 | .prepare = azx_pcm_prepare, | |
873 | .trigger = azx_pcm_trigger, | |
874 | .pointer = azx_pcm_pointer, | |
875 | .wall_clock = azx_get_wallclock_tstamp, | |
876 | .mmap = azx_pcm_mmap, | |
877 | .page = snd_pcm_sgbuf_ops_page, | |
878 | }; | |
879 | ||
880 | static void azx_pcm_free(struct snd_pcm *pcm) | |
881 | { | |
882 | struct azx_pcm *apcm = pcm->private_data; | |
883 | if (apcm) { | |
884 | list_del(&apcm->list); | |
885 | kfree(apcm); | |
886 | } | |
887 | } | |
888 | ||
889 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
890 | ||
7c3e438a DR |
891 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
892 | struct hda_pcm *cpcm) | |
05e84878 DR |
893 | { |
894 | struct azx *chip = bus->private_data; | |
895 | struct snd_pcm *pcm; | |
896 | struct azx_pcm *apcm; | |
897 | int pcm_dev = cpcm->device; | |
898 | unsigned int size; | |
899 | int s, err; | |
900 | ||
901 | list_for_each_entry(apcm, &chip->pcm_list, list) { | |
902 | if (apcm->pcm->device == pcm_dev) { | |
903 | dev_err(chip->card->dev, "PCM %d already exists\n", | |
904 | pcm_dev); | |
905 | return -EBUSY; | |
906 | } | |
907 | } | |
908 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
909 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
910 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
911 | &pcm); | |
912 | if (err < 0) | |
913 | return err; | |
914 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); | |
915 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); | |
916 | if (apcm == NULL) | |
917 | return -ENOMEM; | |
918 | apcm->chip = chip; | |
919 | apcm->pcm = pcm; | |
920 | apcm->codec = codec; | |
921 | pcm->private_data = apcm; | |
922 | pcm->private_free = azx_pcm_free; | |
923 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | |
924 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
925 | list_add_tail(&apcm->list, &chip->pcm_list); | |
926 | cpcm->pcm = pcm; | |
927 | for (s = 0; s < 2; s++) { | |
928 | apcm->hinfo[s] = &cpcm->stream[s]; | |
929 | if (cpcm->stream[s].substreams) | |
930 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
931 | } | |
932 | /* buffer pre-allocation */ | |
933 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
934 | if (size > MAX_PREALLOC_SIZE) | |
935 | size = MAX_PREALLOC_SIZE; | |
936 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, | |
937 | chip->card->dev, | |
938 | size, MAX_PREALLOC_SIZE); | |
939 | /* link to codec */ | |
940 | pcm->dev = &codec->dev; | |
941 | return 0; | |
942 | } | |
05e84878 | 943 | |
6e85dddc DR |
944 | /* |
945 | * CORB / RIRB interface | |
946 | */ | |
f19c3ec2 | 947 | static int azx_alloc_cmd_io(struct azx *chip) |
6e85dddc DR |
948 | { |
949 | int err; | |
950 | ||
951 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
952 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | |
953 | PAGE_SIZE, &chip->rb); | |
954 | if (err < 0) | |
955 | dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n"); | |
956 | return err; | |
957 | } | |
958 | EXPORT_SYMBOL_GPL(azx_alloc_cmd_io); | |
959 | ||
f43923ff | 960 | static void azx_init_cmd_io(struct azx *chip) |
6e85dddc DR |
961 | { |
962 | int timeout; | |
963 | ||
964 | spin_lock_irq(&chip->reg_lock); | |
965 | /* CORB set up */ | |
966 | chip->corb.addr = chip->rb.addr; | |
967 | chip->corb.buf = (u32 *)chip->rb.area; | |
968 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
969 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); | |
970 | ||
971 | /* set the corb size to 256 entries (ULI requires explicitly) */ | |
972 | azx_writeb(chip, CORBSIZE, 0x02); | |
973 | /* set the corb write pointer to 0 */ | |
974 | azx_writew(chip, CORBWP, 0); | |
975 | ||
976 | /* reset the corb hw read pointer */ | |
977 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); | |
6ba736dd TI |
978 | if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) { |
979 | for (timeout = 1000; timeout > 0; timeout--) { | |
980 | if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) | |
981 | break; | |
982 | udelay(1); | |
983 | } | |
984 | if (timeout <= 0) | |
985 | dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", | |
986 | azx_readw(chip, CORBRP)); | |
987 | ||
988 | azx_writew(chip, CORBRP, 0); | |
989 | for (timeout = 1000; timeout > 0; timeout--) { | |
990 | if (azx_readw(chip, CORBRP) == 0) | |
991 | break; | |
992 | udelay(1); | |
993 | } | |
994 | if (timeout <= 0) | |
995 | dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", | |
996 | azx_readw(chip, CORBRP)); | |
6e85dddc | 997 | } |
6e85dddc DR |
998 | |
999 | /* enable corb dma */ | |
1000 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); | |
1001 | ||
1002 | /* RIRB set up */ | |
1003 | chip->rirb.addr = chip->rb.addr + 2048; | |
1004 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
1005 | chip->rirb.wp = chip->rirb.rp = 0; | |
1006 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | |
1007 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
1008 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); | |
1009 | ||
1010 | /* set the rirb size to 256 entries (ULI requires explicitly) */ | |
1011 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1012 | /* reset the rirb hw write pointer */ | |
1013 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); | |
1014 | /* set N=1, get RIRB response interrupt for new entry */ | |
1015 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
1016 | azx_writew(chip, RINTCNT, 0xc0); | |
1017 | else | |
1018 | azx_writew(chip, RINTCNT, 1); | |
1019 | /* enable rirb dma and response irq */ | |
1020 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | |
1021 | spin_unlock_irq(&chip->reg_lock); | |
1022 | } | |
1023 | EXPORT_SYMBOL_GPL(azx_init_cmd_io); | |
1024 | ||
f43923ff | 1025 | static void azx_free_cmd_io(struct azx *chip) |
6e85dddc DR |
1026 | { |
1027 | spin_lock_irq(&chip->reg_lock); | |
1028 | /* disable ringbuffer DMAs */ | |
1029 | azx_writeb(chip, RIRBCTL, 0); | |
1030 | azx_writeb(chip, CORBCTL, 0); | |
1031 | spin_unlock_irq(&chip->reg_lock); | |
1032 | } | |
1033 | EXPORT_SYMBOL_GPL(azx_free_cmd_io); | |
1034 | ||
1035 | static unsigned int azx_command_addr(u32 cmd) | |
1036 | { | |
1037 | unsigned int addr = cmd >> 28; | |
1038 | ||
1039 | if (addr >= AZX_MAX_CODECS) { | |
1040 | snd_BUG(); | |
1041 | addr = 0; | |
1042 | } | |
1043 | ||
1044 | return addr; | |
1045 | } | |
1046 | ||
1047 | /* send a command */ | |
1048 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) | |
1049 | { | |
1050 | struct azx *chip = bus->private_data; | |
1051 | unsigned int addr = azx_command_addr(val); | |
1052 | unsigned int wp, rp; | |
1053 | ||
1054 | spin_lock_irq(&chip->reg_lock); | |
1055 | ||
1056 | /* add command to corb */ | |
1057 | wp = azx_readw(chip, CORBWP); | |
1058 | if (wp == 0xffff) { | |
1059 | /* something wrong, controller likely turned to D3 */ | |
1060 | spin_unlock_irq(&chip->reg_lock); | |
1061 | return -EIO; | |
1062 | } | |
1063 | wp++; | |
1064 | wp %= ICH6_MAX_CORB_ENTRIES; | |
1065 | ||
1066 | rp = azx_readw(chip, CORBRP); | |
1067 | if (wp == rp) { | |
1068 | /* oops, it's full */ | |
1069 | spin_unlock_irq(&chip->reg_lock); | |
1070 | return -EAGAIN; | |
1071 | } | |
1072 | ||
1073 | chip->rirb.cmds[addr]++; | |
1074 | chip->corb.buf[wp] = cpu_to_le32(val); | |
1075 | azx_writew(chip, CORBWP, wp); | |
1076 | ||
1077 | spin_unlock_irq(&chip->reg_lock); | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
1083 | ||
1084 | /* retrieve RIRB entry - called from interrupt handler */ | |
f0b1df88 | 1085 | static void azx_update_rirb(struct azx *chip) |
6e85dddc DR |
1086 | { |
1087 | unsigned int rp, wp; | |
1088 | unsigned int addr; | |
1089 | u32 res, res_ex; | |
1090 | ||
1091 | wp = azx_readw(chip, RIRBWP); | |
1092 | if (wp == 0xffff) { | |
1093 | /* something wrong, controller likely turned to D3 */ | |
1094 | return; | |
1095 | } | |
1096 | ||
1097 | if (wp == chip->rirb.wp) | |
1098 | return; | |
1099 | chip->rirb.wp = wp; | |
1100 | ||
1101 | while (chip->rirb.rp != wp) { | |
1102 | chip->rirb.rp++; | |
1103 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
1104 | ||
1105 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
1106 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
1107 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
1108 | addr = res_ex & 0xf; | |
1109 | if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) { | |
1110 | dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d", | |
1111 | res, res_ex, | |
1112 | chip->rirb.rp, wp); | |
1113 | snd_BUG(); | |
1114 | } | |
1115 | else if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
1116 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
1117 | else if (chip->rirb.cmds[addr]) { | |
1118 | chip->rirb.res[addr] = res; | |
1119 | smp_wmb(); | |
1120 | chip->rirb.cmds[addr]--; | |
1121 | } else if (printk_ratelimit()) { | |
1122 | dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n", | |
1123 | res, res_ex, | |
1124 | chip->last_cmd[addr]); | |
1125 | } | |
1126 | } | |
1127 | } | |
6e85dddc DR |
1128 | |
1129 | /* receive a response */ | |
1130 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, | |
1131 | unsigned int addr) | |
1132 | { | |
1133 | struct azx *chip = bus->private_data; | |
1134 | unsigned long timeout; | |
1135 | unsigned long loopcounter; | |
1136 | int do_poll = 0; | |
1137 | ||
1138 | again: | |
1139 | timeout = jiffies + msecs_to_jiffies(1000); | |
1140 | ||
1141 | for (loopcounter = 0;; loopcounter++) { | |
1142 | if (chip->polling_mode || do_poll) { | |
1143 | spin_lock_irq(&chip->reg_lock); | |
1144 | azx_update_rirb(chip); | |
1145 | spin_unlock_irq(&chip->reg_lock); | |
1146 | } | |
1147 | if (!chip->rirb.cmds[addr]) { | |
1148 | smp_rmb(); | |
1149 | bus->rirb_error = 0; | |
1150 | ||
1151 | if (!do_poll) | |
1152 | chip->poll_count = 0; | |
1153 | return chip->rirb.res[addr]; /* the last value */ | |
1154 | } | |
1155 | if (time_after(jiffies, timeout)) | |
1156 | break; | |
1157 | if (bus->needs_damn_long_delay || loopcounter > 3000) | |
1158 | msleep(2); /* temporary workaround */ | |
1159 | else { | |
1160 | udelay(10); | |
1161 | cond_resched(); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | if (!bus->no_response_fallback) | |
1166 | return -1; | |
1167 | ||
1168 | if (!chip->polling_mode && chip->poll_count < 2) { | |
1169 | dev_dbg(chip->card->dev, | |
1170 | "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n", | |
1171 | chip->last_cmd[addr]); | |
1172 | do_poll = 1; | |
1173 | chip->poll_count++; | |
1174 | goto again; | |
1175 | } | |
1176 | ||
1177 | ||
1178 | if (!chip->polling_mode) { | |
1179 | dev_warn(chip->card->dev, | |
1180 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", | |
1181 | chip->last_cmd[addr]); | |
1182 | chip->polling_mode = 1; | |
1183 | goto again; | |
1184 | } | |
1185 | ||
1186 | if (chip->msi) { | |
1187 | dev_warn(chip->card->dev, | |
1188 | "No response from codec, disabling MSI: last cmd=0x%08x\n", | |
1189 | chip->last_cmd[addr]); | |
1190 | if (chip->ops->disable_msi_reset_irq(chip) && | |
1191 | chip->ops->disable_msi_reset_irq(chip) < 0) { | |
1192 | bus->rirb_error = 1; | |
1193 | return -1; | |
1194 | } | |
1195 | goto again; | |
1196 | } | |
1197 | ||
1198 | if (chip->probing) { | |
1199 | /* If this critical timeout happens during the codec probing | |
1200 | * phase, this is likely an access to a non-existing codec | |
1201 | * slot. Better to return an error and reset the system. | |
1202 | */ | |
1203 | return -1; | |
1204 | } | |
1205 | ||
1206 | /* a fatal communication error; need either to reset or to fallback | |
1207 | * to the single_cmd mode | |
1208 | */ | |
1209 | bus->rirb_error = 1; | |
1210 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { | |
1211 | bus->response_reset = 1; | |
1212 | return -1; /* give a chance to retry */ | |
1213 | } | |
1214 | ||
1215 | dev_err(chip->card->dev, | |
1216 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", | |
1217 | chip->last_cmd[addr]); | |
1218 | chip->single_cmd = 1; | |
1219 | bus->response_reset = 0; | |
1220 | /* release CORB/RIRB */ | |
1221 | azx_free_cmd_io(chip); | |
1222 | /* disable unsolicited responses */ | |
1223 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); | |
1224 | return -1; | |
1225 | } | |
1226 | ||
1227 | /* | |
1228 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
1229 | * | |
1230 | * Note: according to Intel, this is not preferred use. The command was | |
1231 | * intended for the BIOS only, and may get confused with unsolicited | |
1232 | * responses. So, we shouldn't use it for normal operation from the | |
1233 | * driver. | |
1234 | * I left the codes, however, for debugging/testing purposes. | |
1235 | */ | |
1236 | ||
1237 | /* receive a response */ | |
1238 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) | |
1239 | { | |
1240 | int timeout = 50; | |
1241 | ||
1242 | while (timeout--) { | |
1243 | /* check IRV busy bit */ | |
1244 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | |
1245 | /* reuse rirb.res as the response return value */ | |
1246 | chip->rirb.res[addr] = azx_readl(chip, IR); | |
1247 | return 0; | |
1248 | } | |
1249 | udelay(1); | |
1250 | } | |
1251 | if (printk_ratelimit()) | |
1252 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", | |
1253 | azx_readw(chip, IRS)); | |
1254 | chip->rirb.res[addr] = -1; | |
1255 | return -EIO; | |
1256 | } | |
1257 | ||
1258 | /* send a command */ | |
1259 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) | |
1260 | { | |
1261 | struct azx *chip = bus->private_data; | |
1262 | unsigned int addr = azx_command_addr(val); | |
1263 | int timeout = 50; | |
1264 | ||
1265 | bus->rirb_error = 0; | |
1266 | while (timeout--) { | |
1267 | /* check ICB busy bit */ | |
1268 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { | |
1269 | /* Clear IRV valid bit */ | |
1270 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
1271 | ICH6_IRS_VALID); | |
1272 | azx_writel(chip, IC, val); | |
1273 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
1274 | ICH6_IRS_BUSY); | |
1275 | return azx_single_wait_for_response(chip, addr); | |
1276 | } | |
1277 | udelay(1); | |
1278 | } | |
1279 | if (printk_ratelimit()) | |
1280 | dev_dbg(chip->card->dev, | |
1281 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
1282 | azx_readw(chip, IRS), val); | |
1283 | return -EIO; | |
1284 | } | |
1285 | ||
1286 | /* receive a response */ | |
1287 | static unsigned int azx_single_get_response(struct hda_bus *bus, | |
1288 | unsigned int addr) | |
1289 | { | |
1290 | struct azx *chip = bus->private_data; | |
1291 | return chip->rirb.res[addr]; | |
1292 | } | |
1293 | ||
1294 | /* | |
1295 | * The below are the main callbacks from hda_codec. | |
1296 | * | |
1297 | * They are just the skeleton to call sub-callbacks according to the | |
1298 | * current setting of chip->single_cmd. | |
1299 | */ | |
1300 | ||
1301 | /* send a command */ | |
154867cf | 1302 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) |
6e85dddc DR |
1303 | { |
1304 | struct azx *chip = bus->private_data; | |
1305 | ||
1306 | if (chip->disabled) | |
1307 | return 0; | |
1308 | chip->last_cmd[azx_command_addr(val)] = val; | |
1309 | if (chip->single_cmd) | |
1310 | return azx_single_send_cmd(bus, val); | |
1311 | else | |
1312 | return azx_corb_send_cmd(bus, val); | |
1313 | } | |
1314 | EXPORT_SYMBOL_GPL(azx_send_cmd); | |
1315 | ||
1316 | /* get a response */ | |
154867cf | 1317 | static unsigned int azx_get_response(struct hda_bus *bus, |
6e85dddc DR |
1318 | unsigned int addr) |
1319 | { | |
1320 | struct azx *chip = bus->private_data; | |
1321 | if (chip->disabled) | |
1322 | return 0; | |
1323 | if (chip->single_cmd) | |
1324 | return azx_single_get_response(bus, addr); | |
1325 | else | |
1326 | return azx_rirb_get_response(bus, addr); | |
1327 | } | |
1328 | EXPORT_SYMBOL_GPL(azx_get_response); | |
1329 | ||
2b5fd6c2 DR |
1330 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
1331 | /* | |
1332 | * DSP loading code (e.g. for CA0132) | |
1333 | */ | |
1334 | ||
1335 | /* use the first stream for loading DSP */ | |
1336 | static struct azx_dev * | |
1337 | azx_get_dsp_loader_dev(struct azx *chip) | |
1338 | { | |
1339 | return &chip->azx_dev[chip->playback_index_offset]; | |
1340 | } | |
1341 | ||
154867cf DR |
1342 | static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, |
1343 | unsigned int byte_size, | |
1344 | struct snd_dma_buffer *bufp) | |
2b5fd6c2 DR |
1345 | { |
1346 | u32 *bdl; | |
1347 | struct azx *chip = bus->private_data; | |
1348 | struct azx_dev *azx_dev; | |
1349 | int err; | |
1350 | ||
1351 | azx_dev = azx_get_dsp_loader_dev(chip); | |
1352 | ||
1353 | dsp_lock(azx_dev); | |
1354 | spin_lock_irq(&chip->reg_lock); | |
1355 | if (azx_dev->running || azx_dev->locked) { | |
1356 | spin_unlock_irq(&chip->reg_lock); | |
1357 | err = -EBUSY; | |
1358 | goto unlock; | |
1359 | } | |
1360 | azx_dev->prepared = 0; | |
1361 | chip->saved_azx_dev = *azx_dev; | |
1362 | azx_dev->locked = 1; | |
1363 | spin_unlock_irq(&chip->reg_lock); | |
1364 | ||
1365 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG, | |
1366 | byte_size, bufp); | |
1367 | if (err < 0) | |
1368 | goto err_alloc; | |
1369 | ||
1370 | azx_dev->bufsize = byte_size; | |
1371 | azx_dev->period_bytes = byte_size; | |
1372 | azx_dev->format_val = format; | |
1373 | ||
1374 | azx_stream_reset(chip, azx_dev); | |
1375 | ||
1376 | /* reset BDL address */ | |
1377 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
1378 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
1379 | ||
1380 | azx_dev->frags = 0; | |
1381 | bdl = (u32 *)azx_dev->bdl.area; | |
1382 | err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); | |
1383 | if (err < 0) | |
1384 | goto error; | |
1385 | ||
1386 | azx_setup_controller(chip, azx_dev); | |
1387 | dsp_unlock(azx_dev); | |
1388 | return azx_dev->stream_tag; | |
1389 | ||
1390 | error: | |
1391 | chip->ops->dma_free_pages(chip, bufp); | |
1392 | err_alloc: | |
1393 | spin_lock_irq(&chip->reg_lock); | |
1394 | if (azx_dev->opened) | |
1395 | *azx_dev = chip->saved_azx_dev; | |
1396 | azx_dev->locked = 0; | |
1397 | spin_unlock_irq(&chip->reg_lock); | |
1398 | unlock: | |
1399 | dsp_unlock(azx_dev); | |
1400 | return err; | |
1401 | } | |
2b5fd6c2 | 1402 | |
154867cf | 1403 | static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) |
2b5fd6c2 DR |
1404 | { |
1405 | struct azx *chip = bus->private_data; | |
1406 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | |
1407 | ||
1408 | if (start) | |
1409 | azx_stream_start(chip, azx_dev); | |
1410 | else | |
1411 | azx_stream_stop(chip, azx_dev); | |
1412 | azx_dev->running = start; | |
1413 | } | |
2b5fd6c2 | 1414 | |
154867cf DR |
1415 | static void azx_load_dsp_cleanup(struct hda_bus *bus, |
1416 | struct snd_dma_buffer *dmab) | |
2b5fd6c2 DR |
1417 | { |
1418 | struct azx *chip = bus->private_data; | |
1419 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | |
1420 | ||
1421 | if (!dmab->area || !azx_dev->locked) | |
1422 | return; | |
1423 | ||
1424 | dsp_lock(azx_dev); | |
1425 | /* reset BDL address */ | |
1426 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
1427 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
1428 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); | |
1429 | azx_dev->bufsize = 0; | |
1430 | azx_dev->period_bytes = 0; | |
1431 | azx_dev->format_val = 0; | |
1432 | ||
1433 | chip->ops->dma_free_pages(chip, dmab); | |
1434 | dmab->area = NULL; | |
1435 | ||
1436 | spin_lock_irq(&chip->reg_lock); | |
1437 | if (azx_dev->opened) | |
1438 | *azx_dev = chip->saved_azx_dev; | |
1439 | azx_dev->locked = 0; | |
1440 | spin_unlock_irq(&chip->reg_lock); | |
1441 | dsp_unlock(azx_dev); | |
1442 | } | |
2b5fd6c2 DR |
1443 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |
1444 | ||
67908994 DR |
1445 | int azx_alloc_stream_pages(struct azx *chip) |
1446 | { | |
1447 | int i, err; | |
1448 | struct snd_card *card = chip->card; | |
1449 | ||
1450 | for (i = 0; i < chip->num_streams; i++) { | |
1451 | dsp_lock_init(&chip->azx_dev[i]); | |
1452 | /* allocate memory for the BDL for each stream */ | |
1453 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | |
1454 | BDL_SIZE, | |
1455 | &chip->azx_dev[i].bdl); | |
1456 | if (err < 0) { | |
1457 | dev_err(card->dev, "cannot allocate BDL\n"); | |
1458 | return -ENOMEM; | |
1459 | } | |
1460 | } | |
1461 | /* allocate memory for the position buffer */ | |
1462 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | |
1463 | chip->num_streams * 8, &chip->posbuf); | |
1464 | if (err < 0) { | |
1465 | dev_err(card->dev, "cannot allocate posbuf\n"); | |
1466 | return -ENOMEM; | |
1467 | } | |
f19c3ec2 DR |
1468 | |
1469 | /* allocate CORB/RIRB */ | |
1470 | err = azx_alloc_cmd_io(chip); | |
1471 | if (err < 0) | |
1472 | return err; | |
67908994 DR |
1473 | return 0; |
1474 | } | |
1475 | EXPORT_SYMBOL_GPL(azx_alloc_stream_pages); | |
1476 | ||
1477 | void azx_free_stream_pages(struct azx *chip) | |
1478 | { | |
1479 | int i; | |
1480 | if (chip->azx_dev) { | |
1481 | for (i = 0; i < chip->num_streams; i++) | |
1482 | if (chip->azx_dev[i].bdl.area) | |
1483 | chip->ops->dma_free_pages( | |
1484 | chip, &chip->azx_dev[i].bdl); | |
1485 | } | |
1486 | if (chip->rb.area) | |
1487 | chip->ops->dma_free_pages(chip, &chip->rb); | |
1488 | if (chip->posbuf.area) | |
1489 | chip->ops->dma_free_pages(chip, &chip->posbuf); | |
1490 | } | |
1491 | EXPORT_SYMBOL_GPL(azx_free_stream_pages); | |
1492 | ||
f43923ff DR |
1493 | /* |
1494 | * Lowlevel interface | |
1495 | */ | |
1496 | ||
1497 | /* enter link reset */ | |
1498 | void azx_enter_link_reset(struct azx *chip) | |
1499 | { | |
1500 | unsigned long timeout; | |
1501 | ||
1502 | /* reset controller */ | |
1503 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
1504 | ||
1505 | timeout = jiffies + msecs_to_jiffies(100); | |
1506 | while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && | |
1507 | time_before(jiffies, timeout)) | |
1508 | usleep_range(500, 1000); | |
1509 | } | |
1510 | EXPORT_SYMBOL_GPL(azx_enter_link_reset); | |
1511 | ||
1512 | /* exit link reset */ | |
1513 | static void azx_exit_link_reset(struct azx *chip) | |
1514 | { | |
1515 | unsigned long timeout; | |
1516 | ||
1517 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
1518 | ||
1519 | timeout = jiffies + msecs_to_jiffies(100); | |
1520 | while (!azx_readb(chip, GCTL) && | |
1521 | time_before(jiffies, timeout)) | |
1522 | usleep_range(500, 1000); | |
1523 | } | |
1524 | ||
1525 | /* reset codec link */ | |
17c3ad03 | 1526 | static int azx_reset(struct azx *chip, bool full_reset) |
f43923ff DR |
1527 | { |
1528 | if (!full_reset) | |
1529 | goto __skip; | |
1530 | ||
1531 | /* clear STATESTS */ | |
1532 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); | |
1533 | ||
1534 | /* reset controller */ | |
1535 | azx_enter_link_reset(chip); | |
1536 | ||
1537 | /* delay for >= 100us for codec PLL to settle per spec | |
1538 | * Rev 0.9 section 5.5.1 | |
1539 | */ | |
1540 | usleep_range(500, 1000); | |
1541 | ||
1542 | /* Bring controller out of reset */ | |
1543 | azx_exit_link_reset(chip); | |
1544 | ||
1545 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | |
1546 | usleep_range(1000, 1200); | |
1547 | ||
1548 | __skip: | |
1549 | /* check to see if controller is ready */ | |
1550 | if (!azx_readb(chip, GCTL)) { | |
1551 | dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n"); | |
1552 | return -EBUSY; | |
1553 | } | |
1554 | ||
1555 | /* Accept unsolicited responses */ | |
1556 | if (!chip->single_cmd) | |
1557 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | | |
1558 | ICH6_GCTL_UNSOL); | |
1559 | ||
1560 | /* detect codecs */ | |
1561 | if (!chip->codec_mask) { | |
1562 | chip->codec_mask = azx_readw(chip, STATESTS); | |
1563 | dev_dbg(chip->card->dev, "codec_mask = 0x%x\n", | |
1564 | chip->codec_mask); | |
1565 | } | |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
1570 | /* enable interrupts */ | |
1571 | static void azx_int_enable(struct azx *chip) | |
1572 | { | |
1573 | /* enable controller CIE and GIE */ | |
1574 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
1575 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
1576 | } | |
1577 | ||
1578 | /* disable interrupts */ | |
1579 | static void azx_int_disable(struct azx *chip) | |
1580 | { | |
1581 | int i; | |
1582 | ||
1583 | /* disable interrupts in stream descriptor */ | |
1584 | for (i = 0; i < chip->num_streams; i++) { | |
1585 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1586 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
1587 | azx_sd_readb(chip, azx_dev, SD_CTL) & | |
1588 | ~SD_INT_MASK); | |
1589 | } | |
1590 | ||
1591 | /* disable SIE for all streams */ | |
1592 | azx_writeb(chip, INTCTL, 0); | |
1593 | ||
1594 | /* disable controller CIE and GIE */ | |
1595 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
1596 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
1597 | } | |
1598 | ||
1599 | /* clear interrupts */ | |
1600 | static void azx_int_clear(struct azx *chip) | |
1601 | { | |
1602 | int i; | |
1603 | ||
1604 | /* clear stream status */ | |
1605 | for (i = 0; i < chip->num_streams; i++) { | |
1606 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1607 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); | |
1608 | } | |
1609 | ||
1610 | /* clear STATESTS */ | |
1611 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); | |
1612 | ||
1613 | /* clear rirb status */ | |
1614 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
1615 | ||
1616 | /* clear int status */ | |
1617 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
1618 | } | |
1619 | ||
1620 | /* | |
1621 | * reset and start the controller registers | |
1622 | */ | |
17c3ad03 | 1623 | void azx_init_chip(struct azx *chip, bool full_reset) |
f43923ff DR |
1624 | { |
1625 | if (chip->initialized) | |
1626 | return; | |
1627 | ||
1628 | /* reset controller */ | |
1629 | azx_reset(chip, full_reset); | |
1630 | ||
1631 | /* initialize interrupts */ | |
1632 | azx_int_clear(chip); | |
1633 | azx_int_enable(chip); | |
1634 | ||
1635 | /* initialize the codec command I/O */ | |
1636 | if (!chip->single_cmd) | |
1637 | azx_init_cmd_io(chip); | |
1638 | ||
1639 | /* program the position buffer */ | |
1640 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
1641 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); | |
1642 | ||
1643 | chip->initialized = 1; | |
1644 | } | |
1645 | EXPORT_SYMBOL_GPL(azx_init_chip); | |
1646 | ||
1647 | void azx_stop_chip(struct azx *chip) | |
1648 | { | |
1649 | if (!chip->initialized) | |
1650 | return; | |
1651 | ||
1652 | /* disable interrupts */ | |
1653 | azx_int_disable(chip); | |
1654 | azx_int_clear(chip); | |
1655 | ||
1656 | /* disable CORB/RIRB */ | |
1657 | azx_free_cmd_io(chip); | |
1658 | ||
1659 | /* disable position buffer */ | |
1660 | azx_writel(chip, DPLBASE, 0); | |
1661 | azx_writel(chip, DPUBASE, 0); | |
1662 | ||
1663 | chip->initialized = 0; | |
1664 | } | |
154867cf | 1665 | EXPORT_SYMBOL_GPL(azx_stop_chip); |
f43923ff | 1666 | |
f0b1df88 DR |
1667 | /* |
1668 | * interrupt handler | |
1669 | */ | |
1670 | irqreturn_t azx_interrupt(int irq, void *dev_id) | |
1671 | { | |
1672 | struct azx *chip = dev_id; | |
1673 | struct azx_dev *azx_dev; | |
1674 | u32 status; | |
1675 | u8 sd_status; | |
1676 | int i; | |
1677 | ||
1678 | #ifdef CONFIG_PM_RUNTIME | |
1679 | if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) | |
7b0a48f3 | 1680 | if (!pm_runtime_active(chip->card->dev)) |
f0b1df88 DR |
1681 | return IRQ_NONE; |
1682 | #endif | |
1683 | ||
1684 | spin_lock(&chip->reg_lock); | |
1685 | ||
1686 | if (chip->disabled) { | |
1687 | spin_unlock(&chip->reg_lock); | |
1688 | return IRQ_NONE; | |
1689 | } | |
1690 | ||
1691 | status = azx_readl(chip, INTSTS); | |
1692 | if (status == 0 || status == 0xffffffff) { | |
1693 | spin_unlock(&chip->reg_lock); | |
1694 | return IRQ_NONE; | |
1695 | } | |
1696 | ||
1697 | for (i = 0; i < chip->num_streams; i++) { | |
1698 | azx_dev = &chip->azx_dev[i]; | |
1699 | if (status & azx_dev->sd_int_sta_mask) { | |
1700 | sd_status = azx_sd_readb(chip, azx_dev, SD_STS); | |
1701 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); | |
1702 | if (!azx_dev->substream || !azx_dev->running || | |
1703 | !(sd_status & SD_INT_COMPLETE)) | |
1704 | continue; | |
1705 | /* check whether this IRQ is really acceptable */ | |
1706 | if (!chip->ops->position_check || | |
1707 | chip->ops->position_check(chip, azx_dev)) { | |
1708 | spin_unlock(&chip->reg_lock); | |
1709 | snd_pcm_period_elapsed(azx_dev->substream); | |
1710 | spin_lock(&chip->reg_lock); | |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | ||
1715 | /* clear rirb int */ | |
1716 | status = azx_readb(chip, RIRBSTS); | |
1717 | if (status & RIRB_INT_MASK) { | |
1718 | if (status & RIRB_INT_RESPONSE) { | |
1719 | if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) | |
1720 | udelay(80); | |
1721 | azx_update_rirb(chip); | |
1722 | } | |
1723 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
1724 | } | |
1725 | ||
1726 | spin_unlock(&chip->reg_lock); | |
1727 | ||
1728 | return IRQ_HANDLED; | |
1729 | } | |
1730 | EXPORT_SYMBOL_GPL(azx_interrupt); | |
1731 | ||
154867cf DR |
1732 | /* |
1733 | * Codec initerface | |
1734 | */ | |
1735 | ||
1736 | /* | |
1737 | * Probe the given codec address | |
1738 | */ | |
1739 | static int probe_codec(struct azx *chip, int addr) | |
1740 | { | |
1741 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
1742 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
1743 | unsigned int res; | |
1744 | ||
1745 | mutex_lock(&chip->bus->cmd_mutex); | |
1746 | chip->probing = 1; | |
1747 | azx_send_cmd(chip->bus, cmd); | |
1748 | res = azx_get_response(chip->bus, addr); | |
1749 | chip->probing = 0; | |
1750 | mutex_unlock(&chip->bus->cmd_mutex); | |
1751 | if (res == -1) | |
1752 | return -EIO; | |
1753 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); | |
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | static void azx_bus_reset(struct hda_bus *bus) | |
1758 | { | |
1759 | struct azx *chip = bus->private_data; | |
1760 | ||
1761 | bus->in_reset = 1; | |
1762 | azx_stop_chip(chip); | |
17c3ad03 | 1763 | azx_init_chip(chip, true); |
154867cf DR |
1764 | #ifdef CONFIG_PM |
1765 | if (chip->initialized) { | |
1766 | struct azx_pcm *p; | |
1767 | list_for_each_entry(p, &chip->pcm_list, list) | |
1768 | snd_pcm_suspend_all(p->pcm); | |
1769 | snd_hda_suspend(chip->bus); | |
1770 | snd_hda_resume(chip->bus); | |
1771 | } | |
1772 | #endif | |
1773 | bus->in_reset = 0; | |
1774 | } | |
1775 | ||
1776 | #ifdef CONFIG_PM | |
1777 | /* power-up/down the controller */ | |
1778 | static void azx_power_notify(struct hda_bus *bus, bool power_up) | |
1779 | { | |
1780 | struct azx *chip = bus->private_data; | |
1781 | ||
1782 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | |
1783 | return; | |
1784 | ||
1785 | if (power_up) | |
1786 | pm_runtime_get_sync(chip->card->dev); | |
1787 | else | |
1788 | pm_runtime_put_sync(chip->card->dev); | |
1789 | } | |
1790 | #endif | |
1791 | ||
1792 | static int get_jackpoll_interval(struct azx *chip) | |
1793 | { | |
1794 | int i; | |
1795 | unsigned int j; | |
1796 | ||
1797 | if (!chip->jackpoll_ms) | |
1798 | return 0; | |
1799 | ||
1800 | i = chip->jackpoll_ms[chip->dev_index]; | |
1801 | if (i == 0) | |
1802 | return 0; | |
1803 | if (i < 50 || i > 60000) | |
1804 | j = 0; | |
1805 | else | |
1806 | j = msecs_to_jiffies(i); | |
1807 | if (j == 0) | |
1808 | dev_warn(chip->card->dev, | |
1809 | "jackpoll_ms value out of range: %d\n", i); | |
1810 | return j; | |
1811 | } | |
1812 | ||
1813 | /* Codec initialization */ | |
1814 | int azx_codec_create(struct azx *chip, const char *model, | |
1815 | unsigned int max_slots, | |
1816 | int *power_save_to) | |
1817 | { | |
1818 | struct hda_bus_template bus_temp; | |
1819 | int c, codecs, err; | |
1820 | ||
1821 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
1822 | bus_temp.private_data = chip; | |
1823 | bus_temp.modelname = model; | |
1824 | bus_temp.pci = chip->pci; | |
1825 | bus_temp.ops.command = azx_send_cmd; | |
1826 | bus_temp.ops.get_response = azx_get_response; | |
1827 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; | |
1828 | bus_temp.ops.bus_reset = azx_bus_reset; | |
1829 | #ifdef CONFIG_PM | |
1830 | bus_temp.power_save = power_save_to; | |
1831 | bus_temp.ops.pm_notify = azx_power_notify; | |
1832 | #endif | |
1833 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
1834 | bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; | |
1835 | bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; | |
1836 | bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; | |
1837 | #endif | |
1838 | ||
1839 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); | |
1840 | if (err < 0) | |
1841 | return err; | |
1842 | ||
1843 | if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { | |
1844 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); | |
1845 | chip->bus->needs_damn_long_delay = 1; | |
1846 | } | |
1847 | ||
1848 | codecs = 0; | |
1849 | if (!max_slots) | |
1850 | max_slots = AZX_DEFAULT_CODECS; | |
1851 | ||
1852 | /* First try to probe all given codec slots */ | |
1853 | for (c = 0; c < max_slots; c++) { | |
1854 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { | |
1855 | if (probe_codec(chip, c) < 0) { | |
1856 | /* Some BIOSen give you wrong codec addresses | |
1857 | * that don't exist | |
1858 | */ | |
1859 | dev_warn(chip->card->dev, | |
1860 | "Codec #%d probe error; disabling it...\n", c); | |
1861 | chip->codec_mask &= ~(1 << c); | |
1862 | /* More badly, accessing to a non-existing | |
1863 | * codec often screws up the controller chip, | |
1864 | * and disturbs the further communications. | |
1865 | * Thus if an error occurs during probing, | |
1866 | * better to reset the controller chip to | |
1867 | * get back to the sanity state. | |
1868 | */ | |
1869 | azx_stop_chip(chip); | |
17c3ad03 | 1870 | azx_init_chip(chip, true); |
154867cf DR |
1871 | } |
1872 | } | |
1873 | } | |
1874 | ||
1875 | /* AMD chipsets often cause the communication stalls upon certain | |
1876 | * sequence like the pin-detection. It seems that forcing the synced | |
1877 | * access works around the stall. Grrr... | |
1878 | */ | |
1879 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { | |
1880 | dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); | |
1881 | chip->bus->sync_write = 1; | |
1882 | chip->bus->allow_bus_reset = 1; | |
1883 | } | |
1884 | ||
1885 | /* Then create codec instances */ | |
1886 | for (c = 0; c < max_slots; c++) { | |
1887 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { | |
1888 | struct hda_codec *codec; | |
1889 | err = snd_hda_codec_new(chip->bus, c, &codec); | |
1890 | if (err < 0) | |
1891 | continue; | |
1892 | codec->jackpoll_interval = get_jackpoll_interval(chip); | |
1893 | codec->beep_mode = chip->beep_mode; | |
1894 | codecs++; | |
1895 | } | |
1896 | } | |
1897 | if (!codecs) { | |
1898 | dev_err(chip->card->dev, "no codecs initialized\n"); | |
1899 | return -ENXIO; | |
1900 | } | |
1901 | return 0; | |
1902 | } | |
1903 | EXPORT_SYMBOL_GPL(azx_codec_create); | |
1904 | ||
1905 | /* configure each codec instance */ | |
1906 | int azx_codec_configure(struct azx *chip) | |
1907 | { | |
1908 | struct hda_codec *codec; | |
1909 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
1910 | snd_hda_codec_configure(codec); | |
1911 | } | |
1912 | return 0; | |
1913 | } | |
1914 | EXPORT_SYMBOL_GPL(azx_codec_configure); | |
1915 | ||
1916 | /* mixer creation - all stuff is implemented in hda module */ | |
1917 | int azx_mixer_create(struct azx *chip) | |
1918 | { | |
1919 | return snd_hda_build_controls(chip->bus); | |
1920 | } | |
1921 | EXPORT_SYMBOL_GPL(azx_mixer_create); | |
1922 | ||
1923 | ||
1924 | /* initialize SD streams */ | |
1925 | int azx_init_stream(struct azx *chip) | |
1926 | { | |
1927 | int i; | |
1928 | ||
1929 | /* initialize each stream (aka device) | |
1930 | * assign the starting bdl address to each stream (device) | |
1931 | * and initialize | |
1932 | */ | |
1933 | for (i = 0; i < chip->num_streams; i++) { | |
1934 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1935 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); | |
1936 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
1937 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1938 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1939 | azx_dev->sd_int_sta_mask = 1 << i; | |
1940 | /* stream tag: must be non-zero and unique */ | |
1941 | azx_dev->index = i; | |
1942 | azx_dev->stream_tag = i + 1; | |
1943 | } | |
1944 | ||
1945 | return 0; | |
1946 | } | |
1947 | EXPORT_SYMBOL_GPL(azx_init_stream); | |
1948 | ||
05e84878 DR |
1949 | MODULE_LICENSE("GPL"); |
1950 | MODULE_DESCRIPTION("Common HDA driver funcitons"); |