[deliverable/linux.git] / sound / pci / hda / hda_i915.c

/*
 *  hda_i915.c - routines for Haswell HDA controller power well support
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software Foundation,
 *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <sound/core.h>
#include <drm/i915_powerwell.h>
#include "hda_priv.h"
#include "hda_i915.h"

/* Intel HSW/BDW display HDA controller Extended Mode registers.
 * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
 * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
 * The values will be lost when the display power well is disabled.
 */
#define AZX_REG_EM4			0x100c
#define AZX_REG_EM5			0x1010

static int (*get_power)(void);
static int (*put_power)(void);
static int (*get_cdclk)(void);

int hda_display_power(bool enable)
{
	if (!get_power || !put_power)
		return -ENODEV;

	pr_debug("HDA display power %s \n",
			enable ? "Enable" : "Disable");
	if (enable)
		return get_power();
	else
		return put_power();
}

void haswell_set_bclk(struct azx *chip)
{
	int cdclk_freq;
	unsigned int bclk_m, bclk_n;

	if (!get_cdclk)
		return;

	cdclk_freq = get_cdclk();
	switch (cdclk_freq) {
	case 337500:
		bclk_m = 16;
		bclk_n = 225;
		break;

	case 450000:
	default: /* default CDCLK 450MHz */
		bclk_m = 4;
		bclk_n = 75;
		break;

	case 540000:
		bclk_m = 4;
		bclk_n = 90;
		break;

	case 675000:
		bclk_m = 8;
		bclk_n = 225;
		break;
	}

	azx_writew(chip, EM4, bclk_m);
	azx_writew(chip, EM5, bclk_n);
}


int hda_i915_init(void)
{
	int err = 0;

	get_power = symbol_request(i915_request_power_well);
	if (!get_power) {
		pr_warn("hda-i915: get_power symbol get fail\n");
		return -ENODEV;
	}

	put_power = symbol_request(i915_release_power_well);
	if (!put_power) {
		symbol_put(i915_request_power_well);
		get_power = NULL;
		return -ENODEV;
	}

	get_cdclk = symbol_request(i915_get_cdclk_freq);
	if (!get_cdclk)	/* may have abnormal BCLK and audio playback rate */
		pr_warn("hda-i915: get_cdclk symbol get fail\n");

	pr_debug("HDA driver get symbol successfully from i915 module\n");

	return err;
}

int hda_i915_exit(void)
{
	if (get_power) {
		symbol_put(i915_request_power_well);
		get_power = NULL;
	}
	if (put_power) {
		symbol_put(i915_release_power_well);
		put_power = NULL;
	}
	if (get_cdclk) {
		symbol_put(i915_get_cdclk_freq);
		get_cdclk = NULL;
	}

	return 0;
}
Commit	Line	Data
99a2008d WX	1	/*
	2	* hda_i915.c - routines for Haswell HDA controller power well support
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	11	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software Foundation,
	16	* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/module.h>
	21	#include <sound/core.h>
	22	#include <drm/i915_powerwell.h>
e4d9e513	23	#include "hda_priv.h"
99a2008d WX	24	#include "hda_i915.h"
99a2008d WX	25
e4d9e513 ML	26	/* Intel HSW/BDW display HDA controller Extended Mode registers.
	27	* EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
	28	* Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
	29	* The values will be lost when the display power well is disabled.
	30	*/
1a0e3f96 TI	31	#define AZX_REG_EM4 0x100c
1a0e3f96 TI	32	#define AZX_REG_EM5 0x1010
e4d9e513	33
74b0c2d7 TI	34	static int (*get_power)(void);
74b0c2d7 TI	35	static int (*put_power)(void);
e4d9e513	36	static int (*get_cdclk)(void);
99a2008d	37
74b0c2d7	38	int hda_display_power(bool enable)
99a2008d WX	39	{
99a2008d WX	40	if (!get_power \|\| !put_power)
74b0c2d7	41	return -ENODEV;
99a2008d	42
4e76a883	43	pr_debug("HDA display power %s \n",
99a2008d WX	44	enable ? "Enable" : "Disable");
99a2008d WX	45	if (enable)
74b0c2d7	46	return get_power();
99a2008d	47	else
74b0c2d7	48	return put_power();
99a2008d WX	49	}
99a2008d WX	50
e4d9e513 ML	51	void haswell_set_bclk(struct azx *chip)
	52	{
	53	int cdclk_freq;
	54	unsigned int bclk_m, bclk_n;
	55
	56	if (!get_cdclk)
	57	return;
	58
	59	cdclk_freq = get_cdclk();
	60	switch (cdclk_freq) {
	61	case 337500:
	62	bclk_m = 16;
	63	bclk_n = 225;
	64	break;
	65
	66	case 450000:
	67	default: /* default CDCLK 450MHz */
	68	bclk_m = 4;
	69	bclk_n = 75;
	70	break;
	71
	72	case 540000:
	73	bclk_m = 4;
	74	bclk_n = 90;
	75	break;
	76
	77	case 675000:
	78	bclk_m = 8;
	79	bclk_n = 225;
	80	break;
	81	}
	82
	83	azx_writew(chip, EM4, bclk_m);
	84	azx_writew(chip, EM5, bclk_n);
	85	}
	86
	87
99a2008d WX	88	int hda_i915_init(void)
	89	{
	90	int err = 0;
	91
	92	get_power = symbol_request(i915_request_power_well);
	93	if (!get_power) {
4e76a883	94	pr_warn("hda-i915: get_power symbol get fail\n");
99a2008d WX	95	return -ENODEV;
	96	}
	97
	98	put_power = symbol_request(i915_release_power_well);
	99	if (!put_power) {
	100	symbol_put(i915_request_power_well);
	101	get_power = NULL;
	102	return -ENODEV;
	103	}
	104
e4d9e513 ML	105	get_cdclk = symbol_request(i915_get_cdclk_freq);
	106	if (!get_cdclk) /* may have abnormal BCLK and audio playback rate */
	107	pr_warn("hda-i915: get_cdclk symbol get fail\n");
	108
4e76a883	109	pr_debug("HDA driver get symbol successfully from i915 module\n");
99a2008d WX	110
	111	return err;
	112	}
	113
	114	int hda_i915_exit(void)
	115	{
	116	if (get_power) {
	117	symbol_put(i915_request_power_well);
	118	get_power = NULL;
	119	}
	120	if (put_power) {
	121	symbol_put(i915_release_power_well);
	122	put_power = NULL;
	123	}
e4d9e513 ML	124	if (get_cdclk) {
	125	symbol_put(i915_get_cdclk_freq);
	126	get_cdclk = NULL;
	127	}
99a2008d WX	128
	129	return 0;
	130	}