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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
2538a4f5 65#include "hda_priv.h"
e4d9e513 66#include "hda_i915.h"
1da177e4 67
b6050ef6
TI		 68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
9a34af4a
TI		 77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
33124929
TI		 97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
1da177e4 114
5aba4f8e
TI		 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 118static char *model[SNDRV_CARDS];
1dac6695 119static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 120static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 121static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 122static int probe_only[SNDRV_CARDS];
26a6cb6c 123static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 124static bool single_cmd;
71623855 125static int enable_msi = -1;
4ea6fbc8
TI		 126#ifdef CONFIG_SND_HDA_PATCH_LOADER
127static char *patch[SNDRV_CARDS];
128#endif
2dca0bba 129#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 130static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132#endif
1da177e4 133
5aba4f8e 134module_param_array(index, int, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 136module_param_array(id, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 138module_param_array(enable, bool, NULL, 0444);
139MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140module_param_array(model, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 142module_param_array(position_fix, int, NULL, 0444);
4cb36310 143MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 145module_param_array(bdl_pos_adj, int, NULL, 0644);
146MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 147module_param_array(probe_mask, int, NULL, 0444);
606ad75f 148MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 149module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 150MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 151module_param_array(jackpoll_ms, int, NULL, 0444);
152MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 153module_param(single_cmd, bool, 0444);
d01ce99f
TI		 154MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
ac9ef6cf 156module_param(enable_msi, bint, 0444);
134a11f0 157MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 158#ifdef CONFIG_SND_HDA_PATCH_LOADER
159module_param_array(patch, charp, NULL, 0444);
160MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161#endif
2dca0bba 162#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 163module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 164MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 165 "(0=off, 1=on) (default=1).");
2dca0bba 166#endif
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d
TI		 169static int param_set_xint(const char *val, const struct kernel_param *kp);
170static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 177static int *power_save_addr = &power_save;
65fcd41d 178module_param(power_save, xint, 0644);
fee2fba3
TI		 179MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
1da177e4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 189#else
190static int *power_save_addr;
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
c8b00fd2 221 "{Intel, SPT},"
b4565913 222 "{Intel, SPT_LP},"
e926f2c8 223 "{Intel, HPT},"
cea310e8 224 "{Intel, PBG},"
4979bca9 225 "{Intel, SCH},"
fc20a562 226 "{ATI, SB450},"
89be83f8 227 "{ATI, SB600},"
778b6e1b 228 "{ATI, RS600},"
5b15c95f 229 "{ATI, RS690},"
e6db1119
WL		 230 "{ATI, RS780},"
231 "{ATI, R600},"
2797f724
HRK		 232 "{ATI, RV630},"
233 "{ATI, RV610},"
27da1834
WL		 234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
fc20a562 238 "{VIA, VT8251},"
47672310 239 "{VIA, VT8237A},"
07e4ca50
TI		 240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
1da177e4
LT		 242MODULE_DESCRIPTION("Intel HDA driver");
243
a82d51ed 244#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 245#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 246#define SUPPORT_VGA_SWITCHEROO
247#endif
248#endif
249
250
1da177e4 251/*
1da177e4 252 */
1da177e4 253
07e4ca50
TI		 254/* driver types */
255enum {
256 AZX_DRIVER_ICH,
32679f95 257 AZX_DRIVER_PCH,
4979bca9 258 AZX_DRIVER_SCH,
fab1285a 259 AZX_DRIVER_HDMI,
07e4ca50 260 AZX_DRIVER_ATI,
778b6e1b 261 AZX_DRIVER_ATIHDMI,
1815b34a 262 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
da3fca21 266 AZX_DRIVER_NVIDIA,
f269002e 267 AZX_DRIVER_TERA,
14d34f16 268 AZX_DRIVER_CTX,
5ae763b1 269 AZX_DRIVER_CTHDA,
c563f473 270 AZX_DRIVER_CMEDIA,
c4da29ca 271 AZX_DRIVER_GENERIC,
2f5983f2 272 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 273};
274
37e661ee
TI		 275#define azx_get_snoop_type(chip) \
276 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
277#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
278
b42b4afb
TI		 279/* quirks for old Intel chipsets */
280#define AZX_DCAPS_INTEL_ICH \
103884a3 281 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 282
2ea3c6a2 283/* quirks for Intel PCH */
d7dab4db 284#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 285 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 286 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 287
288#define AZX_DCAPS_INTEL_PCH \
289 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 290
33499a15 291#define AZX_DCAPS_INTEL_HASWELL \
103884a3 292 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 293 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
294 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 295
54a0405d
LY		 296/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
297#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 298 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 299 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
300 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 301
9477c58e
TI		 302/* quirks for ATI SB / AMD Hudson */
303#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 304 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
305 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 306
307/* quirks for ATI/AMD HDMI */
308#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
310 AZX_DCAPS_NO_MSI64)
9477c58e 311
37e661ee
TI		 312/* quirks for ATI HDMI with snoop off */
313#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
314 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
315
9477c58e
TI		 316/* quirks for Nvidia */
317#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 318 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 319 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
320 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 321
5ae763b1 322#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 323 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
324 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 325
a82d51ed
TI		 326/*
327 * VGA-switcher support
328 */
329#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 330#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
331#else
332#define use_vga_switcheroo(chip) 0
333#endif
334
48c8b0eb 335static char *driver_short_names[] = {
07e4ca50 336 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 337 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 338 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 339 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 340 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 341 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 342 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 343 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
344 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 345 [AZX_DRIVER_ULI] = "HDA ULI M5461",
346 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 347 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 348 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 349 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 350 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 351 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 352};
353
a07187c9
ML		 354struct hda_intel {
355 struct azx chip;
356
9a34af4a
TI		 357 /* for pending irqs */
358 struct work_struct irq_pending_work;
359
360 /* sync probing */
361 struct completion probe_wait;
362 struct work_struct probe_work;
363
364 /* card list (for power_save trigger) */
365 struct list_head list;
366
367 /* extra flags */
368 unsigned int irq_pending_warned:1;
369
370 /* VGA-switcheroo setup */
371 unsigned int use_vga_switcheroo:1;
372 unsigned int vga_switcheroo_registered:1;
373 unsigned int init_failed:1; /* delayed init failed */
374
375 /* secondary power domain for hdmi audio under vga device */
376 struct dev_pm_domain hdmi_pm_domain;
377};
a07187c9 378
27fe48d9 379#ifdef CONFIG_X86
9ddf1aeb 380static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 381{
9ddf1aeb
TI		 382 int pages;
383
27fe48d9
TI		 384 if (azx_snoop(chip))
385 return;
9ddf1aeb
TI		 386 if (!dmab || !dmab->area || !dmab->bytes)
387 return;
388
389#ifdef CONFIG_SND_DMA_SGBUF
390 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
391 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 392 if (chip->driver_type == AZX_DRIVER_CMEDIA)
393 return; /* deal with only CORB/RIRB buffers */
27fe48d9 394 if (on)
9ddf1aeb 395 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 396 else
9ddf1aeb
TI		 397 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
398 return;
27fe48d9 399 }
9ddf1aeb
TI		 400#endif
401
402 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
403 if (on)
404 set_memory_wc((unsigned long)dmab->area, pages);
405 else
406 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 407}
408
409static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
410 bool on)
411{
9ddf1aeb 412 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 413}
414static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 415 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 416{
417 if (azx_dev->wc_marked != on) {
9ddf1aeb 418 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 419 azx_dev->wc_marked = on;
420 }
421}
422#else
423/* NOP for other archs */
424static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
425 bool on)
426{
427}
428static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 429 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 430{
431}
432#endif
433
68e7fffc 434static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 435
cb53c626
TI		 436/*
437 * initialize the PCI registers
438 */
439/* update bits in a PCI register byte */
440static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
441 unsigned char mask, unsigned char val)
442{
443 unsigned char data;
444
445 pci_read_config_byte(pci, reg, &data);
446 data &= ~mask;
447 data |= (val & mask);
448 pci_write_config_byte(pci, reg, data);
449}
450
451static void azx_init_pci(struct azx *chip)
452{
37e661ee
TI		 453 int snoop_type = azx_get_snoop_type(chip);
454
cb53c626
TI		 455 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
456 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
457 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 458 * codecs.
459 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 460 */
46f2cc80 461 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 462 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 463 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 464 }
cb53c626 465
9477c58e
TI		 466 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
467 * we need to enable snoop.
468 */
37e661ee 469 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 470 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
471 azx_snoop(chip));
cb53c626 472 update_pci_byte(chip->pci,
27fe48d9
TI		 473 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
474 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 475 }
476
477 /* For NVIDIA HDA, enable snoop */
37e661ee 478 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 479 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
480 azx_snoop(chip));
cb53c626
TI		 481 update_pci_byte(chip->pci,
482 NVIDIA_HDA_TRANSREG_ADDR,
483 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 484 update_pci_byte(chip->pci,
485 NVIDIA_HDA_ISTRM_COH,
486 0x01, NVIDIA_HDA_ENABLE_COHBIT);
487 update_pci_byte(chip->pci,
488 NVIDIA_HDA_OSTRM_COH,
489 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 490 }
491
492 /* Enable SCH/PCH snoop if needed */
37e661ee 493 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 494 unsigned short snoop;
90a5ad52 495 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 496 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
497 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
498 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
499 if (!azx_snoop(chip))
500 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
501 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 502 pci_read_config_word(chip->pci,
503 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 504 }
4e76a883
TI		 505 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
506 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
507 "Disabled" : "Enabled");
da3fca21 508 }
1da177e4
LT		 509}
510
b6050ef6
TI		 511/* calculate runtime delay from LPIB */
512static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
513 unsigned int pos)
514{
515 struct snd_pcm_substream *substream = azx_dev->substream;
516 int stream = substream->stream;
517 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
518 int delay;
519
520 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
521 delay = pos - lpib_pos;
522 else
523 delay = lpib_pos - pos;
524 if (delay < 0) {
525 if (delay >= azx_dev->delay_negative_threshold)
526 delay = 0;
527 else
528 delay += azx_dev->bufsize;
529 }
530
531 if (delay >= azx_dev->period_bytes) {
532 dev_info(chip->card->dev,
533 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
534 delay, azx_dev->period_bytes);
535 delay = 0;
536 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
537 chip->get_delay[stream] = NULL;
538 }
539
540 return bytes_to_frames(substream->runtime, delay);
541}
542
9ad593f6
TI		 543static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
544
7ca954a8
DR		 545/* called from IRQ */
546static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
547{
9a34af4a 548 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 549 int ok;
550
551 ok = azx_position_ok(chip, azx_dev);
552 if (ok == 1) {
553 azx_dev->irq_pending = 0;
554 return ok;
555 } else if (ok == 0 && chip->bus && chip->bus->workq) {
556 /* bogus IRQ, process it later */
557 azx_dev->irq_pending = 1;
9a34af4a 558 queue_work(chip->bus->workq, &hda->irq_pending_work);
7ca954a8
DR		 559 }
560 return 0;
561}
562
9ad593f6
TI		 563/*
564 * Check whether the current DMA position is acceptable for updating
565 * periods. Returns non-zero if it's OK.
566 *
567 * Many HD-audio controllers appear pretty inaccurate about
568 * the update-IRQ timing. The IRQ is issued before actually the
569 * data is processed. So, we need to process it afterwords in a
570 * workqueue.
571 */
572static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
573{
b6050ef6
TI		 574 struct snd_pcm_substream *substream = azx_dev->substream;
575 int stream = substream->stream;
e5463720 576 u32 wallclk;
9ad593f6
TI		 577 unsigned int pos;
578
f48f606d
JK		 579 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
580 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 581 return -1; /* bogus (too early) interrupt */
fa00e046 582
b6050ef6
TI		 583 if (chip->get_position[stream])
584 pos = chip->get_position[stream](chip, azx_dev);
585 else { /* use the position buffer as default */
586 pos = azx_get_pos_posbuf(chip, azx_dev);
587 if (!pos || pos == (u32)-1) {
588 dev_info(chip->card->dev,
589 "Invalid position buffer, using LPIB read method instead.\n");
590 chip->get_position[stream] = azx_get_pos_lpib;
591 pos = azx_get_pos_lpib(chip, azx_dev);
592 chip->get_delay[stream] = NULL;
593 } else {
594 chip->get_position[stream] = azx_get_pos_posbuf;
595 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
596 chip->get_delay[stream] = azx_get_delay_from_lpib;
597 }
598 }
599
600 if (pos >= azx_dev->bufsize)
601 pos = 0;
9ad593f6 602
d6d8bf54
TI		 603 if (WARN_ONCE(!azx_dev->period_bytes,
604 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 605 return -1; /* this shouldn't happen! */
edb39935 606 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 607 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
608 /* NG - it's below the first next period boundary */
9cdc0115 609 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 610 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 611 return 1; /* OK, it's fine */
612}
613
614/*
615 * The work for pending PCM period updates.
616 */
617static void azx_irq_pending_work(struct work_struct *work)
618{
9a34af4a
TI		 619 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
620 struct azx *chip = &hda->chip;
e5463720 621 int i, pending, ok;
9ad593f6 622
9a34af4a 623 if (!hda->irq_pending_warned) {
4e76a883
TI		 624 dev_info(chip->card->dev,
625 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
626 chip->card->number);
9a34af4a 627 hda->irq_pending_warned = 1;
a6a950a8
TI		 628 }
629
9ad593f6
TI		 630 for (;;) {
631 pending = 0;
632 spin_lock_irq(&chip->reg_lock);
633 for (i = 0; i < chip->num_streams; i++) {
634 struct azx_dev *azx_dev = &chip->azx_dev[i];
635 if (!azx_dev->irq_pending ||
636 !azx_dev->substream ||
637 !azx_dev->running)
638 continue;
e5463720
JK		 639 ok = azx_position_ok(chip, azx_dev);
640 if (ok > 0) {
9ad593f6
TI		 641 azx_dev->irq_pending = 0;
642 spin_unlock(&chip->reg_lock);
643 snd_pcm_period_elapsed(azx_dev->substream);
644 spin_lock(&chip->reg_lock);
e5463720
JK		 645 } else if (ok < 0) {
646 pending = 0; /* too early */
9ad593f6
TI		 647 } else
648 pending++;
649 }
650 spin_unlock_irq(&chip->reg_lock);
651 if (!pending)
652 return;
08af495f 653 msleep(1);
9ad593f6
TI		 654 }
655}
656
657/* clear irq_pending flags and assure no on-going workq */
658static void azx_clear_irq_pending(struct azx *chip)
659{
660 int i;
661
662 spin_lock_irq(&chip->reg_lock);
663 for (i = 0; i < chip->num_streams; i++)
664 chip->azx_dev[i].irq_pending = 0;
665 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 666}
667
68e7fffc
TI		 668static int azx_acquire_irq(struct azx *chip, int do_disconnect)
669{
437a5a46
TI		 670 if (request_irq(chip->pci->irq, azx_interrupt,
671 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 672 KBUILD_MODNAME, chip)) {
4e76a883
TI		 673 dev_err(chip->card->dev,
674 "unable to grab IRQ %d, disabling device\n",
675 chip->pci->irq);
68e7fffc
TI		 676 if (do_disconnect)
677 snd_card_disconnect(chip->card);
678 return -1;
679 }
680 chip->irq = chip->pci->irq;
69e13418 681 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 682 return 0;
683}
684
b6050ef6
TI		 685/* get the current DMA position with correction on VIA chips */
686static unsigned int azx_via_get_position(struct azx *chip,
687 struct azx_dev *azx_dev)
688{
689 unsigned int link_pos, mini_pos, bound_pos;
690 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
691 unsigned int fifo_size;
692
693 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
694 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
695 /* Playback, no problem using link position */
696 return link_pos;
697 }
698
699 /* Capture */
700 /* For new chipset,
701 * use mod to get the DMA position just like old chipset
702 */
703 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
704 mod_dma_pos %= azx_dev->period_bytes;
705
706 /* azx_dev->fifo_size can't get FIFO size of in stream.
707 * Get from base address + offset.
708 */
709 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
710
711 if (azx_dev->insufficient) {
712 /* Link position never gather than FIFO size */
713 if (link_pos <= fifo_size)
714 return 0;
715
716 azx_dev->insufficient = 0;
717 }
718
719 if (link_pos <= fifo_size)
720 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
721 else
722 mini_pos = link_pos - fifo_size;
723
724 /* Find nearest previous boudary */
725 mod_mini_pos = mini_pos % azx_dev->period_bytes;
726 mod_link_pos = link_pos % azx_dev->period_bytes;
727 if (mod_link_pos >= fifo_size)
728 bound_pos = link_pos - mod_link_pos;
729 else if (mod_dma_pos >= mod_mini_pos)
730 bound_pos = mini_pos - mod_mini_pos;
731 else {
732 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
733 if (bound_pos >= azx_dev->bufsize)
734 bound_pos = 0;
735 }
736
737 /* Calculate real DMA position we want */
738 return bound_pos + mod_dma_pos;
739}
740
83012a7c 741#ifdef CONFIG_PM
65fcd41d
TI		 742static DEFINE_MUTEX(card_list_lock);
743static LIST_HEAD(card_list);
744
745static void azx_add_card_list(struct azx *chip)
746{
9a34af4a 747 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 748 mutex_lock(&card_list_lock);
9a34af4a 749 list_add(&hda->list, &card_list);
65fcd41d
TI		 750 mutex_unlock(&card_list_lock);
751}
752
753static void azx_del_card_list(struct azx *chip)
754{
9a34af4a 755 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 756 mutex_lock(&card_list_lock);
9a34af4a 757 list_del_init(&hda->list);
65fcd41d
TI		 758 mutex_unlock(&card_list_lock);
759}
760
761/* trigger power-save check at writing parameter */
762static int param_set_xint(const char *val, const struct kernel_param *kp)
763{
9a34af4a 764 struct hda_intel *hda;
65fcd41d
TI		 765 struct azx *chip;
766 struct hda_codec *c;
767 int prev = power_save;
768 int ret = param_set_int(val, kp);
769
770 if (ret || prev == power_save)
771 return ret;
772
773 mutex_lock(&card_list_lock);
9a34af4a
TI		 774 list_for_each_entry(hda, &card_list, list) {
775 chip = &hda->chip;
65fcd41d
TI		 776 if (!chip->bus || chip->disabled)
777 continue;
778 list_for_each_entry(c, &chip->bus->codec_list, list)
779 snd_hda_power_sync(c);
780 }
781 mutex_unlock(&card_list_lock);
782 return 0;
783}
784#else
785#define azx_add_card_list(chip) /* NOP */
786#define azx_del_card_list(chip) /* NOP */
83012a7c 787#endif /* CONFIG_PM */
5c0b9bec 788
7ccbde57 789#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 790/*
791 * power management
792 */
68cb2b55 793static int azx_suspend(struct device *dev)
1da177e4 794{
68cb2b55
TI		 795 struct pci_dev *pci = to_pci_dev(dev);
796 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 797 struct azx *chip;
798 struct hda_intel *hda;
01b65bfb 799 struct azx_pcm *p;
1da177e4 800
2d9772ef
TI		 801 if (!card)
802 return 0;
803
804 chip = card->private_data;
805 hda = container_of(chip, struct hda_intel, chip);
1618e84a 806 if (chip->disabled || hda->init_failed)
c5c21523
TI		 807 return 0;
808
421a1252 809 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 810 azx_clear_irq_pending(chip);
01b65bfb
TI		 811 list_for_each_entry(p, &chip->pcm_list, list)
812 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 813 if (chip->initialized)
8dd78330 814 snd_hda_suspend(chip->bus);
cb53c626 815 azx_stop_chip(chip);
7295b264 816 azx_enter_link_reset(chip);
30b35399 817 if (chip->irq >= 0) {
43001c95 818 free_irq(chip->irq, chip);
30b35399
TI		 819 chip->irq = -1;
820 }
a07187c9 821
68e7fffc 822 if (chip->msi)
43001c95 823 pci_disable_msi(chip->pci);
421a1252
TI		 824 pci_disable_device(pci);
825 pci_save_state(pci);
68cb2b55 826 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 827 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
828 hda_display_power(false);
1da177e4
LT		 829 return 0;
830}
831
68cb2b55 832static int azx_resume(struct device *dev)
1da177e4 833{
68cb2b55
TI		 834 struct pci_dev *pci = to_pci_dev(dev);
835 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 836 struct azx *chip;
837 struct hda_intel *hda;
838
839 if (!card)
840 return 0;
1da177e4 841
2d9772ef
TI		 842 chip = card->private_data;
843 hda = container_of(chip, struct hda_intel, chip);
1618e84a 844 if (chip->disabled || hda->init_failed)
c5c21523
TI		 845 return 0;
846
a07187c9 847 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 848 hda_display_power(true);
e4d9e513 849 haswell_set_bclk(chip);
a07187c9 850 }
d14a7e0b
TI		 851 pci_set_power_state(pci, PCI_D0);
852 pci_restore_state(pci);
30b35399 853 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 854 dev_err(chip->card->dev,
855 "pci_enable_device failed, disabling device\n");
30b35399
TI		 856 snd_card_disconnect(card);
857 return -EIO;
858 }
859 pci_set_master(pci);
68e7fffc
TI		 860 if (chip->msi)
861 if (pci_enable_msi(pci) < 0)
862 chip->msi = 0;
863 if (azx_acquire_irq(chip, 1) < 0)
30b35399 864 return -EIO;
cb53c626 865 azx_init_pci(chip);
d804ad92 866
17c3ad03 867 azx_init_chip(chip, true);
d804ad92 868
1da177e4 869 snd_hda_resume(chip->bus);
421a1252 870 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 871 return 0;
872}
b8dfc462
ML		 873#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
874
641d334b 875#ifdef CONFIG_PM
b8dfc462
ML		 876static int azx_runtime_suspend(struct device *dev)
877{
878 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 879 struct azx *chip;
880 struct hda_intel *hda;
b8dfc462 881
2d9772ef
TI		 882 if (!card)
883 return 0;
884
885 chip = card->private_data;
886 hda = container_of(chip, struct hda_intel, chip);
1618e84a 887 if (chip->disabled || hda->init_failed)
246efa4a
DA		 888 return 0;
889
890 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
891 return 0;
892
7d4f606c
WX		 893 /* enable controller wake up event */
894 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
895 STATESTS_INT_MASK);
896
b8dfc462 897 azx_stop_chip(chip);
873ce8ad 898 azx_enter_link_reset(chip);
b8dfc462 899 azx_clear_irq_pending(chip);
e4d9e513 900 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d 901 hda_display_power(false);
e4d9e513 902
b8dfc462
ML		 903 return 0;
904}
905
906static int azx_runtime_resume(struct device *dev)
907{
908 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 909 struct azx *chip;
910 struct hda_intel *hda;
7d4f606c
WX		 911 struct hda_bus *bus;
912 struct hda_codec *codec;
913 int status;
b8dfc462 914
2d9772ef
TI		 915 if (!card)
916 return 0;
917
918 chip = card->private_data;
919 hda = container_of(chip, struct hda_intel, chip);
1618e84a 920 if (chip->disabled || hda->init_failed)
246efa4a
DA		 921 return 0;
922
923 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
924 return 0;
925
a07187c9 926 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 927 hda_display_power(true);
e4d9e513 928 haswell_set_bclk(chip);
a07187c9 929 }
7d4f606c
WX		 930
931 /* Read STATESTS before controller reset */
932 status = azx_readw(chip, STATESTS);
933
b8dfc462 934 azx_init_pci(chip);
17c3ad03 935 azx_init_chip(chip, true);
7d4f606c
WX		 936
937 bus = chip->bus;
938 if (status && bus) {
939 list_for_each_entry(codec, &bus->codec_list, list)
940 if (status & (1 << codec->addr))
941 queue_delayed_work(codec->bus->workq,
942 &codec->jackpoll_work, codec->jackpoll_interval);
943 }
944
945 /* disable controller Wake Up event*/
946 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
947 ~STATESTS_INT_MASK);
948
b8dfc462
ML		 949 return 0;
950}
6eb827d2
TI		 951
952static int azx_runtime_idle(struct device *dev)
953{
954 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 955 struct azx *chip;
956 struct hda_intel *hda;
957
958 if (!card)
959 return 0;
6eb827d2 960
2d9772ef
TI		 961 chip = card->private_data;
962 hda = container_of(chip, struct hda_intel, chip);
1618e84a 963 if (chip->disabled || hda->init_failed)
246efa4a
DA		 964 return 0;
965
6eb827d2
TI		 966 if (!power_save_controller ||
967 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
968 return -EBUSY;
969
970 return 0;
971}
972
b8dfc462
ML		 973static const struct dev_pm_ops azx_pm = {
974 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 975 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 976};
977
68cb2b55
TI		 978#define AZX_PM_OPS &azx_pm
979#else
68cb2b55 980#define AZX_PM_OPS NULL
b8dfc462 981#endif /* CONFIG_PM */
1da177e4
LT		 982
983
48c8b0eb 984static int azx_probe_continue(struct azx *chip);
a82d51ed 985
8393ec4a 986#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 987static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 988
a82d51ed
TI		 989static void azx_vs_set_state(struct pci_dev *pci,
990 enum vga_switcheroo_state state)
991{
992 struct snd_card *card = pci_get_drvdata(pci);
993 struct azx *chip = card->private_data;
9a34af4a 994 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 995 bool disabled;
996
9a34af4a
TI		 997 wait_for_completion(&hda->probe_wait);
998 if (hda->init_failed)
a82d51ed
TI		 999 return;
1000
1001 disabled = (state == VGA_SWITCHEROO_OFF);
1002 if (chip->disabled == disabled)
1003 return;
1004
1005 if (!chip->bus) {
1006 chip->disabled = disabled;
1007 if (!disabled) {
4e76a883
TI		 1008 dev_info(chip->card->dev,
1009 "Start delayed initialization\n");
5c90680e 1010 if (azx_probe_continue(chip) < 0) {
4e76a883 1011 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1012 hda->init_failed = true;
a82d51ed
TI		 1013 }
1014 }
1015 } else {
4e76a883
TI		 1016 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1017 disabled ? "Disabling" : "Enabling");
a82d51ed 1018 if (disabled) {
8928756d
DR		 1019 pm_runtime_put_sync_suspend(card->dev);
1020 azx_suspend(card->dev);
246efa4a
DA		 1021 /* when we get suspended by vga switcheroo we end up in D3cold,
1022 * however we have no ACPI handle, so pci/acpi can't put us there,
1023 * put ourselves there */
1024 pci->current_state = PCI_D3cold;
a82d51ed 1025 chip->disabled = true;
128960a9 1026 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1027 dev_warn(chip->card->dev,
1028 "Cannot lock devices!\n");
a82d51ed
TI		 1029 } else {
1030 snd_hda_unlock_devices(chip->bus);
8928756d 1031 pm_runtime_get_noresume(card->dev);
a82d51ed 1032 chip->disabled = false;
8928756d 1033 azx_resume(card->dev);
a82d51ed
TI		 1034 }
1035 }
1036}
1037
1038static bool azx_vs_can_switch(struct pci_dev *pci)
1039{
1040 struct snd_card *card = pci_get_drvdata(pci);
1041 struct azx *chip = card->private_data;
9a34af4a 1042 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1043
9a34af4a
TI		 1044 wait_for_completion(&hda->probe_wait);
1045 if (hda->init_failed)
a82d51ed
TI		 1046 return false;
1047 if (chip->disabled || !chip->bus)
1048 return true;
1049 if (snd_hda_lock_devices(chip->bus))
1050 return false;
1051 snd_hda_unlock_devices(chip->bus);
1052 return true;
1053}
1054
e23e7a14 1055static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1056{
9a34af4a 1057 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1058 struct pci_dev *p = get_bound_vga(chip->pci);
1059 if (p) {
4e76a883
TI		 1060 dev_info(chip->card->dev,
1061 "Handle VGA-switcheroo audio client\n");
9a34af4a 1062 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1063 pci_dev_put(p);
1064 }
1065}
1066
1067static const struct vga_switcheroo_client_ops azx_vs_ops = {
1068 .set_gpu_state = azx_vs_set_state,
1069 .can_switch = azx_vs_can_switch,
1070};
1071
e23e7a14 1072static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1073{
9a34af4a 1074 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1075 int err;
1076
9a34af4a 1077 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1078 return 0;
1079 /* FIXME: currently only handling DIS controller
1080 * is there any machine with two switchable HDMI audio controllers?
1081 */
128960a9 1082 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1083 VGA_SWITCHEROO_DIS,
1084 chip->bus != NULL);
128960a9
TI		 1085 if (err < 0)
1086 return err;
9a34af4a 1087 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1088
1089 /* register as an optimus hdmi audio power domain */
8928756d 1090 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1091 &hda->hdmi_pm_domain);
128960a9 1092 return 0;
a82d51ed
TI		 1093}
1094#else
1095#define init_vga_switcheroo(chip) /* NOP */
1096#define register_vga_switcheroo(chip) 0
8393ec4a 1097#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1098#endif /* SUPPORT_VGA_SWITCHER */
1099
1da177e4
LT		 1100/*
1101 * destructor
1102 */
a98f90fd 1103static int azx_free(struct azx *chip)
1da177e4 1104{
c67e2228 1105 struct pci_dev *pci = chip->pci;
a07187c9 1106 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1107 int i;
1108
c67e2228
WX		 1109 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1110 && chip->running)
1111 pm_runtime_get_noresume(&pci->dev);
1112
65fcd41d
TI		 1113 azx_del_card_list(chip);
1114
0cbf0098
TI		 1115 azx_notifier_unregister(chip);
1116
9a34af4a
TI		 1117 hda->init_failed = 1; /* to be sure */
1118 complete_all(&hda->probe_wait);
f4c482a4 1119
9a34af4a 1120 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1121 if (chip->disabled && chip->bus)
1122 snd_hda_unlock_devices(chip->bus);
9a34af4a 1123 if (hda->vga_switcheroo_registered)
128960a9 1124 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1125 }
1126
ce43fbae 1127 if (chip->initialized) {
9ad593f6 1128 azx_clear_irq_pending(chip);
07e4ca50 1129 for (i = 0; i < chip->num_streams; i++)
1da177e4 1130 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1131 azx_stop_chip(chip);
1da177e4
LT		 1132 }
1133
f000fd80 1134 if (chip->irq >= 0)
1da177e4 1135 free_irq(chip->irq, (void*)chip);
68e7fffc 1136 if (chip->msi)
30b35399 1137 pci_disable_msi(chip->pci);
f079c25a
TI		 1138 if (chip->remap_addr)
1139 iounmap(chip->remap_addr);
1da177e4 1140
67908994 1141 azx_free_stream_pages(chip);
a82d51ed
TI		 1142 if (chip->region_requested)
1143 pci_release_regions(chip->pci);
1da177e4 1144 pci_disable_device(chip->pci);
07e4ca50 1145 kfree(chip->azx_dev);
4918cdab 1146#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1147 release_firmware(chip->fw);
4918cdab 1148#endif
99a2008d
WX		 1149 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1150 hda_display_power(false);
1151 hda_i915_exit();
1152 }
a07187c9 1153 kfree(hda);
1da177e4
LT		 1154
1155 return 0;
1156}
1157
a98f90fd 1158static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1159{
1160 return azx_free(device->device_data);
1161}
1162
8393ec4a 1163#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1164/*
1165 * Check of disabled HDMI controller by vga-switcheroo
1166 */
e23e7a14 1167static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1168{
1169 struct pci_dev *p;
1170
1171 /* check only discrete GPU */
1172 switch (pci->vendor) {
1173 case PCI_VENDOR_ID_ATI:
1174 case PCI_VENDOR_ID_AMD:
1175 case PCI_VENDOR_ID_NVIDIA:
1176 if (pci->devfn == 1) {
1177 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1178 pci->bus->number, 0);
1179 if (p) {
1180 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1181 return p;
1182 pci_dev_put(p);
1183 }
1184 }
1185 break;
1186 }
1187 return NULL;
1188}
1189
e23e7a14 1190static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1191{
1192 bool vga_inactive = false;
1193 struct pci_dev *p = get_bound_vga(pci);
1194
1195 if (p) {
12b78a7f 1196 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1197 vga_inactive = true;
1198 pci_dev_put(p);
1199 }
1200 return vga_inactive;
1201}
8393ec4a 1202#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1203
3372a153
TI		 1204/*
1205 * white/black-listing for position_fix
1206 */
e23e7a14 1207static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1208 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1209 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1210 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1211 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1212 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1213 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1214 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1215 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1216 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1217 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1218 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1219 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1220 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1221 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1222 {}
1223};
1224
e23e7a14 1225static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1226{
1227 const struct snd_pci_quirk *q;
1228
c673ba1c 1229 switch (fix) {
1dac6695 1230 case POS_FIX_AUTO:
c673ba1c
TI		 1231 case POS_FIX_LPIB:
1232 case POS_FIX_POSBUF:
4cb36310 1233 case POS_FIX_VIACOMBO:
a6f2fd55 1234 case POS_FIX_COMBO:
c673ba1c
TI		 1235 return fix;
1236 }
1237
c673ba1c
TI		 1238 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1239 if (q) {
4e76a883
TI		 1240 dev_info(chip->card->dev,
1241 "position_fix set to %d for device %04x:%04x\n",
1242 q->value, q->subvendor, q->subdevice);
c673ba1c 1243 return q->value;
3372a153 1244 }
bdd9ef24
DH		 1245
1246 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1247 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1248 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1249 return POS_FIX_VIACOMBO;
9477c58e
TI		 1250 }
1251 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1252 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1253 return POS_FIX_LPIB;
bdd9ef24 1254 }
c673ba1c 1255 return POS_FIX_AUTO;
3372a153
TI		 1256}
1257
b6050ef6
TI		 1258static void assign_position_fix(struct azx *chip, int fix)
1259{
1260 static azx_get_pos_callback_t callbacks[] = {
1261 [POS_FIX_AUTO] = NULL,
1262 [POS_FIX_LPIB] = azx_get_pos_lpib,
1263 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1264 [POS_FIX_VIACOMBO] = azx_via_get_position,
1265 [POS_FIX_COMBO] = azx_get_pos_lpib,
1266 };
1267
1268 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1269
1270 /* combo mode uses LPIB only for playback */
1271 if (fix == POS_FIX_COMBO)
1272 chip->get_position[1] = NULL;
1273
1274 if (fix == POS_FIX_POSBUF &&
1275 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1276 chip->get_delay[0] = chip->get_delay[1] =
1277 azx_get_delay_from_lpib;
1278 }
1279
1280}
1281
669ba27a
TI		 1282/*
1283 * black-lists for probe_mask
1284 */
e23e7a14 1285static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1286 /* Thinkpad often breaks the controller communication when accessing
1287 * to the non-working (or non-existing) modem codec slot.
1288 */
1289 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1290 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1291 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1292 /* broken BIOS */
1293 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1294 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1295 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1296 /* forced codec slots */
93574844 1297 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1298 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1299 /* WinFast VP200 H (Teradici) user reported broken communication */
1300 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1301 {}
1302};
1303
f1eaaeec
TI		 1304#define AZX_FORCE_CODEC_MASK 0x100
1305
e23e7a14 1306static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1307{
1308 const struct snd_pci_quirk *q;
1309
f1eaaeec
TI		 1310 chip->codec_probe_mask = probe_mask[dev];
1311 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1312 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1313 if (q) {
4e76a883
TI		 1314 dev_info(chip->card->dev,
1315 "probe_mask set to 0x%x for device %04x:%04x\n",
1316 q->value, q->subvendor, q->subdevice);
f1eaaeec 1317 chip->codec_probe_mask = q->value;
669ba27a
TI		 1318 }
1319 }
f1eaaeec
TI		 1320
1321 /* check forced option */
1322 if (chip->codec_probe_mask != -1 &&
1323 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1324 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1325 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1326 chip->codec_mask);
f1eaaeec 1327 }
669ba27a
TI		 1328}
1329
4d8e22e0 1330/*
71623855 1331 * white/black-list for enable_msi
4d8e22e0 1332 */
e23e7a14 1333static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1334 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1335 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1336 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1337 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1338 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1339 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1340 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1341 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1342 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1343 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1344 {}
1345};
1346
e23e7a14 1347static void check_msi(struct azx *chip)
4d8e22e0
TI		 1348{
1349 const struct snd_pci_quirk *q;
1350
71623855
TI		 1351 if (enable_msi >= 0) {
1352 chip->msi = !!enable_msi;
4d8e22e0 1353 return;
71623855
TI		 1354 }
1355 chip->msi = 1; /* enable MSI as default */
1356 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1357 if (q) {
4e76a883
TI		 1358 dev_info(chip->card->dev,
1359 "msi for device %04x:%04x set to %d\n",
1360 q->subvendor, q->subdevice, q->value);
4d8e22e0 1361 chip->msi = q->value;
80c43ed7
TI		 1362 return;
1363 }
1364
1365 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1366 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1367 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1368 chip->msi = 0;
4d8e22e0
TI		 1369 }
1370}
1371
a1585d76 1372/* check the snoop mode availability */
e23e7a14 1373static void azx_check_snoop_available(struct azx *chip)
a1585d76 1374{
7c732015 1375 int snoop = hda_snoop;
a1585d76 1376
7c732015
TI		 1377 if (snoop >= 0) {
1378 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1379 snoop ? "snoop" : "non-snoop");
1380 chip->snoop = snoop;
1381 return;
1382 }
1383
1384 snoop = true;
37e661ee
TI		 1385 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1386 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1387 /* force to non-snoop mode for a new VIA controller
1388 * when BIOS is set
1389 */
7c732015
TI		 1390 u8 val;
1391 pci_read_config_byte(chip->pci, 0x42, &val);
1392 if (!(val & 0x80) && chip->pci->revision == 0x30)
1393 snoop = false;
a1585d76
TI		 1394 }
1395
37e661ee
TI		 1396 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1397 snoop = false;
1398
7c732015
TI		 1399 chip->snoop = snoop;
1400 if (!snoop)
1401 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1402}
669ba27a 1403
99a2008d
WX		 1404static void azx_probe_work(struct work_struct *work)
1405{
9a34af4a
TI		 1406 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1407 azx_probe_continue(&hda->chip);
99a2008d 1408}
99a2008d 1409
1da177e4
LT		 1410/*
1411 * constructor
1412 */
e23e7a14
BP		 1413static int azx_create(struct snd_card *card, struct pci_dev *pci,
1414 int dev, unsigned int driver_caps,
40830813 1415 const struct hda_controller_ops *hda_ops,
e23e7a14 1416 struct azx **rchip)
1da177e4 1417{
a98f90fd 1418 static struct snd_device_ops ops = {
1da177e4
LT		 1419 .dev_free = azx_dev_free,
1420 };
a07187c9 1421 struct hda_intel *hda;
a82d51ed
TI		 1422 struct azx *chip;
1423 int err;
1da177e4
LT		 1424
1425 *rchip = NULL;
bcd72003 1426
927fc866
PM		 1427 err = pci_enable_device(pci);
1428 if (err < 0)
1da177e4
LT		 1429 return err;
1430
a07187c9
ML		 1431 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1432 if (!hda) {
1433 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1434 pci_disable_device(pci);
1435 return -ENOMEM;
1436 }
1437
a07187c9 1438 chip = &hda->chip;
1da177e4 1439 spin_lock_init(&chip->reg_lock);
62932df8 1440 mutex_init(&chip->open_mutex);
1da177e4
LT		 1441 chip->card = card;
1442 chip->pci = pci;
40830813 1443 chip->ops = hda_ops;
1da177e4 1444 chip->irq = -1;
9477c58e
TI		 1445 chip->driver_caps = driver_caps;
1446 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1447 check_msi(chip);
555e219f 1448 chip->dev_index = dev;
749ee287 1449 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1450 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1451 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1452 INIT_LIST_HEAD(&hda->list);
a82d51ed 1453 init_vga_switcheroo(chip);
9a34af4a 1454 init_completion(&hda->probe_wait);
1da177e4 1455
b6050ef6 1456 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1457
5aba4f8e 1458 check_probe_mask(chip, dev);
3372a153 1459
27346166 1460 chip->single_cmd = single_cmd;
a1585d76 1461 azx_check_snoop_available(chip);
c74db86b 1462
5c0d7bc1
TI		 1463 if (bdl_pos_adj[dev] < 0) {
1464 switch (chip->driver_type) {
0c6341ac 1465 case AZX_DRIVER_ICH:
32679f95 1466 case AZX_DRIVER_PCH:
0c6341ac 1467 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1468 break;
1469 default:
0c6341ac 1470 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1471 break;
1472 }
1473 }
9cdc0115 1474 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1475
a82d51ed
TI		 1476 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1477 if (err < 0) {
4e76a883 1478 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1479 azx_free(chip);
1480 return err;
1481 }
1482
99a2008d 1483 /* continue probing in work context as may trigger request module */
9a34af4a 1484 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1485
a82d51ed 1486 *rchip = chip;
99a2008d 1487
a82d51ed
TI		 1488 return 0;
1489}
1490
48c8b0eb 1491static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1492{
1493 int dev = chip->dev_index;
1494 struct pci_dev *pci = chip->pci;
1495 struct snd_card *card = chip->card;
67908994 1496 int err;
a82d51ed 1497 unsigned short gcap;
413cbf46 1498 unsigned int dma_bits = 64;
a82d51ed 1499
07e4ca50
TI		 1500#if BITS_PER_LONG != 64
1501 /* Fix up base address on ULI M5461 */
1502 if (chip->driver_type == AZX_DRIVER_ULI) {
1503 u16 tmp3;
1504 pci_read_config_word(pci, 0x40, &tmp3);
1505 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1506 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1507 }
1508#endif
1509
927fc866 1510 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1511 if (err < 0)
1da177e4 1512 return err;
a82d51ed 1513 chip->region_requested = 1;
1da177e4 1514
927fc866 1515 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1516 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1517 if (chip->remap_addr == NULL) {
4e76a883 1518 dev_err(card->dev, "ioremap error\n");
a82d51ed 1519 return -ENXIO;
1da177e4
LT		 1520 }
1521
db79afa1
BH		 1522 if (chip->msi) {
1523 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1524 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1525 pci->no_64bit_msi = true;
1526 }
68e7fffc
TI		 1527 if (pci_enable_msi(pci) < 0)
1528 chip->msi = 0;
db79afa1 1529 }
7376d013 1530
a82d51ed
TI		 1531 if (azx_acquire_irq(chip, 0) < 0)
1532 return -EBUSY;
1da177e4
LT		 1533
1534 pci_set_master(pci);
1535 synchronize_irq(chip->irq);
1536
bcd72003 1537 gcap = azx_readw(chip, GCAP);
4e76a883 1538 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1539
413cbf46
TI		 1540 /* AMD devices support 40 or 48bit DMA, take the safe one */
1541 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1542 dma_bits = 40;
1543
dc4c2e6b 1544 /* disable SB600 64bit support for safety */
9477c58e 1545 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1546 struct pci_dev *p_smbus;
413cbf46 1547 dma_bits = 40;
dc4c2e6b
AB		 1548 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1549 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1550 NULL);
1551 if (p_smbus) {
1552 if (p_smbus->revision < 0x30)
fb1d8ac2 1553 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1554 pci_dev_put(p_smbus);
1555 }
1556 }
09240cf4 1557
9477c58e
TI		 1558 /* disable 64bit DMA address on some devices */
1559 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1560 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1561 gcap &= ~AZX_GCAP_64OK;
9477c58e 1562 }
396087ea 1563
2ae66c26 1564 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1565 if (align_buffer_size >= 0)
1566 chip->align_buffer_size = !!align_buffer_size;
1567 else {
103884a3 1568 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1569 chip->align_buffer_size = 0;
7bfe059e
TI		 1570 else
1571 chip->align_buffer_size = 1;
1572 }
2ae66c26 1573
cf7aaca8 1574 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1575 if (!(gcap & AZX_GCAP_64OK))
1576 dma_bits = 32;
1577 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1578 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1579 } else {
e930438c
YH		 1580 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1581 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1582 }
cf7aaca8 1583
8b6ed8e7
TI		 1584 /* read number of streams from GCAP register instead of using
1585 * hardcoded value
1586 */
1587 chip->capture_streams = (gcap >> 8) & 0x0f;
1588 chip->playback_streams = (gcap >> 12) & 0x0f;
1589 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1590 /* gcap didn't give any info, switching to old method */
1591
1592 switch (chip->driver_type) {
1593 case AZX_DRIVER_ULI:
1594 chip->playback_streams = ULI_NUM_PLAYBACK;
1595 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1596 break;
1597 case AZX_DRIVER_ATIHDMI:
1815b34a 1598 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1599 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1600 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1601 break;
c4da29ca 1602 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1603 default:
1604 chip->playback_streams = ICH6_NUM_PLAYBACK;
1605 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1606 break;
1607 }
07e4ca50 1608 }
8b6ed8e7
TI		 1609 chip->capture_index_offset = 0;
1610 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1611 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1612 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1613 GFP_KERNEL);
927fc866 1614 if (!chip->azx_dev) {
4e76a883 1615 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1616 return -ENOMEM;
07e4ca50
TI		 1617 }
1618
67908994 1619 err = azx_alloc_stream_pages(chip);
81740861 1620 if (err < 0)
a82d51ed 1621 return err;
1da177e4
LT		 1622
1623 /* initialize streams */
1624 azx_init_stream(chip);
1625
1626 /* initialize chip */
cb53c626 1627 azx_init_pci(chip);
e4d9e513
ML		 1628
1629 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1630 haswell_set_bclk(chip);
1631
10e77dda 1632 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1633
1634 /* codec detection */
927fc866 1635 if (!chip->codec_mask) {
4e76a883 1636 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1637 return -ENODEV;
1da177e4
LT		 1638 }
1639
07e4ca50 1640 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1641 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1642 sizeof(card->shortname));
1643 snprintf(card->longname, sizeof(card->longname),
1644 "%s at 0x%lx irq %i",
1645 card->shortname, chip->addr, chip->irq);
07e4ca50 1646
1da177e4 1647 return 0;
1da177e4
LT		 1648}
1649
cb53c626
TI		 1650static void power_down_all_codecs(struct azx *chip)
1651{
83012a7c 1652#ifdef CONFIG_PM
cb53c626
TI		 1653 /* The codecs were powered up in snd_hda_codec_new().
1654 * Now all initialization done, so turn them down if possible
1655 */
1656 struct hda_codec *codec;
1657 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1658 snd_hda_power_down(codec);
1659 }
1660#endif
1661}
1662
97c6a3d1 1663#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1664/* callback from request_firmware_nowait() */
1665static void azx_firmware_cb(const struct firmware *fw, void *context)
1666{
1667 struct snd_card *card = context;
1668 struct azx *chip = card->private_data;
1669 struct pci_dev *pci = chip->pci;
1670
1671 if (!fw) {
4e76a883 1672 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1673 goto error;
1674 }
1675
1676 chip->fw = fw;
1677 if (!chip->disabled) {
1678 /* continue probing */
1679 if (azx_probe_continue(chip))
1680 goto error;
1681 }
1682 return; /* OK */
1683
1684 error:
1685 snd_card_free(card);
1686 pci_set_drvdata(pci, NULL);
1687}
97c6a3d1 1688#endif
5cb543db 1689
40830813
DR		 1690/*
1691 * HDA controller ops.
1692 */
1693
1694/* PCI register access. */
db291e36 1695static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1696{
1697 writel(value, addr);
1698}
1699
db291e36 1700static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1701{
1702 return readl(addr);
1703}
1704
db291e36 1705static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1706{
1707 writew(value, addr);
1708}
1709
db291e36 1710static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1711{
1712 return readw(addr);
1713}
1714
db291e36 1715static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1716{
1717 writeb(value, addr);
1718}
1719
db291e36 1720static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1721{
1722 return readb(addr);
1723}
1724
f46ea609
DR		 1725static int disable_msi_reset_irq(struct azx *chip)
1726{
1727 int err;
1728
1729 free_irq(chip->irq, chip);
1730 chip->irq = -1;
1731 pci_disable_msi(chip->pci);
1732 chip->msi = 0;
1733 err = azx_acquire_irq(chip, 1);
1734 if (err < 0)
1735 return err;
1736
1737 return 0;
1738}
1739
b419b35b
DR		 1740/* DMA page allocation helpers. */
1741static int dma_alloc_pages(struct azx *chip,
1742 int type,
1743 size_t size,
1744 struct snd_dma_buffer *buf)
1745{
1746 int err;
1747
1748 err = snd_dma_alloc_pages(type,
1749 chip->card->dev,
1750 size, buf);
1751 if (err < 0)
1752 return err;
1753 mark_pages_wc(chip, buf, true);
1754 return 0;
1755}
1756
1757static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1758{
1759 mark_pages_wc(chip, buf, false);
1760 snd_dma_free_pages(buf);
1761}
1762
1763static int substream_alloc_pages(struct azx *chip,
1764 struct snd_pcm_substream *substream,
1765 size_t size)
1766{
1767 struct azx_dev *azx_dev = get_azx_dev(substream);
1768 int ret;
1769
1770 mark_runtime_wc(chip, azx_dev, substream, false);
1771 azx_dev->bufsize = 0;
1772 azx_dev->period_bytes = 0;
1773 azx_dev->format_val = 0;
1774 ret = snd_pcm_lib_malloc_pages(substream, size);
1775 if (ret < 0)
1776 return ret;
1777 mark_runtime_wc(chip, azx_dev, substream, true);
1778 return 0;
1779}
1780
1781static int substream_free_pages(struct azx *chip,
1782 struct snd_pcm_substream *substream)
1783{
1784 struct azx_dev *azx_dev = get_azx_dev(substream);
1785 mark_runtime_wc(chip, azx_dev, substream, false);
1786 return snd_pcm_lib_free_pages(substream);
1787}
1788
8769b278
DR		 1789static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1790 struct vm_area_struct *area)
1791{
1792#ifdef CONFIG_X86
1793 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1794 struct azx *chip = apcm->chip;
3b70bdba 1795 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1796 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1797#endif
1798}
1799
40830813 1800static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1801 .reg_writel = pci_azx_writel,
1802 .reg_readl = pci_azx_readl,
1803 .reg_writew = pci_azx_writew,
1804 .reg_readw = pci_azx_readw,
1805 .reg_writeb = pci_azx_writeb,
1806 .reg_readb = pci_azx_readb,
f46ea609 1807 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1808 .dma_alloc_pages = dma_alloc_pages,
1809 .dma_free_pages = dma_free_pages,
1810 .substream_alloc_pages = substream_alloc_pages,
1811 .substream_free_pages = substream_free_pages,
8769b278 1812 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1813 .position_check = azx_position_check,
40830813
DR		 1814};
1815
e23e7a14
BP		 1816static int azx_probe(struct pci_dev *pci,
1817 const struct pci_device_id *pci_id)
1da177e4 1818{
5aba4f8e 1819 static int dev;
a98f90fd 1820 struct snd_card *card;
9a34af4a 1821 struct hda_intel *hda;
a98f90fd 1822 struct azx *chip;
aad730d0 1823 bool schedule_probe;
927fc866 1824 int err;
1da177e4 1825
5aba4f8e
TI		 1826 if (dev >= SNDRV_CARDS)
1827 return -ENODEV;
1828 if (!enable[dev]) {
1829 dev++;
1830 return -ENOENT;
1831 }
1832
60c5772b
TI		 1833 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1834 0, &card);
e58de7ba 1835 if (err < 0) {
4e76a883 1836 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1837 return err;
1da177e4
LT		 1838 }
1839
40830813
DR		 1840 err = azx_create(card, pci, dev, pci_id->driver_data,
1841 &pci_hda_ops, &chip);
41dda0fd
WF		 1842 if (err < 0)
1843 goto out_free;
421a1252 1844 card->private_data = chip;
9a34af4a 1845 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1846
1847 pci_set_drvdata(pci, card);
1848
1849 err = register_vga_switcheroo(chip);
1850 if (err < 0) {
4e76a883 1851 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1852 goto out_free;
1853 }
1854
1855 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1856 dev_info(card->dev, "VGA controller is disabled\n");
1857 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1858 chip->disabled = true;
1859 }
1860
aad730d0 1861 schedule_probe = !chip->disabled;
1da177e4 1862
4918cdab
TI		 1863#ifdef CONFIG_SND_HDA_PATCH_LOADER
1864 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1865 dev_info(card->dev, "Applying patch firmware '%s'\n",
1866 patch[dev]);
5cb543db
TI		 1867 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1868 &pci->dev, GFP_KERNEL, card,
1869 azx_firmware_cb);
4918cdab
TI		 1870 if (err < 0)
1871 goto out_free;
aad730d0 1872 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1873 }
1874#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1875
aad730d0
TI		 1876#ifndef CONFIG_SND_HDA_I915
1877 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1878 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1879#endif
99a2008d 1880
aad730d0 1881 if (schedule_probe)
9a34af4a 1882 schedule_work(&hda->probe_work);
a82d51ed 1883
a82d51ed 1884 dev++;
88d071fc 1885 if (chip->disabled)
9a34af4a 1886 complete_all(&hda->probe_wait);
a82d51ed
TI		 1887 return 0;
1888
1889out_free:
1890 snd_card_free(card);
1891 return err;
1892}
1893
e62a42ae
DR		 1894/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1895static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1896 [AZX_DRIVER_NVIDIA] = 8,
1897 [AZX_DRIVER_TERA] = 1,
1898};
1899
48c8b0eb 1900static int azx_probe_continue(struct azx *chip)
a82d51ed 1901{
9a34af4a 1902 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1903 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1904 int dev = chip->dev_index;
1905 int err;
1906
99a2008d
WX		 1907 /* Request power well for Haswell HDA controller and codec */
1908 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1909#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1910 err = hda_i915_init();
1911 if (err < 0) {
4e76a883
TI		 1912 dev_err(chip->card->dev,
1913 "Error request power-well from i915\n");
99a2008d
WX		 1914 goto out_free;
1915 }
74b0c2d7
TI		 1916 err = hda_display_power(true);
1917 if (err < 0) {
1918 dev_err(chip->card->dev,
1919 "Cannot turn on display power on i915\n");
1920 goto out_free;
1921 }
c841ad2a 1922#endif
99a2008d
WX		 1923 }
1924
5c90680e
TI		 1925 err = azx_first_init(chip);
1926 if (err < 0)
1927 goto out_free;
1928
2dca0bba
JK		 1929#ifdef CONFIG_SND_HDA_INPUT_BEEP
1930 chip->beep_mode = beep_mode[dev];
1931#endif
1932
1da177e4 1933 /* create codec instances */
e62a42ae
DR		 1934 err = azx_codec_create(chip, model[dev],
1935 azx_max_codecs[chip->driver_type],
1936 power_save_addr);
1937
41dda0fd
WF		 1938 if (err < 0)
1939 goto out_free;
4ea6fbc8 1940#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1941 if (chip->fw) {
1942 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1943 chip->fw->data);
4ea6fbc8
TI		 1944 if (err < 0)
1945 goto out_free;
e39ae856 1946#ifndef CONFIG_PM
4918cdab
TI		 1947 release_firmware(chip->fw); /* no longer needed */
1948 chip->fw = NULL;
e39ae856 1949#endif
4ea6fbc8
TI		 1950 }
1951#endif
10e77dda 1952 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1953 err = azx_codec_configure(chip);
1954 if (err < 0)
1955 goto out_free;
1956 }
1da177e4
LT		 1957
1958 /* create PCM streams */
176d5335 1959 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1960 if (err < 0)
1961 goto out_free;
1da177e4
LT		 1962
1963 /* create mixer controls */
d01ce99f 1964 err = azx_mixer_create(chip);
41dda0fd
WF		 1965 if (err < 0)
1966 goto out_free;
1da177e4 1967
a82d51ed 1968 err = snd_card_register(chip->card);
41dda0fd
WF		 1969 if (err < 0)
1970 goto out_free;
1da177e4 1971
cb53c626
TI		 1972 chip->running = 1;
1973 power_down_all_codecs(chip);
0cbf0098 1974 azx_notifier_register(chip);
65fcd41d 1975 azx_add_card_list(chip);
9a34af4a 1976 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
c67e2228 1977 pm_runtime_put_noidle(&pci->dev);
1da177e4 1978
41dda0fd 1979out_free:
88d071fc 1980 if (err < 0)
9a34af4a
TI		 1981 hda->init_failed = 1;
1982 complete_all(&hda->probe_wait);
41dda0fd 1983 return err;
1da177e4
LT		 1984}
1985
e23e7a14 1986static void azx_remove(struct pci_dev *pci)
1da177e4 1987{
9121947d 1988 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1989
9121947d
TI		 1990 if (card)
1991 snd_card_free(card);
1da177e4
LT		 1992}
1993
1994/* PCI IDs */
6f51f6cf 1995static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1996 /* CPT */
9477c58e 1997 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1999 /* PBG */
9477c58e 2000 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2002 /* Panther Point */
9477c58e 2003 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 2004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 2005 /* Lynx Point */
2006 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2007 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2008 /* 9 Series */
2009 { PCI_DEVICE(0x8086, 0x8ca0),
2010 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2011 /* Wellsburg */
2012 { PCI_DEVICE(0x8086, 0x8d20),
2013 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2014 { PCI_DEVICE(0x8086, 0x8d21),
2015 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2016 /* Lynx Point-LP */
2017 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2018 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2019 /* Lynx Point-LP */
2020 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2021 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2022 /* Wildcat Point-LP */
2023 { PCI_DEVICE(0x8086, 0x9ca0),
2024 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2025 /* Sunrise Point */
2026 { PCI_DEVICE(0x8086, 0xa170),
2027 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b4565913
DR		 2028 /* Sunrise Point-LP */
2029 { PCI_DEVICE(0x8086, 0x9d70),
2030 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 2031 /* Haswell */
4a7c516b 2032 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2033 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2034 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2035 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2036 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2037 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2038 /* Broadwell */
2039 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2040 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2041 /* 5 Series/3400 */
2042 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2043 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2044 /* Poulsbo */
9477c58e 2045 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2046 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2047 /* Oaktrail */
09904b95 2048 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2049 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2050 /* BayTrail */
2051 { PCI_DEVICE(0x8086, 0x0f04),
2052 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
f31b2ffc
LY		 2053 /* Braswell */
2054 { PCI_DEVICE(0x8086, 0x2284),
2055 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b42b4afb 2056 /* ICH6 */
8b0bd226 2057 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2058 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2059 /* ICH7 */
8b0bd226 2060 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2061 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2062 /* ESB2 */
8b0bd226 2063 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2064 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2065 /* ICH8 */
8b0bd226 2066 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2067 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2068 /* ICH9 */
8b0bd226 2069 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2070 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2071 /* ICH9 */
8b0bd226 2072 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2073 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2074 /* ICH10 */
8b0bd226 2075 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2076 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2077 /* ICH10 */
8b0bd226 2078 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2079 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2080 /* Generic Intel */
2081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2082 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2083 .class_mask = 0xffffff,
103884a3 2084 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2085 /* ATI SB 450/600/700/800/900 */
2086 { PCI_DEVICE(0x1002, 0x437b),
2087 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2088 { PCI_DEVICE(0x1002, 0x4383),
2089 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2090 /* AMD Hudson */
2091 { PCI_DEVICE(0x1022, 0x780d),
2092 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2093 /* ATI HDMI */
9477c58e
TI		 2094 { PCI_DEVICE(0x1002, 0x793b),
2095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2096 { PCI_DEVICE(0x1002, 0x7919),
2097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2098 { PCI_DEVICE(0x1002, 0x960f),
2099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2100 { PCI_DEVICE(0x1002, 0x970f),
2101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102 { PCI_DEVICE(0x1002, 0xaa00),
2103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104 { PCI_DEVICE(0x1002, 0xaa08),
2105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106 { PCI_DEVICE(0x1002, 0xaa10),
2107 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2108 { PCI_DEVICE(0x1002, 0xaa18),
2109 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2110 { PCI_DEVICE(0x1002, 0xaa20),
2111 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2112 { PCI_DEVICE(0x1002, 0xaa28),
2113 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2114 { PCI_DEVICE(0x1002, 0xaa30),
2115 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2116 { PCI_DEVICE(0x1002, 0xaa38),
2117 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2118 { PCI_DEVICE(0x1002, 0xaa40),
2119 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2120 { PCI_DEVICE(0x1002, 0xaa48),
2121 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2122 { PCI_DEVICE(0x1002, 0xaa50),
2123 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2124 { PCI_DEVICE(0x1002, 0xaa58),
2125 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2126 { PCI_DEVICE(0x1002, 0xaa60),
2127 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2128 { PCI_DEVICE(0x1002, 0xaa68),
2129 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2130 { PCI_DEVICE(0x1002, 0xaa80),
2131 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2132 { PCI_DEVICE(0x1002, 0xaa88),
2133 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2134 { PCI_DEVICE(0x1002, 0xaa90),
2135 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2136 { PCI_DEVICE(0x1002, 0xaa98),
2137 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2138 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2139 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2140 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2141 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2142 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2143 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2144 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2145 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2146 /* VIA VT8251/VT8237A */
9477c58e
TI		 2147 { PCI_DEVICE(0x1106, 0x3288),
2148 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2149 /* VIA GFX VT7122/VX900 */
2150 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2151 /* VIA GFX VT6122/VX11 */
2152 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2153 /* SIS966 */
2154 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2155 /* ULI M5461 */
2156 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2157 /* NVIDIA MCP */
0c2fd1bf
TI		 2158 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2159 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2160 .class_mask = 0xffffff,
9477c58e 2161 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2162 /* Teradici */
9477c58e
TI		 2163 { PCI_DEVICE(0x6549, 0x1200),
2164 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2165 { PCI_DEVICE(0x6549, 0x2200),
2166 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2167 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2168 /* CTHDA chips */
2169 { PCI_DEVICE(0x1102, 0x0010),
2170 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2171 { PCI_DEVICE(0x1102, 0x0012),
2172 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2173#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2174 /* the following entry conflicts with snd-ctxfi driver,
2175 * as ctxfi driver mutates from HD-audio to native mode with
2176 * a special command sequence.
2177 */
4e01f54b
TI		 2178 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2179 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2180 .class_mask = 0xffffff,
9477c58e 2181 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2182 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2183#else
2184 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2185 { PCI_DEVICE(0x1102, 0x0009),
2186 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2187 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2188#endif
c563f473
TI		 2189 /* CM8888 */
2190 { PCI_DEVICE(0x13f6, 0x5011),
2191 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2192 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2193 /* Vortex86MX */
2194 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2195 /* VMware HDAudio */
2196 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2197 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2198 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2199 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2200 .class_mask = 0xffffff,
9477c58e 2201 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2202 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2203 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2204 .class_mask = 0xffffff,
9477c58e 2205 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2206 { 0, }
2207};
2208MODULE_DEVICE_TABLE(pci, azx_ids);
2209
2210/* pci_driver definition */
e9f66d9b 2211static struct pci_driver azx_driver = {
3733e424 2212 .name = KBUILD_MODNAME,
1da177e4
LT		 2213 .id_table = azx_ids,
2214 .probe = azx_probe,
e23e7a14 2215 .remove = azx_remove,
68cb2b55
TI		 2216 .driver = {
2217 .pm = AZX_PM_OPS,
2218 },
1da177e4
LT		 2219};
2220
e9f66d9b 2221module_pci_driver(azx_driver);
Linux kernel - Deliverables
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