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[ALSA] hda-intel - Add ATI RS780,R600 HDMI audio support
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36#include <sound/driver.h>
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4
LT		 41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
1da177e4
LT		 47#include <sound/core.h>
48#include <sound/initval.h>
49#include "hda_codec.h"
50
51
b7fe4622
CL		 52static int index = SNDRV_DEFAULT_IDX1;
53static char *id = SNDRV_DEFAULT_STR1;
54static char *model;
55static int position_fix;
954fa19a 56static int probe_mask = -1;
27346166 57static int single_cmd;
134a11f0 58static int enable_msi;
1da177e4 59
b7fe4622 60module_param(index, int, 0444);
1da177e4 61MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
b7fe4622 62module_param(id, charp, 0444);
1da177e4 63MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
b7fe4622 64module_param(model, charp, 0444);
1da177e4 65MODULE_PARM_DESC(model, "Use the given board model.");
b7fe4622 66module_param(position_fix, int, 0444);
0be3b5d3 67MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
606ad75f
TI		 68module_param(probe_mask, int, 0444);
69MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
27346166
TI		 70module_param(single_cmd, bool, 0444);
71MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
134a11f0
TI		 72module_param(enable_msi, int, 0);
73MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 74
1da177e4 75
2b3e584b
TI		 76/* just for backward compatibility */
77static int enable;
698444f3 78module_param(enable, bool, 0444);
2b3e584b 79
1da177e4
LT		 80MODULE_LICENSE("GPL");
81MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
82 "{Intel, ICH6M},"
2f1b3818 83 "{Intel, ICH7},"
f5d40b30 84 "{Intel, ESB2},"
d2981393 85 "{Intel, ICH8},"
f9cc8a8b 86 "{Intel, ICH9},"
fc20a562 87 "{ATI, SB450},"
89be83f8 88 "{ATI, SB600},"
778b6e1b 89 "{ATI, RS600},"
5b15c95f 90 "{ATI, RS690},"
e6db1119
WL		 91 "{ATI, RS780},"
92 "{ATI, R600},"
fc20a562 93 "{VIA, VT8251},"
47672310 94 "{VIA, VT8237A},"
07e4ca50
TI		 95 "{SiS, SIS966},"
96 "{ULI, M5461}}");
1da177e4
LT		 97MODULE_DESCRIPTION("Intel HDA driver");
98
99#define SFX "hda-intel: "
100
101/*
102 * registers
103 */
104#define ICH6_REG_GCAP 0x00
105#define ICH6_REG_VMIN 0x02
106#define ICH6_REG_VMAJ 0x03
107#define ICH6_REG_OUTPAY 0x04
108#define ICH6_REG_INPAY 0x06
109#define ICH6_REG_GCTL 0x08
110#define ICH6_REG_WAKEEN 0x0c
111#define ICH6_REG_STATESTS 0x0e
112#define ICH6_REG_GSTS 0x10
113#define ICH6_REG_INTCTL 0x20
114#define ICH6_REG_INTSTS 0x24
115#define ICH6_REG_WALCLK 0x30
116#define ICH6_REG_SYNC 0x34
117#define ICH6_REG_CORBLBASE 0x40
118#define ICH6_REG_CORBUBASE 0x44
119#define ICH6_REG_CORBWP 0x48
120#define ICH6_REG_CORBRP 0x4A
121#define ICH6_REG_CORBCTL 0x4c
122#define ICH6_REG_CORBSTS 0x4d
123#define ICH6_REG_CORBSIZE 0x4e
124
125#define ICH6_REG_RIRBLBASE 0x50
126#define ICH6_REG_RIRBUBASE 0x54
127#define ICH6_REG_RIRBWP 0x58
128#define ICH6_REG_RINTCNT 0x5a
129#define ICH6_REG_RIRBCTL 0x5c
130#define ICH6_REG_RIRBSTS 0x5d
131#define ICH6_REG_RIRBSIZE 0x5e
132
133#define ICH6_REG_IC 0x60
134#define ICH6_REG_IR 0x64
135#define ICH6_REG_IRS 0x68
136#define ICH6_IRS_VALID (1<<1)
137#define ICH6_IRS_BUSY (1<<0)
138
139#define ICH6_REG_DPLBASE 0x70
140#define ICH6_REG_DPUBASE 0x74
141#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
142
143/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
144enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
145
146/* stream register offsets from stream base */
147#define ICH6_REG_SD_CTL 0x00
148#define ICH6_REG_SD_STS 0x03
149#define ICH6_REG_SD_LPIB 0x04
150#define ICH6_REG_SD_CBL 0x08
151#define ICH6_REG_SD_LVI 0x0c
152#define ICH6_REG_SD_FIFOW 0x0e
153#define ICH6_REG_SD_FIFOSIZE 0x10
154#define ICH6_REG_SD_FORMAT 0x12
155#define ICH6_REG_SD_BDLPL 0x18
156#define ICH6_REG_SD_BDLPU 0x1c
157
158/* PCI space */
159#define ICH6_PCIREG_TCSEL 0x44
160
161/*
162 * other constants
163 */
164
165/* max number of SDs */
07e4ca50
TI		 166/* ICH, ATI and VIA have 4 playback and 4 capture */
167#define ICH6_CAPTURE_INDEX 0
168#define ICH6_NUM_CAPTURE 4
169#define ICH6_PLAYBACK_INDEX 4
170#define ICH6_NUM_PLAYBACK 4
171
172/* ULI has 6 playback and 5 capture */
173#define ULI_CAPTURE_INDEX 0
174#define ULI_NUM_CAPTURE 5
175#define ULI_PLAYBACK_INDEX 5
176#define ULI_NUM_PLAYBACK 6
177
778b6e1b
FK		 178/* ATI HDMI has 1 playback and 0 capture */
179#define ATIHDMI_CAPTURE_INDEX 0
180#define ATIHDMI_NUM_CAPTURE 0
181#define ATIHDMI_PLAYBACK_INDEX 0
182#define ATIHDMI_NUM_PLAYBACK 1
183
07e4ca50
TI		 184/* this number is statically defined for simplicity */
185#define MAX_AZX_DEV 16
186
1da177e4 187/* max number of fragments - we may use more if allocating more pages for BDL */
07e4ca50
TI		 188#define BDL_SIZE PAGE_ALIGN(8192)
189#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
1da177e4
LT		 190/* max buffer size - no h/w limit, you can increase as you like */
191#define AZX_MAX_BUF_SIZE (1024*1024*1024)
192/* max number of PCM devics per card */
ec9e1c5c
TI		 193#define AZX_MAX_AUDIO_PCMS 6
194#define AZX_MAX_MODEM_PCMS 2
195#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
1da177e4
LT		 196
197/* RIRB int mask: overrun[2], response[0] */
198#define RIRB_INT_RESPONSE 0x01
199#define RIRB_INT_OVERRUN 0x04
200#define RIRB_INT_MASK 0x05
201
202/* STATESTS int mask: SD2,SD1,SD0 */
19a982b6 203#define AZX_MAX_CODECS 3
1da177e4 204#define STATESTS_INT_MASK 0x07
1da177e4
LT		 205
206/* SD_CTL bits */
207#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
208#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
209#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
210#define SD_CTL_STREAM_TAG_SHIFT 20
211
212/* SD_CTL and SD_STS */
213#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
214#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
215#define SD_INT_COMPLETE 0x04 /* completion interrupt */
216#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
217
218/* SD_STS */
219#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
220
221/* INTCTL and INTSTS */
222#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
223#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
224#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
225
41e2fce4
M		 226/* GCTL unsolicited response enable bit */
227#define ICH6_GCTL_UREN (1<<8)
228
1da177e4
LT		 229/* GCTL reset bit */
230#define ICH6_GCTL_RESET (1<<0)
231
232/* CORB/RIRB control, read/write pointer */
233#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
234#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
235#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
236/* below are so far hardcoded - should read registers in future */
237#define ICH6_MAX_CORB_ENTRIES 256
238#define ICH6_MAX_RIRB_ENTRIES 256
239
c74db86b
TI		 240/* position fix mode */
241enum {
0be3b5d3 242 POS_FIX_AUTO,
c74db86b 243 POS_FIX_NONE,
0be3b5d3
TI		 244 POS_FIX_POSBUF,
245 POS_FIX_FIFO,
c74db86b 246};
1da177e4 247
f5d40b30 248/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 249#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
250#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
251
da3fca21
V		 252/* Defines for Nvidia HDA support */
253#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
254#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 255
1da177e4
LT		 256/*
257 */
258
a98f90fd 259struct azx_dev {
1da177e4
LT		 260 u32 *bdl; /* virtual address of the BDL */
261 dma_addr_t bdl_addr; /* physical address of the BDL */
929861c6 262 u32 *posbuf; /* position buffer pointer */
1da177e4
LT		 263
264 unsigned int bufsize; /* size of the play buffer in bytes */
265 unsigned int fragsize; /* size of each period in bytes */
266 unsigned int frags; /* number for period in the play buffer */
267 unsigned int fifo_size; /* FIFO size */
268
269 void __iomem *sd_addr; /* stream descriptor pointer */
270
271 u32 sd_int_sta_mask; /* stream int status mask */
272
273 /* pcm support */
a98f90fd 274 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
1da177e4
LT		 275 unsigned int format_val; /* format value to be set in the controller and the codec */
276 unsigned char stream_tag; /* assigned stream */
277 unsigned char index; /* stream index */
1a56f8d6
TI		 278 /* for sanity check of position buffer */
279 unsigned int period_intr;
1da177e4 280
927fc866
PM		 281 unsigned int opened :1;
282 unsigned int running :1;
1da177e4
LT		 283};
284
285/* CORB/RIRB */
a98f90fd 286struct azx_rb {
1da177e4
LT		 287 u32 *buf; /* CORB/RIRB buffer
288 * Each CORB entry is 4byte, RIRB is 8byte
289 */
290 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
291 /* for RIRB */
292 unsigned short rp, wp; /* read/write pointers */
293 int cmds; /* number of pending requests */
294 u32 res; /* last read value */
295};
296
a98f90fd
TI		 297struct azx {
298 struct snd_card *card;
1da177e4
LT		 299 struct pci_dev *pci;
300
07e4ca50
TI		 301 /* chip type specific */
302 int driver_type;
303 int playback_streams;
304 int playback_index_offset;
305 int capture_streams;
306 int capture_index_offset;
307 int num_streams;
308
1da177e4
LT		 309 /* pci resources */
310 unsigned long addr;
311 void __iomem *remap_addr;
312 int irq;
313
314 /* locks */
315 spinlock_t reg_lock;
62932df8 316 struct mutex open_mutex;
1da177e4 317
07e4ca50 318 /* streams (x num_streams) */
a98f90fd 319 struct azx_dev *azx_dev;
1da177e4
LT		 320
321 /* PCM */
322 unsigned int pcm_devs;
a98f90fd 323 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 324
325 /* HD codec */
326 unsigned short codec_mask;
327 struct hda_bus *bus;
328
329 /* CORB/RIRB */
a98f90fd
TI		 330 struct azx_rb corb;
331 struct azx_rb rirb;
1da177e4
LT		 332
333 /* BDL, CORB/RIRB and position buffers */
334 struct snd_dma_buffer bdl;
335 struct snd_dma_buffer rb;
336 struct snd_dma_buffer posbuf;
c74db86b
TI		 337
338 /* flags */
339 int position_fix;
927fc866
PM		 340 unsigned int initialized :1;
341 unsigned int single_cmd :1;
342 unsigned int polling_mode :1;
68e7fffc 343 unsigned int msi :1;
1da177e4
LT		 344};
345
07e4ca50
TI		 346/* driver types */
347enum {
348 AZX_DRIVER_ICH,
349 AZX_DRIVER_ATI,
778b6e1b 350 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 351 AZX_DRIVER_VIA,
352 AZX_DRIVER_SIS,
353 AZX_DRIVER_ULI,
da3fca21 354 AZX_DRIVER_NVIDIA,
07e4ca50
TI		 355};
356
357static char *driver_short_names[] __devinitdata = {
358 [AZX_DRIVER_ICH] = "HDA Intel",
359 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 360 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
362 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 363 [AZX_DRIVER_ULI] = "HDA ULI M5461",
364 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
07e4ca50
TI		 365};
366
1da177e4
LT		 367/*
368 * macros for easy use
369 */
370#define azx_writel(chip,reg,value) \
371 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
372#define azx_readl(chip,reg) \
373 readl((chip)->remap_addr + ICH6_REG_##reg)
374#define azx_writew(chip,reg,value) \
375 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
376#define azx_readw(chip,reg) \
377 readw((chip)->remap_addr + ICH6_REG_##reg)
378#define azx_writeb(chip,reg,value) \
379 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
380#define azx_readb(chip,reg) \
381 readb((chip)->remap_addr + ICH6_REG_##reg)
382
383#define azx_sd_writel(dev,reg,value) \
384 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
385#define azx_sd_readl(dev,reg) \
386 readl((dev)->sd_addr + ICH6_REG_##reg)
387#define azx_sd_writew(dev,reg,value) \
388 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
389#define azx_sd_readw(dev,reg) \
390 readw((dev)->sd_addr + ICH6_REG_##reg)
391#define azx_sd_writeb(dev,reg,value) \
392 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
393#define azx_sd_readb(dev,reg) \
394 readb((dev)->sd_addr + ICH6_REG_##reg)
395
396/* for pcm support */
a98f90fd 397#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4
LT		 398
399/* Get the upper 32bit of the given dma_addr_t
400 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
401 */
402#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
403
68e7fffc 404static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 405
406/*
407 * Interface for HD codec
408 */
409
1da177e4
LT		 410/*
411 * CORB / RIRB interface
412 */
a98f90fd 413static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 414{
415 int err;
416
417 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
418 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
419 PAGE_SIZE, &chip->rb);
420 if (err < 0) {
421 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
422 return err;
423 }
424 return 0;
425}
426
a98f90fd 427static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 428{
429 /* CORB set up */
430 chip->corb.addr = chip->rb.addr;
431 chip->corb.buf = (u32 *)chip->rb.area;
432 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
433 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
434
07e4ca50
TI		 435 /* set the corb size to 256 entries (ULI requires explicitly) */
436 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 437 /* set the corb write pointer to 0 */
438 azx_writew(chip, CORBWP, 0);
439 /* reset the corb hw read pointer */
440 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
441 /* enable corb dma */
442 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
443
444 /* RIRB set up */
445 chip->rirb.addr = chip->rb.addr + 2048;
446 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
447 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
448 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
449
07e4ca50
TI		 450 /* set the rirb size to 256 entries (ULI requires explicitly) */
451 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 452 /* reset the rirb hw write pointer */
453 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
454 /* set N=1, get RIRB response interrupt for new entry */
455 azx_writew(chip, RINTCNT, 1);
456 /* enable rirb dma and response irq */
1da177e4 457 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 458 chip->rirb.rp = chip->rirb.cmds = 0;
459}
460
a98f90fd 461static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 462{
463 /* disable ringbuffer DMAs */
464 azx_writeb(chip, RIRBCTL, 0);
465 azx_writeb(chip, CORBCTL, 0);
466}
467
468/* send a command */
111d3af5
TI		 469static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
470 unsigned int verb, unsigned int para)
1da177e4 471{
a98f90fd 472 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 473 unsigned int wp;
474 u32 val;
475
476 val = (u32)(codec->addr & 0x0f) << 28;
477 val |= (u32)direct << 27;
478 val |= (u32)nid << 20;
479 val |= verb << 8;
480 val |= para;
481
482 /* add command to corb */
483 wp = azx_readb(chip, CORBWP);
484 wp++;
485 wp %= ICH6_MAX_CORB_ENTRIES;
486
487 spin_lock_irq(&chip->reg_lock);
488 chip->rirb.cmds++;
489 chip->corb.buf[wp] = cpu_to_le32(val);
490 azx_writel(chip, CORBWP, wp);
491 spin_unlock_irq(&chip->reg_lock);
492
493 return 0;
494}
495
496#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
497
498/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 499static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 500{
501 unsigned int rp, wp;
502 u32 res, res_ex;
503
504 wp = azx_readb(chip, RIRBWP);
505 if (wp == chip->rirb.wp)
506 return;
507 chip->rirb.wp = wp;
508
509 while (chip->rirb.rp != wp) {
510 chip->rirb.rp++;
511 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
512
513 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
514 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
515 res = le32_to_cpu(chip->rirb.buf[rp]);
516 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
517 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
518 else if (chip->rirb.cmds) {
519 chip->rirb.cmds--;
520 chip->rirb.res = res;
521 }
522 }
523}
524
525/* receive a response */
111d3af5 526static unsigned int azx_rirb_get_response(struct hda_codec *codec)
1da177e4 527{
a98f90fd 528 struct azx *chip = codec->bus->private_data;
5c79b1f8 529 unsigned long timeout;
1da177e4 530
5c79b1f8
TI		 531 again:
532 timeout = jiffies + msecs_to_jiffies(1000);
533 do {
e96224ae
TI		 534 if (chip->polling_mode) {
535 spin_lock_irq(&chip->reg_lock);
536 azx_update_rirb(chip);
537 spin_unlock_irq(&chip->reg_lock);
538 }
539 if (! chip->rirb.cmds)
5c79b1f8
TI		 540 return chip->rirb.res; /* the last value */
541 schedule_timeout_interruptible(1);
542 } while (time_after_eq(timeout, jiffies));
543
68e7fffc
TI		 544 if (chip->msi) {
545 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
546 "disabling MSI...\n");
547 free_irq(chip->irq, chip);
548 chip->irq = -1;
549 pci_disable_msi(chip->pci);
550 chip->msi = 0;
551 if (azx_acquire_irq(chip, 1) < 0)
552 return -1;
553 goto again;
554 }
555
5c79b1f8
TI		 556 if (!chip->polling_mode) {
557 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
558 "switching to polling mode...\n");
559 chip->polling_mode = 1;
560 goto again;
1da177e4 561 }
5c79b1f8
TI		 562
563 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
564 "switching to single_cmd mode...\n");
565 chip->rirb.rp = azx_readb(chip, RIRBWP);
566 chip->rirb.cmds = 0;
567 /* switch to single_cmd mode */
568 chip->single_cmd = 1;
569 azx_free_cmd_io(chip);
570 return -1;
1da177e4
LT		 571}
572
1da177e4
LT		 573/*
574 * Use the single immediate command instead of CORB/RIRB for simplicity
575 *
576 * Note: according to Intel, this is not preferred use. The command was
577 * intended for the BIOS only, and may get confused with unsolicited
578 * responses. So, we shouldn't use it for normal operation from the
579 * driver.
580 * I left the codes, however, for debugging/testing purposes.
581 */
582
1da177e4 583/* send a command */
27346166
TI		 584static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid,
585 int direct, unsigned int verb,
586 unsigned int para)
1da177e4 587{
a98f90fd 588 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 589 u32 val;
590 int timeout = 50;
591
592 val = (u32)(codec->addr & 0x0f) << 28;
593 val |= (u32)direct << 27;
594 val |= (u32)nid << 20;
595 val |= verb << 8;
596 val |= para;
597
598 while (timeout--) {
599 /* check ICB busy bit */
600 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
601 /* Clear IRV valid bit */
602 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
603 azx_writel(chip, IC, val);
604 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
605 return 0;
606 }
607 udelay(1);
608 }
609 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
610 return -EIO;
611}
612
613/* receive a response */
27346166 614static unsigned int azx_single_get_response(struct hda_codec *codec)
1da177e4 615{
a98f90fd 616 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 617 int timeout = 50;
618
619 while (timeout--) {
620 /* check IRV busy bit */
621 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
622 return azx_readl(chip, IR);
623 udelay(1);
624 }
625 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
626 return (unsigned int)-1;
627}
628
111d3af5
TI		 629/*
630 * The below are the main callbacks from hda_codec.
631 *
632 * They are just the skeleton to call sub-callbacks according to the
633 * current setting of chip->single_cmd.
634 */
635
636/* send a command */
637static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
638 int direct, unsigned int verb,
639 unsigned int para)
640{
641 struct azx *chip = codec->bus->private_data;
642 if (chip->single_cmd)
643 return azx_single_send_cmd(codec, nid, direct, verb, para);
644 else
645 return azx_corb_send_cmd(codec, nid, direct, verb, para);
646}
647
648/* get a response */
649static unsigned int azx_get_response(struct hda_codec *codec)
650{
651 struct azx *chip = codec->bus->private_data;
652 if (chip->single_cmd)
653 return azx_single_get_response(codec);
654 else
655 return azx_rirb_get_response(codec);
656}
657
658
1da177e4 659/* reset codec link */
a98f90fd 660static int azx_reset(struct azx *chip)
1da177e4
LT		 661{
662 int count;
663
664 /* reset controller */
665 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
666
667 count = 50;
668 while (azx_readb(chip, GCTL) && --count)
669 msleep(1);
670
671 /* delay for >= 100us for codec PLL to settle per spec
672 * Rev 0.9 section 5.5.1
673 */
674 msleep(1);
675
676 /* Bring controller out of reset */
677 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
678
679 count = 50;
927fc866 680 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 681 msleep(1);
682
927fc866 683 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 684 msleep(1);
685
686 /* check to see if controller is ready */
927fc866 687 if (!azx_readb(chip, GCTL)) {
1da177e4
LT		 688 snd_printd("azx_reset: controller not ready!\n");
689 return -EBUSY;
690 }
691
41e2fce4
M		 692 /* Accept unsolicited responses */
693 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
694
1da177e4 695 /* detect codecs */
927fc866 696 if (!chip->codec_mask) {
1da177e4
LT		 697 chip->codec_mask = azx_readw(chip, STATESTS);
698 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
699 }
700
701 return 0;
702}
703
704
705/*
706 * Lowlevel interface
707 */
708
709/* enable interrupts */
a98f90fd 710static void azx_int_enable(struct azx *chip)
1da177e4
LT		 711{
712 /* enable controller CIE and GIE */
713 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
714 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
715}
716
717/* disable interrupts */
a98f90fd 718static void azx_int_disable(struct azx *chip)
1da177e4
LT		 719{
720 int i;
721
722 /* disable interrupts in stream descriptor */
07e4ca50 723 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 724 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 725 azx_sd_writeb(azx_dev, SD_CTL,
726 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
727 }
728
729 /* disable SIE for all streams */
730 azx_writeb(chip, INTCTL, 0);
731
732 /* disable controller CIE and GIE */
733 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
734 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
735}
736
737/* clear interrupts */
a98f90fd 738static void azx_int_clear(struct azx *chip)
1da177e4
LT		 739{
740 int i;
741
742 /* clear stream status */
07e4ca50 743 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 744 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 745 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
746 }
747
748 /* clear STATESTS */
749 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
750
751 /* clear rirb status */
752 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
753
754 /* clear int status */
755 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
756}
757
758/* start a stream */
a98f90fd 759static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 760{
761 /* enable SIE */
762 azx_writeb(chip, INTCTL,
763 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
764 /* set DMA start and interrupt mask */
765 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
766 SD_CTL_DMA_START | SD_INT_MASK);
767}
768
769/* stop a stream */
a98f90fd 770static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 771{
772 /* stop DMA */
773 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
774 ~(SD_CTL_DMA_START | SD_INT_MASK));
775 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
776 /* disable SIE */
777 azx_writeb(chip, INTCTL,
778 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
779}
780
781
782/*
783 * initialize the chip
784 */
a98f90fd 785static void azx_init_chip(struct azx *chip)
1da177e4 786{
da3fca21 787 unsigned char reg;
1da177e4
LT		 788
789 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
790 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
791 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
792 */
da3fca21
V		 793 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
794 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
1da177e4
LT		 795
796 /* reset controller */
797 azx_reset(chip);
798
799 /* initialize interrupts */
800 azx_int_clear(chip);
801 azx_int_enable(chip);
802
803 /* initialize the codec command I/O */
927fc866 804 if (!chip->single_cmd)
27346166 805 azx_init_cmd_io(chip);
1da177e4 806
0be3b5d3
TI		 807 /* program the position buffer */
808 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
809 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 810
da3fca21
V		 811 switch (chip->driver_type) {
812 case AZX_DRIVER_ATI:
813 /* For ATI SB450 azalia HD audio, we need to enable snoop */
f5d40b30 814 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21 815 &reg);
f5d40b30 816 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21
V		 817 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
818 break;
819 case AZX_DRIVER_NVIDIA:
820 /* For NVIDIA HDA, enable snoop */
821 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
822 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
823 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
824 break;
825 }
1da177e4
LT		 826}
827
828
829/*
830 * interrupt handler
831 */
7d12e780 832static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 833{
a98f90fd
TI		 834 struct azx *chip = dev_id;
835 struct azx_dev *azx_dev;
1da177e4
LT		 836 u32 status;
837 int i;
838
839 spin_lock(&chip->reg_lock);
840
841 status = azx_readl(chip, INTSTS);
842 if (status == 0) {
843 spin_unlock(&chip->reg_lock);
844 return IRQ_NONE;
845 }
846
07e4ca50 847 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 848 azx_dev = &chip->azx_dev[i];
849 if (status & azx_dev->sd_int_sta_mask) {
850 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
851 if (azx_dev->substream && azx_dev->running) {
1a56f8d6 852 azx_dev->period_intr++;
1da177e4
LT		 853 spin_unlock(&chip->reg_lock);
854 snd_pcm_period_elapsed(azx_dev->substream);
855 spin_lock(&chip->reg_lock);
856 }
857 }
858 }
859
860 /* clear rirb int */
861 status = azx_readb(chip, RIRBSTS);
862 if (status & RIRB_INT_MASK) {
27346166 863 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 864 azx_update_rirb(chip);
865 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
866 }
867
868#if 0
869 /* clear state status int */
870 if (azx_readb(chip, STATESTS) & 0x04)
871 azx_writeb(chip, STATESTS, 0x04);
872#endif
873 spin_unlock(&chip->reg_lock);
874
875 return IRQ_HANDLED;
876}
877
878
879/*
880 * set up BDL entries
881 */
a98f90fd 882static void azx_setup_periods(struct azx_dev *azx_dev)
1da177e4
LT		 883{
884 u32 *bdl = azx_dev->bdl;
885 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
886 int idx;
887
888 /* reset BDL address */
889 azx_sd_writel(azx_dev, SD_BDLPL, 0);
890 azx_sd_writel(azx_dev, SD_BDLPU, 0);
891
892 /* program the initial BDL entries */
893 for (idx = 0; idx < azx_dev->frags; idx++) {
894 unsigned int off = idx << 2; /* 4 dword step */
895 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
896 /* program the address field of the BDL entry */
897 bdl[off] = cpu_to_le32((u32)addr);
898 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
899
900 /* program the size field of the BDL entry */
901 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
902
903 /* program the IOC to enable interrupt when buffer completes */
904 bdl[off+3] = cpu_to_le32(0x01);
905 }
906}
907
908/*
909 * set up the SD for streaming
910 */
a98f90fd 911static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 912{
913 unsigned char val;
914 int timeout;
915
916 /* make sure the run bit is zero for SD */
917 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
918 /* reset stream */
919 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
920 udelay(3);
921 timeout = 300;
922 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
923 --timeout)
924 ;
925 val &= ~SD_CTL_STREAM_RESET;
926 azx_sd_writeb(azx_dev, SD_CTL, val);
927 udelay(3);
928
929 timeout = 300;
930 /* waiting for hardware to report that the stream is out of reset */
931 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
932 --timeout)
933 ;
934
935 /* program the stream_tag */
936 azx_sd_writel(azx_dev, SD_CTL,
937 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
938 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
939
940 /* program the length of samples in cyclic buffer */
941 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
942
943 /* program the stream format */
944 /* this value needs to be the same as the one programmed */
945 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
946
947 /* program the stream LVI (last valid index) of the BDL */
948 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
949
950 /* program the BDL address */
951 /* lower BDL address */
952 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
953 /* upper BDL address */
954 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
955
0be3b5d3
TI		 956 /* enable the position buffer */
957 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
958 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
c74db86b 959
1da177e4
LT		 960 /* set the interrupt enable bits in the descriptor control register */
961 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
962
963 return 0;
964}
965
966
967/*
968 * Codec initialization
969 */
970
a9995a35
TI		 971static unsigned int azx_max_codecs[] __devinitdata = {
972 [AZX_DRIVER_ICH] = 3,
973 [AZX_DRIVER_ATI] = 4,
974 [AZX_DRIVER_ATIHDMI] = 4,
975 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
976 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
977 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
978 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
979};
980
a98f90fd 981static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 982{
983 struct hda_bus_template bus_temp;
bccad14e 984 int c, codecs, audio_codecs, err;
1da177e4
LT		 985
986 memset(&bus_temp, 0, sizeof(bus_temp));
987 bus_temp.private_data = chip;
988 bus_temp.modelname = model;
989 bus_temp.pci = chip->pci;
111d3af5
TI		 990 bus_temp.ops.command = azx_send_cmd;
991 bus_temp.ops.get_response = azx_get_response;
1da177e4
LT		 992
993 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
994 return err;
995
bccad14e 996 codecs = audio_codecs = 0;
19a982b6 997 for (c = 0; c < AZX_MAX_CODECS; c++) {
606ad75f 998 if ((chip->codec_mask & (1 << c)) & probe_mask) {
bccad14e
TI		 999 struct hda_codec *codec;
1000 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1001 if (err < 0)
1002 continue;
1003 codecs++;
bccad14e
TI		 1004 if (codec->afg)
1005 audio_codecs++;
1da177e4
LT		 1006 }
1007 }
bccad14e 1008 if (!audio_codecs) {
19a982b6
TI		 1009 /* probe additional slots if no codec is found */
1010 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1011 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1012 err = snd_hda_codec_new(chip->bus, c, NULL);
1013 if (err < 0)
1014 continue;
1015 codecs++;
1016 }
1017 }
1018 }
1019 if (!codecs) {
1da177e4
LT		 1020 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1021 return -ENXIO;
1022 }
1023
1024 return 0;
1025}
1026
1027
1028/*
1029 * PCM support
1030 */
1031
1032/* assign a stream for the PCM */
a98f90fd 1033static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1034{
07e4ca50
TI		 1035 int dev, i, nums;
1036 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1037 dev = chip->playback_index_offset;
1038 nums = chip->playback_streams;
1039 } else {
1040 dev = chip->capture_index_offset;
1041 nums = chip->capture_streams;
1042 }
1043 for (i = 0; i < nums; i++, dev++)
1da177e4
LT		 1044 if (! chip->azx_dev[dev].opened) {
1045 chip->azx_dev[dev].opened = 1;
1046 return &chip->azx_dev[dev];
1047 }
1048 return NULL;
1049}
1050
1051/* release the assigned stream */
a98f90fd 1052static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1053{
1054 azx_dev->opened = 0;
1055}
1056
a98f90fd 1057static struct snd_pcm_hardware azx_pcm_hw = {
1da177e4
LT		 1058 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1059 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1060 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1061 /* No full-resume yet implemented */
1062 /* SNDRV_PCM_INFO_RESUME |*/
1063 SNDRV_PCM_INFO_PAUSE),
1da177e4
LT		 1064 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1065 .rates = SNDRV_PCM_RATE_48000,
1066 .rate_min = 48000,
1067 .rate_max = 48000,
1068 .channels_min = 2,
1069 .channels_max = 2,
1070 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1071 .period_bytes_min = 128,
1072 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1073 .periods_min = 2,
1074 .periods_max = AZX_MAX_FRAG,
1075 .fifo_size = 0,
1076};
1077
1078struct azx_pcm {
a98f90fd 1079 struct azx *chip;
1da177e4
LT		 1080 struct hda_codec *codec;
1081 struct hda_pcm_stream *hinfo[2];
1082};
1083
a98f90fd 1084static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1085{
1086 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1087 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1088 struct azx *chip = apcm->chip;
1089 struct azx_dev *azx_dev;
1090 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1091 unsigned long flags;
1092 int err;
1093
62932df8 1094 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1095 azx_dev = azx_assign_device(chip, substream->stream);
1096 if (azx_dev == NULL) {
62932df8 1097 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1098 return -EBUSY;
1099 }
1100 runtime->hw = azx_pcm_hw;
1101 runtime->hw.channels_min = hinfo->channels_min;
1102 runtime->hw.channels_max = hinfo->channels_max;
1103 runtime->hw.formats = hinfo->formats;
1104 runtime->hw.rates = hinfo->rates;
1105 snd_pcm_limit_hw_rates(runtime);
1106 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1107 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1108 128);
1109 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1110 128);
1da177e4
LT		 1111 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1112 azx_release_device(azx_dev);
62932df8 1113 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1114 return err;
1115 }
1116 spin_lock_irqsave(&chip->reg_lock, flags);
1117 azx_dev->substream = substream;
1118 azx_dev->running = 0;
1119 spin_unlock_irqrestore(&chip->reg_lock, flags);
1120
1121 runtime->private_data = azx_dev;
62932df8 1122 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1123 return 0;
1124}
1125
a98f90fd 1126static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1127{
1128 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1129 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1130 struct azx *chip = apcm->chip;
1131 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1132 unsigned long flags;
1133
62932df8 1134 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1135 spin_lock_irqsave(&chip->reg_lock, flags);
1136 azx_dev->substream = NULL;
1137 azx_dev->running = 0;
1138 spin_unlock_irqrestore(&chip->reg_lock, flags);
1139 azx_release_device(azx_dev);
1140 hinfo->ops.close(hinfo, apcm->codec, substream);
62932df8 1141 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1142 return 0;
1143}
1144
a98f90fd 1145static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 1146{
1147 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1148}
1149
a98f90fd 1150static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1151{
1152 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1153 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1154 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1155
1156 /* reset BDL address */
1157 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1158 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1159 azx_sd_writel(azx_dev, SD_CTL, 0);
1160
1161 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1162
1163 return snd_pcm_lib_free_pages(substream);
1164}
1165
a98f90fd 1166static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1167{
1168 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1169 struct azx *chip = apcm->chip;
1170 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1171 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1172 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1173
1174 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1175 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1176 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1177 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1178 runtime->channels,
1179 runtime->format,
1180 hinfo->maxbps);
1181 if (! azx_dev->format_val) {
1182 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1183 runtime->rate, runtime->channels, runtime->format);
1184 return -EINVAL;
1185 }
1186
1187 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1188 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1189 azx_setup_periods(azx_dev);
1190 azx_setup_controller(chip, azx_dev);
1191 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1192 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1193 else
1194 azx_dev->fifo_size = 0;
1195
1196 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1197 azx_dev->format_val, substream);
1198}
1199
a98f90fd 1200static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1201{
1202 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1203 struct azx_dev *azx_dev = get_azx_dev(substream);
1204 struct azx *chip = apcm->chip;
1da177e4
LT		 1205 int err = 0;
1206
1207 spin_lock(&chip->reg_lock);
1208 switch (cmd) {
1209 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1210 case SNDRV_PCM_TRIGGER_RESUME:
1211 case SNDRV_PCM_TRIGGER_START:
1212 azx_stream_start(chip, azx_dev);
1213 azx_dev->running = 1;
1214 break;
1215 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1216 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1217 case SNDRV_PCM_TRIGGER_STOP:
1218 azx_stream_stop(chip, azx_dev);
1219 azx_dev->running = 0;
1220 break;
1221 default:
1222 err = -EINVAL;
1223 }
1224 spin_unlock(&chip->reg_lock);
1225 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
47123197 1226 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1da177e4
LT		 1227 cmd == SNDRV_PCM_TRIGGER_STOP) {
1228 int timeout = 5000;
1229 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1230 ;
1231 }
1232 return err;
1233}
1234
a98f90fd 1235static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1236{
c74db86b 1237 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1238 struct azx *chip = apcm->chip;
1239 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1240 unsigned int pos;
1241
1a56f8d6
TI		 1242 if (chip->position_fix == POS_FIX_POSBUF ||
1243 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1244 /* use the position buffer */
929861c6 1245 pos = le32_to_cpu(*azx_dev->posbuf);
1a56f8d6
TI		 1246 if (chip->position_fix == POS_FIX_AUTO &&
1247 azx_dev->period_intr == 1 && ! pos) {
1248 printk(KERN_WARNING
1249 "hda-intel: Invalid position buffer, "
1250 "using LPIB read method instead.\n");
1251 chip->position_fix = POS_FIX_NONE;
1252 goto read_lpib;
1253 }
c74db86b 1254 } else {
1a56f8d6 1255 read_lpib:
c74db86b
TI		 1256 /* read LPIB */
1257 pos = azx_sd_readl(azx_dev, SD_LPIB);
1258 if (chip->position_fix == POS_FIX_FIFO)
1259 pos += azx_dev->fifo_size;
1260 }
1da177e4
LT		 1261 if (pos >= azx_dev->bufsize)
1262 pos = 0;
1263 return bytes_to_frames(substream->runtime, pos);
1264}
1265
a98f90fd 1266static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1267 .open = azx_pcm_open,
1268 .close = azx_pcm_close,
1269 .ioctl = snd_pcm_lib_ioctl,
1270 .hw_params = azx_pcm_hw_params,
1271 .hw_free = azx_pcm_hw_free,
1272 .prepare = azx_pcm_prepare,
1273 .trigger = azx_pcm_trigger,
1274 .pointer = azx_pcm_pointer,
1275};
1276
a98f90fd 1277static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4
LT		 1278{
1279 kfree(pcm->private_data);
1280}
1281
a98f90fd 1282static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1da177e4
LT		 1283 struct hda_pcm *cpcm, int pcm_dev)
1284{
1285 int err;
a98f90fd 1286 struct snd_pcm *pcm;
1da177e4
LT		 1287 struct azx_pcm *apcm;
1288
e08a007d
TI		 1289 /* if no substreams are defined for both playback and capture,
1290 * it's just a placeholder. ignore it.
1291 */
1292 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1293 return 0;
1294
1da177e4
LT		 1295 snd_assert(cpcm->name, return -EINVAL);
1296
1297 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1298 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1299 &pcm);
1300 if (err < 0)
1301 return err;
1302 strcpy(pcm->name, cpcm->name);
1303 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1304 if (apcm == NULL)
1305 return -ENOMEM;
1306 apcm->chip = chip;
1307 apcm->codec = codec;
1308 apcm->hinfo[0] = &cpcm->stream[0];
1309 apcm->hinfo[1] = &cpcm->stream[1];
1310 pcm->private_data = apcm;
1311 pcm->private_free = azx_pcm_free;
1312 if (cpcm->stream[0].substreams)
1313 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1314 if (cpcm->stream[1].substreams)
1315 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1316 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1317 snd_dma_pci_data(chip->pci),
b66b3cfe 1318 1024 * 64, 1024 * 1024);
1da177e4 1319 chip->pcm[pcm_dev] = pcm;
e08a007d
TI		 1320 if (chip->pcm_devs < pcm_dev + 1)
1321 chip->pcm_devs = pcm_dev + 1;
1da177e4
LT		 1322
1323 return 0;
1324}
1325
a98f90fd 1326static int __devinit azx_pcm_create(struct azx *chip)
1da177e4
LT		 1327{
1328 struct list_head *p;
1329 struct hda_codec *codec;
1330 int c, err;
1331 int pcm_dev;
1332
1333 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1334 return err;
1335
ec9e1c5c 1336 /* create audio PCMs */
1da177e4
LT		 1337 pcm_dev = 0;
1338 list_for_each(p, &chip->bus->codec_list) {
1339 codec = list_entry(p, struct hda_codec, list);
1340 for (c = 0; c < codec->num_pcms; c++) {
ec9e1c5c
TI		 1341 if (codec->pcm_info[c].is_modem)
1342 continue; /* create later */
1343 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1344 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1345 return -EINVAL;
1346 }
1347 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1348 if (err < 0)
1349 return err;
1350 pcm_dev++;
1351 }
1352 }
1353
1354 /* create modem PCMs */
1355 pcm_dev = AZX_MAX_AUDIO_PCMS;
1356 list_for_each(p, &chip->bus->codec_list) {
1357 codec = list_entry(p, struct hda_codec, list);
1358 for (c = 0; c < codec->num_pcms; c++) {
1359 if (! codec->pcm_info[c].is_modem)
1360 continue; /* already created */
a28f1cda 1361 if (pcm_dev >= AZX_MAX_PCMS) {
ec9e1c5c 1362 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1da177e4
LT		 1363 return -EINVAL;
1364 }
1365 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1366 if (err < 0)
1367 return err;
6632d198 1368 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1da177e4
LT		 1369 pcm_dev++;
1370 }
1371 }
1372 return 0;
1373}
1374
1375/*
1376 * mixer creation - all stuff is implemented in hda module
1377 */
a98f90fd 1378static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1379{
1380 return snd_hda_build_controls(chip->bus);
1381}
1382
1383
1384/*
1385 * initialize SD streams
1386 */
a98f90fd 1387static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1388{
1389 int i;
1390
1391 /* initialize each stream (aka device)
1392 * assign the starting bdl address to each stream (device) and initialize
1393 */
07e4ca50 1394 for (i = 0; i < chip->num_streams; i++) {
1da177e4 1395 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
a98f90fd 1396 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1397 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1398 azx_dev->bdl_addr = chip->bdl.addr + off;
929861c6 1399 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1400 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1401 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1402 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1403 azx_dev->sd_int_sta_mask = 1 << i;
1404 /* stream tag: must be non-zero and unique */
1405 azx_dev->index = i;
1406 azx_dev->stream_tag = i + 1;
1407 }
1408
1409 return 0;
1410}
1411
68e7fffc
TI		 1412static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1413{
437a5a46
TI		 1414 if (request_irq(chip->pci->irq, azx_interrupt,
1415 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1416 "HDA Intel", chip)) {
1417 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1418 "disabling device\n", chip->pci->irq);
1419 if (do_disconnect)
1420 snd_card_disconnect(chip->card);
1421 return -1;
1422 }
1423 chip->irq = chip->pci->irq;
69e13418 1424 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1425 return 0;
1426}
1427
1da177e4
LT		 1428
1429#ifdef CONFIG_PM
1430/*
1431 * power management
1432 */
421a1252 1433static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1434{
421a1252
TI		 1435 struct snd_card *card = pci_get_drvdata(pci);
1436 struct azx *chip = card->private_data;
1da177e4
LT		 1437 int i;
1438
421a1252 1439 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4 1440 for (i = 0; i < chip->pcm_devs; i++)
421a1252 1441 snd_pcm_suspend_all(chip->pcm[i]);
1da177e4 1442 snd_hda_suspend(chip->bus, state);
111d3af5 1443 azx_free_cmd_io(chip);
30b35399
TI		 1444 if (chip->irq >= 0) {
1445 synchronize_irq(chip->irq);
43001c95 1446 free_irq(chip->irq, chip);
30b35399
TI		 1447 chip->irq = -1;
1448 }
68e7fffc 1449 if (chip->msi)
43001c95 1450 pci_disable_msi(chip->pci);
421a1252
TI		 1451 pci_disable_device(pci);
1452 pci_save_state(pci);
30b35399 1453 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1454 return 0;
1455}
1456
421a1252 1457static int azx_resume(struct pci_dev *pci)
1da177e4 1458{
421a1252
TI		 1459 struct snd_card *card = pci_get_drvdata(pci);
1460 struct azx *chip = card->private_data;
1da177e4 1461
30b35399 1462 pci_set_power_state(pci, PCI_D0);
421a1252 1463 pci_restore_state(pci);
30b35399
TI		 1464 if (pci_enable_device(pci) < 0) {
1465 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1466 "disabling device\n");
1467 snd_card_disconnect(card);
1468 return -EIO;
1469 }
1470 pci_set_master(pci);
68e7fffc
TI		 1471 if (chip->msi)
1472 if (pci_enable_msi(pci) < 0)
1473 chip->msi = 0;
1474 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1475 return -EIO;
1da177e4
LT		 1476 azx_init_chip(chip);
1477 snd_hda_resume(chip->bus);
421a1252 1478 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1479 return 0;
1480}
1481#endif /* CONFIG_PM */
1482
1483
1484/*
1485 * destructor
1486 */
a98f90fd 1487static int azx_free(struct azx *chip)
1da177e4 1488{
ce43fbae 1489 if (chip->initialized) {
1da177e4
LT		 1490 int i;
1491
07e4ca50 1492 for (i = 0; i < chip->num_streams; i++)
1da177e4
LT		 1493 azx_stream_stop(chip, &chip->azx_dev[i]);
1494
1495 /* disable interrupts */
1496 azx_int_disable(chip);
1497 azx_int_clear(chip);
1498
1499 /* disable CORB/RIRB */
111d3af5 1500 azx_free_cmd_io(chip);
1da177e4
LT		 1501
1502 /* disable position buffer */
1503 azx_writel(chip, DPLBASE, 0);
1504 azx_writel(chip, DPUBASE, 0);
1da177e4
LT		 1505 }
1506
7376d013 1507 if (chip->irq >= 0) {
30b35399 1508 synchronize_irq(chip->irq);
1da177e4 1509 free_irq(chip->irq, (void*)chip);
7376d013 1510 }
68e7fffc 1511 if (chip->msi)
30b35399 1512 pci_disable_msi(chip->pci);
f079c25a
TI		 1513 if (chip->remap_addr)
1514 iounmap(chip->remap_addr);
1da177e4
LT		 1515
1516 if (chip->bdl.area)
1517 snd_dma_free_pages(&chip->bdl);
1518 if (chip->rb.area)
1519 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 1520 if (chip->posbuf.area)
1521 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 1522 pci_release_regions(chip->pci);
1523 pci_disable_device(chip->pci);
07e4ca50 1524 kfree(chip->azx_dev);
1da177e4
LT		 1525 kfree(chip);
1526
1527 return 0;
1528}
1529
a98f90fd 1530static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1531{
1532 return azx_free(device->device_data);
1533}
1534
3372a153
TI		 1535/*
1536 * white/black-listing for position_fix
1537 */
623ec047 1538static struct snd_pci_quirk position_fix_list[] __devinitdata = {
3372a153
TI		 1539 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1540 {}
1541};
1542
1543static int __devinit check_position_fix(struct azx *chip, int fix)
1544{
1545 const struct snd_pci_quirk *q;
1546
1547 if (fix == POS_FIX_AUTO) {
1548 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1549 if (q) {
1550 snd_printdd(KERN_INFO
1551 "hda_intel: position_fix set to %d "
1552 "for device %04x:%04x\n",
1553 q->value, q->subvendor, q->subdevice);
1554 return q->value;
1555 }
1556 }
1557 return fix;
1558}
1559
1da177e4
LT		 1560/*
1561 * constructor
1562 */
a98f90fd 1563static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
606ad75f 1564 int driver_type,
a98f90fd 1565 struct azx **rchip)
1da177e4 1566{
a98f90fd 1567 struct azx *chip;
927fc866 1568 int err;
a98f90fd 1569 static struct snd_device_ops ops = {
1da177e4
LT		 1570 .dev_free = azx_dev_free,
1571 };
1572
1573 *rchip = NULL;
1574
927fc866
PM		 1575 err = pci_enable_device(pci);
1576 if (err < 0)
1da177e4
LT		 1577 return err;
1578
e560d8d8 1579 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1580 if (!chip) {
1da177e4
LT		 1581 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1582 pci_disable_device(pci);
1583 return -ENOMEM;
1584 }
1585
1586 spin_lock_init(&chip->reg_lock);
62932df8 1587 mutex_init(&chip->open_mutex);
1da177e4
LT		 1588 chip->card = card;
1589 chip->pci = pci;
1590 chip->irq = -1;
07e4ca50 1591 chip->driver_type = driver_type;
134a11f0 1592 chip->msi = enable_msi;
1da177e4 1593
3372a153
TI		 1594 chip->position_fix = check_position_fix(chip, position_fix);
1595
27346166 1596 chip->single_cmd = single_cmd;
c74db86b 1597
07e4ca50
TI		 1598#if BITS_PER_LONG != 64
1599 /* Fix up base address on ULI M5461 */
1600 if (chip->driver_type == AZX_DRIVER_ULI) {
1601 u16 tmp3;
1602 pci_read_config_word(pci, 0x40, &tmp3);
1603 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1604 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1605 }
1606#endif
1607
927fc866
PM		 1608 err = pci_request_regions(pci, "ICH HD audio");
1609 if (err < 0) {
1da177e4
LT		 1610 kfree(chip);
1611 pci_disable_device(pci);
1612 return err;
1613 }
1614
927fc866 1615 chip->addr = pci_resource_start(pci, 0);
1da177e4
LT		 1616 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1617 if (chip->remap_addr == NULL) {
1618 snd_printk(KERN_ERR SFX "ioremap error\n");
1619 err = -ENXIO;
1620 goto errout;
1621 }
1622
68e7fffc
TI		 1623 if (chip->msi)
1624 if (pci_enable_msi(pci) < 0)
1625 chip->msi = 0;
7376d013 1626
68e7fffc 1627 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 1628 err = -EBUSY;
1629 goto errout;
1630 }
1da177e4
LT		 1631
1632 pci_set_master(pci);
1633 synchronize_irq(chip->irq);
1634
07e4ca50
TI		 1635 switch (chip->driver_type) {
1636 case AZX_DRIVER_ULI:
1637 chip->playback_streams = ULI_NUM_PLAYBACK;
1638 chip->capture_streams = ULI_NUM_CAPTURE;
1639 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1640 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1641 break;
778b6e1b
FK		 1642 case AZX_DRIVER_ATIHDMI:
1643 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1644 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1645 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1646 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1647 break;
07e4ca50
TI		 1648 default:
1649 chip->playback_streams = ICH6_NUM_PLAYBACK;
1650 chip->capture_streams = ICH6_NUM_CAPTURE;
1651 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1652 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1653 break;
1654 }
1655 chip->num_streams = chip->playback_streams + chip->capture_streams;
1656 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
927fc866 1657 if (!chip->azx_dev) {
07e4ca50
TI		 1658 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1659 goto errout;
1660 }
1661
1da177e4
LT		 1662 /* allocate memory for the BDL for each stream */
1663 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
07e4ca50 1664 BDL_SIZE, &chip->bdl)) < 0) {
1da177e4
LT		 1665 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1666 goto errout;
1667 }
0be3b5d3
TI		 1668 /* allocate memory for the position buffer */
1669 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1670 chip->num_streams * 8, &chip->posbuf)) < 0) {
1671 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1672 goto errout;
1da177e4 1673 }
1da177e4 1674 /* allocate CORB/RIRB */
27346166
TI		 1675 if (! chip->single_cmd)
1676 if ((err = azx_alloc_cmd_io(chip)) < 0)
1677 goto errout;
1da177e4
LT		 1678
1679 /* initialize streams */
1680 azx_init_stream(chip);
1681
1682 /* initialize chip */
1683 azx_init_chip(chip);
1684
ce43fbae
TI		 1685 chip->initialized = 1;
1686
1da177e4 1687 /* codec detection */
927fc866 1688 if (!chip->codec_mask) {
1da177e4
LT		 1689 snd_printk(KERN_ERR SFX "no codecs found!\n");
1690 err = -ENODEV;
1691 goto errout;
1692 }
1693
1694 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1695 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1696 goto errout;
1697 }
1698
07e4ca50
TI		 1699 strcpy(card->driver, "HDA-Intel");
1700 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1701 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1702
1da177e4
LT		 1703 *rchip = chip;
1704 return 0;
1705
1706 errout:
1707 azx_free(chip);
1708 return err;
1709}
1710
1711static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1712{
a98f90fd
TI		 1713 struct snd_card *card;
1714 struct azx *chip;
927fc866 1715 int err;
1da177e4 1716
b7fe4622 1717 card = snd_card_new(index, id, THIS_MODULE, 0);
927fc866 1718 if (!card) {
1da177e4
LT		 1719 snd_printk(KERN_ERR SFX "Error creating card!\n");
1720 return -ENOMEM;
1721 }
1722
927fc866
PM		 1723 err = azx_create(card, pci, pci_id->driver_data, &chip);
1724 if (err < 0) {
1da177e4
LT		 1725 snd_card_free(card);
1726 return err;
1727 }
421a1252 1728 card->private_data = chip;
1da177e4 1729
1da177e4 1730 /* create codec instances */
b7fe4622 1731 if ((err = azx_codec_create(chip, model)) < 0) {
1da177e4
LT		 1732 snd_card_free(card);
1733 return err;
1734 }
1735
1736 /* create PCM streams */
1737 if ((err = azx_pcm_create(chip)) < 0) {
1738 snd_card_free(card);
1739 return err;
1740 }
1741
1742 /* create mixer controls */
1743 if ((err = azx_mixer_create(chip)) < 0) {
1744 snd_card_free(card);
1745 return err;
1746 }
1747
1da177e4
LT		 1748 snd_card_set_dev(card, &pci->dev);
1749
1750 if ((err = snd_card_register(card)) < 0) {
1751 snd_card_free(card);
1752 return err;
1753 }
1754
1755 pci_set_drvdata(pci, card);
1da177e4
LT		 1756
1757 return err;
1758}
1759
1760static void __devexit azx_remove(struct pci_dev *pci)
1761{
1762 snd_card_free(pci_get_drvdata(pci));
1763 pci_set_drvdata(pci, NULL);
1764}
1765
1766/* PCI IDs */
f40b6890 1767static struct pci_device_id azx_ids[] = {
07e4ca50
TI		 1768 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1769 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1770 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
d2981393 1771 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
f9cc8a8b
JG		 1772 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1773 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
07e4ca50 1774 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
89be83f8 1775 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
778b6e1b 1776 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
5b15c95f 1777 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
e6db1119
WL		 1778 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1779 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
07e4ca50
TI		 1780 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1781 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1782 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
5b005a01
PC		 1783 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1784 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1785 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1786 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1787 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1788 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1789 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1790 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1da177e4
LT		 1791 { 0, }
1792};
1793MODULE_DEVICE_TABLE(pci, azx_ids);
1794
1795/* pci_driver definition */
1796static struct pci_driver driver = {
1797 .name = "HDA Intel",
1798 .id_table = azx_ids,
1799 .probe = azx_probe,
1800 .remove = __devexit_p(azx_remove),
421a1252
TI		 1801#ifdef CONFIG_PM
1802 .suspend = azx_suspend,
1803 .resume = azx_resume,
1804#endif
1da177e4
LT		 1805};
1806
1807static int __init alsa_card_azx_init(void)
1808{
01d25d46 1809 return pci_register_driver(&driver);
1da177e4
LT		 1810}
1811
1812static void __exit alsa_card_azx_exit(void)
1813{
1814 pci_unregister_driver(&driver);
1815}
1816
1817module_init(alsa_card_azx_init)
1818module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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