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ALSA: hda - Fix Skylake codec timeout
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
93#define INTEL_SCH_HDA_DEVC 0x78
94#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96/* Define IN stream 0 FIFO size offset in VIA controller */
97#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98/* Define VIA HD Audio Device ID*/
99#define VIA_HDAC_DEVICE_ID 0x3288
100
33124929
TI		 101/* max number of SDs */
102/* ICH, ATI and VIA have 4 playback and 4 capture */
103#define ICH6_NUM_CAPTURE 4
104#define ICH6_NUM_PLAYBACK 4
105
106/* ULI has 6 playback and 5 capture */
107#define ULI_NUM_CAPTURE 5
108#define ULI_NUM_PLAYBACK 6
109
110/* ATI HDMI may have up to 8 playbacks and 0 capture */
111#define ATIHDMI_NUM_CAPTURE 0
112#define ATIHDMI_NUM_PLAYBACK 8
113
114/* TERA has 4 playback and 3 capture */
115#define TERA_NUM_CAPTURE 3
116#define TERA_NUM_PLAYBACK 4
117
1da177e4 118
5aba4f8e
TI		 119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 122static char *model[SNDRV_CARDS];
1dac6695 123static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 124static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 125static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 126static int probe_only[SNDRV_CARDS];
26a6cb6c 127static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 128static bool single_cmd;
71623855 129static int enable_msi = -1;
4ea6fbc8
TI		 130#ifdef CONFIG_SND_HDA_PATCH_LOADER
131static char *patch[SNDRV_CARDS];
132#endif
2dca0bba 133#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 134static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136#endif
1da177e4 137
5aba4f8e 138module_param_array(index, int, NULL, 0444);
1da177e4 139MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 140module_param_array(id, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 142module_param_array(enable, bool, NULL, 0444);
143MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144module_param_array(model, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 146module_param_array(position_fix, int, NULL, 0444);
4cb36310 147MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 149module_param_array(bdl_pos_adj, int, NULL, 0644);
150MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 151module_param_array(probe_mask, int, NULL, 0444);
606ad75f 152MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 153module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 154MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 155module_param_array(jackpoll_ms, int, NULL, 0444);
156MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 157module_param(single_cmd, bool, 0444);
d01ce99f
TI		 158MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
ac9ef6cf 160module_param(enable_msi, bint, 0444);
134a11f0 161MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 162#ifdef CONFIG_SND_HDA_PATCH_LOADER
163module_param_array(patch, charp, NULL, 0444);
164MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165#endif
2dca0bba 166#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 167module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 168MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 169 "(0=off, 1=on) (default=1).");
2dca0bba 170#endif
606ad75f 171
83012a7c 172#ifdef CONFIG_PM
65fcd41d
TI		 173static int param_set_xint(const char *val, const struct kernel_param *kp);
174static struct kernel_param_ops param_ops_xint = {
175 .set = param_set_xint,
176 .get = param_get_int,
177};
178#define param_check_xint param_check_int
179
fee2fba3 180static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 181module_param(power_save, xint, 0644);
fee2fba3
TI		 182MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
1da177e4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
fab1285a 262 AZX_DRIVER_HDMI,
07e4ca50 263 AZX_DRIVER_ATI,
778b6e1b 264 AZX_DRIVER_ATIHDMI,
1815b34a 265 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
da3fca21 269 AZX_DRIVER_NVIDIA,
f269002e 270 AZX_DRIVER_TERA,
14d34f16 271 AZX_DRIVER_CTX,
5ae763b1 272 AZX_DRIVER_CTHDA,
c563f473 273 AZX_DRIVER_CMEDIA,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
d7dab4db 287#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 290
291#define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 293
33499a15 294#define AZX_DCAPS_INTEL_HASWELL \
103884a3 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 298
54a0405d
LY		 299/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 304
40cc2392
ML		 305#define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
2d846c74
LY		 308#define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
d6795827 311#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
d6795827 314
9477c58e
TI		 315/* quirks for ATI SB / AMD Hudson */
316#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 319
320/* quirks for ATI/AMD HDMI */
321#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
323 AZX_DCAPS_NO_MSI64)
9477c58e 324
37e661ee
TI		 325/* quirks for ATI HDMI with snoop off */
326#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
328
9477c58e
TI		 329/* quirks for Nvidia */
330#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
333 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 334
5ae763b1 335#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
337 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 338
a82d51ed
TI		 339/*
340 * VGA-switcher support
341 */
342#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 343#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
344#else
345#define use_vga_switcheroo(chip) 0
346#endif
347
03b135ce
LY		 348#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
349 ((pci)->device == 0x0c0c) || \
350 ((pci)->device == 0x0d0c) || \
351 ((pci)->device == 0x160c))
352
48c8b0eb 353static char *driver_short_names[] = {
07e4ca50 354 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 355 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 356 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 357 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 358 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 359 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 360 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
362 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 363 [AZX_DRIVER_ULI] = "HDA ULI M5461",
364 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 365 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 366 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 367 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 368 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 369 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 370};
371
27fe48d9 372#ifdef CONFIG_X86
9ddf1aeb 373static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 374{
9ddf1aeb
TI		 375 int pages;
376
27fe48d9
TI		 377 if (azx_snoop(chip))
378 return;
9ddf1aeb
TI		 379 if (!dmab || !dmab->area || !dmab->bytes)
380 return;
381
382#ifdef CONFIG_SND_DMA_SGBUF
383 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
384 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 385 if (chip->driver_type == AZX_DRIVER_CMEDIA)
386 return; /* deal with only CORB/RIRB buffers */
27fe48d9 387 if (on)
9ddf1aeb 388 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 389 else
9ddf1aeb
TI		 390 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
391 return;
27fe48d9 392 }
9ddf1aeb
TI		 393#endif
394
395 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
396 if (on)
397 set_memory_wc((unsigned long)dmab->area, pages);
398 else
399 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 400}
401
402static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403 bool on)
404{
9ddf1aeb 405 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 406}
407static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 408 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 409{
410 if (azx_dev->wc_marked != on) {
9ddf1aeb 411 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 412 azx_dev->wc_marked = on;
413 }
414}
415#else
416/* NOP for other archs */
417static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419{
420}
421static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 422 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 423{
424}
425#endif
426
68e7fffc 427static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 428
cb53c626
TI		 429/*
430 * initialize the PCI registers
431 */
432/* update bits in a PCI register byte */
433static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
434 unsigned char mask, unsigned char val)
435{
436 unsigned char data;
437
438 pci_read_config_byte(pci, reg, &data);
439 data &= ~mask;
440 data |= (val & mask);
441 pci_write_config_byte(pci, reg, data);
442}
443
444static void azx_init_pci(struct azx *chip)
445{
37e661ee
TI		 446 int snoop_type = azx_get_snoop_type(chip);
447
cb53c626
TI		 448 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
449 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
450 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 451 * codecs.
452 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 453 */
46f2cc80 454 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 455 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 456 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 457 }
cb53c626 458
9477c58e
TI		 459 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
460 * we need to enable snoop.
461 */
37e661ee 462 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 463 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
464 azx_snoop(chip));
cb53c626 465 update_pci_byte(chip->pci,
27fe48d9
TI		 466 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
467 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 468 }
469
470 /* For NVIDIA HDA, enable snoop */
37e661ee 471 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 472 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
473 azx_snoop(chip));
cb53c626
TI		 474 update_pci_byte(chip->pci,
475 NVIDIA_HDA_TRANSREG_ADDR,
476 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 477 update_pci_byte(chip->pci,
478 NVIDIA_HDA_ISTRM_COH,
479 0x01, NVIDIA_HDA_ENABLE_COHBIT);
480 update_pci_byte(chip->pci,
481 NVIDIA_HDA_OSTRM_COH,
482 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 483 }
484
485 /* Enable SCH/PCH snoop if needed */
37e661ee 486 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 487 unsigned short snoop;
90a5ad52 488 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 489 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
490 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
491 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
492 if (!azx_snoop(chip))
493 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
494 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 495 pci_read_config_word(chip->pci,
496 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 497 }
4e76a883
TI		 498 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
499 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
500 "Disabled" : "Enabled");
da3fca21 501 }
1da177e4
LT		 502}
503
0a673521
LH		 504static void hda_intel_init_chip(struct azx *chip, bool full_reset)
505{
98d8fc6c 506 struct hdac_bus *bus = azx_bus(chip);
0a673521
LH		 507
508 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 509 snd_hdac_set_codec_wakeup(bus, true);
0a673521
LH		 510 azx_init_chip(chip, full_reset);
511 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 512 snd_hdac_set_codec_wakeup(bus, false);
0a673521
LH		 513}
514
b6050ef6
TI		 515/* calculate runtime delay from LPIB */
516static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
517 unsigned int pos)
518{
7833c3f8 519 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 520 int stream = substream->stream;
521 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
522 int delay;
523
524 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
525 delay = pos - lpib_pos;
526 else
527 delay = lpib_pos - pos;
528 if (delay < 0) {
7833c3f8 529 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 530 delay = 0;
531 else
7833c3f8 532 delay += azx_dev->core.bufsize;
b6050ef6
TI		 533 }
534
7833c3f8 535 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 536 dev_info(chip->card->dev,
537 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 538 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 539 delay = 0;
540 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
541 chip->get_delay[stream] = NULL;
542 }
543
544 return bytes_to_frames(substream->runtime, delay);
545}
546
9ad593f6
TI		 547static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
548
7ca954a8
DR		 549/* called from IRQ */
550static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
551{
9a34af4a 552 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 553 int ok;
554
555 ok = azx_position_ok(chip, azx_dev);
556 if (ok == 1) {
557 azx_dev->irq_pending = 0;
558 return ok;
2f35c630 559 } else if (ok == 0) {
7ca954a8
DR		 560 /* bogus IRQ, process it later */
561 azx_dev->irq_pending = 1;
2f35c630 562 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 563 }
564 return 0;
565}
566
17eccb27
ML		 567/* Enable/disable i915 display power for the link */
568static int azx_intel_link_power(struct azx *chip, bool enable)
569{
98d8fc6c 570 struct hdac_bus *bus = azx_bus(chip);
17eccb27 571
98d8fc6c 572 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 573}
574
9ad593f6
TI		 575/*
576 * Check whether the current DMA position is acceptable for updating
577 * periods. Returns non-zero if it's OK.
578 *
579 * Many HD-audio controllers appear pretty inaccurate about
580 * the update-IRQ timing. The IRQ is issued before actually the
581 * data is processed. So, we need to process it afterwords in a
582 * workqueue.
583 */
584static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
585{
7833c3f8 586 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 587 int stream = substream->stream;
e5463720 588 u32 wallclk;
9ad593f6
TI		 589 unsigned int pos;
590
7833c3f8
TI		 591 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
592 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 593 return -1; /* bogus (too early) interrupt */
fa00e046 594
b6050ef6
TI		 595 if (chip->get_position[stream])
596 pos = chip->get_position[stream](chip, azx_dev);
597 else { /* use the position buffer as default */
598 pos = azx_get_pos_posbuf(chip, azx_dev);
599 if (!pos || pos == (u32)-1) {
600 dev_info(chip->card->dev,
601 "Invalid position buffer, using LPIB read method instead.\n");
602 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 603 if (chip->get_position[0] == azx_get_pos_lpib &&
604 chip->get_position[1] == azx_get_pos_lpib)
605 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 606 pos = azx_get_pos_lpib(chip, azx_dev);
607 chip->get_delay[stream] = NULL;
608 } else {
609 chip->get_position[stream] = azx_get_pos_posbuf;
610 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
611 chip->get_delay[stream] = azx_get_delay_from_lpib;
612 }
613 }
614
7833c3f8 615 if (pos >= azx_dev->core.bufsize)
b6050ef6 616 pos = 0;
9ad593f6 617
7833c3f8 618 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 619 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 620 return -1; /* this shouldn't happen! */
7833c3f8
TI		 621 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
622 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 623 /* NG - it's below the first next period boundary */
9cdc0115 624 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
7833c3f8 625 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 626 return 1; /* OK, it's fine */
627}
628
629/*
630 * The work for pending PCM period updates.
631 */
632static void azx_irq_pending_work(struct work_struct *work)
633{
9a34af4a
TI		 634 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
635 struct azx *chip = &hda->chip;
7833c3f8
TI		 636 struct hdac_bus *bus = azx_bus(chip);
637 struct hdac_stream *s;
638 int pending, ok;
9ad593f6 639
9a34af4a 640 if (!hda->irq_pending_warned) {
4e76a883
TI		 641 dev_info(chip->card->dev,
642 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
643 chip->card->number);
9a34af4a 644 hda->irq_pending_warned = 1;
a6a950a8
TI		 645 }
646
9ad593f6
TI		 647 for (;;) {
648 pending = 0;
a41d1224 649 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 650 list_for_each_entry(s, &bus->stream_list, list) {
651 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 652 if (!azx_dev->irq_pending ||
7833c3f8
TI		 653 !s->substream ||
654 !s->running)
9ad593f6 655 continue;
e5463720
JK		 656 ok = azx_position_ok(chip, azx_dev);
657 if (ok > 0) {
9ad593f6 658 azx_dev->irq_pending = 0;
a41d1224 659 spin_unlock(&bus->reg_lock);
7833c3f8 660 snd_pcm_period_elapsed(s->substream);
a41d1224 661 spin_lock(&bus->reg_lock);
e5463720
JK		 662 } else if (ok < 0) {
663 pending = 0; /* too early */
9ad593f6
TI		 664 } else
665 pending++;
666 }
a41d1224 667 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 668 if (!pending)
669 return;
08af495f 670 msleep(1);
9ad593f6
TI		 671 }
672}
673
674/* clear irq_pending flags and assure no on-going workq */
675static void azx_clear_irq_pending(struct azx *chip)
676{
7833c3f8
TI		 677 struct hdac_bus *bus = azx_bus(chip);
678 struct hdac_stream *s;
9ad593f6 679
a41d1224 680 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 681 list_for_each_entry(s, &bus->stream_list, list) {
682 struct azx_dev *azx_dev = stream_to_azx_dev(s);
683 azx_dev->irq_pending = 0;
684 }
a41d1224 685 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 686}
687
68e7fffc
TI		 688static int azx_acquire_irq(struct azx *chip, int do_disconnect)
689{
a41d1224
TI		 690 struct hdac_bus *bus = azx_bus(chip);
691
437a5a46
TI		 692 if (request_irq(chip->pci->irq, azx_interrupt,
693 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 694 KBUILD_MODNAME, chip)) {
4e76a883
TI		 695 dev_err(chip->card->dev,
696 "unable to grab IRQ %d, disabling device\n",
697 chip->pci->irq);
68e7fffc
TI		 698 if (do_disconnect)
699 snd_card_disconnect(chip->card);
700 return -1;
701 }
a41d1224 702 bus->irq = chip->pci->irq;
69e13418 703 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 704 return 0;
705}
706
b6050ef6
TI		 707/* get the current DMA position with correction on VIA chips */
708static unsigned int azx_via_get_position(struct azx *chip,
709 struct azx_dev *azx_dev)
710{
711 unsigned int link_pos, mini_pos, bound_pos;
712 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
713 unsigned int fifo_size;
714
1604eeee 715 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 716 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 717 /* Playback, no problem using link position */
718 return link_pos;
719 }
720
721 /* Capture */
722 /* For new chipset,
723 * use mod to get the DMA position just like old chipset
724 */
7833c3f8
TI		 725 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
726 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 727
728 /* azx_dev->fifo_size can't get FIFO size of in stream.
729 * Get from base address + offset.
730 */
a41d1224
TI		 731 fifo_size = readw(azx_bus(chip)->remap_addr +
732 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 733
734 if (azx_dev->insufficient) {
735 /* Link position never gather than FIFO size */
736 if (link_pos <= fifo_size)
737 return 0;
738
739 azx_dev->insufficient = 0;
740 }
741
742 if (link_pos <= fifo_size)
7833c3f8 743 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 744 else
745 mini_pos = link_pos - fifo_size;
746
747 /* Find nearest previous boudary */
7833c3f8
TI		 748 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
749 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 750 if (mod_link_pos >= fifo_size)
751 bound_pos = link_pos - mod_link_pos;
752 else if (mod_dma_pos >= mod_mini_pos)
753 bound_pos = mini_pos - mod_mini_pos;
754 else {
7833c3f8
TI		 755 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
756 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 757 bound_pos = 0;
758 }
759
760 /* Calculate real DMA position we want */
761 return bound_pos + mod_dma_pos;
762}
763
83012a7c 764#ifdef CONFIG_PM
65fcd41d
TI		 765static DEFINE_MUTEX(card_list_lock);
766static LIST_HEAD(card_list);
767
768static void azx_add_card_list(struct azx *chip)
769{
9a34af4a 770 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 771 mutex_lock(&card_list_lock);
9a34af4a 772 list_add(&hda->list, &card_list);
65fcd41d
TI		 773 mutex_unlock(&card_list_lock);
774}
775
776static void azx_del_card_list(struct azx *chip)
777{
9a34af4a 778 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 779 mutex_lock(&card_list_lock);
9a34af4a 780 list_del_init(&hda->list);
65fcd41d
TI		 781 mutex_unlock(&card_list_lock);
782}
783
784/* trigger power-save check at writing parameter */
785static int param_set_xint(const char *val, const struct kernel_param *kp)
786{
9a34af4a 787 struct hda_intel *hda;
65fcd41d 788 struct azx *chip;
65fcd41d
TI		 789 int prev = power_save;
790 int ret = param_set_int(val, kp);
791
792 if (ret || prev == power_save)
793 return ret;
794
795 mutex_lock(&card_list_lock);
9a34af4a
TI		 796 list_for_each_entry(hda, &card_list, list) {
797 chip = &hda->chip;
a41d1224 798 if (!hda->probe_continued || chip->disabled)
65fcd41d 799 continue;
a41d1224 800 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 801 }
802 mutex_unlock(&card_list_lock);
803 return 0;
804}
805#else
806#define azx_add_card_list(chip) /* NOP */
807#define azx_del_card_list(chip) /* NOP */
83012a7c 808#endif /* CONFIG_PM */
5c0b9bec 809
98d8fc6c
ML		 810/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
811 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
812 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
813 * BCLK = CDCLK * M / N
814 * The values will be lost when the display power well is disabled and need to
815 * be restored to avoid abnormal playback speed.
816 */
817static void haswell_set_bclk(struct hda_intel *hda)
818{
819 struct azx *chip = &hda->chip;
820 int cdclk_freq;
821 unsigned int bclk_m, bclk_n;
822
823 if (!hda->need_i915_power)
824 return;
825
826 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
827 switch (cdclk_freq) {
828 case 337500:
829 bclk_m = 16;
830 bclk_n = 225;
831 break;
832
833 case 450000:
834 default: /* default CDCLK 450MHz */
835 bclk_m = 4;
836 bclk_n = 75;
837 break;
838
839 case 540000:
840 bclk_m = 4;
841 bclk_n = 90;
842 break;
843
844 case 675000:
845 bclk_m = 8;
846 bclk_n = 225;
847 break;
848 }
849
850 azx_writew(chip, HSW_EM4, bclk_m);
851 azx_writew(chip, HSW_EM5, bclk_n);
852}
853
7ccbde57 854#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 855/*
856 * power management
857 */
68cb2b55 858static int azx_suspend(struct device *dev)
1da177e4 859{
68cb2b55 860 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 861 struct azx *chip;
862 struct hda_intel *hda;
a41d1224 863 struct hdac_bus *bus;
1da177e4 864
2d9772ef
TI		 865 if (!card)
866 return 0;
867
868 chip = card->private_data;
869 hda = container_of(chip, struct hda_intel, chip);
1618e84a 870 if (chip->disabled || hda->init_failed)
c5c21523
TI		 871 return 0;
872
a41d1224 873 bus = azx_bus(chip);
421a1252 874 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 875 azx_clear_irq_pending(chip);
cb53c626 876 azx_stop_chip(chip);
7295b264 877 azx_enter_link_reset(chip);
a41d1224
TI		 878 if (bus->irq >= 0) {
879 free_irq(bus->irq, chip);
880 bus->irq = -1;
30b35399 881 }
a07187c9 882
68e7fffc 883 if (chip->msi)
43001c95 884 pci_disable_msi(chip->pci);
795614dd
ML		 885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
886 && hda->need_i915_power)
98d8fc6c 887 snd_hdac_display_power(bus, false);
785d8c4b
LY		 888
889 trace_azx_suspend(chip);
1da177e4
LT		 890 return 0;
891}
892
68cb2b55 893static int azx_resume(struct device *dev)
1da177e4 894{
68cb2b55
TI		 895 struct pci_dev *pci = to_pci_dev(dev);
896 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 897 struct azx *chip;
898 struct hda_intel *hda;
899
900 if (!card)
901 return 0;
1da177e4 902
2d9772ef
TI		 903 chip = card->private_data;
904 hda = container_of(chip, struct hda_intel, chip);
1618e84a 905 if (chip->disabled || hda->init_failed)
c5c21523
TI		 906 return 0;
907
795614dd
ML		 908 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
909 && hda->need_i915_power) {
98d8fc6c 910 snd_hdac_display_power(azx_bus(chip), true);
926981ae 911 haswell_set_bclk(hda);
a07187c9 912 }
68e7fffc
TI		 913 if (chip->msi)
914 if (pci_enable_msi(pci) < 0)
915 chip->msi = 0;
916 if (azx_acquire_irq(chip, 1) < 0)
30b35399 917 return -EIO;
cb53c626 918 azx_init_pci(chip);
d804ad92 919
0a673521 920 hda_intel_init_chip(chip, true);
d804ad92 921
421a1252 922 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 923
924 trace_azx_resume(chip);
1da177e4
LT		 925 return 0;
926}
b8dfc462
ML		 927#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
928
641d334b 929#ifdef CONFIG_PM
b8dfc462
ML		 930static int azx_runtime_suspend(struct device *dev)
931{
932 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 933 struct azx *chip;
934 struct hda_intel *hda;
b8dfc462 935
2d9772ef
TI		 936 if (!card)
937 return 0;
938
939 chip = card->private_data;
940 hda = container_of(chip, struct hda_intel, chip);
1618e84a 941 if (chip->disabled || hda->init_failed)
246efa4a
DA		 942 return 0;
943
364aa716 944 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 945 return 0;
946
7d4f606c
WX		 947 /* enable controller wake up event */
948 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
949 STATESTS_INT_MASK);
950
b8dfc462 951 azx_stop_chip(chip);
873ce8ad 952 azx_enter_link_reset(chip);
b8dfc462 953 azx_clear_irq_pending(chip);
795614dd
ML		 954 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
955 && hda->need_i915_power)
98d8fc6c 956 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 957
785d8c4b 958 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 959 return 0;
960}
961
962static int azx_runtime_resume(struct device *dev)
963{
964 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 965 struct azx *chip;
966 struct hda_intel *hda;
98d8fc6c 967 struct hdac_bus *bus;
7d4f606c
WX		 968 struct hda_codec *codec;
969 int status;
b8dfc462 970
2d9772ef
TI		 971 if (!card)
972 return 0;
973
974 chip = card->private_data;
975 hda = container_of(chip, struct hda_intel, chip);
1618e84a 976 if (chip->disabled || hda->init_failed)
246efa4a
DA		 977 return 0;
978
364aa716 979 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 980 return 0;
981
033ea349
DH		 982 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
983 bus = azx_bus(chip);
984 if (hda->need_i915_power) {
985 snd_hdac_display_power(bus, true);
986 haswell_set_bclk(hda);
987 } else {
988 /* toggle codec wakeup bit for STATESTS read */
989 snd_hdac_set_codec_wakeup(bus, true);
990 snd_hdac_set_codec_wakeup(bus, false);
991 }
a07187c9 992 }
7d4f606c
WX		 993
994 /* Read STATESTS before controller reset */
995 status = azx_readw(chip, STATESTS);
996
b8dfc462 997 azx_init_pci(chip);
0a673521 998 hda_intel_init_chip(chip, true);
7d4f606c 999
a41d1224
TI		 1000 if (status) {
1001 list_for_each_codec(codec, &chip->bus)
7d4f606c 1002 if (status & (1 << codec->addr))
2f35c630
TI		 1003 schedule_delayed_work(&codec->jackpoll_work,
1004 codec->jackpoll_interval);
7d4f606c
WX		 1005 }
1006
1007 /* disable controller Wake Up event*/
1008 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1009 ~STATESTS_INT_MASK);
1010
785d8c4b 1011 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1012 return 0;
1013}
6eb827d2
TI		 1014
1015static int azx_runtime_idle(struct device *dev)
1016{
1017 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1018 struct azx *chip;
1019 struct hda_intel *hda;
1020
1021 if (!card)
1022 return 0;
6eb827d2 1023
2d9772ef
TI		 1024 chip = card->private_data;
1025 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1026 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1027 return 0;
1028
55ed9cd1 1029 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
a41d1224 1030 azx_bus(chip)->codec_powered)
6eb827d2
TI		 1031 return -EBUSY;
1032
1033 return 0;
1034}
1035
b8dfc462
ML		 1036static const struct dev_pm_ops azx_pm = {
1037 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1038 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1039};
1040
68cb2b55
TI		 1041#define AZX_PM_OPS &azx_pm
1042#else
68cb2b55 1043#define AZX_PM_OPS NULL
b8dfc462 1044#endif /* CONFIG_PM */
1da177e4
LT		 1045
1046
48c8b0eb 1047static int azx_probe_continue(struct azx *chip);
a82d51ed 1048
8393ec4a 1049#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1050static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1051
a82d51ed
TI		 1052static void azx_vs_set_state(struct pci_dev *pci,
1053 enum vga_switcheroo_state state)
1054{
1055 struct snd_card *card = pci_get_drvdata(pci);
1056 struct azx *chip = card->private_data;
9a34af4a 1057 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1058 bool disabled;
1059
9a34af4a
TI		 1060 wait_for_completion(&hda->probe_wait);
1061 if (hda->init_failed)
a82d51ed
TI		 1062 return;
1063
1064 disabled = (state == VGA_SWITCHEROO_OFF);
1065 if (chip->disabled == disabled)
1066 return;
1067
a41d1224 1068 if (!hda->probe_continued) {
a82d51ed
TI		 1069 chip->disabled = disabled;
1070 if (!disabled) {
4e76a883
TI		 1071 dev_info(chip->card->dev,
1072 "Start delayed initialization\n");
5c90680e 1073 if (azx_probe_continue(chip) < 0) {
4e76a883 1074 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1075 hda->init_failed = true;
a82d51ed
TI		 1076 }
1077 }
1078 } else {
4e76a883
TI		 1079 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1080 disabled ? "Disabling" : "Enabling");
a82d51ed 1081 if (disabled) {
8928756d
DR		 1082 pm_runtime_put_sync_suspend(card->dev);
1083 azx_suspend(card->dev);
246efa4a
DA		 1084 /* when we get suspended by vga switcheroo we end up in D3cold,
1085 * however we have no ACPI handle, so pci/acpi can't put us there,
1086 * put ourselves there */
1087 pci->current_state = PCI_D3cold;
a82d51ed 1088 chip->disabled = true;
a41d1224 1089 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1090 dev_warn(chip->card->dev,
1091 "Cannot lock devices!\n");
a82d51ed 1092 } else {
a41d1224 1093 snd_hda_unlock_devices(&chip->bus);
8928756d 1094 pm_runtime_get_noresume(card->dev);
a82d51ed 1095 chip->disabled = false;
8928756d 1096 azx_resume(card->dev);
a82d51ed
TI		 1097 }
1098 }
1099}
1100
1101static bool azx_vs_can_switch(struct pci_dev *pci)
1102{
1103 struct snd_card *card = pci_get_drvdata(pci);
1104 struct azx *chip = card->private_data;
9a34af4a 1105 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1106
9a34af4a
TI		 1107 wait_for_completion(&hda->probe_wait);
1108 if (hda->init_failed)
a82d51ed 1109 return false;
a41d1224 1110 if (chip->disabled || !hda->probe_continued)
a82d51ed 1111 return true;
a41d1224 1112 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1113 return false;
a41d1224 1114 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1115 return true;
1116}
1117
e23e7a14 1118static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1119{
9a34af4a 1120 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1121 struct pci_dev *p = get_bound_vga(chip->pci);
1122 if (p) {
4e76a883
TI		 1123 dev_info(chip->card->dev,
1124 "Handle VGA-switcheroo audio client\n");
9a34af4a 1125 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1126 pci_dev_put(p);
1127 }
1128}
1129
1130static const struct vga_switcheroo_client_ops azx_vs_ops = {
1131 .set_gpu_state = azx_vs_set_state,
1132 .can_switch = azx_vs_can_switch,
1133};
1134
e23e7a14 1135static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1136{
9a34af4a 1137 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1138 int err;
1139
9a34af4a 1140 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1141 return 0;
1142 /* FIXME: currently only handling DIS controller
1143 * is there any machine with two switchable HDMI audio controllers?
1144 */
128960a9 1145 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed 1146 VGA_SWITCHEROO_DIS,
a41d1224 1147 hda->probe_continued);
128960a9
TI		 1148 if (err < 0)
1149 return err;
9a34af4a 1150 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1151
1152 /* register as an optimus hdmi audio power domain */
8928756d 1153 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1154 &hda->hdmi_pm_domain);
128960a9 1155 return 0;
a82d51ed
TI		 1156}
1157#else
1158#define init_vga_switcheroo(chip) /* NOP */
1159#define register_vga_switcheroo(chip) 0
8393ec4a 1160#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1161#endif /* SUPPORT_VGA_SWITCHER */
1162
1da177e4
LT		 1163/*
1164 * destructor
1165 */
a98f90fd 1166static int azx_free(struct azx *chip)
1da177e4 1167{
c67e2228 1168 struct pci_dev *pci = chip->pci;
a07187c9 1169 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1170 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1171
364aa716 1172 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1173 pm_runtime_get_noresume(&pci->dev);
1174
65fcd41d
TI		 1175 azx_del_card_list(chip);
1176
9a34af4a
TI		 1177 hda->init_failed = 1; /* to be sure */
1178 complete_all(&hda->probe_wait);
f4c482a4 1179
9a34af4a 1180 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1181 if (chip->disabled && hda->probe_continued)
1182 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1183 if (hda->vga_switcheroo_registered)
128960a9 1184 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1185 }
1186
a41d1224 1187 if (bus->chip_init) {
9ad593f6 1188 azx_clear_irq_pending(chip);
7833c3f8 1189 azx_stop_all_streams(chip);
cb53c626 1190 azx_stop_chip(chip);
1da177e4
LT		 1191 }
1192
a41d1224
TI		 1193 if (bus->irq >= 0)
1194 free_irq(bus->irq, (void*)chip);
68e7fffc 1195 if (chip->msi)
30b35399 1196 pci_disable_msi(chip->pci);
a41d1224 1197 iounmap(bus->remap_addr);
1da177e4 1198
67908994 1199 azx_free_stream_pages(chip);
a41d1224
TI		 1200 azx_free_streams(chip);
1201 snd_hdac_bus_exit(bus);
1202
a82d51ed
TI		 1203 if (chip->region_requested)
1204 pci_release_regions(chip->pci);
a41d1224 1205
1da177e4 1206 pci_disable_device(chip->pci);
4918cdab 1207#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1208 release_firmware(chip->fw);
4918cdab 1209#endif
98d8fc6c 1210
99a2008d 1211 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1212 if (hda->need_i915_power)
98d8fc6c
ML		 1213 snd_hdac_display_power(bus, false);
1214 snd_hdac_i915_exit(bus);
99a2008d 1215 }
a07187c9 1216 kfree(hda);
1da177e4
LT		 1217
1218 return 0;
1219}
1220
a41d1224
TI		 1221static int azx_dev_disconnect(struct snd_device *device)
1222{
1223 struct azx *chip = device->device_data;
1224
1225 chip->bus.shutdown = 1;
1226 return 0;
1227}
1228
a98f90fd 1229static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1230{
1231 return azx_free(device->device_data);
1232}
1233
8393ec4a 1234#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1235/*
1236 * Check of disabled HDMI controller by vga-switcheroo
1237 */
e23e7a14 1238static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1239{
1240 struct pci_dev *p;
1241
1242 /* check only discrete GPU */
1243 switch (pci->vendor) {
1244 case PCI_VENDOR_ID_ATI:
1245 case PCI_VENDOR_ID_AMD:
1246 case PCI_VENDOR_ID_NVIDIA:
1247 if (pci->devfn == 1) {
1248 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1249 pci->bus->number, 0);
1250 if (p) {
1251 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1252 return p;
1253 pci_dev_put(p);
1254 }
1255 }
1256 break;
1257 }
1258 return NULL;
1259}
1260
e23e7a14 1261static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1262{
1263 bool vga_inactive = false;
1264 struct pci_dev *p = get_bound_vga(pci);
1265
1266 if (p) {
12b78a7f 1267 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1268 vga_inactive = true;
1269 pci_dev_put(p);
1270 }
1271 return vga_inactive;
1272}
8393ec4a 1273#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1274
3372a153
TI		 1275/*
1276 * white/black-listing for position_fix
1277 */
e23e7a14 1278static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1279 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1280 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1281 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1282 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1283 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1284 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1285 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1286 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1287 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1288 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1289 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1290 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1291 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1292 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1293 {}
1294};
1295
e23e7a14 1296static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1297{
1298 const struct snd_pci_quirk *q;
1299
c673ba1c 1300 switch (fix) {
1dac6695 1301 case POS_FIX_AUTO:
c673ba1c
TI		 1302 case POS_FIX_LPIB:
1303 case POS_FIX_POSBUF:
4cb36310 1304 case POS_FIX_VIACOMBO:
a6f2fd55 1305 case POS_FIX_COMBO:
c673ba1c
TI		 1306 return fix;
1307 }
1308
c673ba1c
TI		 1309 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1310 if (q) {
4e76a883
TI		 1311 dev_info(chip->card->dev,
1312 "position_fix set to %d for device %04x:%04x\n",
1313 q->value, q->subvendor, q->subdevice);
c673ba1c 1314 return q->value;
3372a153 1315 }
bdd9ef24
DH		 1316
1317 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1318 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1319 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1320 return POS_FIX_VIACOMBO;
9477c58e
TI		 1321 }
1322 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1323 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1324 return POS_FIX_LPIB;
bdd9ef24 1325 }
c673ba1c 1326 return POS_FIX_AUTO;
3372a153
TI		 1327}
1328
b6050ef6
TI		 1329static void assign_position_fix(struct azx *chip, int fix)
1330{
1331 static azx_get_pos_callback_t callbacks[] = {
1332 [POS_FIX_AUTO] = NULL,
1333 [POS_FIX_LPIB] = azx_get_pos_lpib,
1334 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1335 [POS_FIX_VIACOMBO] = azx_via_get_position,
1336 [POS_FIX_COMBO] = azx_get_pos_lpib,
1337 };
1338
1339 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1340
1341 /* combo mode uses LPIB only for playback */
1342 if (fix == POS_FIX_COMBO)
1343 chip->get_position[1] = NULL;
1344
1345 if (fix == POS_FIX_POSBUF &&
1346 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1347 chip->get_delay[0] = chip->get_delay[1] =
1348 azx_get_delay_from_lpib;
1349 }
1350
1351}
1352
669ba27a
TI		 1353/*
1354 * black-lists for probe_mask
1355 */
e23e7a14 1356static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1357 /* Thinkpad often breaks the controller communication when accessing
1358 * to the non-working (or non-existing) modem codec slot.
1359 */
1360 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1361 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1362 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1363 /* broken BIOS */
1364 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1365 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1366 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1367 /* forced codec slots */
93574844 1368 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1369 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1370 /* WinFast VP200 H (Teradici) user reported broken communication */
1371 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1372 {}
1373};
1374
f1eaaeec
TI		 1375#define AZX_FORCE_CODEC_MASK 0x100
1376
e23e7a14 1377static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1378{
1379 const struct snd_pci_quirk *q;
1380
f1eaaeec
TI		 1381 chip->codec_probe_mask = probe_mask[dev];
1382 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1383 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1384 if (q) {
4e76a883
TI		 1385 dev_info(chip->card->dev,
1386 "probe_mask set to 0x%x for device %04x:%04x\n",
1387 q->value, q->subvendor, q->subdevice);
f1eaaeec 1388 chip->codec_probe_mask = q->value;
669ba27a
TI		 1389 }
1390 }
f1eaaeec
TI		 1391
1392 /* check forced option */
1393 if (chip->codec_probe_mask != -1 &&
1394 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1395 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1396 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1397 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1398 }
669ba27a
TI		 1399}
1400
4d8e22e0 1401/*
71623855 1402 * white/black-list for enable_msi
4d8e22e0 1403 */
e23e7a14 1404static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1405 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1406 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1407 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1408 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1409 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1410 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1411 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1412 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1413 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1414 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1415 {}
1416};
1417
e23e7a14 1418static void check_msi(struct azx *chip)
4d8e22e0
TI		 1419{
1420 const struct snd_pci_quirk *q;
1421
71623855
TI		 1422 if (enable_msi >= 0) {
1423 chip->msi = !!enable_msi;
4d8e22e0 1424 return;
71623855
TI		 1425 }
1426 chip->msi = 1; /* enable MSI as default */
1427 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1428 if (q) {
4e76a883
TI		 1429 dev_info(chip->card->dev,
1430 "msi for device %04x:%04x set to %d\n",
1431 q->subvendor, q->subdevice, q->value);
4d8e22e0 1432 chip->msi = q->value;
80c43ed7
TI		 1433 return;
1434 }
1435
1436 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1437 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1438 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1439 chip->msi = 0;
4d8e22e0
TI		 1440 }
1441}
1442
a1585d76 1443/* check the snoop mode availability */
e23e7a14 1444static void azx_check_snoop_available(struct azx *chip)
a1585d76 1445{
7c732015 1446 int snoop = hda_snoop;
a1585d76 1447
7c732015
TI		 1448 if (snoop >= 0) {
1449 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1450 snoop ? "snoop" : "non-snoop");
1451 chip->snoop = snoop;
1452 return;
1453 }
1454
1455 snoop = true;
37e661ee
TI		 1456 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1457 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1458 /* force to non-snoop mode for a new VIA controller
1459 * when BIOS is set
1460 */
7c732015
TI		 1461 u8 val;
1462 pci_read_config_byte(chip->pci, 0x42, &val);
1463 if (!(val & 0x80) && chip->pci->revision == 0x30)
1464 snoop = false;
a1585d76
TI		 1465 }
1466
37e661ee
TI		 1467 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1468 snoop = false;
1469
7c732015
TI		 1470 chip->snoop = snoop;
1471 if (!snoop)
1472 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1473}
669ba27a 1474
99a2008d
WX		 1475static void azx_probe_work(struct work_struct *work)
1476{
9a34af4a
TI		 1477 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1478 azx_probe_continue(&hda->chip);
99a2008d 1479}
99a2008d 1480
1da177e4
LT		 1481/*
1482 * constructor
1483 */
a43ff5ba
TI		 1484static const struct hdac_io_ops pci_hda_io_ops;
1485static const struct hda_controller_ops pci_hda_ops;
1486
e23e7a14
BP		 1487static int azx_create(struct snd_card *card, struct pci_dev *pci,
1488 int dev, unsigned int driver_caps,
1489 struct azx **rchip)
1da177e4 1490{
a98f90fd 1491 static struct snd_device_ops ops = {
a41d1224 1492 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1493 .dev_free = azx_dev_free,
1494 };
a07187c9 1495 struct hda_intel *hda;
a82d51ed
TI		 1496 struct azx *chip;
1497 int err;
1da177e4
LT		 1498
1499 *rchip = NULL;
bcd72003 1500
927fc866
PM		 1501 err = pci_enable_device(pci);
1502 if (err < 0)
1da177e4
LT		 1503 return err;
1504
a07187c9
ML		 1505 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1506 if (!hda) {
1da177e4
LT		 1507 pci_disable_device(pci);
1508 return -ENOMEM;
1509 }
1510
a07187c9 1511 chip = &hda->chip;
62932df8 1512 mutex_init(&chip->open_mutex);
1da177e4
LT		 1513 chip->card = card;
1514 chip->pci = pci;
a43ff5ba 1515 chip->ops = &pci_hda_ops;
9477c58e
TI		 1516 chip->driver_caps = driver_caps;
1517 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1518 check_msi(chip);
555e219f 1519 chip->dev_index = dev;
749ee287 1520 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1521 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1522 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1523 INIT_LIST_HEAD(&hda->list);
a82d51ed 1524 init_vga_switcheroo(chip);
9a34af4a 1525 init_completion(&hda->probe_wait);
1da177e4 1526
b6050ef6 1527 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1528
5aba4f8e 1529 check_probe_mask(chip, dev);
3372a153 1530
27346166 1531 chip->single_cmd = single_cmd;
a1585d76 1532 azx_check_snoop_available(chip);
c74db86b 1533
5c0d7bc1
TI		 1534 if (bdl_pos_adj[dev] < 0) {
1535 switch (chip->driver_type) {
0c6341ac 1536 case AZX_DRIVER_ICH:
32679f95 1537 case AZX_DRIVER_PCH:
0c6341ac 1538 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1539 break;
1540 default:
0c6341ac 1541 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1542 break;
1543 }
1544 }
9cdc0115 1545 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1546
a41d1224
TI		 1547 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1548 if (err < 0) {
1549 kfree(hda);
1550 pci_disable_device(pci);
1551 return err;
1552 }
1553
a82d51ed
TI		 1554 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1555 if (err < 0) {
4e76a883 1556 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1557 azx_free(chip);
1558 return err;
1559 }
1560
99a2008d 1561 /* continue probing in work context as may trigger request module */
9a34af4a 1562 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1563
a82d51ed 1564 *rchip = chip;
99a2008d 1565
a82d51ed
TI		 1566 return 0;
1567}
1568
48c8b0eb 1569static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1570{
1571 int dev = chip->dev_index;
1572 struct pci_dev *pci = chip->pci;
1573 struct snd_card *card = chip->card;
a41d1224 1574 struct hdac_bus *bus = azx_bus(chip);
67908994 1575 int err;
a82d51ed 1576 unsigned short gcap;
413cbf46 1577 unsigned int dma_bits = 64;
a82d51ed 1578
07e4ca50
TI		 1579#if BITS_PER_LONG != 64
1580 /* Fix up base address on ULI M5461 */
1581 if (chip->driver_type == AZX_DRIVER_ULI) {
1582 u16 tmp3;
1583 pci_read_config_word(pci, 0x40, &tmp3);
1584 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1585 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1586 }
1587#endif
1588
927fc866 1589 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1590 if (err < 0)
1da177e4 1591 return err;
a82d51ed 1592 chip->region_requested = 1;
1da177e4 1593
a41d1224
TI		 1594 bus->addr = pci_resource_start(pci, 0);
1595 bus->remap_addr = pci_ioremap_bar(pci, 0);
1596 if (bus->remap_addr == NULL) {
4e76a883 1597 dev_err(card->dev, "ioremap error\n");
a82d51ed 1598 return -ENXIO;
1da177e4
LT		 1599 }
1600
db79afa1
BH		 1601 if (chip->msi) {
1602 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1603 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1604 pci->no_64bit_msi = true;
1605 }
68e7fffc
TI		 1606 if (pci_enable_msi(pci) < 0)
1607 chip->msi = 0;
db79afa1 1608 }
7376d013 1609
a82d51ed
TI		 1610 if (azx_acquire_irq(chip, 0) < 0)
1611 return -EBUSY;
1da177e4
LT		 1612
1613 pci_set_master(pci);
a41d1224 1614 synchronize_irq(bus->irq);
1da177e4 1615
bcd72003 1616 gcap = azx_readw(chip, GCAP);
4e76a883 1617 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1618
413cbf46
TI		 1619 /* AMD devices support 40 or 48bit DMA, take the safe one */
1620 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1621 dma_bits = 40;
1622
dc4c2e6b 1623 /* disable SB600 64bit support for safety */
9477c58e 1624 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1625 struct pci_dev *p_smbus;
413cbf46 1626 dma_bits = 40;
dc4c2e6b
AB		 1627 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1628 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1629 NULL);
1630 if (p_smbus) {
1631 if (p_smbus->revision < 0x30)
fb1d8ac2 1632 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1633 pci_dev_put(p_smbus);
1634 }
1635 }
09240cf4 1636
9477c58e
TI		 1637 /* disable 64bit DMA address on some devices */
1638 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1639 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1640 gcap &= ~AZX_GCAP_64OK;
9477c58e 1641 }
396087ea 1642
2ae66c26 1643 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1644 if (align_buffer_size >= 0)
1645 chip->align_buffer_size = !!align_buffer_size;
1646 else {
103884a3 1647 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1648 chip->align_buffer_size = 0;
7bfe059e
TI		 1649 else
1650 chip->align_buffer_size = 1;
1651 }
2ae66c26 1652
cf7aaca8 1653 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1654 if (!(gcap & AZX_GCAP_64OK))
1655 dma_bits = 32;
412b979c
QL		 1656 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1657 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1658 } else {
412b979c
QL		 1659 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1660 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1661 }
cf7aaca8 1662
8b6ed8e7
TI		 1663 /* read number of streams from GCAP register instead of using
1664 * hardcoded value
1665 */
1666 chip->capture_streams = (gcap >> 8) & 0x0f;
1667 chip->playback_streams = (gcap >> 12) & 0x0f;
1668 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1669 /* gcap didn't give any info, switching to old method */
1670
1671 switch (chip->driver_type) {
1672 case AZX_DRIVER_ULI:
1673 chip->playback_streams = ULI_NUM_PLAYBACK;
1674 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1675 break;
1676 case AZX_DRIVER_ATIHDMI:
1815b34a 1677 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1678 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1679 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1680 break;
c4da29ca 1681 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1682 default:
1683 chip->playback_streams = ICH6_NUM_PLAYBACK;
1684 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1685 break;
1686 }
07e4ca50 1687 }
8b6ed8e7
TI		 1688 chip->capture_index_offset = 0;
1689 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1690 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1691
a41d1224
TI		 1692 /* initialize streams */
1693 err = azx_init_streams(chip);
81740861 1694 if (err < 0)
a82d51ed 1695 return err;
1da177e4 1696
a41d1224
TI		 1697 err = azx_alloc_stream_pages(chip);
1698 if (err < 0)
1699 return err;
1da177e4
LT		 1700
1701 /* initialize chip */
cb53c626 1702 azx_init_pci(chip);
e4d9e513 1703
926981ae
ID		 1704 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1705 struct hda_intel *hda;
1706
1707 hda = container_of(chip, struct hda_intel, chip);
1708 haswell_set_bclk(hda);
1709 }
e4d9e513 1710
0a673521 1711 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1712
1713 /* codec detection */
a41d1224 1714 if (!azx_bus(chip)->codec_mask) {
4e76a883 1715 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1716 return -ENODEV;
1da177e4
LT		 1717 }
1718
07e4ca50 1719 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1720 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1721 sizeof(card->shortname));
1722 snprintf(card->longname, sizeof(card->longname),
1723 "%s at 0x%lx irq %i",
a41d1224 1724 card->shortname, bus->addr, bus->irq);
07e4ca50 1725
1da177e4 1726 return 0;
1da177e4
LT		 1727}
1728
97c6a3d1 1729#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1730/* callback from request_firmware_nowait() */
1731static void azx_firmware_cb(const struct firmware *fw, void *context)
1732{
1733 struct snd_card *card = context;
1734 struct azx *chip = card->private_data;
1735 struct pci_dev *pci = chip->pci;
1736
1737 if (!fw) {
4e76a883 1738 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1739 goto error;
1740 }
1741
1742 chip->fw = fw;
1743 if (!chip->disabled) {
1744 /* continue probing */
1745 if (azx_probe_continue(chip))
1746 goto error;
1747 }
1748 return; /* OK */
1749
1750 error:
1751 snd_card_free(card);
1752 pci_set_drvdata(pci, NULL);
1753}
97c6a3d1 1754#endif
5cb543db 1755
40830813
DR		 1756/*
1757 * HDA controller ops.
1758 */
1759
1760/* PCI register access. */
db291e36 1761static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1762{
1763 writel(value, addr);
1764}
1765
db291e36 1766static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1767{
1768 return readl(addr);
1769}
1770
db291e36 1771static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1772{
1773 writew(value, addr);
1774}
1775
db291e36 1776static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1777{
1778 return readw(addr);
1779}
1780
db291e36 1781static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1782{
1783 writeb(value, addr);
1784}
1785
db291e36 1786static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1787{
1788 return readb(addr);
1789}
1790
f46ea609
DR		 1791static int disable_msi_reset_irq(struct azx *chip)
1792{
a41d1224 1793 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1794 int err;
1795
a41d1224
TI		 1796 free_irq(bus->irq, chip);
1797 bus->irq = -1;
f46ea609
DR		 1798 pci_disable_msi(chip->pci);
1799 chip->msi = 0;
1800 err = azx_acquire_irq(chip, 1);
1801 if (err < 0)
1802 return err;
1803
1804 return 0;
1805}
1806
b419b35b 1807/* DMA page allocation helpers. */
a43ff5ba 1808static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1809 int type,
1810 size_t size,
1811 struct snd_dma_buffer *buf)
1812{
a41d1224 1813 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1814 int err;
1815
1816 err = snd_dma_alloc_pages(type,
a43ff5ba 1817 bus->dev,
b419b35b
DR		 1818 size, buf);
1819 if (err < 0)
1820 return err;
1821 mark_pages_wc(chip, buf, true);
1822 return 0;
1823}
1824
a43ff5ba 1825static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1826{
a41d1224 1827 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1828
b419b35b
DR		 1829 mark_pages_wc(chip, buf, false);
1830 snd_dma_free_pages(buf);
1831}
1832
1833static int substream_alloc_pages(struct azx *chip,
1834 struct snd_pcm_substream *substream,
1835 size_t size)
1836{
1837 struct azx_dev *azx_dev = get_azx_dev(substream);
1838 int ret;
1839
1840 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1841 ret = snd_pcm_lib_malloc_pages(substream, size);
1842 if (ret < 0)
1843 return ret;
1844 mark_runtime_wc(chip, azx_dev, substream, true);
1845 return 0;
1846}
1847
1848static int substream_free_pages(struct azx *chip,
1849 struct snd_pcm_substream *substream)
1850{
1851 struct azx_dev *azx_dev = get_azx_dev(substream);
1852 mark_runtime_wc(chip, azx_dev, substream, false);
1853 return snd_pcm_lib_free_pages(substream);
1854}
1855
8769b278
DR		 1856static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1857 struct vm_area_struct *area)
1858{
1859#ifdef CONFIG_X86
1860 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1861 struct azx *chip = apcm->chip;
3b70bdba 1862 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1863 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1864#endif
1865}
1866
a43ff5ba 1867static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1868 .reg_writel = pci_azx_writel,
1869 .reg_readl = pci_azx_readl,
1870 .reg_writew = pci_azx_writew,
1871 .reg_readw = pci_azx_readw,
1872 .reg_writeb = pci_azx_writeb,
1873 .reg_readb = pci_azx_readb,
b419b35b
DR		 1874 .dma_alloc_pages = dma_alloc_pages,
1875 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1876};
1877
1878static const struct hda_controller_ops pci_hda_ops = {
1879 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1880 .substream_alloc_pages = substream_alloc_pages,
1881 .substream_free_pages = substream_free_pages,
8769b278 1882 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1883 .position_check = azx_position_check,
17eccb27 1884 .link_power = azx_intel_link_power,
40830813
DR		 1885};
1886
e23e7a14
BP		 1887static int azx_probe(struct pci_dev *pci,
1888 const struct pci_device_id *pci_id)
1da177e4 1889{
5aba4f8e 1890 static int dev;
a98f90fd 1891 struct snd_card *card;
9a34af4a 1892 struct hda_intel *hda;
a98f90fd 1893 struct azx *chip;
aad730d0 1894 bool schedule_probe;
927fc866 1895 int err;
1da177e4 1896
5aba4f8e
TI		 1897 if (dev >= SNDRV_CARDS)
1898 return -ENODEV;
1899 if (!enable[dev]) {
1900 dev++;
1901 return -ENOENT;
1902 }
1903
60c5772b
TI		 1904 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1905 0, &card);
e58de7ba 1906 if (err < 0) {
4e76a883 1907 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1908 return err;
1da177e4
LT		 1909 }
1910
a43ff5ba 1911 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1912 if (err < 0)
1913 goto out_free;
421a1252 1914 card->private_data = chip;
9a34af4a 1915 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1916
1917 pci_set_drvdata(pci, card);
1918
1919 err = register_vga_switcheroo(chip);
1920 if (err < 0) {
4e76a883 1921 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1922 goto out_free;
1923 }
1924
1925 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1926 dev_info(card->dev, "VGA controller is disabled\n");
1927 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1928 chip->disabled = true;
1929 }
1930
aad730d0 1931 schedule_probe = !chip->disabled;
1da177e4 1932
4918cdab
TI		 1933#ifdef CONFIG_SND_HDA_PATCH_LOADER
1934 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1935 dev_info(card->dev, "Applying patch firmware '%s'\n",
1936 patch[dev]);
5cb543db
TI		 1937 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1938 &pci->dev, GFP_KERNEL, card,
1939 azx_firmware_cb);
4918cdab
TI		 1940 if (err < 0)
1941 goto out_free;
aad730d0 1942 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1943 }
1944#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1945
aad730d0
TI		 1946#ifndef CONFIG_SND_HDA_I915
1947 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1948 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1949#endif
99a2008d 1950
aad730d0 1951 if (schedule_probe)
9a34af4a 1952 schedule_work(&hda->probe_work);
a82d51ed 1953
a82d51ed 1954 dev++;
88d071fc 1955 if (chip->disabled)
9a34af4a 1956 complete_all(&hda->probe_wait);
a82d51ed
TI		 1957 return 0;
1958
1959out_free:
1960 snd_card_free(card);
1961 return err;
1962}
1963
e62a42ae
DR		 1964/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1965static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1966 [AZX_DRIVER_NVIDIA] = 8,
1967 [AZX_DRIVER_TERA] = 1,
1968};
1969
48c8b0eb 1970static int azx_probe_continue(struct azx *chip)
a82d51ed 1971{
9a34af4a 1972 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 1973 struct hdac_bus *bus = azx_bus(chip);
c67e2228 1974 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1975 int dev = chip->dev_index;
1976 int err;
1977
a41d1224 1978 hda->probe_continued = 1;
795614dd
ML		 1979
1980 /* Request display power well for the HDA controller or codec. For
1981 * Haswell/Broadwell, both the display HDA controller and codec need
1982 * this power. For other platforms, like Baytrail/Braswell, only the
1983 * display codec needs the power and it can be released after probe.
1984 */
99a2008d 1985 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 1986 /* HSW/BDW controllers need this power */
1987 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 1988 hda->need_i915_power = 1;
1989
98d8fc6c 1990 err = snd_hdac_i915_init(bus);
535115b5
TI		 1991 if (err < 0) {
1992 /* if the controller is bound only with HDMI/DP
1993 * (for HSW and BDW), we need to abort the probe;
1994 * for other chips, still continue probing as other
1995 * codecs can be on the same link.
1996 */
1997 if (CONTROLLER_IN_GPU(pci))
1998 goto out_free;
1999 else
2000 goto skip_i915;
2001 }
795614dd 2002
98d8fc6c 2003 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2004 if (err < 0) {
2005 dev_err(chip->card->dev,
2006 "Cannot turn on display power on i915\n");
795614dd 2007 goto i915_power_fail;
74b0c2d7 2008 }
99a2008d
WX		 2009 }
2010
bf06848b 2011 skip_i915:
5c90680e
TI		 2012 err = azx_first_init(chip);
2013 if (err < 0)
2014 goto out_free;
2015
2dca0bba
JK		 2016#ifdef CONFIG_SND_HDA_INPUT_BEEP
2017 chip->beep_mode = beep_mode[dev];
2018#endif
2019
1da177e4 2020 /* create codec instances */
96d2bd6e 2021 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2022 if (err < 0)
2023 goto out_free;
96d2bd6e 2024
4ea6fbc8 2025#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2026 if (chip->fw) {
a41d1224 2027 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2028 chip->fw->data);
4ea6fbc8
TI		 2029 if (err < 0)
2030 goto out_free;
e39ae856 2031#ifndef CONFIG_PM
4918cdab
TI		 2032 release_firmware(chip->fw); /* no longer needed */
2033 chip->fw = NULL;
e39ae856 2034#endif
4ea6fbc8
TI		 2035 }
2036#endif
10e77dda 2037 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2038 err = azx_codec_configure(chip);
2039 if (err < 0)
2040 goto out_free;
2041 }
1da177e4 2042
a82d51ed 2043 err = snd_card_register(chip->card);
41dda0fd
WF		 2044 if (err < 0)
2045 goto out_free;
1da177e4 2046
cb53c626 2047 chip->running = 1;
65fcd41d 2048 azx_add_card_list(chip);
a41d1224 2049 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2050 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 2051 pm_runtime_put_noidle(&pci->dev);
1da177e4 2052
41dda0fd 2053out_free:
795614dd
ML		 2054 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2055 && !hda->need_i915_power)
98d8fc6c 2056 snd_hdac_display_power(bus, false);
795614dd
ML		 2057
2058i915_power_fail:
88d071fc 2059 if (err < 0)
9a34af4a
TI		 2060 hda->init_failed = 1;
2061 complete_all(&hda->probe_wait);
41dda0fd 2062 return err;
1da177e4
LT		 2063}
2064
e23e7a14 2065static void azx_remove(struct pci_dev *pci)
1da177e4 2066{
9121947d 2067 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 2068
9121947d
TI		 2069 if (card)
2070 snd_card_free(card);
1da177e4
LT		 2071}
2072
b2a0bafa
TI		 2073static void azx_shutdown(struct pci_dev *pci)
2074{
2075 struct snd_card *card = pci_get_drvdata(pci);
2076 struct azx *chip;
2077
2078 if (!card)
2079 return;
2080 chip = card->private_data;
2081 if (chip && chip->running)
2082 azx_stop_chip(chip);
2083}
2084
1da177e4 2085/* PCI IDs */
6f51f6cf 2086static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2087 /* CPT */
9477c58e 2088 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2089 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2090 /* PBG */
9477c58e 2091 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2092 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2093 /* Panther Point */
9477c58e 2094 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2095 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2096 /* Lynx Point */
2097 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2098 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2099 /* 9 Series */
2100 { PCI_DEVICE(0x8086, 0x8ca0),
2101 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2102 /* Wellsburg */
2103 { PCI_DEVICE(0x8086, 0x8d20),
2104 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2105 { PCI_DEVICE(0x8086, 0x8d21),
2106 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2107 /* Lynx Point-LP */
2108 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2109 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2110 /* Lynx Point-LP */
2111 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2112 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2113 /* Wildcat Point-LP */
2114 { PCI_DEVICE(0x8086, 0x9ca0),
2115 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2116 /* Sunrise Point */
2117 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2118 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2119 /* Sunrise Point-LP */
2120 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2121 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 2122 /* Haswell */
4a7c516b 2123 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2124 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2125 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2126 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2127 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2128 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2129 /* Broadwell */
2130 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2131 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2132 /* 5 Series/3400 */
2133 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2134 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2135 /* Poulsbo */
9477c58e 2136 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2137 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2138 /* Oaktrail */
09904b95 2139 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2140 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2141 /* BayTrail */
2142 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2143 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2144 /* Braswell */
2145 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2146 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2147 /* ICH6 */
8b0bd226 2148 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2149 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2150 /* ICH7 */
8b0bd226 2151 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2152 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2153 /* ESB2 */
8b0bd226 2154 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2155 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2156 /* ICH8 */
8b0bd226 2157 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2158 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2159 /* ICH9 */
8b0bd226 2160 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2161 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2162 /* ICH9 */
8b0bd226 2163 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2164 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2165 /* ICH10 */
8b0bd226 2166 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2167 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2168 /* ICH10 */
8b0bd226 2169 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2170 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2171 /* Generic Intel */
2172 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2173 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2174 .class_mask = 0xffffff,
103884a3 2175 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2176 /* ATI SB 450/600/700/800/900 */
2177 { PCI_DEVICE(0x1002, 0x437b),
2178 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2179 { PCI_DEVICE(0x1002, 0x4383),
2180 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2181 /* AMD Hudson */
2182 { PCI_DEVICE(0x1022, 0x780d),
2183 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2184 /* ATI HDMI */
650474fb
AD		 2185 { PCI_DEVICE(0x1002, 0x1308),
2186 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2187 { PCI_DEVICE(0x1002, 0x793b),
2188 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2189 { PCI_DEVICE(0x1002, 0x7919),
2190 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2191 { PCI_DEVICE(0x1002, 0x960f),
2192 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2193 { PCI_DEVICE(0x1002, 0x970f),
2194 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2195 { PCI_DEVICE(0x1002, 0x9840),
2196 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2197 { PCI_DEVICE(0x1002, 0xaa00),
2198 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2199 { PCI_DEVICE(0x1002, 0xaa08),
2200 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2201 { PCI_DEVICE(0x1002, 0xaa10),
2202 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2203 { PCI_DEVICE(0x1002, 0xaa18),
2204 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2205 { PCI_DEVICE(0x1002, 0xaa20),
2206 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207 { PCI_DEVICE(0x1002, 0xaa28),
2208 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209 { PCI_DEVICE(0x1002, 0xaa30),
2210 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2211 { PCI_DEVICE(0x1002, 0xaa38),
2212 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213 { PCI_DEVICE(0x1002, 0xaa40),
2214 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215 { PCI_DEVICE(0x1002, 0xaa48),
2216 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2217 { PCI_DEVICE(0x1002, 0xaa50),
2218 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219 { PCI_DEVICE(0x1002, 0xaa58),
2220 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { PCI_DEVICE(0x1002, 0xaa60),
2222 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223 { PCI_DEVICE(0x1002, 0xaa68),
2224 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225 { PCI_DEVICE(0x1002, 0xaa80),
2226 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227 { PCI_DEVICE(0x1002, 0xaa88),
2228 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229 { PCI_DEVICE(0x1002, 0xaa90),
2230 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231 { PCI_DEVICE(0x1002, 0xaa98),
2232 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2233 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2234 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2235 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2236 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2237 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2238 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2239 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2240 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2241 { PCI_DEVICE(0x1002, 0xaac8),
2242 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2243 /* VIA VT8251/VT8237A */
9477c58e
TI		 2244 { PCI_DEVICE(0x1106, 0x3288),
2245 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2246 /* VIA GFX VT7122/VX900 */
2247 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2248 /* VIA GFX VT6122/VX11 */
2249 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2250 /* SIS966 */
2251 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2252 /* ULI M5461 */
2253 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2254 /* NVIDIA MCP */
0c2fd1bf
TI		 2255 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2256 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2257 .class_mask = 0xffffff,
9477c58e 2258 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2259 /* Teradici */
9477c58e
TI		 2260 { PCI_DEVICE(0x6549, 0x1200),
2261 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2262 { PCI_DEVICE(0x6549, 0x2200),
2263 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2264 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2265 /* CTHDA chips */
2266 { PCI_DEVICE(0x1102, 0x0010),
2267 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2268 { PCI_DEVICE(0x1102, 0x0012),
2269 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2270#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2271 /* the following entry conflicts with snd-ctxfi driver,
2272 * as ctxfi driver mutates from HD-audio to native mode with
2273 * a special command sequence.
2274 */
4e01f54b
TI		 2275 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2276 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2277 .class_mask = 0xffffff,
9477c58e 2278 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2279 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2280#else
2281 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2282 { PCI_DEVICE(0x1102, 0x0009),
2283 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2284 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2285#endif
c563f473
TI		 2286 /* CM8888 */
2287 { PCI_DEVICE(0x13f6, 0x5011),
2288 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2289 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2290 /* Vortex86MX */
2291 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2292 /* VMware HDAudio */
2293 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2294 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2295 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2296 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2297 .class_mask = 0xffffff,
9477c58e 2298 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2299 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2300 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2301 .class_mask = 0xffffff,
9477c58e 2302 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2303 { 0, }
2304};
2305MODULE_DEVICE_TABLE(pci, azx_ids);
2306
2307/* pci_driver definition */
e9f66d9b 2308static struct pci_driver azx_driver = {
3733e424 2309 .name = KBUILD_MODNAME,
1da177e4
LT		 2310 .id_table = azx_ids,
2311 .probe = azx_probe,
e23e7a14 2312 .remove = azx_remove,
b2a0bafa 2313 .shutdown = azx_shutdown,
68cb2b55
TI		 2314 .driver = {
2315 .pm = AZX_PM_OPS,
2316 },
1da177e4
LT		 2317};
2318
e9f66d9b 2319module_pci_driver(azx_driver);
Linux kernel - Deliverables
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