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ALSA: hda - jack poll once if jackpoll_interval==0
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
1da177e4
LT		 66
67
5aba4f8e
TI		 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 70static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 71static char *model[SNDRV_CARDS];
1dac6695 72static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 73static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 74static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 75static int probe_only[SNDRV_CARDS];
26a6cb6c 76static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 77static bool single_cmd;
71623855 78static int enable_msi = -1;
4ea6fbc8
TI		 79#ifdef CONFIG_SND_HDA_PATCH_LOADER
80static char *patch[SNDRV_CARDS];
81#endif
2dca0bba 82#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 83static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85#endif
1da177e4 86
5aba4f8e 87module_param_array(index, int, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 89module_param_array(id, charp, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 91module_param_array(enable, bool, NULL, 0444);
92MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93module_param_array(model, charp, NULL, 0444);
1da177e4 94MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 95module_param_array(position_fix, int, NULL, 0444);
4cb36310 96MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 98module_param_array(bdl_pos_adj, int, NULL, 0644);
99MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 100module_param_array(probe_mask, int, NULL, 0444);
606ad75f 101MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 102module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 103MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 104module_param_array(jackpoll_ms, int, NULL, 0444);
105MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 106module_param(single_cmd, bool, 0444);
d01ce99f
TI		 107MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
ac9ef6cf 109module_param(enable_msi, bint, 0444);
134a11f0 110MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 111#ifdef CONFIG_SND_HDA_PATCH_LOADER
112module_param_array(patch, charp, NULL, 0444);
113MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114#endif
2dca0bba 115#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 116module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 117MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 118 "(0=off, 1=on) (default=1).");
2dca0bba 119#endif
606ad75f 120
83012a7c 121#ifdef CONFIG_PM
65fcd41d
TI		 122static int param_set_xint(const char *val, const struct kernel_param *kp);
123static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126};
127#define param_check_xint param_check_int
128
fee2fba3 129static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 130module_param(power_save, xint, 0644);
fee2fba3
TI		 131MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
1da177e4 133
dee1b66c
TI		 134/* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
8fc24426
TI		 138static bool power_save_controller = 1;
139module_param(power_save_controller, bool, 0644);
dee1b66c 140MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 141#endif /* CONFIG_PM */
dee1b66c 142
7bfe059e
TI		 143static int align_buffer_size = -1;
144module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 145MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
27fe48d9
TI		 148#ifdef CONFIG_X86
149static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else
154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif
157
158
1da177e4
LT		 159MODULE_LICENSE("GPL");
160MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
2f1b3818 162 "{Intel, ICH7},"
f5d40b30 163 "{Intel, ESB2},"
d2981393 164 "{Intel, ICH8},"
f9cc8a8b 165 "{Intel, ICH9},"
c34f5a04 166 "{Intel, ICH10},"
b29c2360 167 "{Intel, PCH},"
d2f2fcd2 168 "{Intel, CPT},"
d2edeb7c 169 "{Intel, PPT},"
8bc039a1 170 "{Intel, LPT},"
144dad99 171 "{Intel, LPT_LP},"
e926f2c8 172 "{Intel, HPT},"
cea310e8 173 "{Intel, PBG},"
4979bca9 174 "{Intel, SCH},"
fc20a562 175 "{ATI, SB450},"
89be83f8 176 "{ATI, SB600},"
778b6e1b 177 "{ATI, RS600},"
5b15c95f 178 "{ATI, RS690},"
e6db1119
WL		 179 "{ATI, RS780},"
180 "{ATI, R600},"
2797f724
HRK		 181 "{ATI, RV630},"
182 "{ATI, RV610},"
27da1834
WL		 183 "{ATI, RV670},"
184 "{ATI, RV635},"
185 "{ATI, RV620},"
186 "{ATI, RV770},"
fc20a562 187 "{VIA, VT8251},"
47672310 188 "{VIA, VT8237A},"
07e4ca50
TI		 189 "{SiS, SIS966},"
190 "{ULI, M5461}}");
1da177e4
LT		 191MODULE_DESCRIPTION("Intel HDA driver");
192
4abc1cc2
TI		 193#ifdef CONFIG_SND_VERBOSE_PRINTK
194#define SFX /* nop */
195#else
445a51b3 196#define SFX "hda-intel "
4abc1cc2 197#endif
cb53c626 198
a82d51ed
TI		 199#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
200#ifdef CONFIG_SND_HDA_CODEC_HDMI
201#define SUPPORT_VGA_SWITCHEROO
202#endif
203#endif
204
205
1da177e4
LT		 206/*
207 * registers
208 */
209#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 210#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
211#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
212#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
213#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
214#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 215#define ICH6_REG_VMIN 0x02
216#define ICH6_REG_VMAJ 0x03
217#define ICH6_REG_OUTPAY 0x04
218#define ICH6_REG_INPAY 0x06
219#define ICH6_REG_GCTL 0x08
8a933ece 220#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 221#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
222#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 223#define ICH6_REG_WAKEEN 0x0c
224#define ICH6_REG_STATESTS 0x0e
225#define ICH6_REG_GSTS 0x10
b21fadb9 226#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 227#define ICH6_REG_INTCTL 0x20
228#define ICH6_REG_INTSTS 0x24
e5463720 229#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 230#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
231#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 232#define ICH6_REG_CORBLBASE 0x40
233#define ICH6_REG_CORBUBASE 0x44
234#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 235#define ICH6_REG_CORBRP 0x4a
236#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 237#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 238#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
239#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 240#define ICH6_REG_CORBSTS 0x4d
b21fadb9 241#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 242#define ICH6_REG_CORBSIZE 0x4e
243
244#define ICH6_REG_RIRBLBASE 0x50
245#define ICH6_REG_RIRBUBASE 0x54
246#define ICH6_REG_RIRBWP 0x58
b21fadb9 247#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 248#define ICH6_REG_RINTCNT 0x5a
249#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 250#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
251#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
252#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 253#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 254#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
255#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 256#define ICH6_REG_RIRBSIZE 0x5e
257
258#define ICH6_REG_IC 0x60
259#define ICH6_REG_IR 0x64
260#define ICH6_REG_IRS 0x68
261#define ICH6_IRS_VALID (1<<1)
262#define ICH6_IRS_BUSY (1<<0)
263
264#define ICH6_REG_DPLBASE 0x70
265#define ICH6_REG_DPUBASE 0x74
266#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
267
268/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
269enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
270
271/* stream register offsets from stream base */
272#define ICH6_REG_SD_CTL 0x00
273#define ICH6_REG_SD_STS 0x03
274#define ICH6_REG_SD_LPIB 0x04
275#define ICH6_REG_SD_CBL 0x08
276#define ICH6_REG_SD_LVI 0x0c
277#define ICH6_REG_SD_FIFOW 0x0e
278#define ICH6_REG_SD_FIFOSIZE 0x10
279#define ICH6_REG_SD_FORMAT 0x12
280#define ICH6_REG_SD_BDLPL 0x18
281#define ICH6_REG_SD_BDLPU 0x1c
282
283/* PCI space */
284#define ICH6_PCIREG_TCSEL 0x44
285
286/*
287 * other constants
288 */
289
290/* max number of SDs */
07e4ca50 291/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 292#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 293#define ICH6_NUM_PLAYBACK 4
294
295/* ULI has 6 playback and 5 capture */
07e4ca50 296#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 297#define ULI_NUM_PLAYBACK 6
298
778b6e1b 299/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 300#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 301#define ATIHDMI_NUM_PLAYBACK 1
302
f269002e
KY		 303/* TERA has 4 playback and 3 capture */
304#define TERA_NUM_CAPTURE 3
305#define TERA_NUM_PLAYBACK 4
306
07e4ca50
TI		 307/* this number is statically defined for simplicity */
308#define MAX_AZX_DEV 16
309
1da177e4 310/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 311#define BDL_SIZE 4096
312#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
313#define AZX_MAX_FRAG 32
1da177e4
LT		 314/* max buffer size - no h/w limit, you can increase as you like */
315#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 316
317/* RIRB int mask: overrun[2], response[0] */
318#define RIRB_INT_RESPONSE 0x01
319#define RIRB_INT_OVERRUN 0x04
320#define RIRB_INT_MASK 0x05
321
2f5983f2 322/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 323#define AZX_MAX_CODECS 8
324#define AZX_DEFAULT_CODECS 4
deadff16 325#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 326
327/* SD_CTL bits */
328#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
329#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 330#define SD_CTL_STRIPE (3 << 16) /* stripe control */
331#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
332#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 333#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
334#define SD_CTL_STREAM_TAG_SHIFT 20
335
336/* SD_CTL and SD_STS */
337#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
338#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
339#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 340#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
341 SD_INT_COMPLETE)
1da177e4
LT		 342
343/* SD_STS */
344#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
345
346/* INTCTL and INTSTS */
d01ce99f
TI		 347#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
348#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
349#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 350
1da177e4
LT		 351/* below are so far hardcoded - should read registers in future */
352#define ICH6_MAX_CORB_ENTRIES 256
353#define ICH6_MAX_RIRB_ENTRIES 256
354
c74db86b
TI		 355/* position fix mode */
356enum {
0be3b5d3 357 POS_FIX_AUTO,
d2e1c973 358 POS_FIX_LPIB,
0be3b5d3 359 POS_FIX_POSBUF,
4cb36310 360 POS_FIX_VIACOMBO,
a6f2fd55 361 POS_FIX_COMBO,
c74db86b 362};
1da177e4 363
f5d40b30 364/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 365#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
366#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
367
da3fca21
V		 368/* Defines for Nvidia HDA support */
369#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
370#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 371#define NVIDIA_HDA_ISTRM_COH 0x4d
372#define NVIDIA_HDA_OSTRM_COH 0x4c
373#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 374
90a5ad52
TI		 375/* Defines for Intel SCH HDA snoop control */
376#define INTEL_SCH_HDA_DEVC 0x78
377#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
378
0e153474
JC		 379/* Define IN stream 0 FIFO size offset in VIA controller */
380#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
381/* Define VIA HD Audio Device ID*/
382#define VIA_HDAC_DEVICE_ID 0x3288
383
c4da29ca
YL		 384/* HD Audio class code */
385#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 386
1da177e4
LT		 387/*
388 */
389
a98f90fd 390struct azx_dev {
4ce107b9 391 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 392 u32 *posbuf; /* position buffer pointer */
1da177e4 393
d01ce99f 394 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 395 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 396 unsigned int frags; /* number for period in the play buffer */
397 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 398 unsigned long start_wallclk; /* start + minimum wallclk */
399 unsigned long period_wallclk; /* wallclk for period */
1da177e4 400
d01ce99f 401 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 402
d01ce99f 403 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 404
405 /* pcm support */
d01ce99f
TI		 406 struct snd_pcm_substream *substream; /* assigned substream,
407 * set in PCM open
408 */
409 unsigned int format_val; /* format value to be set in the
410 * controller and the codec
411 */
1da177e4
LT		 412 unsigned char stream_tag; /* assigned stream */
413 unsigned char index; /* stream index */
d5cf9911 414 int assigned_key; /* last device# key assigned to */
1da177e4 415
927fc866
PM		 416 unsigned int opened :1;
417 unsigned int running :1;
675f25d4 418 unsigned int irq_pending :1;
eb49faa6
TI		 419 unsigned int prepared:1;
420 unsigned int locked:1;
0e153474
JC		 421 /*
422 * For VIA:
423 * A flag to ensure DMA position is 0
424 * when link position is not greater than FIFO size
425 */
426 unsigned int insufficient :1;
27fe48d9 427 unsigned int wc_marked:1;
915bf29e 428 unsigned int no_period_wakeup:1;
5d890f59
PLB		 429
430 struct timecounter azx_tc;
431 struct cyclecounter azx_cc;
eb49faa6
TI		 432
433#ifdef CONFIG_SND_HDA_DSP_LOADER
434 struct mutex dsp_mutex;
435#endif
1da177e4
LT		 436};
437
eb49faa6
TI		 438/* DSP lock helpers */
439#ifdef CONFIG_SND_HDA_DSP_LOADER
440#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
441#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
442#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
443#define dsp_is_locked(dev) ((dev)->locked)
444#else
445#define dsp_lock_init(dev) do {} while (0)
446#define dsp_lock(dev) do {} while (0)
447#define dsp_unlock(dev) do {} while (0)
448#define dsp_is_locked(dev) 0
449#endif
450
1da177e4 451/* CORB/RIRB */
a98f90fd 452struct azx_rb {
1da177e4
LT		 453 u32 *buf; /* CORB/RIRB buffer
454 * Each CORB entry is 4byte, RIRB is 8byte
455 */
456 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
457 /* for RIRB */
458 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 459 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
460 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 461};
462
01b65bfb
TI		 463struct azx_pcm {
464 struct azx *chip;
465 struct snd_pcm *pcm;
466 struct hda_codec *codec;
467 struct hda_pcm_stream *hinfo[2];
468 struct list_head list;
469};
470
a98f90fd
TI		 471struct azx {
472 struct snd_card *card;
1da177e4 473 struct pci_dev *pci;
555e219f 474 int dev_index;
1da177e4 475
07e4ca50
TI		 476 /* chip type specific */
477 int driver_type;
9477c58e 478 unsigned int driver_caps;
07e4ca50
TI		 479 int playback_streams;
480 int playback_index_offset;
481 int capture_streams;
482 int capture_index_offset;
483 int num_streams;
484
1da177e4
LT		 485 /* pci resources */
486 unsigned long addr;
487 void __iomem *remap_addr;
488 int irq;
489
490 /* locks */
491 spinlock_t reg_lock;
62932df8 492 struct mutex open_mutex;
f4c482a4 493 struct completion probe_wait;
1da177e4 494
07e4ca50 495 /* streams (x num_streams) */
a98f90fd 496 struct azx_dev *azx_dev;
1da177e4
LT		 497
498 /* PCM */
01b65bfb 499 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 500
501 /* HD codec */
502 unsigned short codec_mask;
f1eaaeec 503 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 504 struct hda_bus *bus;
2dca0bba 505 unsigned int beep_mode;
1da177e4
LT		 506
507 /* CORB/RIRB */
a98f90fd
TI		 508 struct azx_rb corb;
509 struct azx_rb rirb;
1da177e4 510
4ce107b9 511 /* CORB/RIRB and position buffers */
1da177e4
LT		 512 struct snd_dma_buffer rb;
513 struct snd_dma_buffer posbuf;
c74db86b 514
4918cdab
TI		 515#ifdef CONFIG_SND_HDA_PATCH_LOADER
516 const struct firmware *fw;
517#endif
518
c74db86b 519 /* flags */
beaffc39 520 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 521 int poll_count;
cb53c626 522 unsigned int running :1;
927fc866
PM		 523 unsigned int initialized :1;
524 unsigned int single_cmd :1;
525 unsigned int polling_mode :1;
68e7fffc 526 unsigned int msi :1;
a6a950a8 527 unsigned int irq_pending_warned :1;
6ce4a3bc 528 unsigned int probing :1; /* codec probing phase */
27fe48d9 529 unsigned int snoop:1;
52409aa6 530 unsigned int align_buffer_size:1;
a82d51ed
TI		 531 unsigned int region_requested:1;
532
533 /* VGA-switcheroo setup */
534 unsigned int use_vga_switcheroo:1;
128960a9 535 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 536 unsigned int init_failed:1; /* delayed init failed */
537 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 538
539 /* for debugging */
feb27340 540 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 541
542 /* for pending irqs */
543 struct work_struct irq_pending_work;
0cbf0098 544
99a2008d
WX		 545#ifdef CONFIG_SND_HDA_I915
546 struct work_struct probe_work;
547#endif
548
0cbf0098
TI		 549 /* reboot notifier (for mysterious hangup problem at power-down) */
550 struct notifier_block reboot_notifier;
65fcd41d
TI		 551
552 /* card list (for power_save trigger) */
553 struct list_head list;
eb49faa6
TI		 554
555#ifdef CONFIG_SND_HDA_DSP_LOADER
556 struct azx_dev saved_azx_dev;
557#endif
1da177e4
LT		 558};
559
1a8506d4
TI		 560#define CREATE_TRACE_POINTS
561#include "hda_intel_trace.h"
562
07e4ca50
TI		 563/* driver types */
564enum {
565 AZX_DRIVER_ICH,
32679f95 566 AZX_DRIVER_PCH,
4979bca9 567 AZX_DRIVER_SCH,
07e4ca50 568 AZX_DRIVER_ATI,
778b6e1b 569 AZX_DRIVER_ATIHDMI,
1815b34a 570 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 571 AZX_DRIVER_VIA,
572 AZX_DRIVER_SIS,
573 AZX_DRIVER_ULI,
da3fca21 574 AZX_DRIVER_NVIDIA,
f269002e 575 AZX_DRIVER_TERA,
14d34f16 576 AZX_DRIVER_CTX,
5ae763b1 577 AZX_DRIVER_CTHDA,
c4da29ca 578 AZX_DRIVER_GENERIC,
2f5983f2 579 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 580};
581
9477c58e
TI		 582/* driver quirks (capabilities) */
583/* bits 0-7 are used for indicating driver type */
584#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
585#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
586#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
587#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
588#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
589#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
590#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
591#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
592#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
593#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
594#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
595#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 596#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 597#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 598#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 599#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 600#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2 601#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
99a2008d 602#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
2ea3c6a2
TI		 603
604/* quirks for Intel PCH */
d7dab4db 605#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 606 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 607 AZX_DCAPS_COUNT_LPIB_DELAY)
608
609#define AZX_DCAPS_INTEL_PCH \
610 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 611
612/* quirks for ATI SB / AMD Hudson */
613#define AZX_DCAPS_PRESET_ATI_SB \
614 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
615 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
616
617/* quirks for ATI/AMD HDMI */
618#define AZX_DCAPS_PRESET_ATI_HDMI \
619 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
620
621/* quirks for Nvidia */
622#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 623 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 624 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 625
5ae763b1
TI		 626#define AZX_DCAPS_PRESET_CTHDA \
627 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
628
a82d51ed
TI		 629/*
630 * VGA-switcher support
631 */
632#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 633#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
634#else
635#define use_vga_switcheroo(chip) 0
636#endif
637
48c8b0eb 638static char *driver_short_names[] = {
07e4ca50 639 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 640 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 641 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 642 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 643 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 644 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 645 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
646 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 647 [AZX_DRIVER_ULI] = "HDA ULI M5461",
648 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 649 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 650 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 651 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 652 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 653};
654
1da177e4
LT		 655/*
656 * macros for easy use
657 */
658#define azx_writel(chip,reg,value) \
659 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
660#define azx_readl(chip,reg) \
661 readl((chip)->remap_addr + ICH6_REG_##reg)
662#define azx_writew(chip,reg,value) \
663 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
664#define azx_readw(chip,reg) \
665 readw((chip)->remap_addr + ICH6_REG_##reg)
666#define azx_writeb(chip,reg,value) \
667 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
668#define azx_readb(chip,reg) \
669 readb((chip)->remap_addr + ICH6_REG_##reg)
670
671#define azx_sd_writel(dev,reg,value) \
672 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
673#define azx_sd_readl(dev,reg) \
674 readl((dev)->sd_addr + ICH6_REG_##reg)
675#define azx_sd_writew(dev,reg,value) \
676 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
677#define azx_sd_readw(dev,reg) \
678 readw((dev)->sd_addr + ICH6_REG_##reg)
679#define azx_sd_writeb(dev,reg,value) \
680 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
681#define azx_sd_readb(dev,reg) \
682 readb((dev)->sd_addr + ICH6_REG_##reg)
683
684/* for pcm support */
a98f90fd 685#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 686
27fe48d9 687#ifdef CONFIG_X86
9ddf1aeb 688static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 689{
9ddf1aeb
TI		 690 int pages;
691
27fe48d9
TI		 692 if (azx_snoop(chip))
693 return;
9ddf1aeb
TI		 694 if (!dmab || !dmab->area || !dmab->bytes)
695 return;
696
697#ifdef CONFIG_SND_DMA_SGBUF
698 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
699 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 700 if (on)
9ddf1aeb 701 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 702 else
9ddf1aeb
TI		 703 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
704 return;
27fe48d9 705 }
9ddf1aeb
TI		 706#endif
707
708 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
709 if (on)
710 set_memory_wc((unsigned long)dmab->area, pages);
711 else
712 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 713}
714
715static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
716 bool on)
717{
9ddf1aeb 718 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 719}
720static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 721 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 722{
723 if (azx_dev->wc_marked != on) {
9ddf1aeb 724 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 725 azx_dev->wc_marked = on;
726 }
727}
728#else
729/* NOP for other archs */
730static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
731 bool on)
732{
733}
734static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 735 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 736{
737}
738#endif
739
68e7fffc 740static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 741static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 742/*
743 * Interface for HD codec
744 */
745
1da177e4
LT		 746/*
747 * CORB / RIRB interface
748 */
a98f90fd 749static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 750{
751 int err;
752
753 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 754 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
755 snd_dma_pci_data(chip->pci),
1da177e4
LT		 756 PAGE_SIZE, &chip->rb);
757 if (err < 0) {
445a51b3 758 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 759 return err;
760 }
27fe48d9 761 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 762 return 0;
763}
764
a98f90fd 765static void azx_init_cmd_io(struct azx *chip)
1da177e4 766{
cdb1fbf2 767 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 768 /* CORB set up */
769 chip->corb.addr = chip->rb.addr;
770 chip->corb.buf = (u32 *)chip->rb.area;
771 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 772 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 773
07e4ca50
TI		 774 /* set the corb size to 256 entries (ULI requires explicitly) */
775 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 776 /* set the corb write pointer to 0 */
777 azx_writew(chip, CORBWP, 0);
778 /* reset the corb hw read pointer */
b21fadb9 779 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 780 /* enable corb dma */
b21fadb9 781 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 782
783 /* RIRB set up */
784 chip->rirb.addr = chip->rb.addr + 2048;
785 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 786 chip->rirb.wp = chip->rirb.rp = 0;
787 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 788 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 789 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 790
07e4ca50
TI		 791 /* set the rirb size to 256 entries (ULI requires explicitly) */
792 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 793 /* reset the rirb hw write pointer */
b21fadb9 794 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 795 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 796 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 797 azx_writew(chip, RINTCNT, 0xc0);
798 else
799 azx_writew(chip, RINTCNT, 1);
1da177e4 800 /* enable rirb dma and response irq */
1da177e4 801 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 802 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 803}
804
a98f90fd 805static void azx_free_cmd_io(struct azx *chip)
1da177e4 806{
cdb1fbf2 807 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 808 /* disable ringbuffer DMAs */
809 azx_writeb(chip, RIRBCTL, 0);
810 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 811 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 812}
813
deadff16
WF		 814static unsigned int azx_command_addr(u32 cmd)
815{
816 unsigned int addr = cmd >> 28;
817
818 if (addr >= AZX_MAX_CODECS) {
819 snd_BUG();
820 addr = 0;
821 }
822
823 return addr;
824}
825
826static unsigned int azx_response_addr(u32 res)
827{
828 unsigned int addr = res & 0xf;
829
830 if (addr >= AZX_MAX_CODECS) {
831 snd_BUG();
832 addr = 0;
833 }
834
835 return addr;
1da177e4
LT		 836}
837
838/* send a command */
33fa35ed 839static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 840{
33fa35ed 841 struct azx *chip = bus->private_data;
deadff16 842 unsigned int addr = azx_command_addr(val);
3bcce5c0 843 unsigned int wp, rp;
1da177e4 844
c32649fe
WF		 845 spin_lock_irq(&chip->reg_lock);
846
1da177e4 847 /* add command to corb */
cc5ede3e
TI		 848 wp = azx_readw(chip, CORBWP);
849 if (wp == 0xffff) {
850 /* something wrong, controller likely turned to D3 */
851 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 852 return -EIO;
cc5ede3e 853 }
1da177e4
LT		 854 wp++;
855 wp %= ICH6_MAX_CORB_ENTRIES;
856
3bcce5c0
TI		 857 rp = azx_readw(chip, CORBRP);
858 if (wp == rp) {
859 /* oops, it's full */
860 spin_unlock_irq(&chip->reg_lock);
861 return -EAGAIN;
862 }
863
deadff16 864 chip->rirb.cmds[addr]++;
1da177e4
LT		 865 chip->corb.buf[wp] = cpu_to_le32(val);
866 azx_writel(chip, CORBWP, wp);
c32649fe 867
1da177e4
LT		 868 spin_unlock_irq(&chip->reg_lock);
869
870 return 0;
871}
872
873#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
874
875/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 876static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 877{
878 unsigned int rp, wp;
deadff16 879 unsigned int addr;
1da177e4
LT		 880 u32 res, res_ex;
881
cc5ede3e
TI		 882 wp = azx_readw(chip, RIRBWP);
883 if (wp == 0xffff) {
884 /* something wrong, controller likely turned to D3 */
885 return;
886 }
887
1da177e4
LT		 888 if (wp == chip->rirb.wp)
889 return;
890 chip->rirb.wp = wp;
deadff16 891
1da177e4
LT		 892 while (chip->rirb.rp != wp) {
893 chip->rirb.rp++;
894 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
895
896 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
897 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
898 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 899 addr = azx_response_addr(res_ex);
1da177e4
LT		 900 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
901 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 902 else if (chip->rirb.cmds[addr]) {
903 chip->rirb.res[addr] = res;
2add9b92 904 smp_wmb();
deadff16 905 chip->rirb.cmds[addr]--;
e310bb06 906 } else
9e3d352b 907 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 908 "last cmd=%#08x\n",
9e3d352b 909 pci_name(chip->pci),
e310bb06
WF		 910 res, res_ex,
911 chip->last_cmd[addr]);
1da177e4
LT		 912 }
913}
914
915/* receive a response */
deadff16
WF		 916static unsigned int azx_rirb_get_response(struct hda_bus *bus,
917 unsigned int addr)
1da177e4 918{
33fa35ed 919 struct azx *chip = bus->private_data;
5c79b1f8 920 unsigned long timeout;
32cf4023 921 unsigned long loopcounter;
1eb6dc7d 922 int do_poll = 0;
1da177e4 923
5c79b1f8
TI		 924 again:
925 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 926
927 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 928 if (chip->polling_mode || do_poll) {
e96224ae
TI		 929 spin_lock_irq(&chip->reg_lock);
930 azx_update_rirb(chip);
931 spin_unlock_irq(&chip->reg_lock);
932 }
deadff16 933 if (!chip->rirb.cmds[addr]) {
2add9b92 934 smp_rmb();
b613291f 935 bus->rirb_error = 0;
1eb6dc7d
ML		 936
937 if (!do_poll)
938 chip->poll_count = 0;
deadff16 939 return chip->rirb.res[addr]; /* the last value */
2add9b92 940 }
28a0d9df
TI		 941 if (time_after(jiffies, timeout))
942 break;
32cf4023 943 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 944 msleep(2); /* temporary workaround */
945 else {
946 udelay(10);
947 cond_resched();
948 }
28a0d9df 949 }
5c79b1f8 950
63e51fd7
TI		 951 if (!bus->no_response_fallback)
952 return -1;
953
1eb6dc7d 954 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 955 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 956 "polling the codec once: last cmd=0x%08x\n",
445a51b3 957 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 958 do_poll = 1;
959 chip->poll_count++;
960 goto again;
961 }
962
963
23c4a881 964 if (!chip->polling_mode) {
445a51b3 965 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 966 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 967 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 968 chip->polling_mode = 1;
969 goto again;
970 }
971
68e7fffc 972 if (chip->msi) {
445a51b3 973 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 974 "disabling MSI: last cmd=0x%08x\n",
445a51b3 975 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 976 free_irq(chip->irq, chip);
977 chip->irq = -1;
978 pci_disable_msi(chip->pci);
979 chip->msi = 0;
b613291f
TI		 980 if (azx_acquire_irq(chip, 1) < 0) {
981 bus->rirb_error = 1;
68e7fffc 982 return -1;
b613291f 983 }
68e7fffc
TI		 984 goto again;
985 }
986
6ce4a3bc
TI		 987 if (chip->probing) {
988 /* If this critical timeout happens during the codec probing
989 * phase, this is likely an access to a non-existing codec
990 * slot. Better to return an error and reset the system.
991 */
992 return -1;
993 }
994
8dd78330
TI		 995 /* a fatal communication error; need either to reset or to fallback
996 * to the single_cmd mode
997 */
b613291f 998 bus->rirb_error = 1;
b20f3b83 999 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 1000 bus->response_reset = 1;
1001 return -1; /* give a chance to retry */
1002 }
1003
1004 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1005 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1006 chip->last_cmd[addr]);
8dd78330
TI		 1007 chip->single_cmd = 1;
1008 bus->response_reset = 0;
1a696978 1009 /* release CORB/RIRB */
4fcd3920 1010 azx_free_cmd_io(chip);
1a696978
TI		 1011 /* disable unsolicited responses */
1012 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1013 return -1;
1da177e4
LT		 1014}
1015
1da177e4
LT		 1016/*
1017 * Use the single immediate command instead of CORB/RIRB for simplicity
1018 *
1019 * Note: according to Intel, this is not preferred use. The command was
1020 * intended for the BIOS only, and may get confused with unsolicited
1021 * responses. So, we shouldn't use it for normal operation from the
1022 * driver.
1023 * I left the codes, however, for debugging/testing purposes.
1024 */
1025
b05a7d4f 1026/* receive a response */
deadff16 1027static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1028{
1029 int timeout = 50;
1030
1031 while (timeout--) {
1032 /* check IRV busy bit */
1033 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1034 /* reuse rirb.res as the response return value */
deadff16 1035 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1036 return 0;
1037 }
1038 udelay(1);
1039 }
1040 if (printk_ratelimit())
445a51b3
DB		 1041 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1042 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1043 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1044 return -EIO;
1045}
1046
1da177e4 1047/* send a command */
33fa35ed 1048static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1049{
33fa35ed 1050 struct azx *chip = bus->private_data;
deadff16 1051 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1052 int timeout = 50;
1053
8dd78330 1054 bus->rirb_error = 0;
1da177e4
LT		 1055 while (timeout--) {
1056 /* check ICB busy bit */
d01ce99f 1057 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1058 /* Clear IRV valid bit */
d01ce99f
TI		 1059 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1060 ICH6_IRS_VALID);
1da177e4 1061 azx_writel(chip, IC, val);
d01ce99f
TI		 1062 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1063 ICH6_IRS_BUSY);
deadff16 1064 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1065 }
1066 udelay(1);
1067 }
1cfd52bc 1068 if (printk_ratelimit())
445a51b3
DB		 1069 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1070 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1071 return -EIO;
1072}
1073
1074/* receive a response */
deadff16
WF		 1075static unsigned int azx_single_get_response(struct hda_bus *bus,
1076 unsigned int addr)
1da177e4 1077{
33fa35ed 1078 struct azx *chip = bus->private_data;
deadff16 1079 return chip->rirb.res[addr];
1da177e4
LT		 1080}
1081
111d3af5
TI		 1082/*
1083 * The below are the main callbacks from hda_codec.
1084 *
1085 * They are just the skeleton to call sub-callbacks according to the
1086 * current setting of chip->single_cmd.
1087 */
1088
1089/* send a command */
33fa35ed 1090static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1091{
33fa35ed 1092 struct azx *chip = bus->private_data;
43bbb6cc 1093
a82d51ed
TI		 1094 if (chip->disabled)
1095 return 0;
feb27340 1096 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1097 if (chip->single_cmd)
33fa35ed 1098 return azx_single_send_cmd(bus, val);
111d3af5 1099 else
33fa35ed 1100 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1101}
1102
1103/* get a response */
deadff16
WF		 1104static unsigned int azx_get_response(struct hda_bus *bus,
1105 unsigned int addr)
111d3af5 1106{
33fa35ed 1107 struct azx *chip = bus->private_data;
a82d51ed
TI		 1108 if (chip->disabled)
1109 return 0;
111d3af5 1110 if (chip->single_cmd)
deadff16 1111 return azx_single_get_response(bus, addr);
111d3af5 1112 else
deadff16 1113 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1114}
1115
83012a7c 1116#ifdef CONFIG_PM
68467f51 1117static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1118#endif
111d3af5 1119
1d1a4564
TI		 1120#ifdef CONFIG_SND_HDA_DSP_LOADER
1121static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1122 unsigned int byte_size,
1123 struct snd_dma_buffer *bufp);
1124static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1125static void azx_load_dsp_cleanup(struct hda_bus *bus,
1126 struct snd_dma_buffer *dmab);
1127#endif
1128
3af3f356 1129/* enter link reset */
7295b264 1130static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 1131{
1132 unsigned long timeout;
1133
1134 /* reset controller */
1135 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1136
1137 timeout = jiffies + msecs_to_jiffies(100);
1138 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1139 time_before(jiffies, timeout))
1140 usleep_range(500, 1000);
1141}
1142
7295b264
ML		 1143/* exit link reset */
1144static void azx_exit_link_reset(struct azx *chip)
1da177e4 1145{
fa348da5 1146 unsigned long timeout;
1da177e4 1147
7295b264
ML		 1148 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1149
1150 timeout = jiffies + msecs_to_jiffies(100);
1151 while (!azx_readb(chip, GCTL) &&
1152 time_before(jiffies, timeout))
1153 usleep_range(500, 1000);
1154}
1155
1156/* reset codec link */
1157static int azx_reset(struct azx *chip, int full_reset)
1158{
cd508fe5
JK		 1159 if (!full_reset)
1160 goto __skip;
1161
e8a7f136 1162 /* clear STATESTS */
da7db6ad 1163 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 1164
1da177e4 1165 /* reset controller */
7295b264 1166 azx_enter_link_reset(chip);
1da177e4
LT		 1167
1168 /* delay for >= 100us for codec PLL to settle per spec
1169 * Rev 0.9 section 5.5.1
1170 */
fa348da5 1171 usleep_range(500, 1000);
1da177e4
LT		 1172
1173 /* Bring controller out of reset */
7295b264 1174 azx_exit_link_reset(chip);
1da177e4 1175
927fc866 1176 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1177 usleep_range(1000, 1200);
1da177e4 1178
cd508fe5 1179 __skip:
1da177e4 1180 /* check to see if controller is ready */
927fc866 1181 if (!azx_readb(chip, GCTL)) {
445a51b3 1182 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1183 return -EBUSY;
1184 }
1185
41e2fce4 1186 /* Accept unsolicited responses */
1a696978
TI		 1187 if (!chip->single_cmd)
1188 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1189 ICH6_GCTL_UNSOL);
41e2fce4 1190
1da177e4 1191 /* detect codecs */
927fc866 1192 if (!chip->codec_mask) {
1da177e4 1193 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1194 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1195 }
1196
1197 return 0;
1198}
1199
1200
1201/*
1202 * Lowlevel interface
1203 */
1204
1205/* enable interrupts */
a98f90fd 1206static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1207{
1208 /* enable controller CIE and GIE */
1209 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1210 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1211}
1212
1213/* disable interrupts */
a98f90fd 1214static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1215{
1216 int i;
1217
1218 /* disable interrupts in stream descriptor */
07e4ca50 1219 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1220 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1221 azx_sd_writeb(azx_dev, SD_CTL,
1222 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1223 }
1224
1225 /* disable SIE for all streams */
1226 azx_writeb(chip, INTCTL, 0);
1227
1228 /* disable controller CIE and GIE */
1229 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1230 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1231}
1232
1233/* clear interrupts */
a98f90fd 1234static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1235{
1236 int i;
1237
1238 /* clear stream status */
07e4ca50 1239 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1240 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1241 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1242 }
1243
1244 /* clear STATESTS */
da7db6ad 1245 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 1246
1247 /* clear rirb status */
1248 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1249
1250 /* clear int status */
1251 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1252}
1253
1254/* start a stream */
a98f90fd 1255static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1256{
0e153474
JC		 1257 /*
1258 * Before stream start, initialize parameter
1259 */
1260 azx_dev->insufficient = 1;
1261
1da177e4 1262 /* enable SIE */
ccc5df05
WN		 1263 azx_writel(chip, INTCTL,
1264 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1265 /* set DMA start and interrupt mask */
1266 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1267 SD_CTL_DMA_START | SD_INT_MASK);
1268}
1269
1dddab40
TI		 1270/* stop DMA */
1271static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1272{
1da177e4
LT		 1273 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1274 ~(SD_CTL_DMA_START | SD_INT_MASK));
1275 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1276}
1277
1278/* stop a stream */
1279static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1280{
1281 azx_stream_clear(chip, azx_dev);
1da177e4 1282 /* disable SIE */
ccc5df05
WN		 1283 azx_writel(chip, INTCTL,
1284 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1285}
1286
1287
1288/*
cb53c626 1289 * reset and start the controller registers
1da177e4 1290 */
cd508fe5 1291static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1292{
cb53c626
TI		 1293 if (chip->initialized)
1294 return;
1da177e4
LT		 1295
1296 /* reset controller */
cd508fe5 1297 azx_reset(chip, full_reset);
1da177e4
LT		 1298
1299 /* initialize interrupts */
1300 azx_int_clear(chip);
1301 azx_int_enable(chip);
1302
1303 /* initialize the codec command I/O */
1a696978
TI		 1304 if (!chip->single_cmd)
1305 azx_init_cmd_io(chip);
1da177e4 1306
0be3b5d3
TI		 1307 /* program the position buffer */
1308 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1309 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1310
cb53c626
TI		 1311 chip->initialized = 1;
1312}
1313
1314/*
1315 * initialize the PCI registers
1316 */
1317/* update bits in a PCI register byte */
1318static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1319 unsigned char mask, unsigned char val)
1320{
1321 unsigned char data;
1322
1323 pci_read_config_byte(pci, reg, &data);
1324 data &= ~mask;
1325 data |= (val & mask);
1326 pci_write_config_byte(pci, reg, data);
1327}
1328
1329static void azx_init_pci(struct azx *chip)
1330{
1331 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1332 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1333 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1334 * codecs.
1335 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1336 */
46f2cc80 1337 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1338 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1339 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1340 }
cb53c626 1341
9477c58e
TI		 1342 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1343 * we need to enable snoop.
1344 */
1345 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1346 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1347 update_pci_byte(chip->pci,
27fe48d9
TI		 1348 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1349 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1350 }
1351
1352 /* For NVIDIA HDA, enable snoop */
1353 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1354 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1355 update_pci_byte(chip->pci,
1356 NVIDIA_HDA_TRANSREG_ADDR,
1357 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1358 update_pci_byte(chip->pci,
1359 NVIDIA_HDA_ISTRM_COH,
1360 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1361 update_pci_byte(chip->pci,
1362 NVIDIA_HDA_OSTRM_COH,
1363 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1364 }
1365
1366 /* Enable SCH/PCH snoop if needed */
1367 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1368 unsigned short snoop;
90a5ad52 1369 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1370 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1371 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1372 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1373 if (!azx_snoop(chip))
1374 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1375 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1376 pci_read_config_word(chip->pci,
1377 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1378 }
445a51b3
DB		 1379 snd_printdd(SFX "%s: SCH snoop: %s\n",
1380 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1381 ? "Disabled" : "Enabled");
da3fca21 1382 }
1da177e4
LT		 1383}
1384
1385
9ad593f6
TI		 1386static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1387
1da177e4
LT		 1388/*
1389 * interrupt handler
1390 */
7d12e780 1391static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1392{
a98f90fd
TI		 1393 struct azx *chip = dev_id;
1394 struct azx_dev *azx_dev;
1da177e4 1395 u32 status;
9ef04066 1396 u8 sd_status;
fa00e046 1397 int i, ok;
1da177e4 1398
b8dfc462
ML		 1399#ifdef CONFIG_PM_RUNTIME
1400 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1401 return IRQ_NONE;
1402#endif
1403
1da177e4
LT		 1404 spin_lock(&chip->reg_lock);
1405
60911062
DC		 1406 if (chip->disabled) {
1407 spin_unlock(&chip->reg_lock);
a82d51ed 1408 return IRQ_NONE;
60911062 1409 }
a82d51ed 1410
1da177e4
LT		 1411 status = azx_readl(chip, INTSTS);
1412 if (status == 0) {
1413 spin_unlock(&chip->reg_lock);
1414 return IRQ_NONE;
1415 }
1416
07e4ca50 1417 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1418 azx_dev = &chip->azx_dev[i];
1419 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1420 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1421 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1422 if (!azx_dev->substream || !azx_dev->running ||
1423 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1424 continue;
1425 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1426 ok = azx_position_ok(chip, azx_dev);
1427 if (ok == 1) {
9ad593f6 1428 azx_dev->irq_pending = 0;
1da177e4
LT		 1429 spin_unlock(&chip->reg_lock);
1430 snd_pcm_period_elapsed(azx_dev->substream);
1431 spin_lock(&chip->reg_lock);
fa00e046 1432 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1433 /* bogus IRQ, process it later */
1434 azx_dev->irq_pending = 1;
6acaed38
TI		 1435 queue_work(chip->bus->workq,
1436 &chip->irq_pending_work);
1da177e4
LT		 1437 }
1438 }
1439 }
1440
1441 /* clear rirb int */
1442 status = azx_readb(chip, RIRBSTS);
1443 if (status & RIRB_INT_MASK) {
14d34f16 1444 if (status & RIRB_INT_RESPONSE) {
9477c58e 1445 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1446 udelay(80);
1da177e4 1447 azx_update_rirb(chip);
14d34f16 1448 }
1da177e4
LT		 1449 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1450 }
1451
1452#if 0
1453 /* clear state status int */
da7db6ad
WX		 1454 if (azx_readw(chip, STATESTS) & 0x04)
1455 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1456#endif
1457 spin_unlock(&chip->reg_lock);
1458
1459 return IRQ_HANDLED;
1460}
1461
1462
675f25d4
TI		 1463/*
1464 * set up a BDL entry
1465 */
5ae763b1 1466static int setup_bdle(struct azx *chip,
1d1a4564 1467 struct snd_dma_buffer *dmab,
675f25d4
TI		 1468 struct azx_dev *azx_dev, u32 **bdlp,
1469 int ofs, int size, int with_ioc)
1470{
675f25d4
TI		 1471 u32 *bdl = *bdlp;
1472
1473 while (size > 0) {
1474 dma_addr_t addr;
1475 int chunk;
1476
1477 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1478 return -EINVAL;
1479
1d1a4564 1480 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1481 /* program the address field of the BDL entry */
1482 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1483 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1484 /* program the size field of the BDL entry */
1d1a4564 1485 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1486 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1487 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1488 u32 remain = 0x1000 - (ofs & 0xfff);
1489 if (chunk > remain)
1490 chunk = remain;
1491 }
675f25d4
TI		 1492 bdl[2] = cpu_to_le32(chunk);
1493 /* program the IOC to enable interrupt
1494 * only when the whole fragment is processed
1495 */
1496 size -= chunk;
1497 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1498 bdl += 4;
1499 azx_dev->frags++;
1500 ofs += chunk;
1501 }
1502 *bdlp = bdl;
1503 return ofs;
1504}
1505
1da177e4
LT		 1506/*
1507 * set up BDL entries
1508 */
555e219f
TI		 1509static int azx_setup_periods(struct azx *chip,
1510 struct snd_pcm_substream *substream,
4ce107b9 1511 struct azx_dev *azx_dev)
1da177e4 1512{
4ce107b9
TI		 1513 u32 *bdl;
1514 int i, ofs, periods, period_bytes;
555e219f 1515 int pos_adj;
1da177e4
LT		 1516
1517 /* reset BDL address */
1518 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1519 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1520
97b71c94 1521 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1522 periods = azx_dev->bufsize / period_bytes;
1523
1da177e4 1524 /* program the initial BDL entries */
4ce107b9
TI		 1525 bdl = (u32 *)azx_dev->bdl.area;
1526 ofs = 0;
1527 azx_dev->frags = 0;
555e219f 1528 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1529 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1530 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1531 int pos_align = pos_adj;
555e219f 1532 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1533 if (!pos_adj)
e785d3d8
TI		 1534 pos_adj = pos_align;
1535 else
1536 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1537 pos_align;
675f25d4
TI		 1538 pos_adj = frames_to_bytes(runtime, pos_adj);
1539 if (pos_adj >= period_bytes) {
445a51b3
DB		 1540 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1541 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1542 pos_adj = 0;
1543 } else {
1d1a4564
TI		 1544 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1545 azx_dev,
915bf29e 1546 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1547 if (ofs < 0)
1548 goto error;
4ce107b9 1549 }
555e219f
TI		 1550 } else
1551 pos_adj = 0;
675f25d4
TI		 1552 for (i = 0; i < periods; i++) {
1553 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1554 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1555 azx_dev, &bdl, ofs,
675f25d4
TI		 1556 period_bytes - pos_adj, 0);
1557 else
1d1a4564
TI		 1558 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1559 azx_dev, &bdl, ofs,
7bb8fb70 1560 period_bytes,
915bf29e 1561 !azx_dev->no_period_wakeup);
675f25d4
TI		 1562 if (ofs < 0)
1563 goto error;
1da177e4 1564 }
4ce107b9 1565 return 0;
675f25d4
TI		 1566
1567 error:
445a51b3
DB		 1568 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1569 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1570 return -EINVAL;
1da177e4
LT		 1571}
1572
1dddab40
TI		 1573/* reset stream */
1574static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1575{
1576 unsigned char val;
1577 int timeout;
1578
1dddab40
TI		 1579 azx_stream_clear(chip, azx_dev);
1580
d01ce99f
TI		 1581 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1582 SD_CTL_STREAM_RESET);
1da177e4
LT		 1583 udelay(3);
1584 timeout = 300;
1585 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1586 --timeout)
1587 ;
1588 val &= ~SD_CTL_STREAM_RESET;
1589 azx_sd_writeb(azx_dev, SD_CTL, val);
1590 udelay(3);
1591
1592 timeout = 300;
1593 /* waiting for hardware to report that the stream is out of reset */
1594 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1595 --timeout)
1596 ;
fa00e046
JK		 1597
1598 /* reset first position - may not be synced with hw at this time */
1599 *azx_dev->posbuf = 0;
1dddab40 1600}
1da177e4 1601
1dddab40
TI		 1602/*
1603 * set up the SD for streaming
1604 */
1605static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1606{
27fe48d9 1607 unsigned int val;
1dddab40
TI		 1608 /* make sure the run bit is zero for SD */
1609 azx_stream_clear(chip, azx_dev);
1da177e4 1610 /* program the stream_tag */
27fe48d9
TI		 1611 val = azx_sd_readl(azx_dev, SD_CTL);
1612 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1613 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1614 if (!azx_snoop(chip))
1615 val |= SD_CTL_TRAFFIC_PRIO;
1616 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1617
1618 /* program the length of samples in cyclic buffer */
1619 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1620
1621 /* program the stream format */
1622 /* this value needs to be the same as the one programmed */
1623 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1624
1625 /* program the stream LVI (last valid index) of the BDL */
1626 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1627
1628 /* program the BDL address */
1629 /* lower BDL address */
4ce107b9 1630 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1631 /* upper BDL address */
766979e0 1632 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1633
0be3b5d3 1634 /* enable the position buffer */
4cb36310
DH		 1635 if (chip->position_fix[0] != POS_FIX_LPIB ||
1636 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1637 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1638 azx_writel(chip, DPLBASE,
1639 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1640 }
c74db86b 1641
1da177e4 1642 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1643 azx_sd_writel(azx_dev, SD_CTL,
1644 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1645
1646 return 0;
1647}
1648
6ce4a3bc
TI		 1649/*
1650 * Probe the given codec address
1651 */
1652static int probe_codec(struct azx *chip, int addr)
1653{
1654 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1655 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1656 unsigned int res;
1657
a678cdee 1658 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1659 chip->probing = 1;
1660 azx_send_cmd(chip->bus, cmd);
deadff16 1661 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1662 chip->probing = 0;
a678cdee 1663 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1664 if (res == -1)
1665 return -EIO;
445a51b3 1666 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1667 return 0;
1668}
1669
33fa35ed
TI		 1670static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1671 struct hda_pcm *cpcm);
6ce4a3bc 1672static void azx_stop_chip(struct azx *chip);
1da177e4 1673
8dd78330
TI		 1674static void azx_bus_reset(struct hda_bus *bus)
1675{
1676 struct azx *chip = bus->private_data;
8dd78330
TI		 1677
1678 bus->in_reset = 1;
1679 azx_stop_chip(chip);
cd508fe5 1680 azx_init_chip(chip, 1);
65f75983 1681#ifdef CONFIG_PM
8dd78330 1682 if (chip->initialized) {
01b65bfb
TI		 1683 struct azx_pcm *p;
1684 list_for_each_entry(p, &chip->pcm_list, list)
1685 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1686 snd_hda_suspend(chip->bus);
1687 snd_hda_resume(chip->bus);
1688 }
65f75983 1689#endif
8dd78330
TI		 1690 bus->in_reset = 0;
1691}
1692
26a6cb6c
DH		 1693static int get_jackpoll_interval(struct azx *chip)
1694{
1695 int i = jackpoll_ms[chip->dev_index];
1696 unsigned int j;
1697 if (i == 0)
1698 return 0;
1699 if (i < 50 || i > 60000)
1700 j = 0;
1701 else
1702 j = msecs_to_jiffies(i);
1703 if (j == 0)
1704 snd_printk(KERN_WARNING SFX
1705 "jackpoll_ms value out of range: %d\n", i);
1706 return j;
1707}
1708
1da177e4
LT		 1709/*
1710 * Codec initialization
1711 */
1712
2f5983f2 1713/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1714static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1715 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1716 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1717};
1718
48c8b0eb 1719static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1720{
1721 struct hda_bus_template bus_temp;
34c25350
TI		 1722 int c, codecs, err;
1723 int max_slots;
1da177e4
LT		 1724
1725 memset(&bus_temp, 0, sizeof(bus_temp));
1726 bus_temp.private_data = chip;
1727 bus_temp.modelname = model;
1728 bus_temp.pci = chip->pci;
111d3af5
TI		 1729 bus_temp.ops.command = azx_send_cmd;
1730 bus_temp.ops.get_response = azx_get_response;
176d5335 1731 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1732 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1733#ifdef CONFIG_PM
11cd41b8 1734 bus_temp.power_save = &power_save;
cb53c626
TI		 1735 bus_temp.ops.pm_notify = azx_power_notify;
1736#endif
1d1a4564
TI		 1737#ifdef CONFIG_SND_HDA_DSP_LOADER
1738 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1739 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1740 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1741#endif
1da177e4 1742
d01ce99f
TI		 1743 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1744 if (err < 0)
1da177e4
LT		 1745 return err;
1746
9477c58e 1747 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1748 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1749 chip->bus->needs_damn_long_delay = 1;
9477c58e 1750 }
dc9c8e21 1751
34c25350 1752 codecs = 0;
2f5983f2
TI		 1753 max_slots = azx_max_codecs[chip->driver_type];
1754 if (!max_slots)
7445dfc1 1755 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1756
1757 /* First try to probe all given codec slots */
1758 for (c = 0; c < max_slots; c++) {
f1eaaeec 1759 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1760 if (probe_codec(chip, c) < 0) {
1761 /* Some BIOSen give you wrong codec addresses
1762 * that don't exist
1763 */
4abc1cc2 1764 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1765 "%s: Codec #%d probe error; "
1766 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1767 chip->codec_mask &= ~(1 << c);
1768 /* More badly, accessing to a non-existing
1769 * codec often screws up the controller chip,
2448158e 1770 * and disturbs the further communications.
6ce4a3bc
TI		 1771 * Thus if an error occurs during probing,
1772 * better to reset the controller chip to
1773 * get back to the sanity state.
1774 */
1775 azx_stop_chip(chip);
cd508fe5 1776 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1777 }
1778 }
1779 }
1780
d507cd66
TI		 1781 /* AMD chipsets often cause the communication stalls upon certain
1782 * sequence like the pin-detection. It seems that forcing the synced
1783 * access works around the stall. Grrr...
1784 */
9477c58e 1785 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1786 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1787 pci_name(chip->pci));
d507cd66
TI		 1788 chip->bus->sync_write = 1;
1789 chip->bus->allow_bus_reset = 1;
1790 }
1791
6ce4a3bc 1792 /* Then create codec instances */
34c25350 1793 for (c = 0; c < max_slots; c++) {
f1eaaeec 1794 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1795 struct hda_codec *codec;
a1e21c90 1796 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1797 if (err < 0)
1798 continue;
26a6cb6c 1799 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1800 codec->beep_mode = chip->beep_mode;
1da177e4 1801 codecs++;
19a982b6
TI		 1802 }
1803 }
1804 if (!codecs) {
445a51b3 1805 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1806 return -ENXIO;
1807 }
a1e21c90
TI		 1808 return 0;
1809}
1da177e4 1810
a1e21c90 1811/* configure each codec instance */
e23e7a14 1812static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1813{
1814 struct hda_codec *codec;
1815 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1816 snd_hda_codec_configure(codec);
1817 }
1da177e4
LT		 1818 return 0;
1819}
1820
1821
1822/*
1823 * PCM support
1824 */
1825
1826/* assign a stream for the PCM */
ef18bede
WF		 1827static inline struct azx_dev *
1828azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1829{
07e4ca50 1830 int dev, i, nums;
ef18bede 1831 struct azx_dev *res = NULL;
d5cf9911
TI		 1832 /* make a non-zero unique key for the substream */
1833 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1834 (substream->stream + 1);
ef18bede
WF		 1835
1836 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1837 dev = chip->playback_index_offset;
1838 nums = chip->playback_streams;
1839 } else {
1840 dev = chip->capture_index_offset;
1841 nums = chip->capture_streams;
1842 }
eb49faa6
TI		 1843 for (i = 0; i < nums; i++, dev++) {
1844 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1845 dsp_lock(azx_dev);
1846 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1847 res = azx_dev;
1848 if (res->assigned_key == key) {
1849 res->opened = 1;
1850 res->assigned_key = key;
1851 dsp_unlock(azx_dev);
1852 return azx_dev;
1853 }
1da177e4 1854 }
eb49faa6
TI		 1855 dsp_unlock(azx_dev);
1856 }
ef18bede 1857 if (res) {
eb49faa6 1858 dsp_lock(res);
ef18bede 1859 res->opened = 1;
d5cf9911 1860 res->assigned_key = key;
eb49faa6 1861 dsp_unlock(res);
ef18bede
WF		 1862 }
1863 return res;
1da177e4
LT		 1864}
1865
1866/* release the assigned stream */
a98f90fd 1867static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1868{
1869 azx_dev->opened = 0;
1870}
1871
5d890f59
PLB		 1872static cycle_t azx_cc_read(const struct cyclecounter *cc)
1873{
1874 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1875 struct snd_pcm_substream *substream = azx_dev->substream;
1876 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1877 struct azx *chip = apcm->chip;
1878
1879 return azx_readl(chip, WALLCLK);
1880}
1881
1882static void azx_timecounter_init(struct snd_pcm_substream *substream,
1883 bool force, cycle_t last)
1884{
1885 struct azx_dev *azx_dev = get_azx_dev(substream);
1886 struct timecounter *tc = &azx_dev->azx_tc;
1887 struct cyclecounter *cc = &azx_dev->azx_cc;
1888 u64 nsec;
1889
1890 cc->read = azx_cc_read;
1891 cc->mask = CLOCKSOURCE_MASK(32);
1892
1893 /*
1894 * Converting from 24 MHz to ns means applying a 125/3 factor.
1895 * To avoid any saturation issues in intermediate operations,
1896 * the 125 factor is applied first. The division is applied
1897 * last after reading the timecounter value.
1898 * Applying the 1/3 factor as part of the multiplication
1899 * requires at least 20 bits for a decent precision, however
1900 * overflows occur after about 4 hours or less, not a option.
1901 */
1902
1903 cc->mult = 125; /* saturation after 195 years */
1904 cc->shift = 0;
1905
1906 nsec = 0; /* audio time is elapsed time since trigger */
1907 timecounter_init(tc, cc, nsec);
1908 if (force)
1909 /*
1910 * force timecounter to use predefined value,
1911 * used for synchronized starts
1912 */
1913 tc->cycle_last = last;
1914}
1915
ae03bbb8 1916static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1917 u64 nsec)
1918{
1919 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1920 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1921 u64 codec_frames, codec_nsecs;
1922
1923 if (!hinfo->ops.get_delay)
1924 return nsec;
1925
1926 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1927 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1928 substream->runtime->rate);
1929
ae03bbb8
DR		 1930 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1931 return nsec + codec_nsecs;
1932
78daea29
DR		 1933 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1934}
1935
5d890f59
PLB		 1936static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1937 struct timespec *ts)
1938{
1939 struct azx_dev *azx_dev = get_azx_dev(substream);
1940 u64 nsec;
1941
1942 nsec = timecounter_read(&azx_dev->azx_tc);
1943 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1944 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1945
1946 *ts = ns_to_timespec(nsec);
1947
1948 return 0;
1949}
1950
a98f90fd 1951static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1952 .info = (SNDRV_PCM_INFO_MMAP |
1953 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1954 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1955 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1956 /* No full-resume yet implemented */
1957 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1958 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1959 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1960 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1961 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1962 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1963 .rates = SNDRV_PCM_RATE_48000,
1964 .rate_min = 48000,
1965 .rate_max = 48000,
1966 .channels_min = 2,
1967 .channels_max = 2,
1968 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1969 .period_bytes_min = 128,
1970 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1971 .periods_min = 2,
1972 .periods_max = AZX_MAX_FRAG,
1973 .fifo_size = 0,
1974};
1975
a98f90fd 1976static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1977{
1978 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1979 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1980 struct azx *chip = apcm->chip;
1981 struct azx_dev *azx_dev;
1982 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1983 unsigned long flags;
1984 int err;
2ae66c26 1985 int buff_step;
1da177e4 1986
62932df8 1987 mutex_lock(&chip->open_mutex);
ef18bede 1988 azx_dev = azx_assign_device(chip, substream);
1da177e4 1989 if (azx_dev == NULL) {
62932df8 1990 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1991 return -EBUSY;
1992 }
1993 runtime->hw = azx_pcm_hw;
1994 runtime->hw.channels_min = hinfo->channels_min;
1995 runtime->hw.channels_max = hinfo->channels_max;
1996 runtime->hw.formats = hinfo->formats;
1997 runtime->hw.rates = hinfo->rates;
1998 snd_pcm_limit_hw_rates(runtime);
1999 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 2000
2001 /* avoid wrap-around with wall-clock */
2002 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2003 20,
2004 178000000);
2005
52409aa6 2006 if (chip->align_buffer_size)
2ae66c26
PLB		 2007 /* constrain buffer sizes to be multiple of 128
2008 bytes. This is more efficient in terms of memory
2009 access but isn't required by the HDA spec and
2010 prevents users from specifying exact period/buffer
2011 sizes. For example for 44.1kHz, a period size set
2012 to 20ms will be rounded to 19.59ms. */
2013 buff_step = 128;
2014 else
2015 /* Don't enforce steps on buffer sizes, still need to
2016 be multiple of 4 bytes (HDA spec). Tested on Intel
2017 HDA controllers, may not work on all devices where
2018 option needs to be disabled */
2019 buff_step = 4;
2020
5f1545bc 2021 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2022 buff_step);
5f1545bc 2023 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2024 buff_step);
b4a91cf0 2025 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2026 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2027 if (err < 0) {
1da177e4 2028 azx_release_device(azx_dev);
cb53c626 2029 snd_hda_power_down(apcm->codec);
62932df8 2030 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2031 return err;
2032 }
70d321e6 2033 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2034 /* sanity check */
2035 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2036 snd_BUG_ON(!runtime->hw.channels_max) ||
2037 snd_BUG_ON(!runtime->hw.formats) ||
2038 snd_BUG_ON(!runtime->hw.rates)) {
2039 azx_release_device(azx_dev);
2040 hinfo->ops.close(hinfo, apcm->codec, substream);
2041 snd_hda_power_down(apcm->codec);
2042 mutex_unlock(&chip->open_mutex);
2043 return -EINVAL;
2044 }
5d890f59
PLB		 2045
2046 /* disable WALLCLOCK timestamps for capture streams
2047 until we figure out how to handle digital inputs */
2048 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2049 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2050
1da177e4
LT		 2051 spin_lock_irqsave(&chip->reg_lock, flags);
2052 azx_dev->substream = substream;
2053 azx_dev->running = 0;
2054 spin_unlock_irqrestore(&chip->reg_lock, flags);
2055
2056 runtime->private_data = azx_dev;
850f0e52 2057 snd_pcm_set_sync(substream);
62932df8 2058 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2059 return 0;
2060}
2061
a98f90fd 2062static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2063{
2064 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2065 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2066 struct azx *chip = apcm->chip;
2067 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2068 unsigned long flags;
2069
62932df8 2070 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2071 spin_lock_irqsave(&chip->reg_lock, flags);
2072 azx_dev->substream = NULL;
2073 azx_dev->running = 0;
2074 spin_unlock_irqrestore(&chip->reg_lock, flags);
2075 azx_release_device(azx_dev);
2076 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2077 snd_hda_power_down(apcm->codec);
62932df8 2078 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2079 return 0;
2080}
2081
d01ce99f
TI		 2082static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2083 struct snd_pcm_hw_params *hw_params)
1da177e4 2084{
27fe48d9
TI		 2085 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2086 struct azx *chip = apcm->chip;
97b71c94 2087 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2088 int ret;
97b71c94 2089
eb49faa6
TI		 2090 dsp_lock(azx_dev);
2091 if (dsp_is_locked(azx_dev)) {
2092 ret = -EBUSY;
2093 goto unlock;
2094 }
2095
9ddf1aeb 2096 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2097 azx_dev->bufsize = 0;
2098 azx_dev->period_bytes = 0;
2099 azx_dev->format_val = 0;
27fe48d9 2100 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2101 params_buffer_bytes(hw_params));
27fe48d9 2102 if (ret < 0)
eb49faa6 2103 goto unlock;
9ddf1aeb 2104 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2105 unlock:
2106 dsp_unlock(azx_dev);
27fe48d9 2107 return ret;
1da177e4
LT		 2108}
2109
a98f90fd 2110static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2111{
2112 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2113 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2114 struct azx *chip = apcm->chip;
1da177e4
LT		 2115 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2116
2117 /* reset BDL address */
eb49faa6
TI		 2118 dsp_lock(azx_dev);
2119 if (!dsp_is_locked(azx_dev)) {
2120 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2121 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2122 azx_sd_writel(azx_dev, SD_CTL, 0);
2123 azx_dev->bufsize = 0;
2124 azx_dev->period_bytes = 0;
2125 azx_dev->format_val = 0;
2126 }
1da177e4 2127
eb541337 2128 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2129
9ddf1aeb 2130 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2131 azx_dev->prepared = 0;
2132 dsp_unlock(azx_dev);
1da177e4
LT		 2133 return snd_pcm_lib_free_pages(substream);
2134}
2135
a98f90fd 2136static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2137{
2138 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2139 struct azx *chip = apcm->chip;
2140 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2141 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2142 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2143 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2144 int err;
7c935976
SW		 2145 struct hda_spdif_out *spdif =
2146 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2147 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2148
eb49faa6
TI		 2149 dsp_lock(azx_dev);
2150 if (dsp_is_locked(azx_dev)) {
2151 err = -EBUSY;
2152 goto unlock;
2153 }
2154
fa00e046 2155 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2156 format_val = snd_hda_calc_stream_format(runtime->rate,
2157 runtime->channels,
2158 runtime->format,
32c168c8 2159 hinfo->maxbps,
7c935976 2160 ctls);
97b71c94 2161 if (!format_val) {
d01ce99f 2162 snd_printk(KERN_ERR SFX
445a51b3
DB		 2163 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2164 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2165 err = -EINVAL;
2166 goto unlock;
1da177e4
LT		 2167 }
2168
97b71c94
TI		 2169 bufsize = snd_pcm_lib_buffer_bytes(substream);
2170 period_bytes = snd_pcm_lib_period_bytes(substream);
2171
445a51b3
DB		 2172 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2173 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2174
2175 if (bufsize != azx_dev->bufsize ||
2176 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2177 format_val != azx_dev->format_val ||
2178 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2179 azx_dev->bufsize = bufsize;
2180 azx_dev->period_bytes = period_bytes;
2181 azx_dev->format_val = format_val;
915bf29e 2182 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2183 err = azx_setup_periods(chip, substream, azx_dev);
2184 if (err < 0)
eb49faa6 2185 goto unlock;
97b71c94
TI		 2186 }
2187
e5463720
JK		 2188 /* wallclk has 24Mhz clock source */
2189 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2190 runtime->rate) * 1000);
1da177e4
LT		 2191 azx_setup_controller(chip, azx_dev);
2192 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2193 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2194 else
2195 azx_dev->fifo_size = 0;
2196
62b7e5e0
TI		 2197 stream_tag = azx_dev->stream_tag;
2198 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2199 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2200 stream_tag > chip->capture_streams)
2201 stream_tag -= chip->capture_streams;
eb49faa6 2202 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2203 azx_dev->format_val, substream);
eb49faa6
TI		 2204
2205 unlock:
2206 if (!err)
2207 azx_dev->prepared = 1;
2208 dsp_unlock(azx_dev);
2209 return err;
1da177e4
LT		 2210}
2211
a98f90fd 2212static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2213{
2214 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2215 struct azx *chip = apcm->chip;
850f0e52
TI		 2216 struct azx_dev *azx_dev;
2217 struct snd_pcm_substream *s;
fa00e046 2218 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2219 int nwait, timeout;
1da177e4 2220
1a8506d4
TI		 2221 azx_dev = get_azx_dev(substream);
2222 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2223
eb49faa6
TI		 2224 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2225 return -EPIPE;
2226
1da177e4 2227 switch (cmd) {
fa00e046
JK		 2228 case SNDRV_PCM_TRIGGER_START:
2229 rstart = 1;
1da177e4
LT		 2230 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2231 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2232 start = 1;
1da177e4
LT		 2233 break;
2234 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2235 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2236 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2237 start = 0;
1da177e4
LT		 2238 break;
2239 default:
850f0e52
TI		 2240 return -EINVAL;
2241 }
2242
2243 snd_pcm_group_for_each_entry(s, substream) {
2244 if (s->pcm->card != substream->pcm->card)
2245 continue;
2246 azx_dev = get_azx_dev(s);
2247 sbits |= 1 << azx_dev->index;
2248 nsync++;
2249 snd_pcm_trigger_done(s, substream);
2250 }
2251
2252 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2253
2254 /* first, set SYNC bits of corresponding streams */
2255 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2256 azx_writel(chip, OLD_SSYNC,
2257 azx_readl(chip, OLD_SSYNC) | sbits);
2258 else
2259 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2260
850f0e52
TI		 2261 snd_pcm_group_for_each_entry(s, substream) {
2262 if (s->pcm->card != substream->pcm->card)
2263 continue;
2264 azx_dev = get_azx_dev(s);
e5463720
JK		 2265 if (start) {
2266 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2267 if (!rstart)
2268 azx_dev->start_wallclk -=
2269 azx_dev->period_wallclk;
850f0e52 2270 azx_stream_start(chip, azx_dev);
e5463720 2271 } else {
850f0e52 2272 azx_stream_stop(chip, azx_dev);
e5463720 2273 }
850f0e52 2274 azx_dev->running = start;
1da177e4
LT		 2275 }
2276 spin_unlock(&chip->reg_lock);
850f0e52 2277 if (start) {
850f0e52
TI		 2278 /* wait until all FIFOs get ready */
2279 for (timeout = 5000; timeout; timeout--) {
2280 nwait = 0;
2281 snd_pcm_group_for_each_entry(s, substream) {
2282 if (s->pcm->card != substream->pcm->card)
2283 continue;
2284 azx_dev = get_azx_dev(s);
2285 if (!(azx_sd_readb(azx_dev, SD_STS) &
2286 SD_STS_FIFO_READY))
2287 nwait++;
2288 }
2289 if (!nwait)
2290 break;
2291 cpu_relax();
2292 }
2293 } else {
2294 /* wait until all RUN bits are cleared */
2295 for (timeout = 5000; timeout; timeout--) {
2296 nwait = 0;
2297 snd_pcm_group_for_each_entry(s, substream) {
2298 if (s->pcm->card != substream->pcm->card)
2299 continue;
2300 azx_dev = get_azx_dev(s);
2301 if (azx_sd_readb(azx_dev, SD_CTL) &
2302 SD_CTL_DMA_START)
2303 nwait++;
2304 }
2305 if (!nwait)
2306 break;
2307 cpu_relax();
2308 }
1da177e4 2309 }
172d3b20
PLB		 2310 spin_lock(&chip->reg_lock);
2311 /* reset SYNC bits */
2312 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2313 azx_writel(chip, OLD_SSYNC,
2314 azx_readl(chip, OLD_SSYNC) & ~sbits);
2315 else
2316 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2317 if (start) {
2318 azx_timecounter_init(substream, 0, 0);
2319 if (nsync > 1) {
2320 cycle_t cycle_last;
2321
2322 /* same start cycle for master and group */
2323 azx_dev = get_azx_dev(substream);
2324 cycle_last = azx_dev->azx_tc.cycle_last;
2325
2326 snd_pcm_group_for_each_entry(s, substream) {
2327 if (s->pcm->card != substream->pcm->card)
2328 continue;
2329 azx_timecounter_init(s, 1, cycle_last);
2330 }
2331 }
2332 }
172d3b20 2333 spin_unlock(&chip->reg_lock);
850f0e52 2334 return 0;
1da177e4
LT		 2335}
2336
0e153474
JC		 2337/* get the current DMA position with correction on VIA chips */
2338static unsigned int azx_via_get_position(struct azx *chip,
2339 struct azx_dev *azx_dev)
2340{
2341 unsigned int link_pos, mini_pos, bound_pos;
2342 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2343 unsigned int fifo_size;
2344
2345 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2346 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2347 /* Playback, no problem using link position */
2348 return link_pos;
2349 }
2350
2351 /* Capture */
2352 /* For new chipset,
2353 * use mod to get the DMA position just like old chipset
2354 */
2355 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2356 mod_dma_pos %= azx_dev->period_bytes;
2357
2358 /* azx_dev->fifo_size can't get FIFO size of in stream.
2359 * Get from base address + offset.
2360 */
2361 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2362
2363 if (azx_dev->insufficient) {
2364 /* Link position never gather than FIFO size */
2365 if (link_pos <= fifo_size)
2366 return 0;
2367
2368 azx_dev->insufficient = 0;
2369 }
2370
2371 if (link_pos <= fifo_size)
2372 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2373 else
2374 mini_pos = link_pos - fifo_size;
2375
2376 /* Find nearest previous boudary */
2377 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2378 mod_link_pos = link_pos % azx_dev->period_bytes;
2379 if (mod_link_pos >= fifo_size)
2380 bound_pos = link_pos - mod_link_pos;
2381 else if (mod_dma_pos >= mod_mini_pos)
2382 bound_pos = mini_pos - mod_mini_pos;
2383 else {
2384 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2385 if (bound_pos >= azx_dev->bufsize)
2386 bound_pos = 0;
2387 }
2388
2389 /* Calculate real DMA position we want */
2390 return bound_pos + mod_dma_pos;
2391}
2392
9ad593f6 2393static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2394 struct azx_dev *azx_dev,
2395 bool with_check)
1da177e4 2396{
21229613
TI		 2397 struct snd_pcm_substream *substream = azx_dev->substream;
2398 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2399 unsigned int pos;
21229613
TI		 2400 int stream = substream->stream;
2401 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2402 int delay = 0;
1da177e4 2403
4cb36310
DH		 2404 switch (chip->position_fix[stream]) {
2405 case POS_FIX_LPIB:
2406 /* read LPIB */
2407 pos = azx_sd_readl(azx_dev, SD_LPIB);
2408 break;
2409 case POS_FIX_VIACOMBO:
0e153474 2410 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2411 break;
2412 default:
2413 /* use the position buffer */
2414 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2415 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2416 if (!pos || pos == (u32)-1) {
2417 printk(KERN_WARNING
2418 "hda-intel: Invalid position buffer, "
2419 "using LPIB read method instead.\n");
2420 chip->position_fix[stream] = POS_FIX_LPIB;
2421 pos = azx_sd_readl(azx_dev, SD_LPIB);
2422 } else
2423 chip->position_fix[stream] = POS_FIX_POSBUF;
2424 }
2425 break;
c74db86b 2426 }
4cb36310 2427
1da177e4
LT		 2428 if (pos >= azx_dev->bufsize)
2429 pos = 0;
90accc58
PLB		 2430
2431 /* calculate runtime delay from LPIB */
21229613 2432 if (substream->runtime &&
90accc58
PLB		 2433 chip->position_fix[stream] == POS_FIX_POSBUF &&
2434 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2435 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2436 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2437 delay = pos - lpib_pos;
2438 else
2439 delay = lpib_pos - pos;
2440 if (delay < 0)
2441 delay += azx_dev->bufsize;
2442 if (delay >= azx_dev->period_bytes) {
1f04661f 2443 snd_printk(KERN_WARNING SFX
445a51b3 2444 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2445 "disabling LPIB delay counting\n",
445a51b3 2446 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2447 delay = 0;
2448 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2449 }
21229613 2450 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2451 }
21229613
TI		 2452
2453 if (substream->runtime) {
2454 if (hinfo->ops.get_delay)
2455 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2456 substream);
2457 substream->runtime->delay = delay;
2458 }
2459
1a8506d4 2460 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2461 return pos;
2462}
2463
2464static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2465{
2466 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2467 struct azx *chip = apcm->chip;
2468 struct azx_dev *azx_dev = get_azx_dev(substream);
2469 return bytes_to_frames(substream->runtime,
798cb7e8 2470 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2471}
2472
2473/*
2474 * Check whether the current DMA position is acceptable for updating
2475 * periods. Returns non-zero if it's OK.
2476 *
2477 * Many HD-audio controllers appear pretty inaccurate about
2478 * the update-IRQ timing. The IRQ is issued before actually the
2479 * data is processed. So, we need to process it afterwords in a
2480 * workqueue.
2481 */
2482static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2483{
e5463720 2484 u32 wallclk;
9ad593f6
TI		 2485 unsigned int pos;
2486
f48f606d
JK		 2487 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2488 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2489 return -1; /* bogus (too early) interrupt */
fa00e046 2490
798cb7e8 2491 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2492
d6d8bf54
TI		 2493 if (WARN_ONCE(!azx_dev->period_bytes,
2494 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2495 return -1; /* this shouldn't happen! */
edb39935 2496 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2497 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2498 /* NG - it's below the first next period boundary */
2499 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2500 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2501 return 1; /* OK, it's fine */
2502}
2503
2504/*
2505 * The work for pending PCM period updates.
2506 */
2507static void azx_irq_pending_work(struct work_struct *work)
2508{
2509 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2510 int i, pending, ok;
9ad593f6 2511
a6a950a8
TI		 2512 if (!chip->irq_pending_warned) {
2513 printk(KERN_WARNING
2514 "hda-intel: IRQ timing workaround is activated "
2515 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2516 chip->card->number);
2517 chip->irq_pending_warned = 1;
2518 }
2519
9ad593f6
TI		 2520 for (;;) {
2521 pending = 0;
2522 spin_lock_irq(&chip->reg_lock);
2523 for (i = 0; i < chip->num_streams; i++) {
2524 struct azx_dev *azx_dev = &chip->azx_dev[i];
2525 if (!azx_dev->irq_pending ||
2526 !azx_dev->substream ||
2527 !azx_dev->running)
2528 continue;
e5463720
JK		 2529 ok = azx_position_ok(chip, azx_dev);
2530 if (ok > 0) {
9ad593f6
TI		 2531 azx_dev->irq_pending = 0;
2532 spin_unlock(&chip->reg_lock);
2533 snd_pcm_period_elapsed(azx_dev->substream);
2534 spin_lock(&chip->reg_lock);
e5463720
JK		 2535 } else if (ok < 0) {
2536 pending = 0; /* too early */
9ad593f6
TI		 2537 } else
2538 pending++;
2539 }
2540 spin_unlock_irq(&chip->reg_lock);
2541 if (!pending)
2542 return;
08af495f 2543 msleep(1);
9ad593f6
TI		 2544 }
2545}
2546
2547/* clear irq_pending flags and assure no on-going workq */
2548static void azx_clear_irq_pending(struct azx *chip)
2549{
2550 int i;
2551
2552 spin_lock_irq(&chip->reg_lock);
2553 for (i = 0; i < chip->num_streams; i++)
2554 chip->azx_dev[i].irq_pending = 0;
2555 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2556}
2557
27fe48d9
TI		 2558#ifdef CONFIG_X86
2559static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2560 struct vm_area_struct *area)
2561{
2562 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2563 struct azx *chip = apcm->chip;
2564 if (!azx_snoop(chip))
2565 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2566 return snd_pcm_lib_default_mmap(substream, area);
2567}
2568#else
2569#define azx_pcm_mmap NULL
2570#endif
2571
a98f90fd 2572static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2573 .open = azx_pcm_open,
2574 .close = azx_pcm_close,
2575 .ioctl = snd_pcm_lib_ioctl,
2576 .hw_params = azx_pcm_hw_params,
2577 .hw_free = azx_pcm_hw_free,
2578 .prepare = azx_pcm_prepare,
2579 .trigger = azx_pcm_trigger,
2580 .pointer = azx_pcm_pointer,
5d890f59 2581 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2582 .mmap = azx_pcm_mmap,
4ce107b9 2583 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2584};
2585
a98f90fd 2586static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2587{
176d5335
TI		 2588 struct azx_pcm *apcm = pcm->private_data;
2589 if (apcm) {
01b65bfb 2590 list_del(&apcm->list);
176d5335
TI		 2591 kfree(apcm);
2592 }
1da177e4
LT		 2593}
2594
acfa634f
TI		 2595#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2596
176d5335 2597static int
33fa35ed
TI		 2598azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2599 struct hda_pcm *cpcm)
1da177e4 2600{
33fa35ed 2601 struct azx *chip = bus->private_data;
a98f90fd 2602 struct snd_pcm *pcm;
1da177e4 2603 struct azx_pcm *apcm;
176d5335 2604 int pcm_dev = cpcm->device;
acfa634f 2605 unsigned int size;
176d5335 2606 int s, err;
1da177e4 2607
01b65bfb
TI		 2608 list_for_each_entry(apcm, &chip->pcm_list, list) {
2609 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2610 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2611 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2612 return -EBUSY;
2613 }
176d5335
TI		 2614 }
2615 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2616 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2617 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2618 &pcm);
2619 if (err < 0)
2620 return err;
18cb7109 2621 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2622 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2623 if (apcm == NULL)
2624 return -ENOMEM;
2625 apcm->chip = chip;
01b65bfb 2626 apcm->pcm = pcm;
1da177e4 2627 apcm->codec = codec;
1da177e4
LT		 2628 pcm->private_data = apcm;
2629 pcm->private_free = azx_pcm_free;
176d5335
TI		 2630 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2631 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2632 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2633 cpcm->pcm = pcm;
2634 for (s = 0; s < 2; s++) {
2635 apcm->hinfo[s] = &cpcm->stream[s];
2636 if (cpcm->stream[s].substreams)
2637 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2638 }
2639 /* buffer pre-allocation */
acfa634f
TI		 2640 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2641 if (size > MAX_PREALLOC_SIZE)
2642 size = MAX_PREALLOC_SIZE;
4ce107b9 2643 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2644 snd_dma_pci_data(chip->pci),
acfa634f 2645 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2646 return 0;
2647}
2648
2649/*
2650 * mixer creation - all stuff is implemented in hda module
2651 */
e23e7a14 2652static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2653{
2654 return snd_hda_build_controls(chip->bus);
2655}
2656
2657
2658/*
2659 * initialize SD streams
2660 */
e23e7a14 2661static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2662{
2663 int i;
2664
2665 /* initialize each stream (aka device)
d01ce99f
TI		 2666 * assign the starting bdl address to each stream (device)
2667 * and initialize
1da177e4 2668 */
07e4ca50 2669 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2670 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2671 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2672 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2673 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2674 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2675 azx_dev->sd_int_sta_mask = 1 << i;
2676 /* stream tag: must be non-zero and unique */
2677 azx_dev->index = i;
2678 azx_dev->stream_tag = i + 1;
2679 }
2680
2681 return 0;
2682}
2683
68e7fffc
TI		 2684static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2685{
437a5a46
TI		 2686 if (request_irq(chip->pci->irq, azx_interrupt,
2687 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2688 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2689 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2690 "disabling device\n", chip->pci->irq);
2691 if (do_disconnect)
2692 snd_card_disconnect(chip->card);
2693 return -1;
2694 }
2695 chip->irq = chip->pci->irq;
69e13418 2696 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2697 return 0;
2698}
2699
1da177e4 2700
cb53c626
TI		 2701static void azx_stop_chip(struct azx *chip)
2702{
95e99fda 2703 if (!chip->initialized)
cb53c626
TI		 2704 return;
2705
2706 /* disable interrupts */
2707 azx_int_disable(chip);
2708 azx_int_clear(chip);
2709
2710 /* disable CORB/RIRB */
2711 azx_free_cmd_io(chip);
2712
2713 /* disable position buffer */
2714 azx_writel(chip, DPLBASE, 0);
2715 azx_writel(chip, DPUBASE, 0);
2716
2717 chip->initialized = 0;
2718}
2719
1d1a4564
TI		 2720#ifdef CONFIG_SND_HDA_DSP_LOADER
2721/*
2722 * DSP loading code (e.g. for CA0132)
2723 */
2724
2725/* use the first stream for loading DSP */
2726static struct azx_dev *
2727azx_get_dsp_loader_dev(struct azx *chip)
2728{
2729 return &chip->azx_dev[chip->playback_index_offset];
2730}
2731
2732static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2733 unsigned int byte_size,
2734 struct snd_dma_buffer *bufp)
2735{
2736 u32 *bdl;
2737 struct azx *chip = bus->private_data;
2738 struct azx_dev *azx_dev;
2739 int err;
2740
eb49faa6
TI		 2741 azx_dev = azx_get_dsp_loader_dev(chip);
2742
2743 dsp_lock(azx_dev);
2744 spin_lock_irq(&chip->reg_lock);
2745 if (azx_dev->running || azx_dev->locked) {
2746 spin_unlock_irq(&chip->reg_lock);
2747 err = -EBUSY;
2748 goto unlock;
2749 }
2750 azx_dev->prepared = 0;
2751 chip->saved_azx_dev = *azx_dev;
2752 azx_dev->locked = 1;
2753 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2754
2755 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2756 snd_dma_pci_data(chip->pci),
2757 byte_size, bufp);
2758 if (err < 0)
eb49faa6 2759 goto err_alloc;
1d1a4564 2760
b3667bd7 2761 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2762 azx_dev->bufsize = byte_size;
2763 azx_dev->period_bytes = byte_size;
2764 azx_dev->format_val = format;
2765
2766 azx_stream_reset(chip, azx_dev);
2767
2768 /* reset BDL address */
2769 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2770 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2771
2772 azx_dev->frags = 0;
2773 bdl = (u32 *)azx_dev->bdl.area;
2774 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2775 if (err < 0)
2776 goto error;
2777
2778 azx_setup_controller(chip, azx_dev);
eb49faa6 2779 dsp_unlock(azx_dev);
1d1a4564
TI		 2780 return azx_dev->stream_tag;
2781
2782 error:
b3667bd7
TI		 2783 mark_pages_wc(chip, bufp, false);
2784 snd_dma_free_pages(bufp);
eb49faa6
TI		 2785 err_alloc:
2786 spin_lock_irq(&chip->reg_lock);
2787 if (azx_dev->opened)
2788 *azx_dev = chip->saved_azx_dev;
2789 azx_dev->locked = 0;
2790 spin_unlock_irq(&chip->reg_lock);
2791 unlock:
2792 dsp_unlock(azx_dev);
1d1a4564
TI		 2793 return err;
2794}
2795
2796static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2797{
2798 struct azx *chip = bus->private_data;
2799 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2800
2801 if (start)
2802 azx_stream_start(chip, azx_dev);
2803 else
2804 azx_stream_stop(chip, azx_dev);
2805 azx_dev->running = start;
2806}
2807
2808static void azx_load_dsp_cleanup(struct hda_bus *bus,
2809 struct snd_dma_buffer *dmab)
2810{
2811 struct azx *chip = bus->private_data;
2812 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2813
eb49faa6 2814 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2815 return;
2816
eb49faa6 2817 dsp_lock(azx_dev);
1d1a4564
TI		 2818 /* reset BDL address */
2819 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2820 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2821 azx_sd_writel(azx_dev, SD_CTL, 0);
2822 azx_dev->bufsize = 0;
2823 azx_dev->period_bytes = 0;
2824 azx_dev->format_val = 0;
2825
b3667bd7 2826 mark_pages_wc(chip, dmab, false);
1d1a4564 2827 snd_dma_free_pages(dmab);
b3667bd7 2828 dmab->area = NULL;
1d1a4564 2829
eb49faa6
TI		 2830 spin_lock_irq(&chip->reg_lock);
2831 if (azx_dev->opened)
2832 *azx_dev = chip->saved_azx_dev;
2833 azx_dev->locked = 0;
2834 spin_unlock_irq(&chip->reg_lock);
2835 dsp_unlock(azx_dev);
1d1a4564
TI		 2836}
2837#endif /* CONFIG_SND_HDA_DSP_LOADER */
2838
83012a7c 2839#ifdef CONFIG_PM
cb53c626 2840/* power-up/down the controller */
68467f51 2841static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2842{
33fa35ed 2843 struct azx *chip = bus->private_data;
cb53c626 2844
2ea3c6a2
TI		 2845 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2846 return;
2847
68467f51 2848 if (power_up)
b8dfc462
ML		 2849 pm_runtime_get_sync(&chip->pci->dev);
2850 else
2851 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2852}
65fcd41d
TI		 2853
2854static DEFINE_MUTEX(card_list_lock);
2855static LIST_HEAD(card_list);
2856
2857static void azx_add_card_list(struct azx *chip)
2858{
2859 mutex_lock(&card_list_lock);
2860 list_add(&chip->list, &card_list);
2861 mutex_unlock(&card_list_lock);
2862}
2863
2864static void azx_del_card_list(struct azx *chip)
2865{
2866 mutex_lock(&card_list_lock);
2867 list_del_init(&chip->list);
2868 mutex_unlock(&card_list_lock);
2869}
2870
2871/* trigger power-save check at writing parameter */
2872static int param_set_xint(const char *val, const struct kernel_param *kp)
2873{
2874 struct azx *chip;
2875 struct hda_codec *c;
2876 int prev = power_save;
2877 int ret = param_set_int(val, kp);
2878
2879 if (ret || prev == power_save)
2880 return ret;
2881
2882 mutex_lock(&card_list_lock);
2883 list_for_each_entry(chip, &card_list, list) {
2884 if (!chip->bus || chip->disabled)
2885 continue;
2886 list_for_each_entry(c, &chip->bus->codec_list, list)
2887 snd_hda_power_sync(c);
2888 }
2889 mutex_unlock(&card_list_lock);
2890 return 0;
2891}
2892#else
2893#define azx_add_card_list(chip) /* NOP */
2894#define azx_del_card_list(chip) /* NOP */
83012a7c 2895#endif /* CONFIG_PM */
5c0b9bec 2896
7ccbde57 2897#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2898/*
2899 * power management
2900 */
68cb2b55 2901static int azx_suspend(struct device *dev)
1da177e4 2902{
68cb2b55
TI		 2903 struct pci_dev *pci = to_pci_dev(dev);
2904 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2905 struct azx *chip = card->private_data;
01b65bfb 2906 struct azx_pcm *p;
1da177e4 2907
c5c21523
TI		 2908 if (chip->disabled)
2909 return 0;
2910
421a1252 2911 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2912 azx_clear_irq_pending(chip);
01b65bfb
TI		 2913 list_for_each_entry(p, &chip->pcm_list, list)
2914 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2915 if (chip->initialized)
8dd78330 2916 snd_hda_suspend(chip->bus);
cb53c626 2917 azx_stop_chip(chip);
7295b264 2918 azx_enter_link_reset(chip);
30b35399 2919 if (chip->irq >= 0) {
43001c95 2920 free_irq(chip->irq, chip);
30b35399
TI		 2921 chip->irq = -1;
2922 }
68e7fffc 2923 if (chip->msi)
43001c95 2924 pci_disable_msi(chip->pci);
421a1252
TI		 2925 pci_disable_device(pci);
2926 pci_save_state(pci);
68cb2b55 2927 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2928 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2929 hda_display_power(false);
1da177e4
LT		 2930 return 0;
2931}
2932
68cb2b55 2933static int azx_resume(struct device *dev)
1da177e4 2934{
68cb2b55
TI		 2935 struct pci_dev *pci = to_pci_dev(dev);
2936 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2937 struct azx *chip = card->private_data;
1da177e4 2938
c5c21523
TI		 2939 if (chip->disabled)
2940 return 0;
2941
99a2008d
WX		 2942 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2943 hda_display_power(true);
d14a7e0b
TI		 2944 pci_set_power_state(pci, PCI_D0);
2945 pci_restore_state(pci);
30b35399
TI		 2946 if (pci_enable_device(pci) < 0) {
2947 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2948 "disabling device\n");
2949 snd_card_disconnect(card);
2950 return -EIO;
2951 }
2952 pci_set_master(pci);
68e7fffc
TI		 2953 if (chip->msi)
2954 if (pci_enable_msi(pci) < 0)
2955 chip->msi = 0;
2956 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2957 return -EIO;
cb53c626 2958 azx_init_pci(chip);
d804ad92 2959
7f30830b 2960 azx_init_chip(chip, 1);
d804ad92 2961
1da177e4 2962 snd_hda_resume(chip->bus);
421a1252 2963 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2964 return 0;
2965}
b8dfc462
ML		 2966#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2967
2968#ifdef CONFIG_PM_RUNTIME
2969static int azx_runtime_suspend(struct device *dev)
2970{
2971 struct snd_card *card = dev_get_drvdata(dev);
2972 struct azx *chip = card->private_data;
2973
b8dfc462 2974 azx_stop_chip(chip);
7295b264 2975 azx_enter_link_reset(chip);
b8dfc462 2976 azx_clear_irq_pending(chip);
99a2008d
WX		 2977 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2978 hda_display_power(false);
b8dfc462
ML		 2979 return 0;
2980}
2981
2982static int azx_runtime_resume(struct device *dev)
2983{
2984 struct snd_card *card = dev_get_drvdata(dev);
2985 struct azx *chip = card->private_data;
2986
99a2008d
WX		 2987 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2988 hda_display_power(true);
b8dfc462
ML		 2989 azx_init_pci(chip);
2990 azx_init_chip(chip, 1);
2991 return 0;
2992}
6eb827d2
TI		 2993
2994static int azx_runtime_idle(struct device *dev)
2995{
2996 struct snd_card *card = dev_get_drvdata(dev);
2997 struct azx *chip = card->private_data;
2998
2999 if (!power_save_controller ||
3000 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3001 return -EBUSY;
3002
3003 return 0;
3004}
3005
b8dfc462
ML		 3006#endif /* CONFIG_PM_RUNTIME */
3007
3008#ifdef CONFIG_PM
3009static const struct dev_pm_ops azx_pm = {
3010 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 3011 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 3012};
3013
68cb2b55
TI		 3014#define AZX_PM_OPS &azx_pm
3015#else
68cb2b55 3016#define AZX_PM_OPS NULL
b8dfc462 3017#endif /* CONFIG_PM */
1da177e4
LT		 3018
3019
0cbf0098
TI		 3020/*
3021 * reboot notifier for hang-up problem at power-down
3022 */
3023static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3024{
3025 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3026 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3027 azx_stop_chip(chip);
3028 return NOTIFY_OK;
3029}
3030
3031static void azx_notifier_register(struct azx *chip)
3032{
3033 chip->reboot_notifier.notifier_call = azx_halt;
3034 register_reboot_notifier(&chip->reboot_notifier);
3035}
3036
3037static void azx_notifier_unregister(struct azx *chip)
3038{
3039 if (chip->reboot_notifier.notifier_call)
3040 unregister_reboot_notifier(&chip->reboot_notifier);
3041}
3042
48c8b0eb 3043static int azx_probe_continue(struct azx *chip);
a82d51ed 3044
8393ec4a 3045#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3046static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3047
a82d51ed
TI		 3048static void azx_vs_set_state(struct pci_dev *pci,
3049 enum vga_switcheroo_state state)
3050{
3051 struct snd_card *card = pci_get_drvdata(pci);
3052 struct azx *chip = card->private_data;
3053 bool disabled;
3054
f4c482a4 3055 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3056 if (chip->init_failed)
3057 return;
3058
3059 disabled = (state == VGA_SWITCHEROO_OFF);
3060 if (chip->disabled == disabled)
3061 return;
3062
3063 if (!chip->bus) {
3064 chip->disabled = disabled;
3065 if (!disabled) {
3066 snd_printk(KERN_INFO SFX
3067 "%s: Start delayed initialization\n",
3068 pci_name(chip->pci));
5c90680e 3069 if (azx_probe_continue(chip) < 0) {
a82d51ed
TI		 3070 snd_printk(KERN_ERR SFX
3071 "%s: initialization error\n",
3072 pci_name(chip->pci));
3073 chip->init_failed = true;
3074 }
3075 }
3076 } else {
3077 snd_printk(KERN_INFO SFX
445a51b3
DB		 3078 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3079 disabled ? "Disabling" : "Enabling");
a82d51ed 3080 if (disabled) {
68cb2b55 3081 azx_suspend(&pci->dev);
a82d51ed 3082 chip->disabled = true;
128960a9 3083 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3084 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3085 pci_name(chip->pci));
a82d51ed
TI		 3086 } else {
3087 snd_hda_unlock_devices(chip->bus);
3088 chip->disabled = false;
68cb2b55 3089 azx_resume(&pci->dev);
a82d51ed
TI		 3090 }
3091 }
3092}
3093
3094static bool azx_vs_can_switch(struct pci_dev *pci)
3095{
3096 struct snd_card *card = pci_get_drvdata(pci);
3097 struct azx *chip = card->private_data;
3098
f4c482a4 3099 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3100 if (chip->init_failed)
3101 return false;
3102 if (chip->disabled || !chip->bus)
3103 return true;
3104 if (snd_hda_lock_devices(chip->bus))
3105 return false;
3106 snd_hda_unlock_devices(chip->bus);
3107 return true;
3108}
3109
e23e7a14 3110static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3111{
3112 struct pci_dev *p = get_bound_vga(chip->pci);
3113 if (p) {
3114 snd_printk(KERN_INFO SFX
3115 "%s: Handle VGA-switcheroo audio client\n",
3116 pci_name(chip->pci));
3117 chip->use_vga_switcheroo = 1;
3118 pci_dev_put(p);
3119 }
3120}
3121
3122static const struct vga_switcheroo_client_ops azx_vs_ops = {
3123 .set_gpu_state = azx_vs_set_state,
3124 .can_switch = azx_vs_can_switch,
3125};
3126
e23e7a14 3127static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3128{
128960a9
TI		 3129 int err;
3130
a82d51ed
TI		 3131 if (!chip->use_vga_switcheroo)
3132 return 0;
3133 /* FIXME: currently only handling DIS controller
3134 * is there any machine with two switchable HDMI audio controllers?
3135 */
128960a9 3136 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3137 VGA_SWITCHEROO_DIS,
3138 chip->bus != NULL);
128960a9
TI		 3139 if (err < 0)
3140 return err;
3141 chip->vga_switcheroo_registered = 1;
3142 return 0;
a82d51ed
TI		 3143}
3144#else
3145#define init_vga_switcheroo(chip) /* NOP */
3146#define register_vga_switcheroo(chip) 0
8393ec4a 3147#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3148#endif /* SUPPORT_VGA_SWITCHER */
3149
1da177e4
LT		 3150/*
3151 * destructor
3152 */
a98f90fd 3153static int azx_free(struct azx *chip)
1da177e4 3154{
c67e2228 3155 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 3156 int i;
3157
c67e2228
WX		 3158 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3159 && chip->running)
3160 pm_runtime_get_noresume(&pci->dev);
3161
65fcd41d
TI		 3162 azx_del_card_list(chip);
3163
0cbf0098
TI		 3164 azx_notifier_unregister(chip);
3165
f4c482a4 3166 chip->init_failed = 1; /* to be sure */
44728e97 3167 complete_all(&chip->probe_wait);
f4c482a4 3168
a82d51ed
TI		 3169 if (use_vga_switcheroo(chip)) {
3170 if (chip->disabled && chip->bus)
3171 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3172 if (chip->vga_switcheroo_registered)
3173 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3174 }
3175
ce43fbae 3176 if (chip->initialized) {
9ad593f6 3177 azx_clear_irq_pending(chip);
07e4ca50 3178 for (i = 0; i < chip->num_streams; i++)
1da177e4 3179 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3180 azx_stop_chip(chip);
1da177e4
LT		 3181 }
3182
f000fd80 3183 if (chip->irq >= 0)
1da177e4 3184 free_irq(chip->irq, (void*)chip);
68e7fffc 3185 if (chip->msi)
30b35399 3186 pci_disable_msi(chip->pci);
f079c25a
TI		 3187 if (chip->remap_addr)
3188 iounmap(chip->remap_addr);
1da177e4 3189
4ce107b9
TI		 3190 if (chip->azx_dev) {
3191 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3192 if (chip->azx_dev[i].bdl.area) {
3193 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3194 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3195 }
4ce107b9 3196 }
27fe48d9
TI		 3197 if (chip->rb.area) {
3198 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3199 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3200 }
3201 if (chip->posbuf.area) {
3202 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3203 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3204 }
a82d51ed
TI		 3205 if (chip->region_requested)
3206 pci_release_regions(chip->pci);
1da177e4 3207 pci_disable_device(chip->pci);
07e4ca50 3208 kfree(chip->azx_dev);
4918cdab
TI		 3209#ifdef CONFIG_SND_HDA_PATCH_LOADER
3210 if (chip->fw)
3211 release_firmware(chip->fw);
3212#endif
99a2008d
WX		 3213 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3214 hda_display_power(false);
3215 hda_i915_exit();
3216 }
1da177e4
LT		 3217 kfree(chip);
3218
3219 return 0;
3220}
3221
a98f90fd 3222static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3223{
3224 return azx_free(device->device_data);
3225}
3226
8393ec4a 3227#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3228/*
3229 * Check of disabled HDMI controller by vga-switcheroo
3230 */
e23e7a14 3231static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3232{
3233 struct pci_dev *p;
3234
3235 /* check only discrete GPU */
3236 switch (pci->vendor) {
3237 case PCI_VENDOR_ID_ATI:
3238 case PCI_VENDOR_ID_AMD:
3239 case PCI_VENDOR_ID_NVIDIA:
3240 if (pci->devfn == 1) {
3241 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3242 pci->bus->number, 0);
3243 if (p) {
3244 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3245 return p;
3246 pci_dev_put(p);
3247 }
3248 }
3249 break;
3250 }
3251 return NULL;
3252}
3253
e23e7a14 3254static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3255{
3256 bool vga_inactive = false;
3257 struct pci_dev *p = get_bound_vga(pci);
3258
3259 if (p) {
12b78a7f 3260 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3261 vga_inactive = true;
3262 pci_dev_put(p);
3263 }
3264 return vga_inactive;
3265}
8393ec4a 3266#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3267
3372a153
TI		 3268/*
3269 * white/black-listing for position_fix
3270 */
e23e7a14 3271static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3272 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3273 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3274 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3275 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3276 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3277 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3278 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3279 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3280 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3281 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3282 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3283 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3284 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3285 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3286 {}
3287};
3288
e23e7a14 3289static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3290{
3291 const struct snd_pci_quirk *q;
3292
c673ba1c 3293 switch (fix) {
1dac6695 3294 case POS_FIX_AUTO:
c673ba1c
TI		 3295 case POS_FIX_LPIB:
3296 case POS_FIX_POSBUF:
4cb36310 3297 case POS_FIX_VIACOMBO:
a6f2fd55 3298 case POS_FIX_COMBO:
c673ba1c
TI		 3299 return fix;
3300 }
3301
c673ba1c
TI		 3302 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3303 if (q) {
3304 printk(KERN_INFO
3305 "hda_intel: position_fix set to %d "
3306 "for device %04x:%04x\n",
3307 q->value, q->subvendor, q->subdevice);
3308 return q->value;
3372a153 3309 }
bdd9ef24
DH		 3310
3311 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3312 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3313 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3314 return POS_FIX_VIACOMBO;
9477c58e
TI		 3315 }
3316 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3317 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3318 return POS_FIX_LPIB;
bdd9ef24 3319 }
c673ba1c 3320 return POS_FIX_AUTO;
3372a153
TI		 3321}
3322
669ba27a
TI		 3323/*
3324 * black-lists for probe_mask
3325 */
e23e7a14 3326static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3327 /* Thinkpad often breaks the controller communication when accessing
3328 * to the non-working (or non-existing) modem codec slot.
3329 */
3330 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3331 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3332 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3333 /* broken BIOS */
3334 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3335 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3336 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3337 /* forced codec slots */
93574844 3338 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3339 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3340 /* WinFast VP200 H (Teradici) user reported broken communication */
3341 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3342 {}
3343};
3344
f1eaaeec
TI		 3345#define AZX_FORCE_CODEC_MASK 0x100
3346
e23e7a14 3347static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3348{
3349 const struct snd_pci_quirk *q;
3350
f1eaaeec
TI		 3351 chip->codec_probe_mask = probe_mask[dev];
3352 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3353 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3354 if (q) {
3355 printk(KERN_INFO
3356 "hda_intel: probe_mask set to 0x%x "
3357 "for device %04x:%04x\n",
3358 q->value, q->subvendor, q->subdevice);
f1eaaeec 3359 chip->codec_probe_mask = q->value;
669ba27a
TI		 3360 }
3361 }
f1eaaeec
TI		 3362
3363 /* check forced option */
3364 if (chip->codec_probe_mask != -1 &&
3365 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3366 chip->codec_mask = chip->codec_probe_mask & 0xff;
3367 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3368 chip->codec_mask);
3369 }
669ba27a
TI		 3370}
3371
4d8e22e0 3372/*
71623855 3373 * white/black-list for enable_msi
4d8e22e0 3374 */
e23e7a14 3375static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3376 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3377 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3378 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 3379 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3380 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3381 {}
3382};
3383
e23e7a14 3384static void check_msi(struct azx *chip)
4d8e22e0
TI		 3385{
3386 const struct snd_pci_quirk *q;
3387
71623855
TI		 3388 if (enable_msi >= 0) {
3389 chip->msi = !!enable_msi;
4d8e22e0 3390 return;
71623855
TI		 3391 }
3392 chip->msi = 1; /* enable MSI as default */
3393 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3394 if (q) {
3395 printk(KERN_INFO
3396 "hda_intel: msi for device %04x:%04x set to %d\n",
3397 q->subvendor, q->subdevice, q->value);
3398 chip->msi = q->value;
80c43ed7
TI		 3399 return;
3400 }
3401
3402 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3403 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3404 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3405 chip->msi = 0;
4d8e22e0
TI		 3406 }
3407}
3408
a1585d76 3409/* check the snoop mode availability */
e23e7a14 3410static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3411{
3412 bool snoop = chip->snoop;
3413
3414 switch (chip->driver_type) {
3415 case AZX_DRIVER_VIA:
3416 /* force to non-snoop mode for a new VIA controller
3417 * when BIOS is set
3418 */
3419 if (snoop) {
3420 u8 val;
3421 pci_read_config_byte(chip->pci, 0x42, &val);
3422 if (!(val & 0x80) && chip->pci->revision == 0x30)
3423 snoop = false;
3424 }
3425 break;
3426 case AZX_DRIVER_ATIHDMI_NS:
3427 /* new ATI HDMI requires non-snoop */
3428 snoop = false;
3429 break;
c1279f87
TI		 3430 case AZX_DRIVER_CTHDA:
3431 snoop = false;
3432 break;
a1585d76
TI		 3433 }
3434
3435 if (snoop != chip->snoop) {
445a51b3
DB		 3436 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3437 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3438 chip->snoop = snoop;
3439 }
3440}
669ba27a 3441
99a2008d
WX		 3442#ifdef CONFIG_SND_HDA_I915
3443static void azx_probe_work(struct work_struct *work)
3444{
3445 azx_probe_continue(container_of(work, struct azx, probe_work));
3446}
3447#endif
3448
1da177e4
LT		 3449/*
3450 * constructor
3451 */
e23e7a14
BP		 3452static int azx_create(struct snd_card *card, struct pci_dev *pci,
3453 int dev, unsigned int driver_caps,
3454 struct azx **rchip)
1da177e4 3455{
a98f90fd 3456 static struct snd_device_ops ops = {
1da177e4
LT		 3457 .dev_free = azx_dev_free,
3458 };
a82d51ed
TI		 3459 struct azx *chip;
3460 int err;
1da177e4
LT		 3461
3462 *rchip = NULL;
bcd72003 3463
927fc866
PM		 3464 err = pci_enable_device(pci);
3465 if (err < 0)
1da177e4
LT		 3466 return err;
3467
e560d8d8 3468 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3469 if (!chip) {
445a51b3 3470 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3471 pci_disable_device(pci);
3472 return -ENOMEM;
3473 }
3474
3475 spin_lock_init(&chip->reg_lock);
62932df8 3476 mutex_init(&chip->open_mutex);
1da177e4
LT		 3477 chip->card = card;
3478 chip->pci = pci;
3479 chip->irq = -1;
9477c58e
TI		 3480 chip->driver_caps = driver_caps;
3481 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3482 check_msi(chip);
555e219f 3483 chip->dev_index = dev;
9ad593f6 3484 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3485 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3486 INIT_LIST_HEAD(&chip->list);
a82d51ed 3487 init_vga_switcheroo(chip);
f4c482a4 3488 init_completion(&chip->probe_wait);
1da177e4 3489
beaffc39
SG		 3490 chip->position_fix[0] = chip->position_fix[1] =
3491 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3492 /* combo mode uses LPIB for playback */
3493 if (chip->position_fix[0] == POS_FIX_COMBO) {
3494 chip->position_fix[0] = POS_FIX_LPIB;
3495 chip->position_fix[1] = POS_FIX_AUTO;
3496 }
3497
5aba4f8e 3498 check_probe_mask(chip, dev);
3372a153 3499
27346166 3500 chip->single_cmd = single_cmd;
27fe48d9 3501 chip->snoop = hda_snoop;
a1585d76 3502 azx_check_snoop_available(chip);
c74db86b 3503
5c0d7bc1
TI		 3504 if (bdl_pos_adj[dev] < 0) {
3505 switch (chip->driver_type) {
0c6341ac 3506 case AZX_DRIVER_ICH:
32679f95 3507 case AZX_DRIVER_PCH:
0c6341ac 3508 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3509 break;
3510 default:
0c6341ac 3511 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3512 break;
3513 }
3514 }
3515
a82d51ed
TI		 3516 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3517 if (err < 0) {
445a51b3
DB		 3518 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3519 pci_name(chip->pci));
a82d51ed
TI		 3520 azx_free(chip);
3521 return err;
3522 }
3523
99a2008d
WX		 3524#ifdef CONFIG_SND_HDA_I915
3525 /* continue probing in work context as may trigger request module */
3526 INIT_WORK(&chip->probe_work, azx_probe_work);
3527#endif
3528
a82d51ed 3529 *rchip = chip;
99a2008d 3530
a82d51ed
TI		 3531 return 0;
3532}
3533
48c8b0eb 3534static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3535{
3536 int dev = chip->dev_index;
3537 struct pci_dev *pci = chip->pci;
3538 struct snd_card *card = chip->card;
3539 int i, err;
3540 unsigned short gcap;
3541
07e4ca50
TI		 3542#if BITS_PER_LONG != 64
3543 /* Fix up base address on ULI M5461 */
3544 if (chip->driver_type == AZX_DRIVER_ULI) {
3545 u16 tmp3;
3546 pci_read_config_word(pci, 0x40, &tmp3);
3547 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3548 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3549 }
3550#endif
3551
927fc866 3552 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3553 if (err < 0)
1da177e4 3554 return err;
a82d51ed 3555 chip->region_requested = 1;
1da177e4 3556
927fc866 3557 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3558 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3559 if (chip->remap_addr == NULL) {
445a51b3 3560 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3561 return -ENXIO;
1da177e4
LT		 3562 }
3563
68e7fffc
TI		 3564 if (chip->msi)
3565 if (pci_enable_msi(pci) < 0)
3566 chip->msi = 0;
7376d013 3567
a82d51ed
TI		 3568 if (azx_acquire_irq(chip, 0) < 0)
3569 return -EBUSY;
1da177e4
LT		 3570
3571 pci_set_master(pci);
3572 synchronize_irq(chip->irq);
3573
bcd72003 3574 gcap = azx_readw(chip, GCAP);
445a51b3 3575 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3576
dc4c2e6b 3577 /* disable SB600 64bit support for safety */
9477c58e 3578 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3579 struct pci_dev *p_smbus;
3580 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3581 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3582 NULL);
3583 if (p_smbus) {
3584 if (p_smbus->revision < 0x30)
3585 gcap &= ~ICH6_GCAP_64OK;
3586 pci_dev_put(p_smbus);
3587 }
3588 }
09240cf4 3589
9477c58e
TI		 3590 /* disable 64bit DMA address on some devices */
3591 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3592 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3593 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3594 }
396087ea 3595
2ae66c26 3596 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3597 if (align_buffer_size >= 0)
3598 chip->align_buffer_size = !!align_buffer_size;
3599 else {
3600 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3601 chip->align_buffer_size = 0;
3602 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3603 chip->align_buffer_size = 1;
3604 else
3605 chip->align_buffer_size = 1;
3606 }
2ae66c26 3607
cf7aaca8 3608 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3609 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3610 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3611 else {
e930438c
YH		 3612 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3613 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3614 }
cf7aaca8 3615
8b6ed8e7
TI		 3616 /* read number of streams from GCAP register instead of using
3617 * hardcoded value
3618 */
3619 chip->capture_streams = (gcap >> 8) & 0x0f;
3620 chip->playback_streams = (gcap >> 12) & 0x0f;
3621 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3622 /* gcap didn't give any info, switching to old method */
3623
3624 switch (chip->driver_type) {
3625 case AZX_DRIVER_ULI:
3626 chip->playback_streams = ULI_NUM_PLAYBACK;
3627 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3628 break;
3629 case AZX_DRIVER_ATIHDMI:
1815b34a 3630 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3631 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3632 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3633 break;
c4da29ca 3634 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3635 default:
3636 chip->playback_streams = ICH6_NUM_PLAYBACK;
3637 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3638 break;
3639 }
07e4ca50 3640 }
8b6ed8e7
TI		 3641 chip->capture_index_offset = 0;
3642 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3643 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3644 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3645 GFP_KERNEL);
927fc866 3646 if (!chip->azx_dev) {
445a51b3 3647 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3648 return -ENOMEM;
07e4ca50
TI		 3649 }
3650
4ce107b9 3651 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3652 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3653 /* allocate memory for the BDL for each stream */
3654 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3655 snd_dma_pci_data(chip->pci),
3656 BDL_SIZE, &chip->azx_dev[i].bdl);
3657 if (err < 0) {
445a51b3 3658 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3659 return -ENOMEM;
4ce107b9 3660 }
27fe48d9 3661 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3662 }
0be3b5d3 3663 /* allocate memory for the position buffer */
d01ce99f
TI		 3664 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3665 snd_dma_pci_data(chip->pci),
3666 chip->num_streams * 8, &chip->posbuf);
3667 if (err < 0) {
445a51b3 3668 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3669 return -ENOMEM;
1da177e4 3670 }
27fe48d9 3671 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3672 /* allocate CORB/RIRB */
81740861
TI		 3673 err = azx_alloc_cmd_io(chip);
3674 if (err < 0)
a82d51ed 3675 return err;
1da177e4
LT		 3676
3677 /* initialize streams */
3678 azx_init_stream(chip);
3679
3680 /* initialize chip */
cb53c626 3681 azx_init_pci(chip);
10e77dda 3682 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3683
3684 /* codec detection */
927fc866 3685 if (!chip->codec_mask) {
445a51b3 3686 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3687 return -ENODEV;
1da177e4
LT		 3688 }
3689
07e4ca50 3690 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3691 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3692 sizeof(card->shortname));
3693 snprintf(card->longname, sizeof(card->longname),
3694 "%s at 0x%lx irq %i",
3695 card->shortname, chip->addr, chip->irq);
07e4ca50 3696
1da177e4 3697 return 0;
1da177e4
LT		 3698}
3699
cb53c626
TI		 3700static void power_down_all_codecs(struct azx *chip)
3701{
83012a7c 3702#ifdef CONFIG_PM
cb53c626
TI		 3703 /* The codecs were powered up in snd_hda_codec_new().
3704 * Now all initialization done, so turn them down if possible
3705 */
3706 struct hda_codec *codec;
3707 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3708 snd_hda_power_down(codec);
3709 }
3710#endif
3711}
3712
97c6a3d1 3713#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3714/* callback from request_firmware_nowait() */
3715static void azx_firmware_cb(const struct firmware *fw, void *context)
3716{
3717 struct snd_card *card = context;
3718 struct azx *chip = card->private_data;
3719 struct pci_dev *pci = chip->pci;
3720
3721 if (!fw) {
445a51b3
DB		 3722 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3723 pci_name(chip->pci));
5cb543db
TI		 3724 goto error;
3725 }
3726
3727 chip->fw = fw;
3728 if (!chip->disabled) {
3729 /* continue probing */
3730 if (azx_probe_continue(chip))
3731 goto error;
3732 }
3733 return; /* OK */
3734
3735 error:
3736 snd_card_free(card);
3737 pci_set_drvdata(pci, NULL);
3738}
97c6a3d1 3739#endif
5cb543db 3740
e23e7a14
BP		 3741static int azx_probe(struct pci_dev *pci,
3742 const struct pci_device_id *pci_id)
1da177e4 3743{
5aba4f8e 3744 static int dev;
a98f90fd
TI		 3745 struct snd_card *card;
3746 struct azx *chip;
5cb543db 3747 bool probe_now;
927fc866 3748 int err;
1da177e4 3749
5aba4f8e
TI		 3750 if (dev >= SNDRV_CARDS)
3751 return -ENODEV;
3752 if (!enable[dev]) {
3753 dev++;
3754 return -ENOENT;
3755 }
3756
e58de7ba
TI		 3757 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3758 if (err < 0) {
445a51b3 3759 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3760 return err;
1da177e4
LT		 3761 }
3762
4ea6fbc8
TI		 3763 snd_card_set_dev(card, &pci->dev);
3764
5aba4f8e 3765 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3766 if (err < 0)
3767 goto out_free;
421a1252 3768 card->private_data = chip;
f4c482a4
TI		 3769
3770 pci_set_drvdata(pci, card);
3771
3772 err = register_vga_switcheroo(chip);
3773 if (err < 0) {
3774 snd_printk(KERN_ERR SFX
445a51b3 3775 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3776 goto out_free;
3777 }
3778
3779 if (check_hdmi_disabled(pci)) {
445a51b3 3780 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3781 pci_name(pci));
445a51b3 3782 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3783 chip->disabled = true;
3784 }
3785
5cb543db 3786 probe_now = !chip->disabled;
1da177e4 3787
4918cdab
TI		 3788#ifdef CONFIG_SND_HDA_PATCH_LOADER
3789 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3790 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3791 pci_name(pci), patch[dev]);
5cb543db
TI		 3792 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3793 &pci->dev, GFP_KERNEL, card,
3794 azx_firmware_cb);
4918cdab
TI		 3795 if (err < 0)
3796 goto out_free;
5cb543db 3797 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3798 }
3799#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3800
99a2008d
WX		 3801 /* continue probing in work context, avoid request_module deadlock */
3802 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3803#ifdef CONFIG_SND_HDA_I915
3804 probe_now = false;
3805 schedule_work(&chip->probe_work);
3806#else
3807 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3808#endif
3809 }
3810
5cb543db 3811 if (probe_now) {
a82d51ed
TI		 3812 err = azx_probe_continue(chip);
3813 if (err < 0)
3814 goto out_free;
3815 }
3816
a82d51ed 3817 dev++;
44728e97 3818 complete_all(&chip->probe_wait);
a82d51ed
TI		 3819 return 0;
3820
3821out_free:
3822 snd_card_free(card);
3823 return err;
3824}
3825
48c8b0eb 3826static int azx_probe_continue(struct azx *chip)
a82d51ed 3827{
c67e2228 3828 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3829 int dev = chip->dev_index;
3830 int err;
3831
99a2008d
WX		 3832 /* Request power well for Haswell HDA controller and codec */
3833 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3834 err = hda_i915_init();
3835 if (err < 0) {
3836 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3837 goto out_free;
3838 }
3839 hda_display_power(true);
3840 }
3841
5c90680e
TI		 3842 err = azx_first_init(chip);
3843 if (err < 0)
3844 goto out_free;
3845
2dca0bba
JK		 3846#ifdef CONFIG_SND_HDA_INPUT_BEEP
3847 chip->beep_mode = beep_mode[dev];
3848#endif
3849
1da177e4 3850 /* create codec instances */
a1e21c90 3851 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3852 if (err < 0)
3853 goto out_free;
4ea6fbc8 3854#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3855 if (chip->fw) {
3856 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3857 chip->fw->data);
4ea6fbc8
TI		 3858 if (err < 0)
3859 goto out_free;
e39ae856 3860#ifndef CONFIG_PM
4918cdab
TI		 3861 release_firmware(chip->fw); /* no longer needed */
3862 chip->fw = NULL;
e39ae856 3863#endif
4ea6fbc8
TI		 3864 }
3865#endif
10e77dda 3866 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3867 err = azx_codec_configure(chip);
3868 if (err < 0)
3869 goto out_free;
3870 }
1da177e4
LT		 3871
3872 /* create PCM streams */
176d5335 3873 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3874 if (err < 0)
3875 goto out_free;
1da177e4
LT		 3876
3877 /* create mixer controls */
d01ce99f 3878 err = azx_mixer_create(chip);
41dda0fd
WF		 3879 if (err < 0)
3880 goto out_free;
1da177e4 3881
a82d51ed 3882 err = snd_card_register(chip->card);
41dda0fd
WF		 3883 if (err < 0)
3884 goto out_free;
1da177e4 3885
cb53c626
TI		 3886 chip->running = 1;
3887 power_down_all_codecs(chip);
0cbf0098 3888 azx_notifier_register(chip);
65fcd41d 3889 azx_add_card_list(chip);
c67e2228
WX		 3890 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3891 pm_runtime_put_noidle(&pci->dev);
1da177e4 3892
9121947d
TI		 3893 return 0;
3894
41dda0fd 3895out_free:
a82d51ed 3896 chip->init_failed = 1;
41dda0fd 3897 return err;
1da177e4
LT		 3898}
3899
e23e7a14 3900static void azx_remove(struct pci_dev *pci)
1da177e4 3901{
9121947d 3902 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3903
9121947d
TI		 3904 if (card)
3905 snd_card_free(card);
1da177e4
LT		 3906}
3907
3908/* PCI IDs */
cebe41d4 3909static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3910 /* CPT */
9477c58e 3911 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3912 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3913 /* PBG */
9477c58e 3914 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3915 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3916 /* Panther Point */
9477c58e 3917 { PCI_DEVICE(0x8086, 0x1e20),
d7dab4db 3918 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 3919 /* Lynx Point */
3920 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3921 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3922 /* Wellsburg */
3923 { PCI_DEVICE(0x8086, 0x8d20),
3924 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3925 { PCI_DEVICE(0x8086, 0x8d21),
3926 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3927 /* Lynx Point-LP */
3928 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3929 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3930 /* Lynx Point-LP */
3931 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3932 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3933 /* Haswell */
4a7c516b 3934 { PCI_DEVICE(0x8086, 0x0a0c),
99a2008d
WX		 3935 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3936 AZX_DCAPS_I915_POWERWELL },
e926f2c8 3937 { PCI_DEVICE(0x8086, 0x0c0c),
99a2008d
WX		 3938 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3939 AZX_DCAPS_I915_POWERWELL },
d279fae8 3940 { PCI_DEVICE(0x8086, 0x0d0c),
99a2008d
WX		 3941 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3942 AZX_DCAPS_I915_POWERWELL },
99df18b3
PLB		 3943 /* 5 Series/3400 */
3944 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 3945 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 3946 /* Poulsbo */
9477c58e 3947 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 3948 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3949 /* Oaktrail */
09904b95 3950 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 3951 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 3952 /* BayTrail */
3953 { PCI_DEVICE(0x8086, 0x0f04),
3954 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 3955 /* ICH */
8b0bd226 3956 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3957 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3958 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3959 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3960 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3961 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3962 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3963 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3964 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3965 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3966 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3967 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3968 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3969 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3970 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3971 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3972 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3973 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3974 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3975 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3976 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3977 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3978 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3979 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3980 /* Generic Intel */
3981 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3982 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3983 .class_mask = 0xffffff,
2ae66c26 3984 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3985 /* ATI SB 450/600/700/800/900 */
3986 { PCI_DEVICE(0x1002, 0x437b),
3987 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3988 { PCI_DEVICE(0x1002, 0x4383),
3989 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3990 /* AMD Hudson */
3991 { PCI_DEVICE(0x1022, 0x780d),
3992 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3993 /* ATI HDMI */
9477c58e
TI		 3994 { PCI_DEVICE(0x1002, 0x793b),
3995 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3996 { PCI_DEVICE(0x1002, 0x7919),
3997 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3998 { PCI_DEVICE(0x1002, 0x960f),
3999 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4000 { PCI_DEVICE(0x1002, 0x970f),
4001 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4002 { PCI_DEVICE(0x1002, 0xaa00),
4003 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4004 { PCI_DEVICE(0x1002, 0xaa08),
4005 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4006 { PCI_DEVICE(0x1002, 0xaa10),
4007 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4008 { PCI_DEVICE(0x1002, 0xaa18),
4009 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4010 { PCI_DEVICE(0x1002, 0xaa20),
4011 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4012 { PCI_DEVICE(0x1002, 0xaa28),
4013 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4014 { PCI_DEVICE(0x1002, 0xaa30),
4015 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4016 { PCI_DEVICE(0x1002, 0xaa38),
4017 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4018 { PCI_DEVICE(0x1002, 0xaa40),
4019 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4020 { PCI_DEVICE(0x1002, 0xaa48),
4021 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 4022 { PCI_DEVICE(0x1002, 0x9902),
4023 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4024 { PCI_DEVICE(0x1002, 0xaaa0),
4025 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4026 { PCI_DEVICE(0x1002, 0xaaa8),
4027 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4028 { PCI_DEVICE(0x1002, 0xaab0),
4029 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 4030 /* VIA VT8251/VT8237A */
9477c58e
TI		 4031 { PCI_DEVICE(0x1106, 0x3288),
4032 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 4033 /* VIA GFX VT7122/VX900 */
4034 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4035 /* VIA GFX VT6122/VX11 */
4036 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 4037 /* SIS966 */
4038 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4039 /* ULI M5461 */
4040 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4041 /* NVIDIA MCP */
0c2fd1bf
TI		 4042 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4043 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4044 .class_mask = 0xffffff,
9477c58e 4045 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 4046 /* Teradici */
9477c58e
TI		 4047 { PCI_DEVICE(0x6549, 0x1200),
4048 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 4049 { PCI_DEVICE(0x6549, 0x2200),
4050 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 4051 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 4052 /* CTHDA chips */
4053 { PCI_DEVICE(0x1102, 0x0010),
4054 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4055 { PCI_DEVICE(0x1102, 0x0012),
4056 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 4057#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4058 /* the following entry conflicts with snd-ctxfi driver,
4059 * as ctxfi driver mutates from HD-audio to native mode with
4060 * a special command sequence.
4061 */
4e01f54b
TI		 4062 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4063 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4064 .class_mask = 0xffffff,
9477c58e 4065 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4066 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4067#else
4068 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4069 { PCI_DEVICE(0x1102, 0x0009),
4070 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4071 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4072#endif
e35d4b11
OS		 4073 /* Vortex86MX */
4074 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4075 /* VMware HDAudio */
4076 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4077 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4078 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4079 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4080 .class_mask = 0xffffff,
9477c58e 4081 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4082 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4083 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4084 .class_mask = 0xffffff,
9477c58e 4085 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4086 { 0, }
4087};
4088MODULE_DEVICE_TABLE(pci, azx_ids);
4089
4090/* pci_driver definition */
e9f66d9b 4091static struct pci_driver azx_driver = {
3733e424 4092 .name = KBUILD_MODNAME,
1da177e4
LT		 4093 .id_table = azx_ids,
4094 .probe = azx_probe,
e23e7a14 4095 .remove = azx_remove,
68cb2b55
TI		 4096 .driver = {
4097 .pm = AZX_PM_OPS,
4098 },
1da177e4
LT		 4099};
4100
e9f66d9b 4101module_pci_driver(azx_driver);
Linux kernel - Deliverables
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