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ALSA: hda - Allow different ops to read/write registers
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
2538a4f5 66#include "hda_priv.h"
1da177e4
LT		 67
68
5aba4f8e
TI		 69static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
70static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 71static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 72static char *model[SNDRV_CARDS];
1dac6695 73static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 74static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 75static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 76static int probe_only[SNDRV_CARDS];
26a6cb6c 77static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 78static bool single_cmd;
71623855 79static int enable_msi = -1;
4ea6fbc8
TI		 80#ifdef CONFIG_SND_HDA_PATCH_LOADER
81static char *patch[SNDRV_CARDS];
82#endif
2dca0bba 83#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 84static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 85 CONFIG_SND_HDA_INPUT_BEEP_MODE};
86#endif
1da177e4 87
5aba4f8e 88module_param_array(index, int, NULL, 0444);
1da177e4 89MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 90module_param_array(id, charp, NULL, 0444);
1da177e4 91MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 92module_param_array(enable, bool, NULL, 0444);
93MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
94module_param_array(model, charp, NULL, 0444);
1da177e4 95MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 96module_param_array(position_fix, int, NULL, 0444);
4cb36310 97MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 98 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 99module_param_array(bdl_pos_adj, int, NULL, 0644);
100MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 101module_param_array(probe_mask, int, NULL, 0444);
606ad75f 102MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 103module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 104MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 105module_param_array(jackpoll_ms, int, NULL, 0444);
106MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 107module_param(single_cmd, bool, 0444);
d01ce99f
TI		 108MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
109 "(for debugging only).");
ac9ef6cf 110module_param(enable_msi, bint, 0444);
134a11f0 111MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 112#ifdef CONFIG_SND_HDA_PATCH_LOADER
113module_param_array(patch, charp, NULL, 0444);
114MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
115#endif
2dca0bba 116#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 117module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 118MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 119 "(0=off, 1=on) (default=1).");
2dca0bba 120#endif
606ad75f 121
83012a7c 122#ifdef CONFIG_PM
65fcd41d
TI		 123static int param_set_xint(const char *val, const struct kernel_param *kp);
124static struct kernel_param_ops param_ops_xint = {
125 .set = param_set_xint,
126 .get = param_get_int,
127};
128#define param_check_xint param_check_int
129
fee2fba3 130static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 131module_param(power_save, xint, 0644);
fee2fba3
TI		 132MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
133 "(in second, 0 = disable).");
1da177e4 134
dee1b66c
TI		 135/* reset the HD-audio controller in power save mode.
136 * this may give more power-saving, but will take longer time to
137 * wake up.
138 */
8fc24426
TI		 139static bool power_save_controller = 1;
140module_param(power_save_controller, bool, 0644);
dee1b66c 141MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 142#endif /* CONFIG_PM */
dee1b66c 143
7bfe059e
TI		 144static int align_buffer_size = -1;
145module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 146MODULE_PARM_DESC(align_buffer_size,
147 "Force buffer and period sizes to be multiple of 128 bytes.");
148
27fe48d9
TI		 149#ifdef CONFIG_X86
150static bool hda_snoop = true;
151module_param_named(snoop, hda_snoop, bool, 0444);
152MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 153#else
154#define hda_snoop true
27fe48d9
TI		 155#endif
156
157
1da177e4
LT		 158MODULE_LICENSE("GPL");
159MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
2f1b3818 161 "{Intel, ICH7},"
f5d40b30 162 "{Intel, ESB2},"
d2981393 163 "{Intel, ICH8},"
f9cc8a8b 164 "{Intel, ICH9},"
c34f5a04 165 "{Intel, ICH10},"
b29c2360 166 "{Intel, PCH},"
d2f2fcd2 167 "{Intel, CPT},"
d2edeb7c 168 "{Intel, PPT},"
8bc039a1 169 "{Intel, LPT},"
144dad99 170 "{Intel, LPT_LP},"
4eeca499 171 "{Intel, WPT_LP},"
e926f2c8 172 "{Intel, HPT},"
cea310e8 173 "{Intel, PBG},"
4979bca9 174 "{Intel, SCH},"
fc20a562 175 "{ATI, SB450},"
89be83f8 176 "{ATI, SB600},"
778b6e1b 177 "{ATI, RS600},"
5b15c95f 178 "{ATI, RS690},"
e6db1119
WL		 179 "{ATI, RS780},"
180 "{ATI, R600},"
2797f724
HRK		 181 "{ATI, RV630},"
182 "{ATI, RV610},"
27da1834
WL		 183 "{ATI, RV670},"
184 "{ATI, RV635},"
185 "{ATI, RV620},"
186 "{ATI, RV770},"
fc20a562 187 "{VIA, VT8251},"
47672310 188 "{VIA, VT8237A},"
07e4ca50
TI		 189 "{SiS, SIS966},"
190 "{ULI, M5461}}");
1da177e4
LT		 191MODULE_DESCRIPTION("Intel HDA driver");
192
a82d51ed 193#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 194#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 195#define SUPPORT_VGA_SWITCHEROO
196#endif
197#endif
198
199
1da177e4 200/*
1da177e4 201 */
1da177e4 202
eb49faa6
TI		 203/* DSP lock helpers */
204#ifdef CONFIG_SND_HDA_DSP_LOADER
205#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
206#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
207#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
208#define dsp_is_locked(dev) ((dev)->locked)
209#else
210#define dsp_lock_init(dev) do {} while (0)
211#define dsp_lock(dev) do {} while (0)
212#define dsp_unlock(dev) do {} while (0)
213#define dsp_is_locked(dev) 0
214#endif
215
1a8506d4
TI		 216#define CREATE_TRACE_POINTS
217#include "hda_intel_trace.h"
218
07e4ca50
TI		 219/* driver types */
220enum {
221 AZX_DRIVER_ICH,
32679f95 222 AZX_DRIVER_PCH,
4979bca9 223 AZX_DRIVER_SCH,
fab1285a 224 AZX_DRIVER_HDMI,
07e4ca50 225 AZX_DRIVER_ATI,
778b6e1b 226 AZX_DRIVER_ATIHDMI,
1815b34a 227 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 228 AZX_DRIVER_VIA,
229 AZX_DRIVER_SIS,
230 AZX_DRIVER_ULI,
da3fca21 231 AZX_DRIVER_NVIDIA,
f269002e 232 AZX_DRIVER_TERA,
14d34f16 233 AZX_DRIVER_CTX,
5ae763b1 234 AZX_DRIVER_CTHDA,
c4da29ca 235 AZX_DRIVER_GENERIC,
2f5983f2 236 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 237};
238
2ea3c6a2 239/* quirks for Intel PCH */
d7dab4db 240#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 241 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 242 AZX_DCAPS_COUNT_LPIB_DELAY)
243
244#define AZX_DCAPS_INTEL_PCH \
245 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 246
33499a15
TI		 247#define AZX_DCAPS_INTEL_HASWELL \
248 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
249 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
250 AZX_DCAPS_I915_POWERWELL)
251
9477c58e
TI		 252/* quirks for ATI SB / AMD Hudson */
253#define AZX_DCAPS_PRESET_ATI_SB \
254 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
255 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
256
257/* quirks for ATI/AMD HDMI */
258#define AZX_DCAPS_PRESET_ATI_HDMI \
259 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
260
261/* quirks for Nvidia */
262#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 263 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 264 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 265
5ae763b1
TI		 266#define AZX_DCAPS_PRESET_CTHDA \
267 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
268
a82d51ed
TI		 269/*
270 * VGA-switcher support
271 */
272#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 273#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
274#else
275#define use_vga_switcheroo(chip) 0
276#endif
277
48c8b0eb 278static char *driver_short_names[] = {
07e4ca50 279 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 280 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 281 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 282 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 283 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 284 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 285 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 286 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
287 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 288 [AZX_DRIVER_ULI] = "HDA ULI M5461",
289 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 290 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 291 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 292 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 293 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 294};
295
1da177e4 296/* for pcm support */
a98f90fd 297#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 298
27fe48d9 299#ifdef CONFIG_X86
9ddf1aeb 300static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 301{
9ddf1aeb
TI		 302 int pages;
303
27fe48d9
TI		 304 if (azx_snoop(chip))
305 return;
9ddf1aeb
TI		 306 if (!dmab || !dmab->area || !dmab->bytes)
307 return;
308
309#ifdef CONFIG_SND_DMA_SGBUF
310 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
311 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 312 if (on)
9ddf1aeb 313 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 314 else
9ddf1aeb
TI		 315 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
316 return;
27fe48d9 317 }
9ddf1aeb
TI		 318#endif
319
320 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
321 if (on)
322 set_memory_wc((unsigned long)dmab->area, pages);
323 else
324 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 325}
326
327static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329{
9ddf1aeb 330 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 331}
332static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 333 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 334{
335 if (azx_dev->wc_marked != on) {
9ddf1aeb 336 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 337 azx_dev->wc_marked = on;
338 }
339}
340#else
341/* NOP for other archs */
342static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
343 bool on)
344{
345}
346static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 347 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 348{
349}
350#endif
351
68e7fffc 352static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 353static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 354/*
355 * Interface for HD codec
356 */
357
1da177e4
LT		 358/*
359 * CORB / RIRB interface
360 */
a98f90fd 361static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 362{
363 int err;
364
365 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 366 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
367 snd_dma_pci_data(chip->pci),
1da177e4
LT		 368 PAGE_SIZE, &chip->rb);
369 if (err < 0) {
4e76a883 370 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
1da177e4
LT		 371 return err;
372 }
27fe48d9 373 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 374 return 0;
375}
376
a98f90fd 377static void azx_init_cmd_io(struct azx *chip)
1da177e4 378{
ca460f86
DH		 379 int timeout;
380
cdb1fbf2 381 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 382 /* CORB set up */
383 chip->corb.addr = chip->rb.addr;
384 chip->corb.buf = (u32 *)chip->rb.area;
385 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 386 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 387
07e4ca50
TI		 388 /* set the corb size to 256 entries (ULI requires explicitly) */
389 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 390 /* set the corb write pointer to 0 */
391 azx_writew(chip, CORBWP, 0);
ca460f86 392
1da177e4 393 /* reset the corb hw read pointer */
b21fadb9 394 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
ca460f86
DH		 395 for (timeout = 1000; timeout > 0; timeout--) {
396 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
397 break;
398 udelay(1);
399 }
400 if (timeout <= 0)
401 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
402 azx_readw(chip, CORBRP));
403
404 azx_writew(chip, CORBRP, 0);
405 for (timeout = 1000; timeout > 0; timeout--) {
406 if (azx_readw(chip, CORBRP) == 0)
407 break;
408 udelay(1);
409 }
410 if (timeout <= 0)
411 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
412 azx_readw(chip, CORBRP));
413
1da177e4 414 /* enable corb dma */
b21fadb9 415 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 416
417 /* RIRB set up */
418 chip->rirb.addr = chip->rb.addr + 2048;
419 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 420 chip->rirb.wp = chip->rirb.rp = 0;
421 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 422 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 423 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 424
07e4ca50
TI		 425 /* set the rirb size to 256 entries (ULI requires explicitly) */
426 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 427 /* reset the rirb hw write pointer */
b21fadb9 428 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 429 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 430 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 431 azx_writew(chip, RINTCNT, 0xc0);
432 else
433 azx_writew(chip, RINTCNT, 1);
1da177e4 434 /* enable rirb dma and response irq */
1da177e4 435 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 436 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 437}
438
a98f90fd 439static void azx_free_cmd_io(struct azx *chip)
1da177e4 440{
cdb1fbf2 441 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 442 /* disable ringbuffer DMAs */
443 azx_writeb(chip, RIRBCTL, 0);
444 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 445 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 446}
447
deadff16
WF		 448static unsigned int azx_command_addr(u32 cmd)
449{
450 unsigned int addr = cmd >> 28;
451
452 if (addr >= AZX_MAX_CODECS) {
453 snd_BUG();
454 addr = 0;
455 }
456
457 return addr;
458}
459
1da177e4 460/* send a command */
33fa35ed 461static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 462{
33fa35ed 463 struct azx *chip = bus->private_data;
deadff16 464 unsigned int addr = azx_command_addr(val);
3bcce5c0 465 unsigned int wp, rp;
1da177e4 466
c32649fe
WF		 467 spin_lock_irq(&chip->reg_lock);
468
1da177e4 469 /* add command to corb */
cc5ede3e
TI		 470 wp = azx_readw(chip, CORBWP);
471 if (wp == 0xffff) {
472 /* something wrong, controller likely turned to D3 */
473 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 474 return -EIO;
cc5ede3e 475 }
1da177e4
LT		 476 wp++;
477 wp %= ICH6_MAX_CORB_ENTRIES;
478
3bcce5c0
TI		 479 rp = azx_readw(chip, CORBRP);
480 if (wp == rp) {
481 /* oops, it's full */
482 spin_unlock_irq(&chip->reg_lock);
483 return -EAGAIN;
484 }
485
deadff16 486 chip->rirb.cmds[addr]++;
1da177e4 487 chip->corb.buf[wp] = cpu_to_le32(val);
ca460f86 488 azx_writew(chip, CORBWP, wp);
c32649fe 489
1da177e4
LT		 490 spin_unlock_irq(&chip->reg_lock);
491
492 return 0;
493}
494
495#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
496
497/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 498static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 499{
500 unsigned int rp, wp;
deadff16 501 unsigned int addr;
1da177e4
LT		 502 u32 res, res_ex;
503
cc5ede3e
TI		 504 wp = azx_readw(chip, RIRBWP);
505 if (wp == 0xffff) {
506 /* something wrong, controller likely turned to D3 */
507 return;
508 }
509
1da177e4
LT		 510 if (wp == chip->rirb.wp)
511 return;
512 chip->rirb.wp = wp;
deadff16 513
1da177e4
LT		 514 while (chip->rirb.rp != wp) {
515 chip->rirb.rp++;
516 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
517
518 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
519 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
520 res = le32_to_cpu(chip->rirb.buf[rp]);
3d692451
DH		 521 addr = res_ex & 0xf;
522 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
4e76a883
TI		 523 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
524 res, res_ex,
525 chip->rirb.rp, wp);
3d692451
DH		 526 snd_BUG();
527 }
528 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
1da177e4 529 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 530 else if (chip->rirb.cmds[addr]) {
531 chip->rirb.res[addr] = res;
2add9b92 532 smp_wmb();
deadff16 533 chip->rirb.cmds[addr]--;
3b70a67d 534 } else if (printk_ratelimit()) {
4e76a883
TI		 535 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
536 res, res_ex,
537 chip->last_cmd[addr]);
3b70a67d 538 }
1da177e4
LT		 539 }
540}
541
542/* receive a response */
deadff16
WF		 543static unsigned int azx_rirb_get_response(struct hda_bus *bus,
544 unsigned int addr)
1da177e4 545{
33fa35ed 546 struct azx *chip = bus->private_data;
5c79b1f8 547 unsigned long timeout;
32cf4023 548 unsigned long loopcounter;
1eb6dc7d 549 int do_poll = 0;
1da177e4 550
5c79b1f8
TI		 551 again:
552 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 553
554 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 555 if (chip->polling_mode || do_poll) {
e96224ae
TI		 556 spin_lock_irq(&chip->reg_lock);
557 azx_update_rirb(chip);
558 spin_unlock_irq(&chip->reg_lock);
559 }
deadff16 560 if (!chip->rirb.cmds[addr]) {
2add9b92 561 smp_rmb();
b613291f 562 bus->rirb_error = 0;
1eb6dc7d
ML		 563
564 if (!do_poll)
565 chip->poll_count = 0;
deadff16 566 return chip->rirb.res[addr]; /* the last value */
2add9b92 567 }
28a0d9df
TI		 568 if (time_after(jiffies, timeout))
569 break;
32cf4023 570 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 571 msleep(2); /* temporary workaround */
572 else {
573 udelay(10);
574 cond_resched();
575 }
28a0d9df 576 }
5c79b1f8 577
63e51fd7
TI		 578 if (!bus->no_response_fallback)
579 return -1;
580
1eb6dc7d 581 if (!chip->polling_mode && chip->poll_count < 2) {
4e76a883
TI		 582 dev_dbg(chip->card->dev,
583 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
584 chip->last_cmd[addr]);
1eb6dc7d
ML		 585 do_poll = 1;
586 chip->poll_count++;
587 goto again;
588 }
589
590
23c4a881 591 if (!chip->polling_mode) {
4e76a883
TI		 592 dev_warn(chip->card->dev,
593 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
594 chip->last_cmd[addr]);
23c4a881
TI		 595 chip->polling_mode = 1;
596 goto again;
597 }
598
68e7fffc 599 if (chip->msi) {
4e76a883
TI		 600 dev_warn(chip->card->dev,
601 "No response from codec, disabling MSI: last cmd=0x%08x\n",
602 chip->last_cmd[addr]);
68e7fffc
TI		 603 free_irq(chip->irq, chip);
604 chip->irq = -1;
605 pci_disable_msi(chip->pci);
606 chip->msi = 0;
b613291f
TI		 607 if (azx_acquire_irq(chip, 1) < 0) {
608 bus->rirb_error = 1;
68e7fffc 609 return -1;
b613291f 610 }
68e7fffc
TI		 611 goto again;
612 }
613
6ce4a3bc
TI		 614 if (chip->probing) {
615 /* If this critical timeout happens during the codec probing
616 * phase, this is likely an access to a non-existing codec
617 * slot. Better to return an error and reset the system.
618 */
619 return -1;
620 }
621
8dd78330
TI		 622 /* a fatal communication error; need either to reset or to fallback
623 * to the single_cmd mode
624 */
b613291f 625 bus->rirb_error = 1;
b20f3b83 626 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 627 bus->response_reset = 1;
628 return -1; /* give a chance to retry */
629 }
630
4e76a883
TI		 631 dev_err(chip->card->dev,
632 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
633 chip->last_cmd[addr]);
8dd78330
TI		 634 chip->single_cmd = 1;
635 bus->response_reset = 0;
1a696978 636 /* release CORB/RIRB */
4fcd3920 637 azx_free_cmd_io(chip);
1a696978
TI		 638 /* disable unsolicited responses */
639 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 640 return -1;
1da177e4
LT		 641}
642
1da177e4
LT		 643/*
644 * Use the single immediate command instead of CORB/RIRB for simplicity
645 *
646 * Note: according to Intel, this is not preferred use. The command was
647 * intended for the BIOS only, and may get confused with unsolicited
648 * responses. So, we shouldn't use it for normal operation from the
649 * driver.
650 * I left the codes, however, for debugging/testing purposes.
651 */
652
b05a7d4f 653/* receive a response */
deadff16 654static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 655{
656 int timeout = 50;
657
658 while (timeout--) {
659 /* check IRV busy bit */
660 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
661 /* reuse rirb.res as the response return value */
deadff16 662 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 663 return 0;
664 }
665 udelay(1);
666 }
667 if (printk_ratelimit())
4e76a883
TI		 668 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
669 azx_readw(chip, IRS));
deadff16 670 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 671 return -EIO;
672}
673
1da177e4 674/* send a command */
33fa35ed 675static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 676{
33fa35ed 677 struct azx *chip = bus->private_data;
deadff16 678 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 679 int timeout = 50;
680
8dd78330 681 bus->rirb_error = 0;
1da177e4
LT		 682 while (timeout--) {
683 /* check ICB busy bit */
d01ce99f 684 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 685 /* Clear IRV valid bit */
d01ce99f
TI		 686 azx_writew(chip, IRS, azx_readw(chip, IRS) |
687 ICH6_IRS_VALID);
1da177e4 688 azx_writel(chip, IC, val);
d01ce99f
TI		 689 azx_writew(chip, IRS, azx_readw(chip, IRS) |
690 ICH6_IRS_BUSY);
deadff16 691 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 692 }
693 udelay(1);
694 }
1cfd52bc 695 if (printk_ratelimit())
4e76a883
TI		 696 dev_dbg(chip->card->dev,
697 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
698 azx_readw(chip, IRS), val);
1da177e4
LT		 699 return -EIO;
700}
701
702/* receive a response */
deadff16
WF		 703static unsigned int azx_single_get_response(struct hda_bus *bus,
704 unsigned int addr)
1da177e4 705{
33fa35ed 706 struct azx *chip = bus->private_data;
deadff16 707 return chip->rirb.res[addr];
1da177e4
LT		 708}
709
111d3af5
TI		 710/*
711 * The below are the main callbacks from hda_codec.
712 *
713 * They are just the skeleton to call sub-callbacks according to the
714 * current setting of chip->single_cmd.
715 */
716
717/* send a command */
33fa35ed 718static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 719{
33fa35ed 720 struct azx *chip = bus->private_data;
43bbb6cc 721
a82d51ed
TI		 722 if (chip->disabled)
723 return 0;
feb27340 724 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 725 if (chip->single_cmd)
33fa35ed 726 return azx_single_send_cmd(bus, val);
111d3af5 727 else
33fa35ed 728 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 729}
730
731/* get a response */
deadff16
WF		 732static unsigned int azx_get_response(struct hda_bus *bus,
733 unsigned int addr)
111d3af5 734{
33fa35ed 735 struct azx *chip = bus->private_data;
a82d51ed
TI		 736 if (chip->disabled)
737 return 0;
111d3af5 738 if (chip->single_cmd)
deadff16 739 return azx_single_get_response(bus, addr);
111d3af5 740 else
deadff16 741 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 742}
743
83012a7c 744#ifdef CONFIG_PM
68467f51 745static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 746#endif
111d3af5 747
1d1a4564
TI		 748#ifdef CONFIG_SND_HDA_DSP_LOADER
749static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
750 unsigned int byte_size,
751 struct snd_dma_buffer *bufp);
752static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
753static void azx_load_dsp_cleanup(struct hda_bus *bus,
754 struct snd_dma_buffer *dmab);
755#endif
756
3af3f356 757/* enter link reset */
7295b264 758static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 759{
760 unsigned long timeout;
761
762 /* reset controller */
763 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
764
765 timeout = jiffies + msecs_to_jiffies(100);
766 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
767 time_before(jiffies, timeout))
768 usleep_range(500, 1000);
769}
770
7295b264
ML		 771/* exit link reset */
772static void azx_exit_link_reset(struct azx *chip)
1da177e4 773{
fa348da5 774 unsigned long timeout;
1da177e4 775
7295b264
ML		 776 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
777
778 timeout = jiffies + msecs_to_jiffies(100);
779 while (!azx_readb(chip, GCTL) &&
780 time_before(jiffies, timeout))
781 usleep_range(500, 1000);
782}
783
784/* reset codec link */
785static int azx_reset(struct azx *chip, int full_reset)
786{
cd508fe5
JK		 787 if (!full_reset)
788 goto __skip;
789
e8a7f136 790 /* clear STATESTS */
da7db6ad 791 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 792
1da177e4 793 /* reset controller */
7295b264 794 azx_enter_link_reset(chip);
1da177e4
LT		 795
796 /* delay for >= 100us for codec PLL to settle per spec
797 * Rev 0.9 section 5.5.1
798 */
fa348da5 799 usleep_range(500, 1000);
1da177e4
LT		 800
801 /* Bring controller out of reset */
7295b264 802 azx_exit_link_reset(chip);
1da177e4 803
927fc866 804 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 805 usleep_range(1000, 1200);
1da177e4 806
cd508fe5 807 __skip:
1da177e4 808 /* check to see if controller is ready */
927fc866 809 if (!azx_readb(chip, GCTL)) {
4e76a883 810 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1da177e4
LT		 811 return -EBUSY;
812 }
813
41e2fce4 814 /* Accept unsolicited responses */
1a696978
TI		 815 if (!chip->single_cmd)
816 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
817 ICH6_GCTL_UNSOL);
41e2fce4 818
1da177e4 819 /* detect codecs */
927fc866 820 if (!chip->codec_mask) {
1da177e4 821 chip->codec_mask = azx_readw(chip, STATESTS);
4e76a883
TI		 822 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
823 chip->codec_mask);
1da177e4
LT		 824 }
825
826 return 0;
827}
828
829
830/*
831 * Lowlevel interface
832 */
833
834/* enable interrupts */
a98f90fd 835static void azx_int_enable(struct azx *chip)
1da177e4
LT		 836{
837 /* enable controller CIE and GIE */
838 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
839 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
840}
841
842/* disable interrupts */
a98f90fd 843static void azx_int_disable(struct azx *chip)
1da177e4
LT		 844{
845 int i;
846
847 /* disable interrupts in stream descriptor */
07e4ca50 848 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 849 struct azx_dev *azx_dev = &chip->azx_dev[i];
40830813
DR		 850 azx_sd_writeb(chip, azx_dev, SD_CTL,
851 azx_sd_readb(chip, azx_dev, SD_CTL) &
852 ~SD_INT_MASK);
1da177e4
LT		 853 }
854
855 /* disable SIE for all streams */
856 azx_writeb(chip, INTCTL, 0);
857
858 /* disable controller CIE and GIE */
859 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
860 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
861}
862
863/* clear interrupts */
a98f90fd 864static void azx_int_clear(struct azx *chip)
1da177e4
LT		 865{
866 int i;
867
868 /* clear stream status */
07e4ca50 869 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 870 struct azx_dev *azx_dev = &chip->azx_dev[i];
40830813 871 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1da177e4
LT		 872 }
873
874 /* clear STATESTS */
da7db6ad 875 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 876
877 /* clear rirb status */
878 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
879
880 /* clear int status */
881 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
882}
883
884/* start a stream */
a98f90fd 885static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 886{
0e153474
JC		 887 /*
888 * Before stream start, initialize parameter
889 */
890 azx_dev->insufficient = 1;
891
1da177e4 892 /* enable SIE */
ccc5df05
WN		 893 azx_writel(chip, INTCTL,
894 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4 895 /* set DMA start and interrupt mask */
40830813
DR		 896 azx_sd_writeb(chip, azx_dev, SD_CTL,
897 azx_sd_readb(chip, azx_dev, SD_CTL) |
1da177e4
LT		 898 SD_CTL_DMA_START | SD_INT_MASK);
899}
900
1dddab40
TI		 901/* stop DMA */
902static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 903{
40830813
DR		 904 azx_sd_writeb(chip, azx_dev, SD_CTL,
905 azx_sd_readb(chip, azx_dev, SD_CTL) &
1da177e4 906 ~(SD_CTL_DMA_START | SD_INT_MASK));
40830813 907 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 908}
909
910/* stop a stream */
911static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
912{
913 azx_stream_clear(chip, azx_dev);
1da177e4 914 /* disable SIE */
ccc5df05
WN		 915 azx_writel(chip, INTCTL,
916 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 917}
918
919
920/*
cb53c626 921 * reset and start the controller registers
1da177e4 922 */
cd508fe5 923static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 924{
cb53c626
TI		 925 if (chip->initialized)
926 return;
1da177e4
LT		 927
928 /* reset controller */
cd508fe5 929 azx_reset(chip, full_reset);
1da177e4
LT		 930
931 /* initialize interrupts */
932 azx_int_clear(chip);
933 azx_int_enable(chip);
934
935 /* initialize the codec command I/O */
1a696978
TI		 936 if (!chip->single_cmd)
937 azx_init_cmd_io(chip);
1da177e4 938
0be3b5d3
TI		 939 /* program the position buffer */
940 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 941 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 942
cb53c626
TI		 943 chip->initialized = 1;
944}
945
946/*
947 * initialize the PCI registers
948 */
949/* update bits in a PCI register byte */
950static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
951 unsigned char mask, unsigned char val)
952{
953 unsigned char data;
954
955 pci_read_config_byte(pci, reg, &data);
956 data &= ~mask;
957 data |= (val & mask);
958 pci_write_config_byte(pci, reg, data);
959}
960
961static void azx_init_pci(struct azx *chip)
962{
963 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
964 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
965 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 966 * codecs.
967 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 968 */
46f2cc80 969 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 970 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 971 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 972 }
cb53c626 973
9477c58e
TI		 974 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
975 * we need to enable snoop.
976 */
977 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 978 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
979 azx_snoop(chip));
cb53c626 980 update_pci_byte(chip->pci,
27fe48d9
TI		 981 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
982 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 983 }
984
985 /* For NVIDIA HDA, enable snoop */
986 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 987 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
988 azx_snoop(chip));
cb53c626
TI		 989 update_pci_byte(chip->pci,
990 NVIDIA_HDA_TRANSREG_ADDR,
991 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 992 update_pci_byte(chip->pci,
993 NVIDIA_HDA_ISTRM_COH,
994 0x01, NVIDIA_HDA_ENABLE_COHBIT);
995 update_pci_byte(chip->pci,
996 NVIDIA_HDA_OSTRM_COH,
997 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 998 }
999
1000 /* Enable SCH/PCH snoop if needed */
1001 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1002 unsigned short snoop;
90a5ad52 1003 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1004 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1005 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1006 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1007 if (!azx_snoop(chip))
1008 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1009 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1010 pci_read_config_word(chip->pci,
1011 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1012 }
4e76a883
TI		 1013 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
1014 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
1015 "Disabled" : "Enabled");
da3fca21 1016 }
1da177e4
LT		 1017}
1018
1019
9ad593f6
TI		 1020static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1021
1da177e4
LT		 1022/*
1023 * interrupt handler
1024 */
7d12e780 1025static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1026{
a98f90fd
TI		 1027 struct azx *chip = dev_id;
1028 struct azx_dev *azx_dev;
1da177e4 1029 u32 status;
9ef04066 1030 u8 sd_status;
fa00e046 1031 int i, ok;
1da177e4 1032
b8dfc462 1033#ifdef CONFIG_PM_RUNTIME
246efa4a
DA		 1034 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1035 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1036 return IRQ_NONE;
b8dfc462
ML		 1037#endif
1038
1da177e4
LT		 1039 spin_lock(&chip->reg_lock);
1040
60911062
DC		 1041 if (chip->disabled) {
1042 spin_unlock(&chip->reg_lock);
a82d51ed 1043 return IRQ_NONE;
60911062 1044 }
a82d51ed 1045
1da177e4 1046 status = azx_readl(chip, INTSTS);
246efa4a 1047 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 1048 spin_unlock(&chip->reg_lock);
1049 return IRQ_NONE;
1050 }
1051
07e4ca50 1052 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1053 azx_dev = &chip->azx_dev[i];
1054 if (status & azx_dev->sd_int_sta_mask) {
40830813
DR		 1055 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1056 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1057 if (!azx_dev->substream || !azx_dev->running ||
1058 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1059 continue;
1060 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1061 ok = azx_position_ok(chip, azx_dev);
1062 if (ok == 1) {
9ad593f6 1063 azx_dev->irq_pending = 0;
1da177e4
LT		 1064 spin_unlock(&chip->reg_lock);
1065 snd_pcm_period_elapsed(azx_dev->substream);
1066 spin_lock(&chip->reg_lock);
fa00e046 1067 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1068 /* bogus IRQ, process it later */
1069 azx_dev->irq_pending = 1;
6acaed38
TI		 1070 queue_work(chip->bus->workq,
1071 &chip->irq_pending_work);
1da177e4
LT		 1072 }
1073 }
1074 }
1075
1076 /* clear rirb int */
1077 status = azx_readb(chip, RIRBSTS);
1078 if (status & RIRB_INT_MASK) {
14d34f16 1079 if (status & RIRB_INT_RESPONSE) {
9477c58e 1080 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1081 udelay(80);
1da177e4 1082 azx_update_rirb(chip);
14d34f16 1083 }
1da177e4
LT		 1084 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1085 }
1086
1087#if 0
1088 /* clear state status int */
da7db6ad
WX		 1089 if (azx_readw(chip, STATESTS) & 0x04)
1090 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1091#endif
1092 spin_unlock(&chip->reg_lock);
1093
1094 return IRQ_HANDLED;
1095}
1096
1097
675f25d4
TI		 1098/*
1099 * set up a BDL entry
1100 */
5ae763b1 1101static int setup_bdle(struct azx *chip,
1d1a4564 1102 struct snd_dma_buffer *dmab,
675f25d4
TI		 1103 struct azx_dev *azx_dev, u32 **bdlp,
1104 int ofs, int size, int with_ioc)
1105{
675f25d4
TI		 1106 u32 *bdl = *bdlp;
1107
1108 while (size > 0) {
1109 dma_addr_t addr;
1110 int chunk;
1111
1112 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1113 return -EINVAL;
1114
1d1a4564 1115 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1116 /* program the address field of the BDL entry */
1117 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1118 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1119 /* program the size field of the BDL entry */
1d1a4564 1120 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1121 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1122 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1123 u32 remain = 0x1000 - (ofs & 0xfff);
1124 if (chunk > remain)
1125 chunk = remain;
1126 }
675f25d4
TI		 1127 bdl[2] = cpu_to_le32(chunk);
1128 /* program the IOC to enable interrupt
1129 * only when the whole fragment is processed
1130 */
1131 size -= chunk;
1132 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1133 bdl += 4;
1134 azx_dev->frags++;
1135 ofs += chunk;
1136 }
1137 *bdlp = bdl;
1138 return ofs;
1139}
1140
1da177e4
LT		 1141/*
1142 * set up BDL entries
1143 */
555e219f
TI		 1144static int azx_setup_periods(struct azx *chip,
1145 struct snd_pcm_substream *substream,
4ce107b9 1146 struct azx_dev *azx_dev)
1da177e4 1147{
4ce107b9
TI		 1148 u32 *bdl;
1149 int i, ofs, periods, period_bytes;
555e219f 1150 int pos_adj;
1da177e4
LT		 1151
1152 /* reset BDL address */
40830813
DR		 1153 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1154 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1da177e4 1155
97b71c94 1156 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1157 periods = azx_dev->bufsize / period_bytes;
1158
1da177e4 1159 /* program the initial BDL entries */
4ce107b9
TI		 1160 bdl = (u32 *)azx_dev->bdl.area;
1161 ofs = 0;
1162 azx_dev->frags = 0;
555e219f 1163 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1164 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1165 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1166 int pos_align = pos_adj;
555e219f 1167 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1168 if (!pos_adj)
e785d3d8
TI		 1169 pos_adj = pos_align;
1170 else
1171 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1172 pos_align;
675f25d4
TI		 1173 pos_adj = frames_to_bytes(runtime, pos_adj);
1174 if (pos_adj >= period_bytes) {
4e76a883
TI		 1175 dev_warn(chip->card->dev,"Too big adjustment %d\n",
1176 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1177 pos_adj = 0;
1178 } else {
1d1a4564
TI		 1179 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1180 azx_dev,
915bf29e 1181 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1182 if (ofs < 0)
1183 goto error;
4ce107b9 1184 }
555e219f
TI		 1185 } else
1186 pos_adj = 0;
675f25d4
TI		 1187 for (i = 0; i < periods; i++) {
1188 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1189 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1190 azx_dev, &bdl, ofs,
675f25d4
TI		 1191 period_bytes - pos_adj, 0);
1192 else
1d1a4564
TI		 1193 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1194 azx_dev, &bdl, ofs,
7bb8fb70 1195 period_bytes,
915bf29e 1196 !azx_dev->no_period_wakeup);
675f25d4
TI		 1197 if (ofs < 0)
1198 goto error;
1da177e4 1199 }
4ce107b9 1200 return 0;
675f25d4
TI		 1201
1202 error:
4e76a883
TI		 1203 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1204 azx_dev->bufsize, period_bytes);
675f25d4 1205 return -EINVAL;
1da177e4
LT		 1206}
1207
1dddab40
TI		 1208/* reset stream */
1209static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1210{
1211 unsigned char val;
1212 int timeout;
1213
1dddab40
TI		 1214 azx_stream_clear(chip, azx_dev);
1215
40830813
DR		 1216 azx_sd_writeb(chip, azx_dev, SD_CTL,
1217 azx_sd_readb(chip, azx_dev, SD_CTL) |
d01ce99f 1218 SD_CTL_STREAM_RESET);
1da177e4
LT		 1219 udelay(3);
1220 timeout = 300;
40830813
DR		 1221 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1222 SD_CTL_STREAM_RESET) && --timeout)
1da177e4
LT		 1223 ;
1224 val &= ~SD_CTL_STREAM_RESET;
40830813 1225 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
1da177e4
LT		 1226 udelay(3);
1227
1228 timeout = 300;
1229 /* waiting for hardware to report that the stream is out of reset */
40830813
DR		 1230 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1231 SD_CTL_STREAM_RESET) && --timeout)
1da177e4 1232 ;
fa00e046
JK		 1233
1234 /* reset first position - may not be synced with hw at this time */
1235 *azx_dev->posbuf = 0;
1dddab40 1236}
1da177e4 1237
1dddab40
TI		 1238/*
1239 * set up the SD for streaming
1240 */
1241static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1242{
27fe48d9 1243 unsigned int val;
1dddab40
TI		 1244 /* make sure the run bit is zero for SD */
1245 azx_stream_clear(chip, azx_dev);
1da177e4 1246 /* program the stream_tag */
40830813 1247 val = azx_sd_readl(chip, azx_dev, SD_CTL);
27fe48d9
TI		 1248 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1249 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1250 if (!azx_snoop(chip))
1251 val |= SD_CTL_TRAFFIC_PRIO;
40830813 1252 azx_sd_writel(chip, azx_dev, SD_CTL, val);
1da177e4
LT		 1253
1254 /* program the length of samples in cyclic buffer */
40830813 1255 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
1da177e4
LT		 1256
1257 /* program the stream format */
1258 /* this value needs to be the same as the one programmed */
40830813 1259 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
1da177e4
LT		 1260
1261 /* program the stream LVI (last valid index) of the BDL */
40830813 1262 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
1da177e4
LT		 1263
1264 /* program the BDL address */
1265 /* lower BDL address */
40830813 1266 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1267 /* upper BDL address */
40830813
DR		 1268 azx_sd_writel(chip, azx_dev, SD_BDLPU,
1269 upper_32_bits(azx_dev->bdl.addr));
1da177e4 1270
0be3b5d3 1271 /* enable the position buffer */
4cb36310
DH		 1272 if (chip->position_fix[0] != POS_FIX_LPIB ||
1273 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1274 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1275 azx_writel(chip, DPLBASE,
1276 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1277 }
c74db86b 1278
1da177e4 1279 /* set the interrupt enable bits in the descriptor control register */
40830813
DR		 1280 azx_sd_writel(chip, azx_dev, SD_CTL,
1281 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1282
1283 return 0;
1284}
1285
6ce4a3bc
TI		 1286/*
1287 * Probe the given codec address
1288 */
1289static int probe_codec(struct azx *chip, int addr)
1290{
1291 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1292 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1293 unsigned int res;
1294
a678cdee 1295 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1296 chip->probing = 1;
1297 azx_send_cmd(chip->bus, cmd);
deadff16 1298 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1299 chip->probing = 0;
a678cdee 1300 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1301 if (res == -1)
1302 return -EIO;
4e76a883 1303 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1304 return 0;
1305}
1306
33fa35ed
TI		 1307static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1308 struct hda_pcm *cpcm);
6ce4a3bc 1309static void azx_stop_chip(struct azx *chip);
1da177e4 1310
8dd78330
TI		 1311static void azx_bus_reset(struct hda_bus *bus)
1312{
1313 struct azx *chip = bus->private_data;
8dd78330
TI		 1314
1315 bus->in_reset = 1;
1316 azx_stop_chip(chip);
cd508fe5 1317 azx_init_chip(chip, 1);
65f75983 1318#ifdef CONFIG_PM
8dd78330 1319 if (chip->initialized) {
01b65bfb
TI		 1320 struct azx_pcm *p;
1321 list_for_each_entry(p, &chip->pcm_list, list)
1322 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1323 snd_hda_suspend(chip->bus);
1324 snd_hda_resume(chip->bus);
1325 }
65f75983 1326#endif
8dd78330
TI		 1327 bus->in_reset = 0;
1328}
1329
26a6cb6c
DH		 1330static int get_jackpoll_interval(struct azx *chip)
1331{
1332 int i = jackpoll_ms[chip->dev_index];
1333 unsigned int j;
1334 if (i == 0)
1335 return 0;
1336 if (i < 50 || i > 60000)
1337 j = 0;
1338 else
1339 j = msecs_to_jiffies(i);
1340 if (j == 0)
4e76a883
TI		 1341 dev_warn(chip->card->dev,
1342 "jackpoll_ms value out of range: %d\n", i);
26a6cb6c
DH		 1343 return j;
1344}
1345
1da177e4
LT		 1346/*
1347 * Codec initialization
1348 */
1349
2f5983f2 1350/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1351static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1352 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1353 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1354};
1355
48c8b0eb 1356static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1357{
1358 struct hda_bus_template bus_temp;
34c25350
TI		 1359 int c, codecs, err;
1360 int max_slots;
1da177e4
LT		 1361
1362 memset(&bus_temp, 0, sizeof(bus_temp));
1363 bus_temp.private_data = chip;
1364 bus_temp.modelname = model;
1365 bus_temp.pci = chip->pci;
111d3af5
TI		 1366 bus_temp.ops.command = azx_send_cmd;
1367 bus_temp.ops.get_response = azx_get_response;
176d5335 1368 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1369 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1370#ifdef CONFIG_PM
11cd41b8 1371 bus_temp.power_save = &power_save;
cb53c626
TI		 1372 bus_temp.ops.pm_notify = azx_power_notify;
1373#endif
1d1a4564
TI		 1374#ifdef CONFIG_SND_HDA_DSP_LOADER
1375 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1376 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1377 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1378#endif
1da177e4 1379
d01ce99f
TI		 1380 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1381 if (err < 0)
1da177e4
LT		 1382 return err;
1383
9477c58e 1384 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
4e76a883 1385 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
dc9c8e21 1386 chip->bus->needs_damn_long_delay = 1;
9477c58e 1387 }
dc9c8e21 1388
34c25350 1389 codecs = 0;
2f5983f2
TI		 1390 max_slots = azx_max_codecs[chip->driver_type];
1391 if (!max_slots)
7445dfc1 1392 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1393
1394 /* First try to probe all given codec slots */
1395 for (c = 0; c < max_slots; c++) {
f1eaaeec 1396 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1397 if (probe_codec(chip, c) < 0) {
1398 /* Some BIOSen give you wrong codec addresses
1399 * that don't exist
1400 */
4e76a883
TI		 1401 dev_warn(chip->card->dev,
1402 "Codec #%d probe error; disabling it...\n", c);
6ce4a3bc
TI		 1403 chip->codec_mask &= ~(1 << c);
1404 /* More badly, accessing to a non-existing
1405 * codec often screws up the controller chip,
2448158e 1406 * and disturbs the further communications.
6ce4a3bc
TI		 1407 * Thus if an error occurs during probing,
1408 * better to reset the controller chip to
1409 * get back to the sanity state.
1410 */
1411 azx_stop_chip(chip);
cd508fe5 1412 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1413 }
1414 }
1415 }
1416
d507cd66
TI		 1417 /* AMD chipsets often cause the communication stalls upon certain
1418 * sequence like the pin-detection. It seems that forcing the synced
1419 * access works around the stall. Grrr...
1420 */
9477c58e 1421 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
4e76a883 1422 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
d507cd66
TI		 1423 chip->bus->sync_write = 1;
1424 chip->bus->allow_bus_reset = 1;
1425 }
1426
6ce4a3bc 1427 /* Then create codec instances */
34c25350 1428 for (c = 0; c < max_slots; c++) {
f1eaaeec 1429 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1430 struct hda_codec *codec;
a1e21c90 1431 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1432 if (err < 0)
1433 continue;
26a6cb6c 1434 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1435 codec->beep_mode = chip->beep_mode;
1da177e4 1436 codecs++;
19a982b6
TI		 1437 }
1438 }
1439 if (!codecs) {
4e76a883 1440 dev_err(chip->card->dev, "no codecs initialized\n");
1da177e4
LT		 1441 return -ENXIO;
1442 }
a1e21c90
TI		 1443 return 0;
1444}
1da177e4 1445
a1e21c90 1446/* configure each codec instance */
e23e7a14 1447static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1448{
1449 struct hda_codec *codec;
1450 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1451 snd_hda_codec_configure(codec);
1452 }
1da177e4
LT		 1453 return 0;
1454}
1455
1456
1457/*
1458 * PCM support
1459 */
1460
1461/* assign a stream for the PCM */
ef18bede
WF		 1462static inline struct azx_dev *
1463azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1464{
07e4ca50 1465 int dev, i, nums;
ef18bede 1466 struct azx_dev *res = NULL;
d5cf9911
TI		 1467 /* make a non-zero unique key for the substream */
1468 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1469 (substream->stream + 1);
ef18bede
WF		 1470
1471 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1472 dev = chip->playback_index_offset;
1473 nums = chip->playback_streams;
1474 } else {
1475 dev = chip->capture_index_offset;
1476 nums = chip->capture_streams;
1477 }
eb49faa6
TI		 1478 for (i = 0; i < nums; i++, dev++) {
1479 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1480 dsp_lock(azx_dev);
1481 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1482 res = azx_dev;
1483 if (res->assigned_key == key) {
1484 res->opened = 1;
1485 res->assigned_key = key;
1486 dsp_unlock(azx_dev);
1487 return azx_dev;
1488 }
1da177e4 1489 }
eb49faa6
TI		 1490 dsp_unlock(azx_dev);
1491 }
ef18bede 1492 if (res) {
eb49faa6 1493 dsp_lock(res);
ef18bede 1494 res->opened = 1;
d5cf9911 1495 res->assigned_key = key;
eb49faa6 1496 dsp_unlock(res);
ef18bede
WF		 1497 }
1498 return res;
1da177e4
LT		 1499}
1500
1501/* release the assigned stream */
a98f90fd 1502static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1503{
1504 azx_dev->opened = 0;
1505}
1506
5d890f59
PLB		 1507static cycle_t azx_cc_read(const struct cyclecounter *cc)
1508{
1509 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1510 struct snd_pcm_substream *substream = azx_dev->substream;
1511 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1512 struct azx *chip = apcm->chip;
1513
1514 return azx_readl(chip, WALLCLK);
1515}
1516
1517static void azx_timecounter_init(struct snd_pcm_substream *substream,
1518 bool force, cycle_t last)
1519{
1520 struct azx_dev *azx_dev = get_azx_dev(substream);
1521 struct timecounter *tc = &azx_dev->azx_tc;
1522 struct cyclecounter *cc = &azx_dev->azx_cc;
1523 u64 nsec;
1524
1525 cc->read = azx_cc_read;
1526 cc->mask = CLOCKSOURCE_MASK(32);
1527
1528 /*
1529 * Converting from 24 MHz to ns means applying a 125/3 factor.
1530 * To avoid any saturation issues in intermediate operations,
1531 * the 125 factor is applied first. The division is applied
1532 * last after reading the timecounter value.
1533 * Applying the 1/3 factor as part of the multiplication
1534 * requires at least 20 bits for a decent precision, however
1535 * overflows occur after about 4 hours or less, not a option.
1536 */
1537
1538 cc->mult = 125; /* saturation after 195 years */
1539 cc->shift = 0;
1540
1541 nsec = 0; /* audio time is elapsed time since trigger */
1542 timecounter_init(tc, cc, nsec);
1543 if (force)
1544 /*
1545 * force timecounter to use predefined value,
1546 * used for synchronized starts
1547 */
1548 tc->cycle_last = last;
1549}
1550
ae03bbb8 1551static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1552 u64 nsec)
1553{
1554 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1555 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1556 u64 codec_frames, codec_nsecs;
1557
1558 if (!hinfo->ops.get_delay)
1559 return nsec;
1560
1561 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1562 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1563 substream->runtime->rate);
1564
ae03bbb8
DR		 1565 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1566 return nsec + codec_nsecs;
1567
78daea29
DR		 1568 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1569}
1570
5d890f59
PLB		 1571static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1572 struct timespec *ts)
1573{
1574 struct azx_dev *azx_dev = get_azx_dev(substream);
1575 u64 nsec;
1576
1577 nsec = timecounter_read(&azx_dev->azx_tc);
1578 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1579 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1580
1581 *ts = ns_to_timespec(nsec);
1582
1583 return 0;
1584}
1585
a98f90fd 1586static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1587 .info = (SNDRV_PCM_INFO_MMAP |
1588 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1589 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1590 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1591 /* No full-resume yet implemented */
1592 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1593 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1594 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1595 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1596 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1597 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1598 .rates = SNDRV_PCM_RATE_48000,
1599 .rate_min = 48000,
1600 .rate_max = 48000,
1601 .channels_min = 2,
1602 .channels_max = 2,
1603 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1604 .period_bytes_min = 128,
1605 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1606 .periods_min = 2,
1607 .periods_max = AZX_MAX_FRAG,
1608 .fifo_size = 0,
1609};
1610
a98f90fd 1611static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1612{
1613 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1614 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1615 struct azx *chip = apcm->chip;
1616 struct azx_dev *azx_dev;
1617 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1618 unsigned long flags;
1619 int err;
2ae66c26 1620 int buff_step;
1da177e4 1621
62932df8 1622 mutex_lock(&chip->open_mutex);
ef18bede 1623 azx_dev = azx_assign_device(chip, substream);
1da177e4 1624 if (azx_dev == NULL) {
62932df8 1625 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1626 return -EBUSY;
1627 }
1628 runtime->hw = azx_pcm_hw;
1629 runtime->hw.channels_min = hinfo->channels_min;
1630 runtime->hw.channels_max = hinfo->channels_max;
1631 runtime->hw.formats = hinfo->formats;
1632 runtime->hw.rates = hinfo->rates;
1633 snd_pcm_limit_hw_rates(runtime);
1634 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 1635
1636 /* avoid wrap-around with wall-clock */
1637 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1638 20,
1639 178000000);
1640
52409aa6 1641 if (chip->align_buffer_size)
2ae66c26
PLB		 1642 /* constrain buffer sizes to be multiple of 128
1643 bytes. This is more efficient in terms of memory
1644 access but isn't required by the HDA spec and
1645 prevents users from specifying exact period/buffer
1646 sizes. For example for 44.1kHz, a period size set
1647 to 20ms will be rounded to 19.59ms. */
1648 buff_step = 128;
1649 else
1650 /* Don't enforce steps on buffer sizes, still need to
1651 be multiple of 4 bytes (HDA spec). Tested on Intel
1652 HDA controllers, may not work on all devices where
1653 option needs to be disabled */
1654 buff_step = 4;
1655
5f1545bc 1656 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1657 buff_step);
5f1545bc 1658 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1659 buff_step);
b4a91cf0 1660 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1661 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1662 if (err < 0) {
1da177e4 1663 azx_release_device(azx_dev);
cb53c626 1664 snd_hda_power_down(apcm->codec);
62932df8 1665 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1666 return err;
1667 }
70d321e6 1668 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1669 /* sanity check */
1670 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1671 snd_BUG_ON(!runtime->hw.channels_max) ||
1672 snd_BUG_ON(!runtime->hw.formats) ||
1673 snd_BUG_ON(!runtime->hw.rates)) {
1674 azx_release_device(azx_dev);
1675 hinfo->ops.close(hinfo, apcm->codec, substream);
1676 snd_hda_power_down(apcm->codec);
1677 mutex_unlock(&chip->open_mutex);
1678 return -EINVAL;
1679 }
5d890f59
PLB		 1680
1681 /* disable WALLCLOCK timestamps for capture streams
1682 until we figure out how to handle digital inputs */
1683 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1684 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1685
1da177e4
LT		 1686 spin_lock_irqsave(&chip->reg_lock, flags);
1687 azx_dev->substream = substream;
1688 azx_dev->running = 0;
1689 spin_unlock_irqrestore(&chip->reg_lock, flags);
1690
1691 runtime->private_data = azx_dev;
850f0e52 1692 snd_pcm_set_sync(substream);
62932df8 1693 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1694 return 0;
1695}
1696
a98f90fd 1697static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1698{
1699 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1700 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1701 struct azx *chip = apcm->chip;
1702 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1703 unsigned long flags;
1704
62932df8 1705 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1706 spin_lock_irqsave(&chip->reg_lock, flags);
1707 azx_dev->substream = NULL;
1708 azx_dev->running = 0;
1709 spin_unlock_irqrestore(&chip->reg_lock, flags);
1710 azx_release_device(azx_dev);
1711 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1712 snd_hda_power_down(apcm->codec);
62932df8 1713 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1714 return 0;
1715}
1716
d01ce99f
TI		 1717static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1718 struct snd_pcm_hw_params *hw_params)
1da177e4 1719{
27fe48d9
TI		 1720 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1721 struct azx *chip = apcm->chip;
97b71c94 1722 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1723 int ret;
97b71c94 1724
eb49faa6
TI		 1725 dsp_lock(azx_dev);
1726 if (dsp_is_locked(azx_dev)) {
1727 ret = -EBUSY;
1728 goto unlock;
1729 }
1730
9ddf1aeb 1731 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 1732 azx_dev->bufsize = 0;
1733 azx_dev->period_bytes = 0;
1734 azx_dev->format_val = 0;
27fe48d9 1735 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1736 params_buffer_bytes(hw_params));
27fe48d9 1737 if (ret < 0)
eb49faa6 1738 goto unlock;
9ddf1aeb 1739 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 1740 unlock:
1741 dsp_unlock(azx_dev);
27fe48d9 1742 return ret;
1da177e4
LT		 1743}
1744
a98f90fd 1745static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1746{
1747 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1748 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1749 struct azx *chip = apcm->chip;
1da177e4
LT		 1750 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1751
1752 /* reset BDL address */
eb49faa6
TI		 1753 dsp_lock(azx_dev);
1754 if (!dsp_is_locked(azx_dev)) {
40830813
DR		 1755 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1756 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1757 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
eb49faa6
TI		 1758 azx_dev->bufsize = 0;
1759 azx_dev->period_bytes = 0;
1760 azx_dev->format_val = 0;
1761 }
1da177e4 1762
eb541337 1763 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1764
9ddf1aeb 1765 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 1766 azx_dev->prepared = 0;
1767 dsp_unlock(azx_dev);
1da177e4
LT		 1768 return snd_pcm_lib_free_pages(substream);
1769}
1770
a98f90fd 1771static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1772{
1773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1774 struct azx *chip = apcm->chip;
1775 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1776 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1777 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1778 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1779 int err;
7c935976
SW		 1780 struct hda_spdif_out *spdif =
1781 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1782 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1783
eb49faa6
TI		 1784 dsp_lock(azx_dev);
1785 if (dsp_is_locked(azx_dev)) {
1786 err = -EBUSY;
1787 goto unlock;
1788 }
1789
fa00e046 1790 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1791 format_val = snd_hda_calc_stream_format(runtime->rate,
1792 runtime->channels,
1793 runtime->format,
32c168c8 1794 hinfo->maxbps,
7c935976 1795 ctls);
97b71c94 1796 if (!format_val) {
4e76a883
TI		 1797 dev_err(chip->card->dev,
1798 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1799 runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 1800 err = -EINVAL;
1801 goto unlock;
1da177e4
LT		 1802 }
1803
97b71c94
TI		 1804 bufsize = snd_pcm_lib_buffer_bytes(substream);
1805 period_bytes = snd_pcm_lib_period_bytes(substream);
1806
4e76a883
TI		 1807 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1808 bufsize, format_val);
97b71c94
TI		 1809
1810 if (bufsize != azx_dev->bufsize ||
1811 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 1812 format_val != azx_dev->format_val ||
1813 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 1814 azx_dev->bufsize = bufsize;
1815 azx_dev->period_bytes = period_bytes;
1816 azx_dev->format_val = format_val;
915bf29e 1817 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 1818 err = azx_setup_periods(chip, substream, azx_dev);
1819 if (err < 0)
eb49faa6 1820 goto unlock;
97b71c94
TI		 1821 }
1822
e8648e5e
TI		 1823 /* when LPIB delay correction gives a small negative value,
1824 * we ignore it; currently set the threshold statically to
1825 * 64 frames
1826 */
1827 if (runtime->period_size > 64)
1828 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
1829 else
1830 azx_dev->delay_negative_threshold = 0;
1831
e5463720
JK		 1832 /* wallclk has 24Mhz clock source */
1833 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1834 runtime->rate) * 1000);
1da177e4
LT		 1835 azx_setup_controller(chip, azx_dev);
1836 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
40830813
DR		 1837 azx_dev->fifo_size =
1838 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
1da177e4
LT		 1839 else
1840 azx_dev->fifo_size = 0;
1841
62b7e5e0
TI		 1842 stream_tag = azx_dev->stream_tag;
1843 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1844 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1845 stream_tag > chip->capture_streams)
1846 stream_tag -= chip->capture_streams;
eb49faa6 1847 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1848 azx_dev->format_val, substream);
eb49faa6
TI		 1849
1850 unlock:
1851 if (!err)
1852 azx_dev->prepared = 1;
1853 dsp_unlock(azx_dev);
1854 return err;
1da177e4
LT		 1855}
1856
a98f90fd 1857static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1858{
1859 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1860 struct azx *chip = apcm->chip;
850f0e52
TI		 1861 struct azx_dev *azx_dev;
1862 struct snd_pcm_substream *s;
fa00e046 1863 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1864 int nwait, timeout;
1da177e4 1865
1a8506d4
TI		 1866 azx_dev = get_azx_dev(substream);
1867 trace_azx_pcm_trigger(chip, azx_dev, cmd);
1868
eb49faa6
TI		 1869 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
1870 return -EPIPE;
1871
1da177e4 1872 switch (cmd) {
fa00e046
JK		 1873 case SNDRV_PCM_TRIGGER_START:
1874 rstart = 1;
1da177e4
LT		 1875 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1876 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1877 start = 1;
1da177e4
LT		 1878 break;
1879 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1880 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1881 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1882 start = 0;
1da177e4
LT		 1883 break;
1884 default:
850f0e52
TI		 1885 return -EINVAL;
1886 }
1887
1888 snd_pcm_group_for_each_entry(s, substream) {
1889 if (s->pcm->card != substream->pcm->card)
1890 continue;
1891 azx_dev = get_azx_dev(s);
1892 sbits |= 1 << azx_dev->index;
1893 nsync++;
1894 snd_pcm_trigger_done(s, substream);
1895 }
1896
1897 spin_lock(&chip->reg_lock);
172d3b20
PLB		 1898
1899 /* first, set SYNC bits of corresponding streams */
1900 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1901 azx_writel(chip, OLD_SSYNC,
1902 azx_readl(chip, OLD_SSYNC) | sbits);
1903 else
1904 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1905
850f0e52
TI		 1906 snd_pcm_group_for_each_entry(s, substream) {
1907 if (s->pcm->card != substream->pcm->card)
1908 continue;
1909 azx_dev = get_azx_dev(s);
e5463720
JK		 1910 if (start) {
1911 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1912 if (!rstart)
1913 azx_dev->start_wallclk -=
1914 azx_dev->period_wallclk;
850f0e52 1915 azx_stream_start(chip, azx_dev);
e5463720 1916 } else {
850f0e52 1917 azx_stream_stop(chip, azx_dev);
e5463720 1918 }
850f0e52 1919 azx_dev->running = start;
1da177e4
LT		 1920 }
1921 spin_unlock(&chip->reg_lock);
850f0e52 1922 if (start) {
850f0e52
TI		 1923 /* wait until all FIFOs get ready */
1924 for (timeout = 5000; timeout; timeout--) {
1925 nwait = 0;
1926 snd_pcm_group_for_each_entry(s, substream) {
1927 if (s->pcm->card != substream->pcm->card)
1928 continue;
1929 azx_dev = get_azx_dev(s);
40830813 1930 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
850f0e52
TI		 1931 SD_STS_FIFO_READY))
1932 nwait++;
1933 }
1934 if (!nwait)
1935 break;
1936 cpu_relax();
1937 }
1938 } else {
1939 /* wait until all RUN bits are cleared */
1940 for (timeout = 5000; timeout; timeout--) {
1941 nwait = 0;
1942 snd_pcm_group_for_each_entry(s, substream) {
1943 if (s->pcm->card != substream->pcm->card)
1944 continue;
1945 azx_dev = get_azx_dev(s);
40830813 1946 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
850f0e52
TI		 1947 SD_CTL_DMA_START)
1948 nwait++;
1949 }
1950 if (!nwait)
1951 break;
1952 cpu_relax();
1953 }
1da177e4 1954 }
172d3b20
PLB		 1955 spin_lock(&chip->reg_lock);
1956 /* reset SYNC bits */
1957 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1958 azx_writel(chip, OLD_SSYNC,
1959 azx_readl(chip, OLD_SSYNC) & ~sbits);
1960 else
1961 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 1962 if (start) {
1963 azx_timecounter_init(substream, 0, 0);
1964 if (nsync > 1) {
1965 cycle_t cycle_last;
1966
1967 /* same start cycle for master and group */
1968 azx_dev = get_azx_dev(substream);
1969 cycle_last = azx_dev->azx_tc.cycle_last;
1970
1971 snd_pcm_group_for_each_entry(s, substream) {
1972 if (s->pcm->card != substream->pcm->card)
1973 continue;
1974 azx_timecounter_init(s, 1, cycle_last);
1975 }
1976 }
1977 }
172d3b20 1978 spin_unlock(&chip->reg_lock);
850f0e52 1979 return 0;
1da177e4
LT		 1980}
1981
0e153474
JC		 1982/* get the current DMA position with correction on VIA chips */
1983static unsigned int azx_via_get_position(struct azx *chip,
1984 struct azx_dev *azx_dev)
1985{
1986 unsigned int link_pos, mini_pos, bound_pos;
1987 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1988 unsigned int fifo_size;
1989
40830813 1990 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
b4a655e8 1991 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 1992 /* Playback, no problem using link position */
1993 return link_pos;
1994 }
1995
1996 /* Capture */
1997 /* For new chipset,
1998 * use mod to get the DMA position just like old chipset
1999 */
2000 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2001 mod_dma_pos %= azx_dev->period_bytes;
2002
2003 /* azx_dev->fifo_size can't get FIFO size of in stream.
2004 * Get from base address + offset.
2005 */
2006 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2007
2008 if (azx_dev->insufficient) {
2009 /* Link position never gather than FIFO size */
2010 if (link_pos <= fifo_size)
2011 return 0;
2012
2013 azx_dev->insufficient = 0;
2014 }
2015
2016 if (link_pos <= fifo_size)
2017 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2018 else
2019 mini_pos = link_pos - fifo_size;
2020
2021 /* Find nearest previous boudary */
2022 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2023 mod_link_pos = link_pos % azx_dev->period_bytes;
2024 if (mod_link_pos >= fifo_size)
2025 bound_pos = link_pos - mod_link_pos;
2026 else if (mod_dma_pos >= mod_mini_pos)
2027 bound_pos = mini_pos - mod_mini_pos;
2028 else {
2029 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2030 if (bound_pos >= azx_dev->bufsize)
2031 bound_pos = 0;
2032 }
2033
2034 /* Calculate real DMA position we want */
2035 return bound_pos + mod_dma_pos;
2036}
2037
9ad593f6 2038static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2039 struct azx_dev *azx_dev,
2040 bool with_check)
1da177e4 2041{
21229613
TI		 2042 struct snd_pcm_substream *substream = azx_dev->substream;
2043 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2044 unsigned int pos;
21229613
TI		 2045 int stream = substream->stream;
2046 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2047 int delay = 0;
1da177e4 2048
4cb36310
DH		 2049 switch (chip->position_fix[stream]) {
2050 case POS_FIX_LPIB:
2051 /* read LPIB */
40830813 2052 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
4cb36310
DH		 2053 break;
2054 case POS_FIX_VIACOMBO:
0e153474 2055 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2056 break;
2057 default:
2058 /* use the position buffer */
2059 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2060 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a 2061 if (!pos || pos == (u32)-1) {
4e76a883
TI		 2062 dev_info(chip->card->dev,
2063 "Invalid position buffer, using LPIB read method instead.\n");
a810364a 2064 chip->position_fix[stream] = POS_FIX_LPIB;
40830813 2065 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
a810364a
TI		 2066 } else
2067 chip->position_fix[stream] = POS_FIX_POSBUF;
2068 }
2069 break;
c74db86b 2070 }
4cb36310 2071
1da177e4
LT		 2072 if (pos >= azx_dev->bufsize)
2073 pos = 0;
90accc58
PLB		 2074
2075 /* calculate runtime delay from LPIB */
21229613 2076 if (substream->runtime &&
90accc58
PLB		 2077 chip->position_fix[stream] == POS_FIX_POSBUF &&
2078 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
40830813 2079 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
90accc58
PLB		 2080 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2081 delay = pos - lpib_pos;
2082 else
2083 delay = lpib_pos - pos;
e8648e5e
TI		 2084 if (delay < 0) {
2085 if (delay >= azx_dev->delay_negative_threshold)
2086 delay = 0;
2087 else
2088 delay += azx_dev->bufsize;
2089 }
90accc58 2090 if (delay >= azx_dev->period_bytes) {
4e76a883
TI		 2091 dev_info(chip->card->dev,
2092 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2093 delay, azx_dev->period_bytes);
1f04661f
TI		 2094 delay = 0;
2095 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2096 }
21229613 2097 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2098 }
21229613
TI		 2099
2100 if (substream->runtime) {
2101 if (hinfo->ops.get_delay)
2102 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2103 substream);
2104 substream->runtime->delay = delay;
2105 }
2106
1a8506d4 2107 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2108 return pos;
2109}
2110
2111static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2112{
2113 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2114 struct azx *chip = apcm->chip;
2115 struct azx_dev *azx_dev = get_azx_dev(substream);
2116 return bytes_to_frames(substream->runtime,
798cb7e8 2117 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2118}
2119
2120/*
2121 * Check whether the current DMA position is acceptable for updating
2122 * periods. Returns non-zero if it's OK.
2123 *
2124 * Many HD-audio controllers appear pretty inaccurate about
2125 * the update-IRQ timing. The IRQ is issued before actually the
2126 * data is processed. So, we need to process it afterwords in a
2127 * workqueue.
2128 */
2129static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2130{
e5463720 2131 u32 wallclk;
9ad593f6
TI		 2132 unsigned int pos;
2133
f48f606d
JK		 2134 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2135 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2136 return -1; /* bogus (too early) interrupt */
fa00e046 2137
798cb7e8 2138 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2139
d6d8bf54
TI		 2140 if (WARN_ONCE(!azx_dev->period_bytes,
2141 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2142 return -1; /* this shouldn't happen! */
edb39935 2143 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2144 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2145 /* NG - it's below the first next period boundary */
2146 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2147 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2148 return 1; /* OK, it's fine */
2149}
2150
2151/*
2152 * The work for pending PCM period updates.
2153 */
2154static void azx_irq_pending_work(struct work_struct *work)
2155{
2156 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2157 int i, pending, ok;
9ad593f6 2158
a6a950a8 2159 if (!chip->irq_pending_warned) {
4e76a883
TI		 2160 dev_info(chip->card->dev,
2161 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
2162 chip->card->number);
a6a950a8
TI		 2163 chip->irq_pending_warned = 1;
2164 }
2165
9ad593f6
TI		 2166 for (;;) {
2167 pending = 0;
2168 spin_lock_irq(&chip->reg_lock);
2169 for (i = 0; i < chip->num_streams; i++) {
2170 struct azx_dev *azx_dev = &chip->azx_dev[i];
2171 if (!azx_dev->irq_pending ||
2172 !azx_dev->substream ||
2173 !azx_dev->running)
2174 continue;
e5463720
JK		 2175 ok = azx_position_ok(chip, azx_dev);
2176 if (ok > 0) {
9ad593f6
TI		 2177 azx_dev->irq_pending = 0;
2178 spin_unlock(&chip->reg_lock);
2179 snd_pcm_period_elapsed(azx_dev->substream);
2180 spin_lock(&chip->reg_lock);
e5463720
JK		 2181 } else if (ok < 0) {
2182 pending = 0; /* too early */
9ad593f6
TI		 2183 } else
2184 pending++;
2185 }
2186 spin_unlock_irq(&chip->reg_lock);
2187 if (!pending)
2188 return;
08af495f 2189 msleep(1);
9ad593f6
TI		 2190 }
2191}
2192
2193/* clear irq_pending flags and assure no on-going workq */
2194static void azx_clear_irq_pending(struct azx *chip)
2195{
2196 int i;
2197
2198 spin_lock_irq(&chip->reg_lock);
2199 for (i = 0; i < chip->num_streams; i++)
2200 chip->azx_dev[i].irq_pending = 0;
2201 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2202}
2203
27fe48d9
TI		 2204#ifdef CONFIG_X86
2205static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2206 struct vm_area_struct *area)
2207{
2208 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2209 struct azx *chip = apcm->chip;
2210 if (!azx_snoop(chip))
2211 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2212 return snd_pcm_lib_default_mmap(substream, area);
2213}
2214#else
2215#define azx_pcm_mmap NULL
2216#endif
2217
a98f90fd 2218static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2219 .open = azx_pcm_open,
2220 .close = azx_pcm_close,
2221 .ioctl = snd_pcm_lib_ioctl,
2222 .hw_params = azx_pcm_hw_params,
2223 .hw_free = azx_pcm_hw_free,
2224 .prepare = azx_pcm_prepare,
2225 .trigger = azx_pcm_trigger,
2226 .pointer = azx_pcm_pointer,
5d890f59 2227 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2228 .mmap = azx_pcm_mmap,
4ce107b9 2229 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2230};
2231
a98f90fd 2232static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2233{
176d5335
TI		 2234 struct azx_pcm *apcm = pcm->private_data;
2235 if (apcm) {
01b65bfb 2236 list_del(&apcm->list);
176d5335
TI		 2237 kfree(apcm);
2238 }
1da177e4
LT		 2239}
2240
acfa634f
TI		 2241#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2242
176d5335 2243static int
33fa35ed
TI		 2244azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2245 struct hda_pcm *cpcm)
1da177e4 2246{
33fa35ed 2247 struct azx *chip = bus->private_data;
a98f90fd 2248 struct snd_pcm *pcm;
1da177e4 2249 struct azx_pcm *apcm;
176d5335 2250 int pcm_dev = cpcm->device;
acfa634f 2251 unsigned int size;
176d5335 2252 int s, err;
1da177e4 2253
01b65bfb
TI		 2254 list_for_each_entry(apcm, &chip->pcm_list, list) {
2255 if (apcm->pcm->device == pcm_dev) {
4e76a883
TI		 2256 dev_err(chip->card->dev, "PCM %d already exists\n",
2257 pcm_dev);
01b65bfb
TI		 2258 return -EBUSY;
2259 }
176d5335
TI		 2260 }
2261 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2262 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2263 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2264 &pcm);
2265 if (err < 0)
2266 return err;
18cb7109 2267 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2268 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2269 if (apcm == NULL)
2270 return -ENOMEM;
2271 apcm->chip = chip;
01b65bfb 2272 apcm->pcm = pcm;
1da177e4 2273 apcm->codec = codec;
1da177e4
LT		 2274 pcm->private_data = apcm;
2275 pcm->private_free = azx_pcm_free;
176d5335
TI		 2276 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2277 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2278 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2279 cpcm->pcm = pcm;
2280 for (s = 0; s < 2; s++) {
2281 apcm->hinfo[s] = &cpcm->stream[s];
2282 if (cpcm->stream[s].substreams)
2283 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2284 }
2285 /* buffer pre-allocation */
acfa634f
TI		 2286 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2287 if (size > MAX_PREALLOC_SIZE)
2288 size = MAX_PREALLOC_SIZE;
4ce107b9 2289 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2290 snd_dma_pci_data(chip->pci),
acfa634f 2291 size, MAX_PREALLOC_SIZE);
13aeaf68
TI		 2292 /* link to codec */
2293 pcm->dev = &codec->dev;
1da177e4
LT		 2294 return 0;
2295}
2296
2297/*
2298 * mixer creation - all stuff is implemented in hda module
2299 */
e23e7a14 2300static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2301{
2302 return snd_hda_build_controls(chip->bus);
2303}
2304
2305
2306/*
2307 * initialize SD streams
2308 */
e23e7a14 2309static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2310{
2311 int i;
2312
2313 /* initialize each stream (aka device)
d01ce99f
TI		 2314 * assign the starting bdl address to each stream (device)
2315 * and initialize
1da177e4 2316 */
07e4ca50 2317 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2318 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2319 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2320 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2321 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2322 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2323 azx_dev->sd_int_sta_mask = 1 << i;
2324 /* stream tag: must be non-zero and unique */
2325 azx_dev->index = i;
2326 azx_dev->stream_tag = i + 1;
2327 }
2328
2329 return 0;
2330}
2331
68e7fffc
TI		 2332static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2333{
437a5a46
TI		 2334 if (request_irq(chip->pci->irq, azx_interrupt,
2335 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2336 KBUILD_MODNAME, chip)) {
4e76a883
TI		 2337 dev_err(chip->card->dev,
2338 "unable to grab IRQ %d, disabling device\n",
2339 chip->pci->irq);
68e7fffc
TI		 2340 if (do_disconnect)
2341 snd_card_disconnect(chip->card);
2342 return -1;
2343 }
2344 chip->irq = chip->pci->irq;
69e13418 2345 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2346 return 0;
2347}
2348
1da177e4 2349
cb53c626
TI		 2350static void azx_stop_chip(struct azx *chip)
2351{
95e99fda 2352 if (!chip->initialized)
cb53c626
TI		 2353 return;
2354
2355 /* disable interrupts */
2356 azx_int_disable(chip);
2357 azx_int_clear(chip);
2358
2359 /* disable CORB/RIRB */
2360 azx_free_cmd_io(chip);
2361
2362 /* disable position buffer */
2363 azx_writel(chip, DPLBASE, 0);
2364 azx_writel(chip, DPUBASE, 0);
2365
2366 chip->initialized = 0;
2367}
2368
1d1a4564
TI		 2369#ifdef CONFIG_SND_HDA_DSP_LOADER
2370/*
2371 * DSP loading code (e.g. for CA0132)
2372 */
2373
2374/* use the first stream for loading DSP */
2375static struct azx_dev *
2376azx_get_dsp_loader_dev(struct azx *chip)
2377{
2378 return &chip->azx_dev[chip->playback_index_offset];
2379}
2380
2381static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2382 unsigned int byte_size,
2383 struct snd_dma_buffer *bufp)
2384{
2385 u32 *bdl;
2386 struct azx *chip = bus->private_data;
2387 struct azx_dev *azx_dev;
2388 int err;
2389
eb49faa6
TI		 2390 azx_dev = azx_get_dsp_loader_dev(chip);
2391
2392 dsp_lock(azx_dev);
2393 spin_lock_irq(&chip->reg_lock);
2394 if (azx_dev->running || azx_dev->locked) {
2395 spin_unlock_irq(&chip->reg_lock);
2396 err = -EBUSY;
2397 goto unlock;
2398 }
2399 azx_dev->prepared = 0;
2400 chip->saved_azx_dev = *azx_dev;
2401 azx_dev->locked = 1;
2402 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2403
2404 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2405 snd_dma_pci_data(chip->pci),
2406 byte_size, bufp);
2407 if (err < 0)
eb49faa6 2408 goto err_alloc;
1d1a4564 2409
b3667bd7 2410 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2411 azx_dev->bufsize = byte_size;
2412 azx_dev->period_bytes = byte_size;
2413 azx_dev->format_val = format;
2414
2415 azx_stream_reset(chip, azx_dev);
2416
2417 /* reset BDL address */
40830813
DR		 2418 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2419 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1d1a4564
TI		 2420
2421 azx_dev->frags = 0;
2422 bdl = (u32 *)azx_dev->bdl.area;
2423 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2424 if (err < 0)
2425 goto error;
2426
2427 azx_setup_controller(chip, azx_dev);
eb49faa6 2428 dsp_unlock(azx_dev);
1d1a4564
TI		 2429 return azx_dev->stream_tag;
2430
2431 error:
b3667bd7
TI		 2432 mark_pages_wc(chip, bufp, false);
2433 snd_dma_free_pages(bufp);
eb49faa6
TI		 2434 err_alloc:
2435 spin_lock_irq(&chip->reg_lock);
2436 if (azx_dev->opened)
2437 *azx_dev = chip->saved_azx_dev;
2438 azx_dev->locked = 0;
2439 spin_unlock_irq(&chip->reg_lock);
2440 unlock:
2441 dsp_unlock(azx_dev);
1d1a4564
TI		 2442 return err;
2443}
2444
2445static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2446{
2447 struct azx *chip = bus->private_data;
2448 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2449
2450 if (start)
2451 azx_stream_start(chip, azx_dev);
2452 else
2453 azx_stream_stop(chip, azx_dev);
2454 azx_dev->running = start;
2455}
2456
2457static void azx_load_dsp_cleanup(struct hda_bus *bus,
2458 struct snd_dma_buffer *dmab)
2459{
2460 struct azx *chip = bus->private_data;
2461 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2462
eb49faa6 2463 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2464 return;
2465
eb49faa6 2466 dsp_lock(azx_dev);
1d1a4564 2467 /* reset BDL address */
40830813
DR		 2468 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2469 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2470 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1d1a4564
TI		 2471 azx_dev->bufsize = 0;
2472 azx_dev->period_bytes = 0;
2473 azx_dev->format_val = 0;
2474
b3667bd7 2475 mark_pages_wc(chip, dmab, false);
1d1a4564 2476 snd_dma_free_pages(dmab);
b3667bd7 2477 dmab->area = NULL;
1d1a4564 2478
eb49faa6
TI		 2479 spin_lock_irq(&chip->reg_lock);
2480 if (azx_dev->opened)
2481 *azx_dev = chip->saved_azx_dev;
2482 azx_dev->locked = 0;
2483 spin_unlock_irq(&chip->reg_lock);
2484 dsp_unlock(azx_dev);
1d1a4564
TI		 2485}
2486#endif /* CONFIG_SND_HDA_DSP_LOADER */
2487
83012a7c 2488#ifdef CONFIG_PM
cb53c626 2489/* power-up/down the controller */
68467f51 2490static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2491{
33fa35ed 2492 struct azx *chip = bus->private_data;
cb53c626 2493
2ea3c6a2
TI		 2494 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2495 return;
2496
68467f51 2497 if (power_up)
b8dfc462
ML		 2498 pm_runtime_get_sync(&chip->pci->dev);
2499 else
2500 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2501}
65fcd41d
TI		 2502
2503static DEFINE_MUTEX(card_list_lock);
2504static LIST_HEAD(card_list);
2505
2506static void azx_add_card_list(struct azx *chip)
2507{
2508 mutex_lock(&card_list_lock);
2509 list_add(&chip->list, &card_list);
2510 mutex_unlock(&card_list_lock);
2511}
2512
2513static void azx_del_card_list(struct azx *chip)
2514{
2515 mutex_lock(&card_list_lock);
2516 list_del_init(&chip->list);
2517 mutex_unlock(&card_list_lock);
2518}
2519
2520/* trigger power-save check at writing parameter */
2521static int param_set_xint(const char *val, const struct kernel_param *kp)
2522{
2523 struct azx *chip;
2524 struct hda_codec *c;
2525 int prev = power_save;
2526 int ret = param_set_int(val, kp);
2527
2528 if (ret || prev == power_save)
2529 return ret;
2530
2531 mutex_lock(&card_list_lock);
2532 list_for_each_entry(chip, &card_list, list) {
2533 if (!chip->bus || chip->disabled)
2534 continue;
2535 list_for_each_entry(c, &chip->bus->codec_list, list)
2536 snd_hda_power_sync(c);
2537 }
2538 mutex_unlock(&card_list_lock);
2539 return 0;
2540}
2541#else
2542#define azx_add_card_list(chip) /* NOP */
2543#define azx_del_card_list(chip) /* NOP */
83012a7c 2544#endif /* CONFIG_PM */
5c0b9bec 2545
7ccbde57 2546#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2547/*
2548 * power management
2549 */
68cb2b55 2550static int azx_suspend(struct device *dev)
1da177e4 2551{
68cb2b55
TI		 2552 struct pci_dev *pci = to_pci_dev(dev);
2553 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2554 struct azx *chip = card->private_data;
01b65bfb 2555 struct azx_pcm *p;
1da177e4 2556
c5c21523
TI		 2557 if (chip->disabled)
2558 return 0;
2559
421a1252 2560 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2561 azx_clear_irq_pending(chip);
01b65bfb
TI		 2562 list_for_each_entry(p, &chip->pcm_list, list)
2563 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2564 if (chip->initialized)
8dd78330 2565 snd_hda_suspend(chip->bus);
cb53c626 2566 azx_stop_chip(chip);
7295b264 2567 azx_enter_link_reset(chip);
30b35399 2568 if (chip->irq >= 0) {
43001c95 2569 free_irq(chip->irq, chip);
30b35399
TI		 2570 chip->irq = -1;
2571 }
68e7fffc 2572 if (chip->msi)
43001c95 2573 pci_disable_msi(chip->pci);
421a1252
TI		 2574 pci_disable_device(pci);
2575 pci_save_state(pci);
68cb2b55 2576 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2577 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2578 hda_display_power(false);
1da177e4
LT		 2579 return 0;
2580}
2581
68cb2b55 2582static int azx_resume(struct device *dev)
1da177e4 2583{
68cb2b55
TI		 2584 struct pci_dev *pci = to_pci_dev(dev);
2585 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2586 struct azx *chip = card->private_data;
1da177e4 2587
c5c21523
TI		 2588 if (chip->disabled)
2589 return 0;
2590
99a2008d
WX		 2591 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2592 hda_display_power(true);
d14a7e0b
TI		 2593 pci_set_power_state(pci, PCI_D0);
2594 pci_restore_state(pci);
30b35399 2595 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 2596 dev_err(chip->card->dev,
2597 "pci_enable_device failed, disabling device\n");
30b35399
TI		 2598 snd_card_disconnect(card);
2599 return -EIO;
2600 }
2601 pci_set_master(pci);
68e7fffc
TI		 2602 if (chip->msi)
2603 if (pci_enable_msi(pci) < 0)
2604 chip->msi = 0;
2605 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2606 return -EIO;
cb53c626 2607 azx_init_pci(chip);
d804ad92 2608
7f30830b 2609 azx_init_chip(chip, 1);
d804ad92 2610
1da177e4 2611 snd_hda_resume(chip->bus);
421a1252 2612 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2613 return 0;
2614}
b8dfc462
ML		 2615#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2616
2617#ifdef CONFIG_PM_RUNTIME
2618static int azx_runtime_suspend(struct device *dev)
2619{
2620 struct snd_card *card = dev_get_drvdata(dev);
2621 struct azx *chip = card->private_data;
2622
246efa4a
DA		 2623 if (chip->disabled)
2624 return 0;
2625
2626 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2627 return 0;
2628
7d4f606c
WX		 2629 /* enable controller wake up event */
2630 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2631 STATESTS_INT_MASK);
2632
b8dfc462 2633 azx_stop_chip(chip);
873ce8ad 2634 azx_enter_link_reset(chip);
b8dfc462 2635 azx_clear_irq_pending(chip);
99a2008d
WX		 2636 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2637 hda_display_power(false);
b8dfc462
ML		 2638 return 0;
2639}
2640
2641static int azx_runtime_resume(struct device *dev)
2642{
2643 struct snd_card *card = dev_get_drvdata(dev);
2644 struct azx *chip = card->private_data;
7d4f606c
WX		 2645 struct hda_bus *bus;
2646 struct hda_codec *codec;
2647 int status;
b8dfc462 2648
246efa4a
DA		 2649 if (chip->disabled)
2650 return 0;
2651
2652 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2653 return 0;
2654
99a2008d
WX		 2655 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2656 hda_display_power(true);
7d4f606c
WX		 2657
2658 /* Read STATESTS before controller reset */
2659 status = azx_readw(chip, STATESTS);
2660
b8dfc462
ML		 2661 azx_init_pci(chip);
2662 azx_init_chip(chip, 1);
7d4f606c
WX		 2663
2664 bus = chip->bus;
2665 if (status && bus) {
2666 list_for_each_entry(codec, &bus->codec_list, list)
2667 if (status & (1 << codec->addr))
2668 queue_delayed_work(codec->bus->workq,
2669 &codec->jackpoll_work, codec->jackpoll_interval);
2670 }
2671
2672 /* disable controller Wake Up event*/
2673 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
2674 ~STATESTS_INT_MASK);
2675
b8dfc462
ML		 2676 return 0;
2677}
6eb827d2
TI		 2678
2679static int azx_runtime_idle(struct device *dev)
2680{
2681 struct snd_card *card = dev_get_drvdata(dev);
2682 struct azx *chip = card->private_data;
2683
246efa4a
DA		 2684 if (chip->disabled)
2685 return 0;
2686
6eb827d2
TI		 2687 if (!power_save_controller ||
2688 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2689 return -EBUSY;
2690
2691 return 0;
2692}
2693
b8dfc462
ML		 2694#endif /* CONFIG_PM_RUNTIME */
2695
2696#ifdef CONFIG_PM
2697static const struct dev_pm_ops azx_pm = {
2698 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 2699 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 2700};
2701
68cb2b55
TI		 2702#define AZX_PM_OPS &azx_pm
2703#else
68cb2b55 2704#define AZX_PM_OPS NULL
b8dfc462 2705#endif /* CONFIG_PM */
1da177e4
LT		 2706
2707
0cbf0098
TI		 2708/*
2709 * reboot notifier for hang-up problem at power-down
2710 */
2711static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2712{
2713 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2714 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2715 azx_stop_chip(chip);
2716 return NOTIFY_OK;
2717}
2718
2719static void azx_notifier_register(struct azx *chip)
2720{
2721 chip->reboot_notifier.notifier_call = azx_halt;
2722 register_reboot_notifier(&chip->reboot_notifier);
2723}
2724
2725static void azx_notifier_unregister(struct azx *chip)
2726{
2727 if (chip->reboot_notifier.notifier_call)
2728 unregister_reboot_notifier(&chip->reboot_notifier);
2729}
2730
48c8b0eb 2731static int azx_probe_continue(struct azx *chip);
a82d51ed 2732
8393ec4a 2733#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 2734static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 2735
a82d51ed
TI		 2736static void azx_vs_set_state(struct pci_dev *pci,
2737 enum vga_switcheroo_state state)
2738{
2739 struct snd_card *card = pci_get_drvdata(pci);
2740 struct azx *chip = card->private_data;
2741 bool disabled;
2742
f4c482a4 2743 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2744 if (chip->init_failed)
2745 return;
2746
2747 disabled = (state == VGA_SWITCHEROO_OFF);
2748 if (chip->disabled == disabled)
2749 return;
2750
2751 if (!chip->bus) {
2752 chip->disabled = disabled;
2753 if (!disabled) {
4e76a883
TI		 2754 dev_info(chip->card->dev,
2755 "Start delayed initialization\n");
5c90680e 2756 if (azx_probe_continue(chip) < 0) {
4e76a883 2757 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 2758 chip->init_failed = true;
2759 }
2760 }
2761 } else {
4e76a883
TI		 2762 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
2763 disabled ? "Disabling" : "Enabling");
a82d51ed 2764 if (disabled) {
246efa4a 2765 pm_runtime_put_sync_suspend(&pci->dev);
68cb2b55 2766 azx_suspend(&pci->dev);
246efa4a
DA		 2767 /* when we get suspended by vga switcheroo we end up in D3cold,
2768 * however we have no ACPI handle, so pci/acpi can't put us there,
2769 * put ourselves there */
2770 pci->current_state = PCI_D3cold;
a82d51ed 2771 chip->disabled = true;
128960a9 2772 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 2773 dev_warn(chip->card->dev,
2774 "Cannot lock devices!\n");
a82d51ed
TI		 2775 } else {
2776 snd_hda_unlock_devices(chip->bus);
246efa4a 2777 pm_runtime_get_noresume(&pci->dev);
a82d51ed 2778 chip->disabled = false;
68cb2b55 2779 azx_resume(&pci->dev);
a82d51ed
TI		 2780 }
2781 }
2782}
2783
2784static bool azx_vs_can_switch(struct pci_dev *pci)
2785{
2786 struct snd_card *card = pci_get_drvdata(pci);
2787 struct azx *chip = card->private_data;
2788
f4c482a4 2789 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2790 if (chip->init_failed)
2791 return false;
2792 if (chip->disabled || !chip->bus)
2793 return true;
2794 if (snd_hda_lock_devices(chip->bus))
2795 return false;
2796 snd_hda_unlock_devices(chip->bus);
2797 return true;
2798}
2799
e23e7a14 2800static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 2801{
2802 struct pci_dev *p = get_bound_vga(chip->pci);
2803 if (p) {
4e76a883
TI		 2804 dev_info(chip->card->dev,
2805 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 2806 chip->use_vga_switcheroo = 1;
2807 pci_dev_put(p);
2808 }
2809}
2810
2811static const struct vga_switcheroo_client_ops azx_vs_ops = {
2812 .set_gpu_state = azx_vs_set_state,
2813 .can_switch = azx_vs_can_switch,
2814};
2815
e23e7a14 2816static int register_vga_switcheroo(struct azx *chip)
a82d51ed 2817{
128960a9
TI		 2818 int err;
2819
a82d51ed
TI		 2820 if (!chip->use_vga_switcheroo)
2821 return 0;
2822 /* FIXME: currently only handling DIS controller
2823 * is there any machine with two switchable HDMI audio controllers?
2824 */
128960a9 2825 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 2826 VGA_SWITCHEROO_DIS,
2827 chip->bus != NULL);
128960a9
TI		 2828 if (err < 0)
2829 return err;
2830 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 2831
2832 /* register as an optimus hdmi audio power domain */
2833 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
128960a9 2834 return 0;
a82d51ed
TI		 2835}
2836#else
2837#define init_vga_switcheroo(chip) /* NOP */
2838#define register_vga_switcheroo(chip) 0
8393ec4a 2839#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2840#endif /* SUPPORT_VGA_SWITCHER */
2841
1da177e4
LT		 2842/*
2843 * destructor
2844 */
a98f90fd 2845static int azx_free(struct azx *chip)
1da177e4 2846{
c67e2228 2847 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 2848 int i;
2849
c67e2228
WX		 2850 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
2851 && chip->running)
2852 pm_runtime_get_noresume(&pci->dev);
2853
65fcd41d
TI		 2854 azx_del_card_list(chip);
2855
0cbf0098
TI		 2856 azx_notifier_unregister(chip);
2857
f4c482a4 2858 chip->init_failed = 1; /* to be sure */
44728e97 2859 complete_all(&chip->probe_wait);
f4c482a4 2860
a82d51ed
TI		 2861 if (use_vga_switcheroo(chip)) {
2862 if (chip->disabled && chip->bus)
2863 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 2864 if (chip->vga_switcheroo_registered)
2865 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 2866 }
2867
ce43fbae 2868 if (chip->initialized) {
9ad593f6 2869 azx_clear_irq_pending(chip);
07e4ca50 2870 for (i = 0; i < chip->num_streams; i++)
1da177e4 2871 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2872 azx_stop_chip(chip);
1da177e4
LT		 2873 }
2874
f000fd80 2875 if (chip->irq >= 0)
1da177e4 2876 free_irq(chip->irq, (void*)chip);
68e7fffc 2877 if (chip->msi)
30b35399 2878 pci_disable_msi(chip->pci);
f079c25a
TI		 2879 if (chip->remap_addr)
2880 iounmap(chip->remap_addr);
1da177e4 2881
4ce107b9
TI		 2882 if (chip->azx_dev) {
2883 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2884 if (chip->azx_dev[i].bdl.area) {
2885 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2886 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2887 }
4ce107b9 2888 }
27fe48d9
TI		 2889 if (chip->rb.area) {
2890 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2891 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2892 }
2893 if (chip->posbuf.area) {
2894 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2895 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2896 }
a82d51ed
TI		 2897 if (chip->region_requested)
2898 pci_release_regions(chip->pci);
1da177e4 2899 pci_disable_device(chip->pci);
07e4ca50 2900 kfree(chip->azx_dev);
4918cdab
TI		 2901#ifdef CONFIG_SND_HDA_PATCH_LOADER
2902 if (chip->fw)
2903 release_firmware(chip->fw);
2904#endif
99a2008d
WX		 2905 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2906 hda_display_power(false);
2907 hda_i915_exit();
2908 }
1da177e4
LT		 2909 kfree(chip);
2910
2911 return 0;
2912}
2913
a98f90fd 2914static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2915{
2916 return azx_free(device->device_data);
2917}
2918
8393ec4a 2919#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2920/*
2921 * Check of disabled HDMI controller by vga-switcheroo
2922 */
e23e7a14 2923static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 2924{
2925 struct pci_dev *p;
2926
2927 /* check only discrete GPU */
2928 switch (pci->vendor) {
2929 case PCI_VENDOR_ID_ATI:
2930 case PCI_VENDOR_ID_AMD:
2931 case PCI_VENDOR_ID_NVIDIA:
2932 if (pci->devfn == 1) {
2933 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2934 pci->bus->number, 0);
2935 if (p) {
2936 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2937 return p;
2938 pci_dev_put(p);
2939 }
2940 }
2941 break;
2942 }
2943 return NULL;
2944}
2945
e23e7a14 2946static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 2947{
2948 bool vga_inactive = false;
2949 struct pci_dev *p = get_bound_vga(pci);
2950
2951 if (p) {
12b78a7f 2952 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2953 vga_inactive = true;
2954 pci_dev_put(p);
2955 }
2956 return vga_inactive;
2957}
8393ec4a 2958#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2959
3372a153
TI		 2960/*
2961 * white/black-listing for position_fix
2962 */
e23e7a14 2963static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 2964 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2965 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2966 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2967 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2968 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2969 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2970 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2971 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2972 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2973 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2974 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2975 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2976 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2977 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2978 {}
2979};
2980
e23e7a14 2981static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 2982{
2983 const struct snd_pci_quirk *q;
2984
c673ba1c 2985 switch (fix) {
1dac6695 2986 case POS_FIX_AUTO:
c673ba1c
TI		 2987 case POS_FIX_LPIB:
2988 case POS_FIX_POSBUF:
4cb36310 2989 case POS_FIX_VIACOMBO:
a6f2fd55 2990 case POS_FIX_COMBO:
c673ba1c
TI		 2991 return fix;
2992 }
2993
c673ba1c
TI		 2994 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2995 if (q) {
4e76a883
TI		 2996 dev_info(chip->card->dev,
2997 "position_fix set to %d for device %04x:%04x\n",
2998 q->value, q->subvendor, q->subdevice);
c673ba1c 2999 return q->value;
3372a153 3000 }
bdd9ef24
DH		 3001
3002 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3003 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 3004 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 3005 return POS_FIX_VIACOMBO;
9477c58e
TI		 3006 }
3007 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 3008 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 3009 return POS_FIX_LPIB;
bdd9ef24 3010 }
c673ba1c 3011 return POS_FIX_AUTO;
3372a153
TI		 3012}
3013
669ba27a
TI		 3014/*
3015 * black-lists for probe_mask
3016 */
e23e7a14 3017static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3018 /* Thinkpad often breaks the controller communication when accessing
3019 * to the non-working (or non-existing) modem codec slot.
3020 */
3021 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3022 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3023 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3024 /* broken BIOS */
3025 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3026 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3027 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3028 /* forced codec slots */
93574844 3029 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3030 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3031 /* WinFast VP200 H (Teradici) user reported broken communication */
3032 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3033 {}
3034};
3035
f1eaaeec
TI		 3036#define AZX_FORCE_CODEC_MASK 0x100
3037
e23e7a14 3038static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3039{
3040 const struct snd_pci_quirk *q;
3041
f1eaaeec
TI		 3042 chip->codec_probe_mask = probe_mask[dev];
3043 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3044 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3045 if (q) {
4e76a883
TI		 3046 dev_info(chip->card->dev,
3047 "probe_mask set to 0x%x for device %04x:%04x\n",
3048 q->value, q->subvendor, q->subdevice);
f1eaaeec 3049 chip->codec_probe_mask = q->value;
669ba27a
TI		 3050 }
3051 }
f1eaaeec
TI		 3052
3053 /* check forced option */
3054 if (chip->codec_probe_mask != -1 &&
3055 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3056 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 3057 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
3058 chip->codec_mask);
f1eaaeec 3059 }
669ba27a
TI		 3060}
3061
4d8e22e0 3062/*
71623855 3063 * white/black-list for enable_msi
4d8e22e0 3064 */
e23e7a14 3065static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 3066 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3067 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3068 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3069 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 3070 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3071 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3072 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 3073 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 3074 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3075 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3076 {}
3077};
3078
e23e7a14 3079static void check_msi(struct azx *chip)
4d8e22e0
TI		 3080{
3081 const struct snd_pci_quirk *q;
3082
71623855
TI		 3083 if (enable_msi >= 0) {
3084 chip->msi = !!enable_msi;
4d8e22e0 3085 return;
71623855
TI		 3086 }
3087 chip->msi = 1; /* enable MSI as default */
3088 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 3089 if (q) {
4e76a883
TI		 3090 dev_info(chip->card->dev,
3091 "msi for device %04x:%04x set to %d\n",
3092 q->subvendor, q->subdevice, q->value);
4d8e22e0 3093 chip->msi = q->value;
80c43ed7
TI		 3094 return;
3095 }
3096
3097 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 3098 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 3099 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 3100 chip->msi = 0;
4d8e22e0
TI		 3101 }
3102}
3103
a1585d76 3104/* check the snoop mode availability */
e23e7a14 3105static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3106{
3107 bool snoop = chip->snoop;
3108
3109 switch (chip->driver_type) {
3110 case AZX_DRIVER_VIA:
3111 /* force to non-snoop mode for a new VIA controller
3112 * when BIOS is set
3113 */
3114 if (snoop) {
3115 u8 val;
3116 pci_read_config_byte(chip->pci, 0x42, &val);
3117 if (!(val & 0x80) && chip->pci->revision == 0x30)
3118 snoop = false;
3119 }
3120 break;
3121 case AZX_DRIVER_ATIHDMI_NS:
3122 /* new ATI HDMI requires non-snoop */
3123 snoop = false;
3124 break;
c1279f87
TI		 3125 case AZX_DRIVER_CTHDA:
3126 snoop = false;
3127 break;
a1585d76
TI		 3128 }
3129
3130 if (snoop != chip->snoop) {
4e76a883
TI		 3131 dev_info(chip->card->dev, "Force to %s mode\n",
3132 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3133 chip->snoop = snoop;
3134 }
3135}
669ba27a 3136
99a2008d
WX		 3137static void azx_probe_work(struct work_struct *work)
3138{
3139 azx_probe_continue(container_of(work, struct azx, probe_work));
3140}
99a2008d 3141
1da177e4
LT		 3142/*
3143 * constructor
3144 */
e23e7a14
BP		 3145static int azx_create(struct snd_card *card, struct pci_dev *pci,
3146 int dev, unsigned int driver_caps,
40830813 3147 const struct hda_controller_ops *hda_ops,
e23e7a14 3148 struct azx **rchip)
1da177e4 3149{
a98f90fd 3150 static struct snd_device_ops ops = {
1da177e4
LT		 3151 .dev_free = azx_dev_free,
3152 };
a82d51ed
TI		 3153 struct azx *chip;
3154 int err;
1da177e4
LT		 3155
3156 *rchip = NULL;
bcd72003 3157
927fc866
PM		 3158 err = pci_enable_device(pci);
3159 if (err < 0)
1da177e4
LT		 3160 return err;
3161
e560d8d8 3162 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3163 if (!chip) {
4e76a883 3164 dev_err(card->dev, "Cannot allocate chip\n");
1da177e4
LT		 3165 pci_disable_device(pci);
3166 return -ENOMEM;
3167 }
3168
3169 spin_lock_init(&chip->reg_lock);
62932df8 3170 mutex_init(&chip->open_mutex);
1da177e4
LT		 3171 chip->card = card;
3172 chip->pci = pci;
40830813 3173 chip->ops = hda_ops;
1da177e4 3174 chip->irq = -1;
9477c58e
TI		 3175 chip->driver_caps = driver_caps;
3176 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3177 check_msi(chip);
555e219f 3178 chip->dev_index = dev;
9ad593f6 3179 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3180 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3181 INIT_LIST_HEAD(&chip->list);
a82d51ed 3182 init_vga_switcheroo(chip);
f4c482a4 3183 init_completion(&chip->probe_wait);
1da177e4 3184
beaffc39
SG		 3185 chip->position_fix[0] = chip->position_fix[1] =
3186 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3187 /* combo mode uses LPIB for playback */
3188 if (chip->position_fix[0] == POS_FIX_COMBO) {
3189 chip->position_fix[0] = POS_FIX_LPIB;
3190 chip->position_fix[1] = POS_FIX_AUTO;
3191 }
3192
5aba4f8e 3193 check_probe_mask(chip, dev);
3372a153 3194
27346166 3195 chip->single_cmd = single_cmd;
27fe48d9 3196 chip->snoop = hda_snoop;
a1585d76 3197 azx_check_snoop_available(chip);
c74db86b 3198
5c0d7bc1
TI		 3199 if (bdl_pos_adj[dev] < 0) {
3200 switch (chip->driver_type) {
0c6341ac 3201 case AZX_DRIVER_ICH:
32679f95 3202 case AZX_DRIVER_PCH:
0c6341ac 3203 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3204 break;
3205 default:
0c6341ac 3206 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3207 break;
3208 }
3209 }
3210
a82d51ed
TI		 3211 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3212 if (err < 0) {
4e76a883 3213 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 3214 azx_free(chip);
3215 return err;
3216 }
3217
99a2008d
WX		 3218 /* continue probing in work context as may trigger request module */
3219 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 3220
a82d51ed 3221 *rchip = chip;
99a2008d 3222
a82d51ed
TI		 3223 return 0;
3224}
3225
48c8b0eb 3226static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3227{
3228 int dev = chip->dev_index;
3229 struct pci_dev *pci = chip->pci;
3230 struct snd_card *card = chip->card;
3231 int i, err;
3232 unsigned short gcap;
3233
07e4ca50
TI		 3234#if BITS_PER_LONG != 64
3235 /* Fix up base address on ULI M5461 */
3236 if (chip->driver_type == AZX_DRIVER_ULI) {
3237 u16 tmp3;
3238 pci_read_config_word(pci, 0x40, &tmp3);
3239 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3240 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3241 }
3242#endif
3243
927fc866 3244 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3245 if (err < 0)
1da177e4 3246 return err;
a82d51ed 3247 chip->region_requested = 1;
1da177e4 3248
927fc866 3249 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3250 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3251 if (chip->remap_addr == NULL) {
4e76a883 3252 dev_err(card->dev, "ioremap error\n");
a82d51ed 3253 return -ENXIO;
1da177e4
LT		 3254 }
3255
68e7fffc
TI		 3256 if (chip->msi)
3257 if (pci_enable_msi(pci) < 0)
3258 chip->msi = 0;
7376d013 3259
a82d51ed
TI		 3260 if (azx_acquire_irq(chip, 0) < 0)
3261 return -EBUSY;
1da177e4
LT		 3262
3263 pci_set_master(pci);
3264 synchronize_irq(chip->irq);
3265
bcd72003 3266 gcap = azx_readw(chip, GCAP);
4e76a883 3267 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3268
dc4c2e6b 3269 /* disable SB600 64bit support for safety */
9477c58e 3270 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3271 struct pci_dev *p_smbus;
3272 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3273 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3274 NULL);
3275 if (p_smbus) {
3276 if (p_smbus->revision < 0x30)
3277 gcap &= ~ICH6_GCAP_64OK;
3278 pci_dev_put(p_smbus);
3279 }
3280 }
09240cf4 3281
9477c58e
TI		 3282 /* disable 64bit DMA address on some devices */
3283 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 3284 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 3285 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3286 }
396087ea 3287
2ae66c26 3288 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3289 if (align_buffer_size >= 0)
3290 chip->align_buffer_size = !!align_buffer_size;
3291 else {
3292 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3293 chip->align_buffer_size = 0;
3294 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3295 chip->align_buffer_size = 1;
3296 else
3297 chip->align_buffer_size = 1;
3298 }
2ae66c26 3299
cf7aaca8 3300 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3301 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3302 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3303 else {
e930438c
YH		 3304 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3305 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3306 }
cf7aaca8 3307
8b6ed8e7
TI		 3308 /* read number of streams from GCAP register instead of using
3309 * hardcoded value
3310 */
3311 chip->capture_streams = (gcap >> 8) & 0x0f;
3312 chip->playback_streams = (gcap >> 12) & 0x0f;
3313 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3314 /* gcap didn't give any info, switching to old method */
3315
3316 switch (chip->driver_type) {
3317 case AZX_DRIVER_ULI:
3318 chip->playback_streams = ULI_NUM_PLAYBACK;
3319 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3320 break;
3321 case AZX_DRIVER_ATIHDMI:
1815b34a 3322 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3323 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3324 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3325 break;
c4da29ca 3326 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3327 default:
3328 chip->playback_streams = ICH6_NUM_PLAYBACK;
3329 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3330 break;
3331 }
07e4ca50 3332 }
8b6ed8e7
TI		 3333 chip->capture_index_offset = 0;
3334 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3335 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3336 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3337 GFP_KERNEL);
927fc866 3338 if (!chip->azx_dev) {
4e76a883 3339 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 3340 return -ENOMEM;
07e4ca50
TI		 3341 }
3342
4ce107b9 3343 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3344 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3345 /* allocate memory for the BDL for each stream */
3346 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3347 snd_dma_pci_data(chip->pci),
3348 BDL_SIZE, &chip->azx_dev[i].bdl);
3349 if (err < 0) {
4e76a883 3350 dev_err(card->dev, "cannot allocate BDL\n");
a82d51ed 3351 return -ENOMEM;
4ce107b9 3352 }
27fe48d9 3353 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3354 }
0be3b5d3 3355 /* allocate memory for the position buffer */
d01ce99f
TI		 3356 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3357 snd_dma_pci_data(chip->pci),
3358 chip->num_streams * 8, &chip->posbuf);
3359 if (err < 0) {
4e76a883 3360 dev_err(card->dev, "cannot allocate posbuf\n");
a82d51ed 3361 return -ENOMEM;
1da177e4 3362 }
27fe48d9 3363 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3364 /* allocate CORB/RIRB */
81740861
TI		 3365 err = azx_alloc_cmd_io(chip);
3366 if (err < 0)
a82d51ed 3367 return err;
1da177e4
LT		 3368
3369 /* initialize streams */
3370 azx_init_stream(chip);
3371
3372 /* initialize chip */
cb53c626 3373 azx_init_pci(chip);
10e77dda 3374 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3375
3376 /* codec detection */
927fc866 3377 if (!chip->codec_mask) {
4e76a883 3378 dev_err(card->dev, "no codecs found!\n");
a82d51ed 3379 return -ENODEV;
1da177e4
LT		 3380 }
3381
07e4ca50 3382 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3383 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3384 sizeof(card->shortname));
3385 snprintf(card->longname, sizeof(card->longname),
3386 "%s at 0x%lx irq %i",
3387 card->shortname, chip->addr, chip->irq);
07e4ca50 3388
1da177e4 3389 return 0;
1da177e4
LT		 3390}
3391
cb53c626
TI		 3392static void power_down_all_codecs(struct azx *chip)
3393{
83012a7c 3394#ifdef CONFIG_PM
cb53c626
TI		 3395 /* The codecs were powered up in snd_hda_codec_new().
3396 * Now all initialization done, so turn them down if possible
3397 */
3398 struct hda_codec *codec;
3399 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3400 snd_hda_power_down(codec);
3401 }
3402#endif
3403}
3404
97c6a3d1 3405#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3406/* callback from request_firmware_nowait() */
3407static void azx_firmware_cb(const struct firmware *fw, void *context)
3408{
3409 struct snd_card *card = context;
3410 struct azx *chip = card->private_data;
3411 struct pci_dev *pci = chip->pci;
3412
3413 if (!fw) {
4e76a883 3414 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 3415 goto error;
3416 }
3417
3418 chip->fw = fw;
3419 if (!chip->disabled) {
3420 /* continue probing */
3421 if (azx_probe_continue(chip))
3422 goto error;
3423 }
3424 return; /* OK */
3425
3426 error:
3427 snd_card_free(card);
3428 pci_set_drvdata(pci, NULL);
3429}
97c6a3d1 3430#endif
5cb543db 3431
40830813
DR		 3432/*
3433 * HDA controller ops.
3434 */
3435
3436/* PCI register access. */
3437static void pci_azx_writel(u32 value, u32 *addr)
3438{
3439 writel(value, addr);
3440}
3441
3442static u32 pci_azx_readl(u32 *addr)
3443{
3444 return readl(addr);
3445}
3446
3447static void pci_azx_writew(u16 value, u16 *addr)
3448{
3449 writew(value, addr);
3450}
3451
3452static u16 pci_azx_readw(u16 *addr)
3453{
3454 return readw(addr);
3455}
3456
3457static void pci_azx_writeb(u8 value, u8 *addr)
3458{
3459 writeb(value, addr);
3460}
3461
3462static u8 pci_azx_readb(u8 *addr)
3463{
3464 return readb(addr);
3465}
3466
3467static const struct hda_controller_ops pci_hda_ops = {
3468 .writel = pci_azx_writel,
3469 .readl = pci_azx_readl,
3470 .writew = pci_azx_writew,
3471 .readw = pci_azx_readw,
3472 .writeb = pci_azx_writeb,
3473 .readb = pci_azx_readb,
3474};
3475
e23e7a14
BP		 3476static int azx_probe(struct pci_dev *pci,
3477 const struct pci_device_id *pci_id)
1da177e4 3478{
5aba4f8e 3479 static int dev;
a98f90fd
TI		 3480 struct snd_card *card;
3481 struct azx *chip;
aad730d0 3482 bool schedule_probe;
927fc866 3483 int err;
1da177e4 3484
5aba4f8e
TI		 3485 if (dev >= SNDRV_CARDS)
3486 return -ENODEV;
3487 if (!enable[dev]) {
3488 dev++;
3489 return -ENOENT;
3490 }
3491
60c5772b
TI		 3492 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3493 0, &card);
e58de7ba 3494 if (err < 0) {
4e76a883 3495 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 3496 return err;
1da177e4
LT		 3497 }
3498
40830813
DR		 3499 err = azx_create(card, pci, dev, pci_id->driver_data,
3500 &pci_hda_ops, &chip);
41dda0fd
WF		 3501 if (err < 0)
3502 goto out_free;
421a1252 3503 card->private_data = chip;
f4c482a4
TI		 3504
3505 pci_set_drvdata(pci, card);
3506
3507 err = register_vga_switcheroo(chip);
3508 if (err < 0) {
4e76a883 3509 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 3510 goto out_free;
3511 }
3512
3513 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 3514 dev_info(card->dev, "VGA controller is disabled\n");
3515 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 3516 chip->disabled = true;
3517 }
3518
aad730d0 3519 schedule_probe = !chip->disabled;
1da177e4 3520
4918cdab
TI		 3521#ifdef CONFIG_SND_HDA_PATCH_LOADER
3522 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 3523 dev_info(card->dev, "Applying patch firmware '%s'\n",
3524 patch[dev]);
5cb543db
TI		 3525 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3526 &pci->dev, GFP_KERNEL, card,
3527 azx_firmware_cb);
4918cdab
TI		 3528 if (err < 0)
3529 goto out_free;
aad730d0 3530 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3531 }
3532#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3533
aad730d0
TI		 3534#ifndef CONFIG_SND_HDA_I915
3535 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 3536 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 3537#endif
99a2008d 3538
aad730d0
TI		 3539 if (schedule_probe)
3540 schedule_work(&chip->probe_work);
a82d51ed 3541
a82d51ed 3542 dev++;
88d071fc
TI		 3543 if (chip->disabled)
3544 complete_all(&chip->probe_wait);
a82d51ed
TI		 3545 return 0;
3546
3547out_free:
3548 snd_card_free(card);
3549 return err;
3550}
3551
48c8b0eb 3552static int azx_probe_continue(struct azx *chip)
a82d51ed 3553{
c67e2228 3554 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3555 int dev = chip->dev_index;
3556 int err;
3557
99a2008d
WX		 3558 /* Request power well for Haswell HDA controller and codec */
3559 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 3560#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 3561 err = hda_i915_init();
3562 if (err < 0) {
4e76a883
TI		 3563 dev_err(chip->card->dev,
3564 "Error request power-well from i915\n");
99a2008d
WX		 3565 goto out_free;
3566 }
c841ad2a 3567#endif
99a2008d
WX		 3568 hda_display_power(true);
3569 }
3570
5c90680e
TI		 3571 err = azx_first_init(chip);
3572 if (err < 0)
3573 goto out_free;
3574
2dca0bba
JK		 3575#ifdef CONFIG_SND_HDA_INPUT_BEEP
3576 chip->beep_mode = beep_mode[dev];
3577#endif
3578
1da177e4 3579 /* create codec instances */
a1e21c90 3580 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3581 if (err < 0)
3582 goto out_free;
4ea6fbc8 3583#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3584 if (chip->fw) {
3585 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3586 chip->fw->data);
4ea6fbc8
TI		 3587 if (err < 0)
3588 goto out_free;
e39ae856 3589#ifndef CONFIG_PM
4918cdab
TI		 3590 release_firmware(chip->fw); /* no longer needed */
3591 chip->fw = NULL;
e39ae856 3592#endif
4ea6fbc8
TI		 3593 }
3594#endif
10e77dda 3595 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3596 err = azx_codec_configure(chip);
3597 if (err < 0)
3598 goto out_free;
3599 }
1da177e4
LT		 3600
3601 /* create PCM streams */
176d5335 3602 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3603 if (err < 0)
3604 goto out_free;
1da177e4
LT		 3605
3606 /* create mixer controls */
d01ce99f 3607 err = azx_mixer_create(chip);
41dda0fd
WF		 3608 if (err < 0)
3609 goto out_free;
1da177e4 3610
a82d51ed 3611 err = snd_card_register(chip->card);
41dda0fd
WF		 3612 if (err < 0)
3613 goto out_free;
1da177e4 3614
cb53c626
TI		 3615 chip->running = 1;
3616 power_down_all_codecs(chip);
0cbf0098 3617 azx_notifier_register(chip);
65fcd41d 3618 azx_add_card_list(chip);
246efa4a 3619 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 3620 pm_runtime_put_noidle(&pci->dev);
1da177e4 3621
41dda0fd 3622out_free:
88d071fc
TI		 3623 if (err < 0)
3624 chip->init_failed = 1;
3625 complete_all(&chip->probe_wait);
41dda0fd 3626 return err;
1da177e4
LT		 3627}
3628
e23e7a14 3629static void azx_remove(struct pci_dev *pci)
1da177e4 3630{
9121947d 3631 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3632
9121947d
TI		 3633 if (card)
3634 snd_card_free(card);
1da177e4
LT		 3635}
3636
3637/* PCI IDs */
cebe41d4 3638static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3639 /* CPT */
9477c58e 3640 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3641 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3642 /* PBG */
9477c58e 3643 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3644 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3645 /* Panther Point */
9477c58e 3646 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 3647 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3648 /* Lynx Point */
3649 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3650 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3651 /* Wellsburg */
3652 { PCI_DEVICE(0x8086, 0x8d20),
3653 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3654 { PCI_DEVICE(0x8086, 0x8d21),
3655 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3656 /* Lynx Point-LP */
3657 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3658 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3659 /* Lynx Point-LP */
3660 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3661 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 3662 /* Wildcat Point-LP */
3663 { PCI_DEVICE(0x8086, 0x9ca0),
3664 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3665 /* Haswell */
4a7c516b 3666 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 3667 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 3668 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 3669 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 3670 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 3671 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 3672 /* Broadwell */
3673 { PCI_DEVICE(0x8086, 0x160c),
3674 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 3675 /* 5 Series/3400 */
3676 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 3677 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 3678 /* Poulsbo */
9477c58e 3679 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 3680 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3681 /* Oaktrail */
09904b95 3682 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 3683 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 3684 /* BayTrail */
3685 { PCI_DEVICE(0x8086, 0x0f04),
3686 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 3687 /* ICH */
8b0bd226 3688 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3689 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3690 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3691 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3692 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3693 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3694 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3695 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3696 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3697 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3698 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3699 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3700 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3701 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3702 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3703 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3704 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3705 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3706 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3707 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3708 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3709 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3710 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3711 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3712 /* Generic Intel */
3713 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3714 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3715 .class_mask = 0xffffff,
2ae66c26 3716 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3717 /* ATI SB 450/600/700/800/900 */
3718 { PCI_DEVICE(0x1002, 0x437b),
3719 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3720 { PCI_DEVICE(0x1002, 0x4383),
3721 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3722 /* AMD Hudson */
3723 { PCI_DEVICE(0x1022, 0x780d),
3724 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3725 /* ATI HDMI */
9477c58e
TI		 3726 { PCI_DEVICE(0x1002, 0x793b),
3727 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3728 { PCI_DEVICE(0x1002, 0x7919),
3729 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3730 { PCI_DEVICE(0x1002, 0x960f),
3731 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3732 { PCI_DEVICE(0x1002, 0x970f),
3733 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3734 { PCI_DEVICE(0x1002, 0xaa00),
3735 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3736 { PCI_DEVICE(0x1002, 0xaa08),
3737 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3738 { PCI_DEVICE(0x1002, 0xaa10),
3739 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3740 { PCI_DEVICE(0x1002, 0xaa18),
3741 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3742 { PCI_DEVICE(0x1002, 0xaa20),
3743 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3744 { PCI_DEVICE(0x1002, 0xaa28),
3745 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3746 { PCI_DEVICE(0x1002, 0xaa30),
3747 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3748 { PCI_DEVICE(0x1002, 0xaa38),
3749 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3750 { PCI_DEVICE(0x1002, 0xaa40),
3751 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3752 { PCI_DEVICE(0x1002, 0xaa48),
3753 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 3754 { PCI_DEVICE(0x1002, 0xaa50),
3755 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3756 { PCI_DEVICE(0x1002, 0xaa58),
3757 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3758 { PCI_DEVICE(0x1002, 0xaa60),
3759 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3760 { PCI_DEVICE(0x1002, 0xaa68),
3761 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3762 { PCI_DEVICE(0x1002, 0xaa80),
3763 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3764 { PCI_DEVICE(0x1002, 0xaa88),
3765 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3766 { PCI_DEVICE(0x1002, 0xaa90),
3767 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3768 { PCI_DEVICE(0x1002, 0xaa98),
3769 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3770 { PCI_DEVICE(0x1002, 0x9902),
3771 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3772 { PCI_DEVICE(0x1002, 0xaaa0),
3773 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3774 { PCI_DEVICE(0x1002, 0xaaa8),
3775 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3776 { PCI_DEVICE(0x1002, 0xaab0),
3777 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3778 /* VIA VT8251/VT8237A */
9477c58e
TI		 3779 { PCI_DEVICE(0x1106, 0x3288),
3780 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3781 /* VIA GFX VT7122/VX900 */
3782 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3783 /* VIA GFX VT6122/VX11 */
3784 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3785 /* SIS966 */
3786 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3787 /* ULI M5461 */
3788 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3789 /* NVIDIA MCP */
0c2fd1bf
TI		 3790 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3791 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3792 .class_mask = 0xffffff,
9477c58e 3793 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3794 /* Teradici */
9477c58e
TI		 3795 { PCI_DEVICE(0x6549, 0x1200),
3796 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3797 { PCI_DEVICE(0x6549, 0x2200),
3798 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3799 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3800 /* CTHDA chips */
3801 { PCI_DEVICE(0x1102, 0x0010),
3802 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3803 { PCI_DEVICE(0x1102, 0x0012),
3804 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 3805#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 3806 /* the following entry conflicts with snd-ctxfi driver,
3807 * as ctxfi driver mutates from HD-audio to native mode with
3808 * a special command sequence.
3809 */
4e01f54b
TI		 3810 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3811 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3812 .class_mask = 0xffffff,
9477c58e 3813 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3814 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3815#else
3816 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3817 { PCI_DEVICE(0x1102, 0x0009),
3818 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3819 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3820#endif
e35d4b11
OS		 3821 /* Vortex86MX */
3822 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3823 /* VMware HDAudio */
3824 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3825 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3826 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3827 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3828 .class_mask = 0xffffff,
9477c58e 3829 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3830 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3831 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3832 .class_mask = 0xffffff,
9477c58e 3833 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3834 { 0, }
3835};
3836MODULE_DEVICE_TABLE(pci, azx_ids);
3837
3838/* pci_driver definition */
e9f66d9b 3839static struct pci_driver azx_driver = {
3733e424 3840 .name = KBUILD_MODNAME,
1da177e4
LT		 3841 .id_table = azx_ids,
3842 .probe = azx_probe,
e23e7a14 3843 .remove = azx_remove,
68cb2b55
TI		 3844 .driver = {
3845 .pm = AZX_PM_OPS,
3846 },
1da177e4
LT		 3847};
3848
e9f66d9b 3849module_pci_driver(azx_driver);
Linux kernel - Deliverables
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