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ALSA: hda - Fix D3 clock stop check for codecs with own set_power_state op
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
27fe48d9
TI		 50#ifdef CONFIG_X86
51/* for snoop control */
52#include <asm/pgtable.h>
53#include <asm/cacheflush.h>
54#endif
1da177e4
LT		 55#include <sound/core.h>
56#include <sound/initval.h>
9121947d 57#include <linux/vgaarb.h>
a82d51ed 58#include <linux/vga_switcheroo.h>
4918cdab 59#include <linux/firmware.h>
1da177e4
LT		 60#include "hda_codec.h"
61
62
5aba4f8e
TI		 63static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 65static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 66static char *model[SNDRV_CARDS];
67static int position_fix[SNDRV_CARDS];
5c0d7bc1 68static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 69static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 70static int probe_only[SNDRV_CARDS];
a67ff6a5 71static bool single_cmd;
71623855 72static int enable_msi = -1;
4ea6fbc8
TI		 73#ifdef CONFIG_SND_HDA_PATCH_LOADER
74static char *patch[SNDRV_CARDS];
75#endif
2dca0bba 76#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 77static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79#endif
1da177e4 80
5aba4f8e 81module_param_array(index, int, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 83module_param_array(id, charp, NULL, 0444);
1da177e4 84MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 85module_param_array(enable, bool, NULL, 0444);
86MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87module_param_array(model, charp, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 89module_param_array(position_fix, int, NULL, 0444);
4cb36310 90MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 91 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 92module_param_array(bdl_pos_adj, int, NULL, 0644);
93MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 94module_param_array(probe_mask, int, NULL, 0444);
606ad75f 95MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 96module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 97MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 98module_param(single_cmd, bool, 0444);
d01ce99f
TI		 99MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
ac9ef6cf 101module_param(enable_msi, bint, 0444);
134a11f0 102MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 103#ifdef CONFIG_SND_HDA_PATCH_LOADER
104module_param_array(patch, charp, NULL, 0444);
105MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106#endif
2dca0bba 107#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 108module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 109MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 110 "(0=off, 1=on) (default=1).");
2dca0bba 111#endif
606ad75f 112
dee1b66c 113#ifdef CONFIG_SND_HDA_POWER_SAVE
65fcd41d
TI		 114static int param_set_xint(const char *val, const struct kernel_param *kp);
115static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
118};
119#define param_check_xint param_check_int
120
fee2fba3 121static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 122module_param(power_save, xint, 0644);
fee2fba3
TI		 123MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
1da177e4 125
dee1b66c
TI		 126/* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
128 * wake up.
129 */
a67ff6a5 130static bool power_save_controller = 1;
dee1b66c
TI		 131module_param(power_save_controller, bool, 0644);
132MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
133#endif
134
7bfe059e
TI		 135static int align_buffer_size = -1;
136module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 137MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
139
27fe48d9
TI		 140#ifdef CONFIG_X86
141static bool hda_snoop = true;
142module_param_named(snoop, hda_snoop, bool, 0444);
143MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144#define azx_snoop(chip) (chip)->snoop
145#else
146#define hda_snoop true
147#define azx_snoop(chip) true
148#endif
149
150
1da177e4
LT		 151MODULE_LICENSE("GPL");
152MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153 "{Intel, ICH6M},"
2f1b3818 154 "{Intel, ICH7},"
f5d40b30 155 "{Intel, ESB2},"
d2981393 156 "{Intel, ICH8},"
f9cc8a8b 157 "{Intel, ICH9},"
c34f5a04 158 "{Intel, ICH10},"
b29c2360 159 "{Intel, PCH},"
d2f2fcd2 160 "{Intel, CPT},"
d2edeb7c 161 "{Intel, PPT},"
8bc039a1 162 "{Intel, LPT},"
144dad99 163 "{Intel, LPT_LP},"
e926f2c8 164 "{Intel, HPT},"
cea310e8 165 "{Intel, PBG},"
4979bca9 166 "{Intel, SCH},"
fc20a562 167 "{ATI, SB450},"
89be83f8 168 "{ATI, SB600},"
778b6e1b 169 "{ATI, RS600},"
5b15c95f 170 "{ATI, RS690},"
e6db1119
WL		 171 "{ATI, RS780},"
172 "{ATI, R600},"
2797f724
HRK		 173 "{ATI, RV630},"
174 "{ATI, RV610},"
27da1834
WL		 175 "{ATI, RV670},"
176 "{ATI, RV635},"
177 "{ATI, RV620},"
178 "{ATI, RV770},"
fc20a562 179 "{VIA, VT8251},"
47672310 180 "{VIA, VT8237A},"
07e4ca50
TI		 181 "{SiS, SIS966},"
182 "{ULI, M5461}}");
1da177e4
LT		 183MODULE_DESCRIPTION("Intel HDA driver");
184
4abc1cc2
TI		 185#ifdef CONFIG_SND_VERBOSE_PRINTK
186#define SFX /* nop */
187#else
1da177e4 188#define SFX "hda-intel: "
4abc1cc2 189#endif
cb53c626 190
a82d51ed
TI		 191#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192#ifdef CONFIG_SND_HDA_CODEC_HDMI
193#define SUPPORT_VGA_SWITCHEROO
194#endif
195#endif
196
197
1da177e4
LT		 198/*
199 * registers
200 */
201#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 202#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 207#define ICH6_REG_VMIN 0x02
208#define ICH6_REG_VMAJ 0x03
209#define ICH6_REG_OUTPAY 0x04
210#define ICH6_REG_INPAY 0x06
211#define ICH6_REG_GCTL 0x08
8a933ece 212#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 213#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 215#define ICH6_REG_WAKEEN 0x0c
216#define ICH6_REG_STATESTS 0x0e
217#define ICH6_REG_GSTS 0x10
b21fadb9 218#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 219#define ICH6_REG_INTCTL 0x20
220#define ICH6_REG_INTSTS 0x24
e5463720 221#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 222#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 224#define ICH6_REG_CORBLBASE 0x40
225#define ICH6_REG_CORBUBASE 0x44
226#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 227#define ICH6_REG_CORBRP 0x4a
228#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 229#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 230#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 232#define ICH6_REG_CORBSTS 0x4d
b21fadb9 233#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 234#define ICH6_REG_CORBSIZE 0x4e
235
236#define ICH6_REG_RIRBLBASE 0x50
237#define ICH6_REG_RIRBUBASE 0x54
238#define ICH6_REG_RIRBWP 0x58
b21fadb9 239#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 240#define ICH6_REG_RINTCNT 0x5a
241#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 242#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 245#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 246#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 248#define ICH6_REG_RIRBSIZE 0x5e
249
250#define ICH6_REG_IC 0x60
251#define ICH6_REG_IR 0x64
252#define ICH6_REG_IRS 0x68
253#define ICH6_IRS_VALID (1<<1)
254#define ICH6_IRS_BUSY (1<<0)
255
256#define ICH6_REG_DPLBASE 0x70
257#define ICH6_REG_DPUBASE 0x74
258#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
259
260/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263/* stream register offsets from stream base */
264#define ICH6_REG_SD_CTL 0x00
265#define ICH6_REG_SD_STS 0x03
266#define ICH6_REG_SD_LPIB 0x04
267#define ICH6_REG_SD_CBL 0x08
268#define ICH6_REG_SD_LVI 0x0c
269#define ICH6_REG_SD_FIFOW 0x0e
270#define ICH6_REG_SD_FIFOSIZE 0x10
271#define ICH6_REG_SD_FORMAT 0x12
272#define ICH6_REG_SD_BDLPL 0x18
273#define ICH6_REG_SD_BDLPU 0x1c
274
275/* PCI space */
276#define ICH6_PCIREG_TCSEL 0x44
277
278/*
279 * other constants
280 */
281
282/* max number of SDs */
07e4ca50 283/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 284#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 285#define ICH6_NUM_PLAYBACK 4
286
287/* ULI has 6 playback and 5 capture */
07e4ca50 288#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 289#define ULI_NUM_PLAYBACK 6
290
778b6e1b 291/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 292#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 293#define ATIHDMI_NUM_PLAYBACK 1
294
f269002e
KY		 295/* TERA has 4 playback and 3 capture */
296#define TERA_NUM_CAPTURE 3
297#define TERA_NUM_PLAYBACK 4
298
07e4ca50
TI		 299/* this number is statically defined for simplicity */
300#define MAX_AZX_DEV 16
301
1da177e4 302/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 303#define BDL_SIZE 4096
304#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305#define AZX_MAX_FRAG 32
1da177e4
LT		 306/* max buffer size - no h/w limit, you can increase as you like */
307#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 308
309/* RIRB int mask: overrun[2], response[0] */
310#define RIRB_INT_RESPONSE 0x01
311#define RIRB_INT_OVERRUN 0x04
312#define RIRB_INT_MASK 0x05
313
2f5983f2 314/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 315#define AZX_MAX_CODECS 8
316#define AZX_DEFAULT_CODECS 4
deadff16 317#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 318
319/* SD_CTL bits */
320#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 322#define SD_CTL_STRIPE (3 << 16) /* stripe control */
323#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 325#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326#define SD_CTL_STREAM_TAG_SHIFT 20
327
328/* SD_CTL and SD_STS */
329#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 332#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333 SD_INT_COMPLETE)
1da177e4
LT		 334
335/* SD_STS */
336#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
337
338/* INTCTL and INTSTS */
d01ce99f
TI		 339#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 342
1da177e4
LT		 343/* below are so far hardcoded - should read registers in future */
344#define ICH6_MAX_CORB_ENTRIES 256
345#define ICH6_MAX_RIRB_ENTRIES 256
346
c74db86b
TI		 347/* position fix mode */
348enum {
0be3b5d3 349 POS_FIX_AUTO,
d2e1c973 350 POS_FIX_LPIB,
0be3b5d3 351 POS_FIX_POSBUF,
4cb36310 352 POS_FIX_VIACOMBO,
a6f2fd55 353 POS_FIX_COMBO,
c74db86b 354};
1da177e4 355
f5d40b30 356/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 357#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
359
da3fca21
V		 360/* Defines for Nvidia HDA support */
361#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 363#define NVIDIA_HDA_ISTRM_COH 0x4d
364#define NVIDIA_HDA_OSTRM_COH 0x4c
365#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 366
90a5ad52
TI		 367/* Defines for Intel SCH HDA snoop control */
368#define INTEL_SCH_HDA_DEVC 0x78
369#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
370
0e153474
JC		 371/* Define IN stream 0 FIFO size offset in VIA controller */
372#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373/* Define VIA HD Audio Device ID*/
374#define VIA_HDAC_DEVICE_ID 0x3288
375
c4da29ca
YL		 376/* HD Audio class code */
377#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 378
1da177e4
LT		 379/*
380 */
381
a98f90fd 382struct azx_dev {
4ce107b9 383 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 384 u32 *posbuf; /* position buffer pointer */
1da177e4 385
d01ce99f 386 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 387 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
1da177e4 392
d01ce99f 393 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 394
d01ce99f 395 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 396
397 /* pcm support */
d01ce99f
TI		 398 struct snd_pcm_substream *substream; /* assigned substream,
399 * set in PCM open
400 */
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
403 */
1da177e4
LT		 404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
d5cf9911 406 int assigned_key; /* last device# key assigned to */
1da177e4 407
927fc866
PM		 408 unsigned int opened :1;
409 unsigned int running :1;
675f25d4 410 unsigned int irq_pending :1;
0e153474
JC		 411 /*
412 * For VIA:
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
415 */
416 unsigned int insufficient :1;
27fe48d9 417 unsigned int wc_marked:1;
1da177e4
LT		 418};
419
420/* CORB/RIRB */
a98f90fd 421struct azx_rb {
1da177e4
LT		 422 u32 *buf; /* CORB/RIRB buffer
423 * Each CORB entry is 4byte, RIRB is 8byte
424 */
425 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
426 /* for RIRB */
427 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 428 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
429 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 430};
431
01b65bfb
TI		 432struct azx_pcm {
433 struct azx *chip;
434 struct snd_pcm *pcm;
435 struct hda_codec *codec;
436 struct hda_pcm_stream *hinfo[2];
437 struct list_head list;
438};
439
a98f90fd
TI		 440struct azx {
441 struct snd_card *card;
1da177e4 442 struct pci_dev *pci;
555e219f 443 int dev_index;
1da177e4 444
07e4ca50
TI		 445 /* chip type specific */
446 int driver_type;
9477c58e 447 unsigned int driver_caps;
07e4ca50
TI		 448 int playback_streams;
449 int playback_index_offset;
450 int capture_streams;
451 int capture_index_offset;
452 int num_streams;
453
1da177e4
LT		 454 /* pci resources */
455 unsigned long addr;
456 void __iomem *remap_addr;
457 int irq;
458
459 /* locks */
460 spinlock_t reg_lock;
62932df8 461 struct mutex open_mutex;
1da177e4 462
07e4ca50 463 /* streams (x num_streams) */
a98f90fd 464 struct azx_dev *azx_dev;
1da177e4
LT		 465
466 /* PCM */
01b65bfb 467 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 468
469 /* HD codec */
470 unsigned short codec_mask;
f1eaaeec 471 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 472 struct hda_bus *bus;
2dca0bba 473 unsigned int beep_mode;
1da177e4
LT		 474
475 /* CORB/RIRB */
a98f90fd
TI		 476 struct azx_rb corb;
477 struct azx_rb rirb;
1da177e4 478
4ce107b9 479 /* CORB/RIRB and position buffers */
1da177e4
LT		 480 struct snd_dma_buffer rb;
481 struct snd_dma_buffer posbuf;
c74db86b 482
4918cdab
TI		 483#ifdef CONFIG_SND_HDA_PATCH_LOADER
484 const struct firmware *fw;
485#endif
486
c74db86b 487 /* flags */
beaffc39 488 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 489 int poll_count;
cb53c626 490 unsigned int running :1;
927fc866
PM		 491 unsigned int initialized :1;
492 unsigned int single_cmd :1;
493 unsigned int polling_mode :1;
68e7fffc 494 unsigned int msi :1;
a6a950a8 495 unsigned int irq_pending_warned :1;
6ce4a3bc 496 unsigned int probing :1; /* codec probing phase */
27fe48d9 497 unsigned int snoop:1;
52409aa6 498 unsigned int align_buffer_size:1;
a82d51ed
TI		 499 unsigned int region_requested:1;
500
501 /* VGA-switcheroo setup */
502 unsigned int use_vga_switcheroo:1;
503 unsigned int init_failed:1; /* delayed init failed */
504 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 505
506 /* for debugging */
feb27340 507 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 508
509 /* for pending irqs */
510 struct work_struct irq_pending_work;
0cbf0098
TI		 511
512 /* reboot notifier (for mysterious hangup problem at power-down) */
513 struct notifier_block reboot_notifier;
65fcd41d
TI		 514
515 /* card list (for power_save trigger) */
516 struct list_head list;
1da177e4
LT		 517};
518
07e4ca50
TI		 519/* driver types */
520enum {
521 AZX_DRIVER_ICH,
32679f95 522 AZX_DRIVER_PCH,
4979bca9 523 AZX_DRIVER_SCH,
07e4ca50 524 AZX_DRIVER_ATI,
778b6e1b 525 AZX_DRIVER_ATIHDMI,
1815b34a 526 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 527 AZX_DRIVER_VIA,
528 AZX_DRIVER_SIS,
529 AZX_DRIVER_ULI,
da3fca21 530 AZX_DRIVER_NVIDIA,
f269002e 531 AZX_DRIVER_TERA,
14d34f16 532 AZX_DRIVER_CTX,
5ae763b1 533 AZX_DRIVER_CTHDA,
c4da29ca 534 AZX_DRIVER_GENERIC,
2f5983f2 535 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 536};
537
9477c58e
TI		 538/* driver quirks (capabilities) */
539/* bits 0-7 are used for indicating driver type */
540#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
541#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
542#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
543#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
544#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
545#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
546#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
547#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
548#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
549#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
550#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
551#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 552#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 553#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 554#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 555#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
c20c5a84 556#define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
9477c58e
TI		 557
558/* quirks for ATI SB / AMD Hudson */
559#define AZX_DCAPS_PRESET_ATI_SB \
560 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
561 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
562
563/* quirks for ATI/AMD HDMI */
564#define AZX_DCAPS_PRESET_ATI_HDMI \
565 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
566
567/* quirks for Nvidia */
568#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 569 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
570 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 571
5ae763b1
TI		 572#define AZX_DCAPS_PRESET_CTHDA \
573 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
574
a82d51ed
TI		 575/*
576 * VGA-switcher support
577 */
578#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 579#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
580#else
581#define use_vga_switcheroo(chip) 0
582#endif
583
584#if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
a82d51ed
TI		 585#define DELAYED_INIT_MARK
586#define DELAYED_INITDATA_MARK
a82d51ed
TI		 587#else
588#define DELAYED_INIT_MARK __devinit
589#define DELAYED_INITDATA_MARK __devinitdata
a82d51ed
TI		 590#endif
591
592static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 593 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 594 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 595 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 596 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 597 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 598 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 599 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
600 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 601 [AZX_DRIVER_ULI] = "HDA ULI M5461",
602 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 603 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 604 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 605 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 606 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 607};
608
1da177e4
LT		 609/*
610 * macros for easy use
611 */
612#define azx_writel(chip,reg,value) \
613 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
614#define azx_readl(chip,reg) \
615 readl((chip)->remap_addr + ICH6_REG_##reg)
616#define azx_writew(chip,reg,value) \
617 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
618#define azx_readw(chip,reg) \
619 readw((chip)->remap_addr + ICH6_REG_##reg)
620#define azx_writeb(chip,reg,value) \
621 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
622#define azx_readb(chip,reg) \
623 readb((chip)->remap_addr + ICH6_REG_##reg)
624
625#define azx_sd_writel(dev,reg,value) \
626 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
627#define azx_sd_readl(dev,reg) \
628 readl((dev)->sd_addr + ICH6_REG_##reg)
629#define azx_sd_writew(dev,reg,value) \
630 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
631#define azx_sd_readw(dev,reg) \
632 readw((dev)->sd_addr + ICH6_REG_##reg)
633#define azx_sd_writeb(dev,reg,value) \
634 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
635#define azx_sd_readb(dev,reg) \
636 readb((dev)->sd_addr + ICH6_REG_##reg)
637
638/* for pcm support */
a98f90fd 639#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 640
27fe48d9
TI		 641#ifdef CONFIG_X86
642static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
643{
644 if (azx_snoop(chip))
645 return;
646 if (addr && size) {
647 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
648 if (on)
649 set_memory_wc((unsigned long)addr, pages);
650 else
651 set_memory_wb((unsigned long)addr, pages);
652 }
653}
654
655static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
656 bool on)
657{
658 __mark_pages_wc(chip, buf->area, buf->bytes, on);
659}
660static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
661 struct snd_pcm_runtime *runtime, bool on)
662{
663 if (azx_dev->wc_marked != on) {
664 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
665 azx_dev->wc_marked = on;
666 }
667}
668#else
669/* NOP for other archs */
670static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
671 bool on)
672{
673}
674static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
676{
677}
678#endif
679
68e7fffc 680static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 681static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 682/*
683 * Interface for HD codec
684 */
685
1da177e4
LT		 686/*
687 * CORB / RIRB interface
688 */
a98f90fd 689static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 690{
691 int err;
692
693 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 694 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
695 snd_dma_pci_data(chip->pci),
1da177e4
LT		 696 PAGE_SIZE, &chip->rb);
697 if (err < 0) {
698 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
699 return err;
700 }
27fe48d9 701 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 702 return 0;
703}
704
a98f90fd 705static void azx_init_cmd_io(struct azx *chip)
1da177e4 706{
cdb1fbf2 707 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 708 /* CORB set up */
709 chip->corb.addr = chip->rb.addr;
710 chip->corb.buf = (u32 *)chip->rb.area;
711 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 712 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 713
07e4ca50
TI		 714 /* set the corb size to 256 entries (ULI requires explicitly) */
715 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 716 /* set the corb write pointer to 0 */
717 azx_writew(chip, CORBWP, 0);
718 /* reset the corb hw read pointer */
b21fadb9 719 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 720 /* enable corb dma */
b21fadb9 721 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 722
723 /* RIRB set up */
724 chip->rirb.addr = chip->rb.addr + 2048;
725 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 726 chip->rirb.wp = chip->rirb.rp = 0;
727 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 728 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 729 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 730
07e4ca50
TI		 731 /* set the rirb size to 256 entries (ULI requires explicitly) */
732 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 733 /* reset the rirb hw write pointer */
b21fadb9 734 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 735 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 736 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 737 azx_writew(chip, RINTCNT, 0xc0);
738 else
739 azx_writew(chip, RINTCNT, 1);
1da177e4 740 /* enable rirb dma and response irq */
1da177e4 741 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 742 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 743}
744
a98f90fd 745static void azx_free_cmd_io(struct azx *chip)
1da177e4 746{
cdb1fbf2 747 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 748 /* disable ringbuffer DMAs */
749 azx_writeb(chip, RIRBCTL, 0);
750 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 751 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 752}
753
deadff16
WF		 754static unsigned int azx_command_addr(u32 cmd)
755{
756 unsigned int addr = cmd >> 28;
757
758 if (addr >= AZX_MAX_CODECS) {
759 snd_BUG();
760 addr = 0;
761 }
762
763 return addr;
764}
765
766static unsigned int azx_response_addr(u32 res)
767{
768 unsigned int addr = res & 0xf;
769
770 if (addr >= AZX_MAX_CODECS) {
771 snd_BUG();
772 addr = 0;
773 }
774
775 return addr;
1da177e4
LT		 776}
777
778/* send a command */
33fa35ed 779static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 780{
33fa35ed 781 struct azx *chip = bus->private_data;
deadff16 782 unsigned int addr = azx_command_addr(val);
1da177e4 783 unsigned int wp;
1da177e4 784
c32649fe
WF		 785 spin_lock_irq(&chip->reg_lock);
786
1da177e4
LT		 787 /* add command to corb */
788 wp = azx_readb(chip, CORBWP);
789 wp++;
790 wp %= ICH6_MAX_CORB_ENTRIES;
791
deadff16 792 chip->rirb.cmds[addr]++;
1da177e4
LT		 793 chip->corb.buf[wp] = cpu_to_le32(val);
794 azx_writel(chip, CORBWP, wp);
c32649fe 795
1da177e4
LT		 796 spin_unlock_irq(&chip->reg_lock);
797
798 return 0;
799}
800
801#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
802
803/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 804static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 805{
806 unsigned int rp, wp;
deadff16 807 unsigned int addr;
1da177e4
LT		 808 u32 res, res_ex;
809
810 wp = azx_readb(chip, RIRBWP);
811 if (wp == chip->rirb.wp)
812 return;
813 chip->rirb.wp = wp;
deadff16 814
1da177e4
LT		 815 while (chip->rirb.rp != wp) {
816 chip->rirb.rp++;
817 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
818
819 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
820 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
821 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 822 addr = azx_response_addr(res_ex);
1da177e4
LT		 823 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
824 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 825 else if (chip->rirb.cmds[addr]) {
826 chip->rirb.res[addr] = res;
2add9b92 827 smp_wmb();
deadff16 828 chip->rirb.cmds[addr]--;
e310bb06
WF		 829 } else
830 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
831 "last cmd=%#08x\n",
832 res, res_ex,
833 chip->last_cmd[addr]);
1da177e4
LT		 834 }
835}
836
837/* receive a response */
deadff16
WF		 838static unsigned int azx_rirb_get_response(struct hda_bus *bus,
839 unsigned int addr)
1da177e4 840{
33fa35ed 841 struct azx *chip = bus->private_data;
5c79b1f8 842 unsigned long timeout;
32cf4023 843 unsigned long loopcounter;
1eb6dc7d 844 int do_poll = 0;
1da177e4 845
5c79b1f8
TI		 846 again:
847 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 848
849 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 850 if (chip->polling_mode || do_poll) {
e96224ae
TI		 851 spin_lock_irq(&chip->reg_lock);
852 azx_update_rirb(chip);
853 spin_unlock_irq(&chip->reg_lock);
854 }
deadff16 855 if (!chip->rirb.cmds[addr]) {
2add9b92 856 smp_rmb();
b613291f 857 bus->rirb_error = 0;
1eb6dc7d
ML		 858
859 if (!do_poll)
860 chip->poll_count = 0;
deadff16 861 return chip->rirb.res[addr]; /* the last value */
2add9b92 862 }
28a0d9df
TI		 863 if (time_after(jiffies, timeout))
864 break;
32cf4023 865 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 866 msleep(2); /* temporary workaround */
867 else {
868 udelay(10);
869 cond_resched();
870 }
28a0d9df 871 }
5c79b1f8 872
1eb6dc7d
ML		 873 if (!chip->polling_mode && chip->poll_count < 2) {
874 snd_printdd(SFX "azx_get_response timeout, "
875 "polling the codec once: last cmd=0x%08x\n",
876 chip->last_cmd[addr]);
877 do_poll = 1;
878 chip->poll_count++;
879 goto again;
880 }
881
882
23c4a881
TI		 883 if (!chip->polling_mode) {
884 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
885 "switching to polling mode: last cmd=0x%08x\n",
886 chip->last_cmd[addr]);
887 chip->polling_mode = 1;
888 goto again;
889 }
890
68e7fffc 891 if (chip->msi) {
4abc1cc2 892 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 893 "disabling MSI: last cmd=0x%08x\n",
894 chip->last_cmd[addr]);
68e7fffc
TI		 895 free_irq(chip->irq, chip);
896 chip->irq = -1;
897 pci_disable_msi(chip->pci);
898 chip->msi = 0;
b613291f
TI		 899 if (azx_acquire_irq(chip, 1) < 0) {
900 bus->rirb_error = 1;
68e7fffc 901 return -1;
b613291f 902 }
68e7fffc
TI		 903 goto again;
904 }
905
6ce4a3bc
TI		 906 if (chip->probing) {
907 /* If this critical timeout happens during the codec probing
908 * phase, this is likely an access to a non-existing codec
909 * slot. Better to return an error and reset the system.
910 */
911 return -1;
912 }
913
8dd78330
TI		 914 /* a fatal communication error; need either to reset or to fallback
915 * to the single_cmd mode
916 */
b613291f 917 bus->rirb_error = 1;
b20f3b83 918 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 919 bus->response_reset = 1;
920 return -1; /* give a chance to retry */
921 }
922
923 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
924 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 925 chip->last_cmd[addr]);
8dd78330
TI		 926 chip->single_cmd = 1;
927 bus->response_reset = 0;
1a696978 928 /* release CORB/RIRB */
4fcd3920 929 azx_free_cmd_io(chip);
1a696978
TI		 930 /* disable unsolicited responses */
931 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 932 return -1;
1da177e4
LT		 933}
934
1da177e4
LT		 935/*
936 * Use the single immediate command instead of CORB/RIRB for simplicity
937 *
938 * Note: according to Intel, this is not preferred use. The command was
939 * intended for the BIOS only, and may get confused with unsolicited
940 * responses. So, we shouldn't use it for normal operation from the
941 * driver.
942 * I left the codes, however, for debugging/testing purposes.
943 */
944
b05a7d4f 945/* receive a response */
deadff16 946static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 947{
948 int timeout = 50;
949
950 while (timeout--) {
951 /* check IRV busy bit */
952 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
953 /* reuse rirb.res as the response return value */
deadff16 954 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 955 return 0;
956 }
957 udelay(1);
958 }
959 if (printk_ratelimit())
960 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
961 azx_readw(chip, IRS));
deadff16 962 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 963 return -EIO;
964}
965
1da177e4 966/* send a command */
33fa35ed 967static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 968{
33fa35ed 969 struct azx *chip = bus->private_data;
deadff16 970 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 971 int timeout = 50;
972
8dd78330 973 bus->rirb_error = 0;
1da177e4
LT		 974 while (timeout--) {
975 /* check ICB busy bit */
d01ce99f 976 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 977 /* Clear IRV valid bit */
d01ce99f
TI		 978 azx_writew(chip, IRS, azx_readw(chip, IRS) |
979 ICH6_IRS_VALID);
1da177e4 980 azx_writel(chip, IC, val);
d01ce99f
TI		 981 azx_writew(chip, IRS, azx_readw(chip, IRS) |
982 ICH6_IRS_BUSY);
deadff16 983 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 984 }
985 udelay(1);
986 }
1cfd52bc
MB		 987 if (printk_ratelimit())
988 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
989 azx_readw(chip, IRS), val);
1da177e4
LT		 990 return -EIO;
991}
992
993/* receive a response */
deadff16
WF		 994static unsigned int azx_single_get_response(struct hda_bus *bus,
995 unsigned int addr)
1da177e4 996{
33fa35ed 997 struct azx *chip = bus->private_data;
deadff16 998 return chip->rirb.res[addr];
1da177e4
LT		 999}
1000
111d3af5
TI		 1001/*
1002 * The below are the main callbacks from hda_codec.
1003 *
1004 * They are just the skeleton to call sub-callbacks according to the
1005 * current setting of chip->single_cmd.
1006 */
1007
1008/* send a command */
33fa35ed 1009static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1010{
33fa35ed 1011 struct azx *chip = bus->private_data;
43bbb6cc 1012
a82d51ed
TI		 1013 if (chip->disabled)
1014 return 0;
feb27340 1015 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1016 if (chip->single_cmd)
33fa35ed 1017 return azx_single_send_cmd(bus, val);
111d3af5 1018 else
33fa35ed 1019 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1020}
1021
1022/* get a response */
deadff16
WF		 1023static unsigned int azx_get_response(struct hda_bus *bus,
1024 unsigned int addr)
111d3af5 1025{
33fa35ed 1026 struct azx *chip = bus->private_data;
a82d51ed
TI		 1027 if (chip->disabled)
1028 return 0;
111d3af5 1029 if (chip->single_cmd)
deadff16 1030 return azx_single_get_response(bus, addr);
111d3af5 1031 else
deadff16 1032 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1033}
1034
cb53c626 1035#ifdef CONFIG_SND_HDA_POWER_SAVE
68467f51 1036static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1037#endif
111d3af5 1038
1da177e4 1039/* reset codec link */
cd508fe5 1040static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1041{
1042 int count;
1043
cd508fe5
JK		 1044 if (!full_reset)
1045 goto __skip;
1046
e8a7f136
DT		 1047 /* clear STATESTS */
1048 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1049
1da177e4
LT		 1050 /* reset controller */
1051 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1052
1053 count = 50;
1054 while (azx_readb(chip, GCTL) && --count)
1055 msleep(1);
1056
1057 /* delay for >= 100us for codec PLL to settle per spec
1058 * Rev 0.9 section 5.5.1
1059 */
1060 msleep(1);
1061
1062 /* Bring controller out of reset */
1063 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1064
1065 count = 50;
927fc866 1066 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1067 msleep(1);
1068
927fc866 1069 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1070 msleep(1);
1071
cd508fe5 1072 __skip:
1da177e4 1073 /* check to see if controller is ready */
927fc866 1074 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1075 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1076 return -EBUSY;
1077 }
1078
41e2fce4 1079 /* Accept unsolicited responses */
1a696978
TI		 1080 if (!chip->single_cmd)
1081 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1082 ICH6_GCTL_UNSOL);
41e2fce4 1083
1da177e4 1084 /* detect codecs */
927fc866 1085 if (!chip->codec_mask) {
1da177e4 1086 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1087 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1088 }
1089
1090 return 0;
1091}
1092
1093
1094/*
1095 * Lowlevel interface
1096 */
1097
1098/* enable interrupts */
a98f90fd 1099static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1100{
1101 /* enable controller CIE and GIE */
1102 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1103 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1104}
1105
1106/* disable interrupts */
a98f90fd 1107static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1108{
1109 int i;
1110
1111 /* disable interrupts in stream descriptor */
07e4ca50 1112 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1113 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1114 azx_sd_writeb(azx_dev, SD_CTL,
1115 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1116 }
1117
1118 /* disable SIE for all streams */
1119 azx_writeb(chip, INTCTL, 0);
1120
1121 /* disable controller CIE and GIE */
1122 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1123 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1124}
1125
1126/* clear interrupts */
a98f90fd 1127static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1128{
1129 int i;
1130
1131 /* clear stream status */
07e4ca50 1132 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1133 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1134 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1135 }
1136
1137 /* clear STATESTS */
1138 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1139
1140 /* clear rirb status */
1141 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1142
1143 /* clear int status */
1144 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1145}
1146
1147/* start a stream */
a98f90fd 1148static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1149{
0e153474
JC		 1150 /*
1151 * Before stream start, initialize parameter
1152 */
1153 azx_dev->insufficient = 1;
1154
1da177e4 1155 /* enable SIE */
ccc5df05
WN		 1156 azx_writel(chip, INTCTL,
1157 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1158 /* set DMA start and interrupt mask */
1159 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1160 SD_CTL_DMA_START | SD_INT_MASK);
1161}
1162
1dddab40
TI		 1163/* stop DMA */
1164static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1165{
1da177e4
LT		 1166 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1167 ~(SD_CTL_DMA_START | SD_INT_MASK));
1168 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1169}
1170
1171/* stop a stream */
1172static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1173{
1174 azx_stream_clear(chip, azx_dev);
1da177e4 1175 /* disable SIE */
ccc5df05
WN		 1176 azx_writel(chip, INTCTL,
1177 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1178}
1179
1180
1181/*
cb53c626 1182 * reset and start the controller registers
1da177e4 1183 */
cd508fe5 1184static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1185{
cb53c626
TI		 1186 if (chip->initialized)
1187 return;
1da177e4
LT		 1188
1189 /* reset controller */
cd508fe5 1190 azx_reset(chip, full_reset);
1da177e4
LT		 1191
1192 /* initialize interrupts */
1193 azx_int_clear(chip);
1194 azx_int_enable(chip);
1195
1196 /* initialize the codec command I/O */
1a696978
TI		 1197 if (!chip->single_cmd)
1198 azx_init_cmd_io(chip);
1da177e4 1199
0be3b5d3
TI		 1200 /* program the position buffer */
1201 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1202 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1203
cb53c626
TI		 1204 chip->initialized = 1;
1205}
1206
1207/*
1208 * initialize the PCI registers
1209 */
1210/* update bits in a PCI register byte */
1211static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1212 unsigned char mask, unsigned char val)
1213{
1214 unsigned char data;
1215
1216 pci_read_config_byte(pci, reg, &data);
1217 data &= ~mask;
1218 data |= (val & mask);
1219 pci_write_config_byte(pci, reg, data);
1220}
1221
1222static void azx_init_pci(struct azx *chip)
1223{
1224 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1225 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1226 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1227 * codecs.
1228 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1229 */
46f2cc80 1230 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1231 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1232 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1233 }
cb53c626 1234
9477c58e
TI		 1235 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1236 * we need to enable snoop.
1237 */
1238 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1239 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1240 update_pci_byte(chip->pci,
27fe48d9
TI		 1241 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1242 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1243 }
1244
1245 /* For NVIDIA HDA, enable snoop */
1246 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1247 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1248 update_pci_byte(chip->pci,
1249 NVIDIA_HDA_TRANSREG_ADDR,
1250 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1251 update_pci_byte(chip->pci,
1252 NVIDIA_HDA_ISTRM_COH,
1253 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1254 update_pci_byte(chip->pci,
1255 NVIDIA_HDA_OSTRM_COH,
1256 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1257 }
1258
1259 /* Enable SCH/PCH snoop if needed */
1260 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1261 unsigned short snoop;
90a5ad52 1262 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1263 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1264 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1265 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1266 if (!azx_snoop(chip))
1267 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1268 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1269 pci_read_config_word(chip->pci,
1270 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1271 }
27fe48d9
TI		 1272 snd_printdd(SFX "SCH snoop: %s\n",
1273 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1274 ? "Disabled" : "Enabled");
da3fca21 1275 }
1da177e4
LT		 1276}
1277
1278
9ad593f6
TI		 1279static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1280
1da177e4
LT		 1281/*
1282 * interrupt handler
1283 */
7d12e780 1284static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1285{
a98f90fd
TI		 1286 struct azx *chip = dev_id;
1287 struct azx_dev *azx_dev;
1da177e4 1288 u32 status;
9ef04066 1289 u8 sd_status;
fa00e046 1290 int i, ok;
1da177e4 1291
b8dfc462
ML		 1292#ifdef CONFIG_PM_RUNTIME
1293 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1294 return IRQ_NONE;
1295#endif
1296
1da177e4
LT		 1297 spin_lock(&chip->reg_lock);
1298
60911062
DC		 1299 if (chip->disabled) {
1300 spin_unlock(&chip->reg_lock);
a82d51ed 1301 return IRQ_NONE;
60911062 1302 }
a82d51ed 1303
1da177e4
LT		 1304 status = azx_readl(chip, INTSTS);
1305 if (status == 0) {
1306 spin_unlock(&chip->reg_lock);
1307 return IRQ_NONE;
1308 }
1309
07e4ca50 1310 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1311 azx_dev = &chip->azx_dev[i];
1312 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1313 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1314 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1315 if (!azx_dev->substream || !azx_dev->running ||
1316 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1317 continue;
1318 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1319 ok = azx_position_ok(chip, azx_dev);
1320 if (ok == 1) {
9ad593f6 1321 azx_dev->irq_pending = 0;
1da177e4
LT		 1322 spin_unlock(&chip->reg_lock);
1323 snd_pcm_period_elapsed(azx_dev->substream);
1324 spin_lock(&chip->reg_lock);
fa00e046 1325 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1326 /* bogus IRQ, process it later */
1327 azx_dev->irq_pending = 1;
6acaed38
TI		 1328 queue_work(chip->bus->workq,
1329 &chip->irq_pending_work);
1da177e4
LT		 1330 }
1331 }
1332 }
1333
1334 /* clear rirb int */
1335 status = azx_readb(chip, RIRBSTS);
1336 if (status & RIRB_INT_MASK) {
14d34f16 1337 if (status & RIRB_INT_RESPONSE) {
9477c58e 1338 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1339 udelay(80);
1da177e4 1340 azx_update_rirb(chip);
14d34f16 1341 }
1da177e4
LT		 1342 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1343 }
1344
1345#if 0
1346 /* clear state status int */
1347 if (azx_readb(chip, STATESTS) & 0x04)
1348 azx_writeb(chip, STATESTS, 0x04);
1349#endif
1350 spin_unlock(&chip->reg_lock);
1351
1352 return IRQ_HANDLED;
1353}
1354
1355
675f25d4
TI		 1356/*
1357 * set up a BDL entry
1358 */
5ae763b1
TI		 1359static int setup_bdle(struct azx *chip,
1360 struct snd_pcm_substream *substream,
675f25d4
TI		 1361 struct azx_dev *azx_dev, u32 **bdlp,
1362 int ofs, int size, int with_ioc)
1363{
675f25d4
TI		 1364 u32 *bdl = *bdlp;
1365
1366 while (size > 0) {
1367 dma_addr_t addr;
1368 int chunk;
1369
1370 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1371 return -EINVAL;
1372
77a23f26 1373 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1374 /* program the address field of the BDL entry */
1375 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1376 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1377 /* program the size field of the BDL entry */
fc4abee8 1378 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1379 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1380 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1381 u32 remain = 0x1000 - (ofs & 0xfff);
1382 if (chunk > remain)
1383 chunk = remain;
1384 }
675f25d4
TI		 1385 bdl[2] = cpu_to_le32(chunk);
1386 /* program the IOC to enable interrupt
1387 * only when the whole fragment is processed
1388 */
1389 size -= chunk;
1390 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1391 bdl += 4;
1392 azx_dev->frags++;
1393 ofs += chunk;
1394 }
1395 *bdlp = bdl;
1396 return ofs;
1397}
1398
1da177e4
LT		 1399/*
1400 * set up BDL entries
1401 */
555e219f
TI		 1402static int azx_setup_periods(struct azx *chip,
1403 struct snd_pcm_substream *substream,
4ce107b9 1404 struct azx_dev *azx_dev)
1da177e4 1405{
4ce107b9
TI		 1406 u32 *bdl;
1407 int i, ofs, periods, period_bytes;
555e219f 1408 int pos_adj;
1da177e4
LT		 1409
1410 /* reset BDL address */
1411 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1412 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1413
97b71c94 1414 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1415 periods = azx_dev->bufsize / period_bytes;
1416
1da177e4 1417 /* program the initial BDL entries */
4ce107b9
TI		 1418 bdl = (u32 *)azx_dev->bdl.area;
1419 ofs = 0;
1420 azx_dev->frags = 0;
555e219f
TI		 1421 pos_adj = bdl_pos_adj[chip->dev_index];
1422 if (pos_adj > 0) {
675f25d4 1423 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1424 int pos_align = pos_adj;
555e219f 1425 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1426 if (!pos_adj)
e785d3d8
TI		 1427 pos_adj = pos_align;
1428 else
1429 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1430 pos_align;
675f25d4
TI		 1431 pos_adj = frames_to_bytes(runtime, pos_adj);
1432 if (pos_adj >= period_bytes) {
4abc1cc2 1433 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1434 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1435 pos_adj = 0;
1436 } else {
5ae763b1 1437 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1438 &bdl, ofs, pos_adj,
1439 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1440 if (ofs < 0)
1441 goto error;
4ce107b9 1442 }
555e219f
TI		 1443 } else
1444 pos_adj = 0;
675f25d4
TI		 1445 for (i = 0; i < periods; i++) {
1446 if (i == periods - 1 && pos_adj)
5ae763b1 1447 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1448 period_bytes - pos_adj, 0);
1449 else
5ae763b1 1450 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1451 period_bytes,
1452 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1453 if (ofs < 0)
1454 goto error;
1da177e4 1455 }
4ce107b9 1456 return 0;
675f25d4
TI		 1457
1458 error:
4abc1cc2 1459 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1460 azx_dev->bufsize, period_bytes);
675f25d4 1461 return -EINVAL;
1da177e4
LT		 1462}
1463
1dddab40
TI		 1464/* reset stream */
1465static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1466{
1467 unsigned char val;
1468 int timeout;
1469
1dddab40
TI		 1470 azx_stream_clear(chip, azx_dev);
1471
d01ce99f
TI		 1472 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1473 SD_CTL_STREAM_RESET);
1da177e4
LT		 1474 udelay(3);
1475 timeout = 300;
1476 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1477 --timeout)
1478 ;
1479 val &= ~SD_CTL_STREAM_RESET;
1480 azx_sd_writeb(azx_dev, SD_CTL, val);
1481 udelay(3);
1482
1483 timeout = 300;
1484 /* waiting for hardware to report that the stream is out of reset */
1485 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1486 --timeout)
1487 ;
fa00e046
JK		 1488
1489 /* reset first position - may not be synced with hw at this time */
1490 *azx_dev->posbuf = 0;
1dddab40 1491}
1da177e4 1492
1dddab40
TI		 1493/*
1494 * set up the SD for streaming
1495 */
1496static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1497{
27fe48d9 1498 unsigned int val;
1dddab40
TI		 1499 /* make sure the run bit is zero for SD */
1500 azx_stream_clear(chip, azx_dev);
1da177e4 1501 /* program the stream_tag */
27fe48d9
TI		 1502 val = azx_sd_readl(azx_dev, SD_CTL);
1503 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1504 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1505 if (!azx_snoop(chip))
1506 val |= SD_CTL_TRAFFIC_PRIO;
1507 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1508
1509 /* program the length of samples in cyclic buffer */
1510 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1511
1512 /* program the stream format */
1513 /* this value needs to be the same as the one programmed */
1514 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1515
1516 /* program the stream LVI (last valid index) of the BDL */
1517 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1518
1519 /* program the BDL address */
1520 /* lower BDL address */
4ce107b9 1521 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1522 /* upper BDL address */
766979e0 1523 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1524
0be3b5d3 1525 /* enable the position buffer */
4cb36310
DH		 1526 if (chip->position_fix[0] != POS_FIX_LPIB ||
1527 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1528 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1529 azx_writel(chip, DPLBASE,
1530 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1531 }
c74db86b 1532
1da177e4 1533 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1534 azx_sd_writel(azx_dev, SD_CTL,
1535 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1536
1537 return 0;
1538}
1539
6ce4a3bc
TI		 1540/*
1541 * Probe the given codec address
1542 */
1543static int probe_codec(struct azx *chip, int addr)
1544{
1545 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1546 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1547 unsigned int res;
1548
a678cdee 1549 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1550 chip->probing = 1;
1551 azx_send_cmd(chip->bus, cmd);
deadff16 1552 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1553 chip->probing = 0;
a678cdee 1554 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1555 if (res == -1)
1556 return -EIO;
4abc1cc2 1557 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1558 return 0;
1559}
1560
33fa35ed
TI		 1561static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1562 struct hda_pcm *cpcm);
6ce4a3bc 1563static void azx_stop_chip(struct azx *chip);
1da177e4 1564
8dd78330
TI		 1565static void azx_bus_reset(struct hda_bus *bus)
1566{
1567 struct azx *chip = bus->private_data;
8dd78330
TI		 1568
1569 bus->in_reset = 1;
1570 azx_stop_chip(chip);
cd508fe5 1571 azx_init_chip(chip, 1);
65f75983 1572#ifdef CONFIG_PM
8dd78330 1573 if (chip->initialized) {
01b65bfb
TI		 1574 struct azx_pcm *p;
1575 list_for_each_entry(p, &chip->pcm_list, list)
1576 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1577 snd_hda_suspend(chip->bus);
1578 snd_hda_resume(chip->bus);
1579 }
65f75983 1580#endif
8dd78330
TI		 1581 bus->in_reset = 0;
1582}
1583
1da177e4
LT		 1584/*
1585 * Codec initialization
1586 */
1587
2f5983f2 1588/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1589static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1590 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1591 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1592};
1593
a82d51ed 1594static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1595{
1596 struct hda_bus_template bus_temp;
34c25350
TI		 1597 int c, codecs, err;
1598 int max_slots;
1da177e4
LT		 1599
1600 memset(&bus_temp, 0, sizeof(bus_temp));
1601 bus_temp.private_data = chip;
1602 bus_temp.modelname = model;
1603 bus_temp.pci = chip->pci;
111d3af5
TI		 1604 bus_temp.ops.command = azx_send_cmd;
1605 bus_temp.ops.get_response = azx_get_response;
176d5335 1606 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1607 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1608#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1609 bus_temp.power_save = &power_save;
cb53c626
TI		 1610 bus_temp.ops.pm_notify = azx_power_notify;
1611#endif
1da177e4 1612
d01ce99f
TI		 1613 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1614 if (err < 0)
1da177e4
LT		 1615 return err;
1616
9477c58e
TI		 1617 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1618 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1619 chip->bus->needs_damn_long_delay = 1;
9477c58e 1620 }
dc9c8e21 1621
34c25350 1622 codecs = 0;
2f5983f2
TI		 1623 max_slots = azx_max_codecs[chip->driver_type];
1624 if (!max_slots)
7445dfc1 1625 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1626
1627 /* First try to probe all given codec slots */
1628 for (c = 0; c < max_slots; c++) {
f1eaaeec 1629 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1630 if (probe_codec(chip, c) < 0) {
1631 /* Some BIOSen give you wrong codec addresses
1632 * that don't exist
1633 */
4abc1cc2
TI		 1634 snd_printk(KERN_WARNING SFX
1635 "Codec #%d probe error; "
6ce4a3bc
TI		 1636 "disabling it...\n", c);
1637 chip->codec_mask &= ~(1 << c);
1638 /* More badly, accessing to a non-existing
1639 * codec often screws up the controller chip,
2448158e 1640 * and disturbs the further communications.
6ce4a3bc
TI		 1641 * Thus if an error occurs during probing,
1642 * better to reset the controller chip to
1643 * get back to the sanity state.
1644 */
1645 azx_stop_chip(chip);
cd508fe5 1646 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1647 }
1648 }
1649 }
1650
d507cd66
TI		 1651 /* AMD chipsets often cause the communication stalls upon certain
1652 * sequence like the pin-detection. It seems that forcing the synced
1653 * access works around the stall. Grrr...
1654 */
9477c58e
TI		 1655 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1656 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1657 chip->bus->sync_write = 1;
1658 chip->bus->allow_bus_reset = 1;
1659 }
1660
6ce4a3bc 1661 /* Then create codec instances */
34c25350 1662 for (c = 0; c < max_slots; c++) {
f1eaaeec 1663 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1664 struct hda_codec *codec;
a1e21c90 1665 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1666 if (err < 0)
1667 continue;
2dca0bba 1668 codec->beep_mode = chip->beep_mode;
1da177e4 1669 codecs++;
19a982b6
TI		 1670 }
1671 }
1672 if (!codecs) {
1da177e4
LT		 1673 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1674 return -ENXIO;
1675 }
a1e21c90
TI		 1676 return 0;
1677}
1da177e4 1678
a1e21c90
TI		 1679/* configure each codec instance */
1680static int __devinit azx_codec_configure(struct azx *chip)
1681{
1682 struct hda_codec *codec;
1683 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684 snd_hda_codec_configure(codec);
1685 }
1da177e4
LT		 1686 return 0;
1687}
1688
1689
1690/*
1691 * PCM support
1692 */
1693
1694/* assign a stream for the PCM */
ef18bede
WF		 1695static inline struct azx_dev *
1696azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1697{
07e4ca50 1698 int dev, i, nums;
ef18bede 1699 struct azx_dev *res = NULL;
d5cf9911
TI		 1700 /* make a non-zero unique key for the substream */
1701 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1702 (substream->stream + 1);
ef18bede
WF		 1703
1704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1705 dev = chip->playback_index_offset;
1706 nums = chip->playback_streams;
1707 } else {
1708 dev = chip->capture_index_offset;
1709 nums = chip->capture_streams;
1710 }
1711 for (i = 0; i < nums; i++, dev++)
d01ce99f 1712 if (!chip->azx_dev[dev].opened) {
ef18bede 1713 res = &chip->azx_dev[dev];
d5cf9911 1714 if (res->assigned_key == key)
ef18bede 1715 break;
1da177e4 1716 }
ef18bede
WF		 1717 if (res) {
1718 res->opened = 1;
d5cf9911 1719 res->assigned_key = key;
ef18bede
WF		 1720 }
1721 return res;
1da177e4
LT		 1722}
1723
1724/* release the assigned stream */
a98f90fd 1725static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1726{
1727 azx_dev->opened = 0;
1728}
1729
a98f90fd 1730static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1731 .info = (SNDRV_PCM_INFO_MMAP |
1732 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1733 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1734 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1735 /* No full-resume yet implemented */
1736 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1737 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1738 SNDRV_PCM_INFO_SYNC_START |
1739 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1740 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1741 .rates = SNDRV_PCM_RATE_48000,
1742 .rate_min = 48000,
1743 .rate_max = 48000,
1744 .channels_min = 2,
1745 .channels_max = 2,
1746 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1747 .period_bytes_min = 128,
1748 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1749 .periods_min = 2,
1750 .periods_max = AZX_MAX_FRAG,
1751 .fifo_size = 0,
1752};
1753
a98f90fd 1754static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1755{
1756 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1757 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1758 struct azx *chip = apcm->chip;
1759 struct azx_dev *azx_dev;
1760 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1761 unsigned long flags;
1762 int err;
2ae66c26 1763 int buff_step;
1da177e4 1764
62932df8 1765 mutex_lock(&chip->open_mutex);
ef18bede 1766 azx_dev = azx_assign_device(chip, substream);
1da177e4 1767 if (azx_dev == NULL) {
62932df8 1768 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1769 return -EBUSY;
1770 }
1771 runtime->hw = azx_pcm_hw;
1772 runtime->hw.channels_min = hinfo->channels_min;
1773 runtime->hw.channels_max = hinfo->channels_max;
1774 runtime->hw.formats = hinfo->formats;
1775 runtime->hw.rates = hinfo->rates;
1776 snd_pcm_limit_hw_rates(runtime);
1777 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1778 if (chip->align_buffer_size)
2ae66c26
PLB		 1779 /* constrain buffer sizes to be multiple of 128
1780 bytes. This is more efficient in terms of memory
1781 access but isn't required by the HDA spec and
1782 prevents users from specifying exact period/buffer
1783 sizes. For example for 44.1kHz, a period size set
1784 to 20ms will be rounded to 19.59ms. */
1785 buff_step = 128;
1786 else
1787 /* Don't enforce steps on buffer sizes, still need to
1788 be multiple of 4 bytes (HDA spec). Tested on Intel
1789 HDA controllers, may not work on all devices where
1790 option needs to be disabled */
1791 buff_step = 4;
1792
5f1545bc 1793 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1794 buff_step);
5f1545bc 1795 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1796 buff_step);
b4a91cf0 1797 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1798 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1799 if (err < 0) {
1da177e4 1800 azx_release_device(azx_dev);
cb53c626 1801 snd_hda_power_down(apcm->codec);
62932df8 1802 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1803 return err;
1804 }
70d321e6 1805 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1806 /* sanity check */
1807 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1808 snd_BUG_ON(!runtime->hw.channels_max) ||
1809 snd_BUG_ON(!runtime->hw.formats) ||
1810 snd_BUG_ON(!runtime->hw.rates)) {
1811 azx_release_device(azx_dev);
1812 hinfo->ops.close(hinfo, apcm->codec, substream);
1813 snd_hda_power_down(apcm->codec);
1814 mutex_unlock(&chip->open_mutex);
1815 return -EINVAL;
1816 }
1da177e4
LT		 1817 spin_lock_irqsave(&chip->reg_lock, flags);
1818 azx_dev->substream = substream;
1819 azx_dev->running = 0;
1820 spin_unlock_irqrestore(&chip->reg_lock, flags);
1821
1822 runtime->private_data = azx_dev;
850f0e52 1823 snd_pcm_set_sync(substream);
62932df8 1824 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1825 return 0;
1826}
1827
a98f90fd 1828static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1829{
1830 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1831 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1832 struct azx *chip = apcm->chip;
1833 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1834 unsigned long flags;
1835
62932df8 1836 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1837 spin_lock_irqsave(&chip->reg_lock, flags);
1838 azx_dev->substream = NULL;
1839 azx_dev->running = 0;
1840 spin_unlock_irqrestore(&chip->reg_lock, flags);
1841 azx_release_device(azx_dev);
1842 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1843 snd_hda_power_down(apcm->codec);
62932df8 1844 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1845 return 0;
1846}
1847
d01ce99f
TI		 1848static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1849 struct snd_pcm_hw_params *hw_params)
1da177e4 1850{
27fe48d9
TI		 1851 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1852 struct azx *chip = apcm->chip;
1853 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1854 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1855 int ret;
97b71c94 1856
27fe48d9 1857 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1858 azx_dev->bufsize = 0;
1859 azx_dev->period_bytes = 0;
1860 azx_dev->format_val = 0;
27fe48d9 1861 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1862 params_buffer_bytes(hw_params));
27fe48d9
TI		 1863 if (ret < 0)
1864 return ret;
1865 mark_runtime_wc(chip, azx_dev, runtime, true);
1866 return ret;
1da177e4
LT		 1867}
1868
a98f90fd 1869static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1870{
1871 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1872 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1873 struct azx *chip = apcm->chip;
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1875 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1876
1877 /* reset BDL address */
1878 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1879 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1880 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1881 azx_dev->bufsize = 0;
1882 azx_dev->period_bytes = 0;
1883 azx_dev->format_val = 0;
1da177e4 1884
eb541337 1885 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1886
27fe48d9 1887 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1888 return snd_pcm_lib_free_pages(substream);
1889}
1890
a98f90fd 1891static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1892{
1893 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1894 struct azx *chip = apcm->chip;
1895 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1896 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1897 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1898 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1899 int err;
7c935976
SW		 1900 struct hda_spdif_out *spdif =
1901 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1902 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1903
fa00e046 1904 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1905 format_val = snd_hda_calc_stream_format(runtime->rate,
1906 runtime->channels,
1907 runtime->format,
32c168c8 1908 hinfo->maxbps,
7c935976 1909 ctls);
97b71c94 1910 if (!format_val) {
d01ce99f
TI		 1911 snd_printk(KERN_ERR SFX
1912 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1913 runtime->rate, runtime->channels, runtime->format);
1914 return -EINVAL;
1915 }
1916
97b71c94
TI		 1917 bufsize = snd_pcm_lib_buffer_bytes(substream);
1918 period_bytes = snd_pcm_lib_period_bytes(substream);
1919
4abc1cc2 1920 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1921 bufsize, format_val);
1922
1923 if (bufsize != azx_dev->bufsize ||
1924 period_bytes != azx_dev->period_bytes ||
1925 format_val != azx_dev->format_val) {
1926 azx_dev->bufsize = bufsize;
1927 azx_dev->period_bytes = period_bytes;
1928 azx_dev->format_val = format_val;
1929 err = azx_setup_periods(chip, substream, azx_dev);
1930 if (err < 0)
1931 return err;
1932 }
1933
e5463720
JK		 1934 /* wallclk has 24Mhz clock source */
1935 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1936 runtime->rate) * 1000);
1da177e4
LT		 1937 azx_setup_controller(chip, azx_dev);
1938 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1939 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1940 else
1941 azx_dev->fifo_size = 0;
1942
62b7e5e0
TI		 1943 stream_tag = azx_dev->stream_tag;
1944 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1945 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1946 stream_tag > chip->capture_streams)
1947 stream_tag -= chip->capture_streams;
1948 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1949 azx_dev->format_val, substream);
1da177e4
LT		 1950}
1951
a98f90fd 1952static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1953{
1954 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1955 struct azx *chip = apcm->chip;
850f0e52
TI		 1956 struct azx_dev *azx_dev;
1957 struct snd_pcm_substream *s;
fa00e046 1958 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1959 int nwait, timeout;
1da177e4 1960
1da177e4 1961 switch (cmd) {
fa00e046
JK		 1962 case SNDRV_PCM_TRIGGER_START:
1963 rstart = 1;
1da177e4
LT		 1964 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1965 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1966 start = 1;
1da177e4
LT		 1967 break;
1968 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1969 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1970 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1971 start = 0;
1da177e4
LT		 1972 break;
1973 default:
850f0e52
TI		 1974 return -EINVAL;
1975 }
1976
1977 snd_pcm_group_for_each_entry(s, substream) {
1978 if (s->pcm->card != substream->pcm->card)
1979 continue;
1980 azx_dev = get_azx_dev(s);
1981 sbits |= 1 << azx_dev->index;
1982 nsync++;
1983 snd_pcm_trigger_done(s, substream);
1984 }
1985
1986 spin_lock(&chip->reg_lock);
1987 if (nsync > 1) {
1988 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1989 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1990 azx_writel(chip, OLD_SSYNC,
1991 azx_readl(chip, OLD_SSYNC) | sbits);
1992 else
1993 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1994 }
1995 snd_pcm_group_for_each_entry(s, substream) {
1996 if (s->pcm->card != substream->pcm->card)
1997 continue;
1998 azx_dev = get_azx_dev(s);
e5463720
JK		 1999 if (start) {
2000 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2001 if (!rstart)
2002 azx_dev->start_wallclk -=
2003 azx_dev->period_wallclk;
850f0e52 2004 azx_stream_start(chip, azx_dev);
e5463720 2005 } else {
850f0e52 2006 azx_stream_stop(chip, azx_dev);
e5463720 2007 }
850f0e52 2008 azx_dev->running = start;
1da177e4
LT		 2009 }
2010 spin_unlock(&chip->reg_lock);
850f0e52
TI		 2011 if (start) {
2012 if (nsync == 1)
2013 return 0;
2014 /* wait until all FIFOs get ready */
2015 for (timeout = 5000; timeout; timeout--) {
2016 nwait = 0;
2017 snd_pcm_group_for_each_entry(s, substream) {
2018 if (s->pcm->card != substream->pcm->card)
2019 continue;
2020 azx_dev = get_azx_dev(s);
2021 if (!(azx_sd_readb(azx_dev, SD_STS) &
2022 SD_STS_FIFO_READY))
2023 nwait++;
2024 }
2025 if (!nwait)
2026 break;
2027 cpu_relax();
2028 }
2029 } else {
2030 /* wait until all RUN bits are cleared */
2031 for (timeout = 5000; timeout; timeout--) {
2032 nwait = 0;
2033 snd_pcm_group_for_each_entry(s, substream) {
2034 if (s->pcm->card != substream->pcm->card)
2035 continue;
2036 azx_dev = get_azx_dev(s);
2037 if (azx_sd_readb(azx_dev, SD_CTL) &
2038 SD_CTL_DMA_START)
2039 nwait++;
2040 }
2041 if (!nwait)
2042 break;
2043 cpu_relax();
2044 }
1da177e4 2045 }
850f0e52
TI		 2046 if (nsync > 1) {
2047 spin_lock(&chip->reg_lock);
2048 /* reset SYNC bits */
8b0bd226
TI		 2049 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2050 azx_writel(chip, OLD_SSYNC,
2051 azx_readl(chip, OLD_SSYNC) & ~sbits);
2052 else
2053 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 2054 spin_unlock(&chip->reg_lock);
2055 }
2056 return 0;
1da177e4
LT		 2057}
2058
0e153474
JC		 2059/* get the current DMA position with correction on VIA chips */
2060static unsigned int azx_via_get_position(struct azx *chip,
2061 struct azx_dev *azx_dev)
2062{
2063 unsigned int link_pos, mini_pos, bound_pos;
2064 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2065 unsigned int fifo_size;
2066
2067 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2068 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2069 /* Playback, no problem using link position */
2070 return link_pos;
2071 }
2072
2073 /* Capture */
2074 /* For new chipset,
2075 * use mod to get the DMA position just like old chipset
2076 */
2077 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2078 mod_dma_pos %= azx_dev->period_bytes;
2079
2080 /* azx_dev->fifo_size can't get FIFO size of in stream.
2081 * Get from base address + offset.
2082 */
2083 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2084
2085 if (azx_dev->insufficient) {
2086 /* Link position never gather than FIFO size */
2087 if (link_pos <= fifo_size)
2088 return 0;
2089
2090 azx_dev->insufficient = 0;
2091 }
2092
2093 if (link_pos <= fifo_size)
2094 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2095 else
2096 mini_pos = link_pos - fifo_size;
2097
2098 /* Find nearest previous boudary */
2099 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2100 mod_link_pos = link_pos % azx_dev->period_bytes;
2101 if (mod_link_pos >= fifo_size)
2102 bound_pos = link_pos - mod_link_pos;
2103 else if (mod_dma_pos >= mod_mini_pos)
2104 bound_pos = mini_pos - mod_mini_pos;
2105 else {
2106 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2107 if (bound_pos >= azx_dev->bufsize)
2108 bound_pos = 0;
2109 }
2110
2111 /* Calculate real DMA position we want */
2112 return bound_pos + mod_dma_pos;
2113}
2114
9ad593f6 2115static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2116 struct azx_dev *azx_dev,
2117 bool with_check)
1da177e4 2118{
1da177e4 2119 unsigned int pos;
4cb36310 2120 int stream = azx_dev->substream->stream;
1da177e4 2121
4cb36310
DH		 2122 switch (chip->position_fix[stream]) {
2123 case POS_FIX_LPIB:
2124 /* read LPIB */
2125 pos = azx_sd_readl(azx_dev, SD_LPIB);
2126 break;
2127 case POS_FIX_VIACOMBO:
0e153474 2128 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2129 break;
2130 default:
2131 /* use the position buffer */
2132 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2133 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2134 if (!pos || pos == (u32)-1) {
2135 printk(KERN_WARNING
2136 "hda-intel: Invalid position buffer, "
2137 "using LPIB read method instead.\n");
2138 chip->position_fix[stream] = POS_FIX_LPIB;
2139 pos = azx_sd_readl(azx_dev, SD_LPIB);
2140 } else
2141 chip->position_fix[stream] = POS_FIX_POSBUF;
2142 }
2143 break;
c74db86b 2144 }
4cb36310 2145
1da177e4
LT		 2146 if (pos >= azx_dev->bufsize)
2147 pos = 0;
9ad593f6
TI		 2148 return pos;
2149}
2150
2151static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2152{
2153 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2154 struct azx *chip = apcm->chip;
2155 struct azx_dev *azx_dev = get_azx_dev(substream);
2156 return bytes_to_frames(substream->runtime,
798cb7e8 2157 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2158}
2159
2160/*
2161 * Check whether the current DMA position is acceptable for updating
2162 * periods. Returns non-zero if it's OK.
2163 *
2164 * Many HD-audio controllers appear pretty inaccurate about
2165 * the update-IRQ timing. The IRQ is issued before actually the
2166 * data is processed. So, we need to process it afterwords in a
2167 * workqueue.
2168 */
2169static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2170{
e5463720 2171 u32 wallclk;
9ad593f6 2172 unsigned int pos;
beaffc39 2173 int stream;
9ad593f6 2174
f48f606d
JK		 2175 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2176 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2177 return -1; /* bogus (too early) interrupt */
fa00e046 2178
beaffc39 2179 stream = azx_dev->substream->stream;
798cb7e8 2180 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2181
d6d8bf54
TI		 2182 if (WARN_ONCE(!azx_dev->period_bytes,
2183 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2184 return -1; /* this shouldn't happen! */
edb39935 2185 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2186 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2187 /* NG - it's below the first next period boundary */
2188 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2189 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2190 return 1; /* OK, it's fine */
2191}
2192
2193/*
2194 * The work for pending PCM period updates.
2195 */
2196static void azx_irq_pending_work(struct work_struct *work)
2197{
2198 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2199 int i, pending, ok;
9ad593f6 2200
a6a950a8
TI		 2201 if (!chip->irq_pending_warned) {
2202 printk(KERN_WARNING
2203 "hda-intel: IRQ timing workaround is activated "
2204 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2205 chip->card->number);
2206 chip->irq_pending_warned = 1;
2207 }
2208
9ad593f6
TI		 2209 for (;;) {
2210 pending = 0;
2211 spin_lock_irq(&chip->reg_lock);
2212 for (i = 0; i < chip->num_streams; i++) {
2213 struct azx_dev *azx_dev = &chip->azx_dev[i];
2214 if (!azx_dev->irq_pending ||
2215 !azx_dev->substream ||
2216 !azx_dev->running)
2217 continue;
e5463720
JK		 2218 ok = azx_position_ok(chip, azx_dev);
2219 if (ok > 0) {
9ad593f6
TI		 2220 azx_dev->irq_pending = 0;
2221 spin_unlock(&chip->reg_lock);
2222 snd_pcm_period_elapsed(azx_dev->substream);
2223 spin_lock(&chip->reg_lock);
e5463720
JK		 2224 } else if (ok < 0) {
2225 pending = 0; /* too early */
9ad593f6
TI		 2226 } else
2227 pending++;
2228 }
2229 spin_unlock_irq(&chip->reg_lock);
2230 if (!pending)
2231 return;
08af495f 2232 msleep(1);
9ad593f6
TI		 2233 }
2234}
2235
2236/* clear irq_pending flags and assure no on-going workq */
2237static void azx_clear_irq_pending(struct azx *chip)
2238{
2239 int i;
2240
2241 spin_lock_irq(&chip->reg_lock);
2242 for (i = 0; i < chip->num_streams; i++)
2243 chip->azx_dev[i].irq_pending = 0;
2244 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2245}
2246
27fe48d9
TI		 2247#ifdef CONFIG_X86
2248static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2249 struct vm_area_struct *area)
2250{
2251 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2252 struct azx *chip = apcm->chip;
2253 if (!azx_snoop(chip))
2254 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2255 return snd_pcm_lib_default_mmap(substream, area);
2256}
2257#else
2258#define azx_pcm_mmap NULL
2259#endif
2260
a98f90fd 2261static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2262 .open = azx_pcm_open,
2263 .close = azx_pcm_close,
2264 .ioctl = snd_pcm_lib_ioctl,
2265 .hw_params = azx_pcm_hw_params,
2266 .hw_free = azx_pcm_hw_free,
2267 .prepare = azx_pcm_prepare,
2268 .trigger = azx_pcm_trigger,
2269 .pointer = azx_pcm_pointer,
27fe48d9 2270 .mmap = azx_pcm_mmap,
4ce107b9 2271 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2272};
2273
a98f90fd 2274static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2275{
176d5335
TI		 2276 struct azx_pcm *apcm = pcm->private_data;
2277 if (apcm) {
01b65bfb 2278 list_del(&apcm->list);
176d5335
TI		 2279 kfree(apcm);
2280 }
1da177e4
LT		 2281}
2282
acfa634f
TI		 2283#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2284
176d5335 2285static int
33fa35ed
TI		 2286azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2287 struct hda_pcm *cpcm)
1da177e4 2288{
33fa35ed 2289 struct azx *chip = bus->private_data;
a98f90fd 2290 struct snd_pcm *pcm;
1da177e4 2291 struct azx_pcm *apcm;
176d5335 2292 int pcm_dev = cpcm->device;
acfa634f 2293 unsigned int size;
176d5335 2294 int s, err;
1da177e4 2295
01b65bfb
TI		 2296 list_for_each_entry(apcm, &chip->pcm_list, list) {
2297 if (apcm->pcm->device == pcm_dev) {
2298 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2299 return -EBUSY;
2300 }
176d5335
TI		 2301 }
2302 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2303 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2304 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2305 &pcm);
2306 if (err < 0)
2307 return err;
18cb7109 2308 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2309 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2310 if (apcm == NULL)
2311 return -ENOMEM;
2312 apcm->chip = chip;
01b65bfb 2313 apcm->pcm = pcm;
1da177e4 2314 apcm->codec = codec;
1da177e4
LT		 2315 pcm->private_data = apcm;
2316 pcm->private_free = azx_pcm_free;
176d5335
TI		 2317 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2318 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2319 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2320 cpcm->pcm = pcm;
2321 for (s = 0; s < 2; s++) {
2322 apcm->hinfo[s] = &cpcm->stream[s];
2323 if (cpcm->stream[s].substreams)
2324 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2325 }
2326 /* buffer pre-allocation */
acfa634f
TI		 2327 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2328 if (size > MAX_PREALLOC_SIZE)
2329 size = MAX_PREALLOC_SIZE;
4ce107b9 2330 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2331 snd_dma_pci_data(chip->pci),
acfa634f 2332 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2333 return 0;
2334}
2335
2336/*
2337 * mixer creation - all stuff is implemented in hda module
2338 */
a98f90fd 2339static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2340{
2341 return snd_hda_build_controls(chip->bus);
2342}
2343
2344
2345/*
2346 * initialize SD streams
2347 */
a98f90fd 2348static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2349{
2350 int i;
2351
2352 /* initialize each stream (aka device)
d01ce99f
TI		 2353 * assign the starting bdl address to each stream (device)
2354 * and initialize
1da177e4 2355 */
07e4ca50 2356 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2357 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2358 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2359 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2360 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2361 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2362 azx_dev->sd_int_sta_mask = 1 << i;
2363 /* stream tag: must be non-zero and unique */
2364 azx_dev->index = i;
2365 azx_dev->stream_tag = i + 1;
2366 }
2367
2368 return 0;
2369}
2370
68e7fffc
TI		 2371static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2372{
437a5a46
TI		 2373 if (request_irq(chip->pci->irq, azx_interrupt,
2374 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2375 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2376 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2377 "disabling device\n", chip->pci->irq);
2378 if (do_disconnect)
2379 snd_card_disconnect(chip->card);
2380 return -1;
2381 }
2382 chip->irq = chip->pci->irq;
69e13418 2383 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2384 return 0;
2385}
2386
1da177e4 2387
cb53c626
TI		 2388static void azx_stop_chip(struct azx *chip)
2389{
95e99fda 2390 if (!chip->initialized)
cb53c626
TI		 2391 return;
2392
2393 /* disable interrupts */
2394 azx_int_disable(chip);
2395 azx_int_clear(chip);
2396
2397 /* disable CORB/RIRB */
2398 azx_free_cmd_io(chip);
2399
2400 /* disable position buffer */
2401 azx_writel(chip, DPLBASE, 0);
2402 azx_writel(chip, DPUBASE, 0);
2403
2404 chip->initialized = 0;
2405}
2406
2407#ifdef CONFIG_SND_HDA_POWER_SAVE
2408/* power-up/down the controller */
68467f51 2409static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2410{
33fa35ed 2411 struct azx *chip = bus->private_data;
cb53c626 2412
68467f51 2413 if (power_up)
b8dfc462
ML		 2414 pm_runtime_get_sync(&chip->pci->dev);
2415 else
2416 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2417}
65fcd41d
TI		 2418
2419static DEFINE_MUTEX(card_list_lock);
2420static LIST_HEAD(card_list);
2421
2422static void azx_add_card_list(struct azx *chip)
2423{
2424 mutex_lock(&card_list_lock);
2425 list_add(&chip->list, &card_list);
2426 mutex_unlock(&card_list_lock);
2427}
2428
2429static void azx_del_card_list(struct azx *chip)
2430{
2431 mutex_lock(&card_list_lock);
2432 list_del_init(&chip->list);
2433 mutex_unlock(&card_list_lock);
2434}
2435
2436/* trigger power-save check at writing parameter */
2437static int param_set_xint(const char *val, const struct kernel_param *kp)
2438{
2439 struct azx *chip;
2440 struct hda_codec *c;
2441 int prev = power_save;
2442 int ret = param_set_int(val, kp);
2443
2444 if (ret || prev == power_save)
2445 return ret;
2446
2447 mutex_lock(&card_list_lock);
2448 list_for_each_entry(chip, &card_list, list) {
2449 if (!chip->bus || chip->disabled)
2450 continue;
2451 list_for_each_entry(c, &chip->bus->codec_list, list)
2452 snd_hda_power_sync(c);
2453 }
2454 mutex_unlock(&card_list_lock);
2455 return 0;
2456}
2457#else
2458#define azx_add_card_list(chip) /* NOP */
2459#define azx_del_card_list(chip) /* NOP */
5c0b9bec
TI		 2460#endif /* CONFIG_SND_HDA_POWER_SAVE */
2461
7ccbde57 2462#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2463/*
2464 * power management
2465 */
68cb2b55 2466static int azx_suspend(struct device *dev)
1da177e4 2467{
68cb2b55
TI		 2468 struct pci_dev *pci = to_pci_dev(dev);
2469 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2470 struct azx *chip = card->private_data;
01b65bfb 2471 struct azx_pcm *p;
1da177e4 2472
421a1252 2473 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2474 azx_clear_irq_pending(chip);
01b65bfb
TI		 2475 list_for_each_entry(p, &chip->pcm_list, list)
2476 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2477 if (chip->initialized)
8dd78330 2478 snd_hda_suspend(chip->bus);
cb53c626 2479 azx_stop_chip(chip);
30b35399 2480 if (chip->irq >= 0) {
43001c95 2481 free_irq(chip->irq, chip);
30b35399
TI		 2482 chip->irq = -1;
2483 }
68e7fffc 2484 if (chip->msi)
43001c95 2485 pci_disable_msi(chip->pci);
421a1252
TI		 2486 pci_disable_device(pci);
2487 pci_save_state(pci);
68cb2b55 2488 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2489 return 0;
2490}
2491
68cb2b55 2492static int azx_resume(struct device *dev)
1da177e4 2493{
68cb2b55
TI		 2494 struct pci_dev *pci = to_pci_dev(dev);
2495 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2496 struct azx *chip = card->private_data;
1da177e4 2497
d14a7e0b
TI		 2498 pci_set_power_state(pci, PCI_D0);
2499 pci_restore_state(pci);
30b35399
TI		 2500 if (pci_enable_device(pci) < 0) {
2501 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2502 "disabling device\n");
2503 snd_card_disconnect(card);
2504 return -EIO;
2505 }
2506 pci_set_master(pci);
68e7fffc
TI		 2507 if (chip->msi)
2508 if (pci_enable_msi(pci) < 0)
2509 chip->msi = 0;
2510 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2511 return -EIO;
cb53c626 2512 azx_init_pci(chip);
d804ad92 2513
7f30830b 2514 azx_init_chip(chip, 1);
d804ad92 2515
1da177e4 2516 snd_hda_resume(chip->bus);
421a1252 2517 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2518 return 0;
2519}
b8dfc462
ML		 2520#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2521
2522#ifdef CONFIG_PM_RUNTIME
2523static int azx_runtime_suspend(struct device *dev)
2524{
2525 struct snd_card *card = dev_get_drvdata(dev);
2526 struct azx *chip = card->private_data;
2527
5d6147f1 2528#ifdef CONFIG_SND_HDA_POWER_SAVE
b8dfc462
ML		 2529 if (!power_save_controller)
2530 return -EAGAIN;
5d6147f1 2531#endif
b8dfc462
ML		 2532
2533 azx_stop_chip(chip);
2534 azx_clear_irq_pending(chip);
2535 return 0;
2536}
2537
2538static int azx_runtime_resume(struct device *dev)
2539{
2540 struct snd_card *card = dev_get_drvdata(dev);
2541 struct azx *chip = card->private_data;
2542
2543 azx_init_pci(chip);
2544 azx_init_chip(chip, 1);
2545 return 0;
2546}
2547#endif /* CONFIG_PM_RUNTIME */
2548
2549#ifdef CONFIG_PM
2550static const struct dev_pm_ops azx_pm = {
2551 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2552 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2553};
2554
68cb2b55
TI		 2555#define AZX_PM_OPS &azx_pm
2556#else
68cb2b55 2557#define AZX_PM_OPS NULL
b8dfc462 2558#endif /* CONFIG_PM */
1da177e4
LT		 2559
2560
0cbf0098
TI		 2561/*
2562 * reboot notifier for hang-up problem at power-down
2563 */
2564static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2565{
2566 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2567 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2568 azx_stop_chip(chip);
2569 return NOTIFY_OK;
2570}
2571
2572static void azx_notifier_register(struct azx *chip)
2573{
2574 chip->reboot_notifier.notifier_call = azx_halt;
2575 register_reboot_notifier(&chip->reboot_notifier);
2576}
2577
2578static void azx_notifier_unregister(struct azx *chip)
2579{
2580 if (chip->reboot_notifier.notifier_call)
2581 unregister_reboot_notifier(&chip->reboot_notifier);
2582}
2583
a82d51ed
TI		 2584static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2585static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2586
8393ec4a 2587#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2588static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2589
a82d51ed
TI		 2590static void azx_vs_set_state(struct pci_dev *pci,
2591 enum vga_switcheroo_state state)
2592{
2593 struct snd_card *card = pci_get_drvdata(pci);
2594 struct azx *chip = card->private_data;
2595 bool disabled;
2596
2597 if (chip->init_failed)
2598 return;
2599
2600 disabled = (state == VGA_SWITCHEROO_OFF);
2601 if (chip->disabled == disabled)
2602 return;
2603
2604 if (!chip->bus) {
2605 chip->disabled = disabled;
2606 if (!disabled) {
2607 snd_printk(KERN_INFO SFX
2608 "%s: Start delayed initialization\n",
2609 pci_name(chip->pci));
2610 if (azx_first_init(chip) < 0 ||
2611 azx_probe_continue(chip) < 0) {
2612 snd_printk(KERN_ERR SFX
2613 "%s: initialization error\n",
2614 pci_name(chip->pci));
2615 chip->init_failed = true;
2616 }
2617 }
2618 } else {
2619 snd_printk(KERN_INFO SFX
2620 "%s %s via VGA-switcheroo\n",
2621 disabled ? "Disabling" : "Enabling",
2622 pci_name(chip->pci));
2623 if (disabled) {
68cb2b55 2624 azx_suspend(&pci->dev);
a82d51ed
TI		 2625 chip->disabled = true;
2626 snd_hda_lock_devices(chip->bus);
2627 } else {
2628 snd_hda_unlock_devices(chip->bus);
2629 chip->disabled = false;
68cb2b55 2630 azx_resume(&pci->dev);
a82d51ed
TI		 2631 }
2632 }
2633}
2634
2635static bool azx_vs_can_switch(struct pci_dev *pci)
2636{
2637 struct snd_card *card = pci_get_drvdata(pci);
2638 struct azx *chip = card->private_data;
2639
2640 if (chip->init_failed)
2641 return false;
2642 if (chip->disabled || !chip->bus)
2643 return true;
2644 if (snd_hda_lock_devices(chip->bus))
2645 return false;
2646 snd_hda_unlock_devices(chip->bus);
2647 return true;
2648}
2649
2650static void __devinit init_vga_switcheroo(struct azx *chip)
2651{
2652 struct pci_dev *p = get_bound_vga(chip->pci);
2653 if (p) {
2654 snd_printk(KERN_INFO SFX
2655 "%s: Handle VGA-switcheroo audio client\n",
2656 pci_name(chip->pci));
2657 chip->use_vga_switcheroo = 1;
2658 pci_dev_put(p);
2659 }
2660}
2661
2662static const struct vga_switcheroo_client_ops azx_vs_ops = {
2663 .set_gpu_state = azx_vs_set_state,
2664 .can_switch = azx_vs_can_switch,
2665};
2666
2667static int __devinit register_vga_switcheroo(struct azx *chip)
2668{
2669 if (!chip->use_vga_switcheroo)
2670 return 0;
2671 /* FIXME: currently only handling DIS controller
2672 * is there any machine with two switchable HDMI audio controllers?
2673 */
2674 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2675 VGA_SWITCHEROO_DIS,
2676 chip->bus != NULL);
2677}
2678#else
2679#define init_vga_switcheroo(chip) /* NOP */
2680#define register_vga_switcheroo(chip) 0
8393ec4a 2681#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2682#endif /* SUPPORT_VGA_SWITCHER */
2683
1da177e4
LT		 2684/*
2685 * destructor
2686 */
a98f90fd 2687static int azx_free(struct azx *chip)
1da177e4 2688{
4ce107b9
TI		 2689 int i;
2690
65fcd41d
TI		 2691 azx_del_card_list(chip);
2692
0cbf0098
TI		 2693 azx_notifier_unregister(chip);
2694
a82d51ed
TI		 2695 if (use_vga_switcheroo(chip)) {
2696 if (chip->disabled && chip->bus)
2697 snd_hda_unlock_devices(chip->bus);
2698 vga_switcheroo_unregister_client(chip->pci);
2699 }
2700
ce43fbae 2701 if (chip->initialized) {
9ad593f6 2702 azx_clear_irq_pending(chip);
07e4ca50 2703 for (i = 0; i < chip->num_streams; i++)
1da177e4 2704 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2705 azx_stop_chip(chip);
1da177e4
LT		 2706 }
2707
f000fd80 2708 if (chip->irq >= 0)
1da177e4 2709 free_irq(chip->irq, (void*)chip);
68e7fffc 2710 if (chip->msi)
30b35399 2711 pci_disable_msi(chip->pci);
f079c25a
TI		 2712 if (chip->remap_addr)
2713 iounmap(chip->remap_addr);
1da177e4 2714
4ce107b9
TI		 2715 if (chip->azx_dev) {
2716 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2717 if (chip->azx_dev[i].bdl.area) {
2718 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2719 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2720 }
4ce107b9 2721 }
27fe48d9
TI		 2722 if (chip->rb.area) {
2723 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2724 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2725 }
2726 if (chip->posbuf.area) {
2727 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2728 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2729 }
a82d51ed
TI		 2730 if (chip->region_requested)
2731 pci_release_regions(chip->pci);
1da177e4 2732 pci_disable_device(chip->pci);
07e4ca50 2733 kfree(chip->azx_dev);
4918cdab
TI		 2734#ifdef CONFIG_SND_HDA_PATCH_LOADER
2735 if (chip->fw)
2736 release_firmware(chip->fw);
2737#endif
1da177e4
LT		 2738 kfree(chip);
2739
2740 return 0;
2741}
2742
a98f90fd 2743static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2744{
2745 return azx_free(device->device_data);
2746}
2747
8393ec4a 2748#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2749/*
2750 * Check of disabled HDMI controller by vga-switcheroo
2751 */
2752static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2753{
2754 struct pci_dev *p;
2755
2756 /* check only discrete GPU */
2757 switch (pci->vendor) {
2758 case PCI_VENDOR_ID_ATI:
2759 case PCI_VENDOR_ID_AMD:
2760 case PCI_VENDOR_ID_NVIDIA:
2761 if (pci->devfn == 1) {
2762 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2763 pci->bus->number, 0);
2764 if (p) {
2765 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2766 return p;
2767 pci_dev_put(p);
2768 }
2769 }
2770 break;
2771 }
2772 return NULL;
2773}
2774
2775static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2776{
2777 bool vga_inactive = false;
2778 struct pci_dev *p = get_bound_vga(pci);
2779
2780 if (p) {
12b78a7f 2781 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2782 vga_inactive = true;
2783 pci_dev_put(p);
2784 }
2785 return vga_inactive;
2786}
8393ec4a 2787#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2788
3372a153
TI		 2789/*
2790 * white/black-listing for position_fix
2791 */
623ec047 2792static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2793 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2794 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2795 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2796 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2797 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2798 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2799 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2800 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2801 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2802 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2803 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2804 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2805 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2806 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2807 {}
2808};
2809
2810static int __devinit check_position_fix(struct azx *chip, int fix)
2811{
2812 const struct snd_pci_quirk *q;
2813
c673ba1c
TI		 2814 switch (fix) {
2815 case POS_FIX_LPIB:
2816 case POS_FIX_POSBUF:
4cb36310 2817 case POS_FIX_VIACOMBO:
a6f2fd55 2818 case POS_FIX_COMBO:
c673ba1c
TI		 2819 return fix;
2820 }
2821
c673ba1c
TI		 2822 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2823 if (q) {
2824 printk(KERN_INFO
2825 "hda_intel: position_fix set to %d "
2826 "for device %04x:%04x\n",
2827 q->value, q->subvendor, q->subdevice);
2828 return q->value;
3372a153 2829 }
bdd9ef24
DH		 2830
2831 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2832 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2833 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2834 return POS_FIX_VIACOMBO;
9477c58e
TI		 2835 }
2836 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2837 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2838 return POS_FIX_LPIB;
bdd9ef24 2839 }
c20c5a84
SH		 2840 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2841 snd_printd(SFX "Using COMBO position fix\n");
2842 return POS_FIX_COMBO;
2843 }
c673ba1c 2844 return POS_FIX_AUTO;
3372a153
TI		 2845}
2846
669ba27a
TI		 2847/*
2848 * black-lists for probe_mask
2849 */
2850static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2851 /* Thinkpad often breaks the controller communication when accessing
2852 * to the non-working (or non-existing) modem codec slot.
2853 */
2854 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2855 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2856 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2857 /* broken BIOS */
2858 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2859 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2860 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2861 /* forced codec slots */
93574844 2862 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2863 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2864 /* WinFast VP200 H (Teradici) user reported broken communication */
2865 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2866 {}
2867};
2868
f1eaaeec
TI		 2869#define AZX_FORCE_CODEC_MASK 0x100
2870
5aba4f8e 2871static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2872{
2873 const struct snd_pci_quirk *q;
2874
f1eaaeec
TI		 2875 chip->codec_probe_mask = probe_mask[dev];
2876 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2877 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2878 if (q) {
2879 printk(KERN_INFO
2880 "hda_intel: probe_mask set to 0x%x "
2881 "for device %04x:%04x\n",
2882 q->value, q->subvendor, q->subdevice);
f1eaaeec 2883 chip->codec_probe_mask = q->value;
669ba27a
TI		 2884 }
2885 }
f1eaaeec
TI		 2886
2887 /* check forced option */
2888 if (chip->codec_probe_mask != -1 &&
2889 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2890 chip->codec_mask = chip->codec_probe_mask & 0xff;
2891 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2892 chip->codec_mask);
2893 }
669ba27a
TI		 2894}
2895
4d8e22e0 2896/*
71623855 2897 * white/black-list for enable_msi
4d8e22e0 2898 */
71623855 2899static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2900 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2901 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2902 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2903 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2904 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2905 {}
2906};
2907
2908static void __devinit check_msi(struct azx *chip)
2909{
2910 const struct snd_pci_quirk *q;
2911
71623855
TI		 2912 if (enable_msi >= 0) {
2913 chip->msi = !!enable_msi;
4d8e22e0 2914 return;
71623855
TI		 2915 }
2916 chip->msi = 1; /* enable MSI as default */
2917 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2918 if (q) {
2919 printk(KERN_INFO
2920 "hda_intel: msi for device %04x:%04x set to %d\n",
2921 q->subvendor, q->subdevice, q->value);
2922 chip->msi = q->value;
80c43ed7
TI		 2923 return;
2924 }
2925
2926 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2927 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2928 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2929 chip->msi = 0;
4d8e22e0
TI		 2930 }
2931}
2932
a1585d76
TI		 2933/* check the snoop mode availability */
2934static void __devinit azx_check_snoop_available(struct azx *chip)
2935{
2936 bool snoop = chip->snoop;
2937
2938 switch (chip->driver_type) {
2939 case AZX_DRIVER_VIA:
2940 /* force to non-snoop mode for a new VIA controller
2941 * when BIOS is set
2942 */
2943 if (snoop) {
2944 u8 val;
2945 pci_read_config_byte(chip->pci, 0x42, &val);
2946 if (!(val & 0x80) && chip->pci->revision == 0x30)
2947 snoop = false;
2948 }
2949 break;
2950 case AZX_DRIVER_ATIHDMI_NS:
2951 /* new ATI HDMI requires non-snoop */
2952 snoop = false;
2953 break;
2954 }
2955
2956 if (snoop != chip->snoop) {
2957 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2958 snoop ? "snoop" : "non-snoop");
2959 chip->snoop = snoop;
2960 }
2961}
669ba27a 2962
1da177e4
LT		 2963/*
2964 * constructor
2965 */
a98f90fd 2966static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2967 int dev, unsigned int driver_caps,
a98f90fd 2968 struct azx **rchip)
1da177e4 2969{
a98f90fd 2970 static struct snd_device_ops ops = {
1da177e4
LT		 2971 .dev_free = azx_dev_free,
2972 };
a82d51ed
TI		 2973 struct azx *chip;
2974 int err;
1da177e4
LT		 2975
2976 *rchip = NULL;
bcd72003 2977
927fc866
PM		 2978 err = pci_enable_device(pci);
2979 if (err < 0)
1da177e4
LT		 2980 return err;
2981
e560d8d8 2982 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2983 if (!chip) {
1da177e4
LT		 2984 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2985 pci_disable_device(pci);
2986 return -ENOMEM;
2987 }
2988
2989 spin_lock_init(&chip->reg_lock);
62932df8 2990 mutex_init(&chip->open_mutex);
1da177e4
LT		 2991 chip->card = card;
2992 chip->pci = pci;
2993 chip->irq = -1;
9477c58e
TI		 2994 chip->driver_caps = driver_caps;
2995 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2996 check_msi(chip);
555e219f 2997 chip->dev_index = dev;
9ad593f6 2998 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2999 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3000 INIT_LIST_HEAD(&chip->list);
a82d51ed 3001 init_vga_switcheroo(chip);
1da177e4 3002
beaffc39
SG		 3003 chip->position_fix[0] = chip->position_fix[1] =
3004 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3005 /* combo mode uses LPIB for playback */
3006 if (chip->position_fix[0] == POS_FIX_COMBO) {
3007 chip->position_fix[0] = POS_FIX_LPIB;
3008 chip->position_fix[1] = POS_FIX_AUTO;
3009 }
3010
5aba4f8e 3011 check_probe_mask(chip, dev);
3372a153 3012
27346166 3013 chip->single_cmd = single_cmd;
27fe48d9 3014 chip->snoop = hda_snoop;
a1585d76 3015 azx_check_snoop_available(chip);
c74db86b 3016
5c0d7bc1
TI		 3017 if (bdl_pos_adj[dev] < 0) {
3018 switch (chip->driver_type) {
0c6341ac 3019 case AZX_DRIVER_ICH:
32679f95 3020 case AZX_DRIVER_PCH:
0c6341ac 3021 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3022 break;
3023 default:
0c6341ac 3024 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3025 break;
3026 }
3027 }
3028
a82d51ed
TI		 3029 if (check_hdmi_disabled(pci)) {
3030 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3031 pci_name(pci));
3032 if (use_vga_switcheroo(chip)) {
3033 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3034 chip->disabled = true;
3035 goto ok;
3036 }
3037 kfree(chip);
3038 pci_disable_device(pci);
3039 return -ENXIO;
3040 }
3041
3042 err = azx_first_init(chip);
3043 if (err < 0) {
3044 azx_free(chip);
3045 return err;
3046 }
3047
3048 ok:
3049 err = register_vga_switcheroo(chip);
3050 if (err < 0) {
3051 snd_printk(KERN_ERR SFX
3052 "Error registering VGA-switcheroo client\n");
3053 azx_free(chip);
3054 return err;
3055 }
3056
3057 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3058 if (err < 0) {
3059 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3060 azx_free(chip);
3061 return err;
3062 }
3063
3064 *rchip = chip;
3065 return 0;
3066}
3067
3068static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3069{
3070 int dev = chip->dev_index;
3071 struct pci_dev *pci = chip->pci;
3072 struct snd_card *card = chip->card;
3073 int i, err;
3074 unsigned short gcap;
3075
07e4ca50
TI		 3076#if BITS_PER_LONG != 64
3077 /* Fix up base address on ULI M5461 */
3078 if (chip->driver_type == AZX_DRIVER_ULI) {
3079 u16 tmp3;
3080 pci_read_config_word(pci, 0x40, &tmp3);
3081 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3082 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3083 }
3084#endif
3085
927fc866 3086 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3087 if (err < 0)
1da177e4 3088 return err;
a82d51ed 3089 chip->region_requested = 1;
1da177e4 3090
927fc866 3091 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3092 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 3093 if (chip->remap_addr == NULL) {
3094 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3095 return -ENXIO;
1da177e4
LT		 3096 }
3097
68e7fffc
TI		 3098 if (chip->msi)
3099 if (pci_enable_msi(pci) < 0)
3100 chip->msi = 0;
7376d013 3101
a82d51ed
TI		 3102 if (azx_acquire_irq(chip, 0) < 0)
3103 return -EBUSY;
1da177e4
LT		 3104
3105 pci_set_master(pci);
3106 synchronize_irq(chip->irq);
3107
bcd72003 3108 gcap = azx_readw(chip, GCAP);
4abc1cc2 3109 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3110
dc4c2e6b 3111 /* disable SB600 64bit support for safety */
9477c58e 3112 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3113 struct pci_dev *p_smbus;
3114 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3115 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3116 NULL);
3117 if (p_smbus) {
3118 if (p_smbus->revision < 0x30)
3119 gcap &= ~ICH6_GCAP_64OK;
3120 pci_dev_put(p_smbus);
3121 }
3122 }
09240cf4 3123
9477c58e
TI		 3124 /* disable 64bit DMA address on some devices */
3125 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3126 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3127 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3128 }
396087ea 3129
2ae66c26 3130 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3131 if (align_buffer_size >= 0)
3132 chip->align_buffer_size = !!align_buffer_size;
3133 else {
3134 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3135 chip->align_buffer_size = 0;
3136 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3137 chip->align_buffer_size = 1;
3138 else
3139 chip->align_buffer_size = 1;
3140 }
2ae66c26 3141
cf7aaca8 3142 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3143 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3144 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3145 else {
e930438c
YH		 3146 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3147 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3148 }
cf7aaca8 3149
8b6ed8e7
TI		 3150 /* read number of streams from GCAP register instead of using
3151 * hardcoded value
3152 */
3153 chip->capture_streams = (gcap >> 8) & 0x0f;
3154 chip->playback_streams = (gcap >> 12) & 0x0f;
3155 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3156 /* gcap didn't give any info, switching to old method */
3157
3158 switch (chip->driver_type) {
3159 case AZX_DRIVER_ULI:
3160 chip->playback_streams = ULI_NUM_PLAYBACK;
3161 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3162 break;
3163 case AZX_DRIVER_ATIHDMI:
1815b34a 3164 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3165 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3166 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3167 break;
c4da29ca 3168 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3169 default:
3170 chip->playback_streams = ICH6_NUM_PLAYBACK;
3171 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3172 break;
3173 }
07e4ca50 3174 }
8b6ed8e7
TI		 3175 chip->capture_index_offset = 0;
3176 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3177 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3178 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3179 GFP_KERNEL);
927fc866 3180 if (!chip->azx_dev) {
4abc1cc2 3181 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3182 return -ENOMEM;
07e4ca50
TI		 3183 }
3184
4ce107b9
TI		 3185 for (i = 0; i < chip->num_streams; i++) {
3186 /* allocate memory for the BDL for each stream */
3187 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3188 snd_dma_pci_data(chip->pci),
3189 BDL_SIZE, &chip->azx_dev[i].bdl);
3190 if (err < 0) {
3191 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3192 return -ENOMEM;
4ce107b9 3193 }
27fe48d9 3194 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3195 }
0be3b5d3 3196 /* allocate memory for the position buffer */
d01ce99f
TI		 3197 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3198 snd_dma_pci_data(chip->pci),
3199 chip->num_streams * 8, &chip->posbuf);
3200 if (err < 0) {
0be3b5d3 3201 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3202 return -ENOMEM;
1da177e4 3203 }
27fe48d9 3204 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3205 /* allocate CORB/RIRB */
81740861
TI		 3206 err = azx_alloc_cmd_io(chip);
3207 if (err < 0)
a82d51ed 3208 return err;
1da177e4
LT		 3209
3210 /* initialize streams */
3211 azx_init_stream(chip);
3212
3213 /* initialize chip */
cb53c626 3214 azx_init_pci(chip);
10e77dda 3215 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3216
3217 /* codec detection */
927fc866 3218 if (!chip->codec_mask) {
1da177e4 3219 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3220 return -ENODEV;
1da177e4
LT		 3221 }
3222
07e4ca50 3223 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3224 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3225 sizeof(card->shortname));
3226 snprintf(card->longname, sizeof(card->longname),
3227 "%s at 0x%lx irq %i",
3228 card->shortname, chip->addr, chip->irq);
07e4ca50 3229
1da177e4 3230 return 0;
1da177e4
LT		 3231}
3232
cb53c626
TI		 3233static void power_down_all_codecs(struct azx *chip)
3234{
3235#ifdef CONFIG_SND_HDA_POWER_SAVE
3236 /* The codecs were powered up in snd_hda_codec_new().
3237 * Now all initialization done, so turn them down if possible
3238 */
3239 struct hda_codec *codec;
3240 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3241 snd_hda_power_down(codec);
3242 }
3243#endif
3244}
3245
97c6a3d1 3246#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3247/* callback from request_firmware_nowait() */
3248static void azx_firmware_cb(const struct firmware *fw, void *context)
3249{
3250 struct snd_card *card = context;
3251 struct azx *chip = card->private_data;
3252 struct pci_dev *pci = chip->pci;
3253
3254 if (!fw) {
3255 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3256 goto error;
3257 }
3258
3259 chip->fw = fw;
3260 if (!chip->disabled) {
3261 /* continue probing */
3262 if (azx_probe_continue(chip))
3263 goto error;
3264 }
3265 return; /* OK */
3266
3267 error:
3268 snd_card_free(card);
3269 pci_set_drvdata(pci, NULL);
3270}
97c6a3d1 3271#endif
5cb543db 3272
d01ce99f
TI		 3273static int __devinit azx_probe(struct pci_dev *pci,
3274 const struct pci_device_id *pci_id)
1da177e4 3275{
5aba4f8e 3276 static int dev;
a98f90fd
TI		 3277 struct snd_card *card;
3278 struct azx *chip;
5cb543db 3279 bool probe_now;
927fc866 3280 int err;
1da177e4 3281
5aba4f8e
TI		 3282 if (dev >= SNDRV_CARDS)
3283 return -ENODEV;
3284 if (!enable[dev]) {
3285 dev++;
3286 return -ENOENT;
3287 }
3288
e58de7ba
TI		 3289 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3290 if (err < 0) {
1da177e4 3291 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3292 return err;
1da177e4
LT		 3293 }
3294
4ea6fbc8
TI		 3295 snd_card_set_dev(card, &pci->dev);
3296
5aba4f8e 3297 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3298 if (err < 0)
3299 goto out_free;
421a1252 3300 card->private_data = chip;
5cb543db 3301 probe_now = !chip->disabled;
1da177e4 3302
4918cdab
TI		 3303#ifdef CONFIG_SND_HDA_PATCH_LOADER
3304 if (patch[dev] && *patch[dev]) {
3305 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3306 patch[dev]);
5cb543db
TI		 3307 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3308 &pci->dev, GFP_KERNEL, card,
3309 azx_firmware_cb);
4918cdab
TI		 3310 if (err < 0)
3311 goto out_free;
5cb543db 3312 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3313 }
3314#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3315
5cb543db 3316 if (probe_now) {
a82d51ed
TI		 3317 err = azx_probe_continue(chip);
3318 if (err < 0)
3319 goto out_free;
3320 }
3321
3322 pci_set_drvdata(pci, card);
3323
b8dfc462
ML		 3324 if (pci_dev_run_wake(pci))
3325 pm_runtime_put_noidle(&pci->dev);
3326
a82d51ed
TI		 3327 dev++;
3328 return 0;
3329
3330out_free:
3331 snd_card_free(card);
3332 return err;
3333}
3334
3335static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3336{
3337 int dev = chip->dev_index;
3338 int err;
3339
2dca0bba
JK		 3340#ifdef CONFIG_SND_HDA_INPUT_BEEP
3341 chip->beep_mode = beep_mode[dev];
3342#endif
3343
1da177e4 3344 /* create codec instances */
a1e21c90 3345 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3346 if (err < 0)
3347 goto out_free;
4ea6fbc8 3348#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3349 if (chip->fw) {
3350 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3351 chip->fw->data);
4ea6fbc8
TI		 3352 if (err < 0)
3353 goto out_free;
4918cdab
TI		 3354 release_firmware(chip->fw); /* no longer needed */
3355 chip->fw = NULL;
4ea6fbc8
TI		 3356 }
3357#endif
10e77dda 3358 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3359 err = azx_codec_configure(chip);
3360 if (err < 0)
3361 goto out_free;
3362 }
1da177e4
LT		 3363
3364 /* create PCM streams */
176d5335 3365 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3366 if (err < 0)
3367 goto out_free;
1da177e4
LT		 3368
3369 /* create mixer controls */
d01ce99f 3370 err = azx_mixer_create(chip);
41dda0fd
WF		 3371 if (err < 0)
3372 goto out_free;
1da177e4 3373
a82d51ed 3374 err = snd_card_register(chip->card);
41dda0fd
WF		 3375 if (err < 0)
3376 goto out_free;
1da177e4 3377
cb53c626
TI		 3378 chip->running = 1;
3379 power_down_all_codecs(chip);
0cbf0098 3380 azx_notifier_register(chip);
65fcd41d 3381 azx_add_card_list(chip);
1da177e4 3382
9121947d
TI		 3383 return 0;
3384
41dda0fd 3385out_free:
a82d51ed 3386 chip->init_failed = 1;
41dda0fd 3387 return err;
1da177e4
LT		 3388}
3389
3390static void __devexit azx_remove(struct pci_dev *pci)
3391{
9121947d 3392 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3393
3394 if (pci_dev_run_wake(pci))
3395 pm_runtime_get_noresume(&pci->dev);
3396
9121947d
TI		 3397 if (card)
3398 snd_card_free(card);
1da177e4
LT		 3399 pci_set_drvdata(pci, NULL);
3400}
3401
3402/* PCI IDs */
cebe41d4 3403static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3404 /* CPT */
9477c58e 3405 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26 3406 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3407 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
cea310e8 3408 /* PBG */
9477c58e 3409 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3411 AZX_DCAPS_BUFSIZE},
d2edeb7c 3412 /* Panther Point */
9477c58e 3413 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3415 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
8bc039a1
SH		 3416 /* Lynx Point */
3417 { PCI_DEVICE(0x8086, 0x8c20),
3418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3419 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
144dad99
JR		 3420 /* Lynx Point-LP */
3421 { PCI_DEVICE(0x8086, 0x9c20),
3422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3423 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3424 /* Lynx Point-LP */
3425 { PCI_DEVICE(0x8086, 0x9c21),
3426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3427 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
e926f2c8
WX		 3428 /* Haswell */
3429 { PCI_DEVICE(0x8086, 0x0c0c),
bdbe34de 3430 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
e926f2c8 3431 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
87218e9c 3432 /* SCH */
9477c58e 3433 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3434 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3435 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3436 { PCI_DEVICE(0x8086, 0x080a),
3437 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3438 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3439 /* ICH */
8b0bd226 3440 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3441 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3442 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3443 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3444 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3445 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3446 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3447 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3448 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3449 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3450 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3451 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3452 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3453 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3454 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3455 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3456 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3457 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3458 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3459 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3460 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3461 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3462 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3463 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3464 /* Generic Intel */
3465 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3466 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3467 .class_mask = 0xffffff,
2ae66c26 3468 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3469 /* ATI SB 450/600/700/800/900 */
3470 { PCI_DEVICE(0x1002, 0x437b),
3471 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3472 { PCI_DEVICE(0x1002, 0x4383),
3473 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3474 /* AMD Hudson */
3475 { PCI_DEVICE(0x1022, 0x780d),
3476 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3477 /* ATI HDMI */
9477c58e
TI		 3478 { PCI_DEVICE(0x1002, 0x793b),
3479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3480 { PCI_DEVICE(0x1002, 0x7919),
3481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3482 { PCI_DEVICE(0x1002, 0x960f),
3483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3484 { PCI_DEVICE(0x1002, 0x970f),
3485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3486 { PCI_DEVICE(0x1002, 0xaa00),
3487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3488 { PCI_DEVICE(0x1002, 0xaa08),
3489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3490 { PCI_DEVICE(0x1002, 0xaa10),
3491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3492 { PCI_DEVICE(0x1002, 0xaa18),
3493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3494 { PCI_DEVICE(0x1002, 0xaa20),
3495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3496 { PCI_DEVICE(0x1002, 0xaa28),
3497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3498 { PCI_DEVICE(0x1002, 0xaa30),
3499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3500 { PCI_DEVICE(0x1002, 0xaa38),
3501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3502 { PCI_DEVICE(0x1002, 0xaa40),
3503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3504 { PCI_DEVICE(0x1002, 0xaa48),
3505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3506 { PCI_DEVICE(0x1002, 0x9902),
3507 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3508 { PCI_DEVICE(0x1002, 0xaaa0),
3509 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3510 { PCI_DEVICE(0x1002, 0xaaa8),
3511 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3512 { PCI_DEVICE(0x1002, 0xaab0),
3513 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3514 /* VIA VT8251/VT8237A */
9477c58e
TI		 3515 { PCI_DEVICE(0x1106, 0x3288),
3516 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3517 /* VIA GFX VT7122/VX900 */
3518 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3519 /* VIA GFX VT6122/VX11 */
3520 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3521 /* SIS966 */
3522 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3523 /* ULI M5461 */
3524 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3525 /* NVIDIA MCP */
0c2fd1bf
TI		 3526 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3527 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3528 .class_mask = 0xffffff,
9477c58e 3529 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3530 /* Teradici */
9477c58e
TI		 3531 { PCI_DEVICE(0x6549, 0x1200),
3532 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3533 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3534 /* CTHDA chips */
3535 { PCI_DEVICE(0x1102, 0x0010),
3536 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3537 { PCI_DEVICE(0x1102, 0x0012),
3538 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3539#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3540 /* the following entry conflicts with snd-ctxfi driver,
3541 * as ctxfi driver mutates from HD-audio to native mode with
3542 * a special command sequence.
3543 */
4e01f54b
TI		 3544 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3545 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3546 .class_mask = 0xffffff,
9477c58e 3547 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3548 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3549#else
3550 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3551 { PCI_DEVICE(0x1102, 0x0009),
3552 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3553 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3554#endif
e35d4b11
OS		 3555 /* Vortex86MX */
3556 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3557 /* VMware HDAudio */
3558 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3559 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3560 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3561 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3562 .class_mask = 0xffffff,
9477c58e 3563 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3564 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3565 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3566 .class_mask = 0xffffff,
9477c58e 3567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3568 { 0, }
3569};
3570MODULE_DEVICE_TABLE(pci, azx_ids);
3571
3572/* pci_driver definition */
e9f66d9b 3573static struct pci_driver azx_driver = {
3733e424 3574 .name = KBUILD_MODNAME,
1da177e4
LT		 3575 .id_table = azx_ids,
3576 .probe = azx_probe,
3577 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3578 .driver = {
3579 .pm = AZX_PM_OPS,
3580 },
1da177e4
LT		 3581};
3582
e9f66d9b 3583module_pci_driver(azx_driver);
Linux kernel - Deliverables
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