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vga_switcheroo: Fix error without CONFIG_VGA_SWITCHEROO
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9
TI		 48#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
1da177e4
LT		 54#include <sound/core.h>
55#include <sound/initval.h>
9121947d 56#include <linux/vgaarb.h>
a82d51ed 57#include <linux/vga_switcheroo.h>
1da177e4
LT		 58#include "hda_codec.h"
59
60
5aba4f8e
TI		 61static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 63static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 64static char *model[SNDRV_CARDS];
65static int position_fix[SNDRV_CARDS];
5c0d7bc1 66static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 67static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 68static int probe_only[SNDRV_CARDS];
a67ff6a5 69static bool single_cmd;
71623855 70static int enable_msi = -1;
4ea6fbc8
TI		 71#ifdef CONFIG_SND_HDA_PATCH_LOADER
72static char *patch[SNDRV_CARDS];
73#endif
2dca0bba
JK		 74#ifdef CONFIG_SND_HDA_INPUT_BEEP
75static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
77#endif
1da177e4 78
5aba4f8e 79module_param_array(index, int, NULL, 0444);
1da177e4 80MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 81module_param_array(id, charp, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85module_param_array(model, charp, NULL, 0444);
1da177e4 86MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 87module_param_array(position_fix, int, NULL, 0444);
4cb36310 88MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 90module_param_array(bdl_pos_adj, int, NULL, 0644);
91MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 92module_param_array(probe_mask, int, NULL, 0444);
606ad75f 93MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 94module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 95MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 96module_param(single_cmd, bool, 0444);
d01ce99f
TI		 97MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
ac9ef6cf 99module_param(enable_msi, bint, 0444);
134a11f0 100MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 101#ifdef CONFIG_SND_HDA_PATCH_LOADER
102module_param_array(patch, charp, NULL, 0444);
103MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
104#endif
2dca0bba
JK		 105#ifdef CONFIG_SND_HDA_INPUT_BEEP
106module_param_array(beep_mode, int, NULL, 0444);
107MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
108 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
109#endif
606ad75f 110
dee1b66c 111#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 112static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113module_param(power_save, int, 0644);
114MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
1da177e4 116
dee1b66c
TI		 117/* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
119 * wake up.
120 */
a67ff6a5 121static bool power_save_controller = 1;
dee1b66c
TI		 122module_param(power_save_controller, bool, 0644);
123MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
124#endif
125
7bfe059e
TI		 126static int align_buffer_size = -1;
127module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 128MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
130
27fe48d9
TI		 131#ifdef CONFIG_X86
132static bool hda_snoop = true;
133module_param_named(snoop, hda_snoop, bool, 0444);
134MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135#define azx_snoop(chip) (chip)->snoop
136#else
137#define hda_snoop true
138#define azx_snoop(chip) true
139#endif
140
141
1da177e4
LT		 142MODULE_LICENSE("GPL");
143MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
144 "{Intel, ICH6M},"
2f1b3818 145 "{Intel, ICH7},"
f5d40b30 146 "{Intel, ESB2},"
d2981393 147 "{Intel, ICH8},"
f9cc8a8b 148 "{Intel, ICH9},"
c34f5a04 149 "{Intel, ICH10},"
b29c2360 150 "{Intel, PCH},"
d2f2fcd2 151 "{Intel, CPT},"
d2edeb7c 152 "{Intel, PPT},"
8bc039a1 153 "{Intel, LPT},"
cea310e8 154 "{Intel, PBG},"
4979bca9 155 "{Intel, SCH},"
fc20a562 156 "{ATI, SB450},"
89be83f8 157 "{ATI, SB600},"
778b6e1b 158 "{ATI, RS600},"
5b15c95f 159 "{ATI, RS690},"
e6db1119
WL		 160 "{ATI, RS780},"
161 "{ATI, R600},"
2797f724
HRK		 162 "{ATI, RV630},"
163 "{ATI, RV610},"
27da1834
WL		 164 "{ATI, RV670},"
165 "{ATI, RV635},"
166 "{ATI, RV620},"
167 "{ATI, RV770},"
fc20a562 168 "{VIA, VT8251},"
47672310 169 "{VIA, VT8237A},"
07e4ca50
TI		 170 "{SiS, SIS966},"
171 "{ULI, M5461}}");
1da177e4
LT		 172MODULE_DESCRIPTION("Intel HDA driver");
173
4abc1cc2
TI		 174#ifdef CONFIG_SND_VERBOSE_PRINTK
175#define SFX /* nop */
176#else
1da177e4 177#define SFX "hda-intel: "
4abc1cc2 178#endif
cb53c626 179
a82d51ed
TI		 180#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
181#ifdef CONFIG_SND_HDA_CODEC_HDMI
182#define SUPPORT_VGA_SWITCHEROO
183#endif
184#endif
185
186
1da177e4
LT		 187/*
188 * registers
189 */
190#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 191#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
192#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
193#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
194#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
195#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 196#define ICH6_REG_VMIN 0x02
197#define ICH6_REG_VMAJ 0x03
198#define ICH6_REG_OUTPAY 0x04
199#define ICH6_REG_INPAY 0x06
200#define ICH6_REG_GCTL 0x08
8a933ece 201#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 202#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
203#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 204#define ICH6_REG_WAKEEN 0x0c
205#define ICH6_REG_STATESTS 0x0e
206#define ICH6_REG_GSTS 0x10
b21fadb9 207#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 208#define ICH6_REG_INTCTL 0x20
209#define ICH6_REG_INTSTS 0x24
e5463720 210#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 211#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
212#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 213#define ICH6_REG_CORBLBASE 0x40
214#define ICH6_REG_CORBUBASE 0x44
215#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 216#define ICH6_REG_CORBRP 0x4a
217#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 218#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 219#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
220#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 221#define ICH6_REG_CORBSTS 0x4d
b21fadb9 222#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 223#define ICH6_REG_CORBSIZE 0x4e
224
225#define ICH6_REG_RIRBLBASE 0x50
226#define ICH6_REG_RIRBUBASE 0x54
227#define ICH6_REG_RIRBWP 0x58
b21fadb9 228#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 229#define ICH6_REG_RINTCNT 0x5a
230#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 231#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
232#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
233#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 234#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 235#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
236#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 237#define ICH6_REG_RIRBSIZE 0x5e
238
239#define ICH6_REG_IC 0x60
240#define ICH6_REG_IR 0x64
241#define ICH6_REG_IRS 0x68
242#define ICH6_IRS_VALID (1<<1)
243#define ICH6_IRS_BUSY (1<<0)
244
245#define ICH6_REG_DPLBASE 0x70
246#define ICH6_REG_DPUBASE 0x74
247#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
248
249/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
250enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
251
252/* stream register offsets from stream base */
253#define ICH6_REG_SD_CTL 0x00
254#define ICH6_REG_SD_STS 0x03
255#define ICH6_REG_SD_LPIB 0x04
256#define ICH6_REG_SD_CBL 0x08
257#define ICH6_REG_SD_LVI 0x0c
258#define ICH6_REG_SD_FIFOW 0x0e
259#define ICH6_REG_SD_FIFOSIZE 0x10
260#define ICH6_REG_SD_FORMAT 0x12
261#define ICH6_REG_SD_BDLPL 0x18
262#define ICH6_REG_SD_BDLPU 0x1c
263
264/* PCI space */
265#define ICH6_PCIREG_TCSEL 0x44
266
267/*
268 * other constants
269 */
270
271/* max number of SDs */
07e4ca50 272/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 273#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 274#define ICH6_NUM_PLAYBACK 4
275
276/* ULI has 6 playback and 5 capture */
07e4ca50 277#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 278#define ULI_NUM_PLAYBACK 6
279
778b6e1b 280/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 281#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 282#define ATIHDMI_NUM_PLAYBACK 1
283
f269002e
KY		 284/* TERA has 4 playback and 3 capture */
285#define TERA_NUM_CAPTURE 3
286#define TERA_NUM_PLAYBACK 4
287
07e4ca50
TI		 288/* this number is statically defined for simplicity */
289#define MAX_AZX_DEV 16
290
1da177e4 291/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 292#define BDL_SIZE 4096
293#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
294#define AZX_MAX_FRAG 32
1da177e4
LT		 295/* max buffer size - no h/w limit, you can increase as you like */
296#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 297
298/* RIRB int mask: overrun[2], response[0] */
299#define RIRB_INT_RESPONSE 0x01
300#define RIRB_INT_OVERRUN 0x04
301#define RIRB_INT_MASK 0x05
302
2f5983f2 303/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 304#define AZX_MAX_CODECS 8
305#define AZX_DEFAULT_CODECS 4
deadff16 306#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 307
308/* SD_CTL bits */
309#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
310#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 311#define SD_CTL_STRIPE (3 << 16) /* stripe control */
312#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
313#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 314#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
315#define SD_CTL_STREAM_TAG_SHIFT 20
316
317/* SD_CTL and SD_STS */
318#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
319#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
320#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 321#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
322 SD_INT_COMPLETE)
1da177e4
LT		 323
324/* SD_STS */
325#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
326
327/* INTCTL and INTSTS */
d01ce99f
TI		 328#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
329#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
330#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 331
1da177e4
LT		 332/* below are so far hardcoded - should read registers in future */
333#define ICH6_MAX_CORB_ENTRIES 256
334#define ICH6_MAX_RIRB_ENTRIES 256
335
c74db86b
TI		 336/* position fix mode */
337enum {
0be3b5d3 338 POS_FIX_AUTO,
d2e1c973 339 POS_FIX_LPIB,
0be3b5d3 340 POS_FIX_POSBUF,
4cb36310 341 POS_FIX_VIACOMBO,
a6f2fd55 342 POS_FIX_COMBO,
c74db86b 343};
1da177e4 344
f5d40b30 345/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 346#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
347#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
348
da3fca21
V		 349/* Defines for Nvidia HDA support */
350#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
351#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 352#define NVIDIA_HDA_ISTRM_COH 0x4d
353#define NVIDIA_HDA_OSTRM_COH 0x4c
354#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 355
90a5ad52
TI		 356/* Defines for Intel SCH HDA snoop control */
357#define INTEL_SCH_HDA_DEVC 0x78
358#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
359
0e153474
JC		 360/* Define IN stream 0 FIFO size offset in VIA controller */
361#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
362/* Define VIA HD Audio Device ID*/
363#define VIA_HDAC_DEVICE_ID 0x3288
364
c4da29ca
YL		 365/* HD Audio class code */
366#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 367
1da177e4
LT		 368/*
369 */
370
a98f90fd 371struct azx_dev {
4ce107b9 372 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 373 u32 *posbuf; /* position buffer pointer */
1da177e4 374
d01ce99f 375 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 376 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 377 unsigned int frags; /* number for period in the play buffer */
378 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 379 unsigned long start_wallclk; /* start + minimum wallclk */
380 unsigned long period_wallclk; /* wallclk for period */
1da177e4 381
d01ce99f 382 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 383
d01ce99f 384 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 385
386 /* pcm support */
d01ce99f
TI		 387 struct snd_pcm_substream *substream; /* assigned substream,
388 * set in PCM open
389 */
390 unsigned int format_val; /* format value to be set in the
391 * controller and the codec
392 */
1da177e4
LT		 393 unsigned char stream_tag; /* assigned stream */
394 unsigned char index; /* stream index */
d5cf9911 395 int assigned_key; /* last device# key assigned to */
1da177e4 396
927fc866
PM		 397 unsigned int opened :1;
398 unsigned int running :1;
675f25d4 399 unsigned int irq_pending :1;
0e153474
JC		 400 /*
401 * For VIA:
402 * A flag to ensure DMA position is 0
403 * when link position is not greater than FIFO size
404 */
405 unsigned int insufficient :1;
27fe48d9 406 unsigned int wc_marked:1;
1da177e4
LT		 407};
408
409/* CORB/RIRB */
a98f90fd 410struct azx_rb {
1da177e4
LT		 411 u32 *buf; /* CORB/RIRB buffer
412 * Each CORB entry is 4byte, RIRB is 8byte
413 */
414 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
415 /* for RIRB */
416 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 417 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
418 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 419};
420
01b65bfb
TI		 421struct azx_pcm {
422 struct azx *chip;
423 struct snd_pcm *pcm;
424 struct hda_codec *codec;
425 struct hda_pcm_stream *hinfo[2];
426 struct list_head list;
427};
428
a98f90fd
TI		 429struct azx {
430 struct snd_card *card;
1da177e4 431 struct pci_dev *pci;
555e219f 432 int dev_index;
1da177e4 433
07e4ca50
TI		 434 /* chip type specific */
435 int driver_type;
9477c58e 436 unsigned int driver_caps;
07e4ca50
TI		 437 int playback_streams;
438 int playback_index_offset;
439 int capture_streams;
440 int capture_index_offset;
441 int num_streams;
442
1da177e4
LT		 443 /* pci resources */
444 unsigned long addr;
445 void __iomem *remap_addr;
446 int irq;
447
448 /* locks */
449 spinlock_t reg_lock;
62932df8 450 struct mutex open_mutex;
1da177e4 451
07e4ca50 452 /* streams (x num_streams) */
a98f90fd 453 struct azx_dev *azx_dev;
1da177e4
LT		 454
455 /* PCM */
01b65bfb 456 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 457
458 /* HD codec */
459 unsigned short codec_mask;
f1eaaeec 460 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 461 struct hda_bus *bus;
2dca0bba 462 unsigned int beep_mode;
1da177e4
LT		 463
464 /* CORB/RIRB */
a98f90fd
TI		 465 struct azx_rb corb;
466 struct azx_rb rirb;
1da177e4 467
4ce107b9 468 /* CORB/RIRB and position buffers */
1da177e4
LT		 469 struct snd_dma_buffer rb;
470 struct snd_dma_buffer posbuf;
c74db86b
TI		 471
472 /* flags */
beaffc39 473 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 474 int poll_count;
cb53c626 475 unsigned int running :1;
927fc866
PM		 476 unsigned int initialized :1;
477 unsigned int single_cmd :1;
478 unsigned int polling_mode :1;
68e7fffc 479 unsigned int msi :1;
a6a950a8 480 unsigned int irq_pending_warned :1;
6ce4a3bc 481 unsigned int probing :1; /* codec probing phase */
27fe48d9 482 unsigned int snoop:1;
52409aa6 483 unsigned int align_buffer_size:1;
a82d51ed
TI		 484 unsigned int region_requested:1;
485
486 /* VGA-switcheroo setup */
487 unsigned int use_vga_switcheroo:1;
488 unsigned int init_failed:1; /* delayed init failed */
489 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 490
491 /* for debugging */
feb27340 492 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 493
494 /* for pending irqs */
495 struct work_struct irq_pending_work;
0cbf0098
TI		 496
497 /* reboot notifier (for mysterious hangup problem at power-down) */
498 struct notifier_block reboot_notifier;
1da177e4
LT		 499};
500
07e4ca50
TI		 501/* driver types */
502enum {
503 AZX_DRIVER_ICH,
32679f95 504 AZX_DRIVER_PCH,
4979bca9 505 AZX_DRIVER_SCH,
07e4ca50 506 AZX_DRIVER_ATI,
778b6e1b 507 AZX_DRIVER_ATIHDMI,
1815b34a 508 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 509 AZX_DRIVER_VIA,
510 AZX_DRIVER_SIS,
511 AZX_DRIVER_ULI,
da3fca21 512 AZX_DRIVER_NVIDIA,
f269002e 513 AZX_DRIVER_TERA,
14d34f16 514 AZX_DRIVER_CTX,
5ae763b1 515 AZX_DRIVER_CTHDA,
c4da29ca 516 AZX_DRIVER_GENERIC,
2f5983f2 517 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 518};
519
9477c58e
TI		 520/* driver quirks (capabilities) */
521/* bits 0-7 are used for indicating driver type */
522#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
523#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
524#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
525#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
526#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
527#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
528#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
529#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
530#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
531#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
532#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
533#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 534#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 535#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 536#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 537#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
9477c58e
TI		 538
539/* quirks for ATI SB / AMD Hudson */
540#define AZX_DCAPS_PRESET_ATI_SB \
541 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
542 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
543
544/* quirks for ATI/AMD HDMI */
545#define AZX_DCAPS_PRESET_ATI_HDMI \
546 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
547
548/* quirks for Nvidia */
549#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 550 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
551 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 552
5ae763b1
TI		 553#define AZX_DCAPS_PRESET_CTHDA \
554 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
555
a82d51ed
TI		 556/*
557 * VGA-switcher support
558 */
559#ifdef SUPPORT_VGA_SWITCHEROO
560#define DELAYED_INIT_MARK
561#define DELAYED_INITDATA_MARK
562#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
563#else
564#define DELAYED_INIT_MARK __devinit
565#define DELAYED_INITDATA_MARK __devinitdata
566#define use_vga_switcheroo(chip) 0
567#endif
568
569static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 570 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 571 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 572 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 573 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 574 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 575 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 576 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
577 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 578 [AZX_DRIVER_ULI] = "HDA ULI M5461",
579 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 580 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 581 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 582 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 583 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 584};
585
1da177e4
LT		 586/*
587 * macros for easy use
588 */
589#define azx_writel(chip,reg,value) \
590 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
591#define azx_readl(chip,reg) \
592 readl((chip)->remap_addr + ICH6_REG_##reg)
593#define azx_writew(chip,reg,value) \
594 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
595#define azx_readw(chip,reg) \
596 readw((chip)->remap_addr + ICH6_REG_##reg)
597#define azx_writeb(chip,reg,value) \
598 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
599#define azx_readb(chip,reg) \
600 readb((chip)->remap_addr + ICH6_REG_##reg)
601
602#define azx_sd_writel(dev,reg,value) \
603 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
604#define azx_sd_readl(dev,reg) \
605 readl((dev)->sd_addr + ICH6_REG_##reg)
606#define azx_sd_writew(dev,reg,value) \
607 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
608#define azx_sd_readw(dev,reg) \
609 readw((dev)->sd_addr + ICH6_REG_##reg)
610#define azx_sd_writeb(dev,reg,value) \
611 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
612#define azx_sd_readb(dev,reg) \
613 readb((dev)->sd_addr + ICH6_REG_##reg)
614
615/* for pcm support */
a98f90fd 616#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 617
27fe48d9
TI		 618#ifdef CONFIG_X86
619static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
620{
621 if (azx_snoop(chip))
622 return;
623 if (addr && size) {
624 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
625 if (on)
626 set_memory_wc((unsigned long)addr, pages);
627 else
628 set_memory_wb((unsigned long)addr, pages);
629 }
630}
631
632static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
633 bool on)
634{
635 __mark_pages_wc(chip, buf->area, buf->bytes, on);
636}
637static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
638 struct snd_pcm_runtime *runtime, bool on)
639{
640 if (azx_dev->wc_marked != on) {
641 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
642 azx_dev->wc_marked = on;
643 }
644}
645#else
646/* NOP for other archs */
647static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
648 bool on)
649{
650}
651static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
652 struct snd_pcm_runtime *runtime, bool on)
653{
654}
655#endif
656
68e7fffc 657static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 658static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 659/*
660 * Interface for HD codec
661 */
662
1da177e4
LT		 663/*
664 * CORB / RIRB interface
665 */
a98f90fd 666static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 667{
668 int err;
669
670 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 671 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
672 snd_dma_pci_data(chip->pci),
1da177e4
LT		 673 PAGE_SIZE, &chip->rb);
674 if (err < 0) {
675 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
676 return err;
677 }
27fe48d9 678 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 679 return 0;
680}
681
a98f90fd 682static void azx_init_cmd_io(struct azx *chip)
1da177e4 683{
cdb1fbf2 684 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 685 /* CORB set up */
686 chip->corb.addr = chip->rb.addr;
687 chip->corb.buf = (u32 *)chip->rb.area;
688 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 689 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 690
07e4ca50
TI		 691 /* set the corb size to 256 entries (ULI requires explicitly) */
692 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 693 /* set the corb write pointer to 0 */
694 azx_writew(chip, CORBWP, 0);
695 /* reset the corb hw read pointer */
b21fadb9 696 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 697 /* enable corb dma */
b21fadb9 698 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 699
700 /* RIRB set up */
701 chip->rirb.addr = chip->rb.addr + 2048;
702 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 703 chip->rirb.wp = chip->rirb.rp = 0;
704 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 705 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 706 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 707
07e4ca50
TI		 708 /* set the rirb size to 256 entries (ULI requires explicitly) */
709 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 710 /* reset the rirb hw write pointer */
b21fadb9 711 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 712 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 713 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 714 azx_writew(chip, RINTCNT, 0xc0);
715 else
716 azx_writew(chip, RINTCNT, 1);
1da177e4 717 /* enable rirb dma and response irq */
1da177e4 718 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 719 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 720}
721
a98f90fd 722static void azx_free_cmd_io(struct azx *chip)
1da177e4 723{
cdb1fbf2 724 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 725 /* disable ringbuffer DMAs */
726 azx_writeb(chip, RIRBCTL, 0);
727 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 728 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 729}
730
deadff16
WF		 731static unsigned int azx_command_addr(u32 cmd)
732{
733 unsigned int addr = cmd >> 28;
734
735 if (addr >= AZX_MAX_CODECS) {
736 snd_BUG();
737 addr = 0;
738 }
739
740 return addr;
741}
742
743static unsigned int azx_response_addr(u32 res)
744{
745 unsigned int addr = res & 0xf;
746
747 if (addr >= AZX_MAX_CODECS) {
748 snd_BUG();
749 addr = 0;
750 }
751
752 return addr;
1da177e4
LT		 753}
754
755/* send a command */
33fa35ed 756static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 757{
33fa35ed 758 struct azx *chip = bus->private_data;
deadff16 759 unsigned int addr = azx_command_addr(val);
1da177e4 760 unsigned int wp;
1da177e4 761
c32649fe
WF		 762 spin_lock_irq(&chip->reg_lock);
763
1da177e4
LT		 764 /* add command to corb */
765 wp = azx_readb(chip, CORBWP);
766 wp++;
767 wp %= ICH6_MAX_CORB_ENTRIES;
768
deadff16 769 chip->rirb.cmds[addr]++;
1da177e4
LT		 770 chip->corb.buf[wp] = cpu_to_le32(val);
771 azx_writel(chip, CORBWP, wp);
c32649fe 772
1da177e4
LT		 773 spin_unlock_irq(&chip->reg_lock);
774
775 return 0;
776}
777
778#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
779
780/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 781static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 782{
783 unsigned int rp, wp;
deadff16 784 unsigned int addr;
1da177e4
LT		 785 u32 res, res_ex;
786
787 wp = azx_readb(chip, RIRBWP);
788 if (wp == chip->rirb.wp)
789 return;
790 chip->rirb.wp = wp;
deadff16 791
1da177e4
LT		 792 while (chip->rirb.rp != wp) {
793 chip->rirb.rp++;
794 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
795
796 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
797 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
798 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 799 addr = azx_response_addr(res_ex);
1da177e4
LT		 800 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
801 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 802 else if (chip->rirb.cmds[addr]) {
803 chip->rirb.res[addr] = res;
2add9b92 804 smp_wmb();
deadff16 805 chip->rirb.cmds[addr]--;
e310bb06
WF		 806 } else
807 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
808 "last cmd=%#08x\n",
809 res, res_ex,
810 chip->last_cmd[addr]);
1da177e4
LT		 811 }
812}
813
814/* receive a response */
deadff16
WF		 815static unsigned int azx_rirb_get_response(struct hda_bus *bus,
816 unsigned int addr)
1da177e4 817{
33fa35ed 818 struct azx *chip = bus->private_data;
5c79b1f8 819 unsigned long timeout;
32cf4023 820 unsigned long loopcounter;
1eb6dc7d 821 int do_poll = 0;
1da177e4 822
5c79b1f8
TI		 823 again:
824 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 825
826 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 827 if (chip->polling_mode || do_poll) {
e96224ae
TI		 828 spin_lock_irq(&chip->reg_lock);
829 azx_update_rirb(chip);
830 spin_unlock_irq(&chip->reg_lock);
831 }
deadff16 832 if (!chip->rirb.cmds[addr]) {
2add9b92 833 smp_rmb();
b613291f 834 bus->rirb_error = 0;
1eb6dc7d
ML		 835
836 if (!do_poll)
837 chip->poll_count = 0;
deadff16 838 return chip->rirb.res[addr]; /* the last value */
2add9b92 839 }
28a0d9df
TI		 840 if (time_after(jiffies, timeout))
841 break;
32cf4023 842 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 843 msleep(2); /* temporary workaround */
844 else {
845 udelay(10);
846 cond_resched();
847 }
28a0d9df 848 }
5c79b1f8 849
1eb6dc7d
ML		 850 if (!chip->polling_mode && chip->poll_count < 2) {
851 snd_printdd(SFX "azx_get_response timeout, "
852 "polling the codec once: last cmd=0x%08x\n",
853 chip->last_cmd[addr]);
854 do_poll = 1;
855 chip->poll_count++;
856 goto again;
857 }
858
859
23c4a881
TI		 860 if (!chip->polling_mode) {
861 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
862 "switching to polling mode: last cmd=0x%08x\n",
863 chip->last_cmd[addr]);
864 chip->polling_mode = 1;
865 goto again;
866 }
867
68e7fffc 868 if (chip->msi) {
4abc1cc2 869 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 870 "disabling MSI: last cmd=0x%08x\n",
871 chip->last_cmd[addr]);
68e7fffc
TI		 872 free_irq(chip->irq, chip);
873 chip->irq = -1;
874 pci_disable_msi(chip->pci);
875 chip->msi = 0;
b613291f
TI		 876 if (azx_acquire_irq(chip, 1) < 0) {
877 bus->rirb_error = 1;
68e7fffc 878 return -1;
b613291f 879 }
68e7fffc
TI		 880 goto again;
881 }
882
6ce4a3bc
TI		 883 if (chip->probing) {
884 /* If this critical timeout happens during the codec probing
885 * phase, this is likely an access to a non-existing codec
886 * slot. Better to return an error and reset the system.
887 */
888 return -1;
889 }
890
8dd78330
TI		 891 /* a fatal communication error; need either to reset or to fallback
892 * to the single_cmd mode
893 */
b613291f 894 bus->rirb_error = 1;
b20f3b83 895 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 896 bus->response_reset = 1;
897 return -1; /* give a chance to retry */
898 }
899
900 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
901 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 902 chip->last_cmd[addr]);
8dd78330
TI		 903 chip->single_cmd = 1;
904 bus->response_reset = 0;
1a696978 905 /* release CORB/RIRB */
4fcd3920 906 azx_free_cmd_io(chip);
1a696978
TI		 907 /* disable unsolicited responses */
908 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 909 return -1;
1da177e4
LT		 910}
911
1da177e4
LT		 912/*
913 * Use the single immediate command instead of CORB/RIRB for simplicity
914 *
915 * Note: according to Intel, this is not preferred use. The command was
916 * intended for the BIOS only, and may get confused with unsolicited
917 * responses. So, we shouldn't use it for normal operation from the
918 * driver.
919 * I left the codes, however, for debugging/testing purposes.
920 */
921
b05a7d4f 922/* receive a response */
deadff16 923static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 924{
925 int timeout = 50;
926
927 while (timeout--) {
928 /* check IRV busy bit */
929 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
930 /* reuse rirb.res as the response return value */
deadff16 931 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 932 return 0;
933 }
934 udelay(1);
935 }
936 if (printk_ratelimit())
937 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
938 azx_readw(chip, IRS));
deadff16 939 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 940 return -EIO;
941}
942
1da177e4 943/* send a command */
33fa35ed 944static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 945{
33fa35ed 946 struct azx *chip = bus->private_data;
deadff16 947 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 948 int timeout = 50;
949
8dd78330 950 bus->rirb_error = 0;
1da177e4
LT		 951 while (timeout--) {
952 /* check ICB busy bit */
d01ce99f 953 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 954 /* Clear IRV valid bit */
d01ce99f
TI		 955 azx_writew(chip, IRS, azx_readw(chip, IRS) |
956 ICH6_IRS_VALID);
1da177e4 957 azx_writel(chip, IC, val);
d01ce99f
TI		 958 azx_writew(chip, IRS, azx_readw(chip, IRS) |
959 ICH6_IRS_BUSY);
deadff16 960 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 961 }
962 udelay(1);
963 }
1cfd52bc
MB		 964 if (printk_ratelimit())
965 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
966 azx_readw(chip, IRS), val);
1da177e4
LT		 967 return -EIO;
968}
969
970/* receive a response */
deadff16
WF		 971static unsigned int azx_single_get_response(struct hda_bus *bus,
972 unsigned int addr)
1da177e4 973{
33fa35ed 974 struct azx *chip = bus->private_data;
deadff16 975 return chip->rirb.res[addr];
1da177e4
LT		 976}
977
111d3af5
TI		 978/*
979 * The below are the main callbacks from hda_codec.
980 *
981 * They are just the skeleton to call sub-callbacks according to the
982 * current setting of chip->single_cmd.
983 */
984
985/* send a command */
33fa35ed 986static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 987{
33fa35ed 988 struct azx *chip = bus->private_data;
43bbb6cc 989
a82d51ed
TI		 990 if (chip->disabled)
991 return 0;
feb27340 992 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 993 if (chip->single_cmd)
33fa35ed 994 return azx_single_send_cmd(bus, val);
111d3af5 995 else
33fa35ed 996 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 997}
998
999/* get a response */
deadff16
WF		 1000static unsigned int azx_get_response(struct hda_bus *bus,
1001 unsigned int addr)
111d3af5 1002{
33fa35ed 1003 struct azx *chip = bus->private_data;
a82d51ed
TI		 1004 if (chip->disabled)
1005 return 0;
111d3af5 1006 if (chip->single_cmd)
deadff16 1007 return azx_single_get_response(bus, addr);
111d3af5 1008 else
deadff16 1009 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1010}
1011
cb53c626 1012#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 1013static void azx_power_notify(struct hda_bus *bus);
cb53c626 1014#endif
111d3af5 1015
1da177e4 1016/* reset codec link */
cd508fe5 1017static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1018{
1019 int count;
1020
cd508fe5
JK		 1021 if (!full_reset)
1022 goto __skip;
1023
e8a7f136
DT		 1024 /* clear STATESTS */
1025 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1026
1da177e4
LT		 1027 /* reset controller */
1028 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1029
1030 count = 50;
1031 while (azx_readb(chip, GCTL) && --count)
1032 msleep(1);
1033
1034 /* delay for >= 100us for codec PLL to settle per spec
1035 * Rev 0.9 section 5.5.1
1036 */
1037 msleep(1);
1038
1039 /* Bring controller out of reset */
1040 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1041
1042 count = 50;
927fc866 1043 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1044 msleep(1);
1045
927fc866 1046 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1047 msleep(1);
1048
cd508fe5 1049 __skip:
1da177e4 1050 /* check to see if controller is ready */
927fc866 1051 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1052 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1053 return -EBUSY;
1054 }
1055
41e2fce4 1056 /* Accept unsolicited responses */
1a696978
TI		 1057 if (!chip->single_cmd)
1058 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1059 ICH6_GCTL_UNSOL);
41e2fce4 1060
1da177e4 1061 /* detect codecs */
927fc866 1062 if (!chip->codec_mask) {
1da177e4 1063 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1064 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1065 }
1066
1067 return 0;
1068}
1069
1070
1071/*
1072 * Lowlevel interface
1073 */
1074
1075/* enable interrupts */
a98f90fd 1076static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1077{
1078 /* enable controller CIE and GIE */
1079 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1080 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1081}
1082
1083/* disable interrupts */
a98f90fd 1084static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1085{
1086 int i;
1087
1088 /* disable interrupts in stream descriptor */
07e4ca50 1089 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1090 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1091 azx_sd_writeb(azx_dev, SD_CTL,
1092 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1093 }
1094
1095 /* disable SIE for all streams */
1096 azx_writeb(chip, INTCTL, 0);
1097
1098 /* disable controller CIE and GIE */
1099 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1100 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1101}
1102
1103/* clear interrupts */
a98f90fd 1104static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1105{
1106 int i;
1107
1108 /* clear stream status */
07e4ca50 1109 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1110 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1111 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1112 }
1113
1114 /* clear STATESTS */
1115 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1116
1117 /* clear rirb status */
1118 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1119
1120 /* clear int status */
1121 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1122}
1123
1124/* start a stream */
a98f90fd 1125static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1126{
0e153474
JC		 1127 /*
1128 * Before stream start, initialize parameter
1129 */
1130 azx_dev->insufficient = 1;
1131
1da177e4 1132 /* enable SIE */
ccc5df05
WN		 1133 azx_writel(chip, INTCTL,
1134 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1135 /* set DMA start and interrupt mask */
1136 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1137 SD_CTL_DMA_START | SD_INT_MASK);
1138}
1139
1dddab40
TI		 1140/* stop DMA */
1141static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1142{
1da177e4
LT		 1143 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1144 ~(SD_CTL_DMA_START | SD_INT_MASK));
1145 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1146}
1147
1148/* stop a stream */
1149static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1150{
1151 azx_stream_clear(chip, azx_dev);
1da177e4 1152 /* disable SIE */
ccc5df05
WN		 1153 azx_writel(chip, INTCTL,
1154 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1155}
1156
1157
1158/*
cb53c626 1159 * reset and start the controller registers
1da177e4 1160 */
cd508fe5 1161static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1162{
cb53c626
TI		 1163 if (chip->initialized)
1164 return;
1da177e4
LT		 1165
1166 /* reset controller */
cd508fe5 1167 azx_reset(chip, full_reset);
1da177e4
LT		 1168
1169 /* initialize interrupts */
1170 azx_int_clear(chip);
1171 azx_int_enable(chip);
1172
1173 /* initialize the codec command I/O */
1a696978
TI		 1174 if (!chip->single_cmd)
1175 azx_init_cmd_io(chip);
1da177e4 1176
0be3b5d3
TI		 1177 /* program the position buffer */
1178 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1179 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1180
cb53c626
TI		 1181 chip->initialized = 1;
1182}
1183
1184/*
1185 * initialize the PCI registers
1186 */
1187/* update bits in a PCI register byte */
1188static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1189 unsigned char mask, unsigned char val)
1190{
1191 unsigned char data;
1192
1193 pci_read_config_byte(pci, reg, &data);
1194 data &= ~mask;
1195 data |= (val & mask);
1196 pci_write_config_byte(pci, reg, data);
1197}
1198
1199static void azx_init_pci(struct azx *chip)
1200{
1201 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1202 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1203 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1204 * codecs.
1205 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1206 */
46f2cc80 1207 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1208 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1209 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1210 }
cb53c626 1211
9477c58e
TI		 1212 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1213 * we need to enable snoop.
1214 */
1215 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1216 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1217 update_pci_byte(chip->pci,
27fe48d9
TI		 1218 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1219 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1220 }
1221
1222 /* For NVIDIA HDA, enable snoop */
1223 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1224 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1225 update_pci_byte(chip->pci,
1226 NVIDIA_HDA_TRANSREG_ADDR,
1227 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1228 update_pci_byte(chip->pci,
1229 NVIDIA_HDA_ISTRM_COH,
1230 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1231 update_pci_byte(chip->pci,
1232 NVIDIA_HDA_OSTRM_COH,
1233 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1234 }
1235
1236 /* Enable SCH/PCH snoop if needed */
1237 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1238 unsigned short snoop;
90a5ad52 1239 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1240 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1241 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1242 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1243 if (!azx_snoop(chip))
1244 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1245 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1246 pci_read_config_word(chip->pci,
1247 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1248 }
27fe48d9
TI		 1249 snd_printdd(SFX "SCH snoop: %s\n",
1250 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1251 ? "Disabled" : "Enabled");
da3fca21 1252 }
1da177e4
LT		 1253}
1254
1255
9ad593f6
TI		 1256static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1257
1da177e4
LT		 1258/*
1259 * interrupt handler
1260 */
7d12e780 1261static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1262{
a98f90fd
TI		 1263 struct azx *chip = dev_id;
1264 struct azx_dev *azx_dev;
1da177e4 1265 u32 status;
9ef04066 1266 u8 sd_status;
fa00e046 1267 int i, ok;
1da177e4
LT		 1268
1269 spin_lock(&chip->reg_lock);
1270
60911062
DC		 1271 if (chip->disabled) {
1272 spin_unlock(&chip->reg_lock);
a82d51ed 1273 return IRQ_NONE;
60911062 1274 }
a82d51ed 1275
1da177e4
LT		 1276 status = azx_readl(chip, INTSTS);
1277 if (status == 0) {
1278 spin_unlock(&chip->reg_lock);
1279 return IRQ_NONE;
1280 }
1281
07e4ca50 1282 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1283 azx_dev = &chip->azx_dev[i];
1284 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1285 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1286 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1287 if (!azx_dev->substream || !azx_dev->running ||
1288 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1289 continue;
1290 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1291 ok = azx_position_ok(chip, azx_dev);
1292 if (ok == 1) {
9ad593f6 1293 azx_dev->irq_pending = 0;
1da177e4
LT		 1294 spin_unlock(&chip->reg_lock);
1295 snd_pcm_period_elapsed(azx_dev->substream);
1296 spin_lock(&chip->reg_lock);
fa00e046 1297 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1298 /* bogus IRQ, process it later */
1299 azx_dev->irq_pending = 1;
6acaed38
TI		 1300 queue_work(chip->bus->workq,
1301 &chip->irq_pending_work);
1da177e4
LT		 1302 }
1303 }
1304 }
1305
1306 /* clear rirb int */
1307 status = azx_readb(chip, RIRBSTS);
1308 if (status & RIRB_INT_MASK) {
14d34f16 1309 if (status & RIRB_INT_RESPONSE) {
9477c58e 1310 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1311 udelay(80);
1da177e4 1312 azx_update_rirb(chip);
14d34f16 1313 }
1da177e4
LT		 1314 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1315 }
1316
1317#if 0
1318 /* clear state status int */
1319 if (azx_readb(chip, STATESTS) & 0x04)
1320 azx_writeb(chip, STATESTS, 0x04);
1321#endif
1322 spin_unlock(&chip->reg_lock);
1323
1324 return IRQ_HANDLED;
1325}
1326
1327
675f25d4
TI		 1328/*
1329 * set up a BDL entry
1330 */
5ae763b1
TI		 1331static int setup_bdle(struct azx *chip,
1332 struct snd_pcm_substream *substream,
675f25d4
TI		 1333 struct azx_dev *azx_dev, u32 **bdlp,
1334 int ofs, int size, int with_ioc)
1335{
675f25d4
TI		 1336 u32 *bdl = *bdlp;
1337
1338 while (size > 0) {
1339 dma_addr_t addr;
1340 int chunk;
1341
1342 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1343 return -EINVAL;
1344
77a23f26 1345 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1346 /* program the address field of the BDL entry */
1347 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1348 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1349 /* program the size field of the BDL entry */
fc4abee8 1350 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1351 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1352 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1353 u32 remain = 0x1000 - (ofs & 0xfff);
1354 if (chunk > remain)
1355 chunk = remain;
1356 }
675f25d4
TI		 1357 bdl[2] = cpu_to_le32(chunk);
1358 /* program the IOC to enable interrupt
1359 * only when the whole fragment is processed
1360 */
1361 size -= chunk;
1362 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1363 bdl += 4;
1364 azx_dev->frags++;
1365 ofs += chunk;
1366 }
1367 *bdlp = bdl;
1368 return ofs;
1369}
1370
1da177e4
LT		 1371/*
1372 * set up BDL entries
1373 */
555e219f
TI		 1374static int azx_setup_periods(struct azx *chip,
1375 struct snd_pcm_substream *substream,
4ce107b9 1376 struct azx_dev *azx_dev)
1da177e4 1377{
4ce107b9
TI		 1378 u32 *bdl;
1379 int i, ofs, periods, period_bytes;
555e219f 1380 int pos_adj;
1da177e4
LT		 1381
1382 /* reset BDL address */
1383 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1384 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1385
97b71c94 1386 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1387 periods = azx_dev->bufsize / period_bytes;
1388
1da177e4 1389 /* program the initial BDL entries */
4ce107b9
TI		 1390 bdl = (u32 *)azx_dev->bdl.area;
1391 ofs = 0;
1392 azx_dev->frags = 0;
555e219f
TI		 1393 pos_adj = bdl_pos_adj[chip->dev_index];
1394 if (pos_adj > 0) {
675f25d4 1395 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1396 int pos_align = pos_adj;
555e219f 1397 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1398 if (!pos_adj)
e785d3d8
TI		 1399 pos_adj = pos_align;
1400 else
1401 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1402 pos_align;
675f25d4
TI		 1403 pos_adj = frames_to_bytes(runtime, pos_adj);
1404 if (pos_adj >= period_bytes) {
4abc1cc2 1405 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1406 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1407 pos_adj = 0;
1408 } else {
5ae763b1 1409 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1410 &bdl, ofs, pos_adj,
1411 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1412 if (ofs < 0)
1413 goto error;
4ce107b9 1414 }
555e219f
TI		 1415 } else
1416 pos_adj = 0;
675f25d4
TI		 1417 for (i = 0; i < periods; i++) {
1418 if (i == periods - 1 && pos_adj)
5ae763b1 1419 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1420 period_bytes - pos_adj, 0);
1421 else
5ae763b1 1422 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1423 period_bytes,
1424 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1425 if (ofs < 0)
1426 goto error;
1da177e4 1427 }
4ce107b9 1428 return 0;
675f25d4
TI		 1429
1430 error:
4abc1cc2 1431 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1432 azx_dev->bufsize, period_bytes);
675f25d4 1433 return -EINVAL;
1da177e4
LT		 1434}
1435
1dddab40
TI		 1436/* reset stream */
1437static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1438{
1439 unsigned char val;
1440 int timeout;
1441
1dddab40
TI		 1442 azx_stream_clear(chip, azx_dev);
1443
d01ce99f
TI		 1444 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1445 SD_CTL_STREAM_RESET);
1da177e4
LT		 1446 udelay(3);
1447 timeout = 300;
1448 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1449 --timeout)
1450 ;
1451 val &= ~SD_CTL_STREAM_RESET;
1452 azx_sd_writeb(azx_dev, SD_CTL, val);
1453 udelay(3);
1454
1455 timeout = 300;
1456 /* waiting for hardware to report that the stream is out of reset */
1457 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1458 --timeout)
1459 ;
fa00e046
JK		 1460
1461 /* reset first position - may not be synced with hw at this time */
1462 *azx_dev->posbuf = 0;
1dddab40 1463}
1da177e4 1464
1dddab40
TI		 1465/*
1466 * set up the SD for streaming
1467 */
1468static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1469{
27fe48d9 1470 unsigned int val;
1dddab40
TI		 1471 /* make sure the run bit is zero for SD */
1472 azx_stream_clear(chip, azx_dev);
1da177e4 1473 /* program the stream_tag */
27fe48d9
TI		 1474 val = azx_sd_readl(azx_dev, SD_CTL);
1475 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1476 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1477 if (!azx_snoop(chip))
1478 val |= SD_CTL_TRAFFIC_PRIO;
1479 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1480
1481 /* program the length of samples in cyclic buffer */
1482 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1483
1484 /* program the stream format */
1485 /* this value needs to be the same as the one programmed */
1486 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1487
1488 /* program the stream LVI (last valid index) of the BDL */
1489 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1490
1491 /* program the BDL address */
1492 /* lower BDL address */
4ce107b9 1493 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1494 /* upper BDL address */
766979e0 1495 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1496
0be3b5d3 1497 /* enable the position buffer */
4cb36310
DH		 1498 if (chip->position_fix[0] != POS_FIX_LPIB ||
1499 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1500 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1501 azx_writel(chip, DPLBASE,
1502 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1503 }
c74db86b 1504
1da177e4 1505 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1506 azx_sd_writel(azx_dev, SD_CTL,
1507 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1508
1509 return 0;
1510}
1511
6ce4a3bc
TI		 1512/*
1513 * Probe the given codec address
1514 */
1515static int probe_codec(struct azx *chip, int addr)
1516{
1517 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1518 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1519 unsigned int res;
1520
a678cdee 1521 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1522 chip->probing = 1;
1523 azx_send_cmd(chip->bus, cmd);
deadff16 1524 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1525 chip->probing = 0;
a678cdee 1526 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1527 if (res == -1)
1528 return -EIO;
4abc1cc2 1529 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1530 return 0;
1531}
1532
33fa35ed
TI		 1533static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1534 struct hda_pcm *cpcm);
6ce4a3bc 1535static void azx_stop_chip(struct azx *chip);
1da177e4 1536
8dd78330
TI		 1537static void azx_bus_reset(struct hda_bus *bus)
1538{
1539 struct azx *chip = bus->private_data;
8dd78330
TI		 1540
1541 bus->in_reset = 1;
1542 azx_stop_chip(chip);
cd508fe5 1543 azx_init_chip(chip, 1);
65f75983 1544#ifdef CONFIG_PM
8dd78330 1545 if (chip->initialized) {
01b65bfb
TI		 1546 struct azx_pcm *p;
1547 list_for_each_entry(p, &chip->pcm_list, list)
1548 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1549 snd_hda_suspend(chip->bus);
1550 snd_hda_resume(chip->bus);
1551 }
65f75983 1552#endif
8dd78330
TI		 1553 bus->in_reset = 0;
1554}
1555
1da177e4
LT		 1556/*
1557 * Codec initialization
1558 */
1559
2f5983f2 1560/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1561static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1562 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1563 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1564};
1565
a82d51ed 1566static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1567{
1568 struct hda_bus_template bus_temp;
34c25350
TI		 1569 int c, codecs, err;
1570 int max_slots;
1da177e4
LT		 1571
1572 memset(&bus_temp, 0, sizeof(bus_temp));
1573 bus_temp.private_data = chip;
1574 bus_temp.modelname = model;
1575 bus_temp.pci = chip->pci;
111d3af5
TI		 1576 bus_temp.ops.command = azx_send_cmd;
1577 bus_temp.ops.get_response = azx_get_response;
176d5335 1578 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1579 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1580#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1581 bus_temp.power_save = &power_save;
cb53c626
TI		 1582 bus_temp.ops.pm_notify = azx_power_notify;
1583#endif
1da177e4 1584
d01ce99f
TI		 1585 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1586 if (err < 0)
1da177e4
LT		 1587 return err;
1588
9477c58e
TI		 1589 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1590 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1591 chip->bus->needs_damn_long_delay = 1;
9477c58e 1592 }
dc9c8e21 1593
34c25350 1594 codecs = 0;
2f5983f2
TI		 1595 max_slots = azx_max_codecs[chip->driver_type];
1596 if (!max_slots)
7445dfc1 1597 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1598
1599 /* First try to probe all given codec slots */
1600 for (c = 0; c < max_slots; c++) {
f1eaaeec 1601 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1602 if (probe_codec(chip, c) < 0) {
1603 /* Some BIOSen give you wrong codec addresses
1604 * that don't exist
1605 */
4abc1cc2
TI		 1606 snd_printk(KERN_WARNING SFX
1607 "Codec #%d probe error; "
6ce4a3bc
TI		 1608 "disabling it...\n", c);
1609 chip->codec_mask &= ~(1 << c);
1610 /* More badly, accessing to a non-existing
1611 * codec often screws up the controller chip,
2448158e 1612 * and disturbs the further communications.
6ce4a3bc
TI		 1613 * Thus if an error occurs during probing,
1614 * better to reset the controller chip to
1615 * get back to the sanity state.
1616 */
1617 azx_stop_chip(chip);
cd508fe5 1618 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1619 }
1620 }
1621 }
1622
d507cd66
TI		 1623 /* AMD chipsets often cause the communication stalls upon certain
1624 * sequence like the pin-detection. It seems that forcing the synced
1625 * access works around the stall. Grrr...
1626 */
9477c58e
TI		 1627 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1628 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1629 chip->bus->sync_write = 1;
1630 chip->bus->allow_bus_reset = 1;
1631 }
1632
6ce4a3bc 1633 /* Then create codec instances */
34c25350 1634 for (c = 0; c < max_slots; c++) {
f1eaaeec 1635 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1636 struct hda_codec *codec;
a1e21c90 1637 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1638 if (err < 0)
1639 continue;
2dca0bba 1640 codec->beep_mode = chip->beep_mode;
1da177e4 1641 codecs++;
19a982b6
TI		 1642 }
1643 }
1644 if (!codecs) {
1da177e4
LT		 1645 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1646 return -ENXIO;
1647 }
a1e21c90
TI		 1648 return 0;
1649}
1da177e4 1650
a1e21c90
TI		 1651/* configure each codec instance */
1652static int __devinit azx_codec_configure(struct azx *chip)
1653{
1654 struct hda_codec *codec;
1655 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1656 snd_hda_codec_configure(codec);
1657 }
1da177e4
LT		 1658 return 0;
1659}
1660
1661
1662/*
1663 * PCM support
1664 */
1665
1666/* assign a stream for the PCM */
ef18bede
WF		 1667static inline struct azx_dev *
1668azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1669{
07e4ca50 1670 int dev, i, nums;
ef18bede 1671 struct azx_dev *res = NULL;
d5cf9911
TI		 1672 /* make a non-zero unique key for the substream */
1673 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1674 (substream->stream + 1);
ef18bede
WF		 1675
1676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1677 dev = chip->playback_index_offset;
1678 nums = chip->playback_streams;
1679 } else {
1680 dev = chip->capture_index_offset;
1681 nums = chip->capture_streams;
1682 }
1683 for (i = 0; i < nums; i++, dev++)
d01ce99f 1684 if (!chip->azx_dev[dev].opened) {
ef18bede 1685 res = &chip->azx_dev[dev];
d5cf9911 1686 if (res->assigned_key == key)
ef18bede 1687 break;
1da177e4 1688 }
ef18bede
WF		 1689 if (res) {
1690 res->opened = 1;
d5cf9911 1691 res->assigned_key = key;
ef18bede
WF		 1692 }
1693 return res;
1da177e4
LT		 1694}
1695
1696/* release the assigned stream */
a98f90fd 1697static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1698{
1699 azx_dev->opened = 0;
1700}
1701
a98f90fd 1702static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1703 .info = (SNDRV_PCM_INFO_MMAP |
1704 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1705 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1706 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1707 /* No full-resume yet implemented */
1708 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1709 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1710 SNDRV_PCM_INFO_SYNC_START |
1711 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1712 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1713 .rates = SNDRV_PCM_RATE_48000,
1714 .rate_min = 48000,
1715 .rate_max = 48000,
1716 .channels_min = 2,
1717 .channels_max = 2,
1718 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1719 .period_bytes_min = 128,
1720 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1721 .periods_min = 2,
1722 .periods_max = AZX_MAX_FRAG,
1723 .fifo_size = 0,
1724};
1725
a98f90fd 1726static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1727{
1728 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1729 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1730 struct azx *chip = apcm->chip;
1731 struct azx_dev *azx_dev;
1732 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1733 unsigned long flags;
1734 int err;
2ae66c26 1735 int buff_step;
1da177e4 1736
62932df8 1737 mutex_lock(&chip->open_mutex);
ef18bede 1738 azx_dev = azx_assign_device(chip, substream);
1da177e4 1739 if (azx_dev == NULL) {
62932df8 1740 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1741 return -EBUSY;
1742 }
1743 runtime->hw = azx_pcm_hw;
1744 runtime->hw.channels_min = hinfo->channels_min;
1745 runtime->hw.channels_max = hinfo->channels_max;
1746 runtime->hw.formats = hinfo->formats;
1747 runtime->hw.rates = hinfo->rates;
1748 snd_pcm_limit_hw_rates(runtime);
1749 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1750 if (chip->align_buffer_size)
2ae66c26
PLB		 1751 /* constrain buffer sizes to be multiple of 128
1752 bytes. This is more efficient in terms of memory
1753 access but isn't required by the HDA spec and
1754 prevents users from specifying exact period/buffer
1755 sizes. For example for 44.1kHz, a period size set
1756 to 20ms will be rounded to 19.59ms. */
1757 buff_step = 128;
1758 else
1759 /* Don't enforce steps on buffer sizes, still need to
1760 be multiple of 4 bytes (HDA spec). Tested on Intel
1761 HDA controllers, may not work on all devices where
1762 option needs to be disabled */
1763 buff_step = 4;
1764
5f1545bc 1765 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1766 buff_step);
5f1545bc 1767 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1768 buff_step);
cb53c626 1769 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1770 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1771 if (err < 0) {
1da177e4 1772 azx_release_device(azx_dev);
cb53c626 1773 snd_hda_power_down(apcm->codec);
62932df8 1774 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1775 return err;
1776 }
70d321e6 1777 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1778 /* sanity check */
1779 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1780 snd_BUG_ON(!runtime->hw.channels_max) ||
1781 snd_BUG_ON(!runtime->hw.formats) ||
1782 snd_BUG_ON(!runtime->hw.rates)) {
1783 azx_release_device(azx_dev);
1784 hinfo->ops.close(hinfo, apcm->codec, substream);
1785 snd_hda_power_down(apcm->codec);
1786 mutex_unlock(&chip->open_mutex);
1787 return -EINVAL;
1788 }
1da177e4
LT		 1789 spin_lock_irqsave(&chip->reg_lock, flags);
1790 azx_dev->substream = substream;
1791 azx_dev->running = 0;
1792 spin_unlock_irqrestore(&chip->reg_lock, flags);
1793
1794 runtime->private_data = azx_dev;
850f0e52 1795 snd_pcm_set_sync(substream);
62932df8 1796 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1797 return 0;
1798}
1799
a98f90fd 1800static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1801{
1802 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1803 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1804 struct azx *chip = apcm->chip;
1805 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1806 unsigned long flags;
1807
62932df8 1808 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1809 spin_lock_irqsave(&chip->reg_lock, flags);
1810 azx_dev->substream = NULL;
1811 azx_dev->running = 0;
1812 spin_unlock_irqrestore(&chip->reg_lock, flags);
1813 azx_release_device(azx_dev);
1814 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1815 snd_hda_power_down(apcm->codec);
62932df8 1816 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1817 return 0;
1818}
1819
d01ce99f
TI		 1820static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1821 struct snd_pcm_hw_params *hw_params)
1da177e4 1822{
27fe48d9
TI		 1823 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1824 struct azx *chip = apcm->chip;
1825 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1826 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1827 int ret;
97b71c94 1828
27fe48d9 1829 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1830 azx_dev->bufsize = 0;
1831 azx_dev->period_bytes = 0;
1832 azx_dev->format_val = 0;
27fe48d9 1833 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1834 params_buffer_bytes(hw_params));
27fe48d9
TI		 1835 if (ret < 0)
1836 return ret;
1837 mark_runtime_wc(chip, azx_dev, runtime, true);
1838 return ret;
1da177e4
LT		 1839}
1840
a98f90fd 1841static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1842{
1843 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1844 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1845 struct azx *chip = apcm->chip;
1846 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1847 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1848
1849 /* reset BDL address */
1850 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1851 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1852 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1853 azx_dev->bufsize = 0;
1854 azx_dev->period_bytes = 0;
1855 azx_dev->format_val = 0;
1da177e4 1856
eb541337 1857 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1858
27fe48d9 1859 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1860 return snd_pcm_lib_free_pages(substream);
1861}
1862
a98f90fd 1863static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1864{
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1866 struct azx *chip = apcm->chip;
1867 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1868 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1869 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1870 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1871 int err;
7c935976
SW		 1872 struct hda_spdif_out *spdif =
1873 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1874 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1875
fa00e046 1876 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1877 format_val = snd_hda_calc_stream_format(runtime->rate,
1878 runtime->channels,
1879 runtime->format,
32c168c8 1880 hinfo->maxbps,
7c935976 1881 ctls);
97b71c94 1882 if (!format_val) {
d01ce99f
TI		 1883 snd_printk(KERN_ERR SFX
1884 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1885 runtime->rate, runtime->channels, runtime->format);
1886 return -EINVAL;
1887 }
1888
97b71c94
TI		 1889 bufsize = snd_pcm_lib_buffer_bytes(substream);
1890 period_bytes = snd_pcm_lib_period_bytes(substream);
1891
4abc1cc2 1892 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1893 bufsize, format_val);
1894
1895 if (bufsize != azx_dev->bufsize ||
1896 period_bytes != azx_dev->period_bytes ||
1897 format_val != azx_dev->format_val) {
1898 azx_dev->bufsize = bufsize;
1899 azx_dev->period_bytes = period_bytes;
1900 azx_dev->format_val = format_val;
1901 err = azx_setup_periods(chip, substream, azx_dev);
1902 if (err < 0)
1903 return err;
1904 }
1905
e5463720
JK		 1906 /* wallclk has 24Mhz clock source */
1907 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1908 runtime->rate) * 1000);
1da177e4
LT		 1909 azx_setup_controller(chip, azx_dev);
1910 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1911 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1912 else
1913 azx_dev->fifo_size = 0;
1914
62b7e5e0
TI		 1915 stream_tag = azx_dev->stream_tag;
1916 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1917 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1918 stream_tag > chip->capture_streams)
1919 stream_tag -= chip->capture_streams;
1920 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1921 azx_dev->format_val, substream);
1da177e4
LT		 1922}
1923
a98f90fd 1924static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1925{
1926 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1927 struct azx *chip = apcm->chip;
850f0e52
TI		 1928 struct azx_dev *azx_dev;
1929 struct snd_pcm_substream *s;
fa00e046 1930 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1931 int nwait, timeout;
1da177e4 1932
1da177e4 1933 switch (cmd) {
fa00e046
JK		 1934 case SNDRV_PCM_TRIGGER_START:
1935 rstart = 1;
1da177e4
LT		 1936 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1937 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1938 start = 1;
1da177e4
LT		 1939 break;
1940 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1941 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1942 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1943 start = 0;
1da177e4
LT		 1944 break;
1945 default:
850f0e52
TI		 1946 return -EINVAL;
1947 }
1948
1949 snd_pcm_group_for_each_entry(s, substream) {
1950 if (s->pcm->card != substream->pcm->card)
1951 continue;
1952 azx_dev = get_azx_dev(s);
1953 sbits |= 1 << azx_dev->index;
1954 nsync++;
1955 snd_pcm_trigger_done(s, substream);
1956 }
1957
1958 spin_lock(&chip->reg_lock);
1959 if (nsync > 1) {
1960 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1961 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1962 azx_writel(chip, OLD_SSYNC,
1963 azx_readl(chip, OLD_SSYNC) | sbits);
1964 else
1965 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1966 }
1967 snd_pcm_group_for_each_entry(s, substream) {
1968 if (s->pcm->card != substream->pcm->card)
1969 continue;
1970 azx_dev = get_azx_dev(s);
e5463720
JK		 1971 if (start) {
1972 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1973 if (!rstart)
1974 azx_dev->start_wallclk -=
1975 azx_dev->period_wallclk;
850f0e52 1976 azx_stream_start(chip, azx_dev);
e5463720 1977 } else {
850f0e52 1978 azx_stream_stop(chip, azx_dev);
e5463720 1979 }
850f0e52 1980 azx_dev->running = start;
1da177e4
LT		 1981 }
1982 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1983 if (start) {
1984 if (nsync == 1)
1985 return 0;
1986 /* wait until all FIFOs get ready */
1987 for (timeout = 5000; timeout; timeout--) {
1988 nwait = 0;
1989 snd_pcm_group_for_each_entry(s, substream) {
1990 if (s->pcm->card != substream->pcm->card)
1991 continue;
1992 azx_dev = get_azx_dev(s);
1993 if (!(azx_sd_readb(azx_dev, SD_STS) &
1994 SD_STS_FIFO_READY))
1995 nwait++;
1996 }
1997 if (!nwait)
1998 break;
1999 cpu_relax();
2000 }
2001 } else {
2002 /* wait until all RUN bits are cleared */
2003 for (timeout = 5000; timeout; timeout--) {
2004 nwait = 0;
2005 snd_pcm_group_for_each_entry(s, substream) {
2006 if (s->pcm->card != substream->pcm->card)
2007 continue;
2008 azx_dev = get_azx_dev(s);
2009 if (azx_sd_readb(azx_dev, SD_CTL) &
2010 SD_CTL_DMA_START)
2011 nwait++;
2012 }
2013 if (!nwait)
2014 break;
2015 cpu_relax();
2016 }
1da177e4 2017 }
850f0e52
TI		 2018 if (nsync > 1) {
2019 spin_lock(&chip->reg_lock);
2020 /* reset SYNC bits */
8b0bd226
TI		 2021 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2022 azx_writel(chip, OLD_SSYNC,
2023 azx_readl(chip, OLD_SSYNC) & ~sbits);
2024 else
2025 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 2026 spin_unlock(&chip->reg_lock);
2027 }
2028 return 0;
1da177e4
LT		 2029}
2030
0e153474
JC		 2031/* get the current DMA position with correction on VIA chips */
2032static unsigned int azx_via_get_position(struct azx *chip,
2033 struct azx_dev *azx_dev)
2034{
2035 unsigned int link_pos, mini_pos, bound_pos;
2036 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2037 unsigned int fifo_size;
2038
2039 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2040 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2041 /* Playback, no problem using link position */
2042 return link_pos;
2043 }
2044
2045 /* Capture */
2046 /* For new chipset,
2047 * use mod to get the DMA position just like old chipset
2048 */
2049 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2050 mod_dma_pos %= azx_dev->period_bytes;
2051
2052 /* azx_dev->fifo_size can't get FIFO size of in stream.
2053 * Get from base address + offset.
2054 */
2055 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2056
2057 if (azx_dev->insufficient) {
2058 /* Link position never gather than FIFO size */
2059 if (link_pos <= fifo_size)
2060 return 0;
2061
2062 azx_dev->insufficient = 0;
2063 }
2064
2065 if (link_pos <= fifo_size)
2066 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2067 else
2068 mini_pos = link_pos - fifo_size;
2069
2070 /* Find nearest previous boudary */
2071 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2072 mod_link_pos = link_pos % azx_dev->period_bytes;
2073 if (mod_link_pos >= fifo_size)
2074 bound_pos = link_pos - mod_link_pos;
2075 else if (mod_dma_pos >= mod_mini_pos)
2076 bound_pos = mini_pos - mod_mini_pos;
2077 else {
2078 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2079 if (bound_pos >= azx_dev->bufsize)
2080 bound_pos = 0;
2081 }
2082
2083 /* Calculate real DMA position we want */
2084 return bound_pos + mod_dma_pos;
2085}
2086
9ad593f6 2087static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2088 struct azx_dev *azx_dev,
2089 bool with_check)
1da177e4 2090{
1da177e4 2091 unsigned int pos;
4cb36310 2092 int stream = azx_dev->substream->stream;
1da177e4 2093
4cb36310
DH		 2094 switch (chip->position_fix[stream]) {
2095 case POS_FIX_LPIB:
2096 /* read LPIB */
2097 pos = azx_sd_readl(azx_dev, SD_LPIB);
2098 break;
2099 case POS_FIX_VIACOMBO:
0e153474 2100 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2101 break;
2102 default:
2103 /* use the position buffer */
2104 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2105 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2106 if (!pos || pos == (u32)-1) {
2107 printk(KERN_WARNING
2108 "hda-intel: Invalid position buffer, "
2109 "using LPIB read method instead.\n");
2110 chip->position_fix[stream] = POS_FIX_LPIB;
2111 pos = azx_sd_readl(azx_dev, SD_LPIB);
2112 } else
2113 chip->position_fix[stream] = POS_FIX_POSBUF;
2114 }
2115 break;
c74db86b 2116 }
4cb36310 2117
1da177e4
LT		 2118 if (pos >= azx_dev->bufsize)
2119 pos = 0;
9ad593f6
TI		 2120 return pos;
2121}
2122
2123static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2124{
2125 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2126 struct azx *chip = apcm->chip;
2127 struct azx_dev *azx_dev = get_azx_dev(substream);
2128 return bytes_to_frames(substream->runtime,
798cb7e8 2129 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2130}
2131
2132/*
2133 * Check whether the current DMA position is acceptable for updating
2134 * periods. Returns non-zero if it's OK.
2135 *
2136 * Many HD-audio controllers appear pretty inaccurate about
2137 * the update-IRQ timing. The IRQ is issued before actually the
2138 * data is processed. So, we need to process it afterwords in a
2139 * workqueue.
2140 */
2141static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2142{
e5463720 2143 u32 wallclk;
9ad593f6 2144 unsigned int pos;
beaffc39 2145 int stream;
9ad593f6 2146
f48f606d
JK		 2147 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2148 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2149 return -1; /* bogus (too early) interrupt */
fa00e046 2150
beaffc39 2151 stream = azx_dev->substream->stream;
798cb7e8 2152 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2153
d6d8bf54
TI		 2154 if (WARN_ONCE(!azx_dev->period_bytes,
2155 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2156 return -1; /* this shouldn't happen! */
edb39935 2157 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2158 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2159 /* NG - it's below the first next period boundary */
2160 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2161 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2162 return 1; /* OK, it's fine */
2163}
2164
2165/*
2166 * The work for pending PCM period updates.
2167 */
2168static void azx_irq_pending_work(struct work_struct *work)
2169{
2170 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2171 int i, pending, ok;
9ad593f6 2172
a6a950a8
TI		 2173 if (!chip->irq_pending_warned) {
2174 printk(KERN_WARNING
2175 "hda-intel: IRQ timing workaround is activated "
2176 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2177 chip->card->number);
2178 chip->irq_pending_warned = 1;
2179 }
2180
9ad593f6
TI		 2181 for (;;) {
2182 pending = 0;
2183 spin_lock_irq(&chip->reg_lock);
2184 for (i = 0; i < chip->num_streams; i++) {
2185 struct azx_dev *azx_dev = &chip->azx_dev[i];
2186 if (!azx_dev->irq_pending ||
2187 !azx_dev->substream ||
2188 !azx_dev->running)
2189 continue;
e5463720
JK		 2190 ok = azx_position_ok(chip, azx_dev);
2191 if (ok > 0) {
9ad593f6
TI		 2192 azx_dev->irq_pending = 0;
2193 spin_unlock(&chip->reg_lock);
2194 snd_pcm_period_elapsed(azx_dev->substream);
2195 spin_lock(&chip->reg_lock);
e5463720
JK		 2196 } else if (ok < 0) {
2197 pending = 0; /* too early */
9ad593f6
TI		 2198 } else
2199 pending++;
2200 }
2201 spin_unlock_irq(&chip->reg_lock);
2202 if (!pending)
2203 return;
08af495f 2204 msleep(1);
9ad593f6
TI		 2205 }
2206}
2207
2208/* clear irq_pending flags and assure no on-going workq */
2209static void azx_clear_irq_pending(struct azx *chip)
2210{
2211 int i;
2212
2213 spin_lock_irq(&chip->reg_lock);
2214 for (i = 0; i < chip->num_streams; i++)
2215 chip->azx_dev[i].irq_pending = 0;
2216 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2217}
2218
27fe48d9
TI		 2219#ifdef CONFIG_X86
2220static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2221 struct vm_area_struct *area)
2222{
2223 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2224 struct azx *chip = apcm->chip;
2225 if (!azx_snoop(chip))
2226 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2227 return snd_pcm_lib_default_mmap(substream, area);
2228}
2229#else
2230#define azx_pcm_mmap NULL
2231#endif
2232
a98f90fd 2233static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2234 .open = azx_pcm_open,
2235 .close = azx_pcm_close,
2236 .ioctl = snd_pcm_lib_ioctl,
2237 .hw_params = azx_pcm_hw_params,
2238 .hw_free = azx_pcm_hw_free,
2239 .prepare = azx_pcm_prepare,
2240 .trigger = azx_pcm_trigger,
2241 .pointer = azx_pcm_pointer,
27fe48d9 2242 .mmap = azx_pcm_mmap,
4ce107b9 2243 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2244};
2245
a98f90fd 2246static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2247{
176d5335
TI		 2248 struct azx_pcm *apcm = pcm->private_data;
2249 if (apcm) {
01b65bfb 2250 list_del(&apcm->list);
176d5335
TI		 2251 kfree(apcm);
2252 }
1da177e4
LT		 2253}
2254
acfa634f
TI		 2255#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2256
176d5335 2257static int
33fa35ed
TI		 2258azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2259 struct hda_pcm *cpcm)
1da177e4 2260{
33fa35ed 2261 struct azx *chip = bus->private_data;
a98f90fd 2262 struct snd_pcm *pcm;
1da177e4 2263 struct azx_pcm *apcm;
176d5335 2264 int pcm_dev = cpcm->device;
acfa634f 2265 unsigned int size;
176d5335 2266 int s, err;
1da177e4 2267
01b65bfb
TI		 2268 list_for_each_entry(apcm, &chip->pcm_list, list) {
2269 if (apcm->pcm->device == pcm_dev) {
2270 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2271 return -EBUSY;
2272 }
176d5335
TI		 2273 }
2274 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2275 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2276 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2277 &pcm);
2278 if (err < 0)
2279 return err;
18cb7109 2280 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2281 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2282 if (apcm == NULL)
2283 return -ENOMEM;
2284 apcm->chip = chip;
01b65bfb 2285 apcm->pcm = pcm;
1da177e4 2286 apcm->codec = codec;
1da177e4
LT		 2287 pcm->private_data = apcm;
2288 pcm->private_free = azx_pcm_free;
176d5335
TI		 2289 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2290 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2291 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2292 cpcm->pcm = pcm;
2293 for (s = 0; s < 2; s++) {
2294 apcm->hinfo[s] = &cpcm->stream[s];
2295 if (cpcm->stream[s].substreams)
2296 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2297 }
2298 /* buffer pre-allocation */
acfa634f
TI		 2299 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2300 if (size > MAX_PREALLOC_SIZE)
2301 size = MAX_PREALLOC_SIZE;
4ce107b9 2302 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2303 snd_dma_pci_data(chip->pci),
acfa634f 2304 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2305 return 0;
2306}
2307
2308/*
2309 * mixer creation - all stuff is implemented in hda module
2310 */
a98f90fd 2311static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2312{
2313 return snd_hda_build_controls(chip->bus);
2314}
2315
2316
2317/*
2318 * initialize SD streams
2319 */
a98f90fd 2320static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2321{
2322 int i;
2323
2324 /* initialize each stream (aka device)
d01ce99f
TI		 2325 * assign the starting bdl address to each stream (device)
2326 * and initialize
1da177e4 2327 */
07e4ca50 2328 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2329 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2330 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2331 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2332 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2333 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2334 azx_dev->sd_int_sta_mask = 1 << i;
2335 /* stream tag: must be non-zero and unique */
2336 azx_dev->index = i;
2337 azx_dev->stream_tag = i + 1;
2338 }
2339
2340 return 0;
2341}
2342
68e7fffc
TI		 2343static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2344{
437a5a46
TI		 2345 if (request_irq(chip->pci->irq, azx_interrupt,
2346 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2347 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2348 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2349 "disabling device\n", chip->pci->irq);
2350 if (do_disconnect)
2351 snd_card_disconnect(chip->card);
2352 return -1;
2353 }
2354 chip->irq = chip->pci->irq;
69e13418 2355 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2356 return 0;
2357}
2358
1da177e4 2359
cb53c626
TI		 2360static void azx_stop_chip(struct azx *chip)
2361{
95e99fda 2362 if (!chip->initialized)
cb53c626
TI		 2363 return;
2364
2365 /* disable interrupts */
2366 azx_int_disable(chip);
2367 azx_int_clear(chip);
2368
2369 /* disable CORB/RIRB */
2370 azx_free_cmd_io(chip);
2371
2372 /* disable position buffer */
2373 azx_writel(chip, DPLBASE, 0);
2374 azx_writel(chip, DPUBASE, 0);
2375
2376 chip->initialized = 0;
2377}
2378
2379#ifdef CONFIG_SND_HDA_POWER_SAVE
2380/* power-up/down the controller */
33fa35ed 2381static void azx_power_notify(struct hda_bus *bus)
cb53c626 2382{
33fa35ed 2383 struct azx *chip = bus->private_data;
cb53c626
TI		 2384 struct hda_codec *c;
2385 int power_on = 0;
2386
33fa35ed 2387 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2388 if (c->power_on) {
2389 power_on = 1;
2390 break;
2391 }
2392 }
2393 if (power_on)
cd508fe5 2394 azx_init_chip(chip, 1);
0287d970
WF		 2395 else if (chip->running && power_save_controller &&
2396 !bus->power_keep_link_on)
cb53c626 2397 azx_stop_chip(chip);
cb53c626 2398}
5c0b9bec
TI		 2399#endif /* CONFIG_SND_HDA_POWER_SAVE */
2400
2401#ifdef CONFIG_PM
2402/*
2403 * power management
2404 */
986862bd 2405
421a1252 2406static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2407{
421a1252
TI		 2408 struct snd_card *card = pci_get_drvdata(pci);
2409 struct azx *chip = card->private_data;
01b65bfb 2410 struct azx_pcm *p;
1da177e4 2411
421a1252 2412 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2413 azx_clear_irq_pending(chip);
01b65bfb
TI		 2414 list_for_each_entry(p, &chip->pcm_list, list)
2415 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2416 if (chip->initialized)
8dd78330 2417 snd_hda_suspend(chip->bus);
cb53c626 2418 azx_stop_chip(chip);
30b35399 2419 if (chip->irq >= 0) {
43001c95 2420 free_irq(chip->irq, chip);
30b35399
TI		 2421 chip->irq = -1;
2422 }
68e7fffc 2423 if (chip->msi)
43001c95 2424 pci_disable_msi(chip->pci);
421a1252
TI		 2425 pci_disable_device(pci);
2426 pci_save_state(pci);
30b35399 2427 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2428 return 0;
2429}
2430
421a1252 2431static int azx_resume(struct pci_dev *pci)
1da177e4 2432{
421a1252
TI		 2433 struct snd_card *card = pci_get_drvdata(pci);
2434 struct azx *chip = card->private_data;
1da177e4 2435
d14a7e0b
TI		 2436 pci_set_power_state(pci, PCI_D0);
2437 pci_restore_state(pci);
30b35399
TI		 2438 if (pci_enable_device(pci) < 0) {
2439 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2440 "disabling device\n");
2441 snd_card_disconnect(card);
2442 return -EIO;
2443 }
2444 pci_set_master(pci);
68e7fffc
TI		 2445 if (chip->msi)
2446 if (pci_enable_msi(pci) < 0)
2447 chip->msi = 0;
2448 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2449 return -EIO;
cb53c626 2450 azx_init_pci(chip);
d804ad92 2451
7f30830b 2452 azx_init_chip(chip, 1);
d804ad92 2453
1da177e4 2454 snd_hda_resume(chip->bus);
421a1252 2455 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2456 return 0;
2457}
2458#endif /* CONFIG_PM */
2459
2460
0cbf0098
TI		 2461/*
2462 * reboot notifier for hang-up problem at power-down
2463 */
2464static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2465{
2466 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2467 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2468 azx_stop_chip(chip);
2469 return NOTIFY_OK;
2470}
2471
2472static void azx_notifier_register(struct azx *chip)
2473{
2474 chip->reboot_notifier.notifier_call = azx_halt;
2475 register_reboot_notifier(&chip->reboot_notifier);
2476}
2477
2478static void azx_notifier_unregister(struct azx *chip)
2479{
2480 if (chip->reboot_notifier.notifier_call)
2481 unregister_reboot_notifier(&chip->reboot_notifier);
2482}
2483
a82d51ed
TI		 2484static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2485static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2486
2487static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2488
2489#ifdef SUPPORT_VGA_SWITCHEROO
2490static void azx_vs_set_state(struct pci_dev *pci,
2491 enum vga_switcheroo_state state)
2492{
2493 struct snd_card *card = pci_get_drvdata(pci);
2494 struct azx *chip = card->private_data;
2495 bool disabled;
2496
2497 if (chip->init_failed)
2498 return;
2499
2500 disabled = (state == VGA_SWITCHEROO_OFF);
2501 if (chip->disabled == disabled)
2502 return;
2503
2504 if (!chip->bus) {
2505 chip->disabled = disabled;
2506 if (!disabled) {
2507 snd_printk(KERN_INFO SFX
2508 "%s: Start delayed initialization\n",
2509 pci_name(chip->pci));
2510 if (azx_first_init(chip) < 0 ||
2511 azx_probe_continue(chip) < 0) {
2512 snd_printk(KERN_ERR SFX
2513 "%s: initialization error\n",
2514 pci_name(chip->pci));
2515 chip->init_failed = true;
2516 }
2517 }
2518 } else {
2519 snd_printk(KERN_INFO SFX
2520 "%s %s via VGA-switcheroo\n",
2521 disabled ? "Disabling" : "Enabling",
2522 pci_name(chip->pci));
2523 if (disabled) {
2524 azx_suspend(pci, PMSG_FREEZE);
2525 chip->disabled = true;
2526 snd_hda_lock_devices(chip->bus);
2527 } else {
2528 snd_hda_unlock_devices(chip->bus);
2529 chip->disabled = false;
2530 azx_resume(pci);
2531 }
2532 }
2533}
2534
2535static bool azx_vs_can_switch(struct pci_dev *pci)
2536{
2537 struct snd_card *card = pci_get_drvdata(pci);
2538 struct azx *chip = card->private_data;
2539
2540 if (chip->init_failed)
2541 return false;
2542 if (chip->disabled || !chip->bus)
2543 return true;
2544 if (snd_hda_lock_devices(chip->bus))
2545 return false;
2546 snd_hda_unlock_devices(chip->bus);
2547 return true;
2548}
2549
2550static void __devinit init_vga_switcheroo(struct azx *chip)
2551{
2552 struct pci_dev *p = get_bound_vga(chip->pci);
2553 if (p) {
2554 snd_printk(KERN_INFO SFX
2555 "%s: Handle VGA-switcheroo audio client\n",
2556 pci_name(chip->pci));
2557 chip->use_vga_switcheroo = 1;
2558 pci_dev_put(p);
2559 }
2560}
2561
2562static const struct vga_switcheroo_client_ops azx_vs_ops = {
2563 .set_gpu_state = azx_vs_set_state,
2564 .can_switch = azx_vs_can_switch,
2565};
2566
2567static int __devinit register_vga_switcheroo(struct azx *chip)
2568{
2569 if (!chip->use_vga_switcheroo)
2570 return 0;
2571 /* FIXME: currently only handling DIS controller
2572 * is there any machine with two switchable HDMI audio controllers?
2573 */
2574 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2575 VGA_SWITCHEROO_DIS,
2576 chip->bus != NULL);
2577}
2578#else
2579#define init_vga_switcheroo(chip) /* NOP */
2580#define register_vga_switcheroo(chip) 0
2581#endif /* SUPPORT_VGA_SWITCHER */
2582
1da177e4
LT		 2583/*
2584 * destructor
2585 */
a98f90fd 2586static int azx_free(struct azx *chip)
1da177e4 2587{
4ce107b9
TI		 2588 int i;
2589
0cbf0098
TI		 2590 azx_notifier_unregister(chip);
2591
a82d51ed
TI		 2592 if (use_vga_switcheroo(chip)) {
2593 if (chip->disabled && chip->bus)
2594 snd_hda_unlock_devices(chip->bus);
2595 vga_switcheroo_unregister_client(chip->pci);
2596 }
2597
ce43fbae 2598 if (chip->initialized) {
9ad593f6 2599 azx_clear_irq_pending(chip);
07e4ca50 2600 for (i = 0; i < chip->num_streams; i++)
1da177e4 2601 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2602 azx_stop_chip(chip);
1da177e4
LT		 2603 }
2604
f000fd80 2605 if (chip->irq >= 0)
1da177e4 2606 free_irq(chip->irq, (void*)chip);
68e7fffc 2607 if (chip->msi)
30b35399 2608 pci_disable_msi(chip->pci);
f079c25a
TI		 2609 if (chip->remap_addr)
2610 iounmap(chip->remap_addr);
1da177e4 2611
4ce107b9
TI		 2612 if (chip->azx_dev) {
2613 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2614 if (chip->azx_dev[i].bdl.area) {
2615 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2616 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2617 }
4ce107b9 2618 }
27fe48d9
TI		 2619 if (chip->rb.area) {
2620 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2621 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2622 }
2623 if (chip->posbuf.area) {
2624 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2625 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2626 }
a82d51ed
TI		 2627 if (chip->region_requested)
2628 pci_release_regions(chip->pci);
1da177e4 2629 pci_disable_device(chip->pci);
07e4ca50 2630 kfree(chip->azx_dev);
1da177e4
LT		 2631 kfree(chip);
2632
2633 return 0;
2634}
2635
a98f90fd 2636static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2637{
2638 return azx_free(device->device_data);
2639}
2640
9121947d
TI		 2641/*
2642 * Check of disabled HDMI controller by vga-switcheroo
2643 */
2644static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2645{
2646 struct pci_dev *p;
2647
2648 /* check only discrete GPU */
2649 switch (pci->vendor) {
2650 case PCI_VENDOR_ID_ATI:
2651 case PCI_VENDOR_ID_AMD:
2652 case PCI_VENDOR_ID_NVIDIA:
2653 if (pci->devfn == 1) {
2654 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2655 pci->bus->number, 0);
2656 if (p) {
2657 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2658 return p;
2659 pci_dev_put(p);
2660 }
2661 }
2662 break;
2663 }
2664 return NULL;
2665}
2666
2667static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2668{
2669 bool vga_inactive = false;
2670 struct pci_dev *p = get_bound_vga(pci);
2671
2672 if (p) {
12b78a7f 2673 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2674 vga_inactive = true;
2675 pci_dev_put(p);
2676 }
2677 return vga_inactive;
2678}
2679
3372a153
TI		 2680/*
2681 * white/black-listing for position_fix
2682 */
623ec047 2683static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2684 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2685 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2686 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2687 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2688 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2689 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2690 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2691 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2692 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2693 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2694 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2695 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2696 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2697 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2698 {}
2699};
2700
2701static int __devinit check_position_fix(struct azx *chip, int fix)
2702{
2703 const struct snd_pci_quirk *q;
2704
c673ba1c
TI		 2705 switch (fix) {
2706 case POS_FIX_LPIB:
2707 case POS_FIX_POSBUF:
4cb36310 2708 case POS_FIX_VIACOMBO:
a6f2fd55 2709 case POS_FIX_COMBO:
c673ba1c
TI		 2710 return fix;
2711 }
2712
c673ba1c
TI		 2713 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2714 if (q) {
2715 printk(KERN_INFO
2716 "hda_intel: position_fix set to %d "
2717 "for device %04x:%04x\n",
2718 q->value, q->subvendor, q->subdevice);
2719 return q->value;
3372a153 2720 }
bdd9ef24
DH		 2721
2722 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2723 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2724 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2725 return POS_FIX_VIACOMBO;
9477c58e
TI		 2726 }
2727 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2728 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2729 return POS_FIX_LPIB;
bdd9ef24 2730 }
c673ba1c 2731 return POS_FIX_AUTO;
3372a153
TI		 2732}
2733
669ba27a
TI		 2734/*
2735 * black-lists for probe_mask
2736 */
2737static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2738 /* Thinkpad often breaks the controller communication when accessing
2739 * to the non-working (or non-existing) modem codec slot.
2740 */
2741 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2742 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2743 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2744 /* broken BIOS */
2745 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2746 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2747 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2748 /* forced codec slots */
93574844 2749 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2750 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2751 /* WinFast VP200 H (Teradici) user reported broken communication */
2752 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2753 {}
2754};
2755
f1eaaeec
TI		 2756#define AZX_FORCE_CODEC_MASK 0x100
2757
5aba4f8e 2758static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2759{
2760 const struct snd_pci_quirk *q;
2761
f1eaaeec
TI		 2762 chip->codec_probe_mask = probe_mask[dev];
2763 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2764 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2765 if (q) {
2766 printk(KERN_INFO
2767 "hda_intel: probe_mask set to 0x%x "
2768 "for device %04x:%04x\n",
2769 q->value, q->subvendor, q->subdevice);
f1eaaeec 2770 chip->codec_probe_mask = q->value;
669ba27a
TI		 2771 }
2772 }
f1eaaeec
TI		 2773
2774 /* check forced option */
2775 if (chip->codec_probe_mask != -1 &&
2776 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2777 chip->codec_mask = chip->codec_probe_mask & 0xff;
2778 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2779 chip->codec_mask);
2780 }
669ba27a
TI		 2781}
2782
4d8e22e0 2783/*
71623855 2784 * white/black-list for enable_msi
4d8e22e0 2785 */
71623855 2786static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2787 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2788 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2789 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2790 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2791 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2792 {}
2793};
2794
2795static void __devinit check_msi(struct azx *chip)
2796{
2797 const struct snd_pci_quirk *q;
2798
71623855
TI		 2799 if (enable_msi >= 0) {
2800 chip->msi = !!enable_msi;
4d8e22e0 2801 return;
71623855
TI		 2802 }
2803 chip->msi = 1; /* enable MSI as default */
2804 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2805 if (q) {
2806 printk(KERN_INFO
2807 "hda_intel: msi for device %04x:%04x set to %d\n",
2808 q->subvendor, q->subdevice, q->value);
2809 chip->msi = q->value;
80c43ed7
TI		 2810 return;
2811 }
2812
2813 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2814 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2815 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2816 chip->msi = 0;
4d8e22e0
TI		 2817 }
2818}
2819
a1585d76
TI		 2820/* check the snoop mode availability */
2821static void __devinit azx_check_snoop_available(struct azx *chip)
2822{
2823 bool snoop = chip->snoop;
2824
2825 switch (chip->driver_type) {
2826 case AZX_DRIVER_VIA:
2827 /* force to non-snoop mode for a new VIA controller
2828 * when BIOS is set
2829 */
2830 if (snoop) {
2831 u8 val;
2832 pci_read_config_byte(chip->pci, 0x42, &val);
2833 if (!(val & 0x80) && chip->pci->revision == 0x30)
2834 snoop = false;
2835 }
2836 break;
2837 case AZX_DRIVER_ATIHDMI_NS:
2838 /* new ATI HDMI requires non-snoop */
2839 snoop = false;
2840 break;
2841 }
2842
2843 if (snoop != chip->snoop) {
2844 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2845 snoop ? "snoop" : "non-snoop");
2846 chip->snoop = snoop;
2847 }
2848}
669ba27a 2849
1da177e4
LT		 2850/*
2851 * constructor
2852 */
a98f90fd 2853static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2854 int dev, unsigned int driver_caps,
a98f90fd 2855 struct azx **rchip)
1da177e4 2856{
a98f90fd 2857 static struct snd_device_ops ops = {
1da177e4
LT		 2858 .dev_free = azx_dev_free,
2859 };
a82d51ed
TI		 2860 struct azx *chip;
2861 int err;
1da177e4
LT		 2862
2863 *rchip = NULL;
bcd72003 2864
927fc866
PM		 2865 err = pci_enable_device(pci);
2866 if (err < 0)
1da177e4
LT		 2867 return err;
2868
e560d8d8 2869 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2870 if (!chip) {
1da177e4
LT		 2871 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2872 pci_disable_device(pci);
2873 return -ENOMEM;
2874 }
2875
2876 spin_lock_init(&chip->reg_lock);
62932df8 2877 mutex_init(&chip->open_mutex);
1da177e4
LT		 2878 chip->card = card;
2879 chip->pci = pci;
2880 chip->irq = -1;
9477c58e
TI		 2881 chip->driver_caps = driver_caps;
2882 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2883 check_msi(chip);
555e219f 2884 chip->dev_index = dev;
9ad593f6 2885 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2886 INIT_LIST_HEAD(&chip->pcm_list);
a82d51ed 2887 init_vga_switcheroo(chip);
1da177e4 2888
beaffc39
SG		 2889 chip->position_fix[0] = chip->position_fix[1] =
2890 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 2891 /* combo mode uses LPIB for playback */
2892 if (chip->position_fix[0] == POS_FIX_COMBO) {
2893 chip->position_fix[0] = POS_FIX_LPIB;
2894 chip->position_fix[1] = POS_FIX_AUTO;
2895 }
2896
5aba4f8e 2897 check_probe_mask(chip, dev);
3372a153 2898
27346166 2899 chip->single_cmd = single_cmd;
27fe48d9 2900 chip->snoop = hda_snoop;
a1585d76 2901 azx_check_snoop_available(chip);
c74db86b 2902
5c0d7bc1
TI		 2903 if (bdl_pos_adj[dev] < 0) {
2904 switch (chip->driver_type) {
0c6341ac 2905 case AZX_DRIVER_ICH:
32679f95 2906 case AZX_DRIVER_PCH:
0c6341ac 2907 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2908 break;
2909 default:
0c6341ac 2910 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2911 break;
2912 }
2913 }
2914
a82d51ed
TI		 2915 if (check_hdmi_disabled(pci)) {
2916 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2917 pci_name(pci));
2918 if (use_vga_switcheroo(chip)) {
2919 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2920 chip->disabled = true;
2921 goto ok;
2922 }
2923 kfree(chip);
2924 pci_disable_device(pci);
2925 return -ENXIO;
2926 }
2927
2928 err = azx_first_init(chip);
2929 if (err < 0) {
2930 azx_free(chip);
2931 return err;
2932 }
2933
2934 ok:
2935 err = register_vga_switcheroo(chip);
2936 if (err < 0) {
2937 snd_printk(KERN_ERR SFX
2938 "Error registering VGA-switcheroo client\n");
2939 azx_free(chip);
2940 return err;
2941 }
2942
2943 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2944 if (err < 0) {
2945 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2946 azx_free(chip);
2947 return err;
2948 }
2949
2950 *rchip = chip;
2951 return 0;
2952}
2953
2954static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2955{
2956 int dev = chip->dev_index;
2957 struct pci_dev *pci = chip->pci;
2958 struct snd_card *card = chip->card;
2959 int i, err;
2960 unsigned short gcap;
2961
07e4ca50
TI		 2962#if BITS_PER_LONG != 64
2963 /* Fix up base address on ULI M5461 */
2964 if (chip->driver_type == AZX_DRIVER_ULI) {
2965 u16 tmp3;
2966 pci_read_config_word(pci, 0x40, &tmp3);
2967 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2968 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2969 }
2970#endif
2971
927fc866 2972 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 2973 if (err < 0)
1da177e4 2974 return err;
a82d51ed 2975 chip->region_requested = 1;
1da177e4 2976
927fc866 2977 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2978 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2979 if (chip->remap_addr == NULL) {
2980 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 2981 return -ENXIO;
1da177e4
LT		 2982 }
2983
68e7fffc
TI		 2984 if (chip->msi)
2985 if (pci_enable_msi(pci) < 0)
2986 chip->msi = 0;
7376d013 2987
a82d51ed
TI		 2988 if (azx_acquire_irq(chip, 0) < 0)
2989 return -EBUSY;
1da177e4
LT		 2990
2991 pci_set_master(pci);
2992 synchronize_irq(chip->irq);
2993
bcd72003 2994 gcap = azx_readw(chip, GCAP);
4abc1cc2 2995 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2996
dc4c2e6b 2997 /* disable SB600 64bit support for safety */
9477c58e 2998 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 2999 struct pci_dev *p_smbus;
3000 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3001 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3002 NULL);
3003 if (p_smbus) {
3004 if (p_smbus->revision < 0x30)
3005 gcap &= ~ICH6_GCAP_64OK;
3006 pci_dev_put(p_smbus);
3007 }
3008 }
09240cf4 3009
9477c58e
TI		 3010 /* disable 64bit DMA address on some devices */
3011 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3012 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3013 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3014 }
396087ea 3015
2ae66c26 3016 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3017 if (align_buffer_size >= 0)
3018 chip->align_buffer_size = !!align_buffer_size;
3019 else {
3020 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3021 chip->align_buffer_size = 0;
3022 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3023 chip->align_buffer_size = 1;
3024 else
3025 chip->align_buffer_size = 1;
3026 }
2ae66c26 3027
cf7aaca8 3028 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3029 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3030 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3031 else {
e930438c
YH		 3032 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3033 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3034 }
cf7aaca8 3035
8b6ed8e7
TI		 3036 /* read number of streams from GCAP register instead of using
3037 * hardcoded value
3038 */
3039 chip->capture_streams = (gcap >> 8) & 0x0f;
3040 chip->playback_streams = (gcap >> 12) & 0x0f;
3041 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3042 /* gcap didn't give any info, switching to old method */
3043
3044 switch (chip->driver_type) {
3045 case AZX_DRIVER_ULI:
3046 chip->playback_streams = ULI_NUM_PLAYBACK;
3047 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3048 break;
3049 case AZX_DRIVER_ATIHDMI:
1815b34a 3050 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3051 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3052 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3053 break;
c4da29ca 3054 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3055 default:
3056 chip->playback_streams = ICH6_NUM_PLAYBACK;
3057 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3058 break;
3059 }
07e4ca50 3060 }
8b6ed8e7
TI		 3061 chip->capture_index_offset = 0;
3062 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3063 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3064 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3065 GFP_KERNEL);
927fc866 3066 if (!chip->azx_dev) {
4abc1cc2 3067 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3068 return -ENOMEM;
07e4ca50
TI		 3069 }
3070
4ce107b9
TI		 3071 for (i = 0; i < chip->num_streams; i++) {
3072 /* allocate memory for the BDL for each stream */
3073 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3074 snd_dma_pci_data(chip->pci),
3075 BDL_SIZE, &chip->azx_dev[i].bdl);
3076 if (err < 0) {
3077 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3078 return -ENOMEM;
4ce107b9 3079 }
27fe48d9 3080 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3081 }
0be3b5d3 3082 /* allocate memory for the position buffer */
d01ce99f
TI		 3083 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3084 snd_dma_pci_data(chip->pci),
3085 chip->num_streams * 8, &chip->posbuf);
3086 if (err < 0) {
0be3b5d3 3087 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3088 return -ENOMEM;
1da177e4 3089 }
27fe48d9 3090 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3091 /* allocate CORB/RIRB */
81740861
TI		 3092 err = azx_alloc_cmd_io(chip);
3093 if (err < 0)
a82d51ed 3094 return err;
1da177e4
LT		 3095
3096 /* initialize streams */
3097 azx_init_stream(chip);
3098
3099 /* initialize chip */
cb53c626 3100 azx_init_pci(chip);
10e77dda 3101 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3102
3103 /* codec detection */
927fc866 3104 if (!chip->codec_mask) {
1da177e4 3105 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3106 return -ENODEV;
1da177e4
LT		 3107 }
3108
07e4ca50 3109 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3110 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3111 sizeof(card->shortname));
3112 snprintf(card->longname, sizeof(card->longname),
3113 "%s at 0x%lx irq %i",
3114 card->shortname, chip->addr, chip->irq);
07e4ca50 3115
1da177e4 3116 return 0;
1da177e4
LT		 3117}
3118
cb53c626
TI		 3119static void power_down_all_codecs(struct azx *chip)
3120{
3121#ifdef CONFIG_SND_HDA_POWER_SAVE
3122 /* The codecs were powered up in snd_hda_codec_new().
3123 * Now all initialization done, so turn them down if possible
3124 */
3125 struct hda_codec *codec;
3126 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3127 snd_hda_power_down(codec);
3128 }
3129#endif
3130}
3131
d01ce99f
TI		 3132static int __devinit azx_probe(struct pci_dev *pci,
3133 const struct pci_device_id *pci_id)
1da177e4 3134{
5aba4f8e 3135 static int dev;
a98f90fd
TI		 3136 struct snd_card *card;
3137 struct azx *chip;
927fc866 3138 int err;
1da177e4 3139
5aba4f8e
TI		 3140 if (dev >= SNDRV_CARDS)
3141 return -ENODEV;
3142 if (!enable[dev]) {
3143 dev++;
3144 return -ENOENT;
3145 }
3146
e58de7ba
TI		 3147 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3148 if (err < 0) {
1da177e4 3149 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3150 return err;
1da177e4
LT		 3151 }
3152
4ea6fbc8
TI		 3153 /* set this here since it's referred in snd_hda_load_patch() */
3154 snd_card_set_dev(card, &pci->dev);
3155
5aba4f8e 3156 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3157 if (err < 0)
3158 goto out_free;
421a1252 3159 card->private_data = chip;
1da177e4 3160
a82d51ed
TI		 3161 if (!chip->disabled) {
3162 err = azx_probe_continue(chip);
3163 if (err < 0)
3164 goto out_free;
3165 }
3166
3167 pci_set_drvdata(pci, card);
3168
3169 dev++;
3170 return 0;
3171
3172out_free:
3173 snd_card_free(card);
3174 return err;
3175}
3176
3177static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3178{
3179 int dev = chip->dev_index;
3180 int err;
3181
2dca0bba
JK		 3182#ifdef CONFIG_SND_HDA_INPUT_BEEP
3183 chip->beep_mode = beep_mode[dev];
3184#endif
3185
1da177e4 3186 /* create codec instances */
a1e21c90 3187 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3188 if (err < 0)
3189 goto out_free;
4ea6fbc8 3190#ifdef CONFIG_SND_HDA_PATCH_LOADER
41a63f18 3191 if (patch[dev] && *patch[dev]) {
4ea6fbc8
TI		 3192 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3193 patch[dev]);
3194 err = snd_hda_load_patch(chip->bus, patch[dev]);
3195 if (err < 0)
3196 goto out_free;
3197 }
3198#endif
10e77dda 3199 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3200 err = azx_codec_configure(chip);
3201 if (err < 0)
3202 goto out_free;
3203 }
1da177e4
LT		 3204
3205 /* create PCM streams */
176d5335 3206 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3207 if (err < 0)
3208 goto out_free;
1da177e4
LT		 3209
3210 /* create mixer controls */
d01ce99f 3211 err = azx_mixer_create(chip);
41dda0fd
WF		 3212 if (err < 0)
3213 goto out_free;
1da177e4 3214
a82d51ed 3215 err = snd_card_register(chip->card);
41dda0fd
WF		 3216 if (err < 0)
3217 goto out_free;
1da177e4 3218
cb53c626
TI		 3219 chip->running = 1;
3220 power_down_all_codecs(chip);
0cbf0098 3221 azx_notifier_register(chip);
1da177e4 3222
9121947d
TI		 3223 return 0;
3224
41dda0fd 3225out_free:
a82d51ed 3226 chip->init_failed = 1;
41dda0fd 3227 return err;
1da177e4
LT		 3228}
3229
3230static void __devexit azx_remove(struct pci_dev *pci)
3231{
9121947d
TI		 3232 struct snd_card *card = pci_get_drvdata(pci);
3233 if (card)
3234 snd_card_free(card);
1da177e4
LT		 3235 pci_set_drvdata(pci, NULL);
3236}
3237
3238/* PCI IDs */
cebe41d4 3239static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3240 /* CPT */
9477c58e 3241 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26
PLB		 3242 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3243 AZX_DCAPS_BUFSIZE },
cea310e8 3244 /* PBG */
9477c58e 3245 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3246 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3247 AZX_DCAPS_BUFSIZE},
d2edeb7c 3248 /* Panther Point */
9477c58e 3249 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3250 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
8bc039a1
SH		 3251 AZX_DCAPS_BUFSIZE},
3252 /* Lynx Point */
3253 { PCI_DEVICE(0x8086, 0x8c20),
3254 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2ae66c26 3255 AZX_DCAPS_BUFSIZE},
87218e9c 3256 /* SCH */
9477c58e 3257 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3258 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3259 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3260 { PCI_DEVICE(0x8086, 0x080a),
3261 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3262 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3263 /* ICH */
8b0bd226 3264 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3265 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3266 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3267 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3268 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3269 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3270 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3271 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3272 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3273 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3274 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3275 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3276 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3277 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3278 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3279 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3280 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3281 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3282 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3283 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3284 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3285 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3286 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3287 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3288 /* Generic Intel */
3289 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3290 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3291 .class_mask = 0xffffff,
2ae66c26 3292 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3293 /* ATI SB 450/600/700/800/900 */
3294 { PCI_DEVICE(0x1002, 0x437b),
3295 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3296 { PCI_DEVICE(0x1002, 0x4383),
3297 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3298 /* AMD Hudson */
3299 { PCI_DEVICE(0x1022, 0x780d),
3300 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3301 /* ATI HDMI */
9477c58e
TI		 3302 { PCI_DEVICE(0x1002, 0x793b),
3303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3304 { PCI_DEVICE(0x1002, 0x7919),
3305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3306 { PCI_DEVICE(0x1002, 0x960f),
3307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3308 { PCI_DEVICE(0x1002, 0x970f),
3309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3310 { PCI_DEVICE(0x1002, 0xaa00),
3311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3312 { PCI_DEVICE(0x1002, 0xaa08),
3313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3314 { PCI_DEVICE(0x1002, 0xaa10),
3315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3316 { PCI_DEVICE(0x1002, 0xaa18),
3317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3318 { PCI_DEVICE(0x1002, 0xaa20),
3319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3320 { PCI_DEVICE(0x1002, 0xaa28),
3321 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3322 { PCI_DEVICE(0x1002, 0xaa30),
3323 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3324 { PCI_DEVICE(0x1002, 0xaa38),
3325 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3326 { PCI_DEVICE(0x1002, 0xaa40),
3327 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3328 { PCI_DEVICE(0x1002, 0xaa48),
3329 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3330 { PCI_DEVICE(0x1002, 0x9902),
3331 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3332 { PCI_DEVICE(0x1002, 0xaaa0),
3333 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3334 { PCI_DEVICE(0x1002, 0xaaa8),
3335 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3336 { PCI_DEVICE(0x1002, 0xaab0),
3337 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3338 /* VIA VT8251/VT8237A */
9477c58e
TI		 3339 { PCI_DEVICE(0x1106, 0x3288),
3340 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
87218e9c
TI		 3341 /* SIS966 */
3342 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3343 /* ULI M5461 */
3344 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3345 /* NVIDIA MCP */
0c2fd1bf
TI		 3346 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3347 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3348 .class_mask = 0xffffff,
9477c58e 3349 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3350 /* Teradici */
9477c58e
TI		 3351 { PCI_DEVICE(0x6549, 0x1200),
3352 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3353 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 3354#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3355 /* the following entry conflicts with snd-ctxfi driver,
3356 * as ctxfi driver mutates from HD-audio to native mode with
3357 * a special command sequence.
3358 */
4e01f54b
TI		 3359 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3360 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3361 .class_mask = 0xffffff,
9477c58e 3362 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3363 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3364#else
3365 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3366 { PCI_DEVICE(0x1102, 0x0009),
3367 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3368 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3369#endif
5ae763b1
TI		 3370 /* CTHDA chips */
3371 { PCI_DEVICE(0x1102, 0x0010),
3372 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3373 { PCI_DEVICE(0x1102, 0x0012),
3374 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e35d4b11
OS		 3375 /* Vortex86MX */
3376 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3377 /* VMware HDAudio */
3378 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3379 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3380 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3381 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3382 .class_mask = 0xffffff,
9477c58e 3383 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3384 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3385 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3386 .class_mask = 0xffffff,
9477c58e 3387 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3388 { 0, }
3389};
3390MODULE_DEVICE_TABLE(pci, azx_ids);
3391
3392/* pci_driver definition */
e9f66d9b 3393static struct pci_driver azx_driver = {
3733e424 3394 .name = KBUILD_MODNAME,
1da177e4
LT		 3395 .id_table = azx_ids,
3396 .probe = azx_probe,
3397 .remove = __devexit_p(azx_remove),
421a1252
TI		 3398#ifdef CONFIG_PM
3399 .suspend = azx_suspend,
3400 .resume = azx_resume,
3401#endif
1da177e4
LT		 3402};
3403
e9f66d9b 3404module_pci_driver(azx_driver);
Linux kernel - Deliverables
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