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ALSA: ASoC: Don't block system resume
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
1da177e4
LT		 48#include <sound/core.h>
49#include <sound/initval.h>
50#include "hda_codec.h"
51
52
5aba4f8e
TI		 53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56static char *model[SNDRV_CARDS];
57static int position_fix[SNDRV_CARDS];
5c0d7bc1 58static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 59static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
27346166 60static int single_cmd;
134a11f0 61static int enable_msi;
1da177e4 62
5aba4f8e 63module_param_array(index, int, NULL, 0444);
1da177e4 64MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 65module_param_array(id, charp, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 67module_param_array(enable, bool, NULL, 0444);
68MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69module_param_array(model, charp, NULL, 0444);
1da177e4 70MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 71module_param_array(position_fix, int, NULL, 0444);
d01ce99f 72MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 73 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 74module_param_array(bdl_pos_adj, int, NULL, 0644);
75MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 76module_param_array(probe_mask, int, NULL, 0444);
606ad75f 77MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
27346166 78module_param(single_cmd, bool, 0444);
d01ce99f
TI		 79MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
80 "(for debugging only).");
5aba4f8e 81module_param(enable_msi, int, 0444);
134a11f0 82MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 83
dee1b66c 84#ifdef CONFIG_SND_HDA_POWER_SAVE
cb53c626 85/* power_save option is defined in hda_codec.c */
1da177e4 86
dee1b66c
TI		 87/* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
89 * wake up.
90 */
91static int power_save_controller = 1;
92module_param(power_save_controller, bool, 0644);
93MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
94#endif
95
1da177e4
LT		 96MODULE_LICENSE("GPL");
97MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
98 "{Intel, ICH6M},"
2f1b3818 99 "{Intel, ICH7},"
f5d40b30 100 "{Intel, ESB2},"
d2981393 101 "{Intel, ICH8},"
f9cc8a8b 102 "{Intel, ICH9},"
c34f5a04 103 "{Intel, ICH10},"
4979bca9 104 "{Intel, SCH},"
fc20a562 105 "{ATI, SB450},"
89be83f8 106 "{ATI, SB600},"
778b6e1b 107 "{ATI, RS600},"
5b15c95f 108 "{ATI, RS690},"
e6db1119
WL		 109 "{ATI, RS780},"
110 "{ATI, R600},"
2797f724
HRK		 111 "{ATI, RV630},"
112 "{ATI, RV610},"
27da1834
WL		 113 "{ATI, RV670},"
114 "{ATI, RV635},"
115 "{ATI, RV620},"
116 "{ATI, RV770},"
fc20a562 117 "{VIA, VT8251},"
47672310 118 "{VIA, VT8237A},"
07e4ca50
TI		 119 "{SiS, SIS966},"
120 "{ULI, M5461}}");
1da177e4
LT		 121MODULE_DESCRIPTION("Intel HDA driver");
122
123#define SFX "hda-intel: "
124
cb53c626 125
1da177e4
LT		 126/*
127 * registers
128 */
129#define ICH6_REG_GCAP 0x00
130#define ICH6_REG_VMIN 0x02
131#define ICH6_REG_VMAJ 0x03
132#define ICH6_REG_OUTPAY 0x04
133#define ICH6_REG_INPAY 0x06
134#define ICH6_REG_GCTL 0x08
135#define ICH6_REG_WAKEEN 0x0c
136#define ICH6_REG_STATESTS 0x0e
137#define ICH6_REG_GSTS 0x10
138#define ICH6_REG_INTCTL 0x20
139#define ICH6_REG_INTSTS 0x24
140#define ICH6_REG_WALCLK 0x30
141#define ICH6_REG_SYNC 0x34
142#define ICH6_REG_CORBLBASE 0x40
143#define ICH6_REG_CORBUBASE 0x44
144#define ICH6_REG_CORBWP 0x48
145#define ICH6_REG_CORBRP 0x4A
146#define ICH6_REG_CORBCTL 0x4c
147#define ICH6_REG_CORBSTS 0x4d
148#define ICH6_REG_CORBSIZE 0x4e
149
150#define ICH6_REG_RIRBLBASE 0x50
151#define ICH6_REG_RIRBUBASE 0x54
152#define ICH6_REG_RIRBWP 0x58
153#define ICH6_REG_RINTCNT 0x5a
154#define ICH6_REG_RIRBCTL 0x5c
155#define ICH6_REG_RIRBSTS 0x5d
156#define ICH6_REG_RIRBSIZE 0x5e
157
158#define ICH6_REG_IC 0x60
159#define ICH6_REG_IR 0x64
160#define ICH6_REG_IRS 0x68
161#define ICH6_IRS_VALID (1<<1)
162#define ICH6_IRS_BUSY (1<<0)
163
164#define ICH6_REG_DPLBASE 0x70
165#define ICH6_REG_DPUBASE 0x74
166#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
167
168/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
169enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
170
171/* stream register offsets from stream base */
172#define ICH6_REG_SD_CTL 0x00
173#define ICH6_REG_SD_STS 0x03
174#define ICH6_REG_SD_LPIB 0x04
175#define ICH6_REG_SD_CBL 0x08
176#define ICH6_REG_SD_LVI 0x0c
177#define ICH6_REG_SD_FIFOW 0x0e
178#define ICH6_REG_SD_FIFOSIZE 0x10
179#define ICH6_REG_SD_FORMAT 0x12
180#define ICH6_REG_SD_BDLPL 0x18
181#define ICH6_REG_SD_BDLPU 0x1c
182
183/* PCI space */
184#define ICH6_PCIREG_TCSEL 0x44
185
186/*
187 * other constants
188 */
189
190/* max number of SDs */
07e4ca50 191/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 192#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 193#define ICH6_NUM_PLAYBACK 4
194
195/* ULI has 6 playback and 5 capture */
07e4ca50 196#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 197#define ULI_NUM_PLAYBACK 6
198
778b6e1b 199/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 200#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 201#define ATIHDMI_NUM_PLAYBACK 1
202
f269002e
KY		 203/* TERA has 4 playback and 3 capture */
204#define TERA_NUM_CAPTURE 3
205#define TERA_NUM_PLAYBACK 4
206
07e4ca50
TI		 207/* this number is statically defined for simplicity */
208#define MAX_AZX_DEV 16
209
1da177e4 210/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 211#define BDL_SIZE 4096
212#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
213#define AZX_MAX_FRAG 32
1da177e4
LT		 214/* max buffer size - no h/w limit, you can increase as you like */
215#define AZX_MAX_BUF_SIZE (1024*1024*1024)
216/* max number of PCM devics per card */
7ba72ba1 217#define AZX_MAX_PCMS 8
1da177e4
LT		 218
219/* RIRB int mask: overrun[2], response[0] */
220#define RIRB_INT_RESPONSE 0x01
221#define RIRB_INT_OVERRUN 0x04
222#define RIRB_INT_MASK 0x05
223
224/* STATESTS int mask: SD2,SD1,SD0 */
19a982b6 225#define AZX_MAX_CODECS 3
1da177e4 226#define STATESTS_INT_MASK 0x07
1da177e4
LT		 227
228/* SD_CTL bits */
229#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
230#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 231#define SD_CTL_STRIPE (3 << 16) /* stripe control */
232#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
233#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 234#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
235#define SD_CTL_STREAM_TAG_SHIFT 20
236
237/* SD_CTL and SD_STS */
238#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
239#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
240#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 241#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
242 SD_INT_COMPLETE)
1da177e4
LT		 243
244/* SD_STS */
245#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
246
247/* INTCTL and INTSTS */
d01ce99f
TI		 248#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
249#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
250#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 251
41e2fce4
M		 252/* GCTL unsolicited response enable bit */
253#define ICH6_GCTL_UREN (1<<8)
254
1da177e4
LT		 255/* GCTL reset bit */
256#define ICH6_GCTL_RESET (1<<0)
257
258/* CORB/RIRB control, read/write pointer */
259#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
260#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
261#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
262/* below are so far hardcoded - should read registers in future */
263#define ICH6_MAX_CORB_ENTRIES 256
264#define ICH6_MAX_RIRB_ENTRIES 256
265
c74db86b
TI		 266/* position fix mode */
267enum {
0be3b5d3 268 POS_FIX_AUTO,
d2e1c973 269 POS_FIX_LPIB,
0be3b5d3 270 POS_FIX_POSBUF,
c74db86b 271};
1da177e4 272
f5d40b30 273/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 274#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
275#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
276
da3fca21
V		 277/* Defines for Nvidia HDA support */
278#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
279#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 280
90a5ad52
TI		 281/* Defines for Intel SCH HDA snoop control */
282#define INTEL_SCH_HDA_DEVC 0x78
283#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
284
285
1da177e4
LT		 286/*
287 */
288
a98f90fd 289struct azx_dev {
4ce107b9 290 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 291 u32 *posbuf; /* position buffer pointer */
1da177e4 292
d01ce99f 293 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 294 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 295 unsigned int frags; /* number for period in the play buffer */
296 unsigned int fifo_size; /* FIFO size */
1da177e4 297
d01ce99f 298 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 299
d01ce99f 300 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 301
302 /* pcm support */
d01ce99f
TI		 303 struct snd_pcm_substream *substream; /* assigned substream,
304 * set in PCM open
305 */
306 unsigned int format_val; /* format value to be set in the
307 * controller and the codec
308 */
1da177e4
LT		 309 unsigned char stream_tag; /* assigned stream */
310 unsigned char index; /* stream index */
311
927fc866
PM		 312 unsigned int opened :1;
313 unsigned int running :1;
675f25d4
TI		 314 unsigned int irq_pending :1;
315 unsigned int irq_ignore :1;
1da177e4
LT		 316};
317
318/* CORB/RIRB */
a98f90fd 319struct azx_rb {
1da177e4
LT		 320 u32 *buf; /* CORB/RIRB buffer
321 * Each CORB entry is 4byte, RIRB is 8byte
322 */
323 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
324 /* for RIRB */
325 unsigned short rp, wp; /* read/write pointers */
326 int cmds; /* number of pending requests */
327 u32 res; /* last read value */
328};
329
a98f90fd
TI		 330struct azx {
331 struct snd_card *card;
1da177e4 332 struct pci_dev *pci;
555e219f 333 int dev_index;
1da177e4 334
07e4ca50
TI		 335 /* chip type specific */
336 int driver_type;
337 int playback_streams;
338 int playback_index_offset;
339 int capture_streams;
340 int capture_index_offset;
341 int num_streams;
342
1da177e4
LT		 343 /* pci resources */
344 unsigned long addr;
345 void __iomem *remap_addr;
346 int irq;
347
348 /* locks */
349 spinlock_t reg_lock;
62932df8 350 struct mutex open_mutex;
1da177e4 351
07e4ca50 352 /* streams (x num_streams) */
a98f90fd 353 struct azx_dev *azx_dev;
1da177e4
LT		 354
355 /* PCM */
a98f90fd 356 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 357
358 /* HD codec */
359 unsigned short codec_mask;
360 struct hda_bus *bus;
361
362 /* CORB/RIRB */
a98f90fd
TI		 363 struct azx_rb corb;
364 struct azx_rb rirb;
1da177e4 365
4ce107b9 366 /* CORB/RIRB and position buffers */
1da177e4
LT		 367 struct snd_dma_buffer rb;
368 struct snd_dma_buffer posbuf;
c74db86b
TI		 369
370 /* flags */
371 int position_fix;
cb53c626 372 unsigned int running :1;
927fc866
PM		 373 unsigned int initialized :1;
374 unsigned int single_cmd :1;
375 unsigned int polling_mode :1;
68e7fffc 376 unsigned int msi :1;
a6a950a8 377 unsigned int irq_pending_warned :1;
43bbb6cc
TI		 378
379 /* for debugging */
380 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 381
382 /* for pending irqs */
383 struct work_struct irq_pending_work;
1da177e4
LT		 384};
385
07e4ca50
TI		 386/* driver types */
387enum {
388 AZX_DRIVER_ICH,
4979bca9 389 AZX_DRIVER_SCH,
07e4ca50 390 AZX_DRIVER_ATI,
778b6e1b 391 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 392 AZX_DRIVER_VIA,
393 AZX_DRIVER_SIS,
394 AZX_DRIVER_ULI,
da3fca21 395 AZX_DRIVER_NVIDIA,
f269002e 396 AZX_DRIVER_TERA,
07e4ca50
TI		 397};
398
399static char *driver_short_names[] __devinitdata = {
400 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 401 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 402 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 403 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 404 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
405 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 406 [AZX_DRIVER_ULI] = "HDA ULI M5461",
407 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 408 [AZX_DRIVER_TERA] = "HDA Teradici",
07e4ca50
TI		 409};
410
1da177e4
LT		 411/*
412 * macros for easy use
413 */
414#define azx_writel(chip,reg,value) \
415 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
416#define azx_readl(chip,reg) \
417 readl((chip)->remap_addr + ICH6_REG_##reg)
418#define azx_writew(chip,reg,value) \
419 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
420#define azx_readw(chip,reg) \
421 readw((chip)->remap_addr + ICH6_REG_##reg)
422#define azx_writeb(chip,reg,value) \
423 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
424#define azx_readb(chip,reg) \
425 readb((chip)->remap_addr + ICH6_REG_##reg)
426
427#define azx_sd_writel(dev,reg,value) \
428 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
429#define azx_sd_readl(dev,reg) \
430 readl((dev)->sd_addr + ICH6_REG_##reg)
431#define azx_sd_writew(dev,reg,value) \
432 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
433#define azx_sd_readw(dev,reg) \
434 readw((dev)->sd_addr + ICH6_REG_##reg)
435#define azx_sd_writeb(dev,reg,value) \
436 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
437#define azx_sd_readb(dev,reg) \
438 readb((dev)->sd_addr + ICH6_REG_##reg)
439
440/* for pcm support */
a98f90fd 441#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4
LT		 442
443/* Get the upper 32bit of the given dma_addr_t
444 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
445 */
446#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
447
68e7fffc 448static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 449
450/*
451 * Interface for HD codec
452 */
453
1da177e4
LT		 454/*
455 * CORB / RIRB interface
456 */
a98f90fd 457static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 458{
459 int err;
460
461 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 462 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
463 snd_dma_pci_data(chip->pci),
1da177e4
LT		 464 PAGE_SIZE, &chip->rb);
465 if (err < 0) {
466 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
467 return err;
468 }
469 return 0;
470}
471
a98f90fd 472static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 473{
474 /* CORB set up */
475 chip->corb.addr = chip->rb.addr;
476 chip->corb.buf = (u32 *)chip->rb.area;
477 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
478 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
479
07e4ca50
TI		 480 /* set the corb size to 256 entries (ULI requires explicitly) */
481 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 482 /* set the corb write pointer to 0 */
483 azx_writew(chip, CORBWP, 0);
484 /* reset the corb hw read pointer */
485 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
486 /* enable corb dma */
487 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
488
489 /* RIRB set up */
490 chip->rirb.addr = chip->rb.addr + 2048;
491 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
492 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
493 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
494
07e4ca50
TI		 495 /* set the rirb size to 256 entries (ULI requires explicitly) */
496 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 497 /* reset the rirb hw write pointer */
498 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
499 /* set N=1, get RIRB response interrupt for new entry */
500 azx_writew(chip, RINTCNT, 1);
501 /* enable rirb dma and response irq */
1da177e4 502 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 503 chip->rirb.rp = chip->rirb.cmds = 0;
504}
505
a98f90fd 506static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 507{
508 /* disable ringbuffer DMAs */
509 azx_writeb(chip, RIRBCTL, 0);
510 azx_writeb(chip, CORBCTL, 0);
511}
512
513/* send a command */
43bbb6cc 514static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 515{
a98f90fd 516 struct azx *chip = codec->bus->private_data;
1da177e4 517 unsigned int wp;
1da177e4
LT		 518
519 /* add command to corb */
520 wp = azx_readb(chip, CORBWP);
521 wp++;
522 wp %= ICH6_MAX_CORB_ENTRIES;
523
524 spin_lock_irq(&chip->reg_lock);
525 chip->rirb.cmds++;
526 chip->corb.buf[wp] = cpu_to_le32(val);
527 azx_writel(chip, CORBWP, wp);
528 spin_unlock_irq(&chip->reg_lock);
529
530 return 0;
531}
532
533#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
534
535/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 536static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 537{
538 unsigned int rp, wp;
539 u32 res, res_ex;
540
541 wp = azx_readb(chip, RIRBWP);
542 if (wp == chip->rirb.wp)
543 return;
544 chip->rirb.wp = wp;
545
546 while (chip->rirb.rp != wp) {
547 chip->rirb.rp++;
548 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
549
550 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
551 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
552 res = le32_to_cpu(chip->rirb.buf[rp]);
553 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
554 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
555 else if (chip->rirb.cmds) {
1da177e4 556 chip->rirb.res = res;
2add9b92
TI		 557 smp_wmb();
558 chip->rirb.cmds--;
1da177e4
LT		 559 }
560 }
561}
562
563/* receive a response */
111d3af5 564static unsigned int azx_rirb_get_response(struct hda_codec *codec)
1da177e4 565{
a98f90fd 566 struct azx *chip = codec->bus->private_data;
5c79b1f8 567 unsigned long timeout;
1da177e4 568
5c79b1f8
TI		 569 again:
570 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 571 for (;;) {
e96224ae
TI		 572 if (chip->polling_mode) {
573 spin_lock_irq(&chip->reg_lock);
574 azx_update_rirb(chip);
575 spin_unlock_irq(&chip->reg_lock);
576 }
2add9b92
TI		 577 if (!chip->rirb.cmds) {
578 smp_rmb();
5c79b1f8 579 return chip->rirb.res; /* the last value */
2add9b92 580 }
28a0d9df
TI		 581 if (time_after(jiffies, timeout))
582 break;
52987656
TI		 583 if (codec->bus->needs_damn_long_delay)
584 msleep(2); /* temporary workaround */
585 else {
586 udelay(10);
587 cond_resched();
588 }
28a0d9df 589 }
5c79b1f8 590
68e7fffc
TI		 591 if (chip->msi) {
592 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
43bbb6cc 593 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 594 free_irq(chip->irq, chip);
595 chip->irq = -1;
596 pci_disable_msi(chip->pci);
597 chip->msi = 0;
598 if (azx_acquire_irq(chip, 1) < 0)
599 return -1;
600 goto again;
601 }
602
5c79b1f8
TI		 603 if (!chip->polling_mode) {
604 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 605 "switching to polling mode: last cmd=0x%08x\n",
606 chip->last_cmd);
5c79b1f8
TI		 607 chip->polling_mode = 1;
608 goto again;
1da177e4 609 }
5c79b1f8
TI		 610
611 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 612 "switching to single_cmd mode: last cmd=0x%08x\n",
613 chip->last_cmd);
5c79b1f8
TI		 614 chip->rirb.rp = azx_readb(chip, RIRBWP);
615 chip->rirb.cmds = 0;
616 /* switch to single_cmd mode */
617 chip->single_cmd = 1;
618 azx_free_cmd_io(chip);
619 return -1;
1da177e4
LT		 620}
621
1da177e4
LT		 622/*
623 * Use the single immediate command instead of CORB/RIRB for simplicity
624 *
625 * Note: according to Intel, this is not preferred use. The command was
626 * intended for the BIOS only, and may get confused with unsolicited
627 * responses. So, we shouldn't use it for normal operation from the
628 * driver.
629 * I left the codes, however, for debugging/testing purposes.
630 */
631
1da177e4 632/* send a command */
43bbb6cc 633static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 634{
a98f90fd 635 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 636 int timeout = 50;
637
1da177e4
LT		 638 while (timeout--) {
639 /* check ICB busy bit */
d01ce99f 640 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 641 /* Clear IRV valid bit */
d01ce99f
TI		 642 azx_writew(chip, IRS, azx_readw(chip, IRS) |
643 ICH6_IRS_VALID);
1da177e4 644 azx_writel(chip, IC, val);
d01ce99f
TI		 645 azx_writew(chip, IRS, azx_readw(chip, IRS) |
646 ICH6_IRS_BUSY);
1da177e4
LT		 647 return 0;
648 }
649 udelay(1);
650 }
1cfd52bc
MB		 651 if (printk_ratelimit())
652 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
653 azx_readw(chip, IRS), val);
1da177e4
LT		 654 return -EIO;
655}
656
657/* receive a response */
27346166 658static unsigned int azx_single_get_response(struct hda_codec *codec)
1da177e4 659{
a98f90fd 660 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 661 int timeout = 50;
662
663 while (timeout--) {
664 /* check IRV busy bit */
665 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
666 return azx_readl(chip, IR);
667 udelay(1);
668 }
1cfd52bc
MB		 669 if (printk_ratelimit())
670 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
671 azx_readw(chip, IRS));
1da177e4
LT		 672 return (unsigned int)-1;
673}
674
111d3af5
TI		 675/*
676 * The below are the main callbacks from hda_codec.
677 *
678 * They are just the skeleton to call sub-callbacks according to the
679 * current setting of chip->single_cmd.
680 */
681
682/* send a command */
683static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
684 int direct, unsigned int verb,
685 unsigned int para)
686{
687 struct azx *chip = codec->bus->private_data;
43bbb6cc
TI		 688 u32 val;
689
690 val = (u32)(codec->addr & 0x0f) << 28;
691 val |= (u32)direct << 27;
692 val |= (u32)nid << 20;
693 val |= verb << 8;
694 val |= para;
695 chip->last_cmd = val;
696
111d3af5 697 if (chip->single_cmd)
43bbb6cc 698 return azx_single_send_cmd(codec, val);
111d3af5 699 else
43bbb6cc 700 return azx_corb_send_cmd(codec, val);
111d3af5
TI		 701}
702
703/* get a response */
704static unsigned int azx_get_response(struct hda_codec *codec)
705{
706 struct azx *chip = codec->bus->private_data;
707 if (chip->single_cmd)
708 return azx_single_get_response(codec);
709 else
710 return azx_rirb_get_response(codec);
711}
712
cb53c626
TI		 713#ifdef CONFIG_SND_HDA_POWER_SAVE
714static void azx_power_notify(struct hda_codec *codec);
715#endif
111d3af5 716
1da177e4 717/* reset codec link */
a98f90fd 718static int azx_reset(struct azx *chip)
1da177e4
LT		 719{
720 int count;
721
e8a7f136
DT		 722 /* clear STATESTS */
723 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
724
1da177e4
LT		 725 /* reset controller */
726 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
727
728 count = 50;
729 while (azx_readb(chip, GCTL) && --count)
730 msleep(1);
731
732 /* delay for >= 100us for codec PLL to settle per spec
733 * Rev 0.9 section 5.5.1
734 */
735 msleep(1);
736
737 /* Bring controller out of reset */
738 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
739
740 count = 50;
927fc866 741 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 742 msleep(1);
743
927fc866 744 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 745 msleep(1);
746
747 /* check to see if controller is ready */
927fc866 748 if (!azx_readb(chip, GCTL)) {
1da177e4
LT		 749 snd_printd("azx_reset: controller not ready!\n");
750 return -EBUSY;
751 }
752
41e2fce4
M		 753 /* Accept unsolicited responses */
754 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
755
1da177e4 756 /* detect codecs */
927fc866 757 if (!chip->codec_mask) {
1da177e4
LT		 758 chip->codec_mask = azx_readw(chip, STATESTS);
759 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
760 }
761
762 return 0;
763}
764
765
766/*
767 * Lowlevel interface
768 */
769
770/* enable interrupts */
a98f90fd 771static void azx_int_enable(struct azx *chip)
1da177e4
LT		 772{
773 /* enable controller CIE and GIE */
774 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
775 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
776}
777
778/* disable interrupts */
a98f90fd 779static void azx_int_disable(struct azx *chip)
1da177e4
LT		 780{
781 int i;
782
783 /* disable interrupts in stream descriptor */
07e4ca50 784 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 785 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 786 azx_sd_writeb(azx_dev, SD_CTL,
787 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
788 }
789
790 /* disable SIE for all streams */
791 azx_writeb(chip, INTCTL, 0);
792
793 /* disable controller CIE and GIE */
794 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
795 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
796}
797
798/* clear interrupts */
a98f90fd 799static void azx_int_clear(struct azx *chip)
1da177e4
LT		 800{
801 int i;
802
803 /* clear stream status */
07e4ca50 804 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 805 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 806 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
807 }
808
809 /* clear STATESTS */
810 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
811
812 /* clear rirb status */
813 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
814
815 /* clear int status */
816 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
817}
818
819/* start a stream */
a98f90fd 820static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 821{
822 /* enable SIE */
823 azx_writeb(chip, INTCTL,
824 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
825 /* set DMA start and interrupt mask */
826 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
827 SD_CTL_DMA_START | SD_INT_MASK);
828}
829
830/* stop a stream */
a98f90fd 831static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 832{
833 /* stop DMA */
834 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
835 ~(SD_CTL_DMA_START | SD_INT_MASK));
836 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
837 /* disable SIE */
838 azx_writeb(chip, INTCTL,
839 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
840}
841
842
843/*
cb53c626 844 * reset and start the controller registers
1da177e4 845 */
a98f90fd 846static void azx_init_chip(struct azx *chip)
1da177e4 847{
cb53c626
TI		 848 if (chip->initialized)
849 return;
1da177e4
LT		 850
851 /* reset controller */
852 azx_reset(chip);
853
854 /* initialize interrupts */
855 azx_int_clear(chip);
856 azx_int_enable(chip);
857
858 /* initialize the codec command I/O */
927fc866 859 if (!chip->single_cmd)
27346166 860 azx_init_cmd_io(chip);
1da177e4 861
0be3b5d3
TI		 862 /* program the position buffer */
863 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
864 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 865
cb53c626
TI		 866 chip->initialized = 1;
867}
868
869/*
870 * initialize the PCI registers
871 */
872/* update bits in a PCI register byte */
873static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
874 unsigned char mask, unsigned char val)
875{
876 unsigned char data;
877
878 pci_read_config_byte(pci, reg, &data);
879 data &= ~mask;
880 data |= (val & mask);
881 pci_write_config_byte(pci, reg, data);
882}
883
884static void azx_init_pci(struct azx *chip)
885{
90a5ad52
TI		 886 unsigned short snoop;
887
cb53c626
TI		 888 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
889 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
890 * Ensuring these bits are 0 clears playback static on some HD Audio
891 * codecs
892 */
893 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
894
da3fca21
V		 895 switch (chip->driver_type) {
896 case AZX_DRIVER_ATI:
897 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 898 update_pci_byte(chip->pci,
899 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
900 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 901 break;
902 case AZX_DRIVER_NVIDIA:
903 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 904 update_pci_byte(chip->pci,
905 NVIDIA_HDA_TRANSREG_ADDR,
906 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
da3fca21 907 break;
90a5ad52
TI		 908 case AZX_DRIVER_SCH:
909 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
910 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
911 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
912 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
913 pci_read_config_word(chip->pci,
914 INTEL_SCH_HDA_DEVC, &snoop);
915 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
916 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
917 ? "Failed" : "OK");
918 }
919 break;
920
da3fca21 921 }
1da177e4
LT		 922}
923
924
9ad593f6
TI		 925static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
926
1da177e4
LT		 927/*
928 * interrupt handler
929 */
7d12e780 930static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 931{
a98f90fd
TI		 932 struct azx *chip = dev_id;
933 struct azx_dev *azx_dev;
1da177e4
LT		 934 u32 status;
935 int i;
936
937 spin_lock(&chip->reg_lock);
938
939 status = azx_readl(chip, INTSTS);
940 if (status == 0) {
941 spin_unlock(&chip->reg_lock);
942 return IRQ_NONE;
943 }
944
07e4ca50 945 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 946 azx_dev = &chip->azx_dev[i];
947 if (status & azx_dev->sd_int_sta_mask) {
948 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 949 if (!azx_dev->substream || !azx_dev->running)
950 continue;
675f25d4
TI		 951 /* ignore the first dummy IRQ (due to pos_adj) */
952 if (azx_dev->irq_ignore) {
953 azx_dev->irq_ignore = 0;
954 continue;
955 }
9ad593f6
TI		 956 /* check whether this IRQ is really acceptable */
957 if (azx_position_ok(chip, azx_dev)) {
958 azx_dev->irq_pending = 0;
1da177e4
LT		 959 spin_unlock(&chip->reg_lock);
960 snd_pcm_period_elapsed(azx_dev->substream);
961 spin_lock(&chip->reg_lock);
9ad593f6
TI		 962 } else {
963 /* bogus IRQ, process it later */
964 azx_dev->irq_pending = 1;
965 schedule_work(&chip->irq_pending_work);
1da177e4
LT		 966 }
967 }
968 }
969
970 /* clear rirb int */
971 status = azx_readb(chip, RIRBSTS);
972 if (status & RIRB_INT_MASK) {
d01ce99f 973 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 974 azx_update_rirb(chip);
975 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
976 }
977
978#if 0
979 /* clear state status int */
980 if (azx_readb(chip, STATESTS) & 0x04)
981 azx_writeb(chip, STATESTS, 0x04);
982#endif
983 spin_unlock(&chip->reg_lock);
984
985 return IRQ_HANDLED;
986}
987
988
675f25d4
TI		 989/*
990 * set up a BDL entry
991 */
992static int setup_bdle(struct snd_pcm_substream *substream,
993 struct azx_dev *azx_dev, u32 **bdlp,
994 int ofs, int size, int with_ioc)
995{
996 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
997 u32 *bdl = *bdlp;
998
999 while (size > 0) {
1000 dma_addr_t addr;
1001 int chunk;
1002
1003 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1004 return -EINVAL;
1005
1006 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1007 /* program the address field of the BDL entry */
1008 bdl[0] = cpu_to_le32((u32)addr);
1009 bdl[1] = cpu_to_le32(upper_32bit(addr));
1010 /* program the size field of the BDL entry */
1011 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1012 if (size < chunk)
1013 chunk = size;
1014 bdl[2] = cpu_to_le32(chunk);
1015 /* program the IOC to enable interrupt
1016 * only when the whole fragment is processed
1017 */
1018 size -= chunk;
1019 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1020 bdl += 4;
1021 azx_dev->frags++;
1022 ofs += chunk;
1023 }
1024 *bdlp = bdl;
1025 return ofs;
1026}
1027
1da177e4
LT		 1028/*
1029 * set up BDL entries
1030 */
555e219f
TI		 1031static int azx_setup_periods(struct azx *chip,
1032 struct snd_pcm_substream *substream,
4ce107b9 1033 struct azx_dev *azx_dev)
1da177e4 1034{
4ce107b9
TI		 1035 u32 *bdl;
1036 int i, ofs, periods, period_bytes;
555e219f 1037 int pos_adj;
1da177e4
LT		 1038
1039 /* reset BDL address */
1040 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1041 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1042
4ce107b9 1043 period_bytes = snd_pcm_lib_period_bytes(substream);
9ad593f6 1044 azx_dev->period_bytes = period_bytes;
4ce107b9
TI		 1045 periods = azx_dev->bufsize / period_bytes;
1046
1da177e4 1047 /* program the initial BDL entries */
4ce107b9
TI		 1048 bdl = (u32 *)azx_dev->bdl.area;
1049 ofs = 0;
1050 azx_dev->frags = 0;
675f25d4 1051 azx_dev->irq_ignore = 0;
555e219f
TI		 1052 pos_adj = bdl_pos_adj[chip->dev_index];
1053 if (pos_adj > 0) {
675f25d4 1054 struct snd_pcm_runtime *runtime = substream->runtime;
555e219f 1055 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4
TI		 1056 if (!pos_adj)
1057 pos_adj = 1;
1058 pos_adj = frames_to_bytes(runtime, pos_adj);
1059 if (pos_adj >= period_bytes) {
1060 snd_printk(KERN_WARNING "Too big adjustment %d\n",
555e219f 1061 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1062 pos_adj = 0;
1063 } else {
1064 ofs = setup_bdle(substream, azx_dev,
1065 &bdl, ofs, pos_adj, 1);
1066 if (ofs < 0)
1067 goto error;
1068 azx_dev->irq_ignore = 1;
4ce107b9 1069 }
555e219f
TI		 1070 } else
1071 pos_adj = 0;
675f25d4
TI		 1072 for (i = 0; i < periods; i++) {
1073 if (i == periods - 1 && pos_adj)
1074 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1075 period_bytes - pos_adj, 0);
1076 else
1077 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1078 period_bytes, 1);
1079 if (ofs < 0)
1080 goto error;
1da177e4 1081 }
4ce107b9 1082 return 0;
675f25d4
TI		 1083
1084 error:
1085 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1086 azx_dev->bufsize, period_bytes);
1087 /* reset */
1088 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1089 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1090 return -EINVAL;
1da177e4
LT		 1091}
1092
1093/*
1094 * set up the SD for streaming
1095 */
a98f90fd 1096static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1097{
1098 unsigned char val;
1099 int timeout;
1100
1101 /* make sure the run bit is zero for SD */
d01ce99f
TI		 1102 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1103 ~SD_CTL_DMA_START);
1da177e4 1104 /* reset stream */
d01ce99f
TI		 1105 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1106 SD_CTL_STREAM_RESET);
1da177e4
LT		 1107 udelay(3);
1108 timeout = 300;
1109 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1110 --timeout)
1111 ;
1112 val &= ~SD_CTL_STREAM_RESET;
1113 azx_sd_writeb(azx_dev, SD_CTL, val);
1114 udelay(3);
1115
1116 timeout = 300;
1117 /* waiting for hardware to report that the stream is out of reset */
1118 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1119 --timeout)
1120 ;
1121
1122 /* program the stream_tag */
1123 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1124 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1125 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1126
1127 /* program the length of samples in cyclic buffer */
1128 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1129
1130 /* program the stream format */
1131 /* this value needs to be the same as the one programmed */
1132 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1133
1134 /* program the stream LVI (last valid index) of the BDL */
1135 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1136
1137 /* program the BDL address */
1138 /* lower BDL address */
4ce107b9 1139 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1140 /* upper BDL address */
4ce107b9 1141 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1da177e4 1142
0be3b5d3 1143 /* enable the position buffer */
ee9d6b9a
TI		 1144 if (chip->position_fix == POS_FIX_POSBUF ||
1145 chip->position_fix == POS_FIX_AUTO) {
1146 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1147 azx_writel(chip, DPLBASE,
1148 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1149 }
c74db86b 1150
1da177e4 1151 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1152 azx_sd_writel(azx_dev, SD_CTL,
1153 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1154
1155 return 0;
1156}
1157
1158
1159/*
1160 * Codec initialization
1161 */
1162
a9995a35 1163static unsigned int azx_max_codecs[] __devinitdata = {
607d982b 1164 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
90a5ad52 1165 [AZX_DRIVER_SCH] = 3,
a9995a35
TI		 1166 [AZX_DRIVER_ATI] = 4,
1167 [AZX_DRIVER_ATIHDMI] = 4,
1168 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1169 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1170 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1171 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
f269002e 1172 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1173};
1174
5aba4f8e
TI		 1175static int __devinit azx_codec_create(struct azx *chip, const char *model,
1176 unsigned int codec_probe_mask)
1da177e4
LT		 1177{
1178 struct hda_bus_template bus_temp;
bccad14e 1179 int c, codecs, audio_codecs, err;
1da177e4
LT		 1180
1181 memset(&bus_temp, 0, sizeof(bus_temp));
1182 bus_temp.private_data = chip;
1183 bus_temp.modelname = model;
1184 bus_temp.pci = chip->pci;
111d3af5
TI		 1185 bus_temp.ops.command = azx_send_cmd;
1186 bus_temp.ops.get_response = azx_get_response;
cb53c626
TI		 1187#ifdef CONFIG_SND_HDA_POWER_SAVE
1188 bus_temp.ops.pm_notify = azx_power_notify;
1189#endif
1da177e4 1190
d01ce99f
TI		 1191 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1192 if (err < 0)
1da177e4
LT		 1193 return err;
1194
bccad14e 1195 codecs = audio_codecs = 0;
19a982b6 1196 for (c = 0; c < AZX_MAX_CODECS; c++) {
5aba4f8e 1197 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
bccad14e
TI		 1198 struct hda_codec *codec;
1199 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1200 if (err < 0)
1201 continue;
1202 codecs++;
bccad14e
TI		 1203 if (codec->afg)
1204 audio_codecs++;
1da177e4
LT		 1205 }
1206 }
bccad14e 1207 if (!audio_codecs) {
19a982b6
TI		 1208 /* probe additional slots if no codec is found */
1209 for (; c < azx_max_codecs[chip->driver_type]; c++) {
5aba4f8e 1210 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
19a982b6
TI		 1211 err = snd_hda_codec_new(chip->bus, c, NULL);
1212 if (err < 0)
1213 continue;
1214 codecs++;
1215 }
1216 }
1217 }
1218 if (!codecs) {
1da177e4
LT		 1219 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1220 return -ENXIO;
1221 }
1222
1223 return 0;
1224}
1225
1226
1227/*
1228 * PCM support
1229 */
1230
1231/* assign a stream for the PCM */
a98f90fd 1232static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1233{
07e4ca50
TI		 1234 int dev, i, nums;
1235 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1236 dev = chip->playback_index_offset;
1237 nums = chip->playback_streams;
1238 } else {
1239 dev = chip->capture_index_offset;
1240 nums = chip->capture_streams;
1241 }
1242 for (i = 0; i < nums; i++, dev++)
d01ce99f 1243 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1244 chip->azx_dev[dev].opened = 1;
1245 return &chip->azx_dev[dev];
1246 }
1247 return NULL;
1248}
1249
1250/* release the assigned stream */
a98f90fd 1251static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1252{
1253 azx_dev->opened = 0;
1254}
1255
a98f90fd 1256static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1257 .info = (SNDRV_PCM_INFO_MMAP |
1258 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1259 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1260 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1261 /* No full-resume yet implemented */
1262 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1263 SNDRV_PCM_INFO_PAUSE |
1264 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1265 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1266 .rates = SNDRV_PCM_RATE_48000,
1267 .rate_min = 48000,
1268 .rate_max = 48000,
1269 .channels_min = 2,
1270 .channels_max = 2,
1271 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1272 .period_bytes_min = 128,
1273 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1274 .periods_min = 2,
1275 .periods_max = AZX_MAX_FRAG,
1276 .fifo_size = 0,
1277};
1278
1279struct azx_pcm {
a98f90fd 1280 struct azx *chip;
1da177e4
LT		 1281 struct hda_codec *codec;
1282 struct hda_pcm_stream *hinfo[2];
1283};
1284
a98f90fd 1285static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1286{
1287 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1288 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1289 struct azx *chip = apcm->chip;
1290 struct azx_dev *azx_dev;
1291 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1292 unsigned long flags;
1293 int err;
1294
62932df8 1295 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1296 azx_dev = azx_assign_device(chip, substream->stream);
1297 if (azx_dev == NULL) {
62932df8 1298 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1299 return -EBUSY;
1300 }
1301 runtime->hw = azx_pcm_hw;
1302 runtime->hw.channels_min = hinfo->channels_min;
1303 runtime->hw.channels_max = hinfo->channels_max;
1304 runtime->hw.formats = hinfo->formats;
1305 runtime->hw.rates = hinfo->rates;
1306 snd_pcm_limit_hw_rates(runtime);
1307 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1308 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1309 128);
1310 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1311 128);
cb53c626 1312 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1313 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1314 if (err < 0) {
1da177e4 1315 azx_release_device(azx_dev);
cb53c626 1316 snd_hda_power_down(apcm->codec);
62932df8 1317 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1318 return err;
1319 }
1320 spin_lock_irqsave(&chip->reg_lock, flags);
1321 azx_dev->substream = substream;
1322 azx_dev->running = 0;
1323 spin_unlock_irqrestore(&chip->reg_lock, flags);
1324
1325 runtime->private_data = azx_dev;
850f0e52 1326 snd_pcm_set_sync(substream);
62932df8 1327 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1328 return 0;
1329}
1330
a98f90fd 1331static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1332{
1333 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1334 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1335 struct azx *chip = apcm->chip;
1336 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1337 unsigned long flags;
1338
62932df8 1339 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1340 spin_lock_irqsave(&chip->reg_lock, flags);
1341 azx_dev->substream = NULL;
1342 azx_dev->running = 0;
1343 spin_unlock_irqrestore(&chip->reg_lock, flags);
1344 azx_release_device(azx_dev);
1345 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1346 snd_hda_power_down(apcm->codec);
62932df8 1347 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1348 return 0;
1349}
1350
d01ce99f
TI		 1351static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1352 struct snd_pcm_hw_params *hw_params)
1da177e4 1353{
d01ce99f
TI		 1354 return snd_pcm_lib_malloc_pages(substream,
1355 params_buffer_bytes(hw_params));
1da177e4
LT		 1356}
1357
a98f90fd 1358static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1359{
1360 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1361 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1362 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1363
1364 /* reset BDL address */
1365 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1366 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1367 azx_sd_writel(azx_dev, SD_CTL, 0);
1368
1369 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1370
1371 return snd_pcm_lib_free_pages(substream);
1372}
1373
a98f90fd 1374static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1375{
1376 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1377 struct azx *chip = apcm->chip;
1378 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1379 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1380 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1381
1382 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1da177e4
LT		 1383 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1384 runtime->channels,
1385 runtime->format,
1386 hinfo->maxbps);
d01ce99f
TI		 1387 if (!azx_dev->format_val) {
1388 snd_printk(KERN_ERR SFX
1389 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1390 runtime->rate, runtime->channels, runtime->format);
1391 return -EINVAL;
1392 }
1393
21c7b081
TI		 1394 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1395 azx_dev->bufsize, azx_dev->format_val);
555e219f 1396 if (azx_setup_periods(chip, substream, azx_dev) < 0)
4ce107b9 1397 return -EINVAL;
1da177e4
LT		 1398 azx_setup_controller(chip, azx_dev);
1399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1400 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1401 else
1402 azx_dev->fifo_size = 0;
1403
1404 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1405 azx_dev->format_val, substream);
1406}
1407
a98f90fd 1408static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1409{
1410 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1411 struct azx *chip = apcm->chip;
850f0e52
TI		 1412 struct azx_dev *azx_dev;
1413 struct snd_pcm_substream *s;
1414 int start, nsync = 0, sbits = 0;
1415 int nwait, timeout;
1da177e4 1416
1da177e4
LT		 1417 switch (cmd) {
1418 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1419 case SNDRV_PCM_TRIGGER_RESUME:
1420 case SNDRV_PCM_TRIGGER_START:
850f0e52 1421 start = 1;
1da177e4
LT		 1422 break;
1423 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1424 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1425 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1426 start = 0;
1da177e4
LT		 1427 break;
1428 default:
850f0e52
TI		 1429 return -EINVAL;
1430 }
1431
1432 snd_pcm_group_for_each_entry(s, substream) {
1433 if (s->pcm->card != substream->pcm->card)
1434 continue;
1435 azx_dev = get_azx_dev(s);
1436 sbits |= 1 << azx_dev->index;
1437 nsync++;
1438 snd_pcm_trigger_done(s, substream);
1439 }
1440
1441 spin_lock(&chip->reg_lock);
1442 if (nsync > 1) {
1443 /* first, set SYNC bits of corresponding streams */
1444 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1445 }
1446 snd_pcm_group_for_each_entry(s, substream) {
1447 if (s->pcm->card != substream->pcm->card)
1448 continue;
1449 azx_dev = get_azx_dev(s);
1450 if (start)
1451 azx_stream_start(chip, azx_dev);
1452 else
1453 azx_stream_stop(chip, azx_dev);
1454 azx_dev->running = start;
1da177e4
LT		 1455 }
1456 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1457 if (start) {
1458 if (nsync == 1)
1459 return 0;
1460 /* wait until all FIFOs get ready */
1461 for (timeout = 5000; timeout; timeout--) {
1462 nwait = 0;
1463 snd_pcm_group_for_each_entry(s, substream) {
1464 if (s->pcm->card != substream->pcm->card)
1465 continue;
1466 azx_dev = get_azx_dev(s);
1467 if (!(azx_sd_readb(azx_dev, SD_STS) &
1468 SD_STS_FIFO_READY))
1469 nwait++;
1470 }
1471 if (!nwait)
1472 break;
1473 cpu_relax();
1474 }
1475 } else {
1476 /* wait until all RUN bits are cleared */
1477 for (timeout = 5000; timeout; timeout--) {
1478 nwait = 0;
1479 snd_pcm_group_for_each_entry(s, substream) {
1480 if (s->pcm->card != substream->pcm->card)
1481 continue;
1482 azx_dev = get_azx_dev(s);
1483 if (azx_sd_readb(azx_dev, SD_CTL) &
1484 SD_CTL_DMA_START)
1485 nwait++;
1486 }
1487 if (!nwait)
1488 break;
1489 cpu_relax();
1490 }
1da177e4 1491 }
850f0e52
TI		 1492 if (nsync > 1) {
1493 spin_lock(&chip->reg_lock);
1494 /* reset SYNC bits */
1495 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1496 spin_unlock(&chip->reg_lock);
1497 }
1498 return 0;
1da177e4
LT		 1499}
1500
9ad593f6
TI		 1501static unsigned int azx_get_position(struct azx *chip,
1502 struct azx_dev *azx_dev)
1da177e4 1503{
1da177e4
LT		 1504 unsigned int pos;
1505
1a56f8d6
TI		 1506 if (chip->position_fix == POS_FIX_POSBUF ||
1507 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1508 /* use the position buffer */
929861c6 1509 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1510 } else {
1511 /* read LPIB */
1512 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1513 }
1da177e4
LT		 1514 if (pos >= azx_dev->bufsize)
1515 pos = 0;
9ad593f6
TI		 1516 return pos;
1517}
1518
1519static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1520{
1521 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1522 struct azx *chip = apcm->chip;
1523 struct azx_dev *azx_dev = get_azx_dev(substream);
1524 return bytes_to_frames(substream->runtime,
1525 azx_get_position(chip, azx_dev));
1526}
1527
1528/*
1529 * Check whether the current DMA position is acceptable for updating
1530 * periods. Returns non-zero if it's OK.
1531 *
1532 * Many HD-audio controllers appear pretty inaccurate about
1533 * the update-IRQ timing. The IRQ is issued before actually the
1534 * data is processed. So, we need to process it afterwords in a
1535 * workqueue.
1536 */
1537static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1538{
1539 unsigned int pos;
1540
1541 pos = azx_get_position(chip, azx_dev);
1542 if (chip->position_fix == POS_FIX_AUTO) {
1543 if (!pos) {
1544 printk(KERN_WARNING
1545 "hda-intel: Invalid position buffer, "
1546 "using LPIB read method instead.\n");
d2e1c973 1547 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1548 pos = azx_get_position(chip, azx_dev);
1549 } else
1550 chip->position_fix = POS_FIX_POSBUF;
1551 }
1552
1553 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1554 return 0; /* NG - it's below the period boundary */
1555 return 1; /* OK, it's fine */
1556}
1557
1558/*
1559 * The work for pending PCM period updates.
1560 */
1561static void azx_irq_pending_work(struct work_struct *work)
1562{
1563 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1564 int i, pending;
1565
a6a950a8
TI		 1566 if (!chip->irq_pending_warned) {
1567 printk(KERN_WARNING
1568 "hda-intel: IRQ timing workaround is activated "
1569 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1570 chip->card->number);
1571 chip->irq_pending_warned = 1;
1572 }
1573
9ad593f6
TI		 1574 for (;;) {
1575 pending = 0;
1576 spin_lock_irq(&chip->reg_lock);
1577 for (i = 0; i < chip->num_streams; i++) {
1578 struct azx_dev *azx_dev = &chip->azx_dev[i];
1579 if (!azx_dev->irq_pending ||
1580 !azx_dev->substream ||
1581 !azx_dev->running)
1582 continue;
1583 if (azx_position_ok(chip, azx_dev)) {
1584 azx_dev->irq_pending = 0;
1585 spin_unlock(&chip->reg_lock);
1586 snd_pcm_period_elapsed(azx_dev->substream);
1587 spin_lock(&chip->reg_lock);
1588 } else
1589 pending++;
1590 }
1591 spin_unlock_irq(&chip->reg_lock);
1592 if (!pending)
1593 return;
1594 cond_resched();
1595 }
1596}
1597
1598/* clear irq_pending flags and assure no on-going workq */
1599static void azx_clear_irq_pending(struct azx *chip)
1600{
1601 int i;
1602
1603 spin_lock_irq(&chip->reg_lock);
1604 for (i = 0; i < chip->num_streams; i++)
1605 chip->azx_dev[i].irq_pending = 0;
1606 spin_unlock_irq(&chip->reg_lock);
1607 flush_scheduled_work();
1da177e4
LT		 1608}
1609
a98f90fd 1610static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1611 .open = azx_pcm_open,
1612 .close = azx_pcm_close,
1613 .ioctl = snd_pcm_lib_ioctl,
1614 .hw_params = azx_pcm_hw_params,
1615 .hw_free = azx_pcm_hw_free,
1616 .prepare = azx_pcm_prepare,
1617 .trigger = azx_pcm_trigger,
1618 .pointer = azx_pcm_pointer,
4ce107b9 1619 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1620};
1621
a98f90fd 1622static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4
LT		 1623{
1624 kfree(pcm->private_data);
1625}
1626
a98f90fd 1627static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
7ba72ba1 1628 struct hda_pcm *cpcm)
1da177e4
LT		 1629{
1630 int err;
a98f90fd 1631 struct snd_pcm *pcm;
1da177e4
LT		 1632 struct azx_pcm *apcm;
1633
e08a007d
TI		 1634 /* if no substreams are defined for both playback and capture,
1635 * it's just a placeholder. ignore it.
1636 */
1637 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1638 return 0;
1639
1da177e4
LT		 1640 snd_assert(cpcm->name, return -EINVAL);
1641
7ba72ba1 1642 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
d01ce99f
TI		 1643 cpcm->stream[0].substreams,
1644 cpcm->stream[1].substreams,
1da177e4
LT		 1645 &pcm);
1646 if (err < 0)
1647 return err;
1648 strcpy(pcm->name, cpcm->name);
1649 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1650 if (apcm == NULL)
1651 return -ENOMEM;
1652 apcm->chip = chip;
1653 apcm->codec = codec;
1654 apcm->hinfo[0] = &cpcm->stream[0];
1655 apcm->hinfo[1] = &cpcm->stream[1];
1656 pcm->private_data = apcm;
1657 pcm->private_free = azx_pcm_free;
1658 if (cpcm->stream[0].substreams)
1659 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1660 if (cpcm->stream[1].substreams)
1661 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
4ce107b9 1662 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1663 snd_dma_pci_data(chip->pci),
b66b3cfe 1664 1024 * 64, 1024 * 1024);
7ba72ba1 1665 chip->pcm[cpcm->device] = pcm;
1da177e4
LT		 1666 return 0;
1667}
1668
a98f90fd 1669static int __devinit azx_pcm_create(struct azx *chip)
1da177e4 1670{
7ba72ba1
TI		 1671 static const char *dev_name[HDA_PCM_NTYPES] = {
1672 "Audio", "SPDIF", "HDMI", "Modem"
1673 };
1674 /* starting device index for each PCM type */
1675 static int dev_idx[HDA_PCM_NTYPES] = {
1676 [HDA_PCM_TYPE_AUDIO] = 0,
1677 [HDA_PCM_TYPE_SPDIF] = 1,
1678 [HDA_PCM_TYPE_HDMI] = 3,
1679 [HDA_PCM_TYPE_MODEM] = 6
1680 };
1681 /* normal audio device indices; not linear to keep compatibility */
1682 static int audio_idx[4] = { 0, 2, 4, 5 };
1da177e4
LT		 1683 struct hda_codec *codec;
1684 int c, err;
7ba72ba1 1685 int num_devs[HDA_PCM_NTYPES];
1da177e4 1686
d01ce99f
TI		 1687 err = snd_hda_build_pcms(chip->bus);
1688 if (err < 0)
1da177e4
LT		 1689 return err;
1690
ec9e1c5c 1691 /* create audio PCMs */
7ba72ba1 1692 memset(num_devs, 0, sizeof(num_devs));
33206e86 1693 list_for_each_entry(codec, &chip->bus->codec_list, list) {
ec9e1c5c 1694 for (c = 0; c < codec->num_pcms; c++) {
7ba72ba1
TI		 1695 struct hda_pcm *cpcm = &codec->pcm_info[c];
1696 int type = cpcm->pcm_type;
1697 switch (type) {
1698 case HDA_PCM_TYPE_AUDIO:
1699 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1700 snd_printk(KERN_WARNING
1701 "Too many audio devices\n");
1702 continue;
1703 }
1704 cpcm->device = audio_idx[num_devs[type]];
1705 break;
1706 case HDA_PCM_TYPE_SPDIF:
1707 case HDA_PCM_TYPE_HDMI:
1708 case HDA_PCM_TYPE_MODEM:
1709 if (num_devs[type]) {
1710 snd_printk(KERN_WARNING
1711 "%s already defined\n",
1712 dev_name[type]);
1713 continue;
1714 }
1715 cpcm->device = dev_idx[type];
1716 break;
1717 default:
1718 snd_printk(KERN_WARNING
1719 "Invalid PCM type %d\n", type);
1720 continue;
1da177e4 1721 }
7ba72ba1
TI		 1722 num_devs[type]++;
1723 err = create_codec_pcm(chip, codec, cpcm);
1da177e4
LT		 1724 if (err < 0)
1725 return err;
1da177e4
LT		 1726 }
1727 }
1728 return 0;
1729}
1730
1731/*
1732 * mixer creation - all stuff is implemented in hda module
1733 */
a98f90fd 1734static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1735{
1736 return snd_hda_build_controls(chip->bus);
1737}
1738
1739
1740/*
1741 * initialize SD streams
1742 */
a98f90fd 1743static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1744{
1745 int i;
1746
1747 /* initialize each stream (aka device)
d01ce99f
TI		 1748 * assign the starting bdl address to each stream (device)
1749 * and initialize
1da177e4 1750 */
07e4ca50 1751 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1752 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1753 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1754 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1755 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1756 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1757 azx_dev->sd_int_sta_mask = 1 << i;
1758 /* stream tag: must be non-zero and unique */
1759 azx_dev->index = i;
1760 azx_dev->stream_tag = i + 1;
1761 }
1762
1763 return 0;
1764}
1765
68e7fffc
TI		 1766static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1767{
437a5a46
TI		 1768 if (request_irq(chip->pci->irq, azx_interrupt,
1769 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1770 "HDA Intel", chip)) {
1771 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1772 "disabling device\n", chip->pci->irq);
1773 if (do_disconnect)
1774 snd_card_disconnect(chip->card);
1775 return -1;
1776 }
1777 chip->irq = chip->pci->irq;
69e13418 1778 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1779 return 0;
1780}
1781
1da177e4 1782
cb53c626
TI		 1783static void azx_stop_chip(struct azx *chip)
1784{
95e99fda 1785 if (!chip->initialized)
cb53c626
TI		 1786 return;
1787
1788 /* disable interrupts */
1789 azx_int_disable(chip);
1790 azx_int_clear(chip);
1791
1792 /* disable CORB/RIRB */
1793 azx_free_cmd_io(chip);
1794
1795 /* disable position buffer */
1796 azx_writel(chip, DPLBASE, 0);
1797 azx_writel(chip, DPUBASE, 0);
1798
1799 chip->initialized = 0;
1800}
1801
1802#ifdef CONFIG_SND_HDA_POWER_SAVE
1803/* power-up/down the controller */
1804static void azx_power_notify(struct hda_codec *codec)
1805{
1806 struct azx *chip = codec->bus->private_data;
1807 struct hda_codec *c;
1808 int power_on = 0;
1809
1810 list_for_each_entry(c, &codec->bus->codec_list, list) {
1811 if (c->power_on) {
1812 power_on = 1;
1813 break;
1814 }
1815 }
1816 if (power_on)
1817 azx_init_chip(chip);
dee1b66c 1818 else if (chip->running && power_save_controller)
cb53c626 1819 azx_stop_chip(chip);
cb53c626
TI		 1820}
1821#endif /* CONFIG_SND_HDA_POWER_SAVE */
1822
1da177e4
LT		 1823#ifdef CONFIG_PM
1824/*
1825 * power management
1826 */
421a1252 1827static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1828{
421a1252
TI		 1829 struct snd_card *card = pci_get_drvdata(pci);
1830 struct azx *chip = card->private_data;
1da177e4
LT		 1831 int i;
1832
421a1252 1833 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1834 azx_clear_irq_pending(chip);
7ba72ba1 1835 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 1836 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI		 1837 if (chip->initialized)
1838 snd_hda_suspend(chip->bus, state);
cb53c626 1839 azx_stop_chip(chip);
30b35399 1840 if (chip->irq >= 0) {
43001c95 1841 free_irq(chip->irq, chip);
30b35399
TI		 1842 chip->irq = -1;
1843 }
68e7fffc 1844 if (chip->msi)
43001c95 1845 pci_disable_msi(chip->pci);
421a1252
TI		 1846 pci_disable_device(pci);
1847 pci_save_state(pci);
30b35399 1848 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1849 return 0;
1850}
1851
421a1252 1852static int azx_resume(struct pci_dev *pci)
1da177e4 1853{
421a1252
TI		 1854 struct snd_card *card = pci_get_drvdata(pci);
1855 struct azx *chip = card->private_data;
1da177e4 1856
30b35399 1857 pci_set_power_state(pci, PCI_D0);
421a1252 1858 pci_restore_state(pci);
30b35399
TI		 1859 if (pci_enable_device(pci) < 0) {
1860 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1861 "disabling device\n");
1862 snd_card_disconnect(card);
1863 return -EIO;
1864 }
1865 pci_set_master(pci);
68e7fffc
TI		 1866 if (chip->msi)
1867 if (pci_enable_msi(pci) < 0)
1868 chip->msi = 0;
1869 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1870 return -EIO;
cb53c626 1871 azx_init_pci(chip);
d804ad92
ML		 1872
1873 if (snd_hda_codecs_inuse(chip->bus))
1874 azx_init_chip(chip);
1875
1da177e4 1876 snd_hda_resume(chip->bus);
421a1252 1877 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1878 return 0;
1879}
1880#endif /* CONFIG_PM */
1881
1882
1883/*
1884 * destructor
1885 */
a98f90fd 1886static int azx_free(struct azx *chip)
1da177e4 1887{
4ce107b9
TI		 1888 int i;
1889
ce43fbae 1890 if (chip->initialized) {
9ad593f6 1891 azx_clear_irq_pending(chip);
07e4ca50 1892 for (i = 0; i < chip->num_streams; i++)
1da177e4 1893 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1894 azx_stop_chip(chip);
1da177e4
LT		 1895 }
1896
f000fd80 1897 if (chip->irq >= 0)
1da177e4 1898 free_irq(chip->irq, (void*)chip);
68e7fffc 1899 if (chip->msi)
30b35399 1900 pci_disable_msi(chip->pci);
f079c25a
TI		 1901 if (chip->remap_addr)
1902 iounmap(chip->remap_addr);
1da177e4 1903
4ce107b9
TI		 1904 if (chip->azx_dev) {
1905 for (i = 0; i < chip->num_streams; i++)
1906 if (chip->azx_dev[i].bdl.area)
1907 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1908 }
1da177e4
LT		 1909 if (chip->rb.area)
1910 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 1911 if (chip->posbuf.area)
1912 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 1913 pci_release_regions(chip->pci);
1914 pci_disable_device(chip->pci);
07e4ca50 1915 kfree(chip->azx_dev);
1da177e4
LT		 1916 kfree(chip);
1917
1918 return 0;
1919}
1920
a98f90fd 1921static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1922{
1923 return azx_free(device->device_data);
1924}
1925
3372a153
TI		 1926/*
1927 * white/black-listing for position_fix
1928 */
623ec047 1929static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 1930 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1931 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1932 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 1933 {}
1934};
1935
1936static int __devinit check_position_fix(struct azx *chip, int fix)
1937{
1938 const struct snd_pci_quirk *q;
1939
1940 if (fix == POS_FIX_AUTO) {
1941 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1942 if (q) {
669ba27a 1943 printk(KERN_INFO
3372a153
TI		 1944 "hda_intel: position_fix set to %d "
1945 "for device %04x:%04x\n",
1946 q->value, q->subvendor, q->subdevice);
1947 return q->value;
1948 }
1949 }
1950 return fix;
1951}
1952
669ba27a
TI		 1953/*
1954 * black-lists for probe_mask
1955 */
1956static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1957 /* Thinkpad often breaks the controller communication when accessing
1958 * to the non-working (or non-existing) modem codec slot.
1959 */
1960 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1961 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1962 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1963 {}
1964};
1965
5aba4f8e 1966static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1967{
1968 const struct snd_pci_quirk *q;
1969
5aba4f8e 1970 if (probe_mask[dev] == -1) {
669ba27a
TI		 1971 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1972 if (q) {
1973 printk(KERN_INFO
1974 "hda_intel: probe_mask set to 0x%x "
1975 "for device %04x:%04x\n",
1976 q->value, q->subvendor, q->subdevice);
5aba4f8e 1977 probe_mask[dev] = q->value;
669ba27a
TI		 1978 }
1979 }
1980}
1981
1982
1da177e4
LT		 1983/*
1984 * constructor
1985 */
a98f90fd 1986static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 1987 int dev, int driver_type,
a98f90fd 1988 struct azx **rchip)
1da177e4 1989{
a98f90fd 1990 struct azx *chip;
4ce107b9 1991 int i, err;
bcd72003 1992 unsigned short gcap;
a98f90fd 1993 static struct snd_device_ops ops = {
1da177e4
LT		 1994 .dev_free = azx_dev_free,
1995 };
1996
1997 *rchip = NULL;
bcd72003 1998
927fc866
PM		 1999 err = pci_enable_device(pci);
2000 if (err < 0)
1da177e4
LT		 2001 return err;
2002
e560d8d8 2003 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2004 if (!chip) {
1da177e4
LT		 2005 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2006 pci_disable_device(pci);
2007 return -ENOMEM;
2008 }
2009
2010 spin_lock_init(&chip->reg_lock);
62932df8 2011 mutex_init(&chip->open_mutex);
1da177e4
LT		 2012 chip->card = card;
2013 chip->pci = pci;
2014 chip->irq = -1;
07e4ca50 2015 chip->driver_type = driver_type;
134a11f0 2016 chip->msi = enable_msi;
555e219f 2017 chip->dev_index = dev;
9ad593f6 2018 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2019
5aba4f8e
TI		 2020 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2021 check_probe_mask(chip, dev);
3372a153 2022
27346166 2023 chip->single_cmd = single_cmd;
c74db86b 2024
5c0d7bc1
TI		 2025 if (bdl_pos_adj[dev] < 0) {
2026 switch (chip->driver_type) {
2027 case AZX_DRIVER_ATI:
2028 case AZX_DRIVER_ATIHDMI:
2029 bdl_pos_adj[dev] = 32;
2030 break;
2031 default:
2032 bdl_pos_adj[dev] = 1;
2033 break;
2034 }
2035 }
2036
07e4ca50
TI		 2037#if BITS_PER_LONG != 64
2038 /* Fix up base address on ULI M5461 */
2039 if (chip->driver_type == AZX_DRIVER_ULI) {
2040 u16 tmp3;
2041 pci_read_config_word(pci, 0x40, &tmp3);
2042 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2043 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2044 }
2045#endif
2046
927fc866
PM		 2047 err = pci_request_regions(pci, "ICH HD audio");
2048 if (err < 0) {
1da177e4
LT		 2049 kfree(chip);
2050 pci_disable_device(pci);
2051 return err;
2052 }
2053
927fc866 2054 chip->addr = pci_resource_start(pci, 0);
1da177e4
LT		 2055 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2056 if (chip->remap_addr == NULL) {
2057 snd_printk(KERN_ERR SFX "ioremap error\n");
2058 err = -ENXIO;
2059 goto errout;
2060 }
2061
68e7fffc
TI		 2062 if (chip->msi)
2063 if (pci_enable_msi(pci) < 0)
2064 chip->msi = 0;
7376d013 2065
68e7fffc 2066 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2067 err = -EBUSY;
2068 goto errout;
2069 }
1da177e4
LT		 2070
2071 pci_set_master(pci);
2072 synchronize_irq(chip->irq);
2073
bcd72003
TD		 2074 gcap = azx_readw(chip, GCAP);
2075 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2076
cf7aaca8
TI		 2077 /* allow 64bit DMA address if supported by H/W */
2078 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2079 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2080
8b6ed8e7
TI		 2081 /* read number of streams from GCAP register instead of using
2082 * hardcoded value
2083 */
2084 chip->capture_streams = (gcap >> 8) & 0x0f;
2085 chip->playback_streams = (gcap >> 12) & 0x0f;
2086 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2087 /* gcap didn't give any info, switching to old method */
2088
2089 switch (chip->driver_type) {
2090 case AZX_DRIVER_ULI:
2091 chip->playback_streams = ULI_NUM_PLAYBACK;
2092 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2093 break;
2094 case AZX_DRIVER_ATIHDMI:
2095 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2096 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003
TD		 2097 break;
2098 default:
2099 chip->playback_streams = ICH6_NUM_PLAYBACK;
2100 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2101 break;
2102 }
07e4ca50 2103 }
8b6ed8e7
TI		 2104 chip->capture_index_offset = 0;
2105 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2106 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2107 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2108 GFP_KERNEL);
927fc866 2109 if (!chip->azx_dev) {
07e4ca50
TI		 2110 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2111 goto errout;
2112 }
2113
4ce107b9
TI		 2114 for (i = 0; i < chip->num_streams; i++) {
2115 /* allocate memory for the BDL for each stream */
2116 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2117 snd_dma_pci_data(chip->pci),
2118 BDL_SIZE, &chip->azx_dev[i].bdl);
2119 if (err < 0) {
2120 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2121 goto errout;
2122 }
1da177e4 2123 }
0be3b5d3 2124 /* allocate memory for the position buffer */
d01ce99f
TI		 2125 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2126 snd_dma_pci_data(chip->pci),
2127 chip->num_streams * 8, &chip->posbuf);
2128 if (err < 0) {
0be3b5d3
TI		 2129 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2130 goto errout;
1da177e4 2131 }
1da177e4 2132 /* allocate CORB/RIRB */
d01ce99f
TI		 2133 if (!chip->single_cmd) {
2134 err = azx_alloc_cmd_io(chip);
2135 if (err < 0)
27346166 2136 goto errout;
d01ce99f 2137 }
1da177e4
LT		 2138
2139 /* initialize streams */
2140 azx_init_stream(chip);
2141
2142 /* initialize chip */
cb53c626 2143 azx_init_pci(chip);
1da177e4
LT		 2144 azx_init_chip(chip);
2145
2146 /* codec detection */
927fc866 2147 if (!chip->codec_mask) {
1da177e4
LT		 2148 snd_printk(KERN_ERR SFX "no codecs found!\n");
2149 err = -ENODEV;
2150 goto errout;
2151 }
2152
d01ce99f
TI		 2153 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2154 if (err <0) {
1da177e4
LT		 2155 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2156 goto errout;
2157 }
2158
07e4ca50
TI		 2159 strcpy(card->driver, "HDA-Intel");
2160 strcpy(card->shortname, driver_short_names[chip->driver_type]);
d01ce99f
TI		 2161 sprintf(card->longname, "%s at 0x%lx irq %i",
2162 card->shortname, chip->addr, chip->irq);
07e4ca50 2163
1da177e4
LT		 2164 *rchip = chip;
2165 return 0;
2166
2167 errout:
2168 azx_free(chip);
2169 return err;
2170}
2171
cb53c626
TI		 2172static void power_down_all_codecs(struct azx *chip)
2173{
2174#ifdef CONFIG_SND_HDA_POWER_SAVE
2175 /* The codecs were powered up in snd_hda_codec_new().
2176 * Now all initialization done, so turn them down if possible
2177 */
2178 struct hda_codec *codec;
2179 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2180 snd_hda_power_down(codec);
2181 }
2182#endif
2183}
2184
d01ce99f
TI		 2185static int __devinit azx_probe(struct pci_dev *pci,
2186 const struct pci_device_id *pci_id)
1da177e4 2187{
5aba4f8e 2188 static int dev;
a98f90fd
TI		 2189 struct snd_card *card;
2190 struct azx *chip;
927fc866 2191 int err;
1da177e4 2192
5aba4f8e
TI		 2193 if (dev >= SNDRV_CARDS)
2194 return -ENODEV;
2195 if (!enable[dev]) {
2196 dev++;
2197 return -ENOENT;
2198 }
2199
2200 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
927fc866 2201 if (!card) {
1da177e4
LT		 2202 snd_printk(KERN_ERR SFX "Error creating card!\n");
2203 return -ENOMEM;
2204 }
2205
5aba4f8e 2206 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
927fc866 2207 if (err < 0) {
1da177e4
LT		 2208 snd_card_free(card);
2209 return err;
2210 }
421a1252 2211 card->private_data = chip;
1da177e4 2212
1da177e4 2213 /* create codec instances */
5aba4f8e 2214 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
d01ce99f 2215 if (err < 0) {
1da177e4
LT		 2216 snd_card_free(card);
2217 return err;
2218 }
2219
2220 /* create PCM streams */
d01ce99f
TI		 2221 err = azx_pcm_create(chip);
2222 if (err < 0) {
1da177e4
LT		 2223 snd_card_free(card);
2224 return err;
2225 }
2226
2227 /* create mixer controls */
d01ce99f
TI		 2228 err = azx_mixer_create(chip);
2229 if (err < 0) {
1da177e4
LT		 2230 snd_card_free(card);
2231 return err;
2232 }
2233
1da177e4
LT		 2234 snd_card_set_dev(card, &pci->dev);
2235
d01ce99f
TI		 2236 err = snd_card_register(card);
2237 if (err < 0) {
1da177e4
LT		 2238 snd_card_free(card);
2239 return err;
2240 }
2241
2242 pci_set_drvdata(pci, card);
cb53c626
TI		 2243 chip->running = 1;
2244 power_down_all_codecs(chip);
1da177e4 2245
e25bcdba 2246 dev++;
1da177e4
LT		 2247 return err;
2248}
2249
2250static void __devexit azx_remove(struct pci_dev *pci)
2251{
2252 snd_card_free(pci_get_drvdata(pci));
2253 pci_set_drvdata(pci, NULL);
2254}
2255
2256/* PCI IDs */
f40b6890 2257static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2258 /* ICH 6..10 */
2259 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2260 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2261 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2262 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2263 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2264 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2265 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2266 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2267 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2268 /* SCH */
2269 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2270 /* ATI SB 450/600 */
2271 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2272 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2273 /* ATI HDMI */
2274 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2275 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2276 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2277 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2278 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2279 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2280 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2281 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2282 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2283 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2284 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2285 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2286 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2287 /* VIA VT8251/VT8237A */
2288 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2289 /* SIS966 */
2290 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2291 /* ULI M5461 */
2292 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2293 /* NVIDIA MCP */
2294 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2295 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2296 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2297 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2298 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2299 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2300 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2301 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2302 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2303 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2304 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2305 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2306 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2307 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2308 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2309 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2310 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2311 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
487145a1
PC		 2312 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2313 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2314 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2315 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2316 /* Teradici */
2317 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
1da177e4
LT		 2318 { 0, }
2319};
2320MODULE_DEVICE_TABLE(pci, azx_ids);
2321
2322/* pci_driver definition */
2323static struct pci_driver driver = {
2324 .name = "HDA Intel",
2325 .id_table = azx_ids,
2326 .probe = azx_probe,
2327 .remove = __devexit_p(azx_remove),
421a1252
TI		 2328#ifdef CONFIG_PM
2329 .suspend = azx_suspend,
2330 .resume = azx_resume,
2331#endif
1da177e4
LT		 2332};
2333
2334static int __init alsa_card_azx_init(void)
2335{
01d25d46 2336 return pci_register_driver(&driver);
1da177e4
LT		 2337}
2338
2339static void __exit alsa_card_azx_exit(void)
2340{
2341 pci_unregister_driver(&driver);
2342}
2343
2344module_init(alsa_card_azx_init)
2345module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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