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Merge branch 'kirkwood/boards' of git://git.infradead.org/users/jcooper/linux into...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9
TI		 48#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
1da177e4
LT		 54#include <sound/core.h>
55#include <sound/initval.h>
9121947d 56#include <linux/vgaarb.h>
a82d51ed 57#include <linux/vga_switcheroo.h>
1da177e4
LT		 58#include "hda_codec.h"
59
60
5aba4f8e
TI		 61static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 63static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 64static char *model[SNDRV_CARDS];
65static int position_fix[SNDRV_CARDS];
5c0d7bc1 66static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 67static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 68static int probe_only[SNDRV_CARDS];
a67ff6a5 69static bool single_cmd;
71623855 70static int enable_msi = -1;
4ea6fbc8
TI		 71#ifdef CONFIG_SND_HDA_PATCH_LOADER
72static char *patch[SNDRV_CARDS];
73#endif
2dca0bba 74#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 75static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
77#endif
1da177e4 78
5aba4f8e 79module_param_array(index, int, NULL, 0444);
1da177e4 80MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 81module_param_array(id, charp, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85module_param_array(model, charp, NULL, 0444);
1da177e4 86MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 87module_param_array(position_fix, int, NULL, 0444);
4cb36310 88MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 90module_param_array(bdl_pos_adj, int, NULL, 0644);
91MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 92module_param_array(probe_mask, int, NULL, 0444);
606ad75f 93MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 94module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 95MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 96module_param(single_cmd, bool, 0444);
d01ce99f
TI		 97MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
ac9ef6cf 99module_param(enable_msi, bint, 0444);
134a11f0 100MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 101#ifdef CONFIG_SND_HDA_PATCH_LOADER
102module_param_array(patch, charp, NULL, 0444);
103MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
104#endif
2dca0bba 105#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 106module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 107MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 108 "(0=off, 1=on) (default=1).");
2dca0bba 109#endif
606ad75f 110
dee1b66c 111#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 112static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113module_param(power_save, int, 0644);
114MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
1da177e4 116
dee1b66c
TI		 117/* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
119 * wake up.
120 */
a67ff6a5 121static bool power_save_controller = 1;
dee1b66c
TI		 122module_param(power_save_controller, bool, 0644);
123MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
124#endif
125
7bfe059e
TI		 126static int align_buffer_size = -1;
127module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 128MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
130
27fe48d9
TI		 131#ifdef CONFIG_X86
132static bool hda_snoop = true;
133module_param_named(snoop, hda_snoop, bool, 0444);
134MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135#define azx_snoop(chip) (chip)->snoop
136#else
137#define hda_snoop true
138#define azx_snoop(chip) true
139#endif
140
141
1da177e4
LT		 142MODULE_LICENSE("GPL");
143MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
144 "{Intel, ICH6M},"
2f1b3818 145 "{Intel, ICH7},"
f5d40b30 146 "{Intel, ESB2},"
d2981393 147 "{Intel, ICH8},"
f9cc8a8b 148 "{Intel, ICH9},"
c34f5a04 149 "{Intel, ICH10},"
b29c2360 150 "{Intel, PCH},"
d2f2fcd2 151 "{Intel, CPT},"
d2edeb7c 152 "{Intel, PPT},"
8bc039a1 153 "{Intel, LPT},"
144dad99 154 "{Intel, LPT_LP},"
e926f2c8 155 "{Intel, HPT},"
cea310e8 156 "{Intel, PBG},"
4979bca9 157 "{Intel, SCH},"
fc20a562 158 "{ATI, SB450},"
89be83f8 159 "{ATI, SB600},"
778b6e1b 160 "{ATI, RS600},"
5b15c95f 161 "{ATI, RS690},"
e6db1119
WL		 162 "{ATI, RS780},"
163 "{ATI, R600},"
2797f724
HRK		 164 "{ATI, RV630},"
165 "{ATI, RV610},"
27da1834
WL		 166 "{ATI, RV670},"
167 "{ATI, RV635},"
168 "{ATI, RV620},"
169 "{ATI, RV770},"
fc20a562 170 "{VIA, VT8251},"
47672310 171 "{VIA, VT8237A},"
07e4ca50
TI		 172 "{SiS, SIS966},"
173 "{ULI, M5461}}");
1da177e4
LT		 174MODULE_DESCRIPTION("Intel HDA driver");
175
4abc1cc2
TI		 176#ifdef CONFIG_SND_VERBOSE_PRINTK
177#define SFX /* nop */
178#else
1da177e4 179#define SFX "hda-intel: "
4abc1cc2 180#endif
cb53c626 181
a82d51ed
TI		 182#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
183#ifdef CONFIG_SND_HDA_CODEC_HDMI
184#define SUPPORT_VGA_SWITCHEROO
185#endif
186#endif
187
188
1da177e4
LT		 189/*
190 * registers
191 */
192#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 193#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
194#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
195#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
196#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
197#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 198#define ICH6_REG_VMIN 0x02
199#define ICH6_REG_VMAJ 0x03
200#define ICH6_REG_OUTPAY 0x04
201#define ICH6_REG_INPAY 0x06
202#define ICH6_REG_GCTL 0x08
8a933ece 203#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 204#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
205#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 206#define ICH6_REG_WAKEEN 0x0c
207#define ICH6_REG_STATESTS 0x0e
208#define ICH6_REG_GSTS 0x10
b21fadb9 209#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 210#define ICH6_REG_INTCTL 0x20
211#define ICH6_REG_INTSTS 0x24
e5463720 212#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 213#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
214#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 215#define ICH6_REG_CORBLBASE 0x40
216#define ICH6_REG_CORBUBASE 0x44
217#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 218#define ICH6_REG_CORBRP 0x4a
219#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 220#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 221#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
222#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 223#define ICH6_REG_CORBSTS 0x4d
b21fadb9 224#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 225#define ICH6_REG_CORBSIZE 0x4e
226
227#define ICH6_REG_RIRBLBASE 0x50
228#define ICH6_REG_RIRBUBASE 0x54
229#define ICH6_REG_RIRBWP 0x58
b21fadb9 230#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 231#define ICH6_REG_RINTCNT 0x5a
232#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 233#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
234#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
235#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 236#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 237#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
238#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 239#define ICH6_REG_RIRBSIZE 0x5e
240
241#define ICH6_REG_IC 0x60
242#define ICH6_REG_IR 0x64
243#define ICH6_REG_IRS 0x68
244#define ICH6_IRS_VALID (1<<1)
245#define ICH6_IRS_BUSY (1<<0)
246
247#define ICH6_REG_DPLBASE 0x70
248#define ICH6_REG_DPUBASE 0x74
249#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
250
251/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
252enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
253
254/* stream register offsets from stream base */
255#define ICH6_REG_SD_CTL 0x00
256#define ICH6_REG_SD_STS 0x03
257#define ICH6_REG_SD_LPIB 0x04
258#define ICH6_REG_SD_CBL 0x08
259#define ICH6_REG_SD_LVI 0x0c
260#define ICH6_REG_SD_FIFOW 0x0e
261#define ICH6_REG_SD_FIFOSIZE 0x10
262#define ICH6_REG_SD_FORMAT 0x12
263#define ICH6_REG_SD_BDLPL 0x18
264#define ICH6_REG_SD_BDLPU 0x1c
265
266/* PCI space */
267#define ICH6_PCIREG_TCSEL 0x44
268
269/*
270 * other constants
271 */
272
273/* max number of SDs */
07e4ca50 274/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 275#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 276#define ICH6_NUM_PLAYBACK 4
277
278/* ULI has 6 playback and 5 capture */
07e4ca50 279#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 280#define ULI_NUM_PLAYBACK 6
281
778b6e1b 282/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 283#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 284#define ATIHDMI_NUM_PLAYBACK 1
285
f269002e
KY		 286/* TERA has 4 playback and 3 capture */
287#define TERA_NUM_CAPTURE 3
288#define TERA_NUM_PLAYBACK 4
289
07e4ca50
TI		 290/* this number is statically defined for simplicity */
291#define MAX_AZX_DEV 16
292
1da177e4 293/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 294#define BDL_SIZE 4096
295#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
296#define AZX_MAX_FRAG 32
1da177e4
LT		 297/* max buffer size - no h/w limit, you can increase as you like */
298#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 299
300/* RIRB int mask: overrun[2], response[0] */
301#define RIRB_INT_RESPONSE 0x01
302#define RIRB_INT_OVERRUN 0x04
303#define RIRB_INT_MASK 0x05
304
2f5983f2 305/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 306#define AZX_MAX_CODECS 8
307#define AZX_DEFAULT_CODECS 4
deadff16 308#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 309
310/* SD_CTL bits */
311#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
312#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 313#define SD_CTL_STRIPE (3 << 16) /* stripe control */
314#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
315#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 316#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
317#define SD_CTL_STREAM_TAG_SHIFT 20
318
319/* SD_CTL and SD_STS */
320#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
321#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
322#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 323#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
324 SD_INT_COMPLETE)
1da177e4
LT		 325
326/* SD_STS */
327#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
328
329/* INTCTL and INTSTS */
d01ce99f
TI		 330#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
331#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
332#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 333
1da177e4
LT		 334/* below are so far hardcoded - should read registers in future */
335#define ICH6_MAX_CORB_ENTRIES 256
336#define ICH6_MAX_RIRB_ENTRIES 256
337
c74db86b
TI		 338/* position fix mode */
339enum {
0be3b5d3 340 POS_FIX_AUTO,
d2e1c973 341 POS_FIX_LPIB,
0be3b5d3 342 POS_FIX_POSBUF,
4cb36310 343 POS_FIX_VIACOMBO,
a6f2fd55 344 POS_FIX_COMBO,
c74db86b 345};
1da177e4 346
f5d40b30 347/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 348#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
349#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
350
da3fca21
V		 351/* Defines for Nvidia HDA support */
352#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
353#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 354#define NVIDIA_HDA_ISTRM_COH 0x4d
355#define NVIDIA_HDA_OSTRM_COH 0x4c
356#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 357
90a5ad52
TI		 358/* Defines for Intel SCH HDA snoop control */
359#define INTEL_SCH_HDA_DEVC 0x78
360#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
361
0e153474
JC		 362/* Define IN stream 0 FIFO size offset in VIA controller */
363#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
364/* Define VIA HD Audio Device ID*/
365#define VIA_HDAC_DEVICE_ID 0x3288
366
c4da29ca
YL		 367/* HD Audio class code */
368#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 369
1da177e4
LT		 370/*
371 */
372
a98f90fd 373struct azx_dev {
4ce107b9 374 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 375 u32 *posbuf; /* position buffer pointer */
1da177e4 376
d01ce99f 377 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 378 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 379 unsigned int frags; /* number for period in the play buffer */
380 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 381 unsigned long start_wallclk; /* start + minimum wallclk */
382 unsigned long period_wallclk; /* wallclk for period */
1da177e4 383
d01ce99f 384 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 385
d01ce99f 386 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 387
388 /* pcm support */
d01ce99f
TI		 389 struct snd_pcm_substream *substream; /* assigned substream,
390 * set in PCM open
391 */
392 unsigned int format_val; /* format value to be set in the
393 * controller and the codec
394 */
1da177e4
LT		 395 unsigned char stream_tag; /* assigned stream */
396 unsigned char index; /* stream index */
d5cf9911 397 int assigned_key; /* last device# key assigned to */
1da177e4 398
927fc866
PM		 399 unsigned int opened :1;
400 unsigned int running :1;
675f25d4 401 unsigned int irq_pending :1;
0e153474
JC		 402 /*
403 * For VIA:
404 * A flag to ensure DMA position is 0
405 * when link position is not greater than FIFO size
406 */
407 unsigned int insufficient :1;
27fe48d9 408 unsigned int wc_marked:1;
1da177e4
LT		 409};
410
411/* CORB/RIRB */
a98f90fd 412struct azx_rb {
1da177e4
LT		 413 u32 *buf; /* CORB/RIRB buffer
414 * Each CORB entry is 4byte, RIRB is 8byte
415 */
416 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
417 /* for RIRB */
418 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 419 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
420 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 421};
422
01b65bfb
TI		 423struct azx_pcm {
424 struct azx *chip;
425 struct snd_pcm *pcm;
426 struct hda_codec *codec;
427 struct hda_pcm_stream *hinfo[2];
428 struct list_head list;
429};
430
a98f90fd
TI		 431struct azx {
432 struct snd_card *card;
1da177e4 433 struct pci_dev *pci;
555e219f 434 int dev_index;
1da177e4 435
07e4ca50
TI		 436 /* chip type specific */
437 int driver_type;
9477c58e 438 unsigned int driver_caps;
07e4ca50
TI		 439 int playback_streams;
440 int playback_index_offset;
441 int capture_streams;
442 int capture_index_offset;
443 int num_streams;
444
1da177e4
LT		 445 /* pci resources */
446 unsigned long addr;
447 void __iomem *remap_addr;
448 int irq;
449
450 /* locks */
451 spinlock_t reg_lock;
62932df8 452 struct mutex open_mutex;
1da177e4 453
07e4ca50 454 /* streams (x num_streams) */
a98f90fd 455 struct azx_dev *azx_dev;
1da177e4
LT		 456
457 /* PCM */
01b65bfb 458 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 459
460 /* HD codec */
461 unsigned short codec_mask;
f1eaaeec 462 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 463 struct hda_bus *bus;
2dca0bba 464 unsigned int beep_mode;
1da177e4
LT		 465
466 /* CORB/RIRB */
a98f90fd
TI		 467 struct azx_rb corb;
468 struct azx_rb rirb;
1da177e4 469
4ce107b9 470 /* CORB/RIRB and position buffers */
1da177e4
LT		 471 struct snd_dma_buffer rb;
472 struct snd_dma_buffer posbuf;
c74db86b
TI		 473
474 /* flags */
beaffc39 475 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 476 int poll_count;
cb53c626 477 unsigned int running :1;
927fc866
PM		 478 unsigned int initialized :1;
479 unsigned int single_cmd :1;
480 unsigned int polling_mode :1;
68e7fffc 481 unsigned int msi :1;
a6a950a8 482 unsigned int irq_pending_warned :1;
6ce4a3bc 483 unsigned int probing :1; /* codec probing phase */
27fe48d9 484 unsigned int snoop:1;
52409aa6 485 unsigned int align_buffer_size:1;
a82d51ed
TI		 486 unsigned int region_requested:1;
487
488 /* VGA-switcheroo setup */
489 unsigned int use_vga_switcheroo:1;
490 unsigned int init_failed:1; /* delayed init failed */
491 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 492
493 /* for debugging */
feb27340 494 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 495
496 /* for pending irqs */
497 struct work_struct irq_pending_work;
0cbf0098
TI		 498
499 /* reboot notifier (for mysterious hangup problem at power-down) */
500 struct notifier_block reboot_notifier;
1da177e4
LT		 501};
502
07e4ca50
TI		 503/* driver types */
504enum {
505 AZX_DRIVER_ICH,
32679f95 506 AZX_DRIVER_PCH,
4979bca9 507 AZX_DRIVER_SCH,
07e4ca50 508 AZX_DRIVER_ATI,
778b6e1b 509 AZX_DRIVER_ATIHDMI,
1815b34a 510 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 511 AZX_DRIVER_VIA,
512 AZX_DRIVER_SIS,
513 AZX_DRIVER_ULI,
da3fca21 514 AZX_DRIVER_NVIDIA,
f269002e 515 AZX_DRIVER_TERA,
14d34f16 516 AZX_DRIVER_CTX,
5ae763b1 517 AZX_DRIVER_CTHDA,
c4da29ca 518 AZX_DRIVER_GENERIC,
2f5983f2 519 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 520};
521
9477c58e
TI		 522/* driver quirks (capabilities) */
523/* bits 0-7 are used for indicating driver type */
524#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
525#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
526#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
527#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
528#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
529#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
530#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
531#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
532#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
533#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
534#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
535#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 536#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 537#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 538#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 539#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
c20c5a84 540#define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
9477c58e
TI		 541
542/* quirks for ATI SB / AMD Hudson */
543#define AZX_DCAPS_PRESET_ATI_SB \
544 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
545 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
546
547/* quirks for ATI/AMD HDMI */
548#define AZX_DCAPS_PRESET_ATI_HDMI \
549 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
550
551/* quirks for Nvidia */
552#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 553 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
554 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 555
5ae763b1
TI		 556#define AZX_DCAPS_PRESET_CTHDA \
557 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
558
a82d51ed
TI		 559/*
560 * VGA-switcher support
561 */
562#ifdef SUPPORT_VGA_SWITCHEROO
563#define DELAYED_INIT_MARK
564#define DELAYED_INITDATA_MARK
565#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
566#else
567#define DELAYED_INIT_MARK __devinit
568#define DELAYED_INITDATA_MARK __devinitdata
569#define use_vga_switcheroo(chip) 0
570#endif
571
572static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 573 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 574 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 575 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 576 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 577 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 578 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 579 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
580 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 581 [AZX_DRIVER_ULI] = "HDA ULI M5461",
582 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 583 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 584 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 585 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 586 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 587};
588
1da177e4
LT		 589/*
590 * macros for easy use
591 */
592#define azx_writel(chip,reg,value) \
593 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
594#define azx_readl(chip,reg) \
595 readl((chip)->remap_addr + ICH6_REG_##reg)
596#define azx_writew(chip,reg,value) \
597 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
598#define azx_readw(chip,reg) \
599 readw((chip)->remap_addr + ICH6_REG_##reg)
600#define azx_writeb(chip,reg,value) \
601 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
602#define azx_readb(chip,reg) \
603 readb((chip)->remap_addr + ICH6_REG_##reg)
604
605#define azx_sd_writel(dev,reg,value) \
606 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
607#define azx_sd_readl(dev,reg) \
608 readl((dev)->sd_addr + ICH6_REG_##reg)
609#define azx_sd_writew(dev,reg,value) \
610 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
611#define azx_sd_readw(dev,reg) \
612 readw((dev)->sd_addr + ICH6_REG_##reg)
613#define azx_sd_writeb(dev,reg,value) \
614 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
615#define azx_sd_readb(dev,reg) \
616 readb((dev)->sd_addr + ICH6_REG_##reg)
617
618/* for pcm support */
a98f90fd 619#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 620
27fe48d9
TI		 621#ifdef CONFIG_X86
622static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
623{
624 if (azx_snoop(chip))
625 return;
626 if (addr && size) {
627 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
628 if (on)
629 set_memory_wc((unsigned long)addr, pages);
630 else
631 set_memory_wb((unsigned long)addr, pages);
632 }
633}
634
635static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
636 bool on)
637{
638 __mark_pages_wc(chip, buf->area, buf->bytes, on);
639}
640static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
641 struct snd_pcm_runtime *runtime, bool on)
642{
643 if (azx_dev->wc_marked != on) {
644 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
645 azx_dev->wc_marked = on;
646 }
647}
648#else
649/* NOP for other archs */
650static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
651 bool on)
652{
653}
654static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
655 struct snd_pcm_runtime *runtime, bool on)
656{
657}
658#endif
659
68e7fffc 660static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 661static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 662/*
663 * Interface for HD codec
664 */
665
1da177e4
LT		 666/*
667 * CORB / RIRB interface
668 */
a98f90fd 669static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 670{
671 int err;
672
673 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 674 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
675 snd_dma_pci_data(chip->pci),
1da177e4
LT		 676 PAGE_SIZE, &chip->rb);
677 if (err < 0) {
678 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
679 return err;
680 }
27fe48d9 681 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 682 return 0;
683}
684
a98f90fd 685static void azx_init_cmd_io(struct azx *chip)
1da177e4 686{
cdb1fbf2 687 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 688 /* CORB set up */
689 chip->corb.addr = chip->rb.addr;
690 chip->corb.buf = (u32 *)chip->rb.area;
691 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 692 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 693
07e4ca50
TI		 694 /* set the corb size to 256 entries (ULI requires explicitly) */
695 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 696 /* set the corb write pointer to 0 */
697 azx_writew(chip, CORBWP, 0);
698 /* reset the corb hw read pointer */
b21fadb9 699 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 700 /* enable corb dma */
b21fadb9 701 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 702
703 /* RIRB set up */
704 chip->rirb.addr = chip->rb.addr + 2048;
705 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 706 chip->rirb.wp = chip->rirb.rp = 0;
707 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 708 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 709 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 710
07e4ca50
TI		 711 /* set the rirb size to 256 entries (ULI requires explicitly) */
712 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 713 /* reset the rirb hw write pointer */
b21fadb9 714 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 715 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 716 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 717 azx_writew(chip, RINTCNT, 0xc0);
718 else
719 azx_writew(chip, RINTCNT, 1);
1da177e4 720 /* enable rirb dma and response irq */
1da177e4 721 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 722 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 723}
724
a98f90fd 725static void azx_free_cmd_io(struct azx *chip)
1da177e4 726{
cdb1fbf2 727 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 728 /* disable ringbuffer DMAs */
729 azx_writeb(chip, RIRBCTL, 0);
730 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 731 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 732}
733
deadff16
WF		 734static unsigned int azx_command_addr(u32 cmd)
735{
736 unsigned int addr = cmd >> 28;
737
738 if (addr >= AZX_MAX_CODECS) {
739 snd_BUG();
740 addr = 0;
741 }
742
743 return addr;
744}
745
746static unsigned int azx_response_addr(u32 res)
747{
748 unsigned int addr = res & 0xf;
749
750 if (addr >= AZX_MAX_CODECS) {
751 snd_BUG();
752 addr = 0;
753 }
754
755 return addr;
1da177e4
LT		 756}
757
758/* send a command */
33fa35ed 759static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 760{
33fa35ed 761 struct azx *chip = bus->private_data;
deadff16 762 unsigned int addr = azx_command_addr(val);
1da177e4 763 unsigned int wp;
1da177e4 764
c32649fe
WF		 765 spin_lock_irq(&chip->reg_lock);
766
1da177e4
LT		 767 /* add command to corb */
768 wp = azx_readb(chip, CORBWP);
769 wp++;
770 wp %= ICH6_MAX_CORB_ENTRIES;
771
deadff16 772 chip->rirb.cmds[addr]++;
1da177e4
LT		 773 chip->corb.buf[wp] = cpu_to_le32(val);
774 azx_writel(chip, CORBWP, wp);
c32649fe 775
1da177e4
LT		 776 spin_unlock_irq(&chip->reg_lock);
777
778 return 0;
779}
780
781#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
782
783/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 784static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 785{
786 unsigned int rp, wp;
deadff16 787 unsigned int addr;
1da177e4
LT		 788 u32 res, res_ex;
789
790 wp = azx_readb(chip, RIRBWP);
791 if (wp == chip->rirb.wp)
792 return;
793 chip->rirb.wp = wp;
deadff16 794
1da177e4
LT		 795 while (chip->rirb.rp != wp) {
796 chip->rirb.rp++;
797 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
798
799 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
800 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
801 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 802 addr = azx_response_addr(res_ex);
1da177e4
LT		 803 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
804 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 805 else if (chip->rirb.cmds[addr]) {
806 chip->rirb.res[addr] = res;
2add9b92 807 smp_wmb();
deadff16 808 chip->rirb.cmds[addr]--;
e310bb06
WF		 809 } else
810 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
811 "last cmd=%#08x\n",
812 res, res_ex,
813 chip->last_cmd[addr]);
1da177e4
LT		 814 }
815}
816
817/* receive a response */
deadff16
WF		 818static unsigned int azx_rirb_get_response(struct hda_bus *bus,
819 unsigned int addr)
1da177e4 820{
33fa35ed 821 struct azx *chip = bus->private_data;
5c79b1f8 822 unsigned long timeout;
32cf4023 823 unsigned long loopcounter;
1eb6dc7d 824 int do_poll = 0;
1da177e4 825
5c79b1f8
TI		 826 again:
827 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 828
829 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 830 if (chip->polling_mode || do_poll) {
e96224ae
TI		 831 spin_lock_irq(&chip->reg_lock);
832 azx_update_rirb(chip);
833 spin_unlock_irq(&chip->reg_lock);
834 }
deadff16 835 if (!chip->rirb.cmds[addr]) {
2add9b92 836 smp_rmb();
b613291f 837 bus->rirb_error = 0;
1eb6dc7d
ML		 838
839 if (!do_poll)
840 chip->poll_count = 0;
deadff16 841 return chip->rirb.res[addr]; /* the last value */
2add9b92 842 }
28a0d9df
TI		 843 if (time_after(jiffies, timeout))
844 break;
32cf4023 845 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 846 msleep(2); /* temporary workaround */
847 else {
848 udelay(10);
849 cond_resched();
850 }
28a0d9df 851 }
5c79b1f8 852
1eb6dc7d
ML		 853 if (!chip->polling_mode && chip->poll_count < 2) {
854 snd_printdd(SFX "azx_get_response timeout, "
855 "polling the codec once: last cmd=0x%08x\n",
856 chip->last_cmd[addr]);
857 do_poll = 1;
858 chip->poll_count++;
859 goto again;
860 }
861
862
23c4a881
TI		 863 if (!chip->polling_mode) {
864 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
865 "switching to polling mode: last cmd=0x%08x\n",
866 chip->last_cmd[addr]);
867 chip->polling_mode = 1;
868 goto again;
869 }
870
68e7fffc 871 if (chip->msi) {
4abc1cc2 872 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 873 "disabling MSI: last cmd=0x%08x\n",
874 chip->last_cmd[addr]);
68e7fffc
TI		 875 free_irq(chip->irq, chip);
876 chip->irq = -1;
877 pci_disable_msi(chip->pci);
878 chip->msi = 0;
b613291f
TI		 879 if (azx_acquire_irq(chip, 1) < 0) {
880 bus->rirb_error = 1;
68e7fffc 881 return -1;
b613291f 882 }
68e7fffc
TI		 883 goto again;
884 }
885
6ce4a3bc
TI		 886 if (chip->probing) {
887 /* If this critical timeout happens during the codec probing
888 * phase, this is likely an access to a non-existing codec
889 * slot. Better to return an error and reset the system.
890 */
891 return -1;
892 }
893
8dd78330
TI		 894 /* a fatal communication error; need either to reset or to fallback
895 * to the single_cmd mode
896 */
b613291f 897 bus->rirb_error = 1;
b20f3b83 898 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 899 bus->response_reset = 1;
900 return -1; /* give a chance to retry */
901 }
902
903 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
904 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 905 chip->last_cmd[addr]);
8dd78330
TI		 906 chip->single_cmd = 1;
907 bus->response_reset = 0;
1a696978 908 /* release CORB/RIRB */
4fcd3920 909 azx_free_cmd_io(chip);
1a696978
TI		 910 /* disable unsolicited responses */
911 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 912 return -1;
1da177e4
LT		 913}
914
1da177e4
LT		 915/*
916 * Use the single immediate command instead of CORB/RIRB for simplicity
917 *
918 * Note: according to Intel, this is not preferred use. The command was
919 * intended for the BIOS only, and may get confused with unsolicited
920 * responses. So, we shouldn't use it for normal operation from the
921 * driver.
922 * I left the codes, however, for debugging/testing purposes.
923 */
924
b05a7d4f 925/* receive a response */
deadff16 926static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 927{
928 int timeout = 50;
929
930 while (timeout--) {
931 /* check IRV busy bit */
932 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
933 /* reuse rirb.res as the response return value */
deadff16 934 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 935 return 0;
936 }
937 udelay(1);
938 }
939 if (printk_ratelimit())
940 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
941 azx_readw(chip, IRS));
deadff16 942 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 943 return -EIO;
944}
945
1da177e4 946/* send a command */
33fa35ed 947static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 948{
33fa35ed 949 struct azx *chip = bus->private_data;
deadff16 950 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 951 int timeout = 50;
952
8dd78330 953 bus->rirb_error = 0;
1da177e4
LT		 954 while (timeout--) {
955 /* check ICB busy bit */
d01ce99f 956 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 957 /* Clear IRV valid bit */
d01ce99f
TI		 958 azx_writew(chip, IRS, azx_readw(chip, IRS) |
959 ICH6_IRS_VALID);
1da177e4 960 azx_writel(chip, IC, val);
d01ce99f
TI		 961 azx_writew(chip, IRS, azx_readw(chip, IRS) |
962 ICH6_IRS_BUSY);
deadff16 963 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 964 }
965 udelay(1);
966 }
1cfd52bc
MB		 967 if (printk_ratelimit())
968 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
969 azx_readw(chip, IRS), val);
1da177e4
LT		 970 return -EIO;
971}
972
973/* receive a response */
deadff16
WF		 974static unsigned int azx_single_get_response(struct hda_bus *bus,
975 unsigned int addr)
1da177e4 976{
33fa35ed 977 struct azx *chip = bus->private_data;
deadff16 978 return chip->rirb.res[addr];
1da177e4
LT		 979}
980
111d3af5
TI		 981/*
982 * The below are the main callbacks from hda_codec.
983 *
984 * They are just the skeleton to call sub-callbacks according to the
985 * current setting of chip->single_cmd.
986 */
987
988/* send a command */
33fa35ed 989static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 990{
33fa35ed 991 struct azx *chip = bus->private_data;
43bbb6cc 992
a82d51ed
TI		 993 if (chip->disabled)
994 return 0;
feb27340 995 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 996 if (chip->single_cmd)
33fa35ed 997 return azx_single_send_cmd(bus, val);
111d3af5 998 else
33fa35ed 999 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1000}
1001
1002/* get a response */
deadff16
WF		 1003static unsigned int azx_get_response(struct hda_bus *bus,
1004 unsigned int addr)
111d3af5 1005{
33fa35ed 1006 struct azx *chip = bus->private_data;
a82d51ed
TI		 1007 if (chip->disabled)
1008 return 0;
111d3af5 1009 if (chip->single_cmd)
deadff16 1010 return azx_single_get_response(bus, addr);
111d3af5 1011 else
deadff16 1012 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1013}
1014
cb53c626 1015#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 1016static void azx_power_notify(struct hda_bus *bus);
cb53c626 1017#endif
111d3af5 1018
1da177e4 1019/* reset codec link */
cd508fe5 1020static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1021{
1022 int count;
1023
cd508fe5
JK		 1024 if (!full_reset)
1025 goto __skip;
1026
e8a7f136
DT		 1027 /* clear STATESTS */
1028 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1029
1da177e4
LT		 1030 /* reset controller */
1031 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1032
1033 count = 50;
1034 while (azx_readb(chip, GCTL) && --count)
1035 msleep(1);
1036
1037 /* delay for >= 100us for codec PLL to settle per spec
1038 * Rev 0.9 section 5.5.1
1039 */
1040 msleep(1);
1041
1042 /* Bring controller out of reset */
1043 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1044
1045 count = 50;
927fc866 1046 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1047 msleep(1);
1048
927fc866 1049 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1050 msleep(1);
1051
cd508fe5 1052 __skip:
1da177e4 1053 /* check to see if controller is ready */
927fc866 1054 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1055 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1056 return -EBUSY;
1057 }
1058
41e2fce4 1059 /* Accept unsolicited responses */
1a696978
TI		 1060 if (!chip->single_cmd)
1061 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1062 ICH6_GCTL_UNSOL);
41e2fce4 1063
1da177e4 1064 /* detect codecs */
927fc866 1065 if (!chip->codec_mask) {
1da177e4 1066 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1067 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1068 }
1069
1070 return 0;
1071}
1072
1073
1074/*
1075 * Lowlevel interface
1076 */
1077
1078/* enable interrupts */
a98f90fd 1079static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1080{
1081 /* enable controller CIE and GIE */
1082 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1083 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1084}
1085
1086/* disable interrupts */
a98f90fd 1087static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1088{
1089 int i;
1090
1091 /* disable interrupts in stream descriptor */
07e4ca50 1092 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1093 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1094 azx_sd_writeb(azx_dev, SD_CTL,
1095 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1096 }
1097
1098 /* disable SIE for all streams */
1099 azx_writeb(chip, INTCTL, 0);
1100
1101 /* disable controller CIE and GIE */
1102 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1103 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1104}
1105
1106/* clear interrupts */
a98f90fd 1107static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1108{
1109 int i;
1110
1111 /* clear stream status */
07e4ca50 1112 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1113 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1114 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1115 }
1116
1117 /* clear STATESTS */
1118 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1119
1120 /* clear rirb status */
1121 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1122
1123 /* clear int status */
1124 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1125}
1126
1127/* start a stream */
a98f90fd 1128static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1129{
0e153474
JC		 1130 /*
1131 * Before stream start, initialize parameter
1132 */
1133 azx_dev->insufficient = 1;
1134
1da177e4 1135 /* enable SIE */
ccc5df05
WN		 1136 azx_writel(chip, INTCTL,
1137 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1138 /* set DMA start and interrupt mask */
1139 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1140 SD_CTL_DMA_START | SD_INT_MASK);
1141}
1142
1dddab40
TI		 1143/* stop DMA */
1144static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1145{
1da177e4
LT		 1146 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1147 ~(SD_CTL_DMA_START | SD_INT_MASK));
1148 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1149}
1150
1151/* stop a stream */
1152static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1153{
1154 azx_stream_clear(chip, azx_dev);
1da177e4 1155 /* disable SIE */
ccc5df05
WN		 1156 azx_writel(chip, INTCTL,
1157 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1158}
1159
1160
1161/*
cb53c626 1162 * reset and start the controller registers
1da177e4 1163 */
cd508fe5 1164static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1165{
cb53c626
TI		 1166 if (chip->initialized)
1167 return;
1da177e4
LT		 1168
1169 /* reset controller */
cd508fe5 1170 azx_reset(chip, full_reset);
1da177e4
LT		 1171
1172 /* initialize interrupts */
1173 azx_int_clear(chip);
1174 azx_int_enable(chip);
1175
1176 /* initialize the codec command I/O */
1a696978
TI		 1177 if (!chip->single_cmd)
1178 azx_init_cmd_io(chip);
1da177e4 1179
0be3b5d3
TI		 1180 /* program the position buffer */
1181 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1182 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1183
cb53c626
TI		 1184 chip->initialized = 1;
1185}
1186
1187/*
1188 * initialize the PCI registers
1189 */
1190/* update bits in a PCI register byte */
1191static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1192 unsigned char mask, unsigned char val)
1193{
1194 unsigned char data;
1195
1196 pci_read_config_byte(pci, reg, &data);
1197 data &= ~mask;
1198 data |= (val & mask);
1199 pci_write_config_byte(pci, reg, data);
1200}
1201
1202static void azx_init_pci(struct azx *chip)
1203{
1204 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1205 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1206 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1207 * codecs.
1208 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1209 */
46f2cc80 1210 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1211 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1212 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1213 }
cb53c626 1214
9477c58e
TI		 1215 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1216 * we need to enable snoop.
1217 */
1218 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1219 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1220 update_pci_byte(chip->pci,
27fe48d9
TI		 1221 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1222 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1223 }
1224
1225 /* For NVIDIA HDA, enable snoop */
1226 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1227 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1228 update_pci_byte(chip->pci,
1229 NVIDIA_HDA_TRANSREG_ADDR,
1230 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1231 update_pci_byte(chip->pci,
1232 NVIDIA_HDA_ISTRM_COH,
1233 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1234 update_pci_byte(chip->pci,
1235 NVIDIA_HDA_OSTRM_COH,
1236 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1237 }
1238
1239 /* Enable SCH/PCH snoop if needed */
1240 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1241 unsigned short snoop;
90a5ad52 1242 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1243 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1244 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1245 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1246 if (!azx_snoop(chip))
1247 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1248 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1249 pci_read_config_word(chip->pci,
1250 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1251 }
27fe48d9
TI		 1252 snd_printdd(SFX "SCH snoop: %s\n",
1253 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1254 ? "Disabled" : "Enabled");
da3fca21 1255 }
1da177e4
LT		 1256}
1257
1258
9ad593f6
TI		 1259static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1260
1da177e4
LT		 1261/*
1262 * interrupt handler
1263 */
7d12e780 1264static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1265{
a98f90fd
TI		 1266 struct azx *chip = dev_id;
1267 struct azx_dev *azx_dev;
1da177e4 1268 u32 status;
9ef04066 1269 u8 sd_status;
fa00e046 1270 int i, ok;
1da177e4
LT		 1271
1272 spin_lock(&chip->reg_lock);
1273
60911062
DC		 1274 if (chip->disabled) {
1275 spin_unlock(&chip->reg_lock);
a82d51ed 1276 return IRQ_NONE;
60911062 1277 }
a82d51ed 1278
1da177e4
LT		 1279 status = azx_readl(chip, INTSTS);
1280 if (status == 0) {
1281 spin_unlock(&chip->reg_lock);
1282 return IRQ_NONE;
1283 }
1284
07e4ca50 1285 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1286 azx_dev = &chip->azx_dev[i];
1287 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1288 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1289 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1290 if (!azx_dev->substream || !azx_dev->running ||
1291 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1292 continue;
1293 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1294 ok = azx_position_ok(chip, azx_dev);
1295 if (ok == 1) {
9ad593f6 1296 azx_dev->irq_pending = 0;
1da177e4
LT		 1297 spin_unlock(&chip->reg_lock);
1298 snd_pcm_period_elapsed(azx_dev->substream);
1299 spin_lock(&chip->reg_lock);
fa00e046 1300 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1301 /* bogus IRQ, process it later */
1302 azx_dev->irq_pending = 1;
6acaed38
TI		 1303 queue_work(chip->bus->workq,
1304 &chip->irq_pending_work);
1da177e4
LT		 1305 }
1306 }
1307 }
1308
1309 /* clear rirb int */
1310 status = azx_readb(chip, RIRBSTS);
1311 if (status & RIRB_INT_MASK) {
14d34f16 1312 if (status & RIRB_INT_RESPONSE) {
9477c58e 1313 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1314 udelay(80);
1da177e4 1315 azx_update_rirb(chip);
14d34f16 1316 }
1da177e4
LT		 1317 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1318 }
1319
1320#if 0
1321 /* clear state status int */
1322 if (azx_readb(chip, STATESTS) & 0x04)
1323 azx_writeb(chip, STATESTS, 0x04);
1324#endif
1325 spin_unlock(&chip->reg_lock);
1326
1327 return IRQ_HANDLED;
1328}
1329
1330
675f25d4
TI		 1331/*
1332 * set up a BDL entry
1333 */
5ae763b1
TI		 1334static int setup_bdle(struct azx *chip,
1335 struct snd_pcm_substream *substream,
675f25d4
TI		 1336 struct azx_dev *azx_dev, u32 **bdlp,
1337 int ofs, int size, int with_ioc)
1338{
675f25d4
TI		 1339 u32 *bdl = *bdlp;
1340
1341 while (size > 0) {
1342 dma_addr_t addr;
1343 int chunk;
1344
1345 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1346 return -EINVAL;
1347
77a23f26 1348 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1349 /* program the address field of the BDL entry */
1350 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1351 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1352 /* program the size field of the BDL entry */
fc4abee8 1353 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1354 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1355 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1356 u32 remain = 0x1000 - (ofs & 0xfff);
1357 if (chunk > remain)
1358 chunk = remain;
1359 }
675f25d4
TI		 1360 bdl[2] = cpu_to_le32(chunk);
1361 /* program the IOC to enable interrupt
1362 * only when the whole fragment is processed
1363 */
1364 size -= chunk;
1365 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1366 bdl += 4;
1367 azx_dev->frags++;
1368 ofs += chunk;
1369 }
1370 *bdlp = bdl;
1371 return ofs;
1372}
1373
1da177e4
LT		 1374/*
1375 * set up BDL entries
1376 */
555e219f
TI		 1377static int azx_setup_periods(struct azx *chip,
1378 struct snd_pcm_substream *substream,
4ce107b9 1379 struct azx_dev *azx_dev)
1da177e4 1380{
4ce107b9
TI		 1381 u32 *bdl;
1382 int i, ofs, periods, period_bytes;
555e219f 1383 int pos_adj;
1da177e4
LT		 1384
1385 /* reset BDL address */
1386 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1387 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1388
97b71c94 1389 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1390 periods = azx_dev->bufsize / period_bytes;
1391
1da177e4 1392 /* program the initial BDL entries */
4ce107b9
TI		 1393 bdl = (u32 *)azx_dev->bdl.area;
1394 ofs = 0;
1395 azx_dev->frags = 0;
555e219f
TI		 1396 pos_adj = bdl_pos_adj[chip->dev_index];
1397 if (pos_adj > 0) {
675f25d4 1398 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1399 int pos_align = pos_adj;
555e219f 1400 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1401 if (!pos_adj)
e785d3d8
TI		 1402 pos_adj = pos_align;
1403 else
1404 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1405 pos_align;
675f25d4
TI		 1406 pos_adj = frames_to_bytes(runtime, pos_adj);
1407 if (pos_adj >= period_bytes) {
4abc1cc2 1408 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1409 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1410 pos_adj = 0;
1411 } else {
5ae763b1 1412 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1413 &bdl, ofs, pos_adj,
1414 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1415 if (ofs < 0)
1416 goto error;
4ce107b9 1417 }
555e219f
TI		 1418 } else
1419 pos_adj = 0;
675f25d4
TI		 1420 for (i = 0; i < periods; i++) {
1421 if (i == periods - 1 && pos_adj)
5ae763b1 1422 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1423 period_bytes - pos_adj, 0);
1424 else
5ae763b1 1425 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1426 period_bytes,
1427 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1428 if (ofs < 0)
1429 goto error;
1da177e4 1430 }
4ce107b9 1431 return 0;
675f25d4
TI		 1432
1433 error:
4abc1cc2 1434 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1435 azx_dev->bufsize, period_bytes);
675f25d4 1436 return -EINVAL;
1da177e4
LT		 1437}
1438
1dddab40
TI		 1439/* reset stream */
1440static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1441{
1442 unsigned char val;
1443 int timeout;
1444
1dddab40
TI		 1445 azx_stream_clear(chip, azx_dev);
1446
d01ce99f
TI		 1447 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1448 SD_CTL_STREAM_RESET);
1da177e4
LT		 1449 udelay(3);
1450 timeout = 300;
1451 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1452 --timeout)
1453 ;
1454 val &= ~SD_CTL_STREAM_RESET;
1455 azx_sd_writeb(azx_dev, SD_CTL, val);
1456 udelay(3);
1457
1458 timeout = 300;
1459 /* waiting for hardware to report that the stream is out of reset */
1460 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1461 --timeout)
1462 ;
fa00e046
JK		 1463
1464 /* reset first position - may not be synced with hw at this time */
1465 *azx_dev->posbuf = 0;
1dddab40 1466}
1da177e4 1467
1dddab40
TI		 1468/*
1469 * set up the SD for streaming
1470 */
1471static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1472{
27fe48d9 1473 unsigned int val;
1dddab40
TI		 1474 /* make sure the run bit is zero for SD */
1475 azx_stream_clear(chip, azx_dev);
1da177e4 1476 /* program the stream_tag */
27fe48d9
TI		 1477 val = azx_sd_readl(azx_dev, SD_CTL);
1478 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1479 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1480 if (!azx_snoop(chip))
1481 val |= SD_CTL_TRAFFIC_PRIO;
1482 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1483
1484 /* program the length of samples in cyclic buffer */
1485 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1486
1487 /* program the stream format */
1488 /* this value needs to be the same as the one programmed */
1489 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1490
1491 /* program the stream LVI (last valid index) of the BDL */
1492 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1493
1494 /* program the BDL address */
1495 /* lower BDL address */
4ce107b9 1496 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1497 /* upper BDL address */
766979e0 1498 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1499
0be3b5d3 1500 /* enable the position buffer */
4cb36310
DH		 1501 if (chip->position_fix[0] != POS_FIX_LPIB ||
1502 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1503 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1504 azx_writel(chip, DPLBASE,
1505 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1506 }
c74db86b 1507
1da177e4 1508 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1509 azx_sd_writel(azx_dev, SD_CTL,
1510 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1511
1512 return 0;
1513}
1514
6ce4a3bc
TI		 1515/*
1516 * Probe the given codec address
1517 */
1518static int probe_codec(struct azx *chip, int addr)
1519{
1520 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1521 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1522 unsigned int res;
1523
a678cdee 1524 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1525 chip->probing = 1;
1526 azx_send_cmd(chip->bus, cmd);
deadff16 1527 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1528 chip->probing = 0;
a678cdee 1529 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1530 if (res == -1)
1531 return -EIO;
4abc1cc2 1532 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1533 return 0;
1534}
1535
33fa35ed
TI		 1536static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1537 struct hda_pcm *cpcm);
6ce4a3bc 1538static void azx_stop_chip(struct azx *chip);
1da177e4 1539
8dd78330
TI		 1540static void azx_bus_reset(struct hda_bus *bus)
1541{
1542 struct azx *chip = bus->private_data;
8dd78330
TI		 1543
1544 bus->in_reset = 1;
1545 azx_stop_chip(chip);
cd508fe5 1546 azx_init_chip(chip, 1);
65f75983 1547#ifdef CONFIG_PM
8dd78330 1548 if (chip->initialized) {
01b65bfb
TI		 1549 struct azx_pcm *p;
1550 list_for_each_entry(p, &chip->pcm_list, list)
1551 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1552 snd_hda_suspend(chip->bus);
1553 snd_hda_resume(chip->bus);
1554 }
65f75983 1555#endif
8dd78330
TI		 1556 bus->in_reset = 0;
1557}
1558
1da177e4
LT		 1559/*
1560 * Codec initialization
1561 */
1562
2f5983f2 1563/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1564static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1565 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1566 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1567};
1568
a82d51ed 1569static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1570{
1571 struct hda_bus_template bus_temp;
34c25350
TI		 1572 int c, codecs, err;
1573 int max_slots;
1da177e4
LT		 1574
1575 memset(&bus_temp, 0, sizeof(bus_temp));
1576 bus_temp.private_data = chip;
1577 bus_temp.modelname = model;
1578 bus_temp.pci = chip->pci;
111d3af5
TI		 1579 bus_temp.ops.command = azx_send_cmd;
1580 bus_temp.ops.get_response = azx_get_response;
176d5335 1581 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1582 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1583#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1584 bus_temp.power_save = &power_save;
cb53c626
TI		 1585 bus_temp.ops.pm_notify = azx_power_notify;
1586#endif
1da177e4 1587
d01ce99f
TI		 1588 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1589 if (err < 0)
1da177e4
LT		 1590 return err;
1591
9477c58e
TI		 1592 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1593 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1594 chip->bus->needs_damn_long_delay = 1;
9477c58e 1595 }
dc9c8e21 1596
34c25350 1597 codecs = 0;
2f5983f2
TI		 1598 max_slots = azx_max_codecs[chip->driver_type];
1599 if (!max_slots)
7445dfc1 1600 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1601
1602 /* First try to probe all given codec slots */
1603 for (c = 0; c < max_slots; c++) {
f1eaaeec 1604 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1605 if (probe_codec(chip, c) < 0) {
1606 /* Some BIOSen give you wrong codec addresses
1607 * that don't exist
1608 */
4abc1cc2
TI		 1609 snd_printk(KERN_WARNING SFX
1610 "Codec #%d probe error; "
6ce4a3bc
TI		 1611 "disabling it...\n", c);
1612 chip->codec_mask &= ~(1 << c);
1613 /* More badly, accessing to a non-existing
1614 * codec often screws up the controller chip,
2448158e 1615 * and disturbs the further communications.
6ce4a3bc
TI		 1616 * Thus if an error occurs during probing,
1617 * better to reset the controller chip to
1618 * get back to the sanity state.
1619 */
1620 azx_stop_chip(chip);
cd508fe5 1621 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1622 }
1623 }
1624 }
1625
d507cd66
TI		 1626 /* AMD chipsets often cause the communication stalls upon certain
1627 * sequence like the pin-detection. It seems that forcing the synced
1628 * access works around the stall. Grrr...
1629 */
9477c58e
TI		 1630 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1631 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1632 chip->bus->sync_write = 1;
1633 chip->bus->allow_bus_reset = 1;
1634 }
1635
6ce4a3bc 1636 /* Then create codec instances */
34c25350 1637 for (c = 0; c < max_slots; c++) {
f1eaaeec 1638 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1639 struct hda_codec *codec;
a1e21c90 1640 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1641 if (err < 0)
1642 continue;
2dca0bba 1643 codec->beep_mode = chip->beep_mode;
1da177e4 1644 codecs++;
19a982b6
TI		 1645 }
1646 }
1647 if (!codecs) {
1da177e4
LT		 1648 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1649 return -ENXIO;
1650 }
a1e21c90
TI		 1651 return 0;
1652}
1da177e4 1653
a1e21c90
TI		 1654/* configure each codec instance */
1655static int __devinit azx_codec_configure(struct azx *chip)
1656{
1657 struct hda_codec *codec;
1658 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1659 snd_hda_codec_configure(codec);
1660 }
1da177e4
LT		 1661 return 0;
1662}
1663
1664
1665/*
1666 * PCM support
1667 */
1668
1669/* assign a stream for the PCM */
ef18bede
WF		 1670static inline struct azx_dev *
1671azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1672{
07e4ca50 1673 int dev, i, nums;
ef18bede 1674 struct azx_dev *res = NULL;
d5cf9911
TI		 1675 /* make a non-zero unique key for the substream */
1676 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1677 (substream->stream + 1);
ef18bede
WF		 1678
1679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1680 dev = chip->playback_index_offset;
1681 nums = chip->playback_streams;
1682 } else {
1683 dev = chip->capture_index_offset;
1684 nums = chip->capture_streams;
1685 }
1686 for (i = 0; i < nums; i++, dev++)
d01ce99f 1687 if (!chip->azx_dev[dev].opened) {
ef18bede 1688 res = &chip->azx_dev[dev];
d5cf9911 1689 if (res->assigned_key == key)
ef18bede 1690 break;
1da177e4 1691 }
ef18bede
WF		 1692 if (res) {
1693 res->opened = 1;
d5cf9911 1694 res->assigned_key = key;
ef18bede
WF		 1695 }
1696 return res;
1da177e4
LT		 1697}
1698
1699/* release the assigned stream */
a98f90fd 1700static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1701{
1702 azx_dev->opened = 0;
1703}
1704
a98f90fd 1705static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1706 .info = (SNDRV_PCM_INFO_MMAP |
1707 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1708 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1709 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1710 /* No full-resume yet implemented */
1711 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1712 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1713 SNDRV_PCM_INFO_SYNC_START |
1714 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1715 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1716 .rates = SNDRV_PCM_RATE_48000,
1717 .rate_min = 48000,
1718 .rate_max = 48000,
1719 .channels_min = 2,
1720 .channels_max = 2,
1721 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1722 .period_bytes_min = 128,
1723 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1724 .periods_min = 2,
1725 .periods_max = AZX_MAX_FRAG,
1726 .fifo_size = 0,
1727};
1728
a98f90fd 1729static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1730{
1731 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1732 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1733 struct azx *chip = apcm->chip;
1734 struct azx_dev *azx_dev;
1735 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1736 unsigned long flags;
1737 int err;
2ae66c26 1738 int buff_step;
1da177e4 1739
62932df8 1740 mutex_lock(&chip->open_mutex);
ef18bede 1741 azx_dev = azx_assign_device(chip, substream);
1da177e4 1742 if (azx_dev == NULL) {
62932df8 1743 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1744 return -EBUSY;
1745 }
1746 runtime->hw = azx_pcm_hw;
1747 runtime->hw.channels_min = hinfo->channels_min;
1748 runtime->hw.channels_max = hinfo->channels_max;
1749 runtime->hw.formats = hinfo->formats;
1750 runtime->hw.rates = hinfo->rates;
1751 snd_pcm_limit_hw_rates(runtime);
1752 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1753 if (chip->align_buffer_size)
2ae66c26
PLB		 1754 /* constrain buffer sizes to be multiple of 128
1755 bytes. This is more efficient in terms of memory
1756 access but isn't required by the HDA spec and
1757 prevents users from specifying exact period/buffer
1758 sizes. For example for 44.1kHz, a period size set
1759 to 20ms will be rounded to 19.59ms. */
1760 buff_step = 128;
1761 else
1762 /* Don't enforce steps on buffer sizes, still need to
1763 be multiple of 4 bytes (HDA spec). Tested on Intel
1764 HDA controllers, may not work on all devices where
1765 option needs to be disabled */
1766 buff_step = 4;
1767
5f1545bc 1768 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1769 buff_step);
5f1545bc 1770 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1771 buff_step);
b4a91cf0 1772 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1773 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1774 if (err < 0) {
1da177e4 1775 azx_release_device(azx_dev);
cb53c626 1776 snd_hda_power_down(apcm->codec);
62932df8 1777 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1778 return err;
1779 }
70d321e6 1780 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1781 /* sanity check */
1782 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1783 snd_BUG_ON(!runtime->hw.channels_max) ||
1784 snd_BUG_ON(!runtime->hw.formats) ||
1785 snd_BUG_ON(!runtime->hw.rates)) {
1786 azx_release_device(azx_dev);
1787 hinfo->ops.close(hinfo, apcm->codec, substream);
1788 snd_hda_power_down(apcm->codec);
1789 mutex_unlock(&chip->open_mutex);
1790 return -EINVAL;
1791 }
1da177e4
LT		 1792 spin_lock_irqsave(&chip->reg_lock, flags);
1793 azx_dev->substream = substream;
1794 azx_dev->running = 0;
1795 spin_unlock_irqrestore(&chip->reg_lock, flags);
1796
1797 runtime->private_data = azx_dev;
850f0e52 1798 snd_pcm_set_sync(substream);
62932df8 1799 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1800 return 0;
1801}
1802
a98f90fd 1803static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1804{
1805 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1806 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1807 struct azx *chip = apcm->chip;
1808 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1809 unsigned long flags;
1810
62932df8 1811 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1812 spin_lock_irqsave(&chip->reg_lock, flags);
1813 azx_dev->substream = NULL;
1814 azx_dev->running = 0;
1815 spin_unlock_irqrestore(&chip->reg_lock, flags);
1816 azx_release_device(azx_dev);
1817 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1818 snd_hda_power_down(apcm->codec);
62932df8 1819 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1820 return 0;
1821}
1822
d01ce99f
TI		 1823static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1824 struct snd_pcm_hw_params *hw_params)
1da177e4 1825{
27fe48d9
TI		 1826 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1827 struct azx *chip = apcm->chip;
1828 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1829 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1830 int ret;
97b71c94 1831
27fe48d9 1832 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1833 azx_dev->bufsize = 0;
1834 azx_dev->period_bytes = 0;
1835 azx_dev->format_val = 0;
27fe48d9 1836 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1837 params_buffer_bytes(hw_params));
27fe48d9
TI		 1838 if (ret < 0)
1839 return ret;
1840 mark_runtime_wc(chip, azx_dev, runtime, true);
1841 return ret;
1da177e4
LT		 1842}
1843
a98f90fd 1844static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1845{
1846 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1847 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1848 struct azx *chip = apcm->chip;
1849 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1850 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1851
1852 /* reset BDL address */
1853 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1854 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1855 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1856 azx_dev->bufsize = 0;
1857 azx_dev->period_bytes = 0;
1858 azx_dev->format_val = 0;
1da177e4 1859
eb541337 1860 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1861
27fe48d9 1862 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1863 return snd_pcm_lib_free_pages(substream);
1864}
1865
a98f90fd 1866static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1867{
1868 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1869 struct azx *chip = apcm->chip;
1870 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1871 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1872 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1873 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1874 int err;
7c935976
SW		 1875 struct hda_spdif_out *spdif =
1876 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1877 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1878
fa00e046 1879 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1880 format_val = snd_hda_calc_stream_format(runtime->rate,
1881 runtime->channels,
1882 runtime->format,
32c168c8 1883 hinfo->maxbps,
7c935976 1884 ctls);
97b71c94 1885 if (!format_val) {
d01ce99f
TI		 1886 snd_printk(KERN_ERR SFX
1887 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1888 runtime->rate, runtime->channels, runtime->format);
1889 return -EINVAL;
1890 }
1891
97b71c94
TI		 1892 bufsize = snd_pcm_lib_buffer_bytes(substream);
1893 period_bytes = snd_pcm_lib_period_bytes(substream);
1894
4abc1cc2 1895 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1896 bufsize, format_val);
1897
1898 if (bufsize != azx_dev->bufsize ||
1899 period_bytes != azx_dev->period_bytes ||
1900 format_val != azx_dev->format_val) {
1901 azx_dev->bufsize = bufsize;
1902 azx_dev->period_bytes = period_bytes;
1903 azx_dev->format_val = format_val;
1904 err = azx_setup_periods(chip, substream, azx_dev);
1905 if (err < 0)
1906 return err;
1907 }
1908
e5463720
JK		 1909 /* wallclk has 24Mhz clock source */
1910 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1911 runtime->rate) * 1000);
1da177e4
LT		 1912 azx_setup_controller(chip, azx_dev);
1913 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1914 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1915 else
1916 azx_dev->fifo_size = 0;
1917
62b7e5e0
TI		 1918 stream_tag = azx_dev->stream_tag;
1919 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1920 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1921 stream_tag > chip->capture_streams)
1922 stream_tag -= chip->capture_streams;
1923 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1924 azx_dev->format_val, substream);
1da177e4
LT		 1925}
1926
a98f90fd 1927static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1928{
1929 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1930 struct azx *chip = apcm->chip;
850f0e52
TI		 1931 struct azx_dev *azx_dev;
1932 struct snd_pcm_substream *s;
fa00e046 1933 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1934 int nwait, timeout;
1da177e4 1935
1da177e4 1936 switch (cmd) {
fa00e046
JK		 1937 case SNDRV_PCM_TRIGGER_START:
1938 rstart = 1;
1da177e4
LT		 1939 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1940 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1941 start = 1;
1da177e4
LT		 1942 break;
1943 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1944 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1945 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1946 start = 0;
1da177e4
LT		 1947 break;
1948 default:
850f0e52
TI		 1949 return -EINVAL;
1950 }
1951
1952 snd_pcm_group_for_each_entry(s, substream) {
1953 if (s->pcm->card != substream->pcm->card)
1954 continue;
1955 azx_dev = get_azx_dev(s);
1956 sbits |= 1 << azx_dev->index;
1957 nsync++;
1958 snd_pcm_trigger_done(s, substream);
1959 }
1960
1961 spin_lock(&chip->reg_lock);
1962 if (nsync > 1) {
1963 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1964 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1965 azx_writel(chip, OLD_SSYNC,
1966 azx_readl(chip, OLD_SSYNC) | sbits);
1967 else
1968 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1969 }
1970 snd_pcm_group_for_each_entry(s, substream) {
1971 if (s->pcm->card != substream->pcm->card)
1972 continue;
1973 azx_dev = get_azx_dev(s);
e5463720
JK		 1974 if (start) {
1975 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1976 if (!rstart)
1977 azx_dev->start_wallclk -=
1978 azx_dev->period_wallclk;
850f0e52 1979 azx_stream_start(chip, azx_dev);
e5463720 1980 } else {
850f0e52 1981 azx_stream_stop(chip, azx_dev);
e5463720 1982 }
850f0e52 1983 azx_dev->running = start;
1da177e4
LT		 1984 }
1985 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1986 if (start) {
1987 if (nsync == 1)
1988 return 0;
1989 /* wait until all FIFOs get ready */
1990 for (timeout = 5000; timeout; timeout--) {
1991 nwait = 0;
1992 snd_pcm_group_for_each_entry(s, substream) {
1993 if (s->pcm->card != substream->pcm->card)
1994 continue;
1995 azx_dev = get_azx_dev(s);
1996 if (!(azx_sd_readb(azx_dev, SD_STS) &
1997 SD_STS_FIFO_READY))
1998 nwait++;
1999 }
2000 if (!nwait)
2001 break;
2002 cpu_relax();
2003 }
2004 } else {
2005 /* wait until all RUN bits are cleared */
2006 for (timeout = 5000; timeout; timeout--) {
2007 nwait = 0;
2008 snd_pcm_group_for_each_entry(s, substream) {
2009 if (s->pcm->card != substream->pcm->card)
2010 continue;
2011 azx_dev = get_azx_dev(s);
2012 if (azx_sd_readb(azx_dev, SD_CTL) &
2013 SD_CTL_DMA_START)
2014 nwait++;
2015 }
2016 if (!nwait)
2017 break;
2018 cpu_relax();
2019 }
1da177e4 2020 }
850f0e52
TI		 2021 if (nsync > 1) {
2022 spin_lock(&chip->reg_lock);
2023 /* reset SYNC bits */
8b0bd226
TI		 2024 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2025 azx_writel(chip, OLD_SSYNC,
2026 azx_readl(chip, OLD_SSYNC) & ~sbits);
2027 else
2028 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 2029 spin_unlock(&chip->reg_lock);
2030 }
2031 return 0;
1da177e4
LT		 2032}
2033
0e153474
JC		 2034/* get the current DMA position with correction on VIA chips */
2035static unsigned int azx_via_get_position(struct azx *chip,
2036 struct azx_dev *azx_dev)
2037{
2038 unsigned int link_pos, mini_pos, bound_pos;
2039 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2040 unsigned int fifo_size;
2041
2042 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2043 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2044 /* Playback, no problem using link position */
2045 return link_pos;
2046 }
2047
2048 /* Capture */
2049 /* For new chipset,
2050 * use mod to get the DMA position just like old chipset
2051 */
2052 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2053 mod_dma_pos %= azx_dev->period_bytes;
2054
2055 /* azx_dev->fifo_size can't get FIFO size of in stream.
2056 * Get from base address + offset.
2057 */
2058 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2059
2060 if (azx_dev->insufficient) {
2061 /* Link position never gather than FIFO size */
2062 if (link_pos <= fifo_size)
2063 return 0;
2064
2065 azx_dev->insufficient = 0;
2066 }
2067
2068 if (link_pos <= fifo_size)
2069 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2070 else
2071 mini_pos = link_pos - fifo_size;
2072
2073 /* Find nearest previous boudary */
2074 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2075 mod_link_pos = link_pos % azx_dev->period_bytes;
2076 if (mod_link_pos >= fifo_size)
2077 bound_pos = link_pos - mod_link_pos;
2078 else if (mod_dma_pos >= mod_mini_pos)
2079 bound_pos = mini_pos - mod_mini_pos;
2080 else {
2081 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2082 if (bound_pos >= azx_dev->bufsize)
2083 bound_pos = 0;
2084 }
2085
2086 /* Calculate real DMA position we want */
2087 return bound_pos + mod_dma_pos;
2088}
2089
9ad593f6 2090static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2091 struct azx_dev *azx_dev,
2092 bool with_check)
1da177e4 2093{
1da177e4 2094 unsigned int pos;
4cb36310 2095 int stream = azx_dev->substream->stream;
1da177e4 2096
4cb36310
DH		 2097 switch (chip->position_fix[stream]) {
2098 case POS_FIX_LPIB:
2099 /* read LPIB */
2100 pos = azx_sd_readl(azx_dev, SD_LPIB);
2101 break;
2102 case POS_FIX_VIACOMBO:
0e153474 2103 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2104 break;
2105 default:
2106 /* use the position buffer */
2107 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2108 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2109 if (!pos || pos == (u32)-1) {
2110 printk(KERN_WARNING
2111 "hda-intel: Invalid position buffer, "
2112 "using LPIB read method instead.\n");
2113 chip->position_fix[stream] = POS_FIX_LPIB;
2114 pos = azx_sd_readl(azx_dev, SD_LPIB);
2115 } else
2116 chip->position_fix[stream] = POS_FIX_POSBUF;
2117 }
2118 break;
c74db86b 2119 }
4cb36310 2120
1da177e4
LT		 2121 if (pos >= azx_dev->bufsize)
2122 pos = 0;
9ad593f6
TI		 2123 return pos;
2124}
2125
2126static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2127{
2128 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2129 struct azx *chip = apcm->chip;
2130 struct azx_dev *azx_dev = get_azx_dev(substream);
2131 return bytes_to_frames(substream->runtime,
798cb7e8 2132 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2133}
2134
2135/*
2136 * Check whether the current DMA position is acceptable for updating
2137 * periods. Returns non-zero if it's OK.
2138 *
2139 * Many HD-audio controllers appear pretty inaccurate about
2140 * the update-IRQ timing. The IRQ is issued before actually the
2141 * data is processed. So, we need to process it afterwords in a
2142 * workqueue.
2143 */
2144static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2145{
e5463720 2146 u32 wallclk;
9ad593f6 2147 unsigned int pos;
beaffc39 2148 int stream;
9ad593f6 2149
f48f606d
JK		 2150 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2151 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2152 return -1; /* bogus (too early) interrupt */
fa00e046 2153
beaffc39 2154 stream = azx_dev->substream->stream;
798cb7e8 2155 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2156
d6d8bf54
TI		 2157 if (WARN_ONCE(!azx_dev->period_bytes,
2158 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2159 return -1; /* this shouldn't happen! */
edb39935 2160 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2161 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2162 /* NG - it's below the first next period boundary */
2163 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2164 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2165 return 1; /* OK, it's fine */
2166}
2167
2168/*
2169 * The work for pending PCM period updates.
2170 */
2171static void azx_irq_pending_work(struct work_struct *work)
2172{
2173 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2174 int i, pending, ok;
9ad593f6 2175
a6a950a8
TI		 2176 if (!chip->irq_pending_warned) {
2177 printk(KERN_WARNING
2178 "hda-intel: IRQ timing workaround is activated "
2179 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2180 chip->card->number);
2181 chip->irq_pending_warned = 1;
2182 }
2183
9ad593f6
TI		 2184 for (;;) {
2185 pending = 0;
2186 spin_lock_irq(&chip->reg_lock);
2187 for (i = 0; i < chip->num_streams; i++) {
2188 struct azx_dev *azx_dev = &chip->azx_dev[i];
2189 if (!azx_dev->irq_pending ||
2190 !azx_dev->substream ||
2191 !azx_dev->running)
2192 continue;
e5463720
JK		 2193 ok = azx_position_ok(chip, azx_dev);
2194 if (ok > 0) {
9ad593f6
TI		 2195 azx_dev->irq_pending = 0;
2196 spin_unlock(&chip->reg_lock);
2197 snd_pcm_period_elapsed(azx_dev->substream);
2198 spin_lock(&chip->reg_lock);
e5463720
JK		 2199 } else if (ok < 0) {
2200 pending = 0; /* too early */
9ad593f6
TI		 2201 } else
2202 pending++;
2203 }
2204 spin_unlock_irq(&chip->reg_lock);
2205 if (!pending)
2206 return;
08af495f 2207 msleep(1);
9ad593f6
TI		 2208 }
2209}
2210
2211/* clear irq_pending flags and assure no on-going workq */
2212static void azx_clear_irq_pending(struct azx *chip)
2213{
2214 int i;
2215
2216 spin_lock_irq(&chip->reg_lock);
2217 for (i = 0; i < chip->num_streams; i++)
2218 chip->azx_dev[i].irq_pending = 0;
2219 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2220}
2221
27fe48d9
TI		 2222#ifdef CONFIG_X86
2223static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2224 struct vm_area_struct *area)
2225{
2226 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2227 struct azx *chip = apcm->chip;
2228 if (!azx_snoop(chip))
2229 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2230 return snd_pcm_lib_default_mmap(substream, area);
2231}
2232#else
2233#define azx_pcm_mmap NULL
2234#endif
2235
a98f90fd 2236static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2237 .open = azx_pcm_open,
2238 .close = azx_pcm_close,
2239 .ioctl = snd_pcm_lib_ioctl,
2240 .hw_params = azx_pcm_hw_params,
2241 .hw_free = azx_pcm_hw_free,
2242 .prepare = azx_pcm_prepare,
2243 .trigger = azx_pcm_trigger,
2244 .pointer = azx_pcm_pointer,
27fe48d9 2245 .mmap = azx_pcm_mmap,
4ce107b9 2246 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2247};
2248
a98f90fd 2249static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2250{
176d5335
TI		 2251 struct azx_pcm *apcm = pcm->private_data;
2252 if (apcm) {
01b65bfb 2253 list_del(&apcm->list);
176d5335
TI		 2254 kfree(apcm);
2255 }
1da177e4
LT		 2256}
2257
acfa634f
TI		 2258#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2259
176d5335 2260static int
33fa35ed
TI		 2261azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2262 struct hda_pcm *cpcm)
1da177e4 2263{
33fa35ed 2264 struct azx *chip = bus->private_data;
a98f90fd 2265 struct snd_pcm *pcm;
1da177e4 2266 struct azx_pcm *apcm;
176d5335 2267 int pcm_dev = cpcm->device;
acfa634f 2268 unsigned int size;
176d5335 2269 int s, err;
1da177e4 2270
01b65bfb
TI		 2271 list_for_each_entry(apcm, &chip->pcm_list, list) {
2272 if (apcm->pcm->device == pcm_dev) {
2273 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2274 return -EBUSY;
2275 }
176d5335
TI		 2276 }
2277 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2278 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2279 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2280 &pcm);
2281 if (err < 0)
2282 return err;
18cb7109 2283 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2284 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2285 if (apcm == NULL)
2286 return -ENOMEM;
2287 apcm->chip = chip;
01b65bfb 2288 apcm->pcm = pcm;
1da177e4 2289 apcm->codec = codec;
1da177e4
LT		 2290 pcm->private_data = apcm;
2291 pcm->private_free = azx_pcm_free;
176d5335
TI		 2292 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2293 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2294 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2295 cpcm->pcm = pcm;
2296 for (s = 0; s < 2; s++) {
2297 apcm->hinfo[s] = &cpcm->stream[s];
2298 if (cpcm->stream[s].substreams)
2299 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2300 }
2301 /* buffer pre-allocation */
acfa634f
TI		 2302 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2303 if (size > MAX_PREALLOC_SIZE)
2304 size = MAX_PREALLOC_SIZE;
4ce107b9 2305 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2306 snd_dma_pci_data(chip->pci),
acfa634f 2307 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2308 return 0;
2309}
2310
2311/*
2312 * mixer creation - all stuff is implemented in hda module
2313 */
a98f90fd 2314static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2315{
2316 return snd_hda_build_controls(chip->bus);
2317}
2318
2319
2320/*
2321 * initialize SD streams
2322 */
a98f90fd 2323static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2324{
2325 int i;
2326
2327 /* initialize each stream (aka device)
d01ce99f
TI		 2328 * assign the starting bdl address to each stream (device)
2329 * and initialize
1da177e4 2330 */
07e4ca50 2331 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2332 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2333 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2334 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2335 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2336 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2337 azx_dev->sd_int_sta_mask = 1 << i;
2338 /* stream tag: must be non-zero and unique */
2339 azx_dev->index = i;
2340 azx_dev->stream_tag = i + 1;
2341 }
2342
2343 return 0;
2344}
2345
68e7fffc
TI		 2346static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2347{
437a5a46
TI		 2348 if (request_irq(chip->pci->irq, azx_interrupt,
2349 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2350 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2351 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2352 "disabling device\n", chip->pci->irq);
2353 if (do_disconnect)
2354 snd_card_disconnect(chip->card);
2355 return -1;
2356 }
2357 chip->irq = chip->pci->irq;
69e13418 2358 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2359 return 0;
2360}
2361
1da177e4 2362
cb53c626
TI		 2363static void azx_stop_chip(struct azx *chip)
2364{
95e99fda 2365 if (!chip->initialized)
cb53c626
TI		 2366 return;
2367
2368 /* disable interrupts */
2369 azx_int_disable(chip);
2370 azx_int_clear(chip);
2371
2372 /* disable CORB/RIRB */
2373 azx_free_cmd_io(chip);
2374
2375 /* disable position buffer */
2376 azx_writel(chip, DPLBASE, 0);
2377 azx_writel(chip, DPUBASE, 0);
2378
2379 chip->initialized = 0;
2380}
2381
2382#ifdef CONFIG_SND_HDA_POWER_SAVE
2383/* power-up/down the controller */
33fa35ed 2384static void azx_power_notify(struct hda_bus *bus)
cb53c626 2385{
33fa35ed 2386 struct azx *chip = bus->private_data;
cb53c626
TI		 2387 struct hda_codec *c;
2388 int power_on = 0;
2389
33fa35ed 2390 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2391 if (c->power_on) {
2392 power_on = 1;
2393 break;
2394 }
2395 }
2396 if (power_on)
cd508fe5 2397 azx_init_chip(chip, 1);
0287d970
WF		 2398 else if (chip->running && power_save_controller &&
2399 !bus->power_keep_link_on)
cb53c626 2400 azx_stop_chip(chip);
cb53c626 2401}
5c0b9bec
TI		 2402#endif /* CONFIG_SND_HDA_POWER_SAVE */
2403
2404#ifdef CONFIG_PM
2405/*
2406 * power management
2407 */
986862bd 2408
68cb2b55 2409static int azx_suspend(struct device *dev)
1da177e4 2410{
68cb2b55
TI		 2411 struct pci_dev *pci = to_pci_dev(dev);
2412 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2413 struct azx *chip = card->private_data;
01b65bfb 2414 struct azx_pcm *p;
1da177e4 2415
421a1252 2416 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2417 azx_clear_irq_pending(chip);
01b65bfb
TI		 2418 list_for_each_entry(p, &chip->pcm_list, list)
2419 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2420 if (chip->initialized)
8dd78330 2421 snd_hda_suspend(chip->bus);
cb53c626 2422 azx_stop_chip(chip);
30b35399 2423 if (chip->irq >= 0) {
43001c95 2424 free_irq(chip->irq, chip);
30b35399
TI		 2425 chip->irq = -1;
2426 }
68e7fffc 2427 if (chip->msi)
43001c95 2428 pci_disable_msi(chip->pci);
421a1252
TI		 2429 pci_disable_device(pci);
2430 pci_save_state(pci);
68cb2b55 2431 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2432 return 0;
2433}
2434
68cb2b55 2435static int azx_resume(struct device *dev)
1da177e4 2436{
68cb2b55
TI		 2437 struct pci_dev *pci = to_pci_dev(dev);
2438 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2439 struct azx *chip = card->private_data;
1da177e4 2440
d14a7e0b
TI		 2441 pci_set_power_state(pci, PCI_D0);
2442 pci_restore_state(pci);
30b35399
TI		 2443 if (pci_enable_device(pci) < 0) {
2444 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2445 "disabling device\n");
2446 snd_card_disconnect(card);
2447 return -EIO;
2448 }
2449 pci_set_master(pci);
68e7fffc
TI		 2450 if (chip->msi)
2451 if (pci_enable_msi(pci) < 0)
2452 chip->msi = 0;
2453 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2454 return -EIO;
cb53c626 2455 azx_init_pci(chip);
d804ad92 2456
7f30830b 2457 azx_init_chip(chip, 1);
d804ad92 2458
1da177e4 2459 snd_hda_resume(chip->bus);
421a1252 2460 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2461 return 0;
2462}
68cb2b55
TI		 2463static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2464#define AZX_PM_OPS &azx_pm
2465#else
2466#define azx_suspend(dev)
2467#define azx_resume(dev)
2468#define AZX_PM_OPS NULL
1da177e4
LT		 2469#endif /* CONFIG_PM */
2470
2471
0cbf0098
TI		 2472/*
2473 * reboot notifier for hang-up problem at power-down
2474 */
2475static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2476{
2477 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2478 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2479 azx_stop_chip(chip);
2480 return NOTIFY_OK;
2481}
2482
2483static void azx_notifier_register(struct azx *chip)
2484{
2485 chip->reboot_notifier.notifier_call = azx_halt;
2486 register_reboot_notifier(&chip->reboot_notifier);
2487}
2488
2489static void azx_notifier_unregister(struct azx *chip)
2490{
2491 if (chip->reboot_notifier.notifier_call)
2492 unregister_reboot_notifier(&chip->reboot_notifier);
2493}
2494
a82d51ed
TI		 2495static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2496static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2497
8393ec4a 2498#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2499static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2500
a82d51ed
TI		 2501static void azx_vs_set_state(struct pci_dev *pci,
2502 enum vga_switcheroo_state state)
2503{
2504 struct snd_card *card = pci_get_drvdata(pci);
2505 struct azx *chip = card->private_data;
2506 bool disabled;
2507
2508 if (chip->init_failed)
2509 return;
2510
2511 disabled = (state == VGA_SWITCHEROO_OFF);
2512 if (chip->disabled == disabled)
2513 return;
2514
2515 if (!chip->bus) {
2516 chip->disabled = disabled;
2517 if (!disabled) {
2518 snd_printk(KERN_INFO SFX
2519 "%s: Start delayed initialization\n",
2520 pci_name(chip->pci));
2521 if (azx_first_init(chip) < 0 ||
2522 azx_probe_continue(chip) < 0) {
2523 snd_printk(KERN_ERR SFX
2524 "%s: initialization error\n",
2525 pci_name(chip->pci));
2526 chip->init_failed = true;
2527 }
2528 }
2529 } else {
2530 snd_printk(KERN_INFO SFX
2531 "%s %s via VGA-switcheroo\n",
2532 disabled ? "Disabling" : "Enabling",
2533 pci_name(chip->pci));
2534 if (disabled) {
68cb2b55 2535 azx_suspend(&pci->dev);
a82d51ed
TI		 2536 chip->disabled = true;
2537 snd_hda_lock_devices(chip->bus);
2538 } else {
2539 snd_hda_unlock_devices(chip->bus);
2540 chip->disabled = false;
68cb2b55 2541 azx_resume(&pci->dev);
a82d51ed
TI		 2542 }
2543 }
2544}
2545
2546static bool azx_vs_can_switch(struct pci_dev *pci)
2547{
2548 struct snd_card *card = pci_get_drvdata(pci);
2549 struct azx *chip = card->private_data;
2550
2551 if (chip->init_failed)
2552 return false;
2553 if (chip->disabled || !chip->bus)
2554 return true;
2555 if (snd_hda_lock_devices(chip->bus))
2556 return false;
2557 snd_hda_unlock_devices(chip->bus);
2558 return true;
2559}
2560
2561static void __devinit init_vga_switcheroo(struct azx *chip)
2562{
2563 struct pci_dev *p = get_bound_vga(chip->pci);
2564 if (p) {
2565 snd_printk(KERN_INFO SFX
2566 "%s: Handle VGA-switcheroo audio client\n",
2567 pci_name(chip->pci));
2568 chip->use_vga_switcheroo = 1;
2569 pci_dev_put(p);
2570 }
2571}
2572
2573static const struct vga_switcheroo_client_ops azx_vs_ops = {
2574 .set_gpu_state = azx_vs_set_state,
2575 .can_switch = azx_vs_can_switch,
2576};
2577
2578static int __devinit register_vga_switcheroo(struct azx *chip)
2579{
2580 if (!chip->use_vga_switcheroo)
2581 return 0;
2582 /* FIXME: currently only handling DIS controller
2583 * is there any machine with two switchable HDMI audio controllers?
2584 */
2585 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2586 VGA_SWITCHEROO_DIS,
2587 chip->bus != NULL);
2588}
2589#else
2590#define init_vga_switcheroo(chip) /* NOP */
2591#define register_vga_switcheroo(chip) 0
8393ec4a 2592#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2593#endif /* SUPPORT_VGA_SWITCHER */
2594
1da177e4
LT		 2595/*
2596 * destructor
2597 */
a98f90fd 2598static int azx_free(struct azx *chip)
1da177e4 2599{
4ce107b9
TI		 2600 int i;
2601
0cbf0098
TI		 2602 azx_notifier_unregister(chip);
2603
a82d51ed
TI		 2604 if (use_vga_switcheroo(chip)) {
2605 if (chip->disabled && chip->bus)
2606 snd_hda_unlock_devices(chip->bus);
2607 vga_switcheroo_unregister_client(chip->pci);
2608 }
2609
ce43fbae 2610 if (chip->initialized) {
9ad593f6 2611 azx_clear_irq_pending(chip);
07e4ca50 2612 for (i = 0; i < chip->num_streams; i++)
1da177e4 2613 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2614 azx_stop_chip(chip);
1da177e4
LT		 2615 }
2616
f000fd80 2617 if (chip->irq >= 0)
1da177e4 2618 free_irq(chip->irq, (void*)chip);
68e7fffc 2619 if (chip->msi)
30b35399 2620 pci_disable_msi(chip->pci);
f079c25a
TI		 2621 if (chip->remap_addr)
2622 iounmap(chip->remap_addr);
1da177e4 2623
4ce107b9
TI		 2624 if (chip->azx_dev) {
2625 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2626 if (chip->azx_dev[i].bdl.area) {
2627 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2628 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2629 }
4ce107b9 2630 }
27fe48d9
TI		 2631 if (chip->rb.area) {
2632 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2633 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2634 }
2635 if (chip->posbuf.area) {
2636 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2637 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2638 }
a82d51ed
TI		 2639 if (chip->region_requested)
2640 pci_release_regions(chip->pci);
1da177e4 2641 pci_disable_device(chip->pci);
07e4ca50 2642 kfree(chip->azx_dev);
1da177e4
LT		 2643 kfree(chip);
2644
2645 return 0;
2646}
2647
a98f90fd 2648static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2649{
2650 return azx_free(device->device_data);
2651}
2652
8393ec4a 2653#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2654/*
2655 * Check of disabled HDMI controller by vga-switcheroo
2656 */
2657static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2658{
2659 struct pci_dev *p;
2660
2661 /* check only discrete GPU */
2662 switch (pci->vendor) {
2663 case PCI_VENDOR_ID_ATI:
2664 case PCI_VENDOR_ID_AMD:
2665 case PCI_VENDOR_ID_NVIDIA:
2666 if (pci->devfn == 1) {
2667 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2668 pci->bus->number, 0);
2669 if (p) {
2670 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2671 return p;
2672 pci_dev_put(p);
2673 }
2674 }
2675 break;
2676 }
2677 return NULL;
2678}
2679
2680static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2681{
2682 bool vga_inactive = false;
2683 struct pci_dev *p = get_bound_vga(pci);
2684
2685 if (p) {
12b78a7f 2686 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2687 vga_inactive = true;
2688 pci_dev_put(p);
2689 }
2690 return vga_inactive;
2691}
8393ec4a 2692#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2693
3372a153
TI		 2694/*
2695 * white/black-listing for position_fix
2696 */
623ec047 2697static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2698 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2699 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2700 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2701 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2702 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2703 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
64f1e00d 2704 SND_PCI_QUIRK(0x1043, 0x1ac3, "ASUS X53S", POS_FIX_POSBUF),
c302d613 2705 SND_PCI_QUIRK(0x1043, 0x1b43, "ASUS K53E", POS_FIX_POSBUF),
e96d3127 2706 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2707 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2708 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2709 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2710 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2711 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2712 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2713 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2714 {}
2715};
2716
2717static int __devinit check_position_fix(struct azx *chip, int fix)
2718{
2719 const struct snd_pci_quirk *q;
2720
c673ba1c
TI		 2721 switch (fix) {
2722 case POS_FIX_LPIB:
2723 case POS_FIX_POSBUF:
4cb36310 2724 case POS_FIX_VIACOMBO:
a6f2fd55 2725 case POS_FIX_COMBO:
c673ba1c
TI		 2726 return fix;
2727 }
2728
c673ba1c
TI		 2729 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2730 if (q) {
2731 printk(KERN_INFO
2732 "hda_intel: position_fix set to %d "
2733 "for device %04x:%04x\n",
2734 q->value, q->subvendor, q->subdevice);
2735 return q->value;
3372a153 2736 }
bdd9ef24
DH		 2737
2738 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2739 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2740 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2741 return POS_FIX_VIACOMBO;
9477c58e
TI		 2742 }
2743 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2744 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2745 return POS_FIX_LPIB;
bdd9ef24 2746 }
c20c5a84
SH		 2747 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2748 snd_printd(SFX "Using COMBO position fix\n");
2749 return POS_FIX_COMBO;
2750 }
c673ba1c 2751 return POS_FIX_AUTO;
3372a153
TI		 2752}
2753
669ba27a
TI		 2754/*
2755 * black-lists for probe_mask
2756 */
2757static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2758 /* Thinkpad often breaks the controller communication when accessing
2759 * to the non-working (or non-existing) modem codec slot.
2760 */
2761 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2762 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2763 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2764 /* broken BIOS */
2765 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2766 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2767 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2768 /* forced codec slots */
93574844 2769 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2770 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2771 /* WinFast VP200 H (Teradici) user reported broken communication */
2772 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2773 {}
2774};
2775
f1eaaeec
TI		 2776#define AZX_FORCE_CODEC_MASK 0x100
2777
5aba4f8e 2778static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2779{
2780 const struct snd_pci_quirk *q;
2781
f1eaaeec
TI		 2782 chip->codec_probe_mask = probe_mask[dev];
2783 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2784 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2785 if (q) {
2786 printk(KERN_INFO
2787 "hda_intel: probe_mask set to 0x%x "
2788 "for device %04x:%04x\n",
2789 q->value, q->subvendor, q->subdevice);
f1eaaeec 2790 chip->codec_probe_mask = q->value;
669ba27a
TI		 2791 }
2792 }
f1eaaeec
TI		 2793
2794 /* check forced option */
2795 if (chip->codec_probe_mask != -1 &&
2796 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2797 chip->codec_mask = chip->codec_probe_mask & 0xff;
2798 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2799 chip->codec_mask);
2800 }
669ba27a
TI		 2801}
2802
4d8e22e0 2803/*
71623855 2804 * white/black-list for enable_msi
4d8e22e0 2805 */
71623855 2806static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2807 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2808 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2809 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2810 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2811 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2812 {}
2813};
2814
2815static void __devinit check_msi(struct azx *chip)
2816{
2817 const struct snd_pci_quirk *q;
2818
71623855
TI		 2819 if (enable_msi >= 0) {
2820 chip->msi = !!enable_msi;
4d8e22e0 2821 return;
71623855
TI		 2822 }
2823 chip->msi = 1; /* enable MSI as default */
2824 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2825 if (q) {
2826 printk(KERN_INFO
2827 "hda_intel: msi for device %04x:%04x set to %d\n",
2828 q->subvendor, q->subdevice, q->value);
2829 chip->msi = q->value;
80c43ed7
TI		 2830 return;
2831 }
2832
2833 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2834 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2835 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2836 chip->msi = 0;
4d8e22e0
TI		 2837 }
2838}
2839
a1585d76
TI		 2840/* check the snoop mode availability */
2841static void __devinit azx_check_snoop_available(struct azx *chip)
2842{
2843 bool snoop = chip->snoop;
2844
2845 switch (chip->driver_type) {
2846 case AZX_DRIVER_VIA:
2847 /* force to non-snoop mode for a new VIA controller
2848 * when BIOS is set
2849 */
2850 if (snoop) {
2851 u8 val;
2852 pci_read_config_byte(chip->pci, 0x42, &val);
2853 if (!(val & 0x80) && chip->pci->revision == 0x30)
2854 snoop = false;
2855 }
2856 break;
2857 case AZX_DRIVER_ATIHDMI_NS:
2858 /* new ATI HDMI requires non-snoop */
2859 snoop = false;
2860 break;
2861 }
2862
2863 if (snoop != chip->snoop) {
2864 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2865 snoop ? "snoop" : "non-snoop");
2866 chip->snoop = snoop;
2867 }
2868}
669ba27a 2869
1da177e4
LT		 2870/*
2871 * constructor
2872 */
a98f90fd 2873static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2874 int dev, unsigned int driver_caps,
a98f90fd 2875 struct azx **rchip)
1da177e4 2876{
a98f90fd 2877 static struct snd_device_ops ops = {
1da177e4
LT		 2878 .dev_free = azx_dev_free,
2879 };
a82d51ed
TI		 2880 struct azx *chip;
2881 int err;
1da177e4
LT		 2882
2883 *rchip = NULL;
bcd72003 2884
927fc866
PM		 2885 err = pci_enable_device(pci);
2886 if (err < 0)
1da177e4
LT		 2887 return err;
2888
e560d8d8 2889 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2890 if (!chip) {
1da177e4
LT		 2891 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2892 pci_disable_device(pci);
2893 return -ENOMEM;
2894 }
2895
2896 spin_lock_init(&chip->reg_lock);
62932df8 2897 mutex_init(&chip->open_mutex);
1da177e4
LT		 2898 chip->card = card;
2899 chip->pci = pci;
2900 chip->irq = -1;
9477c58e
TI		 2901 chip->driver_caps = driver_caps;
2902 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2903 check_msi(chip);
555e219f 2904 chip->dev_index = dev;
9ad593f6 2905 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2906 INIT_LIST_HEAD(&chip->pcm_list);
a82d51ed 2907 init_vga_switcheroo(chip);
1da177e4 2908
beaffc39
SG		 2909 chip->position_fix[0] = chip->position_fix[1] =
2910 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 2911 /* combo mode uses LPIB for playback */
2912 if (chip->position_fix[0] == POS_FIX_COMBO) {
2913 chip->position_fix[0] = POS_FIX_LPIB;
2914 chip->position_fix[1] = POS_FIX_AUTO;
2915 }
2916
5aba4f8e 2917 check_probe_mask(chip, dev);
3372a153 2918
27346166 2919 chip->single_cmd = single_cmd;
27fe48d9 2920 chip->snoop = hda_snoop;
a1585d76 2921 azx_check_snoop_available(chip);
c74db86b 2922
5c0d7bc1
TI		 2923 if (bdl_pos_adj[dev] < 0) {
2924 switch (chip->driver_type) {
0c6341ac 2925 case AZX_DRIVER_ICH:
32679f95 2926 case AZX_DRIVER_PCH:
0c6341ac 2927 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2928 break;
2929 default:
0c6341ac 2930 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2931 break;
2932 }
2933 }
2934
a82d51ed
TI		 2935 if (check_hdmi_disabled(pci)) {
2936 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2937 pci_name(pci));
2938 if (use_vga_switcheroo(chip)) {
2939 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2940 chip->disabled = true;
2941 goto ok;
2942 }
2943 kfree(chip);
2944 pci_disable_device(pci);
2945 return -ENXIO;
2946 }
2947
2948 err = azx_first_init(chip);
2949 if (err < 0) {
2950 azx_free(chip);
2951 return err;
2952 }
2953
2954 ok:
2955 err = register_vga_switcheroo(chip);
2956 if (err < 0) {
2957 snd_printk(KERN_ERR SFX
2958 "Error registering VGA-switcheroo client\n");
2959 azx_free(chip);
2960 return err;
2961 }
2962
2963 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2964 if (err < 0) {
2965 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2966 azx_free(chip);
2967 return err;
2968 }
2969
2970 *rchip = chip;
2971 return 0;
2972}
2973
2974static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2975{
2976 int dev = chip->dev_index;
2977 struct pci_dev *pci = chip->pci;
2978 struct snd_card *card = chip->card;
2979 int i, err;
2980 unsigned short gcap;
2981
07e4ca50
TI		 2982#if BITS_PER_LONG != 64
2983 /* Fix up base address on ULI M5461 */
2984 if (chip->driver_type == AZX_DRIVER_ULI) {
2985 u16 tmp3;
2986 pci_read_config_word(pci, 0x40, &tmp3);
2987 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2988 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2989 }
2990#endif
2991
927fc866 2992 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 2993 if (err < 0)
1da177e4 2994 return err;
a82d51ed 2995 chip->region_requested = 1;
1da177e4 2996
927fc866 2997 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2998 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2999 if (chip->remap_addr == NULL) {
3000 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3001 return -ENXIO;
1da177e4
LT		 3002 }
3003
68e7fffc
TI		 3004 if (chip->msi)
3005 if (pci_enable_msi(pci) < 0)
3006 chip->msi = 0;
7376d013 3007
a82d51ed
TI		 3008 if (azx_acquire_irq(chip, 0) < 0)
3009 return -EBUSY;
1da177e4
LT		 3010
3011 pci_set_master(pci);
3012 synchronize_irq(chip->irq);
3013
bcd72003 3014 gcap = azx_readw(chip, GCAP);
4abc1cc2 3015 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3016
dc4c2e6b 3017 /* disable SB600 64bit support for safety */
9477c58e 3018 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3019 struct pci_dev *p_smbus;
3020 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3021 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3022 NULL);
3023 if (p_smbus) {
3024 if (p_smbus->revision < 0x30)
3025 gcap &= ~ICH6_GCAP_64OK;
3026 pci_dev_put(p_smbus);
3027 }
3028 }
09240cf4 3029
9477c58e
TI		 3030 /* disable 64bit DMA address on some devices */
3031 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3032 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3033 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3034 }
396087ea 3035
2ae66c26 3036 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3037 if (align_buffer_size >= 0)
3038 chip->align_buffer_size = !!align_buffer_size;
3039 else {
3040 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3041 chip->align_buffer_size = 0;
3042 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3043 chip->align_buffer_size = 1;
3044 else
3045 chip->align_buffer_size = 1;
3046 }
2ae66c26 3047
cf7aaca8 3048 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3049 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3050 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3051 else {
e930438c
YH		 3052 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3053 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3054 }
cf7aaca8 3055
8b6ed8e7
TI		 3056 /* read number of streams from GCAP register instead of using
3057 * hardcoded value
3058 */
3059 chip->capture_streams = (gcap >> 8) & 0x0f;
3060 chip->playback_streams = (gcap >> 12) & 0x0f;
3061 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3062 /* gcap didn't give any info, switching to old method */
3063
3064 switch (chip->driver_type) {
3065 case AZX_DRIVER_ULI:
3066 chip->playback_streams = ULI_NUM_PLAYBACK;
3067 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3068 break;
3069 case AZX_DRIVER_ATIHDMI:
1815b34a 3070 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3071 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3072 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3073 break;
c4da29ca 3074 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3075 default:
3076 chip->playback_streams = ICH6_NUM_PLAYBACK;
3077 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3078 break;
3079 }
07e4ca50 3080 }
8b6ed8e7
TI		 3081 chip->capture_index_offset = 0;
3082 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3083 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3084 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3085 GFP_KERNEL);
927fc866 3086 if (!chip->azx_dev) {
4abc1cc2 3087 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3088 return -ENOMEM;
07e4ca50
TI		 3089 }
3090
4ce107b9
TI		 3091 for (i = 0; i < chip->num_streams; i++) {
3092 /* allocate memory for the BDL for each stream */
3093 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3094 snd_dma_pci_data(chip->pci),
3095 BDL_SIZE, &chip->azx_dev[i].bdl);
3096 if (err < 0) {
3097 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3098 return -ENOMEM;
4ce107b9 3099 }
27fe48d9 3100 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3101 }
0be3b5d3 3102 /* allocate memory for the position buffer */
d01ce99f
TI		 3103 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3104 snd_dma_pci_data(chip->pci),
3105 chip->num_streams * 8, &chip->posbuf);
3106 if (err < 0) {
0be3b5d3 3107 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3108 return -ENOMEM;
1da177e4 3109 }
27fe48d9 3110 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3111 /* allocate CORB/RIRB */
81740861
TI		 3112 err = azx_alloc_cmd_io(chip);
3113 if (err < 0)
a82d51ed 3114 return err;
1da177e4
LT		 3115
3116 /* initialize streams */
3117 azx_init_stream(chip);
3118
3119 /* initialize chip */
cb53c626 3120 azx_init_pci(chip);
10e77dda 3121 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3122
3123 /* codec detection */
927fc866 3124 if (!chip->codec_mask) {
1da177e4 3125 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3126 return -ENODEV;
1da177e4
LT		 3127 }
3128
07e4ca50 3129 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3130 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3131 sizeof(card->shortname));
3132 snprintf(card->longname, sizeof(card->longname),
3133 "%s at 0x%lx irq %i",
3134 card->shortname, chip->addr, chip->irq);
07e4ca50 3135
1da177e4 3136 return 0;
1da177e4
LT		 3137}
3138
cb53c626
TI		 3139static void power_down_all_codecs(struct azx *chip)
3140{
3141#ifdef CONFIG_SND_HDA_POWER_SAVE
3142 /* The codecs were powered up in snd_hda_codec_new().
3143 * Now all initialization done, so turn them down if possible
3144 */
3145 struct hda_codec *codec;
3146 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3147 snd_hda_power_down(codec);
3148 }
3149#endif
3150}
3151
d01ce99f
TI		 3152static int __devinit azx_probe(struct pci_dev *pci,
3153 const struct pci_device_id *pci_id)
1da177e4 3154{
5aba4f8e 3155 static int dev;
a98f90fd
TI		 3156 struct snd_card *card;
3157 struct azx *chip;
927fc866 3158 int err;
1da177e4 3159
5aba4f8e
TI		 3160 if (dev >= SNDRV_CARDS)
3161 return -ENODEV;
3162 if (!enable[dev]) {
3163 dev++;
3164 return -ENOENT;
3165 }
3166
e58de7ba
TI		 3167 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3168 if (err < 0) {
1da177e4 3169 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3170 return err;
1da177e4
LT		 3171 }
3172
4ea6fbc8
TI		 3173 /* set this here since it's referred in snd_hda_load_patch() */
3174 snd_card_set_dev(card, &pci->dev);
3175
5aba4f8e 3176 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3177 if (err < 0)
3178 goto out_free;
421a1252 3179 card->private_data = chip;
1da177e4 3180
a82d51ed
TI		 3181 if (!chip->disabled) {
3182 err = azx_probe_continue(chip);
3183 if (err < 0)
3184 goto out_free;
3185 }
3186
3187 pci_set_drvdata(pci, card);
3188
3189 dev++;
3190 return 0;
3191
3192out_free:
3193 snd_card_free(card);
3194 return err;
3195}
3196
3197static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3198{
3199 int dev = chip->dev_index;
3200 int err;
3201
2dca0bba
JK		 3202#ifdef CONFIG_SND_HDA_INPUT_BEEP
3203 chip->beep_mode = beep_mode[dev];
3204#endif
3205
1da177e4 3206 /* create codec instances */
a1e21c90 3207 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3208 if (err < 0)
3209 goto out_free;
4ea6fbc8 3210#ifdef CONFIG_SND_HDA_PATCH_LOADER
41a63f18 3211 if (patch[dev] && *patch[dev]) {
4ea6fbc8
TI		 3212 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3213 patch[dev]);
3214 err = snd_hda_load_patch(chip->bus, patch[dev]);
3215 if (err < 0)
3216 goto out_free;
3217 }
3218#endif
10e77dda 3219 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3220 err = azx_codec_configure(chip);
3221 if (err < 0)
3222 goto out_free;
3223 }
1da177e4
LT		 3224
3225 /* create PCM streams */
176d5335 3226 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3227 if (err < 0)
3228 goto out_free;
1da177e4
LT		 3229
3230 /* create mixer controls */
d01ce99f 3231 err = azx_mixer_create(chip);
41dda0fd
WF		 3232 if (err < 0)
3233 goto out_free;
1da177e4 3234
a82d51ed 3235 err = snd_card_register(chip->card);
41dda0fd
WF		 3236 if (err < 0)
3237 goto out_free;
1da177e4 3238
cb53c626
TI		 3239 chip->running = 1;
3240 power_down_all_codecs(chip);
0cbf0098 3241 azx_notifier_register(chip);
1da177e4 3242
9121947d
TI		 3243 return 0;
3244
41dda0fd 3245out_free:
a82d51ed 3246 chip->init_failed = 1;
41dda0fd 3247 return err;
1da177e4
LT		 3248}
3249
3250static void __devexit azx_remove(struct pci_dev *pci)
3251{
9121947d
TI		 3252 struct snd_card *card = pci_get_drvdata(pci);
3253 if (card)
3254 snd_card_free(card);
1da177e4
LT		 3255 pci_set_drvdata(pci, NULL);
3256}
3257
3258/* PCI IDs */
cebe41d4 3259static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3260 /* CPT */
9477c58e 3261 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26 3262 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3263 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
cea310e8 3264 /* PBG */
9477c58e 3265 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3266 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3267 AZX_DCAPS_BUFSIZE},
d2edeb7c 3268 /* Panther Point */
9477c58e 3269 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3270 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3271 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
8bc039a1
SH		 3272 /* Lynx Point */
3273 { PCI_DEVICE(0x8086, 0x8c20),
3274 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3275 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
144dad99
JR		 3276 /* Lynx Point-LP */
3277 { PCI_DEVICE(0x8086, 0x9c20),
3278 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3279 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3280 /* Lynx Point-LP */
3281 { PCI_DEVICE(0x8086, 0x9c21),
3282 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3283 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
e926f2c8
WX		 3284 /* Haswell */
3285 { PCI_DEVICE(0x8086, 0x0c0c),
bdbe34de 3286 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
e926f2c8 3287 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
87218e9c 3288 /* SCH */
9477c58e 3289 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3290 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3291 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3292 { PCI_DEVICE(0x8086, 0x080a),
3293 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3294 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3295 /* ICH */
8b0bd226 3296 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3297 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3298 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3299 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3300 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3301 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3302 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3303 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3304 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3305 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3306 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3307 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3308 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3309 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3310 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3311 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3312 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3313 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3314 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3315 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3316 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3317 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3318 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3319 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3320 /* Generic Intel */
3321 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3322 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3323 .class_mask = 0xffffff,
2ae66c26 3324 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3325 /* ATI SB 450/600/700/800/900 */
3326 { PCI_DEVICE(0x1002, 0x437b),
3327 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3328 { PCI_DEVICE(0x1002, 0x4383),
3329 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3330 /* AMD Hudson */
3331 { PCI_DEVICE(0x1022, 0x780d),
3332 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3333 /* ATI HDMI */
9477c58e
TI		 3334 { PCI_DEVICE(0x1002, 0x793b),
3335 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3336 { PCI_DEVICE(0x1002, 0x7919),
3337 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3338 { PCI_DEVICE(0x1002, 0x960f),
3339 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3340 { PCI_DEVICE(0x1002, 0x970f),
3341 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3342 { PCI_DEVICE(0x1002, 0xaa00),
3343 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3344 { PCI_DEVICE(0x1002, 0xaa08),
3345 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3346 { PCI_DEVICE(0x1002, 0xaa10),
3347 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3348 { PCI_DEVICE(0x1002, 0xaa18),
3349 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3350 { PCI_DEVICE(0x1002, 0xaa20),
3351 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3352 { PCI_DEVICE(0x1002, 0xaa28),
3353 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3354 { PCI_DEVICE(0x1002, 0xaa30),
3355 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3356 { PCI_DEVICE(0x1002, 0xaa38),
3357 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3358 { PCI_DEVICE(0x1002, 0xaa40),
3359 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3360 { PCI_DEVICE(0x1002, 0xaa48),
3361 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3362 { PCI_DEVICE(0x1002, 0x9902),
3363 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3364 { PCI_DEVICE(0x1002, 0xaaa0),
3365 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3366 { PCI_DEVICE(0x1002, 0xaaa8),
3367 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3368 { PCI_DEVICE(0x1002, 0xaab0),
3369 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3370 /* VIA VT8251/VT8237A */
9477c58e
TI		 3371 { PCI_DEVICE(0x1106, 0x3288),
3372 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3373 /* VIA GFX VT7122/VX900 */
3374 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3375 /* VIA GFX VT6122/VX11 */
3376 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3377 /* SIS966 */
3378 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3379 /* ULI M5461 */
3380 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3381 /* NVIDIA MCP */
0c2fd1bf
TI		 3382 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3383 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3384 .class_mask = 0xffffff,
9477c58e 3385 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3386 /* Teradici */
9477c58e
TI		 3387 { PCI_DEVICE(0x6549, 0x1200),
3388 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3389 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3390 /* CTHDA chips */
3391 { PCI_DEVICE(0x1102, 0x0010),
3392 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3393 { PCI_DEVICE(0x1102, 0x0012),
3394 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3395#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3396 /* the following entry conflicts with snd-ctxfi driver,
3397 * as ctxfi driver mutates from HD-audio to native mode with
3398 * a special command sequence.
3399 */
4e01f54b
TI		 3400 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3401 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3402 .class_mask = 0xffffff,
9477c58e 3403 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3404 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3405#else
3406 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3407 { PCI_DEVICE(0x1102, 0x0009),
3408 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3409 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3410#endif
e35d4b11
OS		 3411 /* Vortex86MX */
3412 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3413 /* VMware HDAudio */
3414 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3415 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3416 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3417 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3418 .class_mask = 0xffffff,
9477c58e 3419 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3420 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3421 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3422 .class_mask = 0xffffff,
9477c58e 3423 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3424 { 0, }
3425};
3426MODULE_DEVICE_TABLE(pci, azx_ids);
3427
3428/* pci_driver definition */
e9f66d9b 3429static struct pci_driver azx_driver = {
3733e424 3430 .name = KBUILD_MODNAME,
1da177e4
LT		 3431 .id_table = azx_ids,
3432 .probe = azx_probe,
3433 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3434 .driver = {
3435 .pm = AZX_PM_OPS,
3436 },
1da177e4
LT		 3437};
3438
e9f66d9b 3439module_pci_driver(azx_driver);
Linux kernel - Deliverables
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