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Merge 2.6.38-rc5 into staging-next
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
4cb36310
DH		 81MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 87module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
d2f2fcd2 128 "{Intel, CPT},"
cea310e8 129 "{Intel, PBG},"
4979bca9 130 "{Intel, SCH},"
fc20a562 131 "{ATI, SB450},"
89be83f8 132 "{ATI, SB600},"
778b6e1b 133 "{ATI, RS600},"
5b15c95f 134 "{ATI, RS690},"
e6db1119
WL		 135 "{ATI, RS780},"
136 "{ATI, R600},"
2797f724
HRK		 137 "{ATI, RV630},"
138 "{ATI, RV610},"
27da1834
WL		 139 "{ATI, RV670},"
140 "{ATI, RV635},"
141 "{ATI, RV620},"
142 "{ATI, RV770},"
fc20a562 143 "{VIA, VT8251},"
47672310 144 "{VIA, VT8237A},"
07e4ca50
TI		 145 "{SiS, SIS966},"
146 "{ULI, M5461}}");
1da177e4
LT		 147MODULE_DESCRIPTION("Intel HDA driver");
148
4abc1cc2
TI		 149#ifdef CONFIG_SND_VERBOSE_PRINTK
150#define SFX /* nop */
151#else
1da177e4 152#define SFX "hda-intel: "
4abc1cc2 153#endif
cb53c626 154
1da177e4
LT		 155/*
156 * registers
157 */
158#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 159#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
160#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
161#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
162#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
163#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 164#define ICH6_REG_VMIN 0x02
165#define ICH6_REG_VMAJ 0x03
166#define ICH6_REG_OUTPAY 0x04
167#define ICH6_REG_INPAY 0x06
168#define ICH6_REG_GCTL 0x08
8a933ece 169#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 170#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
171#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 172#define ICH6_REG_WAKEEN 0x0c
173#define ICH6_REG_STATESTS 0x0e
174#define ICH6_REG_GSTS 0x10
b21fadb9 175#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 176#define ICH6_REG_INTCTL 0x20
177#define ICH6_REG_INTSTS 0x24
e5463720 178#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
1da177e4
LT		 179#define ICH6_REG_SYNC 0x34
180#define ICH6_REG_CORBLBASE 0x40
181#define ICH6_REG_CORBUBASE 0x44
182#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 183#define ICH6_REG_CORBRP 0x4a
184#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 185#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 186#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
187#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 188#define ICH6_REG_CORBSTS 0x4d
b21fadb9 189#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 190#define ICH6_REG_CORBSIZE 0x4e
191
192#define ICH6_REG_RIRBLBASE 0x50
193#define ICH6_REG_RIRBUBASE 0x54
194#define ICH6_REG_RIRBWP 0x58
b21fadb9 195#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 196#define ICH6_REG_RINTCNT 0x5a
197#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 198#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
199#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
200#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 201#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 202#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
203#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 204#define ICH6_REG_RIRBSIZE 0x5e
205
206#define ICH6_REG_IC 0x60
207#define ICH6_REG_IR 0x64
208#define ICH6_REG_IRS 0x68
209#define ICH6_IRS_VALID (1<<1)
210#define ICH6_IRS_BUSY (1<<0)
211
212#define ICH6_REG_DPLBASE 0x70
213#define ICH6_REG_DPUBASE 0x74
214#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
215
216/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
217enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
218
219/* stream register offsets from stream base */
220#define ICH6_REG_SD_CTL 0x00
221#define ICH6_REG_SD_STS 0x03
222#define ICH6_REG_SD_LPIB 0x04
223#define ICH6_REG_SD_CBL 0x08
224#define ICH6_REG_SD_LVI 0x0c
225#define ICH6_REG_SD_FIFOW 0x0e
226#define ICH6_REG_SD_FIFOSIZE 0x10
227#define ICH6_REG_SD_FORMAT 0x12
228#define ICH6_REG_SD_BDLPL 0x18
229#define ICH6_REG_SD_BDLPU 0x1c
230
231/* PCI space */
232#define ICH6_PCIREG_TCSEL 0x44
233
234/*
235 * other constants
236 */
237
238/* max number of SDs */
07e4ca50 239/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 240#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 241#define ICH6_NUM_PLAYBACK 4
242
243/* ULI has 6 playback and 5 capture */
07e4ca50 244#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 245#define ULI_NUM_PLAYBACK 6
246
778b6e1b 247/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 248#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 249#define ATIHDMI_NUM_PLAYBACK 1
250
f269002e
KY		 251/* TERA has 4 playback and 3 capture */
252#define TERA_NUM_CAPTURE 3
253#define TERA_NUM_PLAYBACK 4
254
07e4ca50
TI		 255/* this number is statically defined for simplicity */
256#define MAX_AZX_DEV 16
257
1da177e4 258/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 259#define BDL_SIZE 4096
260#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
261#define AZX_MAX_FRAG 32
1da177e4
LT		 262/* max buffer size - no h/w limit, you can increase as you like */
263#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 264
265/* RIRB int mask: overrun[2], response[0] */
266#define RIRB_INT_RESPONSE 0x01
267#define RIRB_INT_OVERRUN 0x04
268#define RIRB_INT_MASK 0x05
269
2f5983f2 270/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 271#define AZX_MAX_CODECS 8
272#define AZX_DEFAULT_CODECS 4
deadff16 273#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 274
275/* SD_CTL bits */
276#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
277#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 278#define SD_CTL_STRIPE (3 << 16) /* stripe control */
279#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
280#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 281#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
282#define SD_CTL_STREAM_TAG_SHIFT 20
283
284/* SD_CTL and SD_STS */
285#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
286#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
287#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 288#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
289 SD_INT_COMPLETE)
1da177e4
LT		 290
291/* SD_STS */
292#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
293
294/* INTCTL and INTSTS */
d01ce99f
TI		 295#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
296#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
297#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 298
1da177e4
LT		 299/* below are so far hardcoded - should read registers in future */
300#define ICH6_MAX_CORB_ENTRIES 256
301#define ICH6_MAX_RIRB_ENTRIES 256
302
c74db86b
TI		 303/* position fix mode */
304enum {
0be3b5d3 305 POS_FIX_AUTO,
d2e1c973 306 POS_FIX_LPIB,
0be3b5d3 307 POS_FIX_POSBUF,
4cb36310 308 POS_FIX_VIACOMBO,
c74db86b 309};
1da177e4 310
f5d40b30 311/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 312#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
313#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
314
da3fca21
V		 315/* Defines for Nvidia HDA support */
316#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
317#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 318#define NVIDIA_HDA_ISTRM_COH 0x4d
319#define NVIDIA_HDA_OSTRM_COH 0x4c
320#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 321
90a5ad52
TI		 322/* Defines for Intel SCH HDA snoop control */
323#define INTEL_SCH_HDA_DEVC 0x78
324#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
325
0e153474
JC		 326/* Define IN stream 0 FIFO size offset in VIA controller */
327#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
328/* Define VIA HD Audio Device ID*/
329#define VIA_HDAC_DEVICE_ID 0x3288
330
c4da29ca
YL		 331/* HD Audio class code */
332#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 333
1da177e4
LT		 334/*
335 */
336
a98f90fd 337struct azx_dev {
4ce107b9 338 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 339 u32 *posbuf; /* position buffer pointer */
1da177e4 340
d01ce99f 341 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 342 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 343 unsigned int frags; /* number for period in the play buffer */
344 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 345 unsigned long start_wallclk; /* start + minimum wallclk */
346 unsigned long period_wallclk; /* wallclk for period */
1da177e4 347
d01ce99f 348 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 349
d01ce99f 350 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 351
352 /* pcm support */
d01ce99f
TI		 353 struct snd_pcm_substream *substream; /* assigned substream,
354 * set in PCM open
355 */
356 unsigned int format_val; /* format value to be set in the
357 * controller and the codec
358 */
1da177e4
LT		 359 unsigned char stream_tag; /* assigned stream */
360 unsigned char index; /* stream index */
ef18bede 361 int device; /* last device number assigned to */
1da177e4 362
927fc866
PM		 363 unsigned int opened :1;
364 unsigned int running :1;
675f25d4 365 unsigned int irq_pending :1;
0e153474
JC		 366 /*
367 * For VIA:
368 * A flag to ensure DMA position is 0
369 * when link position is not greater than FIFO size
370 */
371 unsigned int insufficient :1;
1da177e4
LT		 372};
373
374/* CORB/RIRB */
a98f90fd 375struct azx_rb {
1da177e4
LT		 376 u32 *buf; /* CORB/RIRB buffer
377 * Each CORB entry is 4byte, RIRB is 8byte
378 */
379 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
380 /* for RIRB */
381 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 382 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
383 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 384};
385
a98f90fd
TI		 386struct azx {
387 struct snd_card *card;
1da177e4 388 struct pci_dev *pci;
555e219f 389 int dev_index;
1da177e4 390
07e4ca50
TI		 391 /* chip type specific */
392 int driver_type;
393 int playback_streams;
394 int playback_index_offset;
395 int capture_streams;
396 int capture_index_offset;
397 int num_streams;
398
1da177e4
LT		 399 /* pci resources */
400 unsigned long addr;
401 void __iomem *remap_addr;
402 int irq;
403
404 /* locks */
405 spinlock_t reg_lock;
62932df8 406 struct mutex open_mutex;
1da177e4 407
07e4ca50 408 /* streams (x num_streams) */
a98f90fd 409 struct azx_dev *azx_dev;
1da177e4
LT		 410
411 /* PCM */
c8936222 412 struct snd_pcm *pcm[HDA_MAX_PCMS];
1da177e4
LT		 413
414 /* HD codec */
415 unsigned short codec_mask;
f1eaaeec 416 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 417 struct hda_bus *bus;
2dca0bba 418 unsigned int beep_mode;
1da177e4
LT		 419
420 /* CORB/RIRB */
a98f90fd
TI		 421 struct azx_rb corb;
422 struct azx_rb rirb;
1da177e4 423
4ce107b9 424 /* CORB/RIRB and position buffers */
1da177e4
LT		 425 struct snd_dma_buffer rb;
426 struct snd_dma_buffer posbuf;
c74db86b
TI		 427
428 /* flags */
beaffc39 429 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 430 int poll_count;
cb53c626 431 unsigned int running :1;
927fc866
PM		 432 unsigned int initialized :1;
433 unsigned int single_cmd :1;
434 unsigned int polling_mode :1;
68e7fffc 435 unsigned int msi :1;
a6a950a8 436 unsigned int irq_pending_warned :1;
6ce4a3bc 437 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 438
439 /* for debugging */
feb27340 440 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
0cbf0098
TI		 444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
1da177e4
LT		 447};
448
07e4ca50
TI		 449/* driver types */
450enum {
451 AZX_DRIVER_ICH,
32679f95 452 AZX_DRIVER_PCH,
4979bca9 453 AZX_DRIVER_SCH,
07e4ca50 454 AZX_DRIVER_ATI,
778b6e1b 455 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
da3fca21 459 AZX_DRIVER_NVIDIA,
f269002e 460 AZX_DRIVER_TERA,
14d34f16 461 AZX_DRIVER_CTX,
c4da29ca 462 AZX_DRIVER_GENERIC,
2f5983f2 463 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 464};
465
466static char *driver_short_names[] __devinitdata = {
467 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 468 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 469 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 470 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 471 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 472 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
473 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 474 [AZX_DRIVER_ULI] = "HDA ULI M5461",
475 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 476 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 477 [AZX_DRIVER_CTX] = "HDA Creative",
c4da29ca 478 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 479};
480
1da177e4
LT		 481/*
482 * macros for easy use
483 */
484#define azx_writel(chip,reg,value) \
485 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
486#define azx_readl(chip,reg) \
487 readl((chip)->remap_addr + ICH6_REG_##reg)
488#define azx_writew(chip,reg,value) \
489 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
490#define azx_readw(chip,reg) \
491 readw((chip)->remap_addr + ICH6_REG_##reg)
492#define azx_writeb(chip,reg,value) \
493 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
494#define azx_readb(chip,reg) \
495 readb((chip)->remap_addr + ICH6_REG_##reg)
496
497#define azx_sd_writel(dev,reg,value) \
498 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
499#define azx_sd_readl(dev,reg) \
500 readl((dev)->sd_addr + ICH6_REG_##reg)
501#define azx_sd_writew(dev,reg,value) \
502 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
503#define azx_sd_readw(dev,reg) \
504 readw((dev)->sd_addr + ICH6_REG_##reg)
505#define azx_sd_writeb(dev,reg,value) \
506 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
507#define azx_sd_readb(dev,reg) \
508 readb((dev)->sd_addr + ICH6_REG_##reg)
509
510/* for pcm support */
a98f90fd 511#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 512
68e7fffc 513static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 514static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 515/*
516 * Interface for HD codec
517 */
518
1da177e4
LT		 519/*
520 * CORB / RIRB interface
521 */
a98f90fd 522static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 523{
524 int err;
525
526 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 527 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
528 snd_dma_pci_data(chip->pci),
1da177e4
LT		 529 PAGE_SIZE, &chip->rb);
530 if (err < 0) {
531 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
532 return err;
533 }
534 return 0;
535}
536
a98f90fd 537static void azx_init_cmd_io(struct azx *chip)
1da177e4 538{
cdb1fbf2 539 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 540 /* CORB set up */
541 chip->corb.addr = chip->rb.addr;
542 chip->corb.buf = (u32 *)chip->rb.area;
543 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 544 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 545
07e4ca50
TI		 546 /* set the corb size to 256 entries (ULI requires explicitly) */
547 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 548 /* set the corb write pointer to 0 */
549 azx_writew(chip, CORBWP, 0);
550 /* reset the corb hw read pointer */
b21fadb9 551 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 552 /* enable corb dma */
b21fadb9 553 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 554
555 /* RIRB set up */
556 chip->rirb.addr = chip->rb.addr + 2048;
557 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 558 chip->rirb.wp = chip->rirb.rp = 0;
559 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 560 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 561 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 562
07e4ca50
TI		 563 /* set the rirb size to 256 entries (ULI requires explicitly) */
564 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 565 /* reset the rirb hw write pointer */
b21fadb9 566 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 567 /* set N=1, get RIRB response interrupt for new entry */
14d34f16
TI		 568 if (chip->driver_type == AZX_DRIVER_CTX)
569 azx_writew(chip, RINTCNT, 0xc0);
570 else
571 azx_writew(chip, RINTCNT, 1);
1da177e4 572 /* enable rirb dma and response irq */
1da177e4 573 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 574 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 575}
576
a98f90fd 577static void azx_free_cmd_io(struct azx *chip)
1da177e4 578{
cdb1fbf2 579 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 580 /* disable ringbuffer DMAs */
581 azx_writeb(chip, RIRBCTL, 0);
582 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 583 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 584}
585
deadff16
WF		 586static unsigned int azx_command_addr(u32 cmd)
587{
588 unsigned int addr = cmd >> 28;
589
590 if (addr >= AZX_MAX_CODECS) {
591 snd_BUG();
592 addr = 0;
593 }
594
595 return addr;
596}
597
598static unsigned int azx_response_addr(u32 res)
599{
600 unsigned int addr = res & 0xf;
601
602 if (addr >= AZX_MAX_CODECS) {
603 snd_BUG();
604 addr = 0;
605 }
606
607 return addr;
1da177e4
LT		 608}
609
610/* send a command */
33fa35ed 611static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 612{
33fa35ed 613 struct azx *chip = bus->private_data;
deadff16 614 unsigned int addr = azx_command_addr(val);
1da177e4 615 unsigned int wp;
1da177e4 616
c32649fe
WF		 617 spin_lock_irq(&chip->reg_lock);
618
1da177e4
LT		 619 /* add command to corb */
620 wp = azx_readb(chip, CORBWP);
621 wp++;
622 wp %= ICH6_MAX_CORB_ENTRIES;
623
deadff16 624 chip->rirb.cmds[addr]++;
1da177e4
LT		 625 chip->corb.buf[wp] = cpu_to_le32(val);
626 azx_writel(chip, CORBWP, wp);
c32649fe 627
1da177e4
LT		 628 spin_unlock_irq(&chip->reg_lock);
629
630 return 0;
631}
632
633#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
634
635/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 636static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 637{
638 unsigned int rp, wp;
deadff16 639 unsigned int addr;
1da177e4
LT		 640 u32 res, res_ex;
641
642 wp = azx_readb(chip, RIRBWP);
643 if (wp == chip->rirb.wp)
644 return;
645 chip->rirb.wp = wp;
deadff16 646
1da177e4
LT		 647 while (chip->rirb.rp != wp) {
648 chip->rirb.rp++;
649 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
650
651 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
652 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
653 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 654 addr = azx_response_addr(res_ex);
1da177e4
LT		 655 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
656 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 657 else if (chip->rirb.cmds[addr]) {
658 chip->rirb.res[addr] = res;
2add9b92 659 smp_wmb();
deadff16 660 chip->rirb.cmds[addr]--;
e310bb06
WF		 661 } else
662 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
663 "last cmd=%#08x\n",
664 res, res_ex,
665 chip->last_cmd[addr]);
1da177e4
LT		 666 }
667}
668
669/* receive a response */
deadff16
WF		 670static unsigned int azx_rirb_get_response(struct hda_bus *bus,
671 unsigned int addr)
1da177e4 672{
33fa35ed 673 struct azx *chip = bus->private_data;
5c79b1f8 674 unsigned long timeout;
1eb6dc7d 675 int do_poll = 0;
1da177e4 676
5c79b1f8
TI		 677 again:
678 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 679 for (;;) {
1eb6dc7d 680 if (chip->polling_mode || do_poll) {
e96224ae
TI		 681 spin_lock_irq(&chip->reg_lock);
682 azx_update_rirb(chip);
683 spin_unlock_irq(&chip->reg_lock);
684 }
deadff16 685 if (!chip->rirb.cmds[addr]) {
2add9b92 686 smp_rmb();
b613291f 687 bus->rirb_error = 0;
1eb6dc7d
ML		 688
689 if (!do_poll)
690 chip->poll_count = 0;
deadff16 691 return chip->rirb.res[addr]; /* the last value */
2add9b92 692 }
28a0d9df
TI		 693 if (time_after(jiffies, timeout))
694 break;
33fa35ed 695 if (bus->needs_damn_long_delay)
52987656
TI		 696 msleep(2); /* temporary workaround */
697 else {
698 udelay(10);
699 cond_resched();
700 }
28a0d9df 701 }
5c79b1f8 702
1eb6dc7d
ML		 703 if (!chip->polling_mode && chip->poll_count < 2) {
704 snd_printdd(SFX "azx_get_response timeout, "
705 "polling the codec once: last cmd=0x%08x\n",
706 chip->last_cmd[addr]);
707 do_poll = 1;
708 chip->poll_count++;
709 goto again;
710 }
711
712
23c4a881
TI		 713 if (!chip->polling_mode) {
714 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
715 "switching to polling mode: last cmd=0x%08x\n",
716 chip->last_cmd[addr]);
717 chip->polling_mode = 1;
718 goto again;
719 }
720
68e7fffc 721 if (chip->msi) {
4abc1cc2 722 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 723 "disabling MSI: last cmd=0x%08x\n",
724 chip->last_cmd[addr]);
68e7fffc
TI		 725 free_irq(chip->irq, chip);
726 chip->irq = -1;
727 pci_disable_msi(chip->pci);
728 chip->msi = 0;
b613291f
TI		 729 if (azx_acquire_irq(chip, 1) < 0) {
730 bus->rirb_error = 1;
68e7fffc 731 return -1;
b613291f 732 }
68e7fffc
TI		 733 goto again;
734 }
735
6ce4a3bc
TI		 736 if (chip->probing) {
737 /* If this critical timeout happens during the codec probing
738 * phase, this is likely an access to a non-existing codec
739 * slot. Better to return an error and reset the system.
740 */
741 return -1;
742 }
743
8dd78330
TI		 744 /* a fatal communication error; need either to reset or to fallback
745 * to the single_cmd mode
746 */
b613291f 747 bus->rirb_error = 1;
b20f3b83 748 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 749 bus->response_reset = 1;
750 return -1; /* give a chance to retry */
751 }
752
753 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
754 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 755 chip->last_cmd[addr]);
8dd78330
TI		 756 chip->single_cmd = 1;
757 bus->response_reset = 0;
1a696978 758 /* release CORB/RIRB */
4fcd3920 759 azx_free_cmd_io(chip);
1a696978
TI		 760 /* disable unsolicited responses */
761 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 762 return -1;
1da177e4
LT		 763}
764
1da177e4
LT		 765/*
766 * Use the single immediate command instead of CORB/RIRB for simplicity
767 *
768 * Note: according to Intel, this is not preferred use. The command was
769 * intended for the BIOS only, and may get confused with unsolicited
770 * responses. So, we shouldn't use it for normal operation from the
771 * driver.
772 * I left the codes, however, for debugging/testing purposes.
773 */
774
b05a7d4f 775/* receive a response */
deadff16 776static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 777{
778 int timeout = 50;
779
780 while (timeout--) {
781 /* check IRV busy bit */
782 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
783 /* reuse rirb.res as the response return value */
deadff16 784 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 785 return 0;
786 }
787 udelay(1);
788 }
789 if (printk_ratelimit())
790 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
791 azx_readw(chip, IRS));
deadff16 792 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 793 return -EIO;
794}
795
1da177e4 796/* send a command */
33fa35ed 797static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 798{
33fa35ed 799 struct azx *chip = bus->private_data;
deadff16 800 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 801 int timeout = 50;
802
8dd78330 803 bus->rirb_error = 0;
1da177e4
LT		 804 while (timeout--) {
805 /* check ICB busy bit */
d01ce99f 806 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 807 /* Clear IRV valid bit */
d01ce99f
TI		 808 azx_writew(chip, IRS, azx_readw(chip, IRS) |
809 ICH6_IRS_VALID);
1da177e4 810 azx_writel(chip, IC, val);
d01ce99f
TI		 811 azx_writew(chip, IRS, azx_readw(chip, IRS) |
812 ICH6_IRS_BUSY);
deadff16 813 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 814 }
815 udelay(1);
816 }
1cfd52bc
MB		 817 if (printk_ratelimit())
818 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
819 azx_readw(chip, IRS), val);
1da177e4
LT		 820 return -EIO;
821}
822
823/* receive a response */
deadff16
WF		 824static unsigned int azx_single_get_response(struct hda_bus *bus,
825 unsigned int addr)
1da177e4 826{
33fa35ed 827 struct azx *chip = bus->private_data;
deadff16 828 return chip->rirb.res[addr];
1da177e4
LT		 829}
830
111d3af5
TI		 831/*
832 * The below are the main callbacks from hda_codec.
833 *
834 * They are just the skeleton to call sub-callbacks according to the
835 * current setting of chip->single_cmd.
836 */
837
838/* send a command */
33fa35ed 839static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 840{
33fa35ed 841 struct azx *chip = bus->private_data;
43bbb6cc 842
feb27340 843 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 844 if (chip->single_cmd)
33fa35ed 845 return azx_single_send_cmd(bus, val);
111d3af5 846 else
33fa35ed 847 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 848}
849
850/* get a response */
deadff16
WF		 851static unsigned int azx_get_response(struct hda_bus *bus,
852 unsigned int addr)
111d3af5 853{
33fa35ed 854 struct azx *chip = bus->private_data;
111d3af5 855 if (chip->single_cmd)
deadff16 856 return azx_single_get_response(bus, addr);
111d3af5 857 else
deadff16 858 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 859}
860
cb53c626 861#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 862static void azx_power_notify(struct hda_bus *bus);
cb53c626 863#endif
111d3af5 864
1da177e4 865/* reset codec link */
cd508fe5 866static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 867{
868 int count;
869
cd508fe5
JK		 870 if (!full_reset)
871 goto __skip;
872
e8a7f136
DT		 873 /* clear STATESTS */
874 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
875
1da177e4
LT		 876 /* reset controller */
877 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
878
879 count = 50;
880 while (azx_readb(chip, GCTL) && --count)
881 msleep(1);
882
883 /* delay for >= 100us for codec PLL to settle per spec
884 * Rev 0.9 section 5.5.1
885 */
886 msleep(1);
887
888 /* Bring controller out of reset */
889 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
890
891 count = 50;
927fc866 892 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 893 msleep(1);
894
927fc866 895 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 896 msleep(1);
897
cd508fe5 898 __skip:
1da177e4 899 /* check to see if controller is ready */
927fc866 900 if (!azx_readb(chip, GCTL)) {
4abc1cc2 901 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 902 return -EBUSY;
903 }
904
41e2fce4 905 /* Accept unsolicited responses */
1a696978
TI		 906 if (!chip->single_cmd)
907 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
908 ICH6_GCTL_UNSOL);
41e2fce4 909
1da177e4 910 /* detect codecs */
927fc866 911 if (!chip->codec_mask) {
1da177e4 912 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 913 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 914 }
915
916 return 0;
917}
918
919
920/*
921 * Lowlevel interface
922 */
923
924/* enable interrupts */
a98f90fd 925static void azx_int_enable(struct azx *chip)
1da177e4
LT		 926{
927 /* enable controller CIE and GIE */
928 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
929 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
930}
931
932/* disable interrupts */
a98f90fd 933static void azx_int_disable(struct azx *chip)
1da177e4
LT		 934{
935 int i;
936
937 /* disable interrupts in stream descriptor */
07e4ca50 938 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 939 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 940 azx_sd_writeb(azx_dev, SD_CTL,
941 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
942 }
943
944 /* disable SIE for all streams */
945 azx_writeb(chip, INTCTL, 0);
946
947 /* disable controller CIE and GIE */
948 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
949 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
950}
951
952/* clear interrupts */
a98f90fd 953static void azx_int_clear(struct azx *chip)
1da177e4
LT		 954{
955 int i;
956
957 /* clear stream status */
07e4ca50 958 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 959 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 960 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
961 }
962
963 /* clear STATESTS */
964 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
965
966 /* clear rirb status */
967 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
968
969 /* clear int status */
970 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
971}
972
973/* start a stream */
a98f90fd 974static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 975{
0e153474
JC		 976 /*
977 * Before stream start, initialize parameter
978 */
979 azx_dev->insufficient = 1;
980
1da177e4 981 /* enable SIE */
ccc5df05
WN		 982 azx_writel(chip, INTCTL,
983 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 984 /* set DMA start and interrupt mask */
985 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
986 SD_CTL_DMA_START | SD_INT_MASK);
987}
988
1dddab40
TI		 989/* stop DMA */
990static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 991{
1da177e4
LT		 992 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
993 ~(SD_CTL_DMA_START | SD_INT_MASK));
994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 995}
996
997/* stop a stream */
998static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
999{
1000 azx_stream_clear(chip, azx_dev);
1da177e4 1001 /* disable SIE */
ccc5df05
WN		 1002 azx_writel(chip, INTCTL,
1003 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1004}
1005
1006
1007/*
cb53c626 1008 * reset and start the controller registers
1da177e4 1009 */
cd508fe5 1010static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1011{
cb53c626
TI		 1012 if (chip->initialized)
1013 return;
1da177e4
LT		 1014
1015 /* reset controller */
cd508fe5 1016 azx_reset(chip, full_reset);
1da177e4
LT		 1017
1018 /* initialize interrupts */
1019 azx_int_clear(chip);
1020 azx_int_enable(chip);
1021
1022 /* initialize the codec command I/O */
1a696978
TI		 1023 if (!chip->single_cmd)
1024 azx_init_cmd_io(chip);
1da177e4 1025
0be3b5d3
TI		 1026 /* program the position buffer */
1027 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1028 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1029
cb53c626
TI		 1030 chip->initialized = 1;
1031}
1032
1033/*
1034 * initialize the PCI registers
1035 */
1036/* update bits in a PCI register byte */
1037static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1038 unsigned char mask, unsigned char val)
1039{
1040 unsigned char data;
1041
1042 pci_read_config_byte(pci, reg, &data);
1043 data &= ~mask;
1044 data |= (val & mask);
1045 pci_write_config_byte(pci, reg, data);
1046}
1047
1048static void azx_init_pci(struct azx *chip)
1049{
90a5ad52
TI		 1050 unsigned short snoop;
1051
cb53c626
TI		 1052 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054 * Ensuring these bits are 0 clears playback static on some HD Audio
1055 * codecs
1056 */
1057 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1058
da3fca21
V		 1059 switch (chip->driver_type) {
1060 case AZX_DRIVER_ATI:
1061 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1062 update_pci_byte(chip->pci,
1063 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1064 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1065 break;
1066 case AZX_DRIVER_NVIDIA:
1067 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1068 update_pci_byte(chip->pci,
1069 NVIDIA_HDA_TRANSREG_ADDR,
1070 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1071 update_pci_byte(chip->pci,
1072 NVIDIA_HDA_ISTRM_COH,
1073 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1074 update_pci_byte(chip->pci,
1075 NVIDIA_HDA_OSTRM_COH,
1076 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1077 break;
90a5ad52 1078 case AZX_DRIVER_SCH:
32679f95 1079 case AZX_DRIVER_PCH:
90a5ad52
TI		 1080 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1081 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1082 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1083 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1084 pci_read_config_word(chip->pci,
1085 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1086 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1087 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1088 ? "Failed" : "OK");
1089 }
1090 break;
1091
da3fca21 1092 }
1da177e4
LT		 1093}
1094
1095
9ad593f6
TI		 1096static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1097
1da177e4
LT		 1098/*
1099 * interrupt handler
1100 */
7d12e780 1101static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1102{
a98f90fd
TI		 1103 struct azx *chip = dev_id;
1104 struct azx_dev *azx_dev;
1da177e4 1105 u32 status;
9ef04066 1106 u8 sd_status;
fa00e046 1107 int i, ok;
1da177e4
LT		 1108
1109 spin_lock(&chip->reg_lock);
1110
1111 status = azx_readl(chip, INTSTS);
1112 if (status == 0) {
1113 spin_unlock(&chip->reg_lock);
1114 return IRQ_NONE;
1115 }
1116
07e4ca50 1117 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1118 azx_dev = &chip->azx_dev[i];
1119 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1120 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1121 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1122 if (!azx_dev->substream || !azx_dev->running ||
1123 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1124 continue;
1125 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1126 ok = azx_position_ok(chip, azx_dev);
1127 if (ok == 1) {
9ad593f6 1128 azx_dev->irq_pending = 0;
1da177e4
LT		 1129 spin_unlock(&chip->reg_lock);
1130 snd_pcm_period_elapsed(azx_dev->substream);
1131 spin_lock(&chip->reg_lock);
fa00e046 1132 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1133 /* bogus IRQ, process it later */
1134 azx_dev->irq_pending = 1;
6acaed38
TI		 1135 queue_work(chip->bus->workq,
1136 &chip->irq_pending_work);
1da177e4
LT		 1137 }
1138 }
1139 }
1140
1141 /* clear rirb int */
1142 status = azx_readb(chip, RIRBSTS);
1143 if (status & RIRB_INT_MASK) {
14d34f16
TI		 1144 if (status & RIRB_INT_RESPONSE) {
1145 if (chip->driver_type == AZX_DRIVER_CTX)
1146 udelay(80);
1da177e4 1147 azx_update_rirb(chip);
14d34f16 1148 }
1da177e4
LT		 1149 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1150 }
1151
1152#if 0
1153 /* clear state status int */
1154 if (azx_readb(chip, STATESTS) & 0x04)
1155 azx_writeb(chip, STATESTS, 0x04);
1156#endif
1157 spin_unlock(&chip->reg_lock);
1158
1159 return IRQ_HANDLED;
1160}
1161
1162
675f25d4
TI		 1163/*
1164 * set up a BDL entry
1165 */
1166static int setup_bdle(struct snd_pcm_substream *substream,
1167 struct azx_dev *azx_dev, u32 **bdlp,
1168 int ofs, int size, int with_ioc)
1169{
675f25d4
TI		 1170 u32 *bdl = *bdlp;
1171
1172 while (size > 0) {
1173 dma_addr_t addr;
1174 int chunk;
1175
1176 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1177 return -EINVAL;
1178
77a23f26 1179 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1180 /* program the address field of the BDL entry */
1181 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1182 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1183 /* program the size field of the BDL entry */
fc4abee8 1184 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1185 bdl[2] = cpu_to_le32(chunk);
1186 /* program the IOC to enable interrupt
1187 * only when the whole fragment is processed
1188 */
1189 size -= chunk;
1190 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1191 bdl += 4;
1192 azx_dev->frags++;
1193 ofs += chunk;
1194 }
1195 *bdlp = bdl;
1196 return ofs;
1197}
1198
1da177e4
LT		 1199/*
1200 * set up BDL entries
1201 */
555e219f
TI		 1202static int azx_setup_periods(struct azx *chip,
1203 struct snd_pcm_substream *substream,
4ce107b9 1204 struct azx_dev *azx_dev)
1da177e4 1205{
4ce107b9
TI		 1206 u32 *bdl;
1207 int i, ofs, periods, period_bytes;
555e219f 1208 int pos_adj;
1da177e4
LT		 1209
1210 /* reset BDL address */
1211 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1212 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1213
97b71c94 1214 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1215 periods = azx_dev->bufsize / period_bytes;
1216
1da177e4 1217 /* program the initial BDL entries */
4ce107b9
TI		 1218 bdl = (u32 *)azx_dev->bdl.area;
1219 ofs = 0;
1220 azx_dev->frags = 0;
555e219f
TI		 1221 pos_adj = bdl_pos_adj[chip->dev_index];
1222 if (pos_adj > 0) {
675f25d4 1223 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1224 int pos_align = pos_adj;
555e219f 1225 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1226 if (!pos_adj)
e785d3d8
TI		 1227 pos_adj = pos_align;
1228 else
1229 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1230 pos_align;
675f25d4
TI		 1231 pos_adj = frames_to_bytes(runtime, pos_adj);
1232 if (pos_adj >= period_bytes) {
4abc1cc2 1233 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1234 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1235 pos_adj = 0;
1236 } else {
1237 ofs = setup_bdle(substream, azx_dev,
7bb8fb70
CL		 1238 &bdl, ofs, pos_adj,
1239 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1240 if (ofs < 0)
1241 goto error;
4ce107b9 1242 }
555e219f
TI		 1243 } else
1244 pos_adj = 0;
675f25d4
TI		 1245 for (i = 0; i < periods; i++) {
1246 if (i == periods - 1 && pos_adj)
1247 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1248 period_bytes - pos_adj, 0);
1249 else
1250 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1251 period_bytes,
1252 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1253 if (ofs < 0)
1254 goto error;
1da177e4 1255 }
4ce107b9 1256 return 0;
675f25d4
TI		 1257
1258 error:
4abc1cc2 1259 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1260 azx_dev->bufsize, period_bytes);
675f25d4 1261 return -EINVAL;
1da177e4
LT		 1262}
1263
1dddab40
TI		 1264/* reset stream */
1265static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1266{
1267 unsigned char val;
1268 int timeout;
1269
1dddab40
TI		 1270 azx_stream_clear(chip, azx_dev);
1271
d01ce99f
TI		 1272 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1273 SD_CTL_STREAM_RESET);
1da177e4
LT		 1274 udelay(3);
1275 timeout = 300;
1276 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1277 --timeout)
1278 ;
1279 val &= ~SD_CTL_STREAM_RESET;
1280 azx_sd_writeb(azx_dev, SD_CTL, val);
1281 udelay(3);
1282
1283 timeout = 300;
1284 /* waiting for hardware to report that the stream is out of reset */
1285 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1286 --timeout)
1287 ;
fa00e046
JK		 1288
1289 /* reset first position - may not be synced with hw at this time */
1290 *azx_dev->posbuf = 0;
1dddab40 1291}
1da177e4 1292
1dddab40
TI		 1293/*
1294 * set up the SD for streaming
1295 */
1296static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1297{
1298 /* make sure the run bit is zero for SD */
1299 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1300 /* program the stream_tag */
1301 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1302 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1303 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1304
1305 /* program the length of samples in cyclic buffer */
1306 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1307
1308 /* program the stream format */
1309 /* this value needs to be the same as the one programmed */
1310 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1311
1312 /* program the stream LVI (last valid index) of the BDL */
1313 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1314
1315 /* program the BDL address */
1316 /* lower BDL address */
4ce107b9 1317 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1318 /* upper BDL address */
766979e0 1319 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1320
0be3b5d3 1321 /* enable the position buffer */
4cb36310
DH		 1322 if (chip->position_fix[0] != POS_FIX_LPIB ||
1323 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1324 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1325 azx_writel(chip, DPLBASE,
1326 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1327 }
c74db86b 1328
1da177e4 1329 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1330 azx_sd_writel(azx_dev, SD_CTL,
1331 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1332
1333 return 0;
1334}
1335
6ce4a3bc
TI		 1336/*
1337 * Probe the given codec address
1338 */
1339static int probe_codec(struct azx *chip, int addr)
1340{
1341 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1342 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1343 unsigned int res;
1344
a678cdee 1345 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1346 chip->probing = 1;
1347 azx_send_cmd(chip->bus, cmd);
deadff16 1348 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1349 chip->probing = 0;
a678cdee 1350 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1351 if (res == -1)
1352 return -EIO;
4abc1cc2 1353 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1354 return 0;
1355}
1356
33fa35ed
TI		 1357static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1358 struct hda_pcm *cpcm);
6ce4a3bc 1359static void azx_stop_chip(struct azx *chip);
1da177e4 1360
8dd78330
TI		 1361static void azx_bus_reset(struct hda_bus *bus)
1362{
1363 struct azx *chip = bus->private_data;
8dd78330
TI		 1364
1365 bus->in_reset = 1;
1366 azx_stop_chip(chip);
cd508fe5 1367 azx_init_chip(chip, 1);
65f75983 1368#ifdef CONFIG_PM
8dd78330 1369 if (chip->initialized) {
65f75983
AB		 1370 int i;
1371
c8936222 1372 for (i = 0; i < HDA_MAX_PCMS; i++)
8dd78330
TI		 1373 snd_pcm_suspend_all(chip->pcm[i]);
1374 snd_hda_suspend(chip->bus);
1375 snd_hda_resume(chip->bus);
1376 }
65f75983 1377#endif
8dd78330
TI		 1378 bus->in_reset = 0;
1379}
1380
1da177e4
LT		 1381/*
1382 * Codec initialization
1383 */
1384
2f5983f2
TI		 1385/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1386static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
7445dfc1 1387 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1388 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1389};
1390
a1e21c90 1391static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1392{
1393 struct hda_bus_template bus_temp;
34c25350
TI		 1394 int c, codecs, err;
1395 int max_slots;
1da177e4
LT		 1396
1397 memset(&bus_temp, 0, sizeof(bus_temp));
1398 bus_temp.private_data = chip;
1399 bus_temp.modelname = model;
1400 bus_temp.pci = chip->pci;
111d3af5
TI		 1401 bus_temp.ops.command = azx_send_cmd;
1402 bus_temp.ops.get_response = azx_get_response;
176d5335 1403 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1404 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1405#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1406 bus_temp.power_save = &power_save;
cb53c626
TI		 1407 bus_temp.ops.pm_notify = azx_power_notify;
1408#endif
1da177e4 1409
d01ce99f
TI		 1410 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1411 if (err < 0)
1da177e4
LT		 1412 return err;
1413
dc9c8e21
WN		 1414 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1415 chip->bus->needs_damn_long_delay = 1;
1416
34c25350 1417 codecs = 0;
2f5983f2
TI		 1418 max_slots = azx_max_codecs[chip->driver_type];
1419 if (!max_slots)
7445dfc1 1420 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1421
1422 /* First try to probe all given codec slots */
1423 for (c = 0; c < max_slots; c++) {
f1eaaeec 1424 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1425 if (probe_codec(chip, c) < 0) {
1426 /* Some BIOSen give you wrong codec addresses
1427 * that don't exist
1428 */
4abc1cc2
TI		 1429 snd_printk(KERN_WARNING SFX
1430 "Codec #%d probe error; "
6ce4a3bc
TI		 1431 "disabling it...\n", c);
1432 chip->codec_mask &= ~(1 << c);
1433 /* More badly, accessing to a non-existing
1434 * codec often screws up the controller chip,
2448158e 1435 * and disturbs the further communications.
6ce4a3bc
TI		 1436 * Thus if an error occurs during probing,
1437 * better to reset the controller chip to
1438 * get back to the sanity state.
1439 */
1440 azx_stop_chip(chip);
cd508fe5 1441 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1442 }
1443 }
1444 }
1445
1446 /* Then create codec instances */
34c25350 1447 for (c = 0; c < max_slots; c++) {
f1eaaeec 1448 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1449 struct hda_codec *codec;
a1e21c90 1450 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1451 if (err < 0)
1452 continue;
2dca0bba 1453 codec->beep_mode = chip->beep_mode;
1da177e4 1454 codecs++;
19a982b6
TI		 1455 }
1456 }
1457 if (!codecs) {
1da177e4
LT		 1458 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1459 return -ENXIO;
1460 }
a1e21c90
TI		 1461 return 0;
1462}
1da177e4 1463
a1e21c90
TI		 1464/* configure each codec instance */
1465static int __devinit azx_codec_configure(struct azx *chip)
1466{
1467 struct hda_codec *codec;
1468 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1469 snd_hda_codec_configure(codec);
1470 }
1da177e4
LT		 1471 return 0;
1472}
1473
1474
1475/*
1476 * PCM support
1477 */
1478
1479/* assign a stream for the PCM */
ef18bede
WF		 1480static inline struct azx_dev *
1481azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1482{
07e4ca50 1483 int dev, i, nums;
ef18bede
WF		 1484 struct azx_dev *res = NULL;
1485
1486 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1487 dev = chip->playback_index_offset;
1488 nums = chip->playback_streams;
1489 } else {
1490 dev = chip->capture_index_offset;
1491 nums = chip->capture_streams;
1492 }
1493 for (i = 0; i < nums; i++, dev++)
d01ce99f 1494 if (!chip->azx_dev[dev].opened) {
ef18bede
WF		 1495 res = &chip->azx_dev[dev];
1496 if (res->device == substream->pcm->device)
1497 break;
1da177e4 1498 }
ef18bede
WF		 1499 if (res) {
1500 res->opened = 1;
1501 res->device = substream->pcm->device;
1502 }
1503 return res;
1da177e4
LT		 1504}
1505
1506/* release the assigned stream */
a98f90fd 1507static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1508{
1509 azx_dev->opened = 0;
1510}
1511
a98f90fd 1512static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1513 .info = (SNDRV_PCM_INFO_MMAP |
1514 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1515 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1516 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1517 /* No full-resume yet implemented */
1518 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1519 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1520 SNDRV_PCM_INFO_SYNC_START |
1521 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1522 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1523 .rates = SNDRV_PCM_RATE_48000,
1524 .rate_min = 48000,
1525 .rate_max = 48000,
1526 .channels_min = 2,
1527 .channels_max = 2,
1528 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1529 .period_bytes_min = 128,
1530 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1531 .periods_min = 2,
1532 .periods_max = AZX_MAX_FRAG,
1533 .fifo_size = 0,
1534};
1535
1536struct azx_pcm {
a98f90fd 1537 struct azx *chip;
1da177e4
LT		 1538 struct hda_codec *codec;
1539 struct hda_pcm_stream *hinfo[2];
1540};
1541
a98f90fd 1542static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1543{
1544 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1545 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1546 struct azx *chip = apcm->chip;
1547 struct azx_dev *azx_dev;
1548 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1549 unsigned long flags;
1550 int err;
1551
62932df8 1552 mutex_lock(&chip->open_mutex);
ef18bede 1553 azx_dev = azx_assign_device(chip, substream);
1da177e4 1554 if (azx_dev == NULL) {
62932df8 1555 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1556 return -EBUSY;
1557 }
1558 runtime->hw = azx_pcm_hw;
1559 runtime->hw.channels_min = hinfo->channels_min;
1560 runtime->hw.channels_max = hinfo->channels_max;
1561 runtime->hw.formats = hinfo->formats;
1562 runtime->hw.rates = hinfo->rates;
1563 snd_pcm_limit_hw_rates(runtime);
1564 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1565 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1566 128);
1567 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1568 128);
cb53c626 1569 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1570 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1571 if (err < 0) {
1da177e4 1572 azx_release_device(azx_dev);
cb53c626 1573 snd_hda_power_down(apcm->codec);
62932df8 1574 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1575 return err;
1576 }
70d321e6 1577 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1578 /* sanity check */
1579 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1580 snd_BUG_ON(!runtime->hw.channels_max) ||
1581 snd_BUG_ON(!runtime->hw.formats) ||
1582 snd_BUG_ON(!runtime->hw.rates)) {
1583 azx_release_device(azx_dev);
1584 hinfo->ops.close(hinfo, apcm->codec, substream);
1585 snd_hda_power_down(apcm->codec);
1586 mutex_unlock(&chip->open_mutex);
1587 return -EINVAL;
1588 }
1da177e4
LT		 1589 spin_lock_irqsave(&chip->reg_lock, flags);
1590 azx_dev->substream = substream;
1591 azx_dev->running = 0;
1592 spin_unlock_irqrestore(&chip->reg_lock, flags);
1593
1594 runtime->private_data = azx_dev;
850f0e52 1595 snd_pcm_set_sync(substream);
62932df8 1596 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1597 return 0;
1598}
1599
a98f90fd 1600static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1601{
1602 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1603 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1604 struct azx *chip = apcm->chip;
1605 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1606 unsigned long flags;
1607
62932df8 1608 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1609 spin_lock_irqsave(&chip->reg_lock, flags);
1610 azx_dev->substream = NULL;
1611 azx_dev->running = 0;
1612 spin_unlock_irqrestore(&chip->reg_lock, flags);
1613 azx_release_device(azx_dev);
1614 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1615 snd_hda_power_down(apcm->codec);
62932df8 1616 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1617 return 0;
1618}
1619
d01ce99f
TI		 1620static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1621 struct snd_pcm_hw_params *hw_params)
1da177e4 1622{
97b71c94
TI		 1623 struct azx_dev *azx_dev = get_azx_dev(substream);
1624
1625 azx_dev->bufsize = 0;
1626 azx_dev->period_bytes = 0;
1627 azx_dev->format_val = 0;
d01ce99f
TI		 1628 return snd_pcm_lib_malloc_pages(substream,
1629 params_buffer_bytes(hw_params));
1da177e4
LT		 1630}
1631
a98f90fd 1632static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1633{
1634 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1635 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1636 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1637
1638 /* reset BDL address */
1639 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1640 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1641 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1642 azx_dev->bufsize = 0;
1643 azx_dev->period_bytes = 0;
1644 azx_dev->format_val = 0;
1da177e4 1645
eb541337 1646 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4
LT		 1647
1648 return snd_pcm_lib_free_pages(substream);
1649}
1650
a98f90fd 1651static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1652{
1653 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1654 struct azx *chip = apcm->chip;
1655 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1656 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1657 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1658 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1659 int err;
1da177e4 1660
fa00e046 1661 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1662 format_val = snd_hda_calc_stream_format(runtime->rate,
1663 runtime->channels,
1664 runtime->format,
32c168c8
AH		 1665 hinfo->maxbps,
1666 apcm->codec->spdif_ctls);
97b71c94 1667 if (!format_val) {
d01ce99f
TI		 1668 snd_printk(KERN_ERR SFX
1669 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1670 runtime->rate, runtime->channels, runtime->format);
1671 return -EINVAL;
1672 }
1673
97b71c94
TI		 1674 bufsize = snd_pcm_lib_buffer_bytes(substream);
1675 period_bytes = snd_pcm_lib_period_bytes(substream);
1676
4abc1cc2 1677 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1678 bufsize, format_val);
1679
1680 if (bufsize != azx_dev->bufsize ||
1681 period_bytes != azx_dev->period_bytes ||
1682 format_val != azx_dev->format_val) {
1683 azx_dev->bufsize = bufsize;
1684 azx_dev->period_bytes = period_bytes;
1685 azx_dev->format_val = format_val;
1686 err = azx_setup_periods(chip, substream, azx_dev);
1687 if (err < 0)
1688 return err;
1689 }
1690
e5463720
JK		 1691 /* wallclk has 24Mhz clock source */
1692 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1693 runtime->rate) * 1000);
1da177e4
LT		 1694 azx_setup_controller(chip, azx_dev);
1695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1696 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1697 else
1698 azx_dev->fifo_size = 0;
1699
62b7e5e0
TI		 1700 stream_tag = azx_dev->stream_tag;
1701 /* CA-IBG chips need the playback stream starting from 1 */
1702 if (chip->driver_type == AZX_DRIVER_CTX &&
1703 stream_tag > chip->capture_streams)
1704 stream_tag -= chip->capture_streams;
1705 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1706 azx_dev->format_val, substream);
1da177e4
LT		 1707}
1708
a98f90fd 1709static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1710{
1711 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1712 struct azx *chip = apcm->chip;
850f0e52
TI		 1713 struct azx_dev *azx_dev;
1714 struct snd_pcm_substream *s;
fa00e046 1715 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1716 int nwait, timeout;
1da177e4 1717
1da177e4 1718 switch (cmd) {
fa00e046
JK		 1719 case SNDRV_PCM_TRIGGER_START:
1720 rstart = 1;
1da177e4
LT		 1721 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1722 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1723 start = 1;
1da177e4
LT		 1724 break;
1725 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1726 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1727 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1728 start = 0;
1da177e4
LT		 1729 break;
1730 default:
850f0e52
TI		 1731 return -EINVAL;
1732 }
1733
1734 snd_pcm_group_for_each_entry(s, substream) {
1735 if (s->pcm->card != substream->pcm->card)
1736 continue;
1737 azx_dev = get_azx_dev(s);
1738 sbits |= 1 << azx_dev->index;
1739 nsync++;
1740 snd_pcm_trigger_done(s, substream);
1741 }
1742
1743 spin_lock(&chip->reg_lock);
1744 if (nsync > 1) {
1745 /* first, set SYNC bits of corresponding streams */
1746 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1747 }
1748 snd_pcm_group_for_each_entry(s, substream) {
1749 if (s->pcm->card != substream->pcm->card)
1750 continue;
1751 azx_dev = get_azx_dev(s);
e5463720
JK		 1752 if (start) {
1753 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1754 if (!rstart)
1755 azx_dev->start_wallclk -=
1756 azx_dev->period_wallclk;
850f0e52 1757 azx_stream_start(chip, azx_dev);
e5463720 1758 } else {
850f0e52 1759 azx_stream_stop(chip, azx_dev);
e5463720 1760 }
850f0e52 1761 azx_dev->running = start;
1da177e4
LT		 1762 }
1763 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1764 if (start) {
1765 if (nsync == 1)
1766 return 0;
1767 /* wait until all FIFOs get ready */
1768 for (timeout = 5000; timeout; timeout--) {
1769 nwait = 0;
1770 snd_pcm_group_for_each_entry(s, substream) {
1771 if (s->pcm->card != substream->pcm->card)
1772 continue;
1773 azx_dev = get_azx_dev(s);
1774 if (!(azx_sd_readb(azx_dev, SD_STS) &
1775 SD_STS_FIFO_READY))
1776 nwait++;
1777 }
1778 if (!nwait)
1779 break;
1780 cpu_relax();
1781 }
1782 } else {
1783 /* wait until all RUN bits are cleared */
1784 for (timeout = 5000; timeout; timeout--) {
1785 nwait = 0;
1786 snd_pcm_group_for_each_entry(s, substream) {
1787 if (s->pcm->card != substream->pcm->card)
1788 continue;
1789 azx_dev = get_azx_dev(s);
1790 if (azx_sd_readb(azx_dev, SD_CTL) &
1791 SD_CTL_DMA_START)
1792 nwait++;
1793 }
1794 if (!nwait)
1795 break;
1796 cpu_relax();
1797 }
1da177e4 1798 }
850f0e52
TI		 1799 if (nsync > 1) {
1800 spin_lock(&chip->reg_lock);
1801 /* reset SYNC bits */
1802 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1803 spin_unlock(&chip->reg_lock);
1804 }
1805 return 0;
1da177e4
LT		 1806}
1807
0e153474
JC		 1808/* get the current DMA position with correction on VIA chips */
1809static unsigned int azx_via_get_position(struct azx *chip,
1810 struct azx_dev *azx_dev)
1811{
1812 unsigned int link_pos, mini_pos, bound_pos;
1813 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1814 unsigned int fifo_size;
1815
1816 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1817 if (azx_dev->index >= 4) {
1818 /* Playback, no problem using link position */
1819 return link_pos;
1820 }
1821
1822 /* Capture */
1823 /* For new chipset,
1824 * use mod to get the DMA position just like old chipset
1825 */
1826 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1827 mod_dma_pos %= azx_dev->period_bytes;
1828
1829 /* azx_dev->fifo_size can't get FIFO size of in stream.
1830 * Get from base address + offset.
1831 */
1832 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1833
1834 if (azx_dev->insufficient) {
1835 /* Link position never gather than FIFO size */
1836 if (link_pos <= fifo_size)
1837 return 0;
1838
1839 azx_dev->insufficient = 0;
1840 }
1841
1842 if (link_pos <= fifo_size)
1843 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1844 else
1845 mini_pos = link_pos - fifo_size;
1846
1847 /* Find nearest previous boudary */
1848 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1849 mod_link_pos = link_pos % azx_dev->period_bytes;
1850 if (mod_link_pos >= fifo_size)
1851 bound_pos = link_pos - mod_link_pos;
1852 else if (mod_dma_pos >= mod_mini_pos)
1853 bound_pos = mini_pos - mod_mini_pos;
1854 else {
1855 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1856 if (bound_pos >= azx_dev->bufsize)
1857 bound_pos = 0;
1858 }
1859
1860 /* Calculate real DMA position we want */
1861 return bound_pos + mod_dma_pos;
1862}
1863
9ad593f6
TI		 1864static unsigned int azx_get_position(struct azx *chip,
1865 struct azx_dev *azx_dev)
1da177e4 1866{
1da177e4 1867 unsigned int pos;
4cb36310 1868 int stream = azx_dev->substream->stream;
1da177e4 1869
4cb36310
DH		 1870 switch (chip->position_fix[stream]) {
1871 case POS_FIX_LPIB:
1872 /* read LPIB */
1873 pos = azx_sd_readl(azx_dev, SD_LPIB);
1874 break;
1875 case POS_FIX_VIACOMBO:
0e153474 1876 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 1877 break;
1878 default:
1879 /* use the position buffer */
1880 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b 1881 }
4cb36310 1882
1da177e4
LT		 1883 if (pos >= azx_dev->bufsize)
1884 pos = 0;
9ad593f6
TI		 1885 return pos;
1886}
1887
1888static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1889{
1890 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1891 struct azx *chip = apcm->chip;
1892 struct azx_dev *azx_dev = get_azx_dev(substream);
1893 return bytes_to_frames(substream->runtime,
1894 azx_get_position(chip, azx_dev));
1895}
1896
1897/*
1898 * Check whether the current DMA position is acceptable for updating
1899 * periods. Returns non-zero if it's OK.
1900 *
1901 * Many HD-audio controllers appear pretty inaccurate about
1902 * the update-IRQ timing. The IRQ is issued before actually the
1903 * data is processed. So, we need to process it afterwords in a
1904 * workqueue.
1905 */
1906static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1907{
e5463720 1908 u32 wallclk;
9ad593f6 1909 unsigned int pos;
beaffc39 1910 int stream;
9ad593f6 1911
f48f606d
JK		 1912 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1913 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 1914 return -1; /* bogus (too early) interrupt */
fa00e046 1915
beaffc39 1916 stream = azx_dev->substream->stream;
9ad593f6 1917 pos = azx_get_position(chip, azx_dev);
beaffc39 1918 if (chip->position_fix[stream] == POS_FIX_AUTO) {
9ad593f6
TI		 1919 if (!pos) {
1920 printk(KERN_WARNING
1921 "hda-intel: Invalid position buffer, "
1922 "using LPIB read method instead.\n");
beaffc39 1923 chip->position_fix[stream] = POS_FIX_LPIB;
9ad593f6
TI		 1924 pos = azx_get_position(chip, azx_dev);
1925 } else
beaffc39 1926 chip->position_fix[stream] = POS_FIX_POSBUF;
9ad593f6
TI		 1927 }
1928
d6d8bf54
TI		 1929 if (WARN_ONCE(!azx_dev->period_bytes,
1930 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 1931 return -1; /* this shouldn't happen! */
edb39935 1932 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 1933 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1934 /* NG - it's below the first next period boundary */
1935 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 1936 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 1937 return 1; /* OK, it's fine */
1938}
1939
1940/*
1941 * The work for pending PCM period updates.
1942 */
1943static void azx_irq_pending_work(struct work_struct *work)
1944{
1945 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 1946 int i, pending, ok;
9ad593f6 1947
a6a950a8
TI		 1948 if (!chip->irq_pending_warned) {
1949 printk(KERN_WARNING
1950 "hda-intel: IRQ timing workaround is activated "
1951 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1952 chip->card->number);
1953 chip->irq_pending_warned = 1;
1954 }
1955
9ad593f6
TI		 1956 for (;;) {
1957 pending = 0;
1958 spin_lock_irq(&chip->reg_lock);
1959 for (i = 0; i < chip->num_streams; i++) {
1960 struct azx_dev *azx_dev = &chip->azx_dev[i];
1961 if (!azx_dev->irq_pending ||
1962 !azx_dev->substream ||
1963 !azx_dev->running)
1964 continue;
e5463720
JK		 1965 ok = azx_position_ok(chip, azx_dev);
1966 if (ok > 0) {
9ad593f6
TI		 1967 azx_dev->irq_pending = 0;
1968 spin_unlock(&chip->reg_lock);
1969 snd_pcm_period_elapsed(azx_dev->substream);
1970 spin_lock(&chip->reg_lock);
e5463720
JK		 1971 } else if (ok < 0) {
1972 pending = 0; /* too early */
9ad593f6
TI		 1973 } else
1974 pending++;
1975 }
1976 spin_unlock_irq(&chip->reg_lock);
1977 if (!pending)
1978 return;
08af495f 1979 msleep(1);
9ad593f6
TI		 1980 }
1981}
1982
1983/* clear irq_pending flags and assure no on-going workq */
1984static void azx_clear_irq_pending(struct azx *chip)
1985{
1986 int i;
1987
1988 spin_lock_irq(&chip->reg_lock);
1989 for (i = 0; i < chip->num_streams; i++)
1990 chip->azx_dev[i].irq_pending = 0;
1991 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1992}
1993
a98f90fd 1994static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1995 .open = azx_pcm_open,
1996 .close = azx_pcm_close,
1997 .ioctl = snd_pcm_lib_ioctl,
1998 .hw_params = azx_pcm_hw_params,
1999 .hw_free = azx_pcm_hw_free,
2000 .prepare = azx_pcm_prepare,
2001 .trigger = azx_pcm_trigger,
2002 .pointer = azx_pcm_pointer,
4ce107b9 2003 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2004};
2005
a98f90fd 2006static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2007{
176d5335
TI		 2008 struct azx_pcm *apcm = pcm->private_data;
2009 if (apcm) {
2010 apcm->chip->pcm[pcm->device] = NULL;
2011 kfree(apcm);
2012 }
1da177e4
LT		 2013}
2014
176d5335 2015static int
33fa35ed
TI		 2016azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2017 struct hda_pcm *cpcm)
1da177e4 2018{
33fa35ed 2019 struct azx *chip = bus->private_data;
a98f90fd 2020 struct snd_pcm *pcm;
1da177e4 2021 struct azx_pcm *apcm;
176d5335
TI		 2022 int pcm_dev = cpcm->device;
2023 int s, err;
1da177e4 2024
c8936222 2025 if (pcm_dev >= HDA_MAX_PCMS) {
176d5335
TI		 2026 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2027 pcm_dev);
da3cec35 2028 return -EINVAL;
176d5335
TI		 2029 }
2030 if (chip->pcm[pcm_dev]) {
2031 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2032 return -EBUSY;
2033 }
2034 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2035 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2036 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2037 &pcm);
2038 if (err < 0)
2039 return err;
18cb7109 2040 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2041 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2042 if (apcm == NULL)
2043 return -ENOMEM;
2044 apcm->chip = chip;
2045 apcm->codec = codec;
1da177e4
LT		 2046 pcm->private_data = apcm;
2047 pcm->private_free = azx_pcm_free;
176d5335
TI		 2048 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2049 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2050 chip->pcm[pcm_dev] = pcm;
2051 cpcm->pcm = pcm;
2052 for (s = 0; s < 2; s++) {
2053 apcm->hinfo[s] = &cpcm->stream[s];
2054 if (cpcm->stream[s].substreams)
2055 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2056 }
2057 /* buffer pre-allocation */
4ce107b9 2058 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2059 snd_dma_pci_data(chip->pci),
fc4abee8 2060 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 2061 return 0;
2062}
2063
2064/*
2065 * mixer creation - all stuff is implemented in hda module
2066 */
a98f90fd 2067static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2068{
2069 return snd_hda_build_controls(chip->bus);
2070}
2071
2072
2073/*
2074 * initialize SD streams
2075 */
a98f90fd 2076static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2077{
2078 int i;
2079
2080 /* initialize each stream (aka device)
d01ce99f
TI		 2081 * assign the starting bdl address to each stream (device)
2082 * and initialize
1da177e4 2083 */
07e4ca50 2084 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2085 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2086 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2087 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2088 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2089 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2090 azx_dev->sd_int_sta_mask = 1 << i;
2091 /* stream tag: must be non-zero and unique */
2092 azx_dev->index = i;
2093 azx_dev->stream_tag = i + 1;
2094 }
2095
2096 return 0;
2097}
2098
68e7fffc
TI		 2099static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2100{
437a5a46
TI		 2101 if (request_irq(chip->pci->irq, azx_interrupt,
2102 chip->msi ? 0 : IRQF_SHARED,
9492837a 2103 "hda_intel", chip)) {
68e7fffc
TI		 2104 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2105 "disabling device\n", chip->pci->irq);
2106 if (do_disconnect)
2107 snd_card_disconnect(chip->card);
2108 return -1;
2109 }
2110 chip->irq = chip->pci->irq;
69e13418 2111 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2112 return 0;
2113}
2114
1da177e4 2115
cb53c626
TI		 2116static void azx_stop_chip(struct azx *chip)
2117{
95e99fda 2118 if (!chip->initialized)
cb53c626
TI		 2119 return;
2120
2121 /* disable interrupts */
2122 azx_int_disable(chip);
2123 azx_int_clear(chip);
2124
2125 /* disable CORB/RIRB */
2126 azx_free_cmd_io(chip);
2127
2128 /* disable position buffer */
2129 azx_writel(chip, DPLBASE, 0);
2130 azx_writel(chip, DPUBASE, 0);
2131
2132 chip->initialized = 0;
2133}
2134
2135#ifdef CONFIG_SND_HDA_POWER_SAVE
2136/* power-up/down the controller */
33fa35ed 2137static void azx_power_notify(struct hda_bus *bus)
cb53c626 2138{
33fa35ed 2139 struct azx *chip = bus->private_data;
cb53c626
TI		 2140 struct hda_codec *c;
2141 int power_on = 0;
2142
33fa35ed 2143 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2144 if (c->power_on) {
2145 power_on = 1;
2146 break;
2147 }
2148 }
2149 if (power_on)
cd508fe5 2150 azx_init_chip(chip, 1);
0287d970
WF		 2151 else if (chip->running && power_save_controller &&
2152 !bus->power_keep_link_on)
cb53c626 2153 azx_stop_chip(chip);
cb53c626 2154}
5c0b9bec
TI		 2155#endif /* CONFIG_SND_HDA_POWER_SAVE */
2156
2157#ifdef CONFIG_PM
2158/*
2159 * power management
2160 */
986862bd
TI		 2161
2162static int snd_hda_codecs_inuse(struct hda_bus *bus)
2163{
2164 struct hda_codec *codec;
2165
2166 list_for_each_entry(codec, &bus->codec_list, list) {
2167 if (snd_hda_codec_needs_resume(codec))
2168 return 1;
2169 }
2170 return 0;
2171}
cb53c626 2172
421a1252 2173static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2174{
421a1252
TI		 2175 struct snd_card *card = pci_get_drvdata(pci);
2176 struct azx *chip = card->private_data;
1da177e4
LT		 2177 int i;
2178
421a1252 2179 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2180 azx_clear_irq_pending(chip);
c8936222 2181 for (i = 0; i < HDA_MAX_PCMS; i++)
421a1252 2182 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2183 if (chip->initialized)
8dd78330 2184 snd_hda_suspend(chip->bus);
cb53c626 2185 azx_stop_chip(chip);
30b35399 2186 if (chip->irq >= 0) {
43001c95 2187 free_irq(chip->irq, chip);
30b35399
TI		 2188 chip->irq = -1;
2189 }
68e7fffc 2190 if (chip->msi)
43001c95 2191 pci_disable_msi(chip->pci);
421a1252
TI		 2192 pci_disable_device(pci);
2193 pci_save_state(pci);
30b35399 2194 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2195 return 0;
2196}
2197
421a1252 2198static int azx_resume(struct pci_dev *pci)
1da177e4 2199{
421a1252
TI		 2200 struct snd_card *card = pci_get_drvdata(pci);
2201 struct azx *chip = card->private_data;
1da177e4 2202
d14a7e0b
TI		 2203 pci_set_power_state(pci, PCI_D0);
2204 pci_restore_state(pci);
30b35399
TI		 2205 if (pci_enable_device(pci) < 0) {
2206 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2207 "disabling device\n");
2208 snd_card_disconnect(card);
2209 return -EIO;
2210 }
2211 pci_set_master(pci);
68e7fffc
TI		 2212 if (chip->msi)
2213 if (pci_enable_msi(pci) < 0)
2214 chip->msi = 0;
2215 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2216 return -EIO;
cb53c626 2217 azx_init_pci(chip);
d804ad92
ML		 2218
2219 if (snd_hda_codecs_inuse(chip->bus))
cd508fe5 2220 azx_init_chip(chip, 1);
d804ad92 2221
1da177e4 2222 snd_hda_resume(chip->bus);
421a1252 2223 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2224 return 0;
2225}
2226#endif /* CONFIG_PM */
2227
2228
0cbf0098
TI		 2229/*
2230 * reboot notifier for hang-up problem at power-down
2231 */
2232static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2233{
2234 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2235 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2236 azx_stop_chip(chip);
2237 return NOTIFY_OK;
2238}
2239
2240static void azx_notifier_register(struct azx *chip)
2241{
2242 chip->reboot_notifier.notifier_call = azx_halt;
2243 register_reboot_notifier(&chip->reboot_notifier);
2244}
2245
2246static void azx_notifier_unregister(struct azx *chip)
2247{
2248 if (chip->reboot_notifier.notifier_call)
2249 unregister_reboot_notifier(&chip->reboot_notifier);
2250}
2251
1da177e4
LT		 2252/*
2253 * destructor
2254 */
a98f90fd 2255static int azx_free(struct azx *chip)
1da177e4 2256{
4ce107b9
TI		 2257 int i;
2258
0cbf0098
TI		 2259 azx_notifier_unregister(chip);
2260
ce43fbae 2261 if (chip->initialized) {
9ad593f6 2262 azx_clear_irq_pending(chip);
07e4ca50 2263 for (i = 0; i < chip->num_streams; i++)
1da177e4 2264 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2265 azx_stop_chip(chip);
1da177e4
LT		 2266 }
2267
f000fd80 2268 if (chip->irq >= 0)
1da177e4 2269 free_irq(chip->irq, (void*)chip);
68e7fffc 2270 if (chip->msi)
30b35399 2271 pci_disable_msi(chip->pci);
f079c25a
TI		 2272 if (chip->remap_addr)
2273 iounmap(chip->remap_addr);
1da177e4 2274
4ce107b9
TI		 2275 if (chip->azx_dev) {
2276 for (i = 0; i < chip->num_streams; i++)
2277 if (chip->azx_dev[i].bdl.area)
2278 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2279 }
1da177e4
LT		 2280 if (chip->rb.area)
2281 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2282 if (chip->posbuf.area)
2283 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2284 pci_release_regions(chip->pci);
2285 pci_disable_device(chip->pci);
07e4ca50 2286 kfree(chip->azx_dev);
1da177e4
LT		 2287 kfree(chip);
2288
2289 return 0;
2290}
2291
a98f90fd 2292static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2293{
2294 return azx_free(device->device_data);
2295}
2296
3372a153
TI		 2297/*
2298 * white/black-listing for position_fix
2299 */
623ec047 2300static struct snd_pci_quirk position_fix_list[] __devinitdata = {
7a68be94 2301 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
dd5a089e 2302 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
d2e1c973
TI		 2303 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2304 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
9919c761 2305 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
e03fa055 2306 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2f703e7a 2307 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2308 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2309 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2310 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2311 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
4e0938db
DC		 2312 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2313 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
61bb42c3 2314 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2315 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2316 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
0321b695 2317 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
8815cd03 2318 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2319 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2320 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
572c0e3c 2321 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
3372a153
TI		 2322 {}
2323};
2324
2325static int __devinit check_position_fix(struct azx *chip, int fix)
2326{
2327 const struct snd_pci_quirk *q;
2328
c673ba1c
TI		 2329 switch (fix) {
2330 case POS_FIX_LPIB:
2331 case POS_FIX_POSBUF:
4cb36310 2332 case POS_FIX_VIACOMBO:
c673ba1c
TI		 2333 return fix;
2334 }
2335
c673ba1c
TI		 2336 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2337 if (q) {
2338 printk(KERN_INFO
2339 "hda_intel: position_fix set to %d "
2340 "for device %04x:%04x\n",
2341 q->value, q->subvendor, q->subdevice);
2342 return q->value;
3372a153 2343 }
bdd9ef24
DH		 2344
2345 /* Check VIA/ATI HD Audio Controller exist */
2346 switch (chip->driver_type) {
2347 case AZX_DRIVER_VIA:
2348 case AZX_DRIVER_ATI:
2349 /* Use link position directly, avoid any transfer problem. */
2350 return POS_FIX_VIACOMBO;
2351 }
2352
c673ba1c 2353 return POS_FIX_AUTO;
3372a153
TI		 2354}
2355
669ba27a
TI		 2356/*
2357 * black-lists for probe_mask
2358 */
2359static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2360 /* Thinkpad often breaks the controller communication when accessing
2361 * to the non-working (or non-existing) modem codec slot.
2362 */
2363 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2364 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2365 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2366 /* broken BIOS */
2367 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2368 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2369 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2370 /* forced codec slots */
93574844 2371 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2372 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2373 {}
2374};
2375
f1eaaeec
TI		 2376#define AZX_FORCE_CODEC_MASK 0x100
2377
5aba4f8e 2378static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2379{
2380 const struct snd_pci_quirk *q;
2381
f1eaaeec
TI		 2382 chip->codec_probe_mask = probe_mask[dev];
2383 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2384 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2385 if (q) {
2386 printk(KERN_INFO
2387 "hda_intel: probe_mask set to 0x%x "
2388 "for device %04x:%04x\n",
2389 q->value, q->subvendor, q->subdevice);
f1eaaeec 2390 chip->codec_probe_mask = q->value;
669ba27a
TI		 2391 }
2392 }
f1eaaeec
TI		 2393
2394 /* check forced option */
2395 if (chip->codec_probe_mask != -1 &&
2396 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2397 chip->codec_mask = chip->codec_probe_mask & 0xff;
2398 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2399 chip->codec_mask);
2400 }
669ba27a
TI		 2401}
2402
4d8e22e0 2403/*
71623855 2404 * white/black-list for enable_msi
4d8e22e0 2405 */
71623855 2406static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2407 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2408 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2409 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2410 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2411 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2412 {}
2413};
2414
2415static void __devinit check_msi(struct azx *chip)
2416{
2417 const struct snd_pci_quirk *q;
2418
71623855
TI		 2419 if (enable_msi >= 0) {
2420 chip->msi = !!enable_msi;
4d8e22e0 2421 return;
71623855
TI		 2422 }
2423 chip->msi = 1; /* enable MSI as default */
2424 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2425 if (q) {
2426 printk(KERN_INFO
2427 "hda_intel: msi for device %04x:%04x set to %d\n",
2428 q->subvendor, q->subdevice, q->value);
2429 chip->msi = q->value;
80c43ed7
TI		 2430 return;
2431 }
2432
2433 /* NVidia chipsets seem to cause troubles with MSI */
2434 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2435 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2436 chip->msi = 0;
4d8e22e0
TI		 2437 }
2438}
2439
669ba27a 2440
1da177e4
LT		 2441/*
2442 * constructor
2443 */
a98f90fd 2444static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2445 int dev, int driver_type,
a98f90fd 2446 struct azx **rchip)
1da177e4 2447{
a98f90fd 2448 struct azx *chip;
4ce107b9 2449 int i, err;
bcd72003 2450 unsigned short gcap;
a98f90fd 2451 static struct snd_device_ops ops = {
1da177e4
LT		 2452 .dev_free = azx_dev_free,
2453 };
2454
2455 *rchip = NULL;
bcd72003 2456
927fc866
PM		 2457 err = pci_enable_device(pci);
2458 if (err < 0)
1da177e4
LT		 2459 return err;
2460
e560d8d8 2461 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2462 if (!chip) {
1da177e4
LT		 2463 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2464 pci_disable_device(pci);
2465 return -ENOMEM;
2466 }
2467
2468 spin_lock_init(&chip->reg_lock);
62932df8 2469 mutex_init(&chip->open_mutex);
1da177e4
LT		 2470 chip->card = card;
2471 chip->pci = pci;
2472 chip->irq = -1;
07e4ca50 2473 chip->driver_type = driver_type;
4d8e22e0 2474 check_msi(chip);
555e219f 2475 chip->dev_index = dev;
9ad593f6 2476 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2477
beaffc39
SG		 2478 chip->position_fix[0] = chip->position_fix[1] =
2479 check_position_fix(chip, position_fix[dev]);
5aba4f8e 2480 check_probe_mask(chip, dev);
3372a153 2481
27346166 2482 chip->single_cmd = single_cmd;
c74db86b 2483
5c0d7bc1
TI		 2484 if (bdl_pos_adj[dev] < 0) {
2485 switch (chip->driver_type) {
0c6341ac 2486 case AZX_DRIVER_ICH:
32679f95 2487 case AZX_DRIVER_PCH:
0c6341ac 2488 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2489 break;
2490 default:
0c6341ac 2491 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2492 break;
2493 }
2494 }
2495
07e4ca50
TI		 2496#if BITS_PER_LONG != 64
2497 /* Fix up base address on ULI M5461 */
2498 if (chip->driver_type == AZX_DRIVER_ULI) {
2499 u16 tmp3;
2500 pci_read_config_word(pci, 0x40, &tmp3);
2501 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2502 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2503 }
2504#endif
2505
927fc866
PM		 2506 err = pci_request_regions(pci, "ICH HD audio");
2507 if (err < 0) {
1da177e4
LT		 2508 kfree(chip);
2509 pci_disable_device(pci);
2510 return err;
2511 }
2512
927fc866 2513 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2514 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2515 if (chip->remap_addr == NULL) {
2516 snd_printk(KERN_ERR SFX "ioremap error\n");
2517 err = -ENXIO;
2518 goto errout;
2519 }
2520
68e7fffc
TI		 2521 if (chip->msi)
2522 if (pci_enable_msi(pci) < 0)
2523 chip->msi = 0;
7376d013 2524
68e7fffc 2525 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2526 err = -EBUSY;
2527 goto errout;
2528 }
1da177e4
LT		 2529
2530 pci_set_master(pci);
2531 synchronize_irq(chip->irq);
2532
bcd72003 2533 gcap = azx_readw(chip, GCAP);
4abc1cc2 2534 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2535
dc4c2e6b
AB		 2536 /* disable SB600 64bit support for safety */
2537 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2538 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2539 struct pci_dev *p_smbus;
2540 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2541 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2542 NULL);
2543 if (p_smbus) {
2544 if (p_smbus->revision < 0x30)
2545 gcap &= ~ICH6_GCAP_64OK;
2546 pci_dev_put(p_smbus);
2547 }
2548 }
09240cf4 2549
396087ea
JK		 2550 /* disable 64bit DMA address for Teradici */
2551 /* it does not work with device 6549:1200 subsys e4a2:040b */
2552 if (chip->driver_type == AZX_DRIVER_TERA)
2553 gcap &= ~ICH6_GCAP_64OK;
2554
cf7aaca8 2555 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2556 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2558 else {
e930438c
YH		 2559 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2560 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2561 }
cf7aaca8 2562
8b6ed8e7
TI		 2563 /* read number of streams from GCAP register instead of using
2564 * hardcoded value
2565 */
2566 chip->capture_streams = (gcap >> 8) & 0x0f;
2567 chip->playback_streams = (gcap >> 12) & 0x0f;
2568 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2569 /* gcap didn't give any info, switching to old method */
2570
2571 switch (chip->driver_type) {
2572 case AZX_DRIVER_ULI:
2573 chip->playback_streams = ULI_NUM_PLAYBACK;
2574 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2575 break;
2576 case AZX_DRIVER_ATIHDMI:
2577 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2578 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2579 break;
c4da29ca 2580 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2581 default:
2582 chip->playback_streams = ICH6_NUM_PLAYBACK;
2583 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2584 break;
2585 }
07e4ca50 2586 }
8b6ed8e7
TI		 2587 chip->capture_index_offset = 0;
2588 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2589 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2590 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2591 GFP_KERNEL);
927fc866 2592 if (!chip->azx_dev) {
4abc1cc2 2593 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2594 goto errout;
2595 }
2596
4ce107b9
TI		 2597 for (i = 0; i < chip->num_streams; i++) {
2598 /* allocate memory for the BDL for each stream */
2599 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2600 snd_dma_pci_data(chip->pci),
2601 BDL_SIZE, &chip->azx_dev[i].bdl);
2602 if (err < 0) {
2603 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2604 goto errout;
2605 }
1da177e4 2606 }
0be3b5d3 2607 /* allocate memory for the position buffer */
d01ce99f
TI		 2608 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2609 snd_dma_pci_data(chip->pci),
2610 chip->num_streams * 8, &chip->posbuf);
2611 if (err < 0) {
0be3b5d3
TI		 2612 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2613 goto errout;
1da177e4 2614 }
1da177e4 2615 /* allocate CORB/RIRB */
81740861
TI		 2616 err = azx_alloc_cmd_io(chip);
2617 if (err < 0)
2618 goto errout;
1da177e4
LT		 2619
2620 /* initialize streams */
2621 azx_init_stream(chip);
2622
2623 /* initialize chip */
cb53c626 2624 azx_init_pci(chip);
10e77dda 2625 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2626
2627 /* codec detection */
927fc866 2628 if (!chip->codec_mask) {
1da177e4
LT		 2629 snd_printk(KERN_ERR SFX "no codecs found!\n");
2630 err = -ENODEV;
2631 goto errout;
2632 }
2633
d01ce99f
TI		 2634 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2635 if (err <0) {
1da177e4
LT		 2636 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2637 goto errout;
2638 }
2639
07e4ca50 2640 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2641 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2642 sizeof(card->shortname));
2643 snprintf(card->longname, sizeof(card->longname),
2644 "%s at 0x%lx irq %i",
2645 card->shortname, chip->addr, chip->irq);
07e4ca50 2646
1da177e4
LT		 2647 *rchip = chip;
2648 return 0;
2649
2650 errout:
2651 azx_free(chip);
2652 return err;
2653}
2654
cb53c626
TI		 2655static void power_down_all_codecs(struct azx *chip)
2656{
2657#ifdef CONFIG_SND_HDA_POWER_SAVE
2658 /* The codecs were powered up in snd_hda_codec_new().
2659 * Now all initialization done, so turn them down if possible
2660 */
2661 struct hda_codec *codec;
2662 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2663 snd_hda_power_down(codec);
2664 }
2665#endif
2666}
2667
d01ce99f
TI		 2668static int __devinit azx_probe(struct pci_dev *pci,
2669 const struct pci_device_id *pci_id)
1da177e4 2670{
5aba4f8e 2671 static int dev;
a98f90fd
TI		 2672 struct snd_card *card;
2673 struct azx *chip;
927fc866 2674 int err;
1da177e4 2675
5aba4f8e
TI		 2676 if (dev >= SNDRV_CARDS)
2677 return -ENODEV;
2678 if (!enable[dev]) {
2679 dev++;
2680 return -ENOENT;
2681 }
2682
e58de7ba
TI		 2683 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2684 if (err < 0) {
1da177e4 2685 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2686 return err;
1da177e4
LT		 2687 }
2688
4ea6fbc8
TI		 2689 /* set this here since it's referred in snd_hda_load_patch() */
2690 snd_card_set_dev(card, &pci->dev);
2691
5aba4f8e 2692 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2693 if (err < 0)
2694 goto out_free;
421a1252 2695 card->private_data = chip;
1da177e4 2696
2dca0bba
JK		 2697#ifdef CONFIG_SND_HDA_INPUT_BEEP
2698 chip->beep_mode = beep_mode[dev];
2699#endif
2700
1da177e4 2701 /* create codec instances */
a1e21c90 2702 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2703 if (err < 0)
2704 goto out_free;
4ea6fbc8 2705#ifdef CONFIG_SND_HDA_PATCH_LOADER
41a63f18 2706 if (patch[dev] && *patch[dev]) {
4ea6fbc8
TI		 2707 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2708 patch[dev]);
2709 err = snd_hda_load_patch(chip->bus, patch[dev]);
2710 if (err < 0)
2711 goto out_free;
2712 }
2713#endif
10e77dda 2714 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2715 err = azx_codec_configure(chip);
2716 if (err < 0)
2717 goto out_free;
2718 }
1da177e4
LT		 2719
2720 /* create PCM streams */
176d5335 2721 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2722 if (err < 0)
2723 goto out_free;
1da177e4
LT		 2724
2725 /* create mixer controls */
d01ce99f 2726 err = azx_mixer_create(chip);
41dda0fd
WF		 2727 if (err < 0)
2728 goto out_free;
1da177e4 2729
d01ce99f 2730 err = snd_card_register(card);
41dda0fd
WF		 2731 if (err < 0)
2732 goto out_free;
1da177e4
LT		 2733
2734 pci_set_drvdata(pci, card);
cb53c626
TI		 2735 chip->running = 1;
2736 power_down_all_codecs(chip);
0cbf0098 2737 azx_notifier_register(chip);
1da177e4 2738
e25bcdba 2739 dev++;
1da177e4 2740 return err;
41dda0fd
WF		 2741out_free:
2742 snd_card_free(card);
2743 return err;
1da177e4
LT		 2744}
2745
2746static void __devexit azx_remove(struct pci_dev *pci)
2747{
2748 snd_card_free(pci_get_drvdata(pci));
2749 pci_set_drvdata(pci, NULL);
2750}
2751
2752/* PCI IDs */
cebe41d4 2753static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 2754 /* CPT */
32679f95 2755 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
cea310e8
SH		 2756 /* PBG */
2757 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
87218e9c
TI		 2758 /* SCH */
2759 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
b6864535
TI		 2760 /* Generic Intel */
2761 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2762 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2763 .class_mask = 0xffffff,
2764 .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2765 /* ATI SB 450/600 */
2766 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2767 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2768 /* ATI HDMI */
2769 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2770 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2771 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2772 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2773 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2774 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2775 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2776 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2777 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2778 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2779 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2780 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2781 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2782 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2783 /* VIA VT8251/VT8237A */
2784 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2785 /* SIS966 */
2786 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2787 /* ULI M5461 */
2788 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2789 /* NVIDIA MCP */
0c2fd1bf
TI		 2790 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2791 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2792 .class_mask = 0xffffff,
2793 .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2794 /* Teradici */
2795 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2796 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2797#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2798 /* the following entry conflicts with snd-ctxfi driver,
2799 * as ctxfi driver mutates from HD-audio to native mode with
2800 * a special command sequence.
2801 */
4e01f54b
TI		 2802 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2803 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2804 .class_mask = 0xffffff,
14d34f16 2805 .driver_data = AZX_DRIVER_CTX },
313f6e2d
TI		 2806#else
2807 /* this entry seems still valid -- i.e. without emu20kx chip */
14d34f16 2808 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
313f6e2d 2809#endif
e35d4b11
OS		 2810 /* Vortex86MX */
2811 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2812 /* VMware HDAudio */
2813 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2814 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2815 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2816 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2817 .class_mask = 0xffffff,
2818 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2819 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2820 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2821 .class_mask = 0xffffff,
2822 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2823 { 0, }
2824};
2825MODULE_DEVICE_TABLE(pci, azx_ids);
2826
2827/* pci_driver definition */
2828static struct pci_driver driver = {
2829 .name = "HDA Intel",
2830 .id_table = azx_ids,
2831 .probe = azx_probe,
2832 .remove = __devexit_p(azx_remove),
421a1252
TI		 2833#ifdef CONFIG_PM
2834 .suspend = azx_suspend,
2835 .resume = azx_resume,
2836#endif
1da177e4
LT		 2837};
2838
2839static int __init alsa_card_azx_init(void)
2840{
01d25d46 2841 return pci_register_driver(&driver);
1da177e4
LT		 2842}
2843
2844static void __exit alsa_card_azx_exit(void)
2845{
2846 pci_unregister_driver(&driver);
2847}
2848
2849module_init(alsa_card_azx_init)
2850module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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