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ALSA: usb-audio: Fix races at disconnection and PCM closing
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
05e84878 66#include "hda_controller.h"
2538a4f5 67#include "hda_priv.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
54a0405d
LY		 240/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
241#define AZX_DCAPS_INTEL_BROADWELL \
242 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
243 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
244 AZX_DCAPS_I915_POWERWELL)
245
9477c58e
TI		 246/* quirks for ATI SB / AMD Hudson */
247#define AZX_DCAPS_PRESET_ATI_SB \
248 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
249 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
250
251/* quirks for ATI/AMD HDMI */
252#define AZX_DCAPS_PRESET_ATI_HDMI \
253 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
254
255/* quirks for Nvidia */
256#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 257 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 258 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
259 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 260
5ae763b1
TI		 261#define AZX_DCAPS_PRESET_CTHDA \
262 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
263
a82d51ed
TI		 264/*
265 * VGA-switcher support
266 */
267#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 268#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
269#else
270#define use_vga_switcheroo(chip) 0
271#endif
272
48c8b0eb 273static char *driver_short_names[] = {
07e4ca50 274 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 275 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 276 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 277 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 278 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 279 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 280 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 281 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
282 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 283 [AZX_DRIVER_ULI] = "HDA ULI M5461",
284 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 285 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 286 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 287 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 288 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 289};
290
27fe48d9 291#ifdef CONFIG_X86
9ddf1aeb 292static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 293{
9ddf1aeb
TI		 294 int pages;
295
27fe48d9
TI		 296 if (azx_snoop(chip))
297 return;
9ddf1aeb
TI		 298 if (!dmab || !dmab->area || !dmab->bytes)
299 return;
300
301#ifdef CONFIG_SND_DMA_SGBUF
302 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
303 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 304 if (on)
9ddf1aeb 305 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 306 else
9ddf1aeb
TI		 307 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
308 return;
27fe48d9 309 }
9ddf1aeb
TI		 310#endif
311
312 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
313 if (on)
314 set_memory_wc((unsigned long)dmab->area, pages);
315 else
316 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 317}
318
319static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
320 bool on)
321{
9ddf1aeb 322 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 323}
324static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 325 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 326{
327 if (azx_dev->wc_marked != on) {
9ddf1aeb 328 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 329 azx_dev->wc_marked = on;
330 }
331}
332#else
333/* NOP for other archs */
334static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
335 bool on)
336{
337}
338static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 339 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 340{
341}
342#endif
343
68e7fffc 344static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 345
cb53c626
TI		 346/*
347 * initialize the PCI registers
348 */
349/* update bits in a PCI register byte */
350static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
351 unsigned char mask, unsigned char val)
352{
353 unsigned char data;
354
355 pci_read_config_byte(pci, reg, &data);
356 data &= ~mask;
357 data |= (val & mask);
358 pci_write_config_byte(pci, reg, data);
359}
360
361static void azx_init_pci(struct azx *chip)
362{
363 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
364 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
365 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 366 * codecs.
367 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 368 */
46f2cc80 369 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 370 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 371 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 372 }
cb53c626 373
9477c58e
TI		 374 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
375 * we need to enable snoop.
376 */
377 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 378 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
379 azx_snoop(chip));
cb53c626 380 update_pci_byte(chip->pci,
27fe48d9
TI		 381 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
382 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 383 }
384
385 /* For NVIDIA HDA, enable snoop */
386 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 387 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
388 azx_snoop(chip));
cb53c626
TI		 389 update_pci_byte(chip->pci,
390 NVIDIA_HDA_TRANSREG_ADDR,
391 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 392 update_pci_byte(chip->pci,
393 NVIDIA_HDA_ISTRM_COH,
394 0x01, NVIDIA_HDA_ENABLE_COHBIT);
395 update_pci_byte(chip->pci,
396 NVIDIA_HDA_OSTRM_COH,
397 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 398 }
399
400 /* Enable SCH/PCH snoop if needed */
401 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 402 unsigned short snoop;
90a5ad52 403 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 404 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
405 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
406 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
407 if (!azx_snoop(chip))
408 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
409 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 410 pci_read_config_word(chip->pci,
411 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 412 }
4e76a883
TI		 413 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
414 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
415 "Disabled" : "Enabled");
da3fca21 416 }
1da177e4
LT		 417}
418
9ad593f6
TI		 419static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
420
7ca954a8
DR		 421/* called from IRQ */
422static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
423{
424 int ok;
425
426 ok = azx_position_ok(chip, azx_dev);
427 if (ok == 1) {
428 azx_dev->irq_pending = 0;
429 return ok;
430 } else if (ok == 0 && chip->bus && chip->bus->workq) {
431 /* bogus IRQ, process it later */
432 azx_dev->irq_pending = 1;
433 queue_work(chip->bus->workq, &chip->irq_pending_work);
434 }
435 return 0;
436}
437
9ad593f6
TI		 438/*
439 * Check whether the current DMA position is acceptable for updating
440 * periods. Returns non-zero if it's OK.
441 *
442 * Many HD-audio controllers appear pretty inaccurate about
443 * the update-IRQ timing. The IRQ is issued before actually the
444 * data is processed. So, we need to process it afterwords in a
445 * workqueue.
446 */
447static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
448{
e5463720 449 u32 wallclk;
9ad593f6
TI		 450 unsigned int pos;
451
f48f606d
JK		 452 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
453 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 454 return -1; /* bogus (too early) interrupt */
fa00e046 455
798cb7e8 456 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 457
d6d8bf54
TI		 458 if (WARN_ONCE(!azx_dev->period_bytes,
459 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 460 return -1; /* this shouldn't happen! */
edb39935 461 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 462 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
463 /* NG - it's below the first next period boundary */
9cdc0115 464 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 465 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 466 return 1; /* OK, it's fine */
467}
468
469/*
470 * The work for pending PCM period updates.
471 */
472static void azx_irq_pending_work(struct work_struct *work)
473{
474 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 475 int i, pending, ok;
9ad593f6 476
a6a950a8 477 if (!chip->irq_pending_warned) {
4e76a883
TI		 478 dev_info(chip->card->dev,
479 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
480 chip->card->number);
a6a950a8
TI		 481 chip->irq_pending_warned = 1;
482 }
483
9ad593f6
TI		 484 for (;;) {
485 pending = 0;
486 spin_lock_irq(&chip->reg_lock);
487 for (i = 0; i < chip->num_streams; i++) {
488 struct azx_dev *azx_dev = &chip->azx_dev[i];
489 if (!azx_dev->irq_pending ||
490 !azx_dev->substream ||
491 !azx_dev->running)
492 continue;
e5463720
JK		 493 ok = azx_position_ok(chip, azx_dev);
494 if (ok > 0) {
9ad593f6
TI		 495 azx_dev->irq_pending = 0;
496 spin_unlock(&chip->reg_lock);
497 snd_pcm_period_elapsed(azx_dev->substream);
498 spin_lock(&chip->reg_lock);
e5463720
JK		 499 } else if (ok < 0) {
500 pending = 0; /* too early */
9ad593f6
TI		 501 } else
502 pending++;
503 }
504 spin_unlock_irq(&chip->reg_lock);
505 if (!pending)
506 return;
08af495f 507 msleep(1);
9ad593f6
TI		 508 }
509}
510
511/* clear irq_pending flags and assure no on-going workq */
512static void azx_clear_irq_pending(struct azx *chip)
513{
514 int i;
515
516 spin_lock_irq(&chip->reg_lock);
517 for (i = 0; i < chip->num_streams; i++)
518 chip->azx_dev[i].irq_pending = 0;
519 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 520}
521
68e7fffc
TI		 522static int azx_acquire_irq(struct azx *chip, int do_disconnect)
523{
437a5a46
TI		 524 if (request_irq(chip->pci->irq, azx_interrupt,
525 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 526 KBUILD_MODNAME, chip)) {
4e76a883
TI		 527 dev_err(chip->card->dev,
528 "unable to grab IRQ %d, disabling device\n",
529 chip->pci->irq);
68e7fffc
TI		 530 if (do_disconnect)
531 snd_card_disconnect(chip->card);
532 return -1;
533 }
534 chip->irq = chip->pci->irq;
69e13418 535 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 536 return 0;
537}
538
83012a7c 539#ifdef CONFIG_PM
65fcd41d
TI		 540static DEFINE_MUTEX(card_list_lock);
541static LIST_HEAD(card_list);
542
543static void azx_add_card_list(struct azx *chip)
544{
545 mutex_lock(&card_list_lock);
546 list_add(&chip->list, &card_list);
547 mutex_unlock(&card_list_lock);
548}
549
550static void azx_del_card_list(struct azx *chip)
551{
552 mutex_lock(&card_list_lock);
553 list_del_init(&chip->list);
554 mutex_unlock(&card_list_lock);
555}
556
557/* trigger power-save check at writing parameter */
558static int param_set_xint(const char *val, const struct kernel_param *kp)
559{
560 struct azx *chip;
561 struct hda_codec *c;
562 int prev = power_save;
563 int ret = param_set_int(val, kp);
564
565 if (ret || prev == power_save)
566 return ret;
567
568 mutex_lock(&card_list_lock);
569 list_for_each_entry(chip, &card_list, list) {
570 if (!chip->bus || chip->disabled)
571 continue;
572 list_for_each_entry(c, &chip->bus->codec_list, list)
573 snd_hda_power_sync(c);
574 }
575 mutex_unlock(&card_list_lock);
576 return 0;
577}
578#else
579#define azx_add_card_list(chip) /* NOP */
580#define azx_del_card_list(chip) /* NOP */
83012a7c 581#endif /* CONFIG_PM */
5c0b9bec 582
7ccbde57 583#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 584/*
585 * power management
586 */
68cb2b55 587static int azx_suspend(struct device *dev)
1da177e4 588{
68cb2b55
TI		 589 struct pci_dev *pci = to_pci_dev(dev);
590 struct snd_card *card = dev_get_drvdata(dev);
421a1252 591 struct azx *chip = card->private_data;
01b65bfb 592 struct azx_pcm *p;
1da177e4 593
c5c21523
TI		 594 if (chip->disabled)
595 return 0;
596
421a1252 597 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 598 azx_clear_irq_pending(chip);
01b65bfb
TI		 599 list_for_each_entry(p, &chip->pcm_list, list)
600 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 601 if (chip->initialized)
8dd78330 602 snd_hda_suspend(chip->bus);
cb53c626 603 azx_stop_chip(chip);
7295b264 604 azx_enter_link_reset(chip);
30b35399 605 if (chip->irq >= 0) {
43001c95 606 free_irq(chip->irq, chip);
30b35399
TI		 607 chip->irq = -1;
608 }
68e7fffc 609 if (chip->msi)
43001c95 610 pci_disable_msi(chip->pci);
421a1252
TI		 611 pci_disable_device(pci);
612 pci_save_state(pci);
68cb2b55 613 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 614 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
615 hda_display_power(false);
1da177e4
LT		 616 return 0;
617}
618
68cb2b55 619static int azx_resume(struct device *dev)
1da177e4 620{
68cb2b55
TI		 621 struct pci_dev *pci = to_pci_dev(dev);
622 struct snd_card *card = dev_get_drvdata(dev);
421a1252 623 struct azx *chip = card->private_data;
1da177e4 624
c5c21523
TI		 625 if (chip->disabled)
626 return 0;
627
99a2008d
WX		 628 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
629 hda_display_power(true);
d14a7e0b
TI		 630 pci_set_power_state(pci, PCI_D0);
631 pci_restore_state(pci);
30b35399 632 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 633 dev_err(chip->card->dev,
634 "pci_enable_device failed, disabling device\n");
30b35399
TI		 635 snd_card_disconnect(card);
636 return -EIO;
637 }
638 pci_set_master(pci);
68e7fffc
TI		 639 if (chip->msi)
640 if (pci_enable_msi(pci) < 0)
641 chip->msi = 0;
642 if (azx_acquire_irq(chip, 1) < 0)
30b35399 643 return -EIO;
cb53c626 644 azx_init_pci(chip);
d804ad92 645
17c3ad03 646 azx_init_chip(chip, true);
d804ad92 647
1da177e4 648 snd_hda_resume(chip->bus);
421a1252 649 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 650 return 0;
651}
b8dfc462
ML		 652#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
653
654#ifdef CONFIG_PM_RUNTIME
655static int azx_runtime_suspend(struct device *dev)
656{
657 struct snd_card *card = dev_get_drvdata(dev);
658 struct azx *chip = card->private_data;
659
246efa4a
DA		 660 if (chip->disabled)
661 return 0;
662
663 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
664 return 0;
665
7d4f606c
WX		 666 /* enable controller wake up event */
667 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
668 STATESTS_INT_MASK);
669
b8dfc462 670 azx_stop_chip(chip);
873ce8ad 671 azx_enter_link_reset(chip);
b8dfc462 672 azx_clear_irq_pending(chip);
99a2008d
WX		 673 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
674 hda_display_power(false);
b8dfc462
ML		 675 return 0;
676}
677
678static int azx_runtime_resume(struct device *dev)
679{
680 struct snd_card *card = dev_get_drvdata(dev);
681 struct azx *chip = card->private_data;
7d4f606c
WX		 682 struct hda_bus *bus;
683 struct hda_codec *codec;
684 int status;
b8dfc462 685
246efa4a
DA		 686 if (chip->disabled)
687 return 0;
688
689 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
690 return 0;
691
99a2008d
WX		 692 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
693 hda_display_power(true);
7d4f606c
WX		 694
695 /* Read STATESTS before controller reset */
696 status = azx_readw(chip, STATESTS);
697
b8dfc462 698 azx_init_pci(chip);
17c3ad03 699 azx_init_chip(chip, true);
7d4f606c
WX		 700
701 bus = chip->bus;
702 if (status && bus) {
703 list_for_each_entry(codec, &bus->codec_list, list)
704 if (status & (1 << codec->addr))
705 queue_delayed_work(codec->bus->workq,
706 &codec->jackpoll_work, codec->jackpoll_interval);
707 }
708
709 /* disable controller Wake Up event*/
710 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
711 ~STATESTS_INT_MASK);
712
b8dfc462
ML		 713 return 0;
714}
6eb827d2
TI		 715
716static int azx_runtime_idle(struct device *dev)
717{
718 struct snd_card *card = dev_get_drvdata(dev);
719 struct azx *chip = card->private_data;
720
246efa4a
DA		 721 if (chip->disabled)
722 return 0;
723
6eb827d2
TI		 724 if (!power_save_controller ||
725 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
726 return -EBUSY;
727
728 return 0;
729}
730
b8dfc462
ML		 731#endif /* CONFIG_PM_RUNTIME */
732
733#ifdef CONFIG_PM
734static const struct dev_pm_ops azx_pm = {
735 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 736 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 737};
738
68cb2b55
TI		 739#define AZX_PM_OPS &azx_pm
740#else
68cb2b55 741#define AZX_PM_OPS NULL
b8dfc462 742#endif /* CONFIG_PM */
1da177e4
LT		 743
744
0cbf0098
TI		 745/*
746 * reboot notifier for hang-up problem at power-down
747 */
748static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
749{
750 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 751 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 752 azx_stop_chip(chip);
753 return NOTIFY_OK;
754}
755
756static void azx_notifier_register(struct azx *chip)
757{
758 chip->reboot_notifier.notifier_call = azx_halt;
759 register_reboot_notifier(&chip->reboot_notifier);
760}
761
762static void azx_notifier_unregister(struct azx *chip)
763{
764 if (chip->reboot_notifier.notifier_call)
765 unregister_reboot_notifier(&chip->reboot_notifier);
766}
767
48c8b0eb 768static int azx_probe_continue(struct azx *chip);
a82d51ed 769
8393ec4a 770#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 771static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 772
a82d51ed
TI		 773static void azx_vs_set_state(struct pci_dev *pci,
774 enum vga_switcheroo_state state)
775{
776 struct snd_card *card = pci_get_drvdata(pci);
777 struct azx *chip = card->private_data;
778 bool disabled;
779
f4c482a4 780 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 781 if (chip->init_failed)
782 return;
783
784 disabled = (state == VGA_SWITCHEROO_OFF);
785 if (chip->disabled == disabled)
786 return;
787
788 if (!chip->bus) {
789 chip->disabled = disabled;
790 if (!disabled) {
4e76a883
TI		 791 dev_info(chip->card->dev,
792 "Start delayed initialization\n");
5c90680e 793 if (azx_probe_continue(chip) < 0) {
4e76a883 794 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 795 chip->init_failed = true;
796 }
797 }
798 } else {
4e76a883
TI		 799 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
800 disabled ? "Disabling" : "Enabling");
a82d51ed 801 if (disabled) {
8928756d
DR		 802 pm_runtime_put_sync_suspend(card->dev);
803 azx_suspend(card->dev);
246efa4a
DA		 804 /* when we get suspended by vga switcheroo we end up in D3cold,
805 * however we have no ACPI handle, so pci/acpi can't put us there,
806 * put ourselves there */
807 pci->current_state = PCI_D3cold;
a82d51ed 808 chip->disabled = true;
128960a9 809 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 810 dev_warn(chip->card->dev,
811 "Cannot lock devices!\n");
a82d51ed
TI		 812 } else {
813 snd_hda_unlock_devices(chip->bus);
8928756d 814 pm_runtime_get_noresume(card->dev);
a82d51ed 815 chip->disabled = false;
8928756d 816 azx_resume(card->dev);
a82d51ed
TI		 817 }
818 }
819}
820
821static bool azx_vs_can_switch(struct pci_dev *pci)
822{
823 struct snd_card *card = pci_get_drvdata(pci);
824 struct azx *chip = card->private_data;
825
f4c482a4 826 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 827 if (chip->init_failed)
828 return false;
829 if (chip->disabled || !chip->bus)
830 return true;
831 if (snd_hda_lock_devices(chip->bus))
832 return false;
833 snd_hda_unlock_devices(chip->bus);
834 return true;
835}
836
e23e7a14 837static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 838{
839 struct pci_dev *p = get_bound_vga(chip->pci);
840 if (p) {
4e76a883
TI		 841 dev_info(chip->card->dev,
842 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 843 chip->use_vga_switcheroo = 1;
844 pci_dev_put(p);
845 }
846}
847
848static const struct vga_switcheroo_client_ops azx_vs_ops = {
849 .set_gpu_state = azx_vs_set_state,
850 .can_switch = azx_vs_can_switch,
851};
852
e23e7a14 853static int register_vga_switcheroo(struct azx *chip)
a82d51ed 854{
128960a9
TI		 855 int err;
856
a82d51ed
TI		 857 if (!chip->use_vga_switcheroo)
858 return 0;
859 /* FIXME: currently only handling DIS controller
860 * is there any machine with two switchable HDMI audio controllers?
861 */
128960a9 862 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 863 VGA_SWITCHEROO_DIS,
864 chip->bus != NULL);
128960a9
TI		 865 if (err < 0)
866 return err;
867 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 868
869 /* register as an optimus hdmi audio power domain */
8928756d
DR		 870 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
871 &chip->hdmi_pm_domain);
128960a9 872 return 0;
a82d51ed
TI		 873}
874#else
875#define init_vga_switcheroo(chip) /* NOP */
876#define register_vga_switcheroo(chip) 0
8393ec4a 877#define check_hdmi_disabled(pci) false
a82d51ed
TI		 878#endif /* SUPPORT_VGA_SWITCHER */
879
1da177e4
LT		 880/*
881 * destructor
882 */
a98f90fd 883static int azx_free(struct azx *chip)
1da177e4 884{
c67e2228 885 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 886 int i;
887
c67e2228
WX		 888 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
889 && chip->running)
890 pm_runtime_get_noresume(&pci->dev);
891
65fcd41d
TI		 892 azx_del_card_list(chip);
893
0cbf0098
TI		 894 azx_notifier_unregister(chip);
895
f4c482a4 896 chip->init_failed = 1; /* to be sure */
44728e97 897 complete_all(&chip->probe_wait);
f4c482a4 898
a82d51ed
TI		 899 if (use_vga_switcheroo(chip)) {
900 if (chip->disabled && chip->bus)
901 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 902 if (chip->vga_switcheroo_registered)
903 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 904 }
905
ce43fbae 906 if (chip->initialized) {
9ad593f6 907 azx_clear_irq_pending(chip);
07e4ca50 908 for (i = 0; i < chip->num_streams; i++)
1da177e4 909 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 910 azx_stop_chip(chip);
1da177e4
LT		 911 }
912
f000fd80 913 if (chip->irq >= 0)
1da177e4 914 free_irq(chip->irq, (void*)chip);
68e7fffc 915 if (chip->msi)
30b35399 916 pci_disable_msi(chip->pci);
f079c25a
TI		 917 if (chip->remap_addr)
918 iounmap(chip->remap_addr);
1da177e4 919
67908994 920 azx_free_stream_pages(chip);
a82d51ed
TI		 921 if (chip->region_requested)
922 pci_release_regions(chip->pci);
1da177e4 923 pci_disable_device(chip->pci);
07e4ca50 924 kfree(chip->azx_dev);
4918cdab
TI		 925#ifdef CONFIG_SND_HDA_PATCH_LOADER
926 if (chip->fw)
927 release_firmware(chip->fw);
928#endif
99a2008d
WX		 929 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
930 hda_display_power(false);
931 hda_i915_exit();
932 }
1da177e4
LT		 933 kfree(chip);
934
935 return 0;
936}
937
a98f90fd 938static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 939{
940 return azx_free(device->device_data);
941}
942
8393ec4a 943#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 944/*
945 * Check of disabled HDMI controller by vga-switcheroo
946 */
e23e7a14 947static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 948{
949 struct pci_dev *p;
950
951 /* check only discrete GPU */
952 switch (pci->vendor) {
953 case PCI_VENDOR_ID_ATI:
954 case PCI_VENDOR_ID_AMD:
955 case PCI_VENDOR_ID_NVIDIA:
956 if (pci->devfn == 1) {
957 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
958 pci->bus->number, 0);
959 if (p) {
960 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
961 return p;
962 pci_dev_put(p);
963 }
964 }
965 break;
966 }
967 return NULL;
968}
969
e23e7a14 970static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 971{
972 bool vga_inactive = false;
973 struct pci_dev *p = get_bound_vga(pci);
974
975 if (p) {
12b78a7f 976 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 977 vga_inactive = true;
978 pci_dev_put(p);
979 }
980 return vga_inactive;
981}
8393ec4a 982#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 983
3372a153
TI		 984/*
985 * white/black-listing for position_fix
986 */
e23e7a14 987static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 988 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
989 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 990 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 991 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 992 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 993 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 994 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 995 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 996 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 997 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 998 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 999 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1000 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1001 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1002 {}
1003};
1004
e23e7a14 1005static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1006{
1007 const struct snd_pci_quirk *q;
1008
c673ba1c 1009 switch (fix) {
1dac6695 1010 case POS_FIX_AUTO:
c673ba1c
TI		 1011 case POS_FIX_LPIB:
1012 case POS_FIX_POSBUF:
4cb36310 1013 case POS_FIX_VIACOMBO:
a6f2fd55 1014 case POS_FIX_COMBO:
c673ba1c
TI		 1015 return fix;
1016 }
1017
c673ba1c
TI		 1018 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1019 if (q) {
4e76a883
TI		 1020 dev_info(chip->card->dev,
1021 "position_fix set to %d for device %04x:%04x\n",
1022 q->value, q->subvendor, q->subdevice);
c673ba1c 1023 return q->value;
3372a153 1024 }
bdd9ef24
DH		 1025
1026 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1027 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1028 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1029 return POS_FIX_VIACOMBO;
9477c58e
TI		 1030 }
1031 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1032 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1033 return POS_FIX_LPIB;
bdd9ef24 1034 }
c673ba1c 1035 return POS_FIX_AUTO;
3372a153
TI		 1036}
1037
669ba27a
TI		 1038/*
1039 * black-lists for probe_mask
1040 */
e23e7a14 1041static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1042 /* Thinkpad often breaks the controller communication when accessing
1043 * to the non-working (or non-existing) modem codec slot.
1044 */
1045 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1046 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1047 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1048 /* broken BIOS */
1049 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1050 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1051 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1052 /* forced codec slots */
93574844 1053 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1054 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1055 /* WinFast VP200 H (Teradici) user reported broken communication */
1056 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1057 {}
1058};
1059
f1eaaeec
TI		 1060#define AZX_FORCE_CODEC_MASK 0x100
1061
e23e7a14 1062static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1063{
1064 const struct snd_pci_quirk *q;
1065
f1eaaeec
TI		 1066 chip->codec_probe_mask = probe_mask[dev];
1067 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1068 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1069 if (q) {
4e76a883
TI		 1070 dev_info(chip->card->dev,
1071 "probe_mask set to 0x%x for device %04x:%04x\n",
1072 q->value, q->subvendor, q->subdevice);
f1eaaeec 1073 chip->codec_probe_mask = q->value;
669ba27a
TI		 1074 }
1075 }
f1eaaeec
TI		 1076
1077 /* check forced option */
1078 if (chip->codec_probe_mask != -1 &&
1079 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1080 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1081 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1082 chip->codec_mask);
f1eaaeec 1083 }
669ba27a
TI		 1084}
1085
4d8e22e0 1086/*
71623855 1087 * white/black-list for enable_msi
4d8e22e0 1088 */
e23e7a14 1089static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1090 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1091 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1092 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1093 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1094 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1095 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1096 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1097 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1098 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1099 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1100 {}
1101};
1102
e23e7a14 1103static void check_msi(struct azx *chip)
4d8e22e0
TI		 1104{
1105 const struct snd_pci_quirk *q;
1106
71623855
TI		 1107 if (enable_msi >= 0) {
1108 chip->msi = !!enable_msi;
4d8e22e0 1109 return;
71623855
TI		 1110 }
1111 chip->msi = 1; /* enable MSI as default */
1112 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1113 if (q) {
4e76a883
TI		 1114 dev_info(chip->card->dev,
1115 "msi for device %04x:%04x set to %d\n",
1116 q->subvendor, q->subdevice, q->value);
4d8e22e0 1117 chip->msi = q->value;
80c43ed7
TI		 1118 return;
1119 }
1120
1121 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1122 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1123 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1124 chip->msi = 0;
4d8e22e0
TI		 1125 }
1126}
1127
a1585d76 1128/* check the snoop mode availability */
e23e7a14 1129static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1130{
1131 bool snoop = chip->snoop;
1132
1133 switch (chip->driver_type) {
1134 case AZX_DRIVER_VIA:
1135 /* force to non-snoop mode for a new VIA controller
1136 * when BIOS is set
1137 */
1138 if (snoop) {
1139 u8 val;
1140 pci_read_config_byte(chip->pci, 0x42, &val);
1141 if (!(val & 0x80) && chip->pci->revision == 0x30)
1142 snoop = false;
1143 }
1144 break;
1145 case AZX_DRIVER_ATIHDMI_NS:
1146 /* new ATI HDMI requires non-snoop */
1147 snoop = false;
1148 break;
c1279f87
TI		 1149 case AZX_DRIVER_CTHDA:
1150 snoop = false;
1151 break;
a1585d76
TI		 1152 }
1153
1154 if (snoop != chip->snoop) {
4e76a883
TI		 1155 dev_info(chip->card->dev, "Force to %s mode\n",
1156 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1157 chip->snoop = snoop;
1158 }
1159}
669ba27a 1160
99a2008d
WX		 1161static void azx_probe_work(struct work_struct *work)
1162{
1163 azx_probe_continue(container_of(work, struct azx, probe_work));
1164}
99a2008d 1165
1da177e4
LT		 1166/*
1167 * constructor
1168 */
e23e7a14
BP		 1169static int azx_create(struct snd_card *card, struct pci_dev *pci,
1170 int dev, unsigned int driver_caps,
40830813 1171 const struct hda_controller_ops *hda_ops,
e23e7a14 1172 struct azx **rchip)
1da177e4 1173{
a98f90fd 1174 static struct snd_device_ops ops = {
1da177e4
LT		 1175 .dev_free = azx_dev_free,
1176 };
a82d51ed
TI		 1177 struct azx *chip;
1178 int err;
1da177e4
LT		 1179
1180 *rchip = NULL;
bcd72003 1181
927fc866
PM		 1182 err = pci_enable_device(pci);
1183 if (err < 0)
1da177e4
LT		 1184 return err;
1185
e560d8d8 1186 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1187 if (!chip) {
4e76a883 1188 dev_err(card->dev, "Cannot allocate chip\n");
1da177e4
LT		 1189 pci_disable_device(pci);
1190 return -ENOMEM;
1191 }
1192
1193 spin_lock_init(&chip->reg_lock);
62932df8 1194 mutex_init(&chip->open_mutex);
1da177e4
LT		 1195 chip->card = card;
1196 chip->pci = pci;
40830813 1197 chip->ops = hda_ops;
1da177e4 1198 chip->irq = -1;
9477c58e
TI		 1199 chip->driver_caps = driver_caps;
1200 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1201 check_msi(chip);
555e219f 1202 chip->dev_index = dev;
749ee287 1203 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1204 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1205 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1206 INIT_LIST_HEAD(&chip->list);
a82d51ed 1207 init_vga_switcheroo(chip);
f4c482a4 1208 init_completion(&chip->probe_wait);
1da177e4 1209
beaffc39
SG		 1210 chip->position_fix[0] = chip->position_fix[1] =
1211 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1212 /* combo mode uses LPIB for playback */
1213 if (chip->position_fix[0] == POS_FIX_COMBO) {
1214 chip->position_fix[0] = POS_FIX_LPIB;
1215 chip->position_fix[1] = POS_FIX_AUTO;
1216 }
1217
5aba4f8e 1218 check_probe_mask(chip, dev);
3372a153 1219
27346166 1220 chip->single_cmd = single_cmd;
27fe48d9 1221 chip->snoop = hda_snoop;
a1585d76 1222 azx_check_snoop_available(chip);
c74db86b 1223
5c0d7bc1
TI		 1224 if (bdl_pos_adj[dev] < 0) {
1225 switch (chip->driver_type) {
0c6341ac 1226 case AZX_DRIVER_ICH:
32679f95 1227 case AZX_DRIVER_PCH:
0c6341ac 1228 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1229 break;
1230 default:
0c6341ac 1231 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1232 break;
1233 }
1234 }
9cdc0115 1235 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1236
a82d51ed
TI		 1237 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1238 if (err < 0) {
4e76a883 1239 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1240 azx_free(chip);
1241 return err;
1242 }
1243
99a2008d
WX		 1244 /* continue probing in work context as may trigger request module */
1245 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1246
a82d51ed 1247 *rchip = chip;
99a2008d 1248
a82d51ed
TI		 1249 return 0;
1250}
1251
48c8b0eb 1252static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1253{
1254 int dev = chip->dev_index;
1255 struct pci_dev *pci = chip->pci;
1256 struct snd_card *card = chip->card;
67908994 1257 int err;
a82d51ed
TI		 1258 unsigned short gcap;
1259
07e4ca50
TI		 1260#if BITS_PER_LONG != 64
1261 /* Fix up base address on ULI M5461 */
1262 if (chip->driver_type == AZX_DRIVER_ULI) {
1263 u16 tmp3;
1264 pci_read_config_word(pci, 0x40, &tmp3);
1265 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1266 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1267 }
1268#endif
1269
927fc866 1270 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1271 if (err < 0)
1da177e4 1272 return err;
a82d51ed 1273 chip->region_requested = 1;
1da177e4 1274
927fc866 1275 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1276 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1277 if (chip->remap_addr == NULL) {
4e76a883 1278 dev_err(card->dev, "ioremap error\n");
a82d51ed 1279 return -ENXIO;
1da177e4
LT		 1280 }
1281
68e7fffc
TI		 1282 if (chip->msi)
1283 if (pci_enable_msi(pci) < 0)
1284 chip->msi = 0;
7376d013 1285
a82d51ed
TI		 1286 if (azx_acquire_irq(chip, 0) < 0)
1287 return -EBUSY;
1da177e4
LT		 1288
1289 pci_set_master(pci);
1290 synchronize_irq(chip->irq);
1291
bcd72003 1292 gcap = azx_readw(chip, GCAP);
4e76a883 1293 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1294
dc4c2e6b 1295 /* disable SB600 64bit support for safety */
9477c58e 1296 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1297 struct pci_dev *p_smbus;
1298 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1299 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1300 NULL);
1301 if (p_smbus) {
1302 if (p_smbus->revision < 0x30)
1303 gcap &= ~ICH6_GCAP_64OK;
1304 pci_dev_put(p_smbus);
1305 }
1306 }
09240cf4 1307
9477c58e
TI		 1308 /* disable 64bit DMA address on some devices */
1309 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1310 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1311 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1312 }
396087ea 1313
2ae66c26 1314 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1315 if (align_buffer_size >= 0)
1316 chip->align_buffer_size = !!align_buffer_size;
1317 else {
1318 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1319 chip->align_buffer_size = 0;
1320 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1321 chip->align_buffer_size = 1;
1322 else
1323 chip->align_buffer_size = 1;
1324 }
2ae66c26 1325
cf7aaca8 1326 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1327 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1328 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1329 else {
e930438c
YH		 1330 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1331 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1332 }
cf7aaca8 1333
8b6ed8e7
TI		 1334 /* read number of streams from GCAP register instead of using
1335 * hardcoded value
1336 */
1337 chip->capture_streams = (gcap >> 8) & 0x0f;
1338 chip->playback_streams = (gcap >> 12) & 0x0f;
1339 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1340 /* gcap didn't give any info, switching to old method */
1341
1342 switch (chip->driver_type) {
1343 case AZX_DRIVER_ULI:
1344 chip->playback_streams = ULI_NUM_PLAYBACK;
1345 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1346 break;
1347 case AZX_DRIVER_ATIHDMI:
1815b34a 1348 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1349 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1350 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1351 break;
c4da29ca 1352 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1353 default:
1354 chip->playback_streams = ICH6_NUM_PLAYBACK;
1355 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1356 break;
1357 }
07e4ca50 1358 }
8b6ed8e7
TI		 1359 chip->capture_index_offset = 0;
1360 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1361 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1362 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1363 GFP_KERNEL);
927fc866 1364 if (!chip->azx_dev) {
4e76a883 1365 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1366 return -ENOMEM;
07e4ca50
TI		 1367 }
1368
67908994 1369 err = azx_alloc_stream_pages(chip);
81740861 1370 if (err < 0)
a82d51ed 1371 return err;
1da177e4
LT		 1372
1373 /* initialize streams */
1374 azx_init_stream(chip);
1375
1376 /* initialize chip */
cb53c626 1377 azx_init_pci(chip);
10e77dda 1378 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1379
1380 /* codec detection */
927fc866 1381 if (!chip->codec_mask) {
4e76a883 1382 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1383 return -ENODEV;
1da177e4
LT		 1384 }
1385
07e4ca50 1386 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1387 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1388 sizeof(card->shortname));
1389 snprintf(card->longname, sizeof(card->longname),
1390 "%s at 0x%lx irq %i",
1391 card->shortname, chip->addr, chip->irq);
07e4ca50 1392
1da177e4 1393 return 0;
1da177e4
LT		 1394}
1395
cb53c626
TI		 1396static void power_down_all_codecs(struct azx *chip)
1397{
83012a7c 1398#ifdef CONFIG_PM
cb53c626
TI		 1399 /* The codecs were powered up in snd_hda_codec_new().
1400 * Now all initialization done, so turn them down if possible
1401 */
1402 struct hda_codec *codec;
1403 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1404 snd_hda_power_down(codec);
1405 }
1406#endif
1407}
1408
97c6a3d1 1409#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1410/* callback from request_firmware_nowait() */
1411static void azx_firmware_cb(const struct firmware *fw, void *context)
1412{
1413 struct snd_card *card = context;
1414 struct azx *chip = card->private_data;
1415 struct pci_dev *pci = chip->pci;
1416
1417 if (!fw) {
4e76a883 1418 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1419 goto error;
1420 }
1421
1422 chip->fw = fw;
1423 if (!chip->disabled) {
1424 /* continue probing */
1425 if (azx_probe_continue(chip))
1426 goto error;
1427 }
1428 return; /* OK */
1429
1430 error:
1431 snd_card_free(card);
1432 pci_set_drvdata(pci, NULL);
1433}
97c6a3d1 1434#endif
5cb543db 1435
40830813
DR		 1436/*
1437 * HDA controller ops.
1438 */
1439
1440/* PCI register access. */
db291e36 1441static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1442{
1443 writel(value, addr);
1444}
1445
db291e36 1446static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1447{
1448 return readl(addr);
1449}
1450
db291e36 1451static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1452{
1453 writew(value, addr);
1454}
1455
db291e36 1456static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1457{
1458 return readw(addr);
1459}
1460
db291e36 1461static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1462{
1463 writeb(value, addr);
1464}
1465
db291e36 1466static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1467{
1468 return readb(addr);
1469}
1470
f46ea609
DR		 1471static int disable_msi_reset_irq(struct azx *chip)
1472{
1473 int err;
1474
1475 free_irq(chip->irq, chip);
1476 chip->irq = -1;
1477 pci_disable_msi(chip->pci);
1478 chip->msi = 0;
1479 err = azx_acquire_irq(chip, 1);
1480 if (err < 0)
1481 return err;
1482
1483 return 0;
1484}
1485
b419b35b
DR		 1486/* DMA page allocation helpers. */
1487static int dma_alloc_pages(struct azx *chip,
1488 int type,
1489 size_t size,
1490 struct snd_dma_buffer *buf)
1491{
1492 int err;
1493
1494 err = snd_dma_alloc_pages(type,
1495 chip->card->dev,
1496 size, buf);
1497 if (err < 0)
1498 return err;
1499 mark_pages_wc(chip, buf, true);
1500 return 0;
1501}
1502
1503static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1504{
1505 mark_pages_wc(chip, buf, false);
1506 snd_dma_free_pages(buf);
1507}
1508
1509static int substream_alloc_pages(struct azx *chip,
1510 struct snd_pcm_substream *substream,
1511 size_t size)
1512{
1513 struct azx_dev *azx_dev = get_azx_dev(substream);
1514 int ret;
1515
1516 mark_runtime_wc(chip, azx_dev, substream, false);
1517 azx_dev->bufsize = 0;
1518 azx_dev->period_bytes = 0;
1519 azx_dev->format_val = 0;
1520 ret = snd_pcm_lib_malloc_pages(substream, size);
1521 if (ret < 0)
1522 return ret;
1523 mark_runtime_wc(chip, azx_dev, substream, true);
1524 return 0;
1525}
1526
1527static int substream_free_pages(struct azx *chip,
1528 struct snd_pcm_substream *substream)
1529{
1530 struct azx_dev *azx_dev = get_azx_dev(substream);
1531 mark_runtime_wc(chip, azx_dev, substream, false);
1532 return snd_pcm_lib_free_pages(substream);
1533}
1534
8769b278
DR		 1535static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1536 struct vm_area_struct *area)
1537{
1538#ifdef CONFIG_X86
1539 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1540 struct azx *chip = apcm->chip;
1541 if (!azx_snoop(chip))
1542 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1543#endif
1544}
1545
40830813 1546static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1547 .reg_writel = pci_azx_writel,
1548 .reg_readl = pci_azx_readl,
1549 .reg_writew = pci_azx_writew,
1550 .reg_readw = pci_azx_readw,
1551 .reg_writeb = pci_azx_writeb,
1552 .reg_readb = pci_azx_readb,
f46ea609 1553 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1554 .dma_alloc_pages = dma_alloc_pages,
1555 .dma_free_pages = dma_free_pages,
1556 .substream_alloc_pages = substream_alloc_pages,
1557 .substream_free_pages = substream_free_pages,
8769b278 1558 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1559 .position_check = azx_position_check,
40830813
DR		 1560};
1561
e23e7a14
BP		 1562static int azx_probe(struct pci_dev *pci,
1563 const struct pci_device_id *pci_id)
1da177e4 1564{
5aba4f8e 1565 static int dev;
a98f90fd
TI		 1566 struct snd_card *card;
1567 struct azx *chip;
aad730d0 1568 bool schedule_probe;
927fc866 1569 int err;
1da177e4 1570
5aba4f8e
TI		 1571 if (dev >= SNDRV_CARDS)
1572 return -ENODEV;
1573 if (!enable[dev]) {
1574 dev++;
1575 return -ENOENT;
1576 }
1577
60c5772b
TI		 1578 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1579 0, &card);
e58de7ba 1580 if (err < 0) {
4e76a883 1581 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1582 return err;
1da177e4
LT		 1583 }
1584
40830813
DR		 1585 err = azx_create(card, pci, dev, pci_id->driver_data,
1586 &pci_hda_ops, &chip);
41dda0fd
WF		 1587 if (err < 0)
1588 goto out_free;
421a1252 1589 card->private_data = chip;
f4c482a4
TI		 1590
1591 pci_set_drvdata(pci, card);
1592
1593 err = register_vga_switcheroo(chip);
1594 if (err < 0) {
4e76a883 1595 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1596 goto out_free;
1597 }
1598
1599 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1600 dev_info(card->dev, "VGA controller is disabled\n");
1601 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1602 chip->disabled = true;
1603 }
1604
aad730d0 1605 schedule_probe = !chip->disabled;
1da177e4 1606
4918cdab
TI		 1607#ifdef CONFIG_SND_HDA_PATCH_LOADER
1608 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1609 dev_info(card->dev, "Applying patch firmware '%s'\n",
1610 patch[dev]);
5cb543db
TI		 1611 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1612 &pci->dev, GFP_KERNEL, card,
1613 azx_firmware_cb);
4918cdab
TI		 1614 if (err < 0)
1615 goto out_free;
aad730d0 1616 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1617 }
1618#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1619
aad730d0
TI		 1620#ifndef CONFIG_SND_HDA_I915
1621 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1622 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1623#endif
99a2008d 1624
aad730d0
TI		 1625 if (schedule_probe)
1626 schedule_work(&chip->probe_work);
a82d51ed 1627
a82d51ed 1628 dev++;
88d071fc
TI		 1629 if (chip->disabled)
1630 complete_all(&chip->probe_wait);
a82d51ed
TI		 1631 return 0;
1632
1633out_free:
1634 snd_card_free(card);
1635 return err;
1636}
1637
e62a42ae
DR		 1638/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1639static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1640 [AZX_DRIVER_NVIDIA] = 8,
1641 [AZX_DRIVER_TERA] = 1,
1642};
1643
48c8b0eb 1644static int azx_probe_continue(struct azx *chip)
a82d51ed 1645{
c67e2228 1646 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1647 int dev = chip->dev_index;
1648 int err;
1649
99a2008d
WX		 1650 /* Request power well for Haswell HDA controller and codec */
1651 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1652#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1653 err = hda_i915_init();
1654 if (err < 0) {
4e76a883
TI		 1655 dev_err(chip->card->dev,
1656 "Error request power-well from i915\n");
99a2008d
WX		 1657 goto out_free;
1658 }
74b0c2d7
TI		 1659 err = hda_display_power(true);
1660 if (err < 0) {
1661 dev_err(chip->card->dev,
1662 "Cannot turn on display power on i915\n");
1663 goto out_free;
1664 }
c841ad2a 1665#endif
99a2008d
WX		 1666 }
1667
5c90680e
TI		 1668 err = azx_first_init(chip);
1669 if (err < 0)
1670 goto out_free;
1671
2dca0bba
JK		 1672#ifdef CONFIG_SND_HDA_INPUT_BEEP
1673 chip->beep_mode = beep_mode[dev];
1674#endif
1675
1da177e4 1676 /* create codec instances */
e62a42ae
DR		 1677 err = azx_codec_create(chip, model[dev],
1678 azx_max_codecs[chip->driver_type],
1679 power_save_addr);
1680
41dda0fd
WF		 1681 if (err < 0)
1682 goto out_free;
4ea6fbc8 1683#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1684 if (chip->fw) {
1685 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1686 chip->fw->data);
4ea6fbc8
TI		 1687 if (err < 0)
1688 goto out_free;
e39ae856 1689#ifndef CONFIG_PM
4918cdab
TI		 1690 release_firmware(chip->fw); /* no longer needed */
1691 chip->fw = NULL;
e39ae856 1692#endif
4ea6fbc8
TI		 1693 }
1694#endif
10e77dda 1695 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1696 err = azx_codec_configure(chip);
1697 if (err < 0)
1698 goto out_free;
1699 }
1da177e4
LT		 1700
1701 /* create PCM streams */
176d5335 1702 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1703 if (err < 0)
1704 goto out_free;
1da177e4
LT		 1705
1706 /* create mixer controls */
d01ce99f 1707 err = azx_mixer_create(chip);
41dda0fd
WF		 1708 if (err < 0)
1709 goto out_free;
1da177e4 1710
a82d51ed 1711 err = snd_card_register(chip->card);
41dda0fd
WF		 1712 if (err < 0)
1713 goto out_free;
1da177e4 1714
cb53c626
TI		 1715 chip->running = 1;
1716 power_down_all_codecs(chip);
0cbf0098 1717 azx_notifier_register(chip);
65fcd41d 1718 azx_add_card_list(chip);
246efa4a 1719 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1720 pm_runtime_put_noidle(&pci->dev);
1da177e4 1721
41dda0fd 1722out_free:
88d071fc
TI		 1723 if (err < 0)
1724 chip->init_failed = 1;
1725 complete_all(&chip->probe_wait);
41dda0fd 1726 return err;
1da177e4
LT		 1727}
1728
e23e7a14 1729static void azx_remove(struct pci_dev *pci)
1da177e4 1730{
9121947d 1731 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1732
9121947d
TI		 1733 if (card)
1734 snd_card_free(card);
1da177e4
LT		 1735}
1736
1737/* PCI IDs */
6f51f6cf 1738static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1739 /* CPT */
9477c58e 1740 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1741 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1742 /* PBG */
9477c58e 1743 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1744 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1745 /* Panther Point */
9477c58e 1746 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1747 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1748 /* Lynx Point */
1749 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1750 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1751 /* 9 Series */
1752 { PCI_DEVICE(0x8086, 0x8ca0),
1753 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1754 /* Wellsburg */
1755 { PCI_DEVICE(0x8086, 0x8d20),
1756 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1757 { PCI_DEVICE(0x8086, 0x8d21),
1758 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1759 /* Lynx Point-LP */
1760 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1761 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1762 /* Lynx Point-LP */
1763 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1764 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1765 /* Wildcat Point-LP */
1766 { PCI_DEVICE(0x8086, 0x9ca0),
1767 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 1768 /* Haswell */
4a7c516b 1769 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1770 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1771 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1772 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1773 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1774 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1775 /* Broadwell */
1776 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 1777 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 1778 /* 5 Series/3400 */
1779 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1780 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1781 /* Poulsbo */
9477c58e 1782 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1783 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1784 /* Oaktrail */
09904b95 1785 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1786 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1787 /* BayTrail */
1788 { PCI_DEVICE(0x8086, 0x0f04),
1789 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 1790 /* ICH */
8b0bd226 1791 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 1792 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1793 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 1794 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 1795 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1796 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 1797 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 1798 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1799 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 1800 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 1801 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1802 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 1803 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 1804 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1805 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1806 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 1807 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1808 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1809 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 1810 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1811 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 1812 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 1813 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1814 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 1815 /* Generic Intel */
1816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
1817 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1818 .class_mask = 0xffffff,
2ae66c26 1819 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 1820 /* ATI SB 450/600/700/800/900 */
1821 { PCI_DEVICE(0x1002, 0x437b),
1822 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1823 { PCI_DEVICE(0x1002, 0x4383),
1824 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1825 /* AMD Hudson */
1826 { PCI_DEVICE(0x1022, 0x780d),
1827 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 1828 /* ATI HDMI */
9477c58e
TI		 1829 { PCI_DEVICE(0x1002, 0x793b),
1830 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1831 { PCI_DEVICE(0x1002, 0x7919),
1832 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1833 { PCI_DEVICE(0x1002, 0x960f),
1834 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1835 { PCI_DEVICE(0x1002, 0x970f),
1836 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1837 { PCI_DEVICE(0x1002, 0xaa00),
1838 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1839 { PCI_DEVICE(0x1002, 0xaa08),
1840 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1841 { PCI_DEVICE(0x1002, 0xaa10),
1842 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1843 { PCI_DEVICE(0x1002, 0xaa18),
1844 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1845 { PCI_DEVICE(0x1002, 0xaa20),
1846 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1847 { PCI_DEVICE(0x1002, 0xaa28),
1848 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1849 { PCI_DEVICE(0x1002, 0xaa30),
1850 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1851 { PCI_DEVICE(0x1002, 0xaa38),
1852 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1853 { PCI_DEVICE(0x1002, 0xaa40),
1854 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1855 { PCI_DEVICE(0x1002, 0xaa48),
1856 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 1857 { PCI_DEVICE(0x1002, 0xaa50),
1858 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1859 { PCI_DEVICE(0x1002, 0xaa58),
1860 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1861 { PCI_DEVICE(0x1002, 0xaa60),
1862 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1863 { PCI_DEVICE(0x1002, 0xaa68),
1864 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1865 { PCI_DEVICE(0x1002, 0xaa80),
1866 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1867 { PCI_DEVICE(0x1002, 0xaa88),
1868 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1869 { PCI_DEVICE(0x1002, 0xaa90),
1870 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1871 { PCI_DEVICE(0x1002, 0xaa98),
1872 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 1873 { PCI_DEVICE(0x1002, 0x9902),
1874 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1875 { PCI_DEVICE(0x1002, 0xaaa0),
1876 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1877 { PCI_DEVICE(0x1002, 0xaaa8),
1878 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1879 { PCI_DEVICE(0x1002, 0xaab0),
1880 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 1881 /* VIA VT8251/VT8237A */
9477c58e
TI		 1882 { PCI_DEVICE(0x1106, 0x3288),
1883 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 1884 /* VIA GFX VT7122/VX900 */
1885 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
1886 /* VIA GFX VT6122/VX11 */
1887 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 1888 /* SIS966 */
1889 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
1890 /* ULI M5461 */
1891 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
1892 /* NVIDIA MCP */
0c2fd1bf
TI		 1893 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1894 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1895 .class_mask = 0xffffff,
9477c58e 1896 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 1897 /* Teradici */
9477c58e
TI		 1898 { PCI_DEVICE(0x6549, 0x1200),
1899 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 1900 { PCI_DEVICE(0x6549, 0x2200),
1901 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 1902 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 1903 /* CTHDA chips */
1904 { PCI_DEVICE(0x1102, 0x0010),
1905 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
1906 { PCI_DEVICE(0x1102, 0x0012),
1907 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 1908#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 1909 /* the following entry conflicts with snd-ctxfi driver,
1910 * as ctxfi driver mutates from HD-audio to native mode with
1911 * a special command sequence.
1912 */
4e01f54b
TI		 1913 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
1914 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1915 .class_mask = 0xffffff,
9477c58e 1916 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1917 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 1918#else
1919 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 1920 { PCI_DEVICE(0x1102, 0x0009),
1921 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1922 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 1923#endif
e35d4b11
OS		 1924 /* Vortex86MX */
1925 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 1926 /* VMware HDAudio */
1927 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 1928 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 1929 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
1930 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1931 .class_mask = 0xffffff,
9477c58e 1932 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 1933 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1934 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1935 .class_mask = 0xffffff,
9477c58e 1936 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 1937 { 0, }
1938};
1939MODULE_DEVICE_TABLE(pci, azx_ids);
1940
1941/* pci_driver definition */
e9f66d9b 1942static struct pci_driver azx_driver = {
3733e424 1943 .name = KBUILD_MODNAME,
1da177e4
LT		 1944 .id_table = azx_ids,
1945 .probe = azx_probe,
e23e7a14 1946 .remove = azx_remove,
68cb2b55
TI		 1947 .driver = {
1948 .pm = AZX_PM_OPS,
1949 },
1da177e4
LT		 1950};
1951
e9f66d9b 1952module_pci_driver(azx_driver);
Linux kernel - Deliverables
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