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ALSA: hda - Don't reset BDL unnecessarily
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
134a11f0 63static int enable_msi;
1da177e4 64
5aba4f8e 65module_param_array(index, int, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 67module_param_array(id, charp, NULL, 0444);
1da177e4 68MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71module_param_array(model, charp, NULL, 0444);
1da177e4 72MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 73module_param_array(position_fix, int, NULL, 0444);
d01ce99f 74MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 75 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 76module_param_array(bdl_pos_adj, int, NULL, 0644);
77MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 78module_param_array(probe_mask, int, NULL, 0444);
606ad75f 79MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 80module_param_array(probe_only, bool, NULL, 0444);
81MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 82module_param(single_cmd, bool, 0444);
d01ce99f
TI		 83MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
5aba4f8e 85module_param(enable_msi, int, 0444);
134a11f0 86MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 87
dee1b66c 88#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 89static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90module_param(power_save, int, 0644);
91MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
1da177e4 93
dee1b66c
TI		 94/* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98static int power_save_controller = 1;
99module_param(power_save_controller, bool, 0644);
100MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101#endif
102
1da177e4
LT		 103MODULE_LICENSE("GPL");
104MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
2f1b3818 106 "{Intel, ICH7},"
f5d40b30 107 "{Intel, ESB2},"
d2981393 108 "{Intel, ICH8},"
f9cc8a8b 109 "{Intel, ICH9},"
c34f5a04 110 "{Intel, ICH10},"
b29c2360 111 "{Intel, PCH},"
4979bca9 112 "{Intel, SCH},"
fc20a562 113 "{ATI, SB450},"
89be83f8 114 "{ATI, SB600},"
778b6e1b 115 "{ATI, RS600},"
5b15c95f 116 "{ATI, RS690},"
e6db1119
WL		 117 "{ATI, RS780},"
118 "{ATI, R600},"
2797f724
HRK		 119 "{ATI, RV630},"
120 "{ATI, RV610},"
27da1834
WL		 121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
fc20a562 125 "{VIA, VT8251},"
47672310 126 "{VIA, VT8237A},"
07e4ca50
TI		 127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
1da177e4
LT		 129MODULE_DESCRIPTION("Intel HDA driver");
130
131#define SFX "hda-intel: "
132
cb53c626 133
1da177e4
LT		 134/*
135 * registers
136 */
137#define ICH6_REG_GCAP 0x00
138#define ICH6_REG_VMIN 0x02
139#define ICH6_REG_VMAJ 0x03
140#define ICH6_REG_OUTPAY 0x04
141#define ICH6_REG_INPAY 0x06
142#define ICH6_REG_GCTL 0x08
143#define ICH6_REG_WAKEEN 0x0c
144#define ICH6_REG_STATESTS 0x0e
145#define ICH6_REG_GSTS 0x10
146#define ICH6_REG_INTCTL 0x20
147#define ICH6_REG_INTSTS 0x24
148#define ICH6_REG_WALCLK 0x30
149#define ICH6_REG_SYNC 0x34
150#define ICH6_REG_CORBLBASE 0x40
151#define ICH6_REG_CORBUBASE 0x44
152#define ICH6_REG_CORBWP 0x48
153#define ICH6_REG_CORBRP 0x4A
154#define ICH6_REG_CORBCTL 0x4c
155#define ICH6_REG_CORBSTS 0x4d
156#define ICH6_REG_CORBSIZE 0x4e
157
158#define ICH6_REG_RIRBLBASE 0x50
159#define ICH6_REG_RIRBUBASE 0x54
160#define ICH6_REG_RIRBWP 0x58
161#define ICH6_REG_RINTCNT 0x5a
162#define ICH6_REG_RIRBCTL 0x5c
163#define ICH6_REG_RIRBSTS 0x5d
164#define ICH6_REG_RIRBSIZE 0x5e
165
166#define ICH6_REG_IC 0x60
167#define ICH6_REG_IR 0x64
168#define ICH6_REG_IRS 0x68
169#define ICH6_IRS_VALID (1<<1)
170#define ICH6_IRS_BUSY (1<<0)
171
172#define ICH6_REG_DPLBASE 0x70
173#define ICH6_REG_DPUBASE 0x74
174#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
175
176/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
178
179/* stream register offsets from stream base */
180#define ICH6_REG_SD_CTL 0x00
181#define ICH6_REG_SD_STS 0x03
182#define ICH6_REG_SD_LPIB 0x04
183#define ICH6_REG_SD_CBL 0x08
184#define ICH6_REG_SD_LVI 0x0c
185#define ICH6_REG_SD_FIFOW 0x0e
186#define ICH6_REG_SD_FIFOSIZE 0x10
187#define ICH6_REG_SD_FORMAT 0x12
188#define ICH6_REG_SD_BDLPL 0x18
189#define ICH6_REG_SD_BDLPU 0x1c
190
191/* PCI space */
192#define ICH6_PCIREG_TCSEL 0x44
193
194/*
195 * other constants
196 */
197
198/* max number of SDs */
07e4ca50 199/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 200#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 201#define ICH6_NUM_PLAYBACK 4
202
203/* ULI has 6 playback and 5 capture */
07e4ca50 204#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 205#define ULI_NUM_PLAYBACK 6
206
778b6e1b 207/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 208#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 209#define ATIHDMI_NUM_PLAYBACK 1
210
f269002e
KY		 211/* TERA has 4 playback and 3 capture */
212#define TERA_NUM_CAPTURE 3
213#define TERA_NUM_PLAYBACK 4
214
07e4ca50
TI		 215/* this number is statically defined for simplicity */
216#define MAX_AZX_DEV 16
217
1da177e4 218/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 219#define BDL_SIZE 4096
220#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221#define AZX_MAX_FRAG 32
1da177e4
LT		 222/* max buffer size - no h/w limit, you can increase as you like */
223#define AZX_MAX_BUF_SIZE (1024*1024*1024)
224/* max number of PCM devics per card */
7ba72ba1 225#define AZX_MAX_PCMS 8
1da177e4
LT		 226
227/* RIRB int mask: overrun[2], response[0] */
228#define RIRB_INT_RESPONSE 0x01
229#define RIRB_INT_OVERRUN 0x04
230#define RIRB_INT_MASK 0x05
231
2f5983f2
TI		 232/* STATESTS int mask: S3,SD2,SD1,SD0 */
233#define AZX_MAX_CODECS 4
234#define STATESTS_INT_MASK 0x0f
1da177e4
LT		 235
236/* SD_CTL bits */
237#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 239#define SD_CTL_STRIPE (3 << 16) /* stripe control */
240#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 242#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243#define SD_CTL_STREAM_TAG_SHIFT 20
244
245/* SD_CTL and SD_STS */
246#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 249#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
250 SD_INT_COMPLETE)
1da177e4
LT		 251
252/* SD_STS */
253#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
254
255/* INTCTL and INTSTS */
d01ce99f
TI		 256#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 259
41e2fce4
M		 260/* GCTL unsolicited response enable bit */
261#define ICH6_GCTL_UREN (1<<8)
262
1da177e4
LT		 263/* GCTL reset bit */
264#define ICH6_GCTL_RESET (1<<0)
265
266/* CORB/RIRB control, read/write pointer */
267#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270/* below are so far hardcoded - should read registers in future */
271#define ICH6_MAX_CORB_ENTRIES 256
272#define ICH6_MAX_RIRB_ENTRIES 256
273
c74db86b
TI		 274/* position fix mode */
275enum {
0be3b5d3 276 POS_FIX_AUTO,
d2e1c973 277 POS_FIX_LPIB,
0be3b5d3 278 POS_FIX_POSBUF,
c74db86b 279};
1da177e4 280
f5d40b30 281/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 282#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
284
da3fca21
V		 285/* Defines for Nvidia HDA support */
286#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 288#define NVIDIA_HDA_ISTRM_COH 0x4d
289#define NVIDIA_HDA_OSTRM_COH 0x4c
290#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 291
90a5ad52
TI		 292/* Defines for Intel SCH HDA snoop control */
293#define INTEL_SCH_HDA_DEVC 0x78
294#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
295
0e153474
JC		 296/* Define IN stream 0 FIFO size offset in VIA controller */
297#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298/* Define VIA HD Audio Device ID*/
299#define VIA_HDAC_DEVICE_ID 0x3288
300
c4da29ca
YL		 301/* HD Audio class code */
302#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 303
1da177e4
LT		 304/*
305 */
306
a98f90fd 307struct azx_dev {
4ce107b9 308 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 309 u32 *posbuf; /* position buffer pointer */
1da177e4 310
d01ce99f 311 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 312 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
1da177e4 315
d01ce99f 316 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 317
d01ce99f 318 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 319
320 /* pcm support */
d01ce99f
TI		 321 struct snd_pcm_substream *substream; /* assigned substream,
322 * set in PCM open
323 */
324 unsigned int format_val; /* format value to be set in the
325 * controller and the codec
326 */
1da177e4
LT		 327 unsigned char stream_tag; /* assigned stream */
328 unsigned char index; /* stream index */
329
927fc866
PM		 330 unsigned int opened :1;
331 unsigned int running :1;
675f25d4
TI		 332 unsigned int irq_pending :1;
333 unsigned int irq_ignore :1;
0e153474
JC		 334 /*
335 * For VIA:
336 * A flag to ensure DMA position is 0
337 * when link position is not greater than FIFO size
338 */
339 unsigned int insufficient :1;
1da177e4
LT		 340};
341
342/* CORB/RIRB */
a98f90fd 343struct azx_rb {
1da177e4
LT		 344 u32 *buf; /* CORB/RIRB buffer
345 * Each CORB entry is 4byte, RIRB is 8byte
346 */
347 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
348 /* for RIRB */
349 unsigned short rp, wp; /* read/write pointers */
350 int cmds; /* number of pending requests */
351 u32 res; /* last read value */
352};
353
a98f90fd
TI		 354struct azx {
355 struct snd_card *card;
1da177e4 356 struct pci_dev *pci;
555e219f 357 int dev_index;
1da177e4 358
07e4ca50
TI		 359 /* chip type specific */
360 int driver_type;
361 int playback_streams;
362 int playback_index_offset;
363 int capture_streams;
364 int capture_index_offset;
365 int num_streams;
366
1da177e4
LT		 367 /* pci resources */
368 unsigned long addr;
369 void __iomem *remap_addr;
370 int irq;
371
372 /* locks */
373 spinlock_t reg_lock;
62932df8 374 struct mutex open_mutex;
1da177e4 375
07e4ca50 376 /* streams (x num_streams) */
a98f90fd 377 struct azx_dev *azx_dev;
1da177e4
LT		 378
379 /* PCM */
a98f90fd 380 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 381
382 /* HD codec */
383 unsigned short codec_mask;
f1eaaeec 384 int codec_probe_mask; /* copied from probe_mask option */
1da177e4
LT		 385 struct hda_bus *bus;
386
387 /* CORB/RIRB */
a98f90fd
TI		 388 struct azx_rb corb;
389 struct azx_rb rirb;
1da177e4 390
4ce107b9 391 /* CORB/RIRB and position buffers */
1da177e4
LT		 392 struct snd_dma_buffer rb;
393 struct snd_dma_buffer posbuf;
c74db86b
TI		 394
395 /* flags */
396 int position_fix;
cb53c626 397 unsigned int running :1;
927fc866
PM		 398 unsigned int initialized :1;
399 unsigned int single_cmd :1;
400 unsigned int polling_mode :1;
68e7fffc 401 unsigned int msi :1;
a6a950a8 402 unsigned int irq_pending_warned :1;
0e153474 403 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 404 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 405
406 /* for debugging */
407 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 408
409 /* for pending irqs */
410 struct work_struct irq_pending_work;
0cbf0098
TI		 411
412 /* reboot notifier (for mysterious hangup problem at power-down) */
413 struct notifier_block reboot_notifier;
1da177e4
LT		 414};
415
07e4ca50
TI		 416/* driver types */
417enum {
418 AZX_DRIVER_ICH,
4979bca9 419 AZX_DRIVER_SCH,
07e4ca50 420 AZX_DRIVER_ATI,
778b6e1b 421 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 422 AZX_DRIVER_VIA,
423 AZX_DRIVER_SIS,
424 AZX_DRIVER_ULI,
da3fca21 425 AZX_DRIVER_NVIDIA,
f269002e 426 AZX_DRIVER_TERA,
c4da29ca 427 AZX_DRIVER_GENERIC,
2f5983f2 428 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 429};
430
431static char *driver_short_names[] __devinitdata = {
432 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 433 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 434 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 435 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 436 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
437 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 438 [AZX_DRIVER_ULI] = "HDA ULI M5461",
439 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 440 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 441 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 442};
443
1da177e4
LT		 444/*
445 * macros for easy use
446 */
447#define azx_writel(chip,reg,value) \
448 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
449#define azx_readl(chip,reg) \
450 readl((chip)->remap_addr + ICH6_REG_##reg)
451#define azx_writew(chip,reg,value) \
452 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
453#define azx_readw(chip,reg) \
454 readw((chip)->remap_addr + ICH6_REG_##reg)
455#define azx_writeb(chip,reg,value) \
456 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
457#define azx_readb(chip,reg) \
458 readb((chip)->remap_addr + ICH6_REG_##reg)
459
460#define azx_sd_writel(dev,reg,value) \
461 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
462#define azx_sd_readl(dev,reg) \
463 readl((dev)->sd_addr + ICH6_REG_##reg)
464#define azx_sd_writew(dev,reg,value) \
465 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
466#define azx_sd_readw(dev,reg) \
467 readw((dev)->sd_addr + ICH6_REG_##reg)
468#define azx_sd_writeb(dev,reg,value) \
469 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
470#define azx_sd_readb(dev,reg) \
471 readb((dev)->sd_addr + ICH6_REG_##reg)
472
473/* for pcm support */
a98f90fd 474#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 475
68e7fffc 476static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 477
478/*
479 * Interface for HD codec
480 */
481
1da177e4
LT		 482/*
483 * CORB / RIRB interface
484 */
a98f90fd 485static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 486{
487 int err;
488
489 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 490 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
491 snd_dma_pci_data(chip->pci),
1da177e4
LT		 492 PAGE_SIZE, &chip->rb);
493 if (err < 0) {
494 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
495 return err;
496 }
497 return 0;
498}
499
a98f90fd 500static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 501{
502 /* CORB set up */
503 chip->corb.addr = chip->rb.addr;
504 chip->corb.buf = (u32 *)chip->rb.area;
505 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 506 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 507
07e4ca50
TI		 508 /* set the corb size to 256 entries (ULI requires explicitly) */
509 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 510 /* set the corb write pointer to 0 */
511 azx_writew(chip, CORBWP, 0);
512 /* reset the corb hw read pointer */
513 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
514 /* enable corb dma */
515 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
516
517 /* RIRB set up */
518 chip->rirb.addr = chip->rb.addr + 2048;
519 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
520 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 521 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 522
07e4ca50
TI		 523 /* set the rirb size to 256 entries (ULI requires explicitly) */
524 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 525 /* reset the rirb hw write pointer */
526 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
527 /* set N=1, get RIRB response interrupt for new entry */
528 azx_writew(chip, RINTCNT, 1);
529 /* enable rirb dma and response irq */
1da177e4 530 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 531 chip->rirb.rp = chip->rirb.cmds = 0;
532}
533
a98f90fd 534static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 535{
536 /* disable ringbuffer DMAs */
537 azx_writeb(chip, RIRBCTL, 0);
538 azx_writeb(chip, CORBCTL, 0);
539}
540
541/* send a command */
33fa35ed 542static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 543{
33fa35ed 544 struct azx *chip = bus->private_data;
1da177e4 545 unsigned int wp;
1da177e4
LT		 546
547 /* add command to corb */
548 wp = azx_readb(chip, CORBWP);
549 wp++;
550 wp %= ICH6_MAX_CORB_ENTRIES;
551
552 spin_lock_irq(&chip->reg_lock);
553 chip->rirb.cmds++;
554 chip->corb.buf[wp] = cpu_to_le32(val);
555 azx_writel(chip, CORBWP, wp);
556 spin_unlock_irq(&chip->reg_lock);
557
558 return 0;
559}
560
561#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
562
563/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 564static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 565{
566 unsigned int rp, wp;
567 u32 res, res_ex;
568
569 wp = azx_readb(chip, RIRBWP);
570 if (wp == chip->rirb.wp)
571 return;
572 chip->rirb.wp = wp;
573
574 while (chip->rirb.rp != wp) {
575 chip->rirb.rp++;
576 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
577
578 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
579 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
580 res = le32_to_cpu(chip->rirb.buf[rp]);
581 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
582 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
583 else if (chip->rirb.cmds) {
1da177e4 584 chip->rirb.res = res;
2add9b92
TI		 585 smp_wmb();
586 chip->rirb.cmds--;
1da177e4
LT		 587 }
588 }
589}
590
591/* receive a response */
33fa35ed 592static unsigned int azx_rirb_get_response(struct hda_bus *bus)
1da177e4 593{
33fa35ed 594 struct azx *chip = bus->private_data;
5c79b1f8 595 unsigned long timeout;
1da177e4 596
5c79b1f8
TI		 597 again:
598 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 599 for (;;) {
e96224ae
TI		 600 if (chip->polling_mode) {
601 spin_lock_irq(&chip->reg_lock);
602 azx_update_rirb(chip);
603 spin_unlock_irq(&chip->reg_lock);
604 }
2add9b92
TI		 605 if (!chip->rirb.cmds) {
606 smp_rmb();
5c79b1f8 607 return chip->rirb.res; /* the last value */
2add9b92 608 }
28a0d9df
TI		 609 if (time_after(jiffies, timeout))
610 break;
33fa35ed 611 if (bus->needs_damn_long_delay)
52987656
TI		 612 msleep(2); /* temporary workaround */
613 else {
614 udelay(10);
615 cond_resched();
616 }
28a0d9df 617 }
5c79b1f8 618
68e7fffc
TI		 619 if (chip->msi) {
620 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
43bbb6cc 621 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 622 free_irq(chip->irq, chip);
623 chip->irq = -1;
624 pci_disable_msi(chip->pci);
625 chip->msi = 0;
626 if (azx_acquire_irq(chip, 1) < 0)
627 return -1;
628 goto again;
629 }
630
5c79b1f8
TI		 631 if (!chip->polling_mode) {
632 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 633 "switching to polling mode: last cmd=0x%08x\n",
634 chip->last_cmd);
5c79b1f8
TI		 635 chip->polling_mode = 1;
636 goto again;
1da177e4 637 }
5c79b1f8 638
6ce4a3bc
TI		 639 if (chip->probing) {
640 /* If this critical timeout happens during the codec probing
641 * phase, this is likely an access to a non-existing codec
642 * slot. Better to return an error and reset the system.
643 */
644 return -1;
645 }
646
5c79b1f8 647 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 648 "switching to single_cmd mode: last cmd=0x%08x\n",
649 chip->last_cmd);
5c79b1f8
TI		 650 chip->rirb.rp = azx_readb(chip, RIRBWP);
651 chip->rirb.cmds = 0;
652 /* switch to single_cmd mode */
653 chip->single_cmd = 1;
654 azx_free_cmd_io(chip);
655 return -1;
1da177e4
LT		 656}
657
1da177e4
LT		 658/*
659 * Use the single immediate command instead of CORB/RIRB for simplicity
660 *
661 * Note: according to Intel, this is not preferred use. The command was
662 * intended for the BIOS only, and may get confused with unsolicited
663 * responses. So, we shouldn't use it for normal operation from the
664 * driver.
665 * I left the codes, however, for debugging/testing purposes.
666 */
667
1da177e4 668/* send a command */
33fa35ed 669static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 670{
33fa35ed 671 struct azx *chip = bus->private_data;
1da177e4
LT		 672 int timeout = 50;
673
1da177e4
LT		 674 while (timeout--) {
675 /* check ICB busy bit */
d01ce99f 676 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 677 /* Clear IRV valid bit */
d01ce99f
TI		 678 azx_writew(chip, IRS, azx_readw(chip, IRS) |
679 ICH6_IRS_VALID);
1da177e4 680 azx_writel(chip, IC, val);
d01ce99f
TI		 681 azx_writew(chip, IRS, azx_readw(chip, IRS) |
682 ICH6_IRS_BUSY);
1da177e4
LT		 683 return 0;
684 }
685 udelay(1);
686 }
1cfd52bc
MB		 687 if (printk_ratelimit())
688 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
689 azx_readw(chip, IRS), val);
1da177e4
LT		 690 return -EIO;
691}
692
693/* receive a response */
33fa35ed 694static unsigned int azx_single_get_response(struct hda_bus *bus)
1da177e4 695{
33fa35ed 696 struct azx *chip = bus->private_data;
1da177e4
LT		 697 int timeout = 50;
698
699 while (timeout--) {
700 /* check IRV busy bit */
701 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
702 return azx_readl(chip, IR);
703 udelay(1);
704 }
1cfd52bc
MB		 705 if (printk_ratelimit())
706 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
707 azx_readw(chip, IRS));
1da177e4
LT		 708 return (unsigned int)-1;
709}
710
111d3af5
TI		 711/*
712 * The below are the main callbacks from hda_codec.
713 *
714 * They are just the skeleton to call sub-callbacks according to the
715 * current setting of chip->single_cmd.
716 */
717
718/* send a command */
33fa35ed 719static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 720{
33fa35ed 721 struct azx *chip = bus->private_data;
43bbb6cc 722
33fa35ed 723 chip->last_cmd = val;
111d3af5 724 if (chip->single_cmd)
33fa35ed 725 return azx_single_send_cmd(bus, val);
111d3af5 726 else
33fa35ed 727 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 728}
729
730/* get a response */
33fa35ed 731static unsigned int azx_get_response(struct hda_bus *bus)
111d3af5 732{
33fa35ed 733 struct azx *chip = bus->private_data;
111d3af5 734 if (chip->single_cmd)
33fa35ed 735 return azx_single_get_response(bus);
111d3af5 736 else
33fa35ed 737 return azx_rirb_get_response(bus);
111d3af5
TI		 738}
739
cb53c626 740#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 741static void azx_power_notify(struct hda_bus *bus);
cb53c626 742#endif
111d3af5 743
1da177e4 744/* reset codec link */
a98f90fd 745static int azx_reset(struct azx *chip)
1da177e4
LT		 746{
747 int count;
748
e8a7f136
DT		 749 /* clear STATESTS */
750 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
751
1da177e4
LT		 752 /* reset controller */
753 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
754
755 count = 50;
756 while (azx_readb(chip, GCTL) && --count)
757 msleep(1);
758
759 /* delay for >= 100us for codec PLL to settle per spec
760 * Rev 0.9 section 5.5.1
761 */
762 msleep(1);
763
764 /* Bring controller out of reset */
765 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
766
767 count = 50;
927fc866 768 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 769 msleep(1);
770
927fc866 771 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 772 msleep(1);
773
774 /* check to see if controller is ready */
927fc866 775 if (!azx_readb(chip, GCTL)) {
1da177e4
LT		 776 snd_printd("azx_reset: controller not ready!\n");
777 return -EBUSY;
778 }
779
41e2fce4
M		 780 /* Accept unsolicited responses */
781 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
782
1da177e4 783 /* detect codecs */
927fc866 784 if (!chip->codec_mask) {
1da177e4
LT		 785 chip->codec_mask = azx_readw(chip, STATESTS);
786 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
787 }
788
789 return 0;
790}
791
792
793/*
794 * Lowlevel interface
795 */
796
797/* enable interrupts */
a98f90fd 798static void azx_int_enable(struct azx *chip)
1da177e4
LT		 799{
800 /* enable controller CIE and GIE */
801 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
802 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
803}
804
805/* disable interrupts */
a98f90fd 806static void azx_int_disable(struct azx *chip)
1da177e4
LT		 807{
808 int i;
809
810 /* disable interrupts in stream descriptor */
07e4ca50 811 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 812 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 813 azx_sd_writeb(azx_dev, SD_CTL,
814 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
815 }
816
817 /* disable SIE for all streams */
818 azx_writeb(chip, INTCTL, 0);
819
820 /* disable controller CIE and GIE */
821 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
822 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
823}
824
825/* clear interrupts */
a98f90fd 826static void azx_int_clear(struct azx *chip)
1da177e4
LT		 827{
828 int i;
829
830 /* clear stream status */
07e4ca50 831 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 832 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 833 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
834 }
835
836 /* clear STATESTS */
837 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
838
839 /* clear rirb status */
840 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
841
842 /* clear int status */
843 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
844}
845
846/* start a stream */
a98f90fd 847static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 848{
0e153474
JC		 849 /*
850 * Before stream start, initialize parameter
851 */
852 azx_dev->insufficient = 1;
853
1da177e4
LT		 854 /* enable SIE */
855 azx_writeb(chip, INTCTL,
856 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
857 /* set DMA start and interrupt mask */
858 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
859 SD_CTL_DMA_START | SD_INT_MASK);
860}
861
862/* stop a stream */
a98f90fd 863static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 864{
865 /* stop DMA */
866 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
867 ~(SD_CTL_DMA_START | SD_INT_MASK));
868 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
869 /* disable SIE */
870 azx_writeb(chip, INTCTL,
871 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
872}
873
874
875/*
cb53c626 876 * reset and start the controller registers
1da177e4 877 */
a98f90fd 878static void azx_init_chip(struct azx *chip)
1da177e4 879{
cb53c626
TI		 880 if (chip->initialized)
881 return;
1da177e4
LT		 882
883 /* reset controller */
884 azx_reset(chip);
885
886 /* initialize interrupts */
887 azx_int_clear(chip);
888 azx_int_enable(chip);
889
890 /* initialize the codec command I/O */
927fc866 891 if (!chip->single_cmd)
27346166 892 azx_init_cmd_io(chip);
1da177e4 893
0be3b5d3
TI		 894 /* program the position buffer */
895 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 896 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 897
cb53c626
TI		 898 chip->initialized = 1;
899}
900
901/*
902 * initialize the PCI registers
903 */
904/* update bits in a PCI register byte */
905static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
906 unsigned char mask, unsigned char val)
907{
908 unsigned char data;
909
910 pci_read_config_byte(pci, reg, &data);
911 data &= ~mask;
912 data |= (val & mask);
913 pci_write_config_byte(pci, reg, data);
914}
915
916static void azx_init_pci(struct azx *chip)
917{
90a5ad52
TI		 918 unsigned short snoop;
919
cb53c626
TI		 920 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
921 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
922 * Ensuring these bits are 0 clears playback static on some HD Audio
923 * codecs
924 */
925 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
926
da3fca21
V		 927 switch (chip->driver_type) {
928 case AZX_DRIVER_ATI:
929 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 930 update_pci_byte(chip->pci,
931 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
932 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 933 break;
934 case AZX_DRIVER_NVIDIA:
935 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 936 update_pci_byte(chip->pci,
937 NVIDIA_HDA_TRANSREG_ADDR,
938 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 939 update_pci_byte(chip->pci,
940 NVIDIA_HDA_ISTRM_COH,
941 0x01, NVIDIA_HDA_ENABLE_COHBIT);
942 update_pci_byte(chip->pci,
943 NVIDIA_HDA_OSTRM_COH,
944 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 945 break;
90a5ad52
TI		 946 case AZX_DRIVER_SCH:
947 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
948 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
949 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
950 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
951 pci_read_config_word(chip->pci,
952 INTEL_SCH_HDA_DEVC, &snoop);
953 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
954 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
955 ? "Failed" : "OK");
956 }
957 break;
958
da3fca21 959 }
1da177e4
LT		 960}
961
962
9ad593f6
TI		 963static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
964
1da177e4
LT		 965/*
966 * interrupt handler
967 */
7d12e780 968static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 969{
a98f90fd
TI		 970 struct azx *chip = dev_id;
971 struct azx_dev *azx_dev;
1da177e4
LT		 972 u32 status;
973 int i;
974
975 spin_lock(&chip->reg_lock);
976
977 status = azx_readl(chip, INTSTS);
978 if (status == 0) {
979 spin_unlock(&chip->reg_lock);
980 return IRQ_NONE;
981 }
982
07e4ca50 983 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 984 azx_dev = &chip->azx_dev[i];
985 if (status & azx_dev->sd_int_sta_mask) {
986 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 987 if (!azx_dev->substream || !azx_dev->running)
988 continue;
675f25d4
TI		 989 /* ignore the first dummy IRQ (due to pos_adj) */
990 if (azx_dev->irq_ignore) {
991 azx_dev->irq_ignore = 0;
992 continue;
993 }
9ad593f6
TI		 994 /* check whether this IRQ is really acceptable */
995 if (azx_position_ok(chip, azx_dev)) {
996 azx_dev->irq_pending = 0;
1da177e4
LT		 997 spin_unlock(&chip->reg_lock);
998 snd_pcm_period_elapsed(azx_dev->substream);
999 spin_lock(&chip->reg_lock);
6acaed38 1000 } else if (chip->bus && chip->bus->workq) {
9ad593f6
TI		 1001 /* bogus IRQ, process it later */
1002 azx_dev->irq_pending = 1;
6acaed38
TI		 1003 queue_work(chip->bus->workq,
1004 &chip->irq_pending_work);
1da177e4
LT		 1005 }
1006 }
1007 }
1008
1009 /* clear rirb int */
1010 status = azx_readb(chip, RIRBSTS);
1011 if (status & RIRB_INT_MASK) {
d01ce99f 1012 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 1013 azx_update_rirb(chip);
1014 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1015 }
1016
1017#if 0
1018 /* clear state status int */
1019 if (azx_readb(chip, STATESTS) & 0x04)
1020 azx_writeb(chip, STATESTS, 0x04);
1021#endif
1022 spin_unlock(&chip->reg_lock);
1023
1024 return IRQ_HANDLED;
1025}
1026
1027
675f25d4
TI		 1028/*
1029 * set up a BDL entry
1030 */
1031static int setup_bdle(struct snd_pcm_substream *substream,
1032 struct azx_dev *azx_dev, u32 **bdlp,
1033 int ofs, int size, int with_ioc)
1034{
675f25d4
TI		 1035 u32 *bdl = *bdlp;
1036
1037 while (size > 0) {
1038 dma_addr_t addr;
1039 int chunk;
1040
1041 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1042 return -EINVAL;
1043
77a23f26 1044 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1045 /* program the address field of the BDL entry */
1046 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1047 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1048 /* program the size field of the BDL entry */
fc4abee8 1049 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1050 bdl[2] = cpu_to_le32(chunk);
1051 /* program the IOC to enable interrupt
1052 * only when the whole fragment is processed
1053 */
1054 size -= chunk;
1055 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1056 bdl += 4;
1057 azx_dev->frags++;
1058 ofs += chunk;
1059 }
1060 *bdlp = bdl;
1061 return ofs;
1062}
1063
1da177e4
LT		 1064/*
1065 * set up BDL entries
1066 */
555e219f
TI		 1067static int azx_setup_periods(struct azx *chip,
1068 struct snd_pcm_substream *substream,
4ce107b9 1069 struct azx_dev *azx_dev)
1da177e4 1070{
4ce107b9
TI		 1071 u32 *bdl;
1072 int i, ofs, periods, period_bytes;
555e219f 1073 int pos_adj;
1da177e4
LT		 1074
1075 /* reset BDL address */
1076 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1077 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1078
97b71c94 1079 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1080 periods = azx_dev->bufsize / period_bytes;
1081
1da177e4 1082 /* program the initial BDL entries */
4ce107b9
TI		 1083 bdl = (u32 *)azx_dev->bdl.area;
1084 ofs = 0;
1085 azx_dev->frags = 0;
675f25d4 1086 azx_dev->irq_ignore = 0;
555e219f
TI		 1087 pos_adj = bdl_pos_adj[chip->dev_index];
1088 if (pos_adj > 0) {
675f25d4 1089 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1090 int pos_align = pos_adj;
555e219f 1091 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1092 if (!pos_adj)
e785d3d8
TI		 1093 pos_adj = pos_align;
1094 else
1095 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1096 pos_align;
675f25d4
TI		 1097 pos_adj = frames_to_bytes(runtime, pos_adj);
1098 if (pos_adj >= period_bytes) {
1099 snd_printk(KERN_WARNING "Too big adjustment %d\n",
555e219f 1100 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1101 pos_adj = 0;
1102 } else {
1103 ofs = setup_bdle(substream, azx_dev,
1104 &bdl, ofs, pos_adj, 1);
1105 if (ofs < 0)
1106 goto error;
1107 azx_dev->irq_ignore = 1;
4ce107b9 1108 }
555e219f
TI		 1109 } else
1110 pos_adj = 0;
675f25d4
TI		 1111 for (i = 0; i < periods; i++) {
1112 if (i == periods - 1 && pos_adj)
1113 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1114 period_bytes - pos_adj, 0);
1115 else
1116 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1117 period_bytes, 1);
1118 if (ofs < 0)
1119 goto error;
1da177e4 1120 }
4ce107b9 1121 return 0;
675f25d4
TI		 1122
1123 error:
1124 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1125 azx_dev->bufsize, period_bytes);
675f25d4 1126 return -EINVAL;
1da177e4
LT		 1127}
1128
1129/*
1130 * set up the SD for streaming
1131 */
a98f90fd 1132static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1133{
1134 unsigned char val;
1135 int timeout;
1136
1137 /* make sure the run bit is zero for SD */
d01ce99f
TI		 1138 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1139 ~SD_CTL_DMA_START);
1da177e4 1140 /* reset stream */
d01ce99f
TI		 1141 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1142 SD_CTL_STREAM_RESET);
1da177e4
LT		 1143 udelay(3);
1144 timeout = 300;
1145 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1146 --timeout)
1147 ;
1148 val &= ~SD_CTL_STREAM_RESET;
1149 azx_sd_writeb(azx_dev, SD_CTL, val);
1150 udelay(3);
1151
1152 timeout = 300;
1153 /* waiting for hardware to report that the stream is out of reset */
1154 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1155 --timeout)
1156 ;
1157
1158 /* program the stream_tag */
1159 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1160 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1161 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1162
1163 /* program the length of samples in cyclic buffer */
1164 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1165
1166 /* program the stream format */
1167 /* this value needs to be the same as the one programmed */
1168 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1169
1170 /* program the stream LVI (last valid index) of the BDL */
1171 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1172
1173 /* program the BDL address */
1174 /* lower BDL address */
4ce107b9 1175 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1176 /* upper BDL address */
766979e0 1177 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1178
0be3b5d3 1179 /* enable the position buffer */
ee9d6b9a 1180 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1181 chip->position_fix == POS_FIX_AUTO ||
1182 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1183 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1184 azx_writel(chip, DPLBASE,
1185 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1186 }
c74db86b 1187
1da177e4 1188 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1189 azx_sd_writel(azx_dev, SD_CTL,
1190 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1191
1192 return 0;
1193}
1194
6ce4a3bc
TI		 1195/*
1196 * Probe the given codec address
1197 */
1198static int probe_codec(struct azx *chip, int addr)
1199{
1200 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1201 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1202 unsigned int res;
1203
1204 chip->probing = 1;
1205 azx_send_cmd(chip->bus, cmd);
1206 res = azx_get_response(chip->bus);
1207 chip->probing = 0;
1208 if (res == -1)
1209 return -EIO;
1210 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1211 return 0;
1212}
1213
33fa35ed
TI		 1214static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1215 struct hda_pcm *cpcm);
6ce4a3bc 1216static void azx_stop_chip(struct azx *chip);
1da177e4
LT		 1217
1218/*
1219 * Codec initialization
1220 */
1221
2f5983f2
TI		 1222/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1223static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1224 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1225};
1226
5aba4f8e 1227static int __devinit azx_codec_create(struct azx *chip, const char *model,
d4d9cd03 1228 int no_init)
1da177e4
LT		 1229{
1230 struct hda_bus_template bus_temp;
34c25350
TI		 1231 int c, codecs, err;
1232 int max_slots;
1da177e4
LT		 1233
1234 memset(&bus_temp, 0, sizeof(bus_temp));
1235 bus_temp.private_data = chip;
1236 bus_temp.modelname = model;
1237 bus_temp.pci = chip->pci;
111d3af5
TI		 1238 bus_temp.ops.command = azx_send_cmd;
1239 bus_temp.ops.get_response = azx_get_response;
176d5335 1240 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
cb53c626 1241#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1242 bus_temp.power_save = &power_save;
cb53c626
TI		 1243 bus_temp.ops.pm_notify = azx_power_notify;
1244#endif
1da177e4 1245
d01ce99f
TI		 1246 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1247 if (err < 0)
1da177e4
LT		 1248 return err;
1249
dc9c8e21
WN		 1250 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1251 chip->bus->needs_damn_long_delay = 1;
1252
34c25350 1253 codecs = 0;
2f5983f2
TI		 1254 max_slots = azx_max_codecs[chip->driver_type];
1255 if (!max_slots)
1256 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1257
1258 /* First try to probe all given codec slots */
1259 for (c = 0; c < max_slots; c++) {
f1eaaeec 1260 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1261 if (probe_codec(chip, c) < 0) {
1262 /* Some BIOSen give you wrong codec addresses
1263 * that don't exist
1264 */
1265 snd_printk(KERN_WARNING
1266 "hda_intel: Codec #%d probe error; "
1267 "disabling it...\n", c);
1268 chip->codec_mask &= ~(1 << c);
1269 /* More badly, accessing to a non-existing
1270 * codec often screws up the controller chip,
1271 * and distrubs the further communications.
1272 * Thus if an error occurs during probing,
1273 * better to reset the controller chip to
1274 * get back to the sanity state.
1275 */
1276 azx_stop_chip(chip);
1277 azx_init_chip(chip);
1278 }
1279 }
1280 }
1281
1282 /* Then create codec instances */
34c25350 1283 for (c = 0; c < max_slots; c++) {
f1eaaeec 1284 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1285 struct hda_codec *codec;
d4d9cd03 1286 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1da177e4
LT		 1287 if (err < 0)
1288 continue;
1289 codecs++;
19a982b6
TI		 1290 }
1291 }
1292 if (!codecs) {
1da177e4
LT		 1293 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1294 return -ENXIO;
1295 }
1296
1297 return 0;
1298}
1299
1300
1301/*
1302 * PCM support
1303 */
1304
1305/* assign a stream for the PCM */
a98f90fd 1306static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1307{
07e4ca50
TI		 1308 int dev, i, nums;
1309 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1310 dev = chip->playback_index_offset;
1311 nums = chip->playback_streams;
1312 } else {
1313 dev = chip->capture_index_offset;
1314 nums = chip->capture_streams;
1315 }
1316 for (i = 0; i < nums; i++, dev++)
d01ce99f 1317 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1318 chip->azx_dev[dev].opened = 1;
1319 return &chip->azx_dev[dev];
1320 }
1321 return NULL;
1322}
1323
1324/* release the assigned stream */
a98f90fd 1325static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1326{
1327 azx_dev->opened = 0;
1328}
1329
a98f90fd 1330static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1331 .info = (SNDRV_PCM_INFO_MMAP |
1332 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1333 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1334 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1335 /* No full-resume yet implemented */
1336 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1337 SNDRV_PCM_INFO_PAUSE |
1338 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1339 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1340 .rates = SNDRV_PCM_RATE_48000,
1341 .rate_min = 48000,
1342 .rate_max = 48000,
1343 .channels_min = 2,
1344 .channels_max = 2,
1345 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1346 .period_bytes_min = 128,
1347 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1348 .periods_min = 2,
1349 .periods_max = AZX_MAX_FRAG,
1350 .fifo_size = 0,
1351};
1352
1353struct azx_pcm {
a98f90fd 1354 struct azx *chip;
1da177e4
LT		 1355 struct hda_codec *codec;
1356 struct hda_pcm_stream *hinfo[2];
1357};
1358
a98f90fd 1359static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1360{
1361 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1362 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1363 struct azx *chip = apcm->chip;
1364 struct azx_dev *azx_dev;
1365 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1366 unsigned long flags;
1367 int err;
1368
62932df8 1369 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1370 azx_dev = azx_assign_device(chip, substream->stream);
1371 if (azx_dev == NULL) {
62932df8 1372 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1373 return -EBUSY;
1374 }
1375 runtime->hw = azx_pcm_hw;
1376 runtime->hw.channels_min = hinfo->channels_min;
1377 runtime->hw.channels_max = hinfo->channels_max;
1378 runtime->hw.formats = hinfo->formats;
1379 runtime->hw.rates = hinfo->rates;
1380 snd_pcm_limit_hw_rates(runtime);
1381 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1382 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1383 128);
1384 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1385 128);
cb53c626 1386 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1387 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1388 if (err < 0) {
1da177e4 1389 azx_release_device(azx_dev);
cb53c626 1390 snd_hda_power_down(apcm->codec);
62932df8 1391 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1392 return err;
1393 }
1394 spin_lock_irqsave(&chip->reg_lock, flags);
1395 azx_dev->substream = substream;
1396 azx_dev->running = 0;
1397 spin_unlock_irqrestore(&chip->reg_lock, flags);
1398
1399 runtime->private_data = azx_dev;
850f0e52 1400 snd_pcm_set_sync(substream);
62932df8 1401 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1402 return 0;
1403}
1404
a98f90fd 1405static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1406{
1407 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1408 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1409 struct azx *chip = apcm->chip;
1410 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1411 unsigned long flags;
1412
62932df8 1413 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1414 spin_lock_irqsave(&chip->reg_lock, flags);
1415 azx_dev->substream = NULL;
1416 azx_dev->running = 0;
1417 spin_unlock_irqrestore(&chip->reg_lock, flags);
1418 azx_release_device(azx_dev);
1419 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1420 snd_hda_power_down(apcm->codec);
62932df8 1421 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1422 return 0;
1423}
1424
d01ce99f
TI		 1425static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1426 struct snd_pcm_hw_params *hw_params)
1da177e4 1427{
97b71c94
TI		 1428 struct azx_dev *azx_dev = get_azx_dev(substream);
1429
1430 azx_dev->bufsize = 0;
1431 azx_dev->period_bytes = 0;
1432 azx_dev->format_val = 0;
d01ce99f
TI		 1433 return snd_pcm_lib_malloc_pages(substream,
1434 params_buffer_bytes(hw_params));
1da177e4
LT		 1435}
1436
a98f90fd 1437static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1438{
1439 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1440 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1441 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1442
1443 /* reset BDL address */
1444 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1445 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1446 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1447 azx_dev->bufsize = 0;
1448 azx_dev->period_bytes = 0;
1449 azx_dev->format_val = 0;
1da177e4
LT		 1450
1451 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1452
1453 return snd_pcm_lib_free_pages(substream);
1454}
1455
a98f90fd 1456static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1457{
1458 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1459 struct azx *chip = apcm->chip;
1460 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1461 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1462 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1463 unsigned int bufsize, period_bytes, format_val;
1464 int err;
1da177e4 1465
97b71c94
TI		 1466 format_val = snd_hda_calc_stream_format(runtime->rate,
1467 runtime->channels,
1468 runtime->format,
1469 hinfo->maxbps);
1470 if (!format_val) {
d01ce99f
TI		 1471 snd_printk(KERN_ERR SFX
1472 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1473 runtime->rate, runtime->channels, runtime->format);
1474 return -EINVAL;
1475 }
1476
97b71c94
TI		 1477 bufsize = snd_pcm_lib_buffer_bytes(substream);
1478 period_bytes = snd_pcm_lib_period_bytes(substream);
1479
21c7b081 1480 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1481 bufsize, format_val);
1482
1483 if (bufsize != azx_dev->bufsize ||
1484 period_bytes != azx_dev->period_bytes ||
1485 format_val != azx_dev->format_val) {
1486 azx_dev->bufsize = bufsize;
1487 azx_dev->period_bytes = period_bytes;
1488 azx_dev->format_val = format_val;
1489 err = azx_setup_periods(chip, substream, azx_dev);
1490 if (err < 0)
1491 return err;
1492 }
1493
1da177e4
LT		 1494 azx_setup_controller(chip, azx_dev);
1495 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1496 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1497 else
1498 azx_dev->fifo_size = 0;
1499
1500 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1501 azx_dev->format_val, substream);
1502}
1503
a98f90fd 1504static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1505{
1506 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1507 struct azx *chip = apcm->chip;
850f0e52
TI		 1508 struct azx_dev *azx_dev;
1509 struct snd_pcm_substream *s;
1510 int start, nsync = 0, sbits = 0;
1511 int nwait, timeout;
1da177e4 1512
1da177e4
LT		 1513 switch (cmd) {
1514 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1515 case SNDRV_PCM_TRIGGER_RESUME:
1516 case SNDRV_PCM_TRIGGER_START:
850f0e52 1517 start = 1;
1da177e4
LT		 1518 break;
1519 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1520 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1521 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1522 start = 0;
1da177e4
LT		 1523 break;
1524 default:
850f0e52
TI		 1525 return -EINVAL;
1526 }
1527
1528 snd_pcm_group_for_each_entry(s, substream) {
1529 if (s->pcm->card != substream->pcm->card)
1530 continue;
1531 azx_dev = get_azx_dev(s);
1532 sbits |= 1 << azx_dev->index;
1533 nsync++;
1534 snd_pcm_trigger_done(s, substream);
1535 }
1536
1537 spin_lock(&chip->reg_lock);
1538 if (nsync > 1) {
1539 /* first, set SYNC bits of corresponding streams */
1540 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1541 }
1542 snd_pcm_group_for_each_entry(s, substream) {
1543 if (s->pcm->card != substream->pcm->card)
1544 continue;
1545 azx_dev = get_azx_dev(s);
1546 if (start)
1547 azx_stream_start(chip, azx_dev);
1548 else
1549 azx_stream_stop(chip, azx_dev);
1550 azx_dev->running = start;
1da177e4
LT		 1551 }
1552 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1553 if (start) {
1554 if (nsync == 1)
1555 return 0;
1556 /* wait until all FIFOs get ready */
1557 for (timeout = 5000; timeout; timeout--) {
1558 nwait = 0;
1559 snd_pcm_group_for_each_entry(s, substream) {
1560 if (s->pcm->card != substream->pcm->card)
1561 continue;
1562 azx_dev = get_azx_dev(s);
1563 if (!(azx_sd_readb(azx_dev, SD_STS) &
1564 SD_STS_FIFO_READY))
1565 nwait++;
1566 }
1567 if (!nwait)
1568 break;
1569 cpu_relax();
1570 }
1571 } else {
1572 /* wait until all RUN bits are cleared */
1573 for (timeout = 5000; timeout; timeout--) {
1574 nwait = 0;
1575 snd_pcm_group_for_each_entry(s, substream) {
1576 if (s->pcm->card != substream->pcm->card)
1577 continue;
1578 azx_dev = get_azx_dev(s);
1579 if (azx_sd_readb(azx_dev, SD_CTL) &
1580 SD_CTL_DMA_START)
1581 nwait++;
1582 }
1583 if (!nwait)
1584 break;
1585 cpu_relax();
1586 }
1da177e4 1587 }
850f0e52
TI		 1588 if (nsync > 1) {
1589 spin_lock(&chip->reg_lock);
1590 /* reset SYNC bits */
1591 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1592 spin_unlock(&chip->reg_lock);
1593 }
1594 return 0;
1da177e4
LT		 1595}
1596
0e153474
JC		 1597/* get the current DMA position with correction on VIA chips */
1598static unsigned int azx_via_get_position(struct azx *chip,
1599 struct azx_dev *azx_dev)
1600{
1601 unsigned int link_pos, mini_pos, bound_pos;
1602 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1603 unsigned int fifo_size;
1604
1605 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1606 if (azx_dev->index >= 4) {
1607 /* Playback, no problem using link position */
1608 return link_pos;
1609 }
1610
1611 /* Capture */
1612 /* For new chipset,
1613 * use mod to get the DMA position just like old chipset
1614 */
1615 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1616 mod_dma_pos %= azx_dev->period_bytes;
1617
1618 /* azx_dev->fifo_size can't get FIFO size of in stream.
1619 * Get from base address + offset.
1620 */
1621 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1622
1623 if (azx_dev->insufficient) {
1624 /* Link position never gather than FIFO size */
1625 if (link_pos <= fifo_size)
1626 return 0;
1627
1628 azx_dev->insufficient = 0;
1629 }
1630
1631 if (link_pos <= fifo_size)
1632 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1633 else
1634 mini_pos = link_pos - fifo_size;
1635
1636 /* Find nearest previous boudary */
1637 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1638 mod_link_pos = link_pos % azx_dev->period_bytes;
1639 if (mod_link_pos >= fifo_size)
1640 bound_pos = link_pos - mod_link_pos;
1641 else if (mod_dma_pos >= mod_mini_pos)
1642 bound_pos = mini_pos - mod_mini_pos;
1643 else {
1644 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1645 if (bound_pos >= azx_dev->bufsize)
1646 bound_pos = 0;
1647 }
1648
1649 /* Calculate real DMA position we want */
1650 return bound_pos + mod_dma_pos;
1651}
1652
9ad593f6
TI		 1653static unsigned int azx_get_position(struct azx *chip,
1654 struct azx_dev *azx_dev)
1da177e4 1655{
1da177e4
LT		 1656 unsigned int pos;
1657
0e153474
JC		 1658 if (chip->via_dmapos_patch)
1659 pos = azx_via_get_position(chip, azx_dev);
1660 else if (chip->position_fix == POS_FIX_POSBUF ||
1661 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1662 /* use the position buffer */
929861c6 1663 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1664 } else {
1665 /* read LPIB */
1666 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1667 }
1da177e4
LT		 1668 if (pos >= azx_dev->bufsize)
1669 pos = 0;
9ad593f6
TI		 1670 return pos;
1671}
1672
1673static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1674{
1675 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1676 struct azx *chip = apcm->chip;
1677 struct azx_dev *azx_dev = get_azx_dev(substream);
1678 return bytes_to_frames(substream->runtime,
1679 azx_get_position(chip, azx_dev));
1680}
1681
1682/*
1683 * Check whether the current DMA position is acceptable for updating
1684 * periods. Returns non-zero if it's OK.
1685 *
1686 * Many HD-audio controllers appear pretty inaccurate about
1687 * the update-IRQ timing. The IRQ is issued before actually the
1688 * data is processed. So, we need to process it afterwords in a
1689 * workqueue.
1690 */
1691static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1692{
1693 unsigned int pos;
1694
1695 pos = azx_get_position(chip, azx_dev);
1696 if (chip->position_fix == POS_FIX_AUTO) {
1697 if (!pos) {
1698 printk(KERN_WARNING
1699 "hda-intel: Invalid position buffer, "
1700 "using LPIB read method instead.\n");
d2e1c973 1701 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1702 pos = azx_get_position(chip, azx_dev);
1703 } else
1704 chip->position_fix = POS_FIX_POSBUF;
1705 }
1706
a62741cf
TI		 1707 if (!bdl_pos_adj[chip->dev_index])
1708 return 1; /* no delayed ack */
9ad593f6
TI		 1709 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1710 return 0; /* NG - it's below the period boundary */
1711 return 1; /* OK, it's fine */
1712}
1713
1714/*
1715 * The work for pending PCM period updates.
1716 */
1717static void azx_irq_pending_work(struct work_struct *work)
1718{
1719 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1720 int i, pending;
1721
a6a950a8
TI		 1722 if (!chip->irq_pending_warned) {
1723 printk(KERN_WARNING
1724 "hda-intel: IRQ timing workaround is activated "
1725 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1726 chip->card->number);
1727 chip->irq_pending_warned = 1;
1728 }
1729
9ad593f6
TI		 1730 for (;;) {
1731 pending = 0;
1732 spin_lock_irq(&chip->reg_lock);
1733 for (i = 0; i < chip->num_streams; i++) {
1734 struct azx_dev *azx_dev = &chip->azx_dev[i];
1735 if (!azx_dev->irq_pending ||
1736 !azx_dev->substream ||
1737 !azx_dev->running)
1738 continue;
1739 if (azx_position_ok(chip, azx_dev)) {
1740 azx_dev->irq_pending = 0;
1741 spin_unlock(&chip->reg_lock);
1742 snd_pcm_period_elapsed(azx_dev->substream);
1743 spin_lock(&chip->reg_lock);
1744 } else
1745 pending++;
1746 }
1747 spin_unlock_irq(&chip->reg_lock);
1748 if (!pending)
1749 return;
1750 cond_resched();
1751 }
1752}
1753
1754/* clear irq_pending flags and assure no on-going workq */
1755static void azx_clear_irq_pending(struct azx *chip)
1756{
1757 int i;
1758
1759 spin_lock_irq(&chip->reg_lock);
1760 for (i = 0; i < chip->num_streams; i++)
1761 chip->azx_dev[i].irq_pending = 0;
1762 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1763}
1764
a98f90fd 1765static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1766 .open = azx_pcm_open,
1767 .close = azx_pcm_close,
1768 .ioctl = snd_pcm_lib_ioctl,
1769 .hw_params = azx_pcm_hw_params,
1770 .hw_free = azx_pcm_hw_free,
1771 .prepare = azx_pcm_prepare,
1772 .trigger = azx_pcm_trigger,
1773 .pointer = azx_pcm_pointer,
4ce107b9 1774 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1775};
1776
a98f90fd 1777static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1778{
176d5335
TI		 1779 struct azx_pcm *apcm = pcm->private_data;
1780 if (apcm) {
1781 apcm->chip->pcm[pcm->device] = NULL;
1782 kfree(apcm);
1783 }
1da177e4
LT		 1784}
1785
176d5335 1786static int
33fa35ed
TI		 1787azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1788 struct hda_pcm *cpcm)
1da177e4 1789{
33fa35ed 1790 struct azx *chip = bus->private_data;
a98f90fd 1791 struct snd_pcm *pcm;
1da177e4 1792 struct azx_pcm *apcm;
176d5335
TI		 1793 int pcm_dev = cpcm->device;
1794 int s, err;
1da177e4 1795
176d5335
TI		 1796 if (pcm_dev >= AZX_MAX_PCMS) {
1797 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1798 pcm_dev);
da3cec35 1799 return -EINVAL;
176d5335
TI		 1800 }
1801 if (chip->pcm[pcm_dev]) {
1802 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1803 return -EBUSY;
1804 }
1805 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1806 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1807 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1808 &pcm);
1809 if (err < 0)
1810 return err;
1811 strcpy(pcm->name, cpcm->name);
176d5335 1812 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1813 if (apcm == NULL)
1814 return -ENOMEM;
1815 apcm->chip = chip;
1816 apcm->codec = codec;
1da177e4
LT		 1817 pcm->private_data = apcm;
1818 pcm->private_free = azx_pcm_free;
176d5335
TI		 1819 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1820 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1821 chip->pcm[pcm_dev] = pcm;
1822 cpcm->pcm = pcm;
1823 for (s = 0; s < 2; s++) {
1824 apcm->hinfo[s] = &cpcm->stream[s];
1825 if (cpcm->stream[s].substreams)
1826 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1827 }
1828 /* buffer pre-allocation */
4ce107b9 1829 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1830 snd_dma_pci_data(chip->pci),
fc4abee8 1831 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 1832 return 0;
1833}
1834
1835/*
1836 * mixer creation - all stuff is implemented in hda module
1837 */
a98f90fd 1838static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1839{
1840 return snd_hda_build_controls(chip->bus);
1841}
1842
1843
1844/*
1845 * initialize SD streams
1846 */
a98f90fd 1847static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1848{
1849 int i;
1850
1851 /* initialize each stream (aka device)
d01ce99f
TI		 1852 * assign the starting bdl address to each stream (device)
1853 * and initialize
1da177e4 1854 */
07e4ca50 1855 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1856 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1857 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1858 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1859 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1860 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1861 azx_dev->sd_int_sta_mask = 1 << i;
1862 /* stream tag: must be non-zero and unique */
1863 azx_dev->index = i;
1864 azx_dev->stream_tag = i + 1;
1865 }
1866
1867 return 0;
1868}
1869
68e7fffc
TI		 1870static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1871{
437a5a46
TI		 1872 if (request_irq(chip->pci->irq, azx_interrupt,
1873 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1874 "HDA Intel", chip)) {
1875 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1876 "disabling device\n", chip->pci->irq);
1877 if (do_disconnect)
1878 snd_card_disconnect(chip->card);
1879 return -1;
1880 }
1881 chip->irq = chip->pci->irq;
69e13418 1882 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1883 return 0;
1884}
1885
1da177e4 1886
cb53c626
TI		 1887static void azx_stop_chip(struct azx *chip)
1888{
95e99fda 1889 if (!chip->initialized)
cb53c626
TI		 1890 return;
1891
1892 /* disable interrupts */
1893 azx_int_disable(chip);
1894 azx_int_clear(chip);
1895
1896 /* disable CORB/RIRB */
1897 azx_free_cmd_io(chip);
1898
1899 /* disable position buffer */
1900 azx_writel(chip, DPLBASE, 0);
1901 azx_writel(chip, DPUBASE, 0);
1902
1903 chip->initialized = 0;
1904}
1905
1906#ifdef CONFIG_SND_HDA_POWER_SAVE
1907/* power-up/down the controller */
33fa35ed 1908static void azx_power_notify(struct hda_bus *bus)
cb53c626 1909{
33fa35ed 1910 struct azx *chip = bus->private_data;
cb53c626
TI		 1911 struct hda_codec *c;
1912 int power_on = 0;
1913
33fa35ed 1914 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 1915 if (c->power_on) {
1916 power_on = 1;
1917 break;
1918 }
1919 }
1920 if (power_on)
1921 azx_init_chip(chip);
dee1b66c 1922 else if (chip->running && power_save_controller)
cb53c626 1923 azx_stop_chip(chip);
cb53c626 1924}
5c0b9bec
TI		 1925#endif /* CONFIG_SND_HDA_POWER_SAVE */
1926
1927#ifdef CONFIG_PM
1928/*
1929 * power management
1930 */
986862bd
TI		 1931
1932static int snd_hda_codecs_inuse(struct hda_bus *bus)
1933{
1934 struct hda_codec *codec;
1935
1936 list_for_each_entry(codec, &bus->codec_list, list) {
1937 if (snd_hda_codec_needs_resume(codec))
1938 return 1;
1939 }
1940 return 0;
1941}
cb53c626 1942
421a1252 1943static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1944{
421a1252
TI		 1945 struct snd_card *card = pci_get_drvdata(pci);
1946 struct azx *chip = card->private_data;
1da177e4
LT		 1947 int i;
1948
421a1252 1949 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1950 azx_clear_irq_pending(chip);
7ba72ba1 1951 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 1952 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI		 1953 if (chip->initialized)
1954 snd_hda_suspend(chip->bus, state);
cb53c626 1955 azx_stop_chip(chip);
30b35399 1956 if (chip->irq >= 0) {
43001c95 1957 free_irq(chip->irq, chip);
30b35399
TI		 1958 chip->irq = -1;
1959 }
68e7fffc 1960 if (chip->msi)
43001c95 1961 pci_disable_msi(chip->pci);
421a1252
TI		 1962 pci_disable_device(pci);
1963 pci_save_state(pci);
30b35399 1964 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1965 return 0;
1966}
1967
421a1252 1968static int azx_resume(struct pci_dev *pci)
1da177e4 1969{
421a1252
TI		 1970 struct snd_card *card = pci_get_drvdata(pci);
1971 struct azx *chip = card->private_data;
1da177e4 1972
d14a7e0b
TI		 1973 pci_set_power_state(pci, PCI_D0);
1974 pci_restore_state(pci);
30b35399
TI		 1975 if (pci_enable_device(pci) < 0) {
1976 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1977 "disabling device\n");
1978 snd_card_disconnect(card);
1979 return -EIO;
1980 }
1981 pci_set_master(pci);
68e7fffc
TI		 1982 if (chip->msi)
1983 if (pci_enable_msi(pci) < 0)
1984 chip->msi = 0;
1985 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1986 return -EIO;
cb53c626 1987 azx_init_pci(chip);
d804ad92
ML		 1988
1989 if (snd_hda_codecs_inuse(chip->bus))
1990 azx_init_chip(chip);
1991
1da177e4 1992 snd_hda_resume(chip->bus);
421a1252 1993 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1994 return 0;
1995}
1996#endif /* CONFIG_PM */
1997
1998
0cbf0098
TI		 1999/*
2000 * reboot notifier for hang-up problem at power-down
2001 */
2002static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2003{
2004 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2005 azx_stop_chip(chip);
2006 return NOTIFY_OK;
2007}
2008
2009static void azx_notifier_register(struct azx *chip)
2010{
2011 chip->reboot_notifier.notifier_call = azx_halt;
2012 register_reboot_notifier(&chip->reboot_notifier);
2013}
2014
2015static void azx_notifier_unregister(struct azx *chip)
2016{
2017 if (chip->reboot_notifier.notifier_call)
2018 unregister_reboot_notifier(&chip->reboot_notifier);
2019}
2020
1da177e4
LT		 2021/*
2022 * destructor
2023 */
a98f90fd 2024static int azx_free(struct azx *chip)
1da177e4 2025{
4ce107b9
TI		 2026 int i;
2027
0cbf0098
TI		 2028 azx_notifier_unregister(chip);
2029
ce43fbae 2030 if (chip->initialized) {
9ad593f6 2031 azx_clear_irq_pending(chip);
07e4ca50 2032 for (i = 0; i < chip->num_streams; i++)
1da177e4 2033 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2034 azx_stop_chip(chip);
1da177e4
LT		 2035 }
2036
f000fd80 2037 if (chip->irq >= 0)
1da177e4 2038 free_irq(chip->irq, (void*)chip);
68e7fffc 2039 if (chip->msi)
30b35399 2040 pci_disable_msi(chip->pci);
f079c25a
TI		 2041 if (chip->remap_addr)
2042 iounmap(chip->remap_addr);
1da177e4 2043
4ce107b9
TI		 2044 if (chip->azx_dev) {
2045 for (i = 0; i < chip->num_streams; i++)
2046 if (chip->azx_dev[i].bdl.area)
2047 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2048 }
1da177e4
LT		 2049 if (chip->rb.area)
2050 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2051 if (chip->posbuf.area)
2052 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2053 pci_release_regions(chip->pci);
2054 pci_disable_device(chip->pci);
07e4ca50 2055 kfree(chip->azx_dev);
1da177e4
LT		 2056 kfree(chip);
2057
2058 return 0;
2059}
2060
a98f90fd 2061static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2062{
2063 return azx_free(device->device_data);
2064}
2065
3372a153
TI		 2066/*
2067 * white/black-listing for position_fix
2068 */
623ec047 2069static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2070 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2071 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2072 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 2073 {}
2074};
2075
2076static int __devinit check_position_fix(struct azx *chip, int fix)
2077{
2078 const struct snd_pci_quirk *q;
2079
c673ba1c
TI		 2080 switch (fix) {
2081 case POS_FIX_LPIB:
2082 case POS_FIX_POSBUF:
2083 return fix;
2084 }
2085
2086 /* Check VIA/ATI HD Audio Controller exist */
2087 switch (chip->driver_type) {
2088 case AZX_DRIVER_VIA:
2089 case AZX_DRIVER_ATI:
0e153474
JC		 2090 chip->via_dmapos_patch = 1;
2091 /* Use link position directly, avoid any transfer problem. */
2092 return POS_FIX_LPIB;
2093 }
2094 chip->via_dmapos_patch = 0;
2095
c673ba1c
TI		 2096 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2097 if (q) {
2098 printk(KERN_INFO
2099 "hda_intel: position_fix set to %d "
2100 "for device %04x:%04x\n",
2101 q->value, q->subvendor, q->subdevice);
2102 return q->value;
3372a153 2103 }
c673ba1c 2104 return POS_FIX_AUTO;
3372a153
TI		 2105}
2106
669ba27a
TI		 2107/*
2108 * black-lists for probe_mask
2109 */
2110static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2111 /* Thinkpad often breaks the controller communication when accessing
2112 * to the non-working (or non-existing) modem codec slot.
2113 */
2114 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2115 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2116 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2117 /* broken BIOS */
2118 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2119 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2120 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0
TI		 2121 /* forced codec slots */
2122 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2123 {}
2124};
2125
f1eaaeec
TI		 2126#define AZX_FORCE_CODEC_MASK 0x100
2127
5aba4f8e 2128static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2129{
2130 const struct snd_pci_quirk *q;
2131
f1eaaeec
TI		 2132 chip->codec_probe_mask = probe_mask[dev];
2133 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2134 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2135 if (q) {
2136 printk(KERN_INFO
2137 "hda_intel: probe_mask set to 0x%x "
2138 "for device %04x:%04x\n",
2139 q->value, q->subvendor, q->subdevice);
f1eaaeec 2140 chip->codec_probe_mask = q->value;
669ba27a
TI		 2141 }
2142 }
f1eaaeec
TI		 2143
2144 /* check forced option */
2145 if (chip->codec_probe_mask != -1 &&
2146 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2147 chip->codec_mask = chip->codec_probe_mask & 0xff;
2148 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2149 chip->codec_mask);
2150 }
669ba27a
TI		 2151}
2152
2153
1da177e4
LT		 2154/*
2155 * constructor
2156 */
a98f90fd 2157static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2158 int dev, int driver_type,
a98f90fd 2159 struct azx **rchip)
1da177e4 2160{
a98f90fd 2161 struct azx *chip;
4ce107b9 2162 int i, err;
bcd72003 2163 unsigned short gcap;
a98f90fd 2164 static struct snd_device_ops ops = {
1da177e4
LT		 2165 .dev_free = azx_dev_free,
2166 };
2167
2168 *rchip = NULL;
bcd72003 2169
927fc866
PM		 2170 err = pci_enable_device(pci);
2171 if (err < 0)
1da177e4
LT		 2172 return err;
2173
e560d8d8 2174 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2175 if (!chip) {
1da177e4
LT		 2176 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2177 pci_disable_device(pci);
2178 return -ENOMEM;
2179 }
2180
2181 spin_lock_init(&chip->reg_lock);
62932df8 2182 mutex_init(&chip->open_mutex);
1da177e4
LT		 2183 chip->card = card;
2184 chip->pci = pci;
2185 chip->irq = -1;
07e4ca50 2186 chip->driver_type = driver_type;
134a11f0 2187 chip->msi = enable_msi;
555e219f 2188 chip->dev_index = dev;
9ad593f6 2189 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2190
5aba4f8e
TI		 2191 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2192 check_probe_mask(chip, dev);
3372a153 2193
27346166 2194 chip->single_cmd = single_cmd;
c74db86b 2195
5c0d7bc1
TI		 2196 if (bdl_pos_adj[dev] < 0) {
2197 switch (chip->driver_type) {
0c6341ac
TI		 2198 case AZX_DRIVER_ICH:
2199 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2200 break;
2201 default:
0c6341ac 2202 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2203 break;
2204 }
2205 }
2206
07e4ca50
TI		 2207#if BITS_PER_LONG != 64
2208 /* Fix up base address on ULI M5461 */
2209 if (chip->driver_type == AZX_DRIVER_ULI) {
2210 u16 tmp3;
2211 pci_read_config_word(pci, 0x40, &tmp3);
2212 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2213 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2214 }
2215#endif
2216
927fc866
PM		 2217 err = pci_request_regions(pci, "ICH HD audio");
2218 if (err < 0) {
1da177e4
LT		 2219 kfree(chip);
2220 pci_disable_device(pci);
2221 return err;
2222 }
2223
927fc866 2224 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2225 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2226 if (chip->remap_addr == NULL) {
2227 snd_printk(KERN_ERR SFX "ioremap error\n");
2228 err = -ENXIO;
2229 goto errout;
2230 }
2231
68e7fffc
TI		 2232 if (chip->msi)
2233 if (pci_enable_msi(pci) < 0)
2234 chip->msi = 0;
7376d013 2235
68e7fffc 2236 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2237 err = -EBUSY;
2238 goto errout;
2239 }
1da177e4
LT		 2240
2241 pci_set_master(pci);
2242 synchronize_irq(chip->irq);
2243
bcd72003
TD		 2244 gcap = azx_readw(chip, GCAP);
2245 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2246
09240cf4
TI		 2247 /* ATI chips seems buggy about 64bit DMA addresses */
2248 if (chip->driver_type == AZX_DRIVER_ATI)
2249 gcap &= ~0x01;
2250
cf7aaca8
TI		 2251 /* allow 64bit DMA address if supported by H/W */
2252 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2253 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
09240cf4
TI		 2254 else {
2255 pci_set_dma_mask(pci, DMA_32BIT_MASK);
2256 pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
2257 }
cf7aaca8 2258
8b6ed8e7
TI		 2259 /* read number of streams from GCAP register instead of using
2260 * hardcoded value
2261 */
2262 chip->capture_streams = (gcap >> 8) & 0x0f;
2263 chip->playback_streams = (gcap >> 12) & 0x0f;
2264 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2265 /* gcap didn't give any info, switching to old method */
2266
2267 switch (chip->driver_type) {
2268 case AZX_DRIVER_ULI:
2269 chip->playback_streams = ULI_NUM_PLAYBACK;
2270 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2271 break;
2272 case AZX_DRIVER_ATIHDMI:
2273 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2274 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2275 break;
c4da29ca 2276 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2277 default:
2278 chip->playback_streams = ICH6_NUM_PLAYBACK;
2279 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2280 break;
2281 }
07e4ca50 2282 }
8b6ed8e7
TI		 2283 chip->capture_index_offset = 0;
2284 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2285 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2286 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2287 GFP_KERNEL);
927fc866 2288 if (!chip->azx_dev) {
07e4ca50
TI		 2289 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2290 goto errout;
2291 }
2292
4ce107b9
TI		 2293 for (i = 0; i < chip->num_streams; i++) {
2294 /* allocate memory for the BDL for each stream */
2295 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2296 snd_dma_pci_data(chip->pci),
2297 BDL_SIZE, &chip->azx_dev[i].bdl);
2298 if (err < 0) {
2299 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2300 goto errout;
2301 }
1da177e4 2302 }
0be3b5d3 2303 /* allocate memory for the position buffer */
d01ce99f
TI		 2304 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2305 snd_dma_pci_data(chip->pci),
2306 chip->num_streams * 8, &chip->posbuf);
2307 if (err < 0) {
0be3b5d3
TI		 2308 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2309 goto errout;
1da177e4 2310 }
1da177e4 2311 /* allocate CORB/RIRB */
d01ce99f
TI		 2312 if (!chip->single_cmd) {
2313 err = azx_alloc_cmd_io(chip);
2314 if (err < 0)
27346166 2315 goto errout;
d01ce99f 2316 }
1da177e4
LT		 2317
2318 /* initialize streams */
2319 azx_init_stream(chip);
2320
2321 /* initialize chip */
cb53c626 2322 azx_init_pci(chip);
1da177e4
LT		 2323 azx_init_chip(chip);
2324
2325 /* codec detection */
927fc866 2326 if (!chip->codec_mask) {
1da177e4
LT		 2327 snd_printk(KERN_ERR SFX "no codecs found!\n");
2328 err = -ENODEV;
2329 goto errout;
2330 }
2331
d01ce99f
TI		 2332 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2333 if (err <0) {
1da177e4
LT		 2334 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2335 goto errout;
2336 }
2337
07e4ca50
TI		 2338 strcpy(card->driver, "HDA-Intel");
2339 strcpy(card->shortname, driver_short_names[chip->driver_type]);
d01ce99f
TI		 2340 sprintf(card->longname, "%s at 0x%lx irq %i",
2341 card->shortname, chip->addr, chip->irq);
07e4ca50 2342
1da177e4
LT		 2343 *rchip = chip;
2344 return 0;
2345
2346 errout:
2347 azx_free(chip);
2348 return err;
2349}
2350
cb53c626
TI		 2351static void power_down_all_codecs(struct azx *chip)
2352{
2353#ifdef CONFIG_SND_HDA_POWER_SAVE
2354 /* The codecs were powered up in snd_hda_codec_new().
2355 * Now all initialization done, so turn them down if possible
2356 */
2357 struct hda_codec *codec;
2358 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2359 snd_hda_power_down(codec);
2360 }
2361#endif
2362}
2363
d01ce99f
TI		 2364static int __devinit azx_probe(struct pci_dev *pci,
2365 const struct pci_device_id *pci_id)
1da177e4 2366{
5aba4f8e 2367 static int dev;
a98f90fd
TI		 2368 struct snd_card *card;
2369 struct azx *chip;
927fc866 2370 int err;
1da177e4 2371
5aba4f8e
TI		 2372 if (dev >= SNDRV_CARDS)
2373 return -ENODEV;
2374 if (!enable[dev]) {
2375 dev++;
2376 return -ENOENT;
2377 }
2378
2379 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
927fc866 2380 if (!card) {
1da177e4
LT		 2381 snd_printk(KERN_ERR SFX "Error creating card!\n");
2382 return -ENOMEM;
2383 }
2384
5aba4f8e 2385 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2386 if (err < 0)
2387 goto out_free;
421a1252 2388 card->private_data = chip;
1da177e4 2389
1da177e4 2390 /* create codec instances */
f1eaaeec 2391 err = azx_codec_create(chip, model[dev], probe_only[dev]);
41dda0fd
WF		 2392 if (err < 0)
2393 goto out_free;
1da177e4
LT		 2394
2395 /* create PCM streams */
176d5335 2396 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2397 if (err < 0)
2398 goto out_free;
1da177e4
LT		 2399
2400 /* create mixer controls */
d01ce99f 2401 err = azx_mixer_create(chip);
41dda0fd
WF		 2402 if (err < 0)
2403 goto out_free;
1da177e4 2404
1da177e4
LT		 2405 snd_card_set_dev(card, &pci->dev);
2406
d01ce99f 2407 err = snd_card_register(card);
41dda0fd
WF		 2408 if (err < 0)
2409 goto out_free;
1da177e4
LT		 2410
2411 pci_set_drvdata(pci, card);
cb53c626
TI		 2412 chip->running = 1;
2413 power_down_all_codecs(chip);
0cbf0098 2414 azx_notifier_register(chip);
1da177e4 2415
e25bcdba 2416 dev++;
1da177e4 2417 return err;
41dda0fd
WF		 2418out_free:
2419 snd_card_free(card);
2420 return err;
1da177e4
LT		 2421}
2422
2423static void __devexit azx_remove(struct pci_dev *pci)
2424{
2425 snd_card_free(pci_get_drvdata(pci));
2426 pci_set_drvdata(pci, NULL);
2427}
2428
2429/* PCI IDs */
f40b6890 2430static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2431 /* ICH 6..10 */
2432 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2433 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2434 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2435 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2436 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2437 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2438 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2439 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2440 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2441 /* PCH */
2442 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2443 /* SCH */
2444 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2445 /* ATI SB 450/600 */
2446 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2447 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2448 /* ATI HDMI */
2449 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2450 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2451 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2452 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2453 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2454 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2455 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2456 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2457 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2458 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2459 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2460 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2461 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2462 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2463 /* VIA VT8251/VT8237A */
2464 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2465 /* SIS966 */
2466 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2467 /* ULI M5461 */
2468 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2469 /* NVIDIA MCP */
2470 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2471 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2472 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2473 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2474 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2475 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2476 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2477 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2478 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2479 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2480 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2481 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2482 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2483 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2484 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2485 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2486 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2487 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
bedfcebb 2488 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2489 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2490 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2491 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2492 /* Teradici */
2493 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
c4da29ca
YL		 2494 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2495 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2496 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2497 .class_mask = 0xffffff,
2498 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2499 { 0, }
2500};
2501MODULE_DEVICE_TABLE(pci, azx_ids);
2502
2503/* pci_driver definition */
2504static struct pci_driver driver = {
2505 .name = "HDA Intel",
2506 .id_table = azx_ids,
2507 .probe = azx_probe,
2508 .remove = __devexit_p(azx_remove),
421a1252
TI		 2509#ifdef CONFIG_PM
2510 .suspend = azx_suspend,
2511 .resume = azx_resume,
2512#endif
1da177e4
LT		 2513};
2514
2515static int __init alsa_card_azx_init(void)
2516{
01d25d46 2517 return pci_register_driver(&driver);
1da177e4
LT		 2518}
2519
2520static void __exit alsa_card_azx_exit(void)
2521{
2522 pci_unregister_driver(&driver);
2523}
2524
2525module_init(alsa_card_azx_init)
2526module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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