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ALSA: hda - fix use-after-free after module unload
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 93#define INTEL_HDA_CGCTL 0x48
94#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 95#define INTEL_SCH_HDA_DEVC 0x78
96#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98/* Define IN stream 0 FIFO size offset in VIA controller */
99#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100/* Define VIA HD Audio Device ID*/
101#define VIA_HDAC_DEVICE_ID 0x3288
102
33124929
TI		 103/* max number of SDs */
104/* ICH, ATI and VIA have 4 playback and 4 capture */
105#define ICH6_NUM_CAPTURE 4
106#define ICH6_NUM_PLAYBACK 4
107
108/* ULI has 6 playback and 5 capture */
109#define ULI_NUM_CAPTURE 5
110#define ULI_NUM_PLAYBACK 6
111
112/* ATI HDMI may have up to 8 playbacks and 0 capture */
113#define ATIHDMI_NUM_CAPTURE 0
114#define ATIHDMI_NUM_PLAYBACK 8
115
116/* TERA has 4 playback and 3 capture */
117#define TERA_NUM_CAPTURE 3
118#define TERA_NUM_PLAYBACK 4
119
1da177e4 120
5aba4f8e
TI		 121static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 123static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 124static char *model[SNDRV_CARDS];
1dac6695 125static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 126static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 127static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 128static int probe_only[SNDRV_CARDS];
26a6cb6c 129static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 130static bool single_cmd;
71623855 131static int enable_msi = -1;
4ea6fbc8
TI		 132#ifdef CONFIG_SND_HDA_PATCH_LOADER
133static char *patch[SNDRV_CARDS];
134#endif
2dca0bba 135#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 136static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138#endif
1da177e4 139
5aba4f8e 140module_param_array(index, int, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 142module_param_array(id, charp, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 144module_param_array(enable, bool, NULL, 0444);
145MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146module_param_array(model, charp, NULL, 0444);
1da177e4 147MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 148module_param_array(position_fix, int, NULL, 0444);
4cb36310 149MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 151module_param_array(bdl_pos_adj, int, NULL, 0644);
152MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 153module_param_array(probe_mask, int, NULL, 0444);
606ad75f 154MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 155module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 156MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 157module_param_array(jackpoll_ms, int, NULL, 0444);
158MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 159module_param(single_cmd, bool, 0444);
d01ce99f
TI		 160MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
ac9ef6cf 162module_param(enable_msi, bint, 0444);
134a11f0 163MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 164#ifdef CONFIG_SND_HDA_PATCH_LOADER
165module_param_array(patch, charp, NULL, 0444);
166MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167#endif
2dca0bba 168#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 169module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 170MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 171 "(0=off, 1=on) (default=1).");
2dca0bba 172#endif
606ad75f 173
83012a7c 174#ifdef CONFIG_PM
65fcd41d 175static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 176static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 177 .set = param_set_xint,
178 .get = param_get_int,
179};
180#define param_check_xint param_check_int
181
fee2fba3 182static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 183module_param(power_save, xint, 0644);
fee2fba3
TI		 184MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
1da177e4 186
dee1b66c
TI		 187/* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
8fc24426
TI		 191static bool power_save_controller = 1;
192module_param(power_save_controller, bool, 0644);
dee1b66c 193MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 194#else
bb573928 195#define power_save 0
83012a7c 196#endif /* CONFIG_PM */
dee1b66c 197
7bfe059e
TI		 198static int align_buffer_size = -1;
199module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 200MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
27fe48d9 203#ifdef CONFIG_X86
7c732015
TI		 204static int hda_snoop = -1;
205module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 206MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 207#else
208#define hda_snoop true
27fe48d9
TI		 209#endif
210
211
1da177e4
LT		 212MODULE_LICENSE("GPL");
213MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
2f1b3818 215 "{Intel, ICH7},"
f5d40b30 216 "{Intel, ESB2},"
d2981393 217 "{Intel, ICH8},"
f9cc8a8b 218 "{Intel, ICH9},"
c34f5a04 219 "{Intel, ICH10},"
b29c2360 220 "{Intel, PCH},"
d2f2fcd2 221 "{Intel, CPT},"
d2edeb7c 222 "{Intel, PPT},"
8bc039a1 223 "{Intel, LPT},"
144dad99 224 "{Intel, LPT_LP},"
4eeca499 225 "{Intel, WPT_LP},"
c8b00fd2 226 "{Intel, SPT},"
b4565913 227 "{Intel, SPT_LP},"
e926f2c8 228 "{Intel, HPT},"
cea310e8 229 "{Intel, PBG},"
4979bca9 230 "{Intel, SCH},"
fc20a562 231 "{ATI, SB450},"
89be83f8 232 "{ATI, SB600},"
778b6e1b 233 "{ATI, RS600},"
5b15c95f 234 "{ATI, RS690},"
e6db1119
WL		 235 "{ATI, RS780},"
236 "{ATI, R600},"
2797f724
HRK		 237 "{ATI, RV630},"
238 "{ATI, RV610},"
27da1834
WL		 239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
fc20a562 243 "{VIA, VT8251},"
47672310 244 "{VIA, VT8237A},"
07e4ca50
TI		 245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
1da177e4
LT		 247MODULE_DESCRIPTION("Intel HDA driver");
248
a82d51ed 249#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 250#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 251#define SUPPORT_VGA_SWITCHEROO
252#endif
253#endif
254
255
1da177e4 256/*
1da177e4 257 */
1da177e4 258
07e4ca50
TI		 259/* driver types */
260enum {
261 AZX_DRIVER_ICH,
32679f95 262 AZX_DRIVER_PCH,
4979bca9 263 AZX_DRIVER_SCH,
fab1285a 264 AZX_DRIVER_HDMI,
07e4ca50 265 AZX_DRIVER_ATI,
778b6e1b 266 AZX_DRIVER_ATIHDMI,
1815b34a 267 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
da3fca21 271 AZX_DRIVER_NVIDIA,
f269002e 272 AZX_DRIVER_TERA,
14d34f16 273 AZX_DRIVER_CTX,
5ae763b1 274 AZX_DRIVER_CTHDA,
c563f473 275 AZX_DRIVER_CMEDIA,
c4da29ca 276 AZX_DRIVER_GENERIC,
2f5983f2 277 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 278};
279
37e661ee
TI		 280#define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
b42b4afb
TI		 284/* quirks for old Intel chipsets */
285#define AZX_DCAPS_INTEL_ICH \
103884a3 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 287
2ea3c6a2 288/* quirks for Intel PCH */
6603249d 289#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 291 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 292
55913110 293/* PCH up to IVB; no runtime PM */
6603249d 294#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 295 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 296
55913110 297/* PCH for HSW/BDW; with runtime PM */
d7dab4db 298#define AZX_DCAPS_INTEL_PCH \
6603249d 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 300
6603249d 301/* HSW HDMI */
33499a15 302#define AZX_DCAPS_INTEL_HASWELL \
103884a3 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 306
54a0405d
LY		 307/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
308#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
311 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 312
40cc2392
ML		 313#define AZX_DCAPS_INTEL_BAYTRAIL \
314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
315
2d846c74
LY		 316#define AZX_DCAPS_INTEL_BRASWELL \
317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
318
d6795827 319#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
321 AZX_DCAPS_I915_POWERWELL)
d6795827 322
c87693da
LH		 323#define AZX_DCAPS_INTEL_BROXTON \
324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
325 AZX_DCAPS_I915_POWERWELL)
326
9477c58e
TI		 327/* quirks for ATI SB / AMD Hudson */
328#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 331
332/* quirks for ATI/AMD HDMI */
333#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
9477c58e 336
37e661ee
TI		 337/* quirks for ATI HDMI with snoop off */
338#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
9477c58e
TI		 341/* quirks for Nvidia */
342#define AZX_DCAPS_PRESET_NVIDIA \
7d9a1808 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
345 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 346
5ae763b1 347#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 349 AZX_DCAPS_NO_64BIT |\
37e661ee 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 351
a82d51ed 352/*
2b760d88 353 * vga_switcheroo support
a82d51ed
TI		 354 */
355#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 356#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
357#else
358#define use_vga_switcheroo(chip) 0
359#endif
360
03b135ce
LY		 361#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
362 ((pci)->device == 0x0c0c) || \
363 ((pci)->device == 0x0d0c) || \
364 ((pci)->device == 0x160c))
365
7e31a015
TI		 366#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
367#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
35639a0e
VK		 368#define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
369#define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
6858107e 370#define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
7e31a015 371#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
35639a0e 372#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
6858107e 373 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
7c23b7c1 374
48c8b0eb 375static char *driver_short_names[] = {
07e4ca50 376 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 377 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 378 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 379 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 380 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 381 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 382 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 383 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
384 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 385 [AZX_DRIVER_ULI] = "HDA ULI M5461",
386 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 387 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 388 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 389 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 390 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 391 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 392};
393
27fe48d9 394#ifdef CONFIG_X86
9ddf1aeb 395static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 396{
9ddf1aeb
TI		 397 int pages;
398
27fe48d9
TI		 399 if (azx_snoop(chip))
400 return;
9ddf1aeb
TI		 401 if (!dmab || !dmab->area || !dmab->bytes)
402 return;
403
404#ifdef CONFIG_SND_DMA_SGBUF
405 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
406 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 407 if (chip->driver_type == AZX_DRIVER_CMEDIA)
408 return; /* deal with only CORB/RIRB buffers */
27fe48d9 409 if (on)
9ddf1aeb 410 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 411 else
9ddf1aeb
TI		 412 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
413 return;
27fe48d9 414 }
9ddf1aeb
TI		 415#endif
416
417 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
418 if (on)
419 set_memory_wc((unsigned long)dmab->area, pages);
420 else
421 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 422}
423
424static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
425 bool on)
426{
9ddf1aeb 427 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 428}
429static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 430 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 431{
432 if (azx_dev->wc_marked != on) {
9ddf1aeb 433 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 434 azx_dev->wc_marked = on;
435 }
436}
437#else
438/* NOP for other archs */
439static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
440 bool on)
441{
442}
443static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 444 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 445{
446}
447#endif
448
68e7fffc 449static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 450
cb53c626
TI		 451/*
452 * initialize the PCI registers
453 */
454/* update bits in a PCI register byte */
455static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
456 unsigned char mask, unsigned char val)
457{
458 unsigned char data;
459
460 pci_read_config_byte(pci, reg, &data);
461 data &= ~mask;
462 data |= (val & mask);
463 pci_write_config_byte(pci, reg, data);
464}
465
466static void azx_init_pci(struct azx *chip)
467{
37e661ee
TI		 468 int snoop_type = azx_get_snoop_type(chip);
469
cb53c626
TI		 470 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
471 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
472 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 473 * codecs.
474 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 475 */
46f2cc80 476 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 477 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 478 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 479 }
cb53c626 480
9477c58e
TI		 481 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
482 * we need to enable snoop.
483 */
37e661ee 484 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 485 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
486 azx_snoop(chip));
cb53c626 487 update_pci_byte(chip->pci,
27fe48d9
TI		 488 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
489 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 490 }
491
492 /* For NVIDIA HDA, enable snoop */
37e661ee 493 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 494 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
495 azx_snoop(chip));
cb53c626
TI		 496 update_pci_byte(chip->pci,
497 NVIDIA_HDA_TRANSREG_ADDR,
498 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 499 update_pci_byte(chip->pci,
500 NVIDIA_HDA_ISTRM_COH,
501 0x01, NVIDIA_HDA_ENABLE_COHBIT);
502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_OSTRM_COH,
504 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 505 }
506
507 /* Enable SCH/PCH snoop if needed */
37e661ee 508 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 509 unsigned short snoop;
90a5ad52 510 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 511 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
512 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
513 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
514 if (!azx_snoop(chip))
515 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
516 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 517 pci_read_config_word(chip->pci,
518 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 519 }
4e76a883
TI		 520 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
521 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
522 "Disabled" : "Enabled");
da3fca21 523 }
1da177e4
LT		 524}
525
7c23b7c1
LH		 526/*
527 * In BXT-P A0, HD-Audio DMA requests is later than expected,
528 * and makes an audio stream sensitive to system latencies when
529 * 24/32 bits are playing.
530 * Adjusting threshold of DMA fifo to force the DMA request
531 * sooner to improve latency tolerance at the expense of power.
532 */
533static void bxt_reduce_dma_latency(struct azx *chip)
534{
535 u32 val;
536
537 val = azx_readl(chip, SKL_EM4L);
538 val &= (0x3 << 20);
539 azx_writel(chip, SKL_EM4L, val);
540}
541
0a673521
LH		 542static void hda_intel_init_chip(struct azx *chip, bool full_reset)
543{
98d8fc6c 544 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 545 struct pci_dev *pci = chip->pci;
6639484d 546 u32 val;
0a673521
LH		 547
548 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 549 snd_hdac_set_codec_wakeup(bus, true);
7e31a015 550 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 551 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
552 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
553 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
554 }
0a673521 555 azx_init_chip(chip, full_reset);
7e31a015 556 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
0a673521 561 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 562 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 563
564 /* reduce dma latency to avoid noise */
7e31a015 565 if (IS_BXT(pci))
7c23b7c1 566 bxt_reduce_dma_latency(chip);
0a673521
LH		 567}
568
b6050ef6
TI		 569/* calculate runtime delay from LPIB */
570static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
571 unsigned int pos)
572{
7833c3f8 573 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 574 int stream = substream->stream;
575 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
576 int delay;
577
578 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
579 delay = pos - lpib_pos;
580 else
581 delay = lpib_pos - pos;
582 if (delay < 0) {
7833c3f8 583 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 584 delay = 0;
585 else
7833c3f8 586 delay += azx_dev->core.bufsize;
b6050ef6
TI		 587 }
588
7833c3f8 589 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 590 dev_info(chip->card->dev,
591 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 592 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 593 delay = 0;
594 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
595 chip->get_delay[stream] = NULL;
596 }
597
598 return bytes_to_frames(substream->runtime, delay);
599}
600
9ad593f6
TI		 601static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
602
7ca954a8
DR		 603/* called from IRQ */
604static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
605{
9a34af4a 606 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 607 int ok;
608
609 ok = azx_position_ok(chip, azx_dev);
610 if (ok == 1) {
611 azx_dev->irq_pending = 0;
612 return ok;
2f35c630 613 } else if (ok == 0) {
7ca954a8
DR		 614 /* bogus IRQ, process it later */
615 azx_dev->irq_pending = 1;
2f35c630 616 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 617 }
618 return 0;
619}
620
17eccb27
ML		 621/* Enable/disable i915 display power for the link */
622static int azx_intel_link_power(struct azx *chip, bool enable)
623{
98d8fc6c 624 struct hdac_bus *bus = azx_bus(chip);
17eccb27 625
98d8fc6c 626 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 627}
628
9ad593f6
TI		 629/*
630 * Check whether the current DMA position is acceptable for updating
631 * periods. Returns non-zero if it's OK.
632 *
633 * Many HD-audio controllers appear pretty inaccurate about
634 * the update-IRQ timing. The IRQ is issued before actually the
635 * data is processed. So, we need to process it afterwords in a
636 * workqueue.
637 */
638static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
639{
7833c3f8 640 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 641 int stream = substream->stream;
e5463720 642 u32 wallclk;
9ad593f6
TI		 643 unsigned int pos;
644
7833c3f8
TI		 645 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
646 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 647 return -1; /* bogus (too early) interrupt */
fa00e046 648
b6050ef6
TI		 649 if (chip->get_position[stream])
650 pos = chip->get_position[stream](chip, azx_dev);
651 else { /* use the position buffer as default */
652 pos = azx_get_pos_posbuf(chip, azx_dev);
653 if (!pos || pos == (u32)-1) {
654 dev_info(chip->card->dev,
655 "Invalid position buffer, using LPIB read method instead.\n");
656 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 657 if (chip->get_position[0] == azx_get_pos_lpib &&
658 chip->get_position[1] == azx_get_pos_lpib)
659 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 660 pos = azx_get_pos_lpib(chip, azx_dev);
661 chip->get_delay[stream] = NULL;
662 } else {
663 chip->get_position[stream] = azx_get_pos_posbuf;
664 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
665 chip->get_delay[stream] = azx_get_delay_from_lpib;
666 }
667 }
668
7833c3f8 669 if (pos >= azx_dev->core.bufsize)
b6050ef6 670 pos = 0;
9ad593f6 671
7833c3f8 672 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 673 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 674 return -1; /* this shouldn't happen! */
7833c3f8
TI		 675 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
676 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 677 /* NG - it's below the first next period boundary */
4f0189be 678 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 679 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 680 return 1; /* OK, it's fine */
681}
682
683/*
684 * The work for pending PCM period updates.
685 */
686static void azx_irq_pending_work(struct work_struct *work)
687{
9a34af4a
TI		 688 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
689 struct azx *chip = &hda->chip;
7833c3f8
TI		 690 struct hdac_bus *bus = azx_bus(chip);
691 struct hdac_stream *s;
692 int pending, ok;
9ad593f6 693
9a34af4a 694 if (!hda->irq_pending_warned) {
4e76a883
TI		 695 dev_info(chip->card->dev,
696 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
697 chip->card->number);
9a34af4a 698 hda->irq_pending_warned = 1;
a6a950a8
TI		 699 }
700
9ad593f6
TI		 701 for (;;) {
702 pending = 0;
a41d1224 703 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 704 list_for_each_entry(s, &bus->stream_list, list) {
705 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 706 if (!azx_dev->irq_pending ||
7833c3f8
TI		 707 !s->substream ||
708 !s->running)
9ad593f6 709 continue;
e5463720
JK		 710 ok = azx_position_ok(chip, azx_dev);
711 if (ok > 0) {
9ad593f6 712 azx_dev->irq_pending = 0;
a41d1224 713 spin_unlock(&bus->reg_lock);
7833c3f8 714 snd_pcm_period_elapsed(s->substream);
a41d1224 715 spin_lock(&bus->reg_lock);
e5463720
JK		 716 } else if (ok < 0) {
717 pending = 0; /* too early */
9ad593f6
TI		 718 } else
719 pending++;
720 }
a41d1224 721 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 722 if (!pending)
723 return;
08af495f 724 msleep(1);
9ad593f6
TI		 725 }
726}
727
728/* clear irq_pending flags and assure no on-going workq */
729static void azx_clear_irq_pending(struct azx *chip)
730{
7833c3f8
TI		 731 struct hdac_bus *bus = azx_bus(chip);
732 struct hdac_stream *s;
9ad593f6 733
a41d1224 734 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 735 list_for_each_entry(s, &bus->stream_list, list) {
736 struct azx_dev *azx_dev = stream_to_azx_dev(s);
737 azx_dev->irq_pending = 0;
738 }
a41d1224 739 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 740}
741
68e7fffc
TI		 742static int azx_acquire_irq(struct azx *chip, int do_disconnect)
743{
a41d1224
TI		 744 struct hdac_bus *bus = azx_bus(chip);
745
437a5a46
TI		 746 if (request_irq(chip->pci->irq, azx_interrupt,
747 chip->msi ? 0 : IRQF_SHARED,
de65360b 748 chip->card->irq_descr, chip)) {
4e76a883
TI		 749 dev_err(chip->card->dev,
750 "unable to grab IRQ %d, disabling device\n",
751 chip->pci->irq);
68e7fffc
TI		 752 if (do_disconnect)
753 snd_card_disconnect(chip->card);
754 return -1;
755 }
a41d1224 756 bus->irq = chip->pci->irq;
69e13418 757 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 758 return 0;
759}
760
b6050ef6
TI		 761/* get the current DMA position with correction on VIA chips */
762static unsigned int azx_via_get_position(struct azx *chip,
763 struct azx_dev *azx_dev)
764{
765 unsigned int link_pos, mini_pos, bound_pos;
766 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
767 unsigned int fifo_size;
768
1604eeee 769 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 770 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 771 /* Playback, no problem using link position */
772 return link_pos;
773 }
774
775 /* Capture */
776 /* For new chipset,
777 * use mod to get the DMA position just like old chipset
778 */
7833c3f8
TI		 779 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
780 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 781
782 /* azx_dev->fifo_size can't get FIFO size of in stream.
783 * Get from base address + offset.
784 */
a41d1224
TI		 785 fifo_size = readw(azx_bus(chip)->remap_addr +
786 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 787
788 if (azx_dev->insufficient) {
789 /* Link position never gather than FIFO size */
790 if (link_pos <= fifo_size)
791 return 0;
792
793 azx_dev->insufficient = 0;
794 }
795
796 if (link_pos <= fifo_size)
7833c3f8 797 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 798 else
799 mini_pos = link_pos - fifo_size;
800
801 /* Find nearest previous boudary */
7833c3f8
TI		 802 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
803 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 804 if (mod_link_pos >= fifo_size)
805 bound_pos = link_pos - mod_link_pos;
806 else if (mod_dma_pos >= mod_mini_pos)
807 bound_pos = mini_pos - mod_mini_pos;
808 else {
7833c3f8
TI		 809 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
810 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 811 bound_pos = 0;
812 }
813
814 /* Calculate real DMA position we want */
815 return bound_pos + mod_dma_pos;
816}
817
83012a7c 818#ifdef CONFIG_PM
65fcd41d
TI		 819static DEFINE_MUTEX(card_list_lock);
820static LIST_HEAD(card_list);
821
822static void azx_add_card_list(struct azx *chip)
823{
9a34af4a 824 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 825 mutex_lock(&card_list_lock);
9a34af4a 826 list_add(&hda->list, &card_list);
65fcd41d
TI		 827 mutex_unlock(&card_list_lock);
828}
829
830static void azx_del_card_list(struct azx *chip)
831{
9a34af4a 832 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 833 mutex_lock(&card_list_lock);
9a34af4a 834 list_del_init(&hda->list);
65fcd41d
TI		 835 mutex_unlock(&card_list_lock);
836}
837
838/* trigger power-save check at writing parameter */
839static int param_set_xint(const char *val, const struct kernel_param *kp)
840{
9a34af4a 841 struct hda_intel *hda;
65fcd41d 842 struct azx *chip;
65fcd41d
TI		 843 int prev = power_save;
844 int ret = param_set_int(val, kp);
845
846 if (ret || prev == power_save)
847 return ret;
848
849 mutex_lock(&card_list_lock);
9a34af4a
TI		 850 list_for_each_entry(hda, &card_list, list) {
851 chip = &hda->chip;
a41d1224 852 if (!hda->probe_continued || chip->disabled)
65fcd41d 853 continue;
a41d1224 854 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 855 }
856 mutex_unlock(&card_list_lock);
857 return 0;
858}
859#else
860#define azx_add_card_list(chip) /* NOP */
861#define azx_del_card_list(chip) /* NOP */
83012a7c 862#endif /* CONFIG_PM */
5c0b9bec 863
7ccbde57 864#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 865/*
866 * power management
867 */
68cb2b55 868static int azx_suspend(struct device *dev)
1da177e4 869{
68cb2b55 870 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 871 struct azx *chip;
872 struct hda_intel *hda;
a41d1224 873 struct hdac_bus *bus;
1da177e4 874
2d9772ef
TI		 875 if (!card)
876 return 0;
877
878 chip = card->private_data;
879 hda = container_of(chip, struct hda_intel, chip);
342e8449 880 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 881 return 0;
882
a41d1224 883 bus = azx_bus(chip);
421a1252 884 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 885 azx_clear_irq_pending(chip);
cb53c626 886 azx_stop_chip(chip);
7295b264 887 azx_enter_link_reset(chip);
a41d1224
TI		 888 if (bus->irq >= 0) {
889 free_irq(bus->irq, chip);
890 bus->irq = -1;
30b35399 891 }
a07187c9 892
68e7fffc 893 if (chip->msi)
43001c95 894 pci_disable_msi(chip->pci);
795614dd
ML		 895 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
896 && hda->need_i915_power)
98d8fc6c 897 snd_hdac_display_power(bus, false);
785d8c4b
LY		 898
899 trace_azx_suspend(chip);
1da177e4
LT		 900 return 0;
901}
902
68cb2b55 903static int azx_resume(struct device *dev)
1da177e4 904{
68cb2b55
TI		 905 struct pci_dev *pci = to_pci_dev(dev);
906 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 907 struct azx *chip;
908 struct hda_intel *hda;
909
910 if (!card)
911 return 0;
1da177e4 912
2d9772ef
TI		 913 chip = card->private_data;
914 hda = container_of(chip, struct hda_intel, chip);
342e8449 915 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 916 return 0;
917
795614dd
ML		 918 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
919 && hda->need_i915_power) {
98d8fc6c 920 snd_hdac_display_power(azx_bus(chip), true);
bb03ed21 921 snd_hdac_i915_set_bclk(azx_bus(chip));
a07187c9 922 }
68e7fffc
TI		 923 if (chip->msi)
924 if (pci_enable_msi(pci) < 0)
925 chip->msi = 0;
926 if (azx_acquire_irq(chip, 1) < 0)
30b35399 927 return -EIO;
cb53c626 928 azx_init_pci(chip);
d804ad92 929
0a673521 930 hda_intel_init_chip(chip, true);
d804ad92 931
421a1252 932 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 933
934 trace_azx_resume(chip);
1da177e4
LT		 935 return 0;
936}
b8dfc462
ML		 937#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
938
3e6db33a
XZ		 939#ifdef CONFIG_PM_SLEEP
940/* put codec down to D3 at hibernation for Intel SKL+;
941 * otherwise BIOS may still access the codec and screw up the driver
942 */
3e6db33a
XZ		 943static int azx_freeze_noirq(struct device *dev)
944{
945 struct pci_dev *pci = to_pci_dev(dev);
946
947 if (IS_SKL_PLUS(pci))
948 pci_set_power_state(pci, PCI_D3hot);
949
950 return 0;
951}
952
953static int azx_thaw_noirq(struct device *dev)
954{
955 struct pci_dev *pci = to_pci_dev(dev);
956
957 if (IS_SKL_PLUS(pci))
958 pci_set_power_state(pci, PCI_D0);
959
960 return 0;
961}
962#endif /* CONFIG_PM_SLEEP */
963
641d334b 964#ifdef CONFIG_PM
b8dfc462
ML		 965static int azx_runtime_suspend(struct device *dev)
966{
967 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 968 struct azx *chip;
969 struct hda_intel *hda;
b8dfc462 970
2d9772ef
TI		 971 if (!card)
972 return 0;
973
974 chip = card->private_data;
975 hda = container_of(chip, struct hda_intel, chip);
1618e84a 976 if (chip->disabled || hda->init_failed)
246efa4a
DA		 977 return 0;
978
364aa716 979 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 980 return 0;
981
7d4f606c
WX		 982 /* enable controller wake up event */
983 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
984 STATESTS_INT_MASK);
985
b8dfc462 986 azx_stop_chip(chip);
873ce8ad 987 azx_enter_link_reset(chip);
b8dfc462 988 azx_clear_irq_pending(chip);
795614dd
ML		 989 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
990 && hda->need_i915_power)
98d8fc6c 991 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 992
785d8c4b 993 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 994 return 0;
995}
996
997static int azx_runtime_resume(struct device *dev)
998{
999 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1000 struct azx *chip;
1001 struct hda_intel *hda;
98d8fc6c 1002 struct hdac_bus *bus;
7d4f606c
WX		 1003 struct hda_codec *codec;
1004 int status;
b8dfc462 1005
2d9772ef
TI		 1006 if (!card)
1007 return 0;
1008
1009 chip = card->private_data;
1010 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1011 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1012 return 0;
1013
364aa716 1014 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1015 return 0;
1016
033ea349
DH		 1017 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1018 bus = azx_bus(chip);
1019 if (hda->need_i915_power) {
1020 snd_hdac_display_power(bus, true);
bb03ed21 1021 snd_hdac_i915_set_bclk(bus);
033ea349
DH		 1022 } else {
1023 /* toggle codec wakeup bit for STATESTS read */
1024 snd_hdac_set_codec_wakeup(bus, true);
1025 snd_hdac_set_codec_wakeup(bus, false);
1026 }
a07187c9 1027 }
7d4f606c
WX		 1028
1029 /* Read STATESTS before controller reset */
1030 status = azx_readw(chip, STATESTS);
1031
b8dfc462 1032 azx_init_pci(chip);
0a673521 1033 hda_intel_init_chip(chip, true);
7d4f606c 1034
a41d1224
TI		 1035 if (status) {
1036 list_for_each_codec(codec, &chip->bus)
7d4f606c 1037 if (status & (1 << codec->addr))
2f35c630
TI		 1038 schedule_delayed_work(&codec->jackpoll_work,
1039 codec->jackpoll_interval);
7d4f606c
WX		 1040 }
1041
1042 /* disable controller Wake Up event*/
1043 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1044 ~STATESTS_INT_MASK);
1045
785d8c4b 1046 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1047 return 0;
1048}
6eb827d2
TI		 1049
1050static int azx_runtime_idle(struct device *dev)
1051{
1052 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1053 struct azx *chip;
1054 struct hda_intel *hda;
1055
1056 if (!card)
1057 return 0;
6eb827d2 1058
2d9772ef
TI		 1059 chip = card->private_data;
1060 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1061 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1062 return 0;
1063
55ed9cd1 1064 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1065 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1066 return -EBUSY;
1067
1068 return 0;
1069}
1070
b8dfc462
ML		 1071static const struct dev_pm_ops azx_pm = {
1072 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1073#ifdef CONFIG_PM_SLEEP
1074 .freeze_noirq = azx_freeze_noirq,
1075 .thaw_noirq = azx_thaw_noirq,
1076#endif
6eb827d2 1077 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1078};
1079
68cb2b55
TI		 1080#define AZX_PM_OPS &azx_pm
1081#else
68cb2b55 1082#define AZX_PM_OPS NULL
b8dfc462 1083#endif /* CONFIG_PM */
1da177e4
LT		 1084
1085
48c8b0eb 1086static int azx_probe_continue(struct azx *chip);
a82d51ed 1087
8393ec4a 1088#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1089static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1090
a82d51ed
TI		 1091static void azx_vs_set_state(struct pci_dev *pci,
1092 enum vga_switcheroo_state state)
1093{
1094 struct snd_card *card = pci_get_drvdata(pci);
1095 struct azx *chip = card->private_data;
9a34af4a 1096 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1097 bool disabled;
1098
9a34af4a
TI		 1099 wait_for_completion(&hda->probe_wait);
1100 if (hda->init_failed)
a82d51ed
TI		 1101 return;
1102
1103 disabled = (state == VGA_SWITCHEROO_OFF);
1104 if (chip->disabled == disabled)
1105 return;
1106
a41d1224 1107 if (!hda->probe_continued) {
a82d51ed
TI		 1108 chip->disabled = disabled;
1109 if (!disabled) {
4e76a883
TI		 1110 dev_info(chip->card->dev,
1111 "Start delayed initialization\n");
5c90680e 1112 if (azx_probe_continue(chip) < 0) {
4e76a883 1113 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1114 hda->init_failed = true;
a82d51ed
TI		 1115 }
1116 }
1117 } else {
2b760d88 1118 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1119 disabled ? "Disabling" : "Enabling");
a82d51ed 1120 if (disabled) {
8928756d
DR		 1121 pm_runtime_put_sync_suspend(card->dev);
1122 azx_suspend(card->dev);
2b760d88 1123 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1124 * however we have no ACPI handle, so pci/acpi can't put us there,
1125 * put ourselves there */
1126 pci->current_state = PCI_D3cold;
a82d51ed 1127 chip->disabled = true;
a41d1224 1128 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1129 dev_warn(chip->card->dev,
1130 "Cannot lock devices!\n");
a82d51ed 1131 } else {
a41d1224 1132 snd_hda_unlock_devices(&chip->bus);
8928756d 1133 pm_runtime_get_noresume(card->dev);
a82d51ed 1134 chip->disabled = false;
8928756d 1135 azx_resume(card->dev);
a82d51ed
TI		 1136 }
1137 }
1138}
1139
1140static bool azx_vs_can_switch(struct pci_dev *pci)
1141{
1142 struct snd_card *card = pci_get_drvdata(pci);
1143 struct azx *chip = card->private_data;
9a34af4a 1144 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1145
9a34af4a
TI		 1146 wait_for_completion(&hda->probe_wait);
1147 if (hda->init_failed)
a82d51ed 1148 return false;
a41d1224 1149 if (chip->disabled || !hda->probe_continued)
a82d51ed 1150 return true;
a41d1224 1151 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1152 return false;
a41d1224 1153 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1154 return true;
1155}
1156
e23e7a14 1157static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1158{
9a34af4a 1159 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1160 struct pci_dev *p = get_bound_vga(chip->pci);
1161 if (p) {
4e76a883 1162 dev_info(chip->card->dev,
2b760d88 1163 "Handle vga_switcheroo audio client\n");
9a34af4a 1164 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1165 pci_dev_put(p);
1166 }
1167}
1168
1169static const struct vga_switcheroo_client_ops azx_vs_ops = {
1170 .set_gpu_state = azx_vs_set_state,
1171 .can_switch = azx_vs_can_switch,
1172};
1173
e23e7a14 1174static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1175{
9a34af4a 1176 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1177 int err;
1178
9a34af4a 1179 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1180 return 0;
1181 /* FIXME: currently only handling DIS controller
1182 * is there any machine with two switchable HDMI audio controllers?
1183 */
128960a9 1184 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1185 VGA_SWITCHEROO_DIS);
128960a9
TI		 1186 if (err < 0)
1187 return err;
9a34af4a 1188 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1189
1190 /* register as an optimus hdmi audio power domain */
8928756d 1191 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1192 &hda->hdmi_pm_domain);
128960a9 1193 return 0;
a82d51ed
TI		 1194}
1195#else
1196#define init_vga_switcheroo(chip) /* NOP */
1197#define register_vga_switcheroo(chip) 0
8393ec4a 1198#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1199#endif /* SUPPORT_VGA_SWITCHER */
1200
1da177e4
LT		 1201/*
1202 * destructor
1203 */
a98f90fd 1204static int azx_free(struct azx *chip)
1da177e4 1205{
c67e2228 1206 struct pci_dev *pci = chip->pci;
a07187c9 1207 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1208 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1209
364aa716 1210 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1211 pm_runtime_get_noresume(&pci->dev);
1212
65fcd41d
TI		 1213 azx_del_card_list(chip);
1214
9a34af4a
TI		 1215 hda->init_failed = 1; /* to be sure */
1216 complete_all(&hda->probe_wait);
f4c482a4 1217
9a34af4a 1218 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1219 if (chip->disabled && hda->probe_continued)
1220 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1221 if (hda->vga_switcheroo_registered) {
128960a9 1222 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1223 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1224 }
a82d51ed
TI		 1225 }
1226
a41d1224 1227 if (bus->chip_init) {
9ad593f6 1228 azx_clear_irq_pending(chip);
7833c3f8 1229 azx_stop_all_streams(chip);
cb53c626 1230 azx_stop_chip(chip);
1da177e4
LT		 1231 }
1232
a41d1224
TI		 1233 if (bus->irq >= 0)
1234 free_irq(bus->irq, (void*)chip);
68e7fffc 1235 if (chip->msi)
30b35399 1236 pci_disable_msi(chip->pci);
a41d1224 1237 iounmap(bus->remap_addr);
1da177e4 1238
67908994 1239 azx_free_stream_pages(chip);
a41d1224
TI		 1240 azx_free_streams(chip);
1241 snd_hdac_bus_exit(bus);
1242
a82d51ed
TI		 1243 if (chip->region_requested)
1244 pci_release_regions(chip->pci);
a41d1224 1245
1da177e4 1246 pci_disable_device(chip->pci);
4918cdab 1247#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1248 release_firmware(chip->fw);
4918cdab 1249#endif
98d8fc6c 1250
99a2008d 1251 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1252 if (hda->need_i915_power)
98d8fc6c
ML		 1253 snd_hdac_display_power(bus, false);
1254 snd_hdac_i915_exit(bus);
99a2008d 1255 }
a07187c9 1256 kfree(hda);
1da177e4
LT		 1257
1258 return 0;
1259}
1260
a41d1224
TI		 1261static int azx_dev_disconnect(struct snd_device *device)
1262{
1263 struct azx *chip = device->device_data;
1264
1265 chip->bus.shutdown = 1;
1266 return 0;
1267}
1268
a98f90fd 1269static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1270{
1271 return azx_free(device->device_data);
1272}
1273
8393ec4a 1274#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1275/*
2b760d88 1276 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1277 */
e23e7a14 1278static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1279{
1280 struct pci_dev *p;
1281
1282 /* check only discrete GPU */
1283 switch (pci->vendor) {
1284 case PCI_VENDOR_ID_ATI:
1285 case PCI_VENDOR_ID_AMD:
1286 case PCI_VENDOR_ID_NVIDIA:
1287 if (pci->devfn == 1) {
1288 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1289 pci->bus->number, 0);
1290 if (p) {
1291 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1292 return p;
1293 pci_dev_put(p);
1294 }
1295 }
1296 break;
1297 }
1298 return NULL;
1299}
1300
e23e7a14 1301static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1302{
1303 bool vga_inactive = false;
1304 struct pci_dev *p = get_bound_vga(pci);
1305
1306 if (p) {
12b78a7f 1307 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1308 vga_inactive = true;
1309 pci_dev_put(p);
1310 }
1311 return vga_inactive;
1312}
8393ec4a 1313#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1314
3372a153
TI		 1315/*
1316 * white/black-listing for position_fix
1317 */
e23e7a14 1318static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1319 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1320 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1321 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1322 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1323 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1324 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1325 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1326 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1327 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1328 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1329 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1330 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1331 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1332 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1333 {}
1334};
1335
e23e7a14 1336static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1337{
1338 const struct snd_pci_quirk *q;
1339
c673ba1c 1340 switch (fix) {
1dac6695 1341 case POS_FIX_AUTO:
c673ba1c
TI		 1342 case POS_FIX_LPIB:
1343 case POS_FIX_POSBUF:
4cb36310 1344 case POS_FIX_VIACOMBO:
a6f2fd55 1345 case POS_FIX_COMBO:
c673ba1c
TI		 1346 return fix;
1347 }
1348
c673ba1c
TI		 1349 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1350 if (q) {
4e76a883
TI		 1351 dev_info(chip->card->dev,
1352 "position_fix set to %d for device %04x:%04x\n",
1353 q->value, q->subvendor, q->subdevice);
c673ba1c 1354 return q->value;
3372a153 1355 }
bdd9ef24
DH		 1356
1357 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1358 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1359 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1360 return POS_FIX_VIACOMBO;
9477c58e
TI		 1361 }
1362 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1363 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1364 return POS_FIX_LPIB;
bdd9ef24 1365 }
c673ba1c 1366 return POS_FIX_AUTO;
3372a153
TI		 1367}
1368
b6050ef6
TI		 1369static void assign_position_fix(struct azx *chip, int fix)
1370{
1371 static azx_get_pos_callback_t callbacks[] = {
1372 [POS_FIX_AUTO] = NULL,
1373 [POS_FIX_LPIB] = azx_get_pos_lpib,
1374 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1375 [POS_FIX_VIACOMBO] = azx_via_get_position,
1376 [POS_FIX_COMBO] = azx_get_pos_lpib,
1377 };
1378
1379 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1380
1381 /* combo mode uses LPIB only for playback */
1382 if (fix == POS_FIX_COMBO)
1383 chip->get_position[1] = NULL;
1384
1385 if (fix == POS_FIX_POSBUF &&
1386 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1387 chip->get_delay[0] = chip->get_delay[1] =
1388 azx_get_delay_from_lpib;
1389 }
1390
1391}
1392
669ba27a
TI		 1393/*
1394 * black-lists for probe_mask
1395 */
e23e7a14 1396static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1397 /* Thinkpad often breaks the controller communication when accessing
1398 * to the non-working (or non-existing) modem codec slot.
1399 */
1400 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1401 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1402 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1403 /* broken BIOS */
1404 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1405 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1406 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1407 /* forced codec slots */
93574844 1408 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1409 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1410 /* WinFast VP200 H (Teradici) user reported broken communication */
1411 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1412 {}
1413};
1414
f1eaaeec
TI		 1415#define AZX_FORCE_CODEC_MASK 0x100
1416
e23e7a14 1417static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1418{
1419 const struct snd_pci_quirk *q;
1420
f1eaaeec
TI		 1421 chip->codec_probe_mask = probe_mask[dev];
1422 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1423 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1424 if (q) {
4e76a883
TI		 1425 dev_info(chip->card->dev,
1426 "probe_mask set to 0x%x for device %04x:%04x\n",
1427 q->value, q->subvendor, q->subdevice);
f1eaaeec 1428 chip->codec_probe_mask = q->value;
669ba27a
TI		 1429 }
1430 }
f1eaaeec
TI		 1431
1432 /* check forced option */
1433 if (chip->codec_probe_mask != -1 &&
1434 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1435 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1436 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1437 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1438 }
669ba27a
TI		 1439}
1440
4d8e22e0 1441/*
71623855 1442 * white/black-list for enable_msi
4d8e22e0 1443 */
e23e7a14 1444static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1445 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1446 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1447 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1448 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1449 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1450 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1451 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1452 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1453 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1454 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1455 {}
1456};
1457
e23e7a14 1458static void check_msi(struct azx *chip)
4d8e22e0
TI		 1459{
1460 const struct snd_pci_quirk *q;
1461
71623855
TI		 1462 if (enable_msi >= 0) {
1463 chip->msi = !!enable_msi;
4d8e22e0 1464 return;
71623855
TI		 1465 }
1466 chip->msi = 1; /* enable MSI as default */
1467 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1468 if (q) {
4e76a883
TI		 1469 dev_info(chip->card->dev,
1470 "msi for device %04x:%04x set to %d\n",
1471 q->subvendor, q->subdevice, q->value);
4d8e22e0 1472 chip->msi = q->value;
80c43ed7
TI		 1473 return;
1474 }
1475
1476 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1477 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1478 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1479 chip->msi = 0;
4d8e22e0
TI		 1480 }
1481}
1482
a1585d76 1483/* check the snoop mode availability */
e23e7a14 1484static void azx_check_snoop_available(struct azx *chip)
a1585d76 1485{
7c732015 1486 int snoop = hda_snoop;
a1585d76 1487
7c732015
TI		 1488 if (snoop >= 0) {
1489 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1490 snoop ? "snoop" : "non-snoop");
1491 chip->snoop = snoop;
1492 return;
1493 }
1494
1495 snoop = true;
37e661ee
TI		 1496 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1497 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1498 /* force to non-snoop mode for a new VIA controller
1499 * when BIOS is set
1500 */
7c732015
TI		 1501 u8 val;
1502 pci_read_config_byte(chip->pci, 0x42, &val);
1503 if (!(val & 0x80) && chip->pci->revision == 0x30)
1504 snoop = false;
a1585d76
TI		 1505 }
1506
37e661ee
TI		 1507 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1508 snoop = false;
1509
7c732015
TI		 1510 chip->snoop = snoop;
1511 if (!snoop)
1512 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1513}
669ba27a 1514
99a2008d
WX		 1515static void azx_probe_work(struct work_struct *work)
1516{
9a34af4a
TI		 1517 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1518 azx_probe_continue(&hda->chip);
99a2008d 1519}
99a2008d 1520
4f0189be
TI		 1521static int default_bdl_pos_adj(struct azx *chip)
1522{
2cf721db
TI		 1523 /* some exceptions: Atoms seem problematic with value 1 */
1524 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1525 switch (chip->pci->device) {
1526 case 0x0f04: /* Baytrail */
1527 case 0x2284: /* Braswell */
1528 return 32;
1529 }
1530 }
1531
4f0189be
TI		 1532 switch (chip->driver_type) {
1533 case AZX_DRIVER_ICH:
1534 case AZX_DRIVER_PCH:
1535 return 1;
1536 default:
1537 return 32;
1538 }
1539}
1540
1da177e4
LT		 1541/*
1542 * constructor
1543 */
a43ff5ba
TI		 1544static const struct hdac_io_ops pci_hda_io_ops;
1545static const struct hda_controller_ops pci_hda_ops;
1546
e23e7a14
BP		 1547static int azx_create(struct snd_card *card, struct pci_dev *pci,
1548 int dev, unsigned int driver_caps,
1549 struct azx **rchip)
1da177e4 1550{
a98f90fd 1551 static struct snd_device_ops ops = {
a41d1224 1552 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1553 .dev_free = azx_dev_free,
1554 };
a07187c9 1555 struct hda_intel *hda;
a82d51ed
TI		 1556 struct azx *chip;
1557 int err;
1da177e4
LT		 1558
1559 *rchip = NULL;
bcd72003 1560
927fc866
PM		 1561 err = pci_enable_device(pci);
1562 if (err < 0)
1da177e4
LT		 1563 return err;
1564
a07187c9
ML		 1565 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1566 if (!hda) {
1da177e4
LT		 1567 pci_disable_device(pci);
1568 return -ENOMEM;
1569 }
1570
a07187c9 1571 chip = &hda->chip;
62932df8 1572 mutex_init(&chip->open_mutex);
1da177e4
LT		 1573 chip->card = card;
1574 chip->pci = pci;
a43ff5ba 1575 chip->ops = &pci_hda_ops;
9477c58e
TI		 1576 chip->driver_caps = driver_caps;
1577 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1578 check_msi(chip);
555e219f 1579 chip->dev_index = dev;
749ee287 1580 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1581 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1582 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1583 INIT_LIST_HEAD(&hda->list);
a82d51ed 1584 init_vga_switcheroo(chip);
9a34af4a 1585 init_completion(&hda->probe_wait);
1da177e4 1586
b6050ef6 1587 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1588
5aba4f8e 1589 check_probe_mask(chip, dev);
3372a153 1590
27346166 1591 chip->single_cmd = single_cmd;
a1585d76 1592 azx_check_snoop_available(chip);
c74db86b 1593
4f0189be
TI		 1594 if (bdl_pos_adj[dev] < 0)
1595 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1596 else
1597 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1598
a41d1224
TI		 1599 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1600 if (err < 0) {
1601 kfree(hda);
1602 pci_disable_device(pci);
1603 return err;
1604 }
1605
7d9a1808
TI		 1606 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1607 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1608 chip->bus.needs_damn_long_delay = 1;
1609 }
1610
a82d51ed
TI		 1611 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1612 if (err < 0) {
4e76a883 1613 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1614 azx_free(chip);
1615 return err;
1616 }
1617
99a2008d 1618 /* continue probing in work context as may trigger request module */
9a34af4a 1619 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1620
a82d51ed 1621 *rchip = chip;
99a2008d 1622
a82d51ed
TI		 1623 return 0;
1624}
1625
48c8b0eb 1626static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1627{
1628 int dev = chip->dev_index;
1629 struct pci_dev *pci = chip->pci;
1630 struct snd_card *card = chip->card;
a41d1224 1631 struct hdac_bus *bus = azx_bus(chip);
67908994 1632 int err;
a82d51ed 1633 unsigned short gcap;
413cbf46 1634 unsigned int dma_bits = 64;
a82d51ed 1635
07e4ca50
TI		 1636#if BITS_PER_LONG != 64
1637 /* Fix up base address on ULI M5461 */
1638 if (chip->driver_type == AZX_DRIVER_ULI) {
1639 u16 tmp3;
1640 pci_read_config_word(pci, 0x40, &tmp3);
1641 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1642 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1643 }
1644#endif
1645
927fc866 1646 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1647 if (err < 0)
1da177e4 1648 return err;
a82d51ed 1649 chip->region_requested = 1;
1da177e4 1650
a41d1224
TI		 1651 bus->addr = pci_resource_start(pci, 0);
1652 bus->remap_addr = pci_ioremap_bar(pci, 0);
1653 if (bus->remap_addr == NULL) {
4e76a883 1654 dev_err(card->dev, "ioremap error\n");
a82d51ed 1655 return -ENXIO;
1da177e4
LT		 1656 }
1657
db79afa1
BH		 1658 if (chip->msi) {
1659 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1660 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1661 pci->no_64bit_msi = true;
1662 }
68e7fffc
TI		 1663 if (pci_enable_msi(pci) < 0)
1664 chip->msi = 0;
db79afa1 1665 }
7376d013 1666
a82d51ed
TI		 1667 if (azx_acquire_irq(chip, 0) < 0)
1668 return -EBUSY;
1da177e4
LT		 1669
1670 pci_set_master(pci);
a41d1224 1671 synchronize_irq(bus->irq);
1da177e4 1672
bcd72003 1673 gcap = azx_readw(chip, GCAP);
4e76a883 1674 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1675
413cbf46
TI		 1676 /* AMD devices support 40 or 48bit DMA, take the safe one */
1677 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1678 dma_bits = 40;
1679
dc4c2e6b 1680 /* disable SB600 64bit support for safety */
9477c58e 1681 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1682 struct pci_dev *p_smbus;
413cbf46 1683 dma_bits = 40;
dc4c2e6b
AB		 1684 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1685 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1686 NULL);
1687 if (p_smbus) {
1688 if (p_smbus->revision < 0x30)
fb1d8ac2 1689 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1690 pci_dev_put(p_smbus);
1691 }
1692 }
09240cf4 1693
9477c58e
TI		 1694 /* disable 64bit DMA address on some devices */
1695 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1696 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1697 gcap &= ~AZX_GCAP_64OK;
9477c58e 1698 }
396087ea 1699
2ae66c26 1700 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1701 if (align_buffer_size >= 0)
1702 chip->align_buffer_size = !!align_buffer_size;
1703 else {
103884a3 1704 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1705 chip->align_buffer_size = 0;
7bfe059e
TI		 1706 else
1707 chip->align_buffer_size = 1;
1708 }
2ae66c26 1709
cf7aaca8 1710 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1711 if (!(gcap & AZX_GCAP_64OK))
1712 dma_bits = 32;
412b979c
QL		 1713 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1714 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1715 } else {
412b979c
QL		 1716 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1717 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1718 }
cf7aaca8 1719
8b6ed8e7
TI		 1720 /* read number of streams from GCAP register instead of using
1721 * hardcoded value
1722 */
1723 chip->capture_streams = (gcap >> 8) & 0x0f;
1724 chip->playback_streams = (gcap >> 12) & 0x0f;
1725 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1726 /* gcap didn't give any info, switching to old method */
1727
1728 switch (chip->driver_type) {
1729 case AZX_DRIVER_ULI:
1730 chip->playback_streams = ULI_NUM_PLAYBACK;
1731 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1732 break;
1733 case AZX_DRIVER_ATIHDMI:
1815b34a 1734 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1735 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1736 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1737 break;
c4da29ca 1738 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1739 default:
1740 chip->playback_streams = ICH6_NUM_PLAYBACK;
1741 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1742 break;
1743 }
07e4ca50 1744 }
8b6ed8e7
TI		 1745 chip->capture_index_offset = 0;
1746 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1747 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1748
a41d1224
TI		 1749 /* initialize streams */
1750 err = azx_init_streams(chip);
81740861 1751 if (err < 0)
a82d51ed 1752 return err;
1da177e4 1753
a41d1224
TI		 1754 err = azx_alloc_stream_pages(chip);
1755 if (err < 0)
1756 return err;
1da177e4
LT		 1757
1758 /* initialize chip */
cb53c626 1759 azx_init_pci(chip);
e4d9e513 1760
bb03ed21
TI		 1761 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1762 snd_hdac_i915_set_bclk(bus);
e4d9e513 1763
0a673521 1764 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1765
1766 /* codec detection */
a41d1224 1767 if (!azx_bus(chip)->codec_mask) {
4e76a883 1768 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1769 return -ENODEV;
1da177e4
LT		 1770 }
1771
07e4ca50 1772 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1773 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1774 sizeof(card->shortname));
1775 snprintf(card->longname, sizeof(card->longname),
1776 "%s at 0x%lx irq %i",
a41d1224 1777 card->shortname, bus->addr, bus->irq);
07e4ca50 1778
1da177e4 1779 return 0;
1da177e4
LT		 1780}
1781
97c6a3d1 1782#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1783/* callback from request_firmware_nowait() */
1784static void azx_firmware_cb(const struct firmware *fw, void *context)
1785{
1786 struct snd_card *card = context;
1787 struct azx *chip = card->private_data;
1788 struct pci_dev *pci = chip->pci;
1789
1790 if (!fw) {
4e76a883 1791 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1792 goto error;
1793 }
1794
1795 chip->fw = fw;
1796 if (!chip->disabled) {
1797 /* continue probing */
1798 if (azx_probe_continue(chip))
1799 goto error;
1800 }
1801 return; /* OK */
1802
1803 error:
1804 snd_card_free(card);
1805 pci_set_drvdata(pci, NULL);
1806}
97c6a3d1 1807#endif
5cb543db 1808
40830813
DR		 1809/*
1810 * HDA controller ops.
1811 */
1812
1813/* PCI register access. */
db291e36 1814static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1815{
1816 writel(value, addr);
1817}
1818
db291e36 1819static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1820{
1821 return readl(addr);
1822}
1823
db291e36 1824static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1825{
1826 writew(value, addr);
1827}
1828
db291e36 1829static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1830{
1831 return readw(addr);
1832}
1833
db291e36 1834static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1835{
1836 writeb(value, addr);
1837}
1838
db291e36 1839static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1840{
1841 return readb(addr);
1842}
1843
f46ea609
DR		 1844static int disable_msi_reset_irq(struct azx *chip)
1845{
a41d1224 1846 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1847 int err;
1848
a41d1224
TI		 1849 free_irq(bus->irq, chip);
1850 bus->irq = -1;
f46ea609
DR		 1851 pci_disable_msi(chip->pci);
1852 chip->msi = 0;
1853 err = azx_acquire_irq(chip, 1);
1854 if (err < 0)
1855 return err;
1856
1857 return 0;
1858}
1859
b419b35b 1860/* DMA page allocation helpers. */
a43ff5ba 1861static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1862 int type,
1863 size_t size,
1864 struct snd_dma_buffer *buf)
1865{
a41d1224 1866 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1867 int err;
1868
1869 err = snd_dma_alloc_pages(type,
a43ff5ba 1870 bus->dev,
b419b35b
DR		 1871 size, buf);
1872 if (err < 0)
1873 return err;
1874 mark_pages_wc(chip, buf, true);
1875 return 0;
1876}
1877
a43ff5ba 1878static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1879{
a41d1224 1880 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1881
b419b35b
DR		 1882 mark_pages_wc(chip, buf, false);
1883 snd_dma_free_pages(buf);
1884}
1885
1886static int substream_alloc_pages(struct azx *chip,
1887 struct snd_pcm_substream *substream,
1888 size_t size)
1889{
1890 struct azx_dev *azx_dev = get_azx_dev(substream);
1891 int ret;
1892
1893 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1894 ret = snd_pcm_lib_malloc_pages(substream, size);
1895 if (ret < 0)
1896 return ret;
1897 mark_runtime_wc(chip, azx_dev, substream, true);
1898 return 0;
1899}
1900
1901static int substream_free_pages(struct azx *chip,
1902 struct snd_pcm_substream *substream)
1903{
1904 struct azx_dev *azx_dev = get_azx_dev(substream);
1905 mark_runtime_wc(chip, azx_dev, substream, false);
1906 return snd_pcm_lib_free_pages(substream);
1907}
1908
8769b278
DR		 1909static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1910 struct vm_area_struct *area)
1911{
1912#ifdef CONFIG_X86
1913 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1914 struct azx *chip = apcm->chip;
3b70bdba 1915 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1916 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1917#endif
1918}
1919
a43ff5ba 1920static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1921 .reg_writel = pci_azx_writel,
1922 .reg_readl = pci_azx_readl,
1923 .reg_writew = pci_azx_writew,
1924 .reg_readw = pci_azx_readw,
1925 .reg_writeb = pci_azx_writeb,
1926 .reg_readb = pci_azx_readb,
b419b35b
DR		 1927 .dma_alloc_pages = dma_alloc_pages,
1928 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1929};
1930
1931static const struct hda_controller_ops pci_hda_ops = {
1932 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1933 .substream_alloc_pages = substream_alloc_pages,
1934 .substream_free_pages = substream_free_pages,
8769b278 1935 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1936 .position_check = azx_position_check,
17eccb27 1937 .link_power = azx_intel_link_power,
40830813
DR		 1938};
1939
e23e7a14
BP		 1940static int azx_probe(struct pci_dev *pci,
1941 const struct pci_device_id *pci_id)
1da177e4 1942{
5aba4f8e 1943 static int dev;
a98f90fd 1944 struct snd_card *card;
9a34af4a 1945 struct hda_intel *hda;
a98f90fd 1946 struct azx *chip;
aad730d0 1947 bool schedule_probe;
927fc866 1948 int err;
1da177e4 1949
5aba4f8e
TI		 1950 if (dev >= SNDRV_CARDS)
1951 return -ENODEV;
1952 if (!enable[dev]) {
1953 dev++;
1954 return -ENOENT;
1955 }
1956
60c5772b
TI		 1957 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1958 0, &card);
e58de7ba 1959 if (err < 0) {
4e76a883 1960 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1961 return err;
1da177e4
LT		 1962 }
1963
a43ff5ba 1964 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1965 if (err < 0)
1966 goto out_free;
421a1252 1967 card->private_data = chip;
9a34af4a 1968 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1969
1970 pci_set_drvdata(pci, card);
1971
1972 err = register_vga_switcheroo(chip);
1973 if (err < 0) {
2b760d88 1974 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 1975 goto out_free;
1976 }
1977
1978 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1979 dev_info(card->dev, "VGA controller is disabled\n");
1980 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1981 chip->disabled = true;
1982 }
1983
aad730d0 1984 schedule_probe = !chip->disabled;
1da177e4 1985
4918cdab
TI		 1986#ifdef CONFIG_SND_HDA_PATCH_LOADER
1987 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1988 dev_info(card->dev, "Applying patch firmware '%s'\n",
1989 patch[dev]);
5cb543db
TI		 1990 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1991 &pci->dev, GFP_KERNEL, card,
1992 azx_firmware_cb);
4918cdab
TI		 1993 if (err < 0)
1994 goto out_free;
aad730d0 1995 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1996 }
1997#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1998
aad730d0 1999#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2000 if (CONTROLLER_IN_GPU(pci))
2001 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2002#endif
99a2008d 2003
aad730d0 2004 if (schedule_probe)
9a34af4a 2005 schedule_work(&hda->probe_work);
a82d51ed 2006
a82d51ed 2007 dev++;
88d071fc 2008 if (chip->disabled)
9a34af4a 2009 complete_all(&hda->probe_wait);
a82d51ed
TI		 2010 return 0;
2011
2012out_free:
2013 snd_card_free(card);
2014 return err;
2015}
2016
e62a42ae
DR		 2017/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2018static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2019 [AZX_DRIVER_NVIDIA] = 8,
2020 [AZX_DRIVER_TERA] = 1,
2021};
2022
48c8b0eb 2023static int azx_probe_continue(struct azx *chip)
a82d51ed 2024{
9a34af4a 2025 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2026 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2027 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2028 int dev = chip->dev_index;
2029 int err;
2030
a41d1224 2031 hda->probe_continued = 1;
795614dd
ML		 2032
2033 /* Request display power well for the HDA controller or codec. For
2034 * Haswell/Broadwell, both the display HDA controller and codec need
2035 * this power. For other platforms, like Baytrail/Braswell, only the
2036 * display codec needs the power and it can be released after probe.
2037 */
99a2008d 2038 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2039 /* HSW/BDW controllers need this power */
2040 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2041 hda->need_i915_power = 1;
2042
98d8fc6c 2043 err = snd_hdac_i915_init(bus);
535115b5
TI		 2044 if (err < 0) {
2045 /* if the controller is bound only with HDMI/DP
2046 * (for HSW and BDW), we need to abort the probe;
2047 * for other chips, still continue probing as other
2048 * codecs can be on the same link.
2049 */
bed2e98e
TI		 2050 if (CONTROLLER_IN_GPU(pci)) {
2051 dev_err(chip->card->dev,
2052 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2053 goto out_free;
bed2e98e 2054 } else
535115b5
TI		 2055 goto skip_i915;
2056 }
795614dd 2057
98d8fc6c 2058 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2059 if (err < 0) {
2060 dev_err(chip->card->dev,
2061 "Cannot turn on display power on i915\n");
795614dd 2062 goto i915_power_fail;
74b0c2d7 2063 }
99a2008d
WX		 2064 }
2065
bf06848b 2066 skip_i915:
5c90680e
TI		 2067 err = azx_first_init(chip);
2068 if (err < 0)
2069 goto out_free;
2070
2dca0bba
JK		 2071#ifdef CONFIG_SND_HDA_INPUT_BEEP
2072 chip->beep_mode = beep_mode[dev];
2073#endif
2074
1da177e4 2075 /* create codec instances */
96d2bd6e 2076 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2077 if (err < 0)
2078 goto out_free;
96d2bd6e 2079
4ea6fbc8 2080#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2081 if (chip->fw) {
a41d1224 2082 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2083 chip->fw->data);
4ea6fbc8
TI		 2084 if (err < 0)
2085 goto out_free;
e39ae856 2086#ifndef CONFIG_PM
4918cdab
TI		 2087 release_firmware(chip->fw); /* no longer needed */
2088 chip->fw = NULL;
e39ae856 2089#endif
4ea6fbc8
TI		 2090 }
2091#endif
10e77dda 2092 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2093 err = azx_codec_configure(chip);
2094 if (err < 0)
2095 goto out_free;
2096 }
1da177e4 2097
a82d51ed 2098 err = snd_card_register(chip->card);
41dda0fd
WF		 2099 if (err < 0)
2100 goto out_free;
1da177e4 2101
cb53c626 2102 chip->running = 1;
65fcd41d 2103 azx_add_card_list(chip);
a41d1224 2104 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2105 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2106 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2107
41dda0fd 2108out_free:
795614dd
ML		 2109 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2110 && !hda->need_i915_power)
98d8fc6c 2111 snd_hdac_display_power(bus, false);
795614dd
ML		 2112
2113i915_power_fail:
88d071fc 2114 if (err < 0)
9a34af4a
TI		 2115 hda->init_failed = 1;
2116 complete_all(&hda->probe_wait);
41dda0fd 2117 return err;
1da177e4
LT		 2118}
2119
e23e7a14 2120static void azx_remove(struct pci_dev *pci)
1da177e4 2121{
9121947d 2122 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2123 struct azx *chip;
2124 struct hda_intel *hda;
2125
2126 if (card) {
0b8c8219 2127 /* cancel the pending probing work */
991f86d7
TI		 2128 chip = card->private_data;
2129 hda = container_of(chip, struct hda_intel, chip);
0b8c8219 2130 cancel_work_sync(&hda->probe_work);
b8dfc462 2131
9121947d 2132 snd_card_free(card);
991f86d7 2133 }
1da177e4
LT		 2134}
2135
b2a0bafa
TI		 2136static void azx_shutdown(struct pci_dev *pci)
2137{
2138 struct snd_card *card = pci_get_drvdata(pci);
2139 struct azx *chip;
2140
2141 if (!card)
2142 return;
2143 chip = card->private_data;
2144 if (chip && chip->running)
2145 azx_stop_chip(chip);
2146}
2147
1da177e4 2148/* PCI IDs */
6f51f6cf 2149static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2150 /* CPT */
9477c58e 2151 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2152 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2153 /* PBG */
9477c58e 2154 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2155 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2156 /* Panther Point */
9477c58e 2157 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2158 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2159 /* Lynx Point */
2160 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2161 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2162 /* 9 Series */
2163 { PCI_DEVICE(0x8086, 0x8ca0),
2164 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2165 /* Wellsburg */
2166 { PCI_DEVICE(0x8086, 0x8d20),
2167 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2168 { PCI_DEVICE(0x8086, 0x8d21),
2169 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2170 /* Lewisburg */
2171 { PCI_DEVICE(0x8086, 0xa1f0),
2172 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2173 { PCI_DEVICE(0x8086, 0xa270),
2174 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2175 /* Lynx Point-LP */
2176 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2177 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2178 /* Lynx Point-LP */
2179 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2180 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2181 /* Wildcat Point-LP */
2182 { PCI_DEVICE(0x8086, 0x9ca0),
2183 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2184 /* Sunrise Point */
2185 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2186 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2187 /* Sunrise Point-LP */
2188 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2190 /* Kabylake */
2191 { PCI_DEVICE(0x8086, 0xa171),
2192 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2193 /* Kabylake-LP */
2194 { PCI_DEVICE(0x8086, 0x9d71),
2195 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2196 /* Kabylake-H */
2197 { PCI_DEVICE(0x8086, 0xa2f0),
2198 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2199 /* Broxton-P(Apollolake) */
2200 { PCI_DEVICE(0x8086, 0x5a98),
2201 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2202 /* Broxton-T */
2203 { PCI_DEVICE(0x8086, 0x1a98),
2204 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2205 /* Haswell */
4a7c516b 2206 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2207 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2208 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2209 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2210 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2211 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2212 /* Broadwell */
2213 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2214 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2215 /* 5 Series/3400 */
2216 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2217 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2218 /* Poulsbo */
9477c58e 2219 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2220 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2221 /* Oaktrail */
09904b95 2222 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2223 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2224 /* BayTrail */
2225 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2226 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2227 /* Braswell */
2228 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2229 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2230 /* ICH6 */
8b0bd226 2231 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2232 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2233 /* ICH7 */
8b0bd226 2234 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2235 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2236 /* ESB2 */
8b0bd226 2237 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2238 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2239 /* ICH8 */
8b0bd226 2240 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2241 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2242 /* ICH9 */
8b0bd226 2243 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2244 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2245 /* ICH9 */
8b0bd226 2246 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2247 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2248 /* ICH10 */
8b0bd226 2249 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2250 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2251 /* ICH10 */
8b0bd226 2252 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2253 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2254 /* Generic Intel */
2255 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2256 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2257 .class_mask = 0xffffff,
103884a3 2258 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2259 /* ATI SB 450/600/700/800/900 */
2260 { PCI_DEVICE(0x1002, 0x437b),
2261 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2262 { PCI_DEVICE(0x1002, 0x4383),
2263 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2264 /* AMD Hudson */
2265 { PCI_DEVICE(0x1022, 0x780d),
2266 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2267 /* ATI HDMI */
650474fb
AD		 2268 { PCI_DEVICE(0x1002, 0x1308),
2269 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2270 { PCI_DEVICE(0x1002, 0x157a),
2271 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2272 { PCI_DEVICE(0x1002, 0x793b),
2273 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2274 { PCI_DEVICE(0x1002, 0x7919),
2275 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2276 { PCI_DEVICE(0x1002, 0x960f),
2277 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2278 { PCI_DEVICE(0x1002, 0x970f),
2279 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2280 { PCI_DEVICE(0x1002, 0x9840),
2281 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2282 { PCI_DEVICE(0x1002, 0xaa00),
2283 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2284 { PCI_DEVICE(0x1002, 0xaa08),
2285 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2286 { PCI_DEVICE(0x1002, 0xaa10),
2287 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2288 { PCI_DEVICE(0x1002, 0xaa18),
2289 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2290 { PCI_DEVICE(0x1002, 0xaa20),
2291 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2292 { PCI_DEVICE(0x1002, 0xaa28),
2293 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2294 { PCI_DEVICE(0x1002, 0xaa30),
2295 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2296 { PCI_DEVICE(0x1002, 0xaa38),
2297 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2298 { PCI_DEVICE(0x1002, 0xaa40),
2299 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2300 { PCI_DEVICE(0x1002, 0xaa48),
2301 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2302 { PCI_DEVICE(0x1002, 0xaa50),
2303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2304 { PCI_DEVICE(0x1002, 0xaa58),
2305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2306 { PCI_DEVICE(0x1002, 0xaa60),
2307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2308 { PCI_DEVICE(0x1002, 0xaa68),
2309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2310 { PCI_DEVICE(0x1002, 0xaa80),
2311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2312 { PCI_DEVICE(0x1002, 0xaa88),
2313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2314 { PCI_DEVICE(0x1002, 0xaa90),
2315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2316 { PCI_DEVICE(0x1002, 0xaa98),
2317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2318 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2319 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2320 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2321 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2322 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2323 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2324 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2325 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2326 { PCI_DEVICE(0x1002, 0xaac0),
2327 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2328 { PCI_DEVICE(0x1002, 0xaac8),
2329 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2330 { PCI_DEVICE(0x1002, 0xaad8),
2331 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2332 { PCI_DEVICE(0x1002, 0xaae8),
2333 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2334 { PCI_DEVICE(0x1002, 0xaae0),
2335 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2336 { PCI_DEVICE(0x1002, 0xaaf0),
2337 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2338 /* VIA VT8251/VT8237A */
26f05717 2339 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2340 /* VIA GFX VT7122/VX900 */
2341 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2342 /* VIA GFX VT6122/VX11 */
2343 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2344 /* SIS966 */
2345 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2346 /* ULI M5461 */
2347 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2348 /* NVIDIA MCP */
0c2fd1bf
TI		 2349 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2350 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2351 .class_mask = 0xffffff,
9477c58e 2352 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2353 /* Teradici */
9477c58e
TI		 2354 { PCI_DEVICE(0x6549, 0x1200),
2355 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2356 { PCI_DEVICE(0x6549, 0x2200),
2357 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2358 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2359 /* CTHDA chips */
2360 { PCI_DEVICE(0x1102, 0x0010),
2361 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2362 { PCI_DEVICE(0x1102, 0x0012),
2363 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2364#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2365 /* the following entry conflicts with snd-ctxfi driver,
2366 * as ctxfi driver mutates from HD-audio to native mode with
2367 * a special command sequence.
2368 */
4e01f54b
TI		 2369 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2370 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2371 .class_mask = 0xffffff,
9477c58e 2372 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2373 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2374#else
2375 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2376 { PCI_DEVICE(0x1102, 0x0009),
2377 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2378 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2379#endif
c563f473
TI		 2380 /* CM8888 */
2381 { PCI_DEVICE(0x13f6, 0x5011),
2382 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2383 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2384 /* Vortex86MX */
2385 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2386 /* VMware HDAudio */
2387 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2388 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2389 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2390 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2391 .class_mask = 0xffffff,
9477c58e 2392 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2393 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2394 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2395 .class_mask = 0xffffff,
9477c58e 2396 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2397 { 0, }
2398};
2399MODULE_DEVICE_TABLE(pci, azx_ids);
2400
2401/* pci_driver definition */
e9f66d9b 2402static struct pci_driver azx_driver = {
3733e424 2403 .name = KBUILD_MODNAME,
1da177e4
LT		 2404 .id_table = azx_ids,
2405 .probe = azx_probe,
e23e7a14 2406 .remove = azx_remove,
b2a0bafa 2407 .shutdown = azx_shutdown,
68cb2b55
TI		 2408 .driver = {
2409 .pm = AZX_PM_OPS,
2410 },
1da177e4
LT		 2411};
2412
e9f66d9b 2413module_pci_driver(azx_driver);
Linux kernel - Deliverables
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