projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - Enable sysfs attributes without CONFIG_SND_HDA_RECONFIG
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
1da177e4
LT		 66
67
5aba4f8e
TI		 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 70static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 71static char *model[SNDRV_CARDS];
1dac6695 72static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 73static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 74static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 75static int probe_only[SNDRV_CARDS];
26a6cb6c 76static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 77static bool single_cmd;
71623855 78static int enable_msi = -1;
4ea6fbc8
TI		 79#ifdef CONFIG_SND_HDA_PATCH_LOADER
80static char *patch[SNDRV_CARDS];
81#endif
2dca0bba 82#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 83static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85#endif
1da177e4 86
5aba4f8e 87module_param_array(index, int, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 89module_param_array(id, charp, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 91module_param_array(enable, bool, NULL, 0444);
92MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93module_param_array(model, charp, NULL, 0444);
1da177e4 94MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 95module_param_array(position_fix, int, NULL, 0444);
4cb36310 96MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 98module_param_array(bdl_pos_adj, int, NULL, 0644);
99MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 100module_param_array(probe_mask, int, NULL, 0444);
606ad75f 101MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 102module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 103MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 104module_param_array(jackpoll_ms, int, NULL, 0444);
105MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 106module_param(single_cmd, bool, 0444);
d01ce99f
TI		 107MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
ac9ef6cf 109module_param(enable_msi, bint, 0444);
134a11f0 110MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 111#ifdef CONFIG_SND_HDA_PATCH_LOADER
112module_param_array(patch, charp, NULL, 0444);
113MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114#endif
2dca0bba 115#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 116module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 117MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 118 "(0=off, 1=on) (default=1).");
2dca0bba 119#endif
606ad75f 120
83012a7c 121#ifdef CONFIG_PM
65fcd41d
TI		 122static int param_set_xint(const char *val, const struct kernel_param *kp);
123static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126};
127#define param_check_xint param_check_int
128
fee2fba3 129static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 130module_param(power_save, xint, 0644);
fee2fba3
TI		 131MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
1da177e4 133
dee1b66c
TI		 134/* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
8fc24426
TI		 138static bool power_save_controller = 1;
139module_param(power_save_controller, bool, 0644);
dee1b66c 140MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 141#endif /* CONFIG_PM */
dee1b66c 142
7bfe059e
TI		 143static int align_buffer_size = -1;
144module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 145MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
27fe48d9
TI		 148#ifdef CONFIG_X86
149static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else
154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif
157
158
1da177e4
LT		 159MODULE_LICENSE("GPL");
160MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
2f1b3818 162 "{Intel, ICH7},"
f5d40b30 163 "{Intel, ESB2},"
d2981393 164 "{Intel, ICH8},"
f9cc8a8b 165 "{Intel, ICH9},"
c34f5a04 166 "{Intel, ICH10},"
b29c2360 167 "{Intel, PCH},"
d2f2fcd2 168 "{Intel, CPT},"
d2edeb7c 169 "{Intel, PPT},"
8bc039a1 170 "{Intel, LPT},"
144dad99 171 "{Intel, LPT_LP},"
4eeca499 172 "{Intel, WPT_LP},"
e926f2c8 173 "{Intel, HPT},"
cea310e8 174 "{Intel, PBG},"
4979bca9 175 "{Intel, SCH},"
fc20a562 176 "{ATI, SB450},"
89be83f8 177 "{ATI, SB600},"
778b6e1b 178 "{ATI, RS600},"
5b15c95f 179 "{ATI, RS690},"
e6db1119
WL		 180 "{ATI, RS780},"
181 "{ATI, R600},"
2797f724
HRK		 182 "{ATI, RV630},"
183 "{ATI, RV610},"
27da1834
WL		 184 "{ATI, RV670},"
185 "{ATI, RV635},"
186 "{ATI, RV620},"
187 "{ATI, RV770},"
fc20a562 188 "{VIA, VT8251},"
47672310 189 "{VIA, VT8237A},"
07e4ca50
TI		 190 "{SiS, SIS966},"
191 "{ULI, M5461}}");
1da177e4
LT		 192MODULE_DESCRIPTION("Intel HDA driver");
193
4abc1cc2
TI		 194#ifdef CONFIG_SND_VERBOSE_PRINTK
195#define SFX /* nop */
196#else
445a51b3 197#define SFX "hda-intel "
4abc1cc2 198#endif
cb53c626 199
a82d51ed 200#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 201#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 202#define SUPPORT_VGA_SWITCHEROO
203#endif
204#endif
205
206
1da177e4
LT		 207/*
208 * registers
209 */
210#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 211#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
212#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
213#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
214#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
215#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 216#define ICH6_REG_VMIN 0x02
217#define ICH6_REG_VMAJ 0x03
218#define ICH6_REG_OUTPAY 0x04
219#define ICH6_REG_INPAY 0x06
220#define ICH6_REG_GCTL 0x08
8a933ece 221#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 222#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
223#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 224#define ICH6_REG_WAKEEN 0x0c
225#define ICH6_REG_STATESTS 0x0e
226#define ICH6_REG_GSTS 0x10
b21fadb9 227#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 228#define ICH6_REG_INTCTL 0x20
229#define ICH6_REG_INTSTS 0x24
e5463720 230#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 231#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
232#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 233#define ICH6_REG_CORBLBASE 0x40
234#define ICH6_REG_CORBUBASE 0x44
235#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 236#define ICH6_REG_CORBRP 0x4a
237#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 238#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 239#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
240#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 241#define ICH6_REG_CORBSTS 0x4d
b21fadb9 242#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 243#define ICH6_REG_CORBSIZE 0x4e
244
245#define ICH6_REG_RIRBLBASE 0x50
246#define ICH6_REG_RIRBUBASE 0x54
247#define ICH6_REG_RIRBWP 0x58
b21fadb9 248#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 249#define ICH6_REG_RINTCNT 0x5a
250#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 251#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
252#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
253#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 254#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 255#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
256#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 257#define ICH6_REG_RIRBSIZE 0x5e
258
259#define ICH6_REG_IC 0x60
260#define ICH6_REG_IR 0x64
261#define ICH6_REG_IRS 0x68
262#define ICH6_IRS_VALID (1<<1)
263#define ICH6_IRS_BUSY (1<<0)
264
265#define ICH6_REG_DPLBASE 0x70
266#define ICH6_REG_DPUBASE 0x74
267#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
268
269/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
271
272/* stream register offsets from stream base */
273#define ICH6_REG_SD_CTL 0x00
274#define ICH6_REG_SD_STS 0x03
275#define ICH6_REG_SD_LPIB 0x04
276#define ICH6_REG_SD_CBL 0x08
277#define ICH6_REG_SD_LVI 0x0c
278#define ICH6_REG_SD_FIFOW 0x0e
279#define ICH6_REG_SD_FIFOSIZE 0x10
280#define ICH6_REG_SD_FORMAT 0x12
281#define ICH6_REG_SD_BDLPL 0x18
282#define ICH6_REG_SD_BDLPU 0x1c
283
284/* PCI space */
285#define ICH6_PCIREG_TCSEL 0x44
286
287/*
288 * other constants
289 */
290
291/* max number of SDs */
07e4ca50 292/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 293#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 294#define ICH6_NUM_PLAYBACK 4
295
296/* ULI has 6 playback and 5 capture */
07e4ca50 297#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 298#define ULI_NUM_PLAYBACK 6
299
7546abfb 300/* ATI HDMI may have up to 8 playbacks and 0 capture */
778b6e1b 301#define ATIHDMI_NUM_CAPTURE 0
7546abfb 302#define ATIHDMI_NUM_PLAYBACK 8
778b6e1b 303
f269002e
KY		 304/* TERA has 4 playback and 3 capture */
305#define TERA_NUM_CAPTURE 3
306#define TERA_NUM_PLAYBACK 4
307
07e4ca50
TI		 308/* this number is statically defined for simplicity */
309#define MAX_AZX_DEV 16
310
1da177e4 311/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 312#define BDL_SIZE 4096
313#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
314#define AZX_MAX_FRAG 32
1da177e4
LT		 315/* max buffer size - no h/w limit, you can increase as you like */
316#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 317
318/* RIRB int mask: overrun[2], response[0] */
319#define RIRB_INT_RESPONSE 0x01
320#define RIRB_INT_OVERRUN 0x04
321#define RIRB_INT_MASK 0x05
322
2f5983f2 323/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 324#define AZX_MAX_CODECS 8
325#define AZX_DEFAULT_CODECS 4
deadff16 326#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 327
328/* SD_CTL bits */
329#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
330#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 331#define SD_CTL_STRIPE (3 << 16) /* stripe control */
332#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
333#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 334#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
335#define SD_CTL_STREAM_TAG_SHIFT 20
336
337/* SD_CTL and SD_STS */
338#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
339#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
340#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 341#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342 SD_INT_COMPLETE)
1da177e4
LT		 343
344/* SD_STS */
345#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
346
347/* INTCTL and INTSTS */
d01ce99f
TI		 348#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
349#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
350#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 351
1da177e4
LT		 352/* below are so far hardcoded - should read registers in future */
353#define ICH6_MAX_CORB_ENTRIES 256
354#define ICH6_MAX_RIRB_ENTRIES 256
355
c74db86b
TI		 356/* position fix mode */
357enum {
0be3b5d3 358 POS_FIX_AUTO,
d2e1c973 359 POS_FIX_LPIB,
0be3b5d3 360 POS_FIX_POSBUF,
4cb36310 361 POS_FIX_VIACOMBO,
a6f2fd55 362 POS_FIX_COMBO,
c74db86b 363};
1da177e4 364
f5d40b30 365/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 366#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
367#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
368
da3fca21
V		 369/* Defines for Nvidia HDA support */
370#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
371#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 372#define NVIDIA_HDA_ISTRM_COH 0x4d
373#define NVIDIA_HDA_OSTRM_COH 0x4c
374#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 375
90a5ad52
TI		 376/* Defines for Intel SCH HDA snoop control */
377#define INTEL_SCH_HDA_DEVC 0x78
378#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
379
0e153474
JC		 380/* Define IN stream 0 FIFO size offset in VIA controller */
381#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382/* Define VIA HD Audio Device ID*/
383#define VIA_HDAC_DEVICE_ID 0x3288
384
c4da29ca
YL		 385/* HD Audio class code */
386#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 387
1da177e4
LT		 388/*
389 */
390
a98f90fd 391struct azx_dev {
4ce107b9 392 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 393 u32 *posbuf; /* position buffer pointer */
1da177e4 394
d01ce99f 395 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 396 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 399 unsigned long start_wallclk; /* start + minimum wallclk */
400 unsigned long period_wallclk; /* wallclk for period */
1da177e4 401
d01ce99f 402 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 403
d01ce99f 404 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 405
406 /* pcm support */
d01ce99f
TI		 407 struct snd_pcm_substream *substream; /* assigned substream,
408 * set in PCM open
409 */
410 unsigned int format_val; /* format value to be set in the
411 * controller and the codec
412 */
1da177e4
LT		 413 unsigned char stream_tag; /* assigned stream */
414 unsigned char index; /* stream index */
d5cf9911 415 int assigned_key; /* last device# key assigned to */
1da177e4 416
927fc866
PM		 417 unsigned int opened :1;
418 unsigned int running :1;
675f25d4 419 unsigned int irq_pending :1;
eb49faa6
TI		 420 unsigned int prepared:1;
421 unsigned int locked:1;
0e153474
JC		 422 /*
423 * For VIA:
424 * A flag to ensure DMA position is 0
425 * when link position is not greater than FIFO size
426 */
427 unsigned int insufficient :1;
27fe48d9 428 unsigned int wc_marked:1;
915bf29e 429 unsigned int no_period_wakeup:1;
5d890f59
PLB		 430
431 struct timecounter azx_tc;
432 struct cyclecounter azx_cc;
eb49faa6 433
e8648e5e
TI		 434 int delay_negative_threshold;
435
eb49faa6
TI		 436#ifdef CONFIG_SND_HDA_DSP_LOADER
437 struct mutex dsp_mutex;
438#endif
1da177e4
LT		 439};
440
eb49faa6
TI		 441/* DSP lock helpers */
442#ifdef CONFIG_SND_HDA_DSP_LOADER
443#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
444#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
445#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
446#define dsp_is_locked(dev) ((dev)->locked)
447#else
448#define dsp_lock_init(dev) do {} while (0)
449#define dsp_lock(dev) do {} while (0)
450#define dsp_unlock(dev) do {} while (0)
451#define dsp_is_locked(dev) 0
452#endif
453
1da177e4 454/* CORB/RIRB */
a98f90fd 455struct azx_rb {
1da177e4
LT		 456 u32 *buf; /* CORB/RIRB buffer
457 * Each CORB entry is 4byte, RIRB is 8byte
458 */
459 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
460 /* for RIRB */
461 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 462 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
463 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 464};
465
01b65bfb
TI		 466struct azx_pcm {
467 struct azx *chip;
468 struct snd_pcm *pcm;
469 struct hda_codec *codec;
470 struct hda_pcm_stream *hinfo[2];
471 struct list_head list;
472};
473
a98f90fd
TI		 474struct azx {
475 struct snd_card *card;
1da177e4 476 struct pci_dev *pci;
555e219f 477 int dev_index;
1da177e4 478
07e4ca50
TI		 479 /* chip type specific */
480 int driver_type;
9477c58e 481 unsigned int driver_caps;
07e4ca50
TI		 482 int playback_streams;
483 int playback_index_offset;
484 int capture_streams;
485 int capture_index_offset;
486 int num_streams;
487
1da177e4
LT		 488 /* pci resources */
489 unsigned long addr;
490 void __iomem *remap_addr;
491 int irq;
492
493 /* locks */
494 spinlock_t reg_lock;
62932df8 495 struct mutex open_mutex;
f4c482a4 496 struct completion probe_wait;
1da177e4 497
07e4ca50 498 /* streams (x num_streams) */
a98f90fd 499 struct azx_dev *azx_dev;
1da177e4
LT		 500
501 /* PCM */
01b65bfb 502 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 503
504 /* HD codec */
505 unsigned short codec_mask;
f1eaaeec 506 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 507 struct hda_bus *bus;
2dca0bba 508 unsigned int beep_mode;
1da177e4
LT		 509
510 /* CORB/RIRB */
a98f90fd
TI		 511 struct azx_rb corb;
512 struct azx_rb rirb;
1da177e4 513
4ce107b9 514 /* CORB/RIRB and position buffers */
1da177e4
LT		 515 struct snd_dma_buffer rb;
516 struct snd_dma_buffer posbuf;
c74db86b 517
4918cdab
TI		 518#ifdef CONFIG_SND_HDA_PATCH_LOADER
519 const struct firmware *fw;
520#endif
521
c74db86b 522 /* flags */
beaffc39 523 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 524 int poll_count;
cb53c626 525 unsigned int running :1;
927fc866
PM		 526 unsigned int initialized :1;
527 unsigned int single_cmd :1;
528 unsigned int polling_mode :1;
68e7fffc 529 unsigned int msi :1;
a6a950a8 530 unsigned int irq_pending_warned :1;
6ce4a3bc 531 unsigned int probing :1; /* codec probing phase */
27fe48d9 532 unsigned int snoop:1;
52409aa6 533 unsigned int align_buffer_size:1;
a82d51ed
TI		 534 unsigned int region_requested:1;
535
536 /* VGA-switcheroo setup */
537 unsigned int use_vga_switcheroo:1;
128960a9 538 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 539 unsigned int init_failed:1; /* delayed init failed */
540 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 541
542 /* for debugging */
feb27340 543 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 544
545 /* for pending irqs */
546 struct work_struct irq_pending_work;
0cbf0098 547
99a2008d 548 struct work_struct probe_work;
99a2008d 549
0cbf0098
TI		 550 /* reboot notifier (for mysterious hangup problem at power-down) */
551 struct notifier_block reboot_notifier;
65fcd41d
TI		 552
553 /* card list (for power_save trigger) */
554 struct list_head list;
eb49faa6
TI		 555
556#ifdef CONFIG_SND_HDA_DSP_LOADER
557 struct azx_dev saved_azx_dev;
558#endif
246efa4a
DA		 559
560 /* secondary power domain for hdmi audio under vga device */
561 struct dev_pm_domain hdmi_pm_domain;
1da177e4
LT		 562};
563
1a8506d4
TI		 564#define CREATE_TRACE_POINTS
565#include "hda_intel_trace.h"
566
07e4ca50
TI		 567/* driver types */
568enum {
569 AZX_DRIVER_ICH,
32679f95 570 AZX_DRIVER_PCH,
4979bca9 571 AZX_DRIVER_SCH,
fab1285a 572 AZX_DRIVER_HDMI,
07e4ca50 573 AZX_DRIVER_ATI,
778b6e1b 574 AZX_DRIVER_ATIHDMI,
1815b34a 575 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 576 AZX_DRIVER_VIA,
577 AZX_DRIVER_SIS,
578 AZX_DRIVER_ULI,
da3fca21 579 AZX_DRIVER_NVIDIA,
f269002e 580 AZX_DRIVER_TERA,
14d34f16 581 AZX_DRIVER_CTX,
5ae763b1 582 AZX_DRIVER_CTHDA,
c4da29ca 583 AZX_DRIVER_GENERIC,
2f5983f2 584 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 585};
586
9477c58e
TI		 587/* driver quirks (capabilities) */
588/* bits 0-7 are used for indicating driver type */
589#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
590#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
591#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
592#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
593#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
594#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
595#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
596#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
597#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
598#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
599#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
600#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 601#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 602#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 603#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 604#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 605#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2 606#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
99a2008d 607#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
2ea3c6a2
TI		 608
609/* quirks for Intel PCH */
d7dab4db 610#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 611 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 612 AZX_DCAPS_COUNT_LPIB_DELAY)
613
614#define AZX_DCAPS_INTEL_PCH \
615 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 616
33499a15
TI		 617#define AZX_DCAPS_INTEL_HASWELL \
618 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
619 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
620 AZX_DCAPS_I915_POWERWELL)
621
9477c58e
TI		 622/* quirks for ATI SB / AMD Hudson */
623#define AZX_DCAPS_PRESET_ATI_SB \
624 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
625 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
626
627/* quirks for ATI/AMD HDMI */
628#define AZX_DCAPS_PRESET_ATI_HDMI \
629 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
630
631/* quirks for Nvidia */
632#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 633 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 634 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 635
5ae763b1
TI		 636#define AZX_DCAPS_PRESET_CTHDA \
637 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
638
a82d51ed
TI		 639/*
640 * VGA-switcher support
641 */
642#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 643#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
644#else
645#define use_vga_switcheroo(chip) 0
646#endif
647
48c8b0eb 648static char *driver_short_names[] = {
07e4ca50 649 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 650 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 651 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 652 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 653 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 654 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 655 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 656 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
657 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 658 [AZX_DRIVER_ULI] = "HDA ULI M5461",
659 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 660 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 661 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 662 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 663 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 664};
665
1da177e4
LT		 666/*
667 * macros for easy use
668 */
669#define azx_writel(chip,reg,value) \
670 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
671#define azx_readl(chip,reg) \
672 readl((chip)->remap_addr + ICH6_REG_##reg)
673#define azx_writew(chip,reg,value) \
674 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
675#define azx_readw(chip,reg) \
676 readw((chip)->remap_addr + ICH6_REG_##reg)
677#define azx_writeb(chip,reg,value) \
678 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
679#define azx_readb(chip,reg) \
680 readb((chip)->remap_addr + ICH6_REG_##reg)
681
682#define azx_sd_writel(dev,reg,value) \
683 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
684#define azx_sd_readl(dev,reg) \
685 readl((dev)->sd_addr + ICH6_REG_##reg)
686#define azx_sd_writew(dev,reg,value) \
687 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
688#define azx_sd_readw(dev,reg) \
689 readw((dev)->sd_addr + ICH6_REG_##reg)
690#define azx_sd_writeb(dev,reg,value) \
691 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
692#define azx_sd_readb(dev,reg) \
693 readb((dev)->sd_addr + ICH6_REG_##reg)
694
695/* for pcm support */
a98f90fd 696#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 697
27fe48d9 698#ifdef CONFIG_X86
9ddf1aeb 699static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 700{
9ddf1aeb
TI		 701 int pages;
702
27fe48d9
TI		 703 if (azx_snoop(chip))
704 return;
9ddf1aeb
TI		 705 if (!dmab || !dmab->area || !dmab->bytes)
706 return;
707
708#ifdef CONFIG_SND_DMA_SGBUF
709 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
710 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 711 if (on)
9ddf1aeb 712 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 713 else
9ddf1aeb
TI		 714 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
715 return;
27fe48d9 716 }
9ddf1aeb
TI		 717#endif
718
719 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
720 if (on)
721 set_memory_wc((unsigned long)dmab->area, pages);
722 else
723 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 724}
725
726static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
727 bool on)
728{
9ddf1aeb 729 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 730}
731static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 732 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 733{
734 if (azx_dev->wc_marked != on) {
9ddf1aeb 735 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 736 azx_dev->wc_marked = on;
737 }
738}
739#else
740/* NOP for other archs */
741static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
742 bool on)
743{
744}
745static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 746 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 747{
748}
749#endif
750
68e7fffc 751static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 752static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 753/*
754 * Interface for HD codec
755 */
756
1da177e4
LT		 757/*
758 * CORB / RIRB interface
759 */
a98f90fd 760static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 761{
762 int err;
763
764 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 765 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
766 snd_dma_pci_data(chip->pci),
1da177e4
LT		 767 PAGE_SIZE, &chip->rb);
768 if (err < 0) {
445a51b3 769 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 770 return err;
771 }
27fe48d9 772 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 773 return 0;
774}
775
a98f90fd 776static void azx_init_cmd_io(struct azx *chip)
1da177e4 777{
cdb1fbf2 778 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 779 /* CORB set up */
780 chip->corb.addr = chip->rb.addr;
781 chip->corb.buf = (u32 *)chip->rb.area;
782 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 783 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 784
07e4ca50
TI		 785 /* set the corb size to 256 entries (ULI requires explicitly) */
786 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 787 /* set the corb write pointer to 0 */
788 azx_writew(chip, CORBWP, 0);
789 /* reset the corb hw read pointer */
b21fadb9 790 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 791 /* enable corb dma */
b21fadb9 792 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 793
794 /* RIRB set up */
795 chip->rirb.addr = chip->rb.addr + 2048;
796 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 797 chip->rirb.wp = chip->rirb.rp = 0;
798 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 799 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 800 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 801
07e4ca50
TI		 802 /* set the rirb size to 256 entries (ULI requires explicitly) */
803 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 804 /* reset the rirb hw write pointer */
b21fadb9 805 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 806 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 807 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 808 azx_writew(chip, RINTCNT, 0xc0);
809 else
810 azx_writew(chip, RINTCNT, 1);
1da177e4 811 /* enable rirb dma and response irq */
1da177e4 812 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 813 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 814}
815
a98f90fd 816static void azx_free_cmd_io(struct azx *chip)
1da177e4 817{
cdb1fbf2 818 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 819 /* disable ringbuffer DMAs */
820 azx_writeb(chip, RIRBCTL, 0);
821 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 822 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 823}
824
deadff16
WF		 825static unsigned int azx_command_addr(u32 cmd)
826{
827 unsigned int addr = cmd >> 28;
828
829 if (addr >= AZX_MAX_CODECS) {
830 snd_BUG();
831 addr = 0;
832 }
833
834 return addr;
835}
836
1da177e4 837/* send a command */
33fa35ed 838static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 839{
33fa35ed 840 struct azx *chip = bus->private_data;
deadff16 841 unsigned int addr = azx_command_addr(val);
3bcce5c0 842 unsigned int wp, rp;
1da177e4 843
c32649fe
WF		 844 spin_lock_irq(&chip->reg_lock);
845
1da177e4 846 /* add command to corb */
cc5ede3e
TI		 847 wp = azx_readw(chip, CORBWP);
848 if (wp == 0xffff) {
849 /* something wrong, controller likely turned to D3 */
850 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 851 return -EIO;
cc5ede3e 852 }
1da177e4
LT		 853 wp++;
854 wp %= ICH6_MAX_CORB_ENTRIES;
855
3bcce5c0
TI		 856 rp = azx_readw(chip, CORBRP);
857 if (wp == rp) {
858 /* oops, it's full */
859 spin_unlock_irq(&chip->reg_lock);
860 return -EAGAIN;
861 }
862
deadff16 863 chip->rirb.cmds[addr]++;
1da177e4
LT		 864 chip->corb.buf[wp] = cpu_to_le32(val);
865 azx_writel(chip, CORBWP, wp);
c32649fe 866
1da177e4
LT		 867 spin_unlock_irq(&chip->reg_lock);
868
869 return 0;
870}
871
872#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
873
874/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 875static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 876{
877 unsigned int rp, wp;
deadff16 878 unsigned int addr;
1da177e4
LT		 879 u32 res, res_ex;
880
cc5ede3e
TI		 881 wp = azx_readw(chip, RIRBWP);
882 if (wp == 0xffff) {
883 /* something wrong, controller likely turned to D3 */
884 return;
885 }
886
1da177e4
LT		 887 if (wp == chip->rirb.wp)
888 return;
889 chip->rirb.wp = wp;
deadff16 890
1da177e4
LT		 891 while (chip->rirb.rp != wp) {
892 chip->rirb.rp++;
893 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
894
895 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
896 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
897 res = le32_to_cpu(chip->rirb.buf[rp]);
3d692451
DH		 898 addr = res_ex & 0xf;
899 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
900 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, rp = %d, wp = %d",
901 pci_name(chip->pci),
902 res, res_ex,
903 chip->rirb.rp, wp);
904 snd_BUG();
905 }
906 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
1da177e4 907 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 908 else if (chip->rirb.cmds[addr]) {
909 chip->rirb.res[addr] = res;
2add9b92 910 smp_wmb();
deadff16 911 chip->rirb.cmds[addr]--;
3b70a67d
JP		 912 } else if (printk_ratelimit()) {
913 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, last cmd=%#08x\n",
9e3d352b 914 pci_name(chip->pci),
e310bb06
WF		 915 res, res_ex,
916 chip->last_cmd[addr]);
3b70a67d 917 }
1da177e4
LT		 918 }
919}
920
921/* receive a response */
deadff16
WF		 922static unsigned int azx_rirb_get_response(struct hda_bus *bus,
923 unsigned int addr)
1da177e4 924{
33fa35ed 925 struct azx *chip = bus->private_data;
5c79b1f8 926 unsigned long timeout;
32cf4023 927 unsigned long loopcounter;
1eb6dc7d 928 int do_poll = 0;
1da177e4 929
5c79b1f8
TI		 930 again:
931 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 932
933 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 934 if (chip->polling_mode || do_poll) {
e96224ae
TI		 935 spin_lock_irq(&chip->reg_lock);
936 azx_update_rirb(chip);
937 spin_unlock_irq(&chip->reg_lock);
938 }
deadff16 939 if (!chip->rirb.cmds[addr]) {
2add9b92 940 smp_rmb();
b613291f 941 bus->rirb_error = 0;
1eb6dc7d
ML		 942
943 if (!do_poll)
944 chip->poll_count = 0;
deadff16 945 return chip->rirb.res[addr]; /* the last value */
2add9b92 946 }
28a0d9df
TI		 947 if (time_after(jiffies, timeout))
948 break;
32cf4023 949 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 950 msleep(2); /* temporary workaround */
951 else {
952 udelay(10);
953 cond_resched();
954 }
28a0d9df 955 }
5c79b1f8 956
63e51fd7
TI		 957 if (!bus->no_response_fallback)
958 return -1;
959
1eb6dc7d 960 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 961 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 962 "polling the codec once: last cmd=0x%08x\n",
445a51b3 963 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 964 do_poll = 1;
965 chip->poll_count++;
966 goto again;
967 }
968
969
23c4a881 970 if (!chip->polling_mode) {
445a51b3 971 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 972 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 973 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 974 chip->polling_mode = 1;
975 goto again;
976 }
977
68e7fffc 978 if (chip->msi) {
445a51b3 979 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 980 "disabling MSI: last cmd=0x%08x\n",
445a51b3 981 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 982 free_irq(chip->irq, chip);
983 chip->irq = -1;
984 pci_disable_msi(chip->pci);
985 chip->msi = 0;
b613291f
TI		 986 if (azx_acquire_irq(chip, 1) < 0) {
987 bus->rirb_error = 1;
68e7fffc 988 return -1;
b613291f 989 }
68e7fffc
TI		 990 goto again;
991 }
992
6ce4a3bc
TI		 993 if (chip->probing) {
994 /* If this critical timeout happens during the codec probing
995 * phase, this is likely an access to a non-existing codec
996 * slot. Better to return an error and reset the system.
997 */
998 return -1;
999 }
1000
8dd78330
TI		 1001 /* a fatal communication error; need either to reset or to fallback
1002 * to the single_cmd mode
1003 */
b613291f 1004 bus->rirb_error = 1;
b20f3b83 1005 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 1006 bus->response_reset = 1;
1007 return -1; /* give a chance to retry */
1008 }
1009
1010 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1011 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1012 chip->last_cmd[addr]);
8dd78330
TI		 1013 chip->single_cmd = 1;
1014 bus->response_reset = 0;
1a696978 1015 /* release CORB/RIRB */
4fcd3920 1016 azx_free_cmd_io(chip);
1a696978
TI		 1017 /* disable unsolicited responses */
1018 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1019 return -1;
1da177e4
LT		 1020}
1021
1da177e4
LT		 1022/*
1023 * Use the single immediate command instead of CORB/RIRB for simplicity
1024 *
1025 * Note: according to Intel, this is not preferred use. The command was
1026 * intended for the BIOS only, and may get confused with unsolicited
1027 * responses. So, we shouldn't use it for normal operation from the
1028 * driver.
1029 * I left the codes, however, for debugging/testing purposes.
1030 */
1031
b05a7d4f 1032/* receive a response */
deadff16 1033static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1034{
1035 int timeout = 50;
1036
1037 while (timeout--) {
1038 /* check IRV busy bit */
1039 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1040 /* reuse rirb.res as the response return value */
deadff16 1041 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1042 return 0;
1043 }
1044 udelay(1);
1045 }
1046 if (printk_ratelimit())
445a51b3
DB		 1047 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1048 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1049 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1050 return -EIO;
1051}
1052
1da177e4 1053/* send a command */
33fa35ed 1054static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1055{
33fa35ed 1056 struct azx *chip = bus->private_data;
deadff16 1057 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1058 int timeout = 50;
1059
8dd78330 1060 bus->rirb_error = 0;
1da177e4
LT		 1061 while (timeout--) {
1062 /* check ICB busy bit */
d01ce99f 1063 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1064 /* Clear IRV valid bit */
d01ce99f
TI		 1065 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1066 ICH6_IRS_VALID);
1da177e4 1067 azx_writel(chip, IC, val);
d01ce99f
TI		 1068 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1069 ICH6_IRS_BUSY);
deadff16 1070 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1071 }
1072 udelay(1);
1073 }
1cfd52bc 1074 if (printk_ratelimit())
445a51b3
DB		 1075 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1076 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1077 return -EIO;
1078}
1079
1080/* receive a response */
deadff16
WF		 1081static unsigned int azx_single_get_response(struct hda_bus *bus,
1082 unsigned int addr)
1da177e4 1083{
33fa35ed 1084 struct azx *chip = bus->private_data;
deadff16 1085 return chip->rirb.res[addr];
1da177e4
LT		 1086}
1087
111d3af5
TI		 1088/*
1089 * The below are the main callbacks from hda_codec.
1090 *
1091 * They are just the skeleton to call sub-callbacks according to the
1092 * current setting of chip->single_cmd.
1093 */
1094
1095/* send a command */
33fa35ed 1096static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1097{
33fa35ed 1098 struct azx *chip = bus->private_data;
43bbb6cc 1099
a82d51ed
TI		 1100 if (chip->disabled)
1101 return 0;
feb27340 1102 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1103 if (chip->single_cmd)
33fa35ed 1104 return azx_single_send_cmd(bus, val);
111d3af5 1105 else
33fa35ed 1106 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1107}
1108
1109/* get a response */
deadff16
WF		 1110static unsigned int azx_get_response(struct hda_bus *bus,
1111 unsigned int addr)
111d3af5 1112{
33fa35ed 1113 struct azx *chip = bus->private_data;
a82d51ed
TI		 1114 if (chip->disabled)
1115 return 0;
111d3af5 1116 if (chip->single_cmd)
deadff16 1117 return azx_single_get_response(bus, addr);
111d3af5 1118 else
deadff16 1119 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1120}
1121
83012a7c 1122#ifdef CONFIG_PM
68467f51 1123static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1124#endif
111d3af5 1125
1d1a4564
TI		 1126#ifdef CONFIG_SND_HDA_DSP_LOADER
1127static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1128 unsigned int byte_size,
1129 struct snd_dma_buffer *bufp);
1130static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1131static void azx_load_dsp_cleanup(struct hda_bus *bus,
1132 struct snd_dma_buffer *dmab);
1133#endif
1134
3af3f356 1135/* enter link reset */
7295b264 1136static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 1137{
1138 unsigned long timeout;
1139
1140 /* reset controller */
1141 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1142
1143 timeout = jiffies + msecs_to_jiffies(100);
1144 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1145 time_before(jiffies, timeout))
1146 usleep_range(500, 1000);
1147}
1148
7295b264
ML		 1149/* exit link reset */
1150static void azx_exit_link_reset(struct azx *chip)
1da177e4 1151{
fa348da5 1152 unsigned long timeout;
1da177e4 1153
7295b264
ML		 1154 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1155
1156 timeout = jiffies + msecs_to_jiffies(100);
1157 while (!azx_readb(chip, GCTL) &&
1158 time_before(jiffies, timeout))
1159 usleep_range(500, 1000);
1160}
1161
1162/* reset codec link */
1163static int azx_reset(struct azx *chip, int full_reset)
1164{
cd508fe5
JK		 1165 if (!full_reset)
1166 goto __skip;
1167
e8a7f136 1168 /* clear STATESTS */
da7db6ad 1169 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 1170
1da177e4 1171 /* reset controller */
7295b264 1172 azx_enter_link_reset(chip);
1da177e4
LT		 1173
1174 /* delay for >= 100us for codec PLL to settle per spec
1175 * Rev 0.9 section 5.5.1
1176 */
fa348da5 1177 usleep_range(500, 1000);
1da177e4
LT		 1178
1179 /* Bring controller out of reset */
7295b264 1180 azx_exit_link_reset(chip);
1da177e4 1181
927fc866 1182 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1183 usleep_range(1000, 1200);
1da177e4 1184
cd508fe5 1185 __skip:
1da177e4 1186 /* check to see if controller is ready */
927fc866 1187 if (!azx_readb(chip, GCTL)) {
445a51b3 1188 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1189 return -EBUSY;
1190 }
1191
41e2fce4 1192 /* Accept unsolicited responses */
1a696978
TI		 1193 if (!chip->single_cmd)
1194 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1195 ICH6_GCTL_UNSOL);
41e2fce4 1196
1da177e4 1197 /* detect codecs */
927fc866 1198 if (!chip->codec_mask) {
1da177e4 1199 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1200 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1201 }
1202
1203 return 0;
1204}
1205
1206
1207/*
1208 * Lowlevel interface
1209 */
1210
1211/* enable interrupts */
a98f90fd 1212static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1213{
1214 /* enable controller CIE and GIE */
1215 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1216 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1217}
1218
1219/* disable interrupts */
a98f90fd 1220static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1221{
1222 int i;
1223
1224 /* disable interrupts in stream descriptor */
07e4ca50 1225 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1226 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1227 azx_sd_writeb(azx_dev, SD_CTL,
1228 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1229 }
1230
1231 /* disable SIE for all streams */
1232 azx_writeb(chip, INTCTL, 0);
1233
1234 /* disable controller CIE and GIE */
1235 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1236 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1237}
1238
1239/* clear interrupts */
a98f90fd 1240static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1241{
1242 int i;
1243
1244 /* clear stream status */
07e4ca50 1245 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1246 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1247 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1248 }
1249
1250 /* clear STATESTS */
da7db6ad 1251 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 1252
1253 /* clear rirb status */
1254 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1255
1256 /* clear int status */
1257 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1258}
1259
1260/* start a stream */
a98f90fd 1261static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1262{
0e153474
JC		 1263 /*
1264 * Before stream start, initialize parameter
1265 */
1266 azx_dev->insufficient = 1;
1267
1da177e4 1268 /* enable SIE */
ccc5df05
WN		 1269 azx_writel(chip, INTCTL,
1270 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1271 /* set DMA start and interrupt mask */
1272 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1273 SD_CTL_DMA_START | SD_INT_MASK);
1274}
1275
1dddab40
TI		 1276/* stop DMA */
1277static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1278{
1da177e4
LT		 1279 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1280 ~(SD_CTL_DMA_START | SD_INT_MASK));
1281 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1282}
1283
1284/* stop a stream */
1285static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1286{
1287 azx_stream_clear(chip, azx_dev);
1da177e4 1288 /* disable SIE */
ccc5df05
WN		 1289 azx_writel(chip, INTCTL,
1290 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1291}
1292
1293
1294/*
cb53c626 1295 * reset and start the controller registers
1da177e4 1296 */
cd508fe5 1297static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1298{
cb53c626
TI		 1299 if (chip->initialized)
1300 return;
1da177e4
LT		 1301
1302 /* reset controller */
cd508fe5 1303 azx_reset(chip, full_reset);
1da177e4
LT		 1304
1305 /* initialize interrupts */
1306 azx_int_clear(chip);
1307 azx_int_enable(chip);
1308
1309 /* initialize the codec command I/O */
1a696978
TI		 1310 if (!chip->single_cmd)
1311 azx_init_cmd_io(chip);
1da177e4 1312
0be3b5d3
TI		 1313 /* program the position buffer */
1314 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1315 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1316
cb53c626
TI		 1317 chip->initialized = 1;
1318}
1319
1320/*
1321 * initialize the PCI registers
1322 */
1323/* update bits in a PCI register byte */
1324static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1325 unsigned char mask, unsigned char val)
1326{
1327 unsigned char data;
1328
1329 pci_read_config_byte(pci, reg, &data);
1330 data &= ~mask;
1331 data |= (val & mask);
1332 pci_write_config_byte(pci, reg, data);
1333}
1334
1335static void azx_init_pci(struct azx *chip)
1336{
1337 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1338 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1339 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1340 * codecs.
1341 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1342 */
46f2cc80 1343 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1344 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1345 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1346 }
cb53c626 1347
9477c58e
TI		 1348 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1349 * we need to enable snoop.
1350 */
1351 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1352 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1353 update_pci_byte(chip->pci,
27fe48d9
TI		 1354 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1355 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1356 }
1357
1358 /* For NVIDIA HDA, enable snoop */
1359 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1360 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1361 update_pci_byte(chip->pci,
1362 NVIDIA_HDA_TRANSREG_ADDR,
1363 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1364 update_pci_byte(chip->pci,
1365 NVIDIA_HDA_ISTRM_COH,
1366 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1367 update_pci_byte(chip->pci,
1368 NVIDIA_HDA_OSTRM_COH,
1369 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1370 }
1371
1372 /* Enable SCH/PCH snoop if needed */
1373 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1374 unsigned short snoop;
90a5ad52 1375 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1376 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1377 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1378 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1379 if (!azx_snoop(chip))
1380 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1381 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1382 pci_read_config_word(chip->pci,
1383 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1384 }
445a51b3
DB		 1385 snd_printdd(SFX "%s: SCH snoop: %s\n",
1386 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1387 ? "Disabled" : "Enabled");
da3fca21 1388 }
1da177e4
LT		 1389}
1390
1391
9ad593f6
TI		 1392static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1393
1da177e4
LT		 1394/*
1395 * interrupt handler
1396 */
7d12e780 1397static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1398{
a98f90fd
TI		 1399 struct azx *chip = dev_id;
1400 struct azx_dev *azx_dev;
1da177e4 1401 u32 status;
9ef04066 1402 u8 sd_status;
fa00e046 1403 int i, ok;
1da177e4 1404
b8dfc462 1405#ifdef CONFIG_PM_RUNTIME
246efa4a
DA		 1406 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1407 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1408 return IRQ_NONE;
b8dfc462
ML		 1409#endif
1410
1da177e4
LT		 1411 spin_lock(&chip->reg_lock);
1412
60911062
DC		 1413 if (chip->disabled) {
1414 spin_unlock(&chip->reg_lock);
a82d51ed 1415 return IRQ_NONE;
60911062 1416 }
a82d51ed 1417
1da177e4 1418 status = azx_readl(chip, INTSTS);
246efa4a 1419 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 1420 spin_unlock(&chip->reg_lock);
1421 return IRQ_NONE;
1422 }
1423
07e4ca50 1424 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1425 azx_dev = &chip->azx_dev[i];
1426 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1427 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1428 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1429 if (!azx_dev->substream || !azx_dev->running ||
1430 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1431 continue;
1432 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1433 ok = azx_position_ok(chip, azx_dev);
1434 if (ok == 1) {
9ad593f6 1435 azx_dev->irq_pending = 0;
1da177e4
LT		 1436 spin_unlock(&chip->reg_lock);
1437 snd_pcm_period_elapsed(azx_dev->substream);
1438 spin_lock(&chip->reg_lock);
fa00e046 1439 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1440 /* bogus IRQ, process it later */
1441 azx_dev->irq_pending = 1;
6acaed38
TI		 1442 queue_work(chip->bus->workq,
1443 &chip->irq_pending_work);
1da177e4
LT		 1444 }
1445 }
1446 }
1447
1448 /* clear rirb int */
1449 status = azx_readb(chip, RIRBSTS);
1450 if (status & RIRB_INT_MASK) {
14d34f16 1451 if (status & RIRB_INT_RESPONSE) {
9477c58e 1452 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1453 udelay(80);
1da177e4 1454 azx_update_rirb(chip);
14d34f16 1455 }
1da177e4
LT		 1456 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1457 }
1458
1459#if 0
1460 /* clear state status int */
da7db6ad
WX		 1461 if (azx_readw(chip, STATESTS) & 0x04)
1462 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1463#endif
1464 spin_unlock(&chip->reg_lock);
1465
1466 return IRQ_HANDLED;
1467}
1468
1469
675f25d4
TI		 1470/*
1471 * set up a BDL entry
1472 */
5ae763b1 1473static int setup_bdle(struct azx *chip,
1d1a4564 1474 struct snd_dma_buffer *dmab,
675f25d4
TI		 1475 struct azx_dev *azx_dev, u32 **bdlp,
1476 int ofs, int size, int with_ioc)
1477{
675f25d4
TI		 1478 u32 *bdl = *bdlp;
1479
1480 while (size > 0) {
1481 dma_addr_t addr;
1482 int chunk;
1483
1484 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1485 return -EINVAL;
1486
1d1a4564 1487 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1488 /* program the address field of the BDL entry */
1489 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1490 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1491 /* program the size field of the BDL entry */
1d1a4564 1492 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1493 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1494 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1495 u32 remain = 0x1000 - (ofs & 0xfff);
1496 if (chunk > remain)
1497 chunk = remain;
1498 }
675f25d4
TI		 1499 bdl[2] = cpu_to_le32(chunk);
1500 /* program the IOC to enable interrupt
1501 * only when the whole fragment is processed
1502 */
1503 size -= chunk;
1504 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1505 bdl += 4;
1506 azx_dev->frags++;
1507 ofs += chunk;
1508 }
1509 *bdlp = bdl;
1510 return ofs;
1511}
1512
1da177e4
LT		 1513/*
1514 * set up BDL entries
1515 */
555e219f
TI		 1516static int azx_setup_periods(struct azx *chip,
1517 struct snd_pcm_substream *substream,
4ce107b9 1518 struct azx_dev *azx_dev)
1da177e4 1519{
4ce107b9
TI		 1520 u32 *bdl;
1521 int i, ofs, periods, period_bytes;
555e219f 1522 int pos_adj;
1da177e4
LT		 1523
1524 /* reset BDL address */
1525 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1526 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1527
97b71c94 1528 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1529 periods = azx_dev->bufsize / period_bytes;
1530
1da177e4 1531 /* program the initial BDL entries */
4ce107b9
TI		 1532 bdl = (u32 *)azx_dev->bdl.area;
1533 ofs = 0;
1534 azx_dev->frags = 0;
555e219f 1535 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1536 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1537 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1538 int pos_align = pos_adj;
555e219f 1539 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1540 if (!pos_adj)
e785d3d8
TI		 1541 pos_adj = pos_align;
1542 else
1543 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1544 pos_align;
675f25d4
TI		 1545 pos_adj = frames_to_bytes(runtime, pos_adj);
1546 if (pos_adj >= period_bytes) {
445a51b3
DB		 1547 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1548 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1549 pos_adj = 0;
1550 } else {
1d1a4564
TI		 1551 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1552 azx_dev,
915bf29e 1553 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1554 if (ofs < 0)
1555 goto error;
4ce107b9 1556 }
555e219f
TI		 1557 } else
1558 pos_adj = 0;
675f25d4
TI		 1559 for (i = 0; i < periods; i++) {
1560 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1561 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1562 azx_dev, &bdl, ofs,
675f25d4
TI		 1563 period_bytes - pos_adj, 0);
1564 else
1d1a4564
TI		 1565 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1566 azx_dev, &bdl, ofs,
7bb8fb70 1567 period_bytes,
915bf29e 1568 !azx_dev->no_period_wakeup);
675f25d4
TI		 1569 if (ofs < 0)
1570 goto error;
1da177e4 1571 }
4ce107b9 1572 return 0;
675f25d4
TI		 1573
1574 error:
445a51b3
DB		 1575 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1576 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1577 return -EINVAL;
1da177e4
LT		 1578}
1579
1dddab40
TI		 1580/* reset stream */
1581static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1582{
1583 unsigned char val;
1584 int timeout;
1585
1dddab40
TI		 1586 azx_stream_clear(chip, azx_dev);
1587
d01ce99f
TI		 1588 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1589 SD_CTL_STREAM_RESET);
1da177e4
LT		 1590 udelay(3);
1591 timeout = 300;
1592 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1593 --timeout)
1594 ;
1595 val &= ~SD_CTL_STREAM_RESET;
1596 azx_sd_writeb(azx_dev, SD_CTL, val);
1597 udelay(3);
1598
1599 timeout = 300;
1600 /* waiting for hardware to report that the stream is out of reset */
1601 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1602 --timeout)
1603 ;
fa00e046
JK		 1604
1605 /* reset first position - may not be synced with hw at this time */
1606 *azx_dev->posbuf = 0;
1dddab40 1607}
1da177e4 1608
1dddab40
TI		 1609/*
1610 * set up the SD for streaming
1611 */
1612static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1613{
27fe48d9 1614 unsigned int val;
1dddab40
TI		 1615 /* make sure the run bit is zero for SD */
1616 azx_stream_clear(chip, azx_dev);
1da177e4 1617 /* program the stream_tag */
27fe48d9
TI		 1618 val = azx_sd_readl(azx_dev, SD_CTL);
1619 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1620 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1621 if (!azx_snoop(chip))
1622 val |= SD_CTL_TRAFFIC_PRIO;
1623 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1624
1625 /* program the length of samples in cyclic buffer */
1626 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1627
1628 /* program the stream format */
1629 /* this value needs to be the same as the one programmed */
1630 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1631
1632 /* program the stream LVI (last valid index) of the BDL */
1633 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1634
1635 /* program the BDL address */
1636 /* lower BDL address */
4ce107b9 1637 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1638 /* upper BDL address */
766979e0 1639 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1640
0be3b5d3 1641 /* enable the position buffer */
4cb36310
DH		 1642 if (chip->position_fix[0] != POS_FIX_LPIB ||
1643 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1644 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1645 azx_writel(chip, DPLBASE,
1646 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1647 }
c74db86b 1648
1da177e4 1649 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1650 azx_sd_writel(azx_dev, SD_CTL,
1651 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1652
1653 return 0;
1654}
1655
6ce4a3bc
TI		 1656/*
1657 * Probe the given codec address
1658 */
1659static int probe_codec(struct azx *chip, int addr)
1660{
1661 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1662 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1663 unsigned int res;
1664
a678cdee 1665 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1666 chip->probing = 1;
1667 azx_send_cmd(chip->bus, cmd);
deadff16 1668 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1669 chip->probing = 0;
a678cdee 1670 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1671 if (res == -1)
1672 return -EIO;
445a51b3 1673 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1674 return 0;
1675}
1676
33fa35ed
TI		 1677static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1678 struct hda_pcm *cpcm);
6ce4a3bc 1679static void azx_stop_chip(struct azx *chip);
1da177e4 1680
8dd78330
TI		 1681static void azx_bus_reset(struct hda_bus *bus)
1682{
1683 struct azx *chip = bus->private_data;
8dd78330
TI		 1684
1685 bus->in_reset = 1;
1686 azx_stop_chip(chip);
cd508fe5 1687 azx_init_chip(chip, 1);
65f75983 1688#ifdef CONFIG_PM
8dd78330 1689 if (chip->initialized) {
01b65bfb
TI		 1690 struct azx_pcm *p;
1691 list_for_each_entry(p, &chip->pcm_list, list)
1692 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1693 snd_hda_suspend(chip->bus);
1694 snd_hda_resume(chip->bus);
1695 }
65f75983 1696#endif
8dd78330
TI		 1697 bus->in_reset = 0;
1698}
1699
26a6cb6c
DH		 1700static int get_jackpoll_interval(struct azx *chip)
1701{
1702 int i = jackpoll_ms[chip->dev_index];
1703 unsigned int j;
1704 if (i == 0)
1705 return 0;
1706 if (i < 50 || i > 60000)
1707 j = 0;
1708 else
1709 j = msecs_to_jiffies(i);
1710 if (j == 0)
1711 snd_printk(KERN_WARNING SFX
1712 "jackpoll_ms value out of range: %d\n", i);
1713 return j;
1714}
1715
1da177e4
LT		 1716/*
1717 * Codec initialization
1718 */
1719
2f5983f2 1720/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1721static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1722 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1723 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1724};
1725
48c8b0eb 1726static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1727{
1728 struct hda_bus_template bus_temp;
34c25350
TI		 1729 int c, codecs, err;
1730 int max_slots;
1da177e4
LT		 1731
1732 memset(&bus_temp, 0, sizeof(bus_temp));
1733 bus_temp.private_data = chip;
1734 bus_temp.modelname = model;
1735 bus_temp.pci = chip->pci;
111d3af5
TI		 1736 bus_temp.ops.command = azx_send_cmd;
1737 bus_temp.ops.get_response = azx_get_response;
176d5335 1738 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1739 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1740#ifdef CONFIG_PM
11cd41b8 1741 bus_temp.power_save = &power_save;
cb53c626
TI		 1742 bus_temp.ops.pm_notify = azx_power_notify;
1743#endif
1d1a4564
TI		 1744#ifdef CONFIG_SND_HDA_DSP_LOADER
1745 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1746 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1747 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1748#endif
1da177e4 1749
d01ce99f
TI		 1750 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1751 if (err < 0)
1da177e4
LT		 1752 return err;
1753
9477c58e 1754 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1755 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1756 chip->bus->needs_damn_long_delay = 1;
9477c58e 1757 }
dc9c8e21 1758
34c25350 1759 codecs = 0;
2f5983f2
TI		 1760 max_slots = azx_max_codecs[chip->driver_type];
1761 if (!max_slots)
7445dfc1 1762 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1763
1764 /* First try to probe all given codec slots */
1765 for (c = 0; c < max_slots; c++) {
f1eaaeec 1766 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1767 if (probe_codec(chip, c) < 0) {
1768 /* Some BIOSen give you wrong codec addresses
1769 * that don't exist
1770 */
4abc1cc2 1771 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1772 "%s: Codec #%d probe error; "
1773 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1774 chip->codec_mask &= ~(1 << c);
1775 /* More badly, accessing to a non-existing
1776 * codec often screws up the controller chip,
2448158e 1777 * and disturbs the further communications.
6ce4a3bc
TI		 1778 * Thus if an error occurs during probing,
1779 * better to reset the controller chip to
1780 * get back to the sanity state.
1781 */
1782 azx_stop_chip(chip);
cd508fe5 1783 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1784 }
1785 }
1786 }
1787
d507cd66
TI		 1788 /* AMD chipsets often cause the communication stalls upon certain
1789 * sequence like the pin-detection. It seems that forcing the synced
1790 * access works around the stall. Grrr...
1791 */
9477c58e 1792 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1793 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1794 pci_name(chip->pci));
d507cd66
TI		 1795 chip->bus->sync_write = 1;
1796 chip->bus->allow_bus_reset = 1;
1797 }
1798
6ce4a3bc 1799 /* Then create codec instances */
34c25350 1800 for (c = 0; c < max_slots; c++) {
f1eaaeec 1801 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1802 struct hda_codec *codec;
a1e21c90 1803 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1804 if (err < 0)
1805 continue;
26a6cb6c 1806 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1807 codec->beep_mode = chip->beep_mode;
1da177e4 1808 codecs++;
19a982b6
TI		 1809 }
1810 }
1811 if (!codecs) {
445a51b3 1812 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1813 return -ENXIO;
1814 }
a1e21c90
TI		 1815 return 0;
1816}
1da177e4 1817
a1e21c90 1818/* configure each codec instance */
e23e7a14 1819static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1820{
1821 struct hda_codec *codec;
1822 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1823 snd_hda_codec_configure(codec);
1824 }
1da177e4
LT		 1825 return 0;
1826}
1827
1828
1829/*
1830 * PCM support
1831 */
1832
1833/* assign a stream for the PCM */
ef18bede
WF		 1834static inline struct azx_dev *
1835azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1836{
07e4ca50 1837 int dev, i, nums;
ef18bede 1838 struct azx_dev *res = NULL;
d5cf9911
TI		 1839 /* make a non-zero unique key for the substream */
1840 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1841 (substream->stream + 1);
ef18bede
WF		 1842
1843 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1844 dev = chip->playback_index_offset;
1845 nums = chip->playback_streams;
1846 } else {
1847 dev = chip->capture_index_offset;
1848 nums = chip->capture_streams;
1849 }
eb49faa6
TI		 1850 for (i = 0; i < nums; i++, dev++) {
1851 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1852 dsp_lock(azx_dev);
1853 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1854 res = azx_dev;
1855 if (res->assigned_key == key) {
1856 res->opened = 1;
1857 res->assigned_key = key;
1858 dsp_unlock(azx_dev);
1859 return azx_dev;
1860 }
1da177e4 1861 }
eb49faa6
TI		 1862 dsp_unlock(azx_dev);
1863 }
ef18bede 1864 if (res) {
eb49faa6 1865 dsp_lock(res);
ef18bede 1866 res->opened = 1;
d5cf9911 1867 res->assigned_key = key;
eb49faa6 1868 dsp_unlock(res);
ef18bede
WF		 1869 }
1870 return res;
1da177e4
LT		 1871}
1872
1873/* release the assigned stream */
a98f90fd 1874static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1875{
1876 azx_dev->opened = 0;
1877}
1878
5d890f59
PLB		 1879static cycle_t azx_cc_read(const struct cyclecounter *cc)
1880{
1881 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1882 struct snd_pcm_substream *substream = azx_dev->substream;
1883 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1884 struct azx *chip = apcm->chip;
1885
1886 return azx_readl(chip, WALLCLK);
1887}
1888
1889static void azx_timecounter_init(struct snd_pcm_substream *substream,
1890 bool force, cycle_t last)
1891{
1892 struct azx_dev *azx_dev = get_azx_dev(substream);
1893 struct timecounter *tc = &azx_dev->azx_tc;
1894 struct cyclecounter *cc = &azx_dev->azx_cc;
1895 u64 nsec;
1896
1897 cc->read = azx_cc_read;
1898 cc->mask = CLOCKSOURCE_MASK(32);
1899
1900 /*
1901 * Converting from 24 MHz to ns means applying a 125/3 factor.
1902 * To avoid any saturation issues in intermediate operations,
1903 * the 125 factor is applied first. The division is applied
1904 * last after reading the timecounter value.
1905 * Applying the 1/3 factor as part of the multiplication
1906 * requires at least 20 bits for a decent precision, however
1907 * overflows occur after about 4 hours or less, not a option.
1908 */
1909
1910 cc->mult = 125; /* saturation after 195 years */
1911 cc->shift = 0;
1912
1913 nsec = 0; /* audio time is elapsed time since trigger */
1914 timecounter_init(tc, cc, nsec);
1915 if (force)
1916 /*
1917 * force timecounter to use predefined value,
1918 * used for synchronized starts
1919 */
1920 tc->cycle_last = last;
1921}
1922
ae03bbb8 1923static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1924 u64 nsec)
1925{
1926 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1927 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1928 u64 codec_frames, codec_nsecs;
1929
1930 if (!hinfo->ops.get_delay)
1931 return nsec;
1932
1933 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1934 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1935 substream->runtime->rate);
1936
ae03bbb8
DR		 1937 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1938 return nsec + codec_nsecs;
1939
78daea29
DR		 1940 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1941}
1942
5d890f59
PLB		 1943static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1944 struct timespec *ts)
1945{
1946 struct azx_dev *azx_dev = get_azx_dev(substream);
1947 u64 nsec;
1948
1949 nsec = timecounter_read(&azx_dev->azx_tc);
1950 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1951 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1952
1953 *ts = ns_to_timespec(nsec);
1954
1955 return 0;
1956}
1957
a98f90fd 1958static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1959 .info = (SNDRV_PCM_INFO_MMAP |
1960 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1961 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1962 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1963 /* No full-resume yet implemented */
1964 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1965 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1966 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1967 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1968 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1969 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1970 .rates = SNDRV_PCM_RATE_48000,
1971 .rate_min = 48000,
1972 .rate_max = 48000,
1973 .channels_min = 2,
1974 .channels_max = 2,
1975 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1976 .period_bytes_min = 128,
1977 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1978 .periods_min = 2,
1979 .periods_max = AZX_MAX_FRAG,
1980 .fifo_size = 0,
1981};
1982
a98f90fd 1983static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1984{
1985 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1986 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1987 struct azx *chip = apcm->chip;
1988 struct azx_dev *azx_dev;
1989 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1990 unsigned long flags;
1991 int err;
2ae66c26 1992 int buff_step;
1da177e4 1993
62932df8 1994 mutex_lock(&chip->open_mutex);
ef18bede 1995 azx_dev = azx_assign_device(chip, substream);
1da177e4 1996 if (azx_dev == NULL) {
62932df8 1997 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1998 return -EBUSY;
1999 }
2000 runtime->hw = azx_pcm_hw;
2001 runtime->hw.channels_min = hinfo->channels_min;
2002 runtime->hw.channels_max = hinfo->channels_max;
2003 runtime->hw.formats = hinfo->formats;
2004 runtime->hw.rates = hinfo->rates;
2005 snd_pcm_limit_hw_rates(runtime);
2006 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 2007
2008 /* avoid wrap-around with wall-clock */
2009 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2010 20,
2011 178000000);
2012
52409aa6 2013 if (chip->align_buffer_size)
2ae66c26
PLB		 2014 /* constrain buffer sizes to be multiple of 128
2015 bytes. This is more efficient in terms of memory
2016 access but isn't required by the HDA spec and
2017 prevents users from specifying exact period/buffer
2018 sizes. For example for 44.1kHz, a period size set
2019 to 20ms will be rounded to 19.59ms. */
2020 buff_step = 128;
2021 else
2022 /* Don't enforce steps on buffer sizes, still need to
2023 be multiple of 4 bytes (HDA spec). Tested on Intel
2024 HDA controllers, may not work on all devices where
2025 option needs to be disabled */
2026 buff_step = 4;
2027
5f1545bc 2028 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2029 buff_step);
5f1545bc 2030 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2031 buff_step);
b4a91cf0 2032 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2033 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2034 if (err < 0) {
1da177e4 2035 azx_release_device(azx_dev);
cb53c626 2036 snd_hda_power_down(apcm->codec);
62932df8 2037 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2038 return err;
2039 }
70d321e6 2040 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2041 /* sanity check */
2042 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2043 snd_BUG_ON(!runtime->hw.channels_max) ||
2044 snd_BUG_ON(!runtime->hw.formats) ||
2045 snd_BUG_ON(!runtime->hw.rates)) {
2046 azx_release_device(azx_dev);
2047 hinfo->ops.close(hinfo, apcm->codec, substream);
2048 snd_hda_power_down(apcm->codec);
2049 mutex_unlock(&chip->open_mutex);
2050 return -EINVAL;
2051 }
5d890f59
PLB		 2052
2053 /* disable WALLCLOCK timestamps for capture streams
2054 until we figure out how to handle digital inputs */
2055 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2056 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2057
1da177e4
LT		 2058 spin_lock_irqsave(&chip->reg_lock, flags);
2059 azx_dev->substream = substream;
2060 azx_dev->running = 0;
2061 spin_unlock_irqrestore(&chip->reg_lock, flags);
2062
2063 runtime->private_data = azx_dev;
850f0e52 2064 snd_pcm_set_sync(substream);
62932df8 2065 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2066 return 0;
2067}
2068
a98f90fd 2069static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2070{
2071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2072 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2073 struct azx *chip = apcm->chip;
2074 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2075 unsigned long flags;
2076
62932df8 2077 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2078 spin_lock_irqsave(&chip->reg_lock, flags);
2079 azx_dev->substream = NULL;
2080 azx_dev->running = 0;
2081 spin_unlock_irqrestore(&chip->reg_lock, flags);
2082 azx_release_device(azx_dev);
2083 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2084 snd_hda_power_down(apcm->codec);
62932df8 2085 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2086 return 0;
2087}
2088
d01ce99f
TI		 2089static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2090 struct snd_pcm_hw_params *hw_params)
1da177e4 2091{
27fe48d9
TI		 2092 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2093 struct azx *chip = apcm->chip;
97b71c94 2094 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2095 int ret;
97b71c94 2096
eb49faa6
TI		 2097 dsp_lock(azx_dev);
2098 if (dsp_is_locked(azx_dev)) {
2099 ret = -EBUSY;
2100 goto unlock;
2101 }
2102
9ddf1aeb 2103 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2104 azx_dev->bufsize = 0;
2105 azx_dev->period_bytes = 0;
2106 azx_dev->format_val = 0;
27fe48d9 2107 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2108 params_buffer_bytes(hw_params));
27fe48d9 2109 if (ret < 0)
eb49faa6 2110 goto unlock;
9ddf1aeb 2111 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2112 unlock:
2113 dsp_unlock(azx_dev);
27fe48d9 2114 return ret;
1da177e4
LT		 2115}
2116
a98f90fd 2117static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2118{
2119 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2120 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2121 struct azx *chip = apcm->chip;
1da177e4
LT		 2122 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2123
2124 /* reset BDL address */
eb49faa6
TI		 2125 dsp_lock(azx_dev);
2126 if (!dsp_is_locked(azx_dev)) {
2127 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2128 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2129 azx_sd_writel(azx_dev, SD_CTL, 0);
2130 azx_dev->bufsize = 0;
2131 azx_dev->period_bytes = 0;
2132 azx_dev->format_val = 0;
2133 }
1da177e4 2134
eb541337 2135 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2136
9ddf1aeb 2137 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2138 azx_dev->prepared = 0;
2139 dsp_unlock(azx_dev);
1da177e4
LT		 2140 return snd_pcm_lib_free_pages(substream);
2141}
2142
a98f90fd 2143static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2144{
2145 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2146 struct azx *chip = apcm->chip;
2147 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2148 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2149 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2150 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2151 int err;
7c935976
SW		 2152 struct hda_spdif_out *spdif =
2153 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2154 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2155
eb49faa6
TI		 2156 dsp_lock(azx_dev);
2157 if (dsp_is_locked(azx_dev)) {
2158 err = -EBUSY;
2159 goto unlock;
2160 }
2161
fa00e046 2162 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2163 format_val = snd_hda_calc_stream_format(runtime->rate,
2164 runtime->channels,
2165 runtime->format,
32c168c8 2166 hinfo->maxbps,
7c935976 2167 ctls);
97b71c94 2168 if (!format_val) {
d01ce99f 2169 snd_printk(KERN_ERR SFX
445a51b3
DB		 2170 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2171 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2172 err = -EINVAL;
2173 goto unlock;
1da177e4
LT		 2174 }
2175
97b71c94
TI		 2176 bufsize = snd_pcm_lib_buffer_bytes(substream);
2177 period_bytes = snd_pcm_lib_period_bytes(substream);
2178
445a51b3
DB		 2179 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2180 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2181
2182 if (bufsize != azx_dev->bufsize ||
2183 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2184 format_val != azx_dev->format_val ||
2185 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2186 azx_dev->bufsize = bufsize;
2187 azx_dev->period_bytes = period_bytes;
2188 azx_dev->format_val = format_val;
915bf29e 2189 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2190 err = azx_setup_periods(chip, substream, azx_dev);
2191 if (err < 0)
eb49faa6 2192 goto unlock;
97b71c94
TI		 2193 }
2194
e8648e5e
TI		 2195 /* when LPIB delay correction gives a small negative value,
2196 * we ignore it; currently set the threshold statically to
2197 * 64 frames
2198 */
2199 if (runtime->period_size > 64)
2200 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
2201 else
2202 azx_dev->delay_negative_threshold = 0;
2203
e5463720
JK		 2204 /* wallclk has 24Mhz clock source */
2205 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2206 runtime->rate) * 1000);
1da177e4
LT		 2207 azx_setup_controller(chip, azx_dev);
2208 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2209 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2210 else
2211 azx_dev->fifo_size = 0;
2212
62b7e5e0
TI		 2213 stream_tag = azx_dev->stream_tag;
2214 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2215 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2216 stream_tag > chip->capture_streams)
2217 stream_tag -= chip->capture_streams;
eb49faa6 2218 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2219 azx_dev->format_val, substream);
eb49faa6
TI		 2220
2221 unlock:
2222 if (!err)
2223 azx_dev->prepared = 1;
2224 dsp_unlock(azx_dev);
2225 return err;
1da177e4
LT		 2226}
2227
a98f90fd 2228static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2229{
2230 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2231 struct azx *chip = apcm->chip;
850f0e52
TI		 2232 struct azx_dev *azx_dev;
2233 struct snd_pcm_substream *s;
fa00e046 2234 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2235 int nwait, timeout;
1da177e4 2236
1a8506d4
TI		 2237 azx_dev = get_azx_dev(substream);
2238 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2239
eb49faa6
TI		 2240 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2241 return -EPIPE;
2242
1da177e4 2243 switch (cmd) {
fa00e046
JK		 2244 case SNDRV_PCM_TRIGGER_START:
2245 rstart = 1;
1da177e4
LT		 2246 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2247 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2248 start = 1;
1da177e4
LT		 2249 break;
2250 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2251 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2252 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2253 start = 0;
1da177e4
LT		 2254 break;
2255 default:
850f0e52
TI		 2256 return -EINVAL;
2257 }
2258
2259 snd_pcm_group_for_each_entry(s, substream) {
2260 if (s->pcm->card != substream->pcm->card)
2261 continue;
2262 azx_dev = get_azx_dev(s);
2263 sbits |= 1 << azx_dev->index;
2264 nsync++;
2265 snd_pcm_trigger_done(s, substream);
2266 }
2267
2268 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2269
2270 /* first, set SYNC bits of corresponding streams */
2271 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2272 azx_writel(chip, OLD_SSYNC,
2273 azx_readl(chip, OLD_SSYNC) | sbits);
2274 else
2275 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2276
850f0e52
TI		 2277 snd_pcm_group_for_each_entry(s, substream) {
2278 if (s->pcm->card != substream->pcm->card)
2279 continue;
2280 azx_dev = get_azx_dev(s);
e5463720
JK		 2281 if (start) {
2282 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2283 if (!rstart)
2284 azx_dev->start_wallclk -=
2285 azx_dev->period_wallclk;
850f0e52 2286 azx_stream_start(chip, azx_dev);
e5463720 2287 } else {
850f0e52 2288 azx_stream_stop(chip, azx_dev);
e5463720 2289 }
850f0e52 2290 azx_dev->running = start;
1da177e4
LT		 2291 }
2292 spin_unlock(&chip->reg_lock);
850f0e52 2293 if (start) {
850f0e52
TI		 2294 /* wait until all FIFOs get ready */
2295 for (timeout = 5000; timeout; timeout--) {
2296 nwait = 0;
2297 snd_pcm_group_for_each_entry(s, substream) {
2298 if (s->pcm->card != substream->pcm->card)
2299 continue;
2300 azx_dev = get_azx_dev(s);
2301 if (!(azx_sd_readb(azx_dev, SD_STS) &
2302 SD_STS_FIFO_READY))
2303 nwait++;
2304 }
2305 if (!nwait)
2306 break;
2307 cpu_relax();
2308 }
2309 } else {
2310 /* wait until all RUN bits are cleared */
2311 for (timeout = 5000; timeout; timeout--) {
2312 nwait = 0;
2313 snd_pcm_group_for_each_entry(s, substream) {
2314 if (s->pcm->card != substream->pcm->card)
2315 continue;
2316 azx_dev = get_azx_dev(s);
2317 if (azx_sd_readb(azx_dev, SD_CTL) &
2318 SD_CTL_DMA_START)
2319 nwait++;
2320 }
2321 if (!nwait)
2322 break;
2323 cpu_relax();
2324 }
1da177e4 2325 }
172d3b20
PLB		 2326 spin_lock(&chip->reg_lock);
2327 /* reset SYNC bits */
2328 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2329 azx_writel(chip, OLD_SSYNC,
2330 azx_readl(chip, OLD_SSYNC) & ~sbits);
2331 else
2332 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2333 if (start) {
2334 azx_timecounter_init(substream, 0, 0);
2335 if (nsync > 1) {
2336 cycle_t cycle_last;
2337
2338 /* same start cycle for master and group */
2339 azx_dev = get_azx_dev(substream);
2340 cycle_last = azx_dev->azx_tc.cycle_last;
2341
2342 snd_pcm_group_for_each_entry(s, substream) {
2343 if (s->pcm->card != substream->pcm->card)
2344 continue;
2345 azx_timecounter_init(s, 1, cycle_last);
2346 }
2347 }
2348 }
172d3b20 2349 spin_unlock(&chip->reg_lock);
850f0e52 2350 return 0;
1da177e4
LT		 2351}
2352
0e153474
JC		 2353/* get the current DMA position with correction on VIA chips */
2354static unsigned int azx_via_get_position(struct azx *chip,
2355 struct azx_dev *azx_dev)
2356{
2357 unsigned int link_pos, mini_pos, bound_pos;
2358 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2359 unsigned int fifo_size;
2360
2361 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2362 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2363 /* Playback, no problem using link position */
2364 return link_pos;
2365 }
2366
2367 /* Capture */
2368 /* For new chipset,
2369 * use mod to get the DMA position just like old chipset
2370 */
2371 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2372 mod_dma_pos %= azx_dev->period_bytes;
2373
2374 /* azx_dev->fifo_size can't get FIFO size of in stream.
2375 * Get from base address + offset.
2376 */
2377 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2378
2379 if (azx_dev->insufficient) {
2380 /* Link position never gather than FIFO size */
2381 if (link_pos <= fifo_size)
2382 return 0;
2383
2384 azx_dev->insufficient = 0;
2385 }
2386
2387 if (link_pos <= fifo_size)
2388 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2389 else
2390 mini_pos = link_pos - fifo_size;
2391
2392 /* Find nearest previous boudary */
2393 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2394 mod_link_pos = link_pos % azx_dev->period_bytes;
2395 if (mod_link_pos >= fifo_size)
2396 bound_pos = link_pos - mod_link_pos;
2397 else if (mod_dma_pos >= mod_mini_pos)
2398 bound_pos = mini_pos - mod_mini_pos;
2399 else {
2400 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2401 if (bound_pos >= azx_dev->bufsize)
2402 bound_pos = 0;
2403 }
2404
2405 /* Calculate real DMA position we want */
2406 return bound_pos + mod_dma_pos;
2407}
2408
9ad593f6 2409static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2410 struct azx_dev *azx_dev,
2411 bool with_check)
1da177e4 2412{
21229613
TI		 2413 struct snd_pcm_substream *substream = azx_dev->substream;
2414 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2415 unsigned int pos;
21229613
TI		 2416 int stream = substream->stream;
2417 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2418 int delay = 0;
1da177e4 2419
4cb36310
DH		 2420 switch (chip->position_fix[stream]) {
2421 case POS_FIX_LPIB:
2422 /* read LPIB */
2423 pos = azx_sd_readl(azx_dev, SD_LPIB);
2424 break;
2425 case POS_FIX_VIACOMBO:
0e153474 2426 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2427 break;
2428 default:
2429 /* use the position buffer */
2430 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2431 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2432 if (!pos || pos == (u32)-1) {
2433 printk(KERN_WARNING
2434 "hda-intel: Invalid position buffer, "
2435 "using LPIB read method instead.\n");
2436 chip->position_fix[stream] = POS_FIX_LPIB;
2437 pos = azx_sd_readl(azx_dev, SD_LPIB);
2438 } else
2439 chip->position_fix[stream] = POS_FIX_POSBUF;
2440 }
2441 break;
c74db86b 2442 }
4cb36310 2443
1da177e4
LT		 2444 if (pos >= azx_dev->bufsize)
2445 pos = 0;
90accc58
PLB		 2446
2447 /* calculate runtime delay from LPIB */
21229613 2448 if (substream->runtime &&
90accc58
PLB		 2449 chip->position_fix[stream] == POS_FIX_POSBUF &&
2450 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2451 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2452 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2453 delay = pos - lpib_pos;
2454 else
2455 delay = lpib_pos - pos;
e8648e5e
TI		 2456 if (delay < 0) {
2457 if (delay >= azx_dev->delay_negative_threshold)
2458 delay = 0;
2459 else
2460 delay += azx_dev->bufsize;
2461 }
90accc58 2462 if (delay >= azx_dev->period_bytes) {
1f04661f 2463 snd_printk(KERN_WARNING SFX
445a51b3 2464 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2465 "disabling LPIB delay counting\n",
445a51b3 2466 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2467 delay = 0;
2468 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2469 }
21229613 2470 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2471 }
21229613
TI		 2472
2473 if (substream->runtime) {
2474 if (hinfo->ops.get_delay)
2475 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2476 substream);
2477 substream->runtime->delay = delay;
2478 }
2479
1a8506d4 2480 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2481 return pos;
2482}
2483
2484static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2485{
2486 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2487 struct azx *chip = apcm->chip;
2488 struct azx_dev *azx_dev = get_azx_dev(substream);
2489 return bytes_to_frames(substream->runtime,
798cb7e8 2490 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2491}
2492
2493/*
2494 * Check whether the current DMA position is acceptable for updating
2495 * periods. Returns non-zero if it's OK.
2496 *
2497 * Many HD-audio controllers appear pretty inaccurate about
2498 * the update-IRQ timing. The IRQ is issued before actually the
2499 * data is processed. So, we need to process it afterwords in a
2500 * workqueue.
2501 */
2502static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2503{
e5463720 2504 u32 wallclk;
9ad593f6
TI		 2505 unsigned int pos;
2506
f48f606d
JK		 2507 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2508 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2509 return -1; /* bogus (too early) interrupt */
fa00e046 2510
798cb7e8 2511 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2512
d6d8bf54
TI		 2513 if (WARN_ONCE(!azx_dev->period_bytes,
2514 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2515 return -1; /* this shouldn't happen! */
edb39935 2516 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2517 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2518 /* NG - it's below the first next period boundary */
2519 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2520 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2521 return 1; /* OK, it's fine */
2522}
2523
2524/*
2525 * The work for pending PCM period updates.
2526 */
2527static void azx_irq_pending_work(struct work_struct *work)
2528{
2529 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2530 int i, pending, ok;
9ad593f6 2531
a6a950a8
TI		 2532 if (!chip->irq_pending_warned) {
2533 printk(KERN_WARNING
2534 "hda-intel: IRQ timing workaround is activated "
2535 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2536 chip->card->number);
2537 chip->irq_pending_warned = 1;
2538 }
2539
9ad593f6
TI		 2540 for (;;) {
2541 pending = 0;
2542 spin_lock_irq(&chip->reg_lock);
2543 for (i = 0; i < chip->num_streams; i++) {
2544 struct azx_dev *azx_dev = &chip->azx_dev[i];
2545 if (!azx_dev->irq_pending ||
2546 !azx_dev->substream ||
2547 !azx_dev->running)
2548 continue;
e5463720
JK		 2549 ok = azx_position_ok(chip, azx_dev);
2550 if (ok > 0) {
9ad593f6
TI		 2551 azx_dev->irq_pending = 0;
2552 spin_unlock(&chip->reg_lock);
2553 snd_pcm_period_elapsed(azx_dev->substream);
2554 spin_lock(&chip->reg_lock);
e5463720
JK		 2555 } else if (ok < 0) {
2556 pending = 0; /* too early */
9ad593f6
TI		 2557 } else
2558 pending++;
2559 }
2560 spin_unlock_irq(&chip->reg_lock);
2561 if (!pending)
2562 return;
08af495f 2563 msleep(1);
9ad593f6
TI		 2564 }
2565}
2566
2567/* clear irq_pending flags and assure no on-going workq */
2568static void azx_clear_irq_pending(struct azx *chip)
2569{
2570 int i;
2571
2572 spin_lock_irq(&chip->reg_lock);
2573 for (i = 0; i < chip->num_streams; i++)
2574 chip->azx_dev[i].irq_pending = 0;
2575 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2576}
2577
27fe48d9
TI		 2578#ifdef CONFIG_X86
2579static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2580 struct vm_area_struct *area)
2581{
2582 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2583 struct azx *chip = apcm->chip;
2584 if (!azx_snoop(chip))
2585 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2586 return snd_pcm_lib_default_mmap(substream, area);
2587}
2588#else
2589#define azx_pcm_mmap NULL
2590#endif
2591
a98f90fd 2592static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2593 .open = azx_pcm_open,
2594 .close = azx_pcm_close,
2595 .ioctl = snd_pcm_lib_ioctl,
2596 .hw_params = azx_pcm_hw_params,
2597 .hw_free = azx_pcm_hw_free,
2598 .prepare = azx_pcm_prepare,
2599 .trigger = azx_pcm_trigger,
2600 .pointer = azx_pcm_pointer,
5d890f59 2601 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2602 .mmap = azx_pcm_mmap,
4ce107b9 2603 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2604};
2605
a98f90fd 2606static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2607{
176d5335
TI		 2608 struct azx_pcm *apcm = pcm->private_data;
2609 if (apcm) {
01b65bfb 2610 list_del(&apcm->list);
176d5335
TI		 2611 kfree(apcm);
2612 }
1da177e4
LT		 2613}
2614
acfa634f
TI		 2615#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2616
176d5335 2617static int
33fa35ed
TI		 2618azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2619 struct hda_pcm *cpcm)
1da177e4 2620{
33fa35ed 2621 struct azx *chip = bus->private_data;
a98f90fd 2622 struct snd_pcm *pcm;
1da177e4 2623 struct azx_pcm *apcm;
176d5335 2624 int pcm_dev = cpcm->device;
acfa634f 2625 unsigned int size;
176d5335 2626 int s, err;
1da177e4 2627
01b65bfb
TI		 2628 list_for_each_entry(apcm, &chip->pcm_list, list) {
2629 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2630 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2631 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2632 return -EBUSY;
2633 }
176d5335
TI		 2634 }
2635 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2636 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2637 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2638 &pcm);
2639 if (err < 0)
2640 return err;
18cb7109 2641 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2642 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2643 if (apcm == NULL)
2644 return -ENOMEM;
2645 apcm->chip = chip;
01b65bfb 2646 apcm->pcm = pcm;
1da177e4 2647 apcm->codec = codec;
1da177e4
LT		 2648 pcm->private_data = apcm;
2649 pcm->private_free = azx_pcm_free;
176d5335
TI		 2650 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2651 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2652 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2653 cpcm->pcm = pcm;
2654 for (s = 0; s < 2; s++) {
2655 apcm->hinfo[s] = &cpcm->stream[s];
2656 if (cpcm->stream[s].substreams)
2657 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2658 }
2659 /* buffer pre-allocation */
acfa634f
TI		 2660 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2661 if (size > MAX_PREALLOC_SIZE)
2662 size = MAX_PREALLOC_SIZE;
4ce107b9 2663 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2664 snd_dma_pci_data(chip->pci),
acfa634f 2665 size, MAX_PREALLOC_SIZE);
13aeaf68
TI		 2666 /* link to codec */
2667 pcm->dev = &codec->dev;
1da177e4
LT		 2668 return 0;
2669}
2670
2671/*
2672 * mixer creation - all stuff is implemented in hda module
2673 */
e23e7a14 2674static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2675{
2676 return snd_hda_build_controls(chip->bus);
2677}
2678
2679
2680/*
2681 * initialize SD streams
2682 */
e23e7a14 2683static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2684{
2685 int i;
2686
2687 /* initialize each stream (aka device)
d01ce99f
TI		 2688 * assign the starting bdl address to each stream (device)
2689 * and initialize
1da177e4 2690 */
07e4ca50 2691 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2692 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2693 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2694 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2695 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2696 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2697 azx_dev->sd_int_sta_mask = 1 << i;
2698 /* stream tag: must be non-zero and unique */
2699 azx_dev->index = i;
2700 azx_dev->stream_tag = i + 1;
2701 }
2702
2703 return 0;
2704}
2705
68e7fffc
TI		 2706static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2707{
437a5a46
TI		 2708 if (request_irq(chip->pci->irq, azx_interrupt,
2709 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2710 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2711 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2712 "disabling device\n", chip->pci->irq);
2713 if (do_disconnect)
2714 snd_card_disconnect(chip->card);
2715 return -1;
2716 }
2717 chip->irq = chip->pci->irq;
69e13418 2718 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2719 return 0;
2720}
2721
1da177e4 2722
cb53c626
TI		 2723static void azx_stop_chip(struct azx *chip)
2724{
95e99fda 2725 if (!chip->initialized)
cb53c626
TI		 2726 return;
2727
2728 /* disable interrupts */
2729 azx_int_disable(chip);
2730 azx_int_clear(chip);
2731
2732 /* disable CORB/RIRB */
2733 azx_free_cmd_io(chip);
2734
2735 /* disable position buffer */
2736 azx_writel(chip, DPLBASE, 0);
2737 azx_writel(chip, DPUBASE, 0);
2738
2739 chip->initialized = 0;
2740}
2741
1d1a4564
TI		 2742#ifdef CONFIG_SND_HDA_DSP_LOADER
2743/*
2744 * DSP loading code (e.g. for CA0132)
2745 */
2746
2747/* use the first stream for loading DSP */
2748static struct azx_dev *
2749azx_get_dsp_loader_dev(struct azx *chip)
2750{
2751 return &chip->azx_dev[chip->playback_index_offset];
2752}
2753
2754static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2755 unsigned int byte_size,
2756 struct snd_dma_buffer *bufp)
2757{
2758 u32 *bdl;
2759 struct azx *chip = bus->private_data;
2760 struct azx_dev *azx_dev;
2761 int err;
2762
eb49faa6
TI		 2763 azx_dev = azx_get_dsp_loader_dev(chip);
2764
2765 dsp_lock(azx_dev);
2766 spin_lock_irq(&chip->reg_lock);
2767 if (azx_dev->running || azx_dev->locked) {
2768 spin_unlock_irq(&chip->reg_lock);
2769 err = -EBUSY;
2770 goto unlock;
2771 }
2772 azx_dev->prepared = 0;
2773 chip->saved_azx_dev = *azx_dev;
2774 azx_dev->locked = 1;
2775 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2776
2777 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2778 snd_dma_pci_data(chip->pci),
2779 byte_size, bufp);
2780 if (err < 0)
eb49faa6 2781 goto err_alloc;
1d1a4564 2782
b3667bd7 2783 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2784 azx_dev->bufsize = byte_size;
2785 azx_dev->period_bytes = byte_size;
2786 azx_dev->format_val = format;
2787
2788 azx_stream_reset(chip, azx_dev);
2789
2790 /* reset BDL address */
2791 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2792 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2793
2794 azx_dev->frags = 0;
2795 bdl = (u32 *)azx_dev->bdl.area;
2796 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2797 if (err < 0)
2798 goto error;
2799
2800 azx_setup_controller(chip, azx_dev);
eb49faa6 2801 dsp_unlock(azx_dev);
1d1a4564
TI		 2802 return azx_dev->stream_tag;
2803
2804 error:
b3667bd7
TI		 2805 mark_pages_wc(chip, bufp, false);
2806 snd_dma_free_pages(bufp);
eb49faa6
TI		 2807 err_alloc:
2808 spin_lock_irq(&chip->reg_lock);
2809 if (azx_dev->opened)
2810 *azx_dev = chip->saved_azx_dev;
2811 azx_dev->locked = 0;
2812 spin_unlock_irq(&chip->reg_lock);
2813 unlock:
2814 dsp_unlock(azx_dev);
1d1a4564
TI		 2815 return err;
2816}
2817
2818static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2819{
2820 struct azx *chip = bus->private_data;
2821 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2822
2823 if (start)
2824 azx_stream_start(chip, azx_dev);
2825 else
2826 azx_stream_stop(chip, azx_dev);
2827 azx_dev->running = start;
2828}
2829
2830static void azx_load_dsp_cleanup(struct hda_bus *bus,
2831 struct snd_dma_buffer *dmab)
2832{
2833 struct azx *chip = bus->private_data;
2834 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2835
eb49faa6 2836 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2837 return;
2838
eb49faa6 2839 dsp_lock(azx_dev);
1d1a4564
TI		 2840 /* reset BDL address */
2841 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2842 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2843 azx_sd_writel(azx_dev, SD_CTL, 0);
2844 azx_dev->bufsize = 0;
2845 azx_dev->period_bytes = 0;
2846 azx_dev->format_val = 0;
2847
b3667bd7 2848 mark_pages_wc(chip, dmab, false);
1d1a4564 2849 snd_dma_free_pages(dmab);
b3667bd7 2850 dmab->area = NULL;
1d1a4564 2851
eb49faa6
TI		 2852 spin_lock_irq(&chip->reg_lock);
2853 if (azx_dev->opened)
2854 *azx_dev = chip->saved_azx_dev;
2855 azx_dev->locked = 0;
2856 spin_unlock_irq(&chip->reg_lock);
2857 dsp_unlock(azx_dev);
1d1a4564
TI		 2858}
2859#endif /* CONFIG_SND_HDA_DSP_LOADER */
2860
83012a7c 2861#ifdef CONFIG_PM
cb53c626 2862/* power-up/down the controller */
68467f51 2863static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2864{
33fa35ed 2865 struct azx *chip = bus->private_data;
cb53c626 2866
2ea3c6a2
TI		 2867 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2868 return;
2869
68467f51 2870 if (power_up)
b8dfc462
ML		 2871 pm_runtime_get_sync(&chip->pci->dev);
2872 else
2873 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2874}
65fcd41d
TI		 2875
2876static DEFINE_MUTEX(card_list_lock);
2877static LIST_HEAD(card_list);
2878
2879static void azx_add_card_list(struct azx *chip)
2880{
2881 mutex_lock(&card_list_lock);
2882 list_add(&chip->list, &card_list);
2883 mutex_unlock(&card_list_lock);
2884}
2885
2886static void azx_del_card_list(struct azx *chip)
2887{
2888 mutex_lock(&card_list_lock);
2889 list_del_init(&chip->list);
2890 mutex_unlock(&card_list_lock);
2891}
2892
2893/* trigger power-save check at writing parameter */
2894static int param_set_xint(const char *val, const struct kernel_param *kp)
2895{
2896 struct azx *chip;
2897 struct hda_codec *c;
2898 int prev = power_save;
2899 int ret = param_set_int(val, kp);
2900
2901 if (ret || prev == power_save)
2902 return ret;
2903
2904 mutex_lock(&card_list_lock);
2905 list_for_each_entry(chip, &card_list, list) {
2906 if (!chip->bus || chip->disabled)
2907 continue;
2908 list_for_each_entry(c, &chip->bus->codec_list, list)
2909 snd_hda_power_sync(c);
2910 }
2911 mutex_unlock(&card_list_lock);
2912 return 0;
2913}
2914#else
2915#define azx_add_card_list(chip) /* NOP */
2916#define azx_del_card_list(chip) /* NOP */
83012a7c 2917#endif /* CONFIG_PM */
5c0b9bec 2918
7ccbde57 2919#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2920/*
2921 * power management
2922 */
68cb2b55 2923static int azx_suspend(struct device *dev)
1da177e4 2924{
68cb2b55
TI		 2925 struct pci_dev *pci = to_pci_dev(dev);
2926 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2927 struct azx *chip = card->private_data;
01b65bfb 2928 struct azx_pcm *p;
1da177e4 2929
c5c21523
TI		 2930 if (chip->disabled)
2931 return 0;
2932
421a1252 2933 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2934 azx_clear_irq_pending(chip);
01b65bfb
TI		 2935 list_for_each_entry(p, &chip->pcm_list, list)
2936 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2937 if (chip->initialized)
8dd78330 2938 snd_hda_suspend(chip->bus);
cb53c626 2939 azx_stop_chip(chip);
7295b264 2940 azx_enter_link_reset(chip);
30b35399 2941 if (chip->irq >= 0) {
43001c95 2942 free_irq(chip->irq, chip);
30b35399
TI		 2943 chip->irq = -1;
2944 }
68e7fffc 2945 if (chip->msi)
43001c95 2946 pci_disable_msi(chip->pci);
421a1252
TI		 2947 pci_disable_device(pci);
2948 pci_save_state(pci);
68cb2b55 2949 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2950 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2951 hda_display_power(false);
1da177e4
LT		 2952 return 0;
2953}
2954
68cb2b55 2955static int azx_resume(struct device *dev)
1da177e4 2956{
68cb2b55
TI		 2957 struct pci_dev *pci = to_pci_dev(dev);
2958 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2959 struct azx *chip = card->private_data;
1da177e4 2960
c5c21523
TI		 2961 if (chip->disabled)
2962 return 0;
2963
99a2008d
WX		 2964 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2965 hda_display_power(true);
d14a7e0b
TI		 2966 pci_set_power_state(pci, PCI_D0);
2967 pci_restore_state(pci);
30b35399
TI		 2968 if (pci_enable_device(pci) < 0) {
2969 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2970 "disabling device\n");
2971 snd_card_disconnect(card);
2972 return -EIO;
2973 }
2974 pci_set_master(pci);
68e7fffc
TI		 2975 if (chip->msi)
2976 if (pci_enable_msi(pci) < 0)
2977 chip->msi = 0;
2978 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2979 return -EIO;
cb53c626 2980 azx_init_pci(chip);
d804ad92 2981
7f30830b 2982 azx_init_chip(chip, 1);
d804ad92 2983
1da177e4 2984 snd_hda_resume(chip->bus);
421a1252 2985 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2986 return 0;
2987}
b8dfc462
ML		 2988#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2989
2990#ifdef CONFIG_PM_RUNTIME
2991static int azx_runtime_suspend(struct device *dev)
2992{
2993 struct snd_card *card = dev_get_drvdata(dev);
2994 struct azx *chip = card->private_data;
2995
246efa4a
DA		 2996 if (chip->disabled)
2997 return 0;
2998
2999 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3000 return 0;
3001
7d4f606c
WX		 3002 /* enable controller wake up event */
3003 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
3004 STATESTS_INT_MASK);
3005
b8dfc462 3006 azx_stop_chip(chip);
873ce8ad 3007 azx_enter_link_reset(chip);
b8dfc462 3008 azx_clear_irq_pending(chip);
99a2008d
WX		 3009 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3010 hda_display_power(false);
b8dfc462
ML		 3011 return 0;
3012}
3013
3014static int azx_runtime_resume(struct device *dev)
3015{
3016 struct snd_card *card = dev_get_drvdata(dev);
3017 struct azx *chip = card->private_data;
7d4f606c
WX		 3018 struct hda_bus *bus;
3019 struct hda_codec *codec;
3020 int status;
b8dfc462 3021
246efa4a
DA		 3022 if (chip->disabled)
3023 return 0;
3024
3025 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3026 return 0;
3027
99a2008d
WX		 3028 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3029 hda_display_power(true);
7d4f606c
WX		 3030
3031 /* Read STATESTS before controller reset */
3032 status = azx_readw(chip, STATESTS);
3033
b8dfc462
ML		 3034 azx_init_pci(chip);
3035 azx_init_chip(chip, 1);
7d4f606c
WX		 3036
3037 bus = chip->bus;
3038 if (status && bus) {
3039 list_for_each_entry(codec, &bus->codec_list, list)
3040 if (status & (1 << codec->addr))
3041 queue_delayed_work(codec->bus->workq,
3042 &codec->jackpoll_work, codec->jackpoll_interval);
3043 }
3044
3045 /* disable controller Wake Up event*/
3046 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3047 ~STATESTS_INT_MASK);
3048
b8dfc462
ML		 3049 return 0;
3050}
6eb827d2
TI		 3051
3052static int azx_runtime_idle(struct device *dev)
3053{
3054 struct snd_card *card = dev_get_drvdata(dev);
3055 struct azx *chip = card->private_data;
3056
246efa4a
DA		 3057 if (chip->disabled)
3058 return 0;
3059
6eb827d2
TI		 3060 if (!power_save_controller ||
3061 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3062 return -EBUSY;
3063
3064 return 0;
3065}
3066
b8dfc462
ML		 3067#endif /* CONFIG_PM_RUNTIME */
3068
3069#ifdef CONFIG_PM
3070static const struct dev_pm_ops azx_pm = {
3071 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 3072 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 3073};
3074
68cb2b55
TI		 3075#define AZX_PM_OPS &azx_pm
3076#else
68cb2b55 3077#define AZX_PM_OPS NULL
b8dfc462 3078#endif /* CONFIG_PM */
1da177e4
LT		 3079
3080
0cbf0098
TI		 3081/*
3082 * reboot notifier for hang-up problem at power-down
3083 */
3084static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3085{
3086 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3087 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3088 azx_stop_chip(chip);
3089 return NOTIFY_OK;
3090}
3091
3092static void azx_notifier_register(struct azx *chip)
3093{
3094 chip->reboot_notifier.notifier_call = azx_halt;
3095 register_reboot_notifier(&chip->reboot_notifier);
3096}
3097
3098static void azx_notifier_unregister(struct azx *chip)
3099{
3100 if (chip->reboot_notifier.notifier_call)
3101 unregister_reboot_notifier(&chip->reboot_notifier);
3102}
3103
48c8b0eb 3104static int azx_probe_continue(struct azx *chip);
a82d51ed 3105
8393ec4a 3106#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3107static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3108
a82d51ed
TI		 3109static void azx_vs_set_state(struct pci_dev *pci,
3110 enum vga_switcheroo_state state)
3111{
3112 struct snd_card *card = pci_get_drvdata(pci);
3113 struct azx *chip = card->private_data;
3114 bool disabled;
3115
f4c482a4 3116 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3117 if (chip->init_failed)
3118 return;
3119
3120 disabled = (state == VGA_SWITCHEROO_OFF);
3121 if (chip->disabled == disabled)
3122 return;
3123
3124 if (!chip->bus) {
3125 chip->disabled = disabled;
3126 if (!disabled) {
3127 snd_printk(KERN_INFO SFX
3128 "%s: Start delayed initialization\n",
3129 pci_name(chip->pci));
5c90680e 3130 if (azx_probe_continue(chip) < 0) {
a82d51ed
TI		 3131 snd_printk(KERN_ERR SFX
3132 "%s: initialization error\n",
3133 pci_name(chip->pci));
3134 chip->init_failed = true;
3135 }
3136 }
3137 } else {
3138 snd_printk(KERN_INFO SFX
445a51b3
DB		 3139 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3140 disabled ? "Disabling" : "Enabling");
a82d51ed 3141 if (disabled) {
246efa4a 3142 pm_runtime_put_sync_suspend(&pci->dev);
68cb2b55 3143 azx_suspend(&pci->dev);
246efa4a
DA		 3144 /* when we get suspended by vga switcheroo we end up in D3cold,
3145 * however we have no ACPI handle, so pci/acpi can't put us there,
3146 * put ourselves there */
3147 pci->current_state = PCI_D3cold;
a82d51ed 3148 chip->disabled = true;
128960a9 3149 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3150 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3151 pci_name(chip->pci));
a82d51ed
TI		 3152 } else {
3153 snd_hda_unlock_devices(chip->bus);
246efa4a 3154 pm_runtime_get_noresume(&pci->dev);
a82d51ed 3155 chip->disabled = false;
68cb2b55 3156 azx_resume(&pci->dev);
a82d51ed
TI		 3157 }
3158 }
3159}
3160
3161static bool azx_vs_can_switch(struct pci_dev *pci)
3162{
3163 struct snd_card *card = pci_get_drvdata(pci);
3164 struct azx *chip = card->private_data;
3165
f4c482a4 3166 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3167 if (chip->init_failed)
3168 return false;
3169 if (chip->disabled || !chip->bus)
3170 return true;
3171 if (snd_hda_lock_devices(chip->bus))
3172 return false;
3173 snd_hda_unlock_devices(chip->bus);
3174 return true;
3175}
3176
e23e7a14 3177static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3178{
3179 struct pci_dev *p = get_bound_vga(chip->pci);
3180 if (p) {
3181 snd_printk(KERN_INFO SFX
3182 "%s: Handle VGA-switcheroo audio client\n",
3183 pci_name(chip->pci));
3184 chip->use_vga_switcheroo = 1;
3185 pci_dev_put(p);
3186 }
3187}
3188
3189static const struct vga_switcheroo_client_ops azx_vs_ops = {
3190 .set_gpu_state = azx_vs_set_state,
3191 .can_switch = azx_vs_can_switch,
3192};
3193
e23e7a14 3194static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3195{
128960a9
TI		 3196 int err;
3197
a82d51ed
TI		 3198 if (!chip->use_vga_switcheroo)
3199 return 0;
3200 /* FIXME: currently only handling DIS controller
3201 * is there any machine with two switchable HDMI audio controllers?
3202 */
128960a9 3203 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3204 VGA_SWITCHEROO_DIS,
3205 chip->bus != NULL);
128960a9
TI		 3206 if (err < 0)
3207 return err;
3208 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 3209
3210 /* register as an optimus hdmi audio power domain */
3211 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
128960a9 3212 return 0;
a82d51ed
TI		 3213}
3214#else
3215#define init_vga_switcheroo(chip) /* NOP */
3216#define register_vga_switcheroo(chip) 0
8393ec4a 3217#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3218#endif /* SUPPORT_VGA_SWITCHER */
3219
1da177e4
LT		 3220/*
3221 * destructor
3222 */
a98f90fd 3223static int azx_free(struct azx *chip)
1da177e4 3224{
c67e2228 3225 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 3226 int i;
3227
c67e2228
WX		 3228 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3229 && chip->running)
3230 pm_runtime_get_noresume(&pci->dev);
3231
65fcd41d
TI		 3232 azx_del_card_list(chip);
3233
0cbf0098
TI		 3234 azx_notifier_unregister(chip);
3235
f4c482a4 3236 chip->init_failed = 1; /* to be sure */
44728e97 3237 complete_all(&chip->probe_wait);
f4c482a4 3238
a82d51ed
TI		 3239 if (use_vga_switcheroo(chip)) {
3240 if (chip->disabled && chip->bus)
3241 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3242 if (chip->vga_switcheroo_registered)
3243 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3244 }
3245
ce43fbae 3246 if (chip->initialized) {
9ad593f6 3247 azx_clear_irq_pending(chip);
07e4ca50 3248 for (i = 0; i < chip->num_streams; i++)
1da177e4 3249 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3250 azx_stop_chip(chip);
1da177e4
LT		 3251 }
3252
f000fd80 3253 if (chip->irq >= 0)
1da177e4 3254 free_irq(chip->irq, (void*)chip);
68e7fffc 3255 if (chip->msi)
30b35399 3256 pci_disable_msi(chip->pci);
f079c25a
TI		 3257 if (chip->remap_addr)
3258 iounmap(chip->remap_addr);
1da177e4 3259
4ce107b9
TI		 3260 if (chip->azx_dev) {
3261 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3262 if (chip->azx_dev[i].bdl.area) {
3263 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3264 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3265 }
4ce107b9 3266 }
27fe48d9
TI		 3267 if (chip->rb.area) {
3268 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3269 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3270 }
3271 if (chip->posbuf.area) {
3272 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3273 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3274 }
a82d51ed
TI		 3275 if (chip->region_requested)
3276 pci_release_regions(chip->pci);
1da177e4 3277 pci_disable_device(chip->pci);
07e4ca50 3278 kfree(chip->azx_dev);
4918cdab
TI		 3279#ifdef CONFIG_SND_HDA_PATCH_LOADER
3280 if (chip->fw)
3281 release_firmware(chip->fw);
3282#endif
99a2008d
WX		 3283 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3284 hda_display_power(false);
3285 hda_i915_exit();
3286 }
1da177e4
LT		 3287 kfree(chip);
3288
3289 return 0;
3290}
3291
a98f90fd 3292static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3293{
3294 return azx_free(device->device_data);
3295}
3296
8393ec4a 3297#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3298/*
3299 * Check of disabled HDMI controller by vga-switcheroo
3300 */
e23e7a14 3301static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3302{
3303 struct pci_dev *p;
3304
3305 /* check only discrete GPU */
3306 switch (pci->vendor) {
3307 case PCI_VENDOR_ID_ATI:
3308 case PCI_VENDOR_ID_AMD:
3309 case PCI_VENDOR_ID_NVIDIA:
3310 if (pci->devfn == 1) {
3311 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3312 pci->bus->number, 0);
3313 if (p) {
3314 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3315 return p;
3316 pci_dev_put(p);
3317 }
3318 }
3319 break;
3320 }
3321 return NULL;
3322}
3323
e23e7a14 3324static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3325{
3326 bool vga_inactive = false;
3327 struct pci_dev *p = get_bound_vga(pci);
3328
3329 if (p) {
12b78a7f 3330 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3331 vga_inactive = true;
3332 pci_dev_put(p);
3333 }
3334 return vga_inactive;
3335}
8393ec4a 3336#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3337
3372a153
TI		 3338/*
3339 * white/black-listing for position_fix
3340 */
e23e7a14 3341static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3342 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3343 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3344 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3345 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3346 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3347 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3348 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3349 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3350 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3351 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3352 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3353 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3354 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3355 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3356 {}
3357};
3358
e23e7a14 3359static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3360{
3361 const struct snd_pci_quirk *q;
3362
c673ba1c 3363 switch (fix) {
1dac6695 3364 case POS_FIX_AUTO:
c673ba1c
TI		 3365 case POS_FIX_LPIB:
3366 case POS_FIX_POSBUF:
4cb36310 3367 case POS_FIX_VIACOMBO:
a6f2fd55 3368 case POS_FIX_COMBO:
c673ba1c
TI		 3369 return fix;
3370 }
3371
c673ba1c
TI		 3372 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3373 if (q) {
3374 printk(KERN_INFO
3375 "hda_intel: position_fix set to %d "
3376 "for device %04x:%04x\n",
3377 q->value, q->subvendor, q->subdevice);
3378 return q->value;
3372a153 3379 }
bdd9ef24
DH		 3380
3381 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3382 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3383 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3384 return POS_FIX_VIACOMBO;
9477c58e
TI		 3385 }
3386 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3387 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3388 return POS_FIX_LPIB;
bdd9ef24 3389 }
c673ba1c 3390 return POS_FIX_AUTO;
3372a153
TI		 3391}
3392
669ba27a
TI		 3393/*
3394 * black-lists for probe_mask
3395 */
e23e7a14 3396static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3397 /* Thinkpad often breaks the controller communication when accessing
3398 * to the non-working (or non-existing) modem codec slot.
3399 */
3400 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3401 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3402 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3403 /* broken BIOS */
3404 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3405 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3406 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3407 /* forced codec slots */
93574844 3408 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3409 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3410 /* WinFast VP200 H (Teradici) user reported broken communication */
3411 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3412 {}
3413};
3414
f1eaaeec
TI		 3415#define AZX_FORCE_CODEC_MASK 0x100
3416
e23e7a14 3417static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3418{
3419 const struct snd_pci_quirk *q;
3420
f1eaaeec
TI		 3421 chip->codec_probe_mask = probe_mask[dev];
3422 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3423 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3424 if (q) {
3425 printk(KERN_INFO
3426 "hda_intel: probe_mask set to 0x%x "
3427 "for device %04x:%04x\n",
3428 q->value, q->subvendor, q->subdevice);
f1eaaeec 3429 chip->codec_probe_mask = q->value;
669ba27a
TI		 3430 }
3431 }
f1eaaeec
TI		 3432
3433 /* check forced option */
3434 if (chip->codec_probe_mask != -1 &&
3435 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3436 chip->codec_mask = chip->codec_probe_mask & 0xff;
3437 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3438 chip->codec_mask);
3439 }
669ba27a
TI		 3440}
3441
4d8e22e0 3442/*
71623855 3443 * white/black-list for enable_msi
4d8e22e0 3444 */
e23e7a14 3445static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 3446 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3447 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3448 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3449 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 3450 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3451 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3452 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 3453 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 3454 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3455 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3456 {}
3457};
3458
e23e7a14 3459static void check_msi(struct azx *chip)
4d8e22e0
TI		 3460{
3461 const struct snd_pci_quirk *q;
3462
71623855
TI		 3463 if (enable_msi >= 0) {
3464 chip->msi = !!enable_msi;
4d8e22e0 3465 return;
71623855
TI		 3466 }
3467 chip->msi = 1; /* enable MSI as default */
3468 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3469 if (q) {
3470 printk(KERN_INFO
3471 "hda_intel: msi for device %04x:%04x set to %d\n",
3472 q->subvendor, q->subdevice, q->value);
3473 chip->msi = q->value;
80c43ed7
TI		 3474 return;
3475 }
3476
3477 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3478 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3479 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3480 chip->msi = 0;
4d8e22e0
TI		 3481 }
3482}
3483
a1585d76 3484/* check the snoop mode availability */
e23e7a14 3485static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3486{
3487 bool snoop = chip->snoop;
3488
3489 switch (chip->driver_type) {
3490 case AZX_DRIVER_VIA:
3491 /* force to non-snoop mode for a new VIA controller
3492 * when BIOS is set
3493 */
3494 if (snoop) {
3495 u8 val;
3496 pci_read_config_byte(chip->pci, 0x42, &val);
3497 if (!(val & 0x80) && chip->pci->revision == 0x30)
3498 snoop = false;
3499 }
3500 break;
3501 case AZX_DRIVER_ATIHDMI_NS:
3502 /* new ATI HDMI requires non-snoop */
3503 snoop = false;
3504 break;
c1279f87
TI		 3505 case AZX_DRIVER_CTHDA:
3506 snoop = false;
3507 break;
a1585d76
TI		 3508 }
3509
3510 if (snoop != chip->snoop) {
445a51b3
DB		 3511 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3512 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3513 chip->snoop = snoop;
3514 }
3515}
669ba27a 3516
99a2008d
WX		 3517static void azx_probe_work(struct work_struct *work)
3518{
3519 azx_probe_continue(container_of(work, struct azx, probe_work));
3520}
99a2008d 3521
1da177e4
LT		 3522/*
3523 * constructor
3524 */
e23e7a14
BP		 3525static int azx_create(struct snd_card *card, struct pci_dev *pci,
3526 int dev, unsigned int driver_caps,
3527 struct azx **rchip)
1da177e4 3528{
a98f90fd 3529 static struct snd_device_ops ops = {
1da177e4
LT		 3530 .dev_free = azx_dev_free,
3531 };
a82d51ed
TI		 3532 struct azx *chip;
3533 int err;
1da177e4
LT		 3534
3535 *rchip = NULL;
bcd72003 3536
927fc866
PM		 3537 err = pci_enable_device(pci);
3538 if (err < 0)
1da177e4
LT		 3539 return err;
3540
e560d8d8 3541 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3542 if (!chip) {
445a51b3 3543 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3544 pci_disable_device(pci);
3545 return -ENOMEM;
3546 }
3547
3548 spin_lock_init(&chip->reg_lock);
62932df8 3549 mutex_init(&chip->open_mutex);
1da177e4
LT		 3550 chip->card = card;
3551 chip->pci = pci;
3552 chip->irq = -1;
9477c58e
TI		 3553 chip->driver_caps = driver_caps;
3554 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3555 check_msi(chip);
555e219f 3556 chip->dev_index = dev;
9ad593f6 3557 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3558 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3559 INIT_LIST_HEAD(&chip->list);
a82d51ed 3560 init_vga_switcheroo(chip);
f4c482a4 3561 init_completion(&chip->probe_wait);
1da177e4 3562
beaffc39
SG		 3563 chip->position_fix[0] = chip->position_fix[1] =
3564 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3565 /* combo mode uses LPIB for playback */
3566 if (chip->position_fix[0] == POS_FIX_COMBO) {
3567 chip->position_fix[0] = POS_FIX_LPIB;
3568 chip->position_fix[1] = POS_FIX_AUTO;
3569 }
3570
5aba4f8e 3571 check_probe_mask(chip, dev);
3372a153 3572
27346166 3573 chip->single_cmd = single_cmd;
27fe48d9 3574 chip->snoop = hda_snoop;
a1585d76 3575 azx_check_snoop_available(chip);
c74db86b 3576
5c0d7bc1
TI		 3577 if (bdl_pos_adj[dev] < 0) {
3578 switch (chip->driver_type) {
0c6341ac 3579 case AZX_DRIVER_ICH:
32679f95 3580 case AZX_DRIVER_PCH:
0c6341ac 3581 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3582 break;
3583 default:
0c6341ac 3584 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3585 break;
3586 }
3587 }
3588
a82d51ed
TI		 3589 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3590 if (err < 0) {
445a51b3
DB		 3591 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3592 pci_name(chip->pci));
a82d51ed
TI		 3593 azx_free(chip);
3594 return err;
3595 }
3596
99a2008d
WX		 3597 /* continue probing in work context as may trigger request module */
3598 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 3599
a82d51ed 3600 *rchip = chip;
99a2008d 3601
a82d51ed
TI		 3602 return 0;
3603}
3604
48c8b0eb 3605static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3606{
3607 int dev = chip->dev_index;
3608 struct pci_dev *pci = chip->pci;
3609 struct snd_card *card = chip->card;
3610 int i, err;
3611 unsigned short gcap;
3612
07e4ca50
TI		 3613#if BITS_PER_LONG != 64
3614 /* Fix up base address on ULI M5461 */
3615 if (chip->driver_type == AZX_DRIVER_ULI) {
3616 u16 tmp3;
3617 pci_read_config_word(pci, 0x40, &tmp3);
3618 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3619 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3620 }
3621#endif
3622
927fc866 3623 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3624 if (err < 0)
1da177e4 3625 return err;
a82d51ed 3626 chip->region_requested = 1;
1da177e4 3627
927fc866 3628 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3629 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3630 if (chip->remap_addr == NULL) {
445a51b3 3631 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3632 return -ENXIO;
1da177e4
LT		 3633 }
3634
68e7fffc
TI		 3635 if (chip->msi)
3636 if (pci_enable_msi(pci) < 0)
3637 chip->msi = 0;
7376d013 3638
a82d51ed
TI		 3639 if (azx_acquire_irq(chip, 0) < 0)
3640 return -EBUSY;
1da177e4
LT		 3641
3642 pci_set_master(pci);
3643 synchronize_irq(chip->irq);
3644
bcd72003 3645 gcap = azx_readw(chip, GCAP);
445a51b3 3646 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3647
dc4c2e6b 3648 /* disable SB600 64bit support for safety */
9477c58e 3649 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3650 struct pci_dev *p_smbus;
3651 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3652 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3653 NULL);
3654 if (p_smbus) {
3655 if (p_smbus->revision < 0x30)
3656 gcap &= ~ICH6_GCAP_64OK;
3657 pci_dev_put(p_smbus);
3658 }
3659 }
09240cf4 3660
9477c58e
TI		 3661 /* disable 64bit DMA address on some devices */
3662 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3663 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3664 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3665 }
396087ea 3666
2ae66c26 3667 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3668 if (align_buffer_size >= 0)
3669 chip->align_buffer_size = !!align_buffer_size;
3670 else {
3671 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3672 chip->align_buffer_size = 0;
3673 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3674 chip->align_buffer_size = 1;
3675 else
3676 chip->align_buffer_size = 1;
3677 }
2ae66c26 3678
cf7aaca8 3679 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3680 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3681 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3682 else {
e930438c
YH		 3683 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3684 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3685 }
cf7aaca8 3686
8b6ed8e7
TI		 3687 /* read number of streams from GCAP register instead of using
3688 * hardcoded value
3689 */
3690 chip->capture_streams = (gcap >> 8) & 0x0f;
3691 chip->playback_streams = (gcap >> 12) & 0x0f;
3692 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3693 /* gcap didn't give any info, switching to old method */
3694
3695 switch (chip->driver_type) {
3696 case AZX_DRIVER_ULI:
3697 chip->playback_streams = ULI_NUM_PLAYBACK;
3698 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3699 break;
3700 case AZX_DRIVER_ATIHDMI:
1815b34a 3701 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3702 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3703 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3704 break;
c4da29ca 3705 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3706 default:
3707 chip->playback_streams = ICH6_NUM_PLAYBACK;
3708 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3709 break;
3710 }
07e4ca50 3711 }
8b6ed8e7
TI		 3712 chip->capture_index_offset = 0;
3713 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3714 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3715 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3716 GFP_KERNEL);
927fc866 3717 if (!chip->azx_dev) {
445a51b3 3718 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3719 return -ENOMEM;
07e4ca50
TI		 3720 }
3721
4ce107b9 3722 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3723 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3724 /* allocate memory for the BDL for each stream */
3725 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3726 snd_dma_pci_data(chip->pci),
3727 BDL_SIZE, &chip->azx_dev[i].bdl);
3728 if (err < 0) {
445a51b3 3729 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3730 return -ENOMEM;
4ce107b9 3731 }
27fe48d9 3732 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3733 }
0be3b5d3 3734 /* allocate memory for the position buffer */
d01ce99f
TI		 3735 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3736 snd_dma_pci_data(chip->pci),
3737 chip->num_streams * 8, &chip->posbuf);
3738 if (err < 0) {
445a51b3 3739 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3740 return -ENOMEM;
1da177e4 3741 }
27fe48d9 3742 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3743 /* allocate CORB/RIRB */
81740861
TI		 3744 err = azx_alloc_cmd_io(chip);
3745 if (err < 0)
a82d51ed 3746 return err;
1da177e4
LT		 3747
3748 /* initialize streams */
3749 azx_init_stream(chip);
3750
3751 /* initialize chip */
cb53c626 3752 azx_init_pci(chip);
10e77dda 3753 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3754
3755 /* codec detection */
927fc866 3756 if (!chip->codec_mask) {
445a51b3 3757 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3758 return -ENODEV;
1da177e4
LT		 3759 }
3760
07e4ca50 3761 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3762 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3763 sizeof(card->shortname));
3764 snprintf(card->longname, sizeof(card->longname),
3765 "%s at 0x%lx irq %i",
3766 card->shortname, chip->addr, chip->irq);
07e4ca50 3767
1da177e4 3768 return 0;
1da177e4
LT		 3769}
3770
cb53c626
TI		 3771static void power_down_all_codecs(struct azx *chip)
3772{
83012a7c 3773#ifdef CONFIG_PM
cb53c626
TI		 3774 /* The codecs were powered up in snd_hda_codec_new().
3775 * Now all initialization done, so turn them down if possible
3776 */
3777 struct hda_codec *codec;
3778 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3779 snd_hda_power_down(codec);
3780 }
3781#endif
3782}
3783
97c6a3d1 3784#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3785/* callback from request_firmware_nowait() */
3786static void azx_firmware_cb(const struct firmware *fw, void *context)
3787{
3788 struct snd_card *card = context;
3789 struct azx *chip = card->private_data;
3790 struct pci_dev *pci = chip->pci;
3791
3792 if (!fw) {
445a51b3
DB		 3793 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3794 pci_name(chip->pci));
5cb543db
TI		 3795 goto error;
3796 }
3797
3798 chip->fw = fw;
3799 if (!chip->disabled) {
3800 /* continue probing */
3801 if (azx_probe_continue(chip))
3802 goto error;
3803 }
3804 return; /* OK */
3805
3806 error:
3807 snd_card_free(card);
3808 pci_set_drvdata(pci, NULL);
3809}
97c6a3d1 3810#endif
5cb543db 3811
e23e7a14
BP		 3812static int azx_probe(struct pci_dev *pci,
3813 const struct pci_device_id *pci_id)
1da177e4 3814{
5aba4f8e 3815 static int dev;
a98f90fd
TI		 3816 struct snd_card *card;
3817 struct azx *chip;
aad730d0 3818 bool schedule_probe;
927fc866 3819 int err;
1da177e4 3820
5aba4f8e
TI		 3821 if (dev >= SNDRV_CARDS)
3822 return -ENODEV;
3823 if (!enable[dev]) {
3824 dev++;
3825 return -ENOENT;
3826 }
3827
60c5772b
TI		 3828 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3829 0, &card);
e58de7ba 3830 if (err < 0) {
445a51b3 3831 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3832 return err;
1da177e4
LT		 3833 }
3834
5aba4f8e 3835 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3836 if (err < 0)
3837 goto out_free;
421a1252 3838 card->private_data = chip;
f4c482a4
TI		 3839
3840 pci_set_drvdata(pci, card);
3841
3842 err = register_vga_switcheroo(chip);
3843 if (err < 0) {
3844 snd_printk(KERN_ERR SFX
445a51b3 3845 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3846 goto out_free;
3847 }
3848
3849 if (check_hdmi_disabled(pci)) {
445a51b3 3850 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3851 pci_name(pci));
445a51b3 3852 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3853 chip->disabled = true;
3854 }
3855
aad730d0 3856 schedule_probe = !chip->disabled;
1da177e4 3857
4918cdab
TI		 3858#ifdef CONFIG_SND_HDA_PATCH_LOADER
3859 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3860 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3861 pci_name(pci), patch[dev]);
5cb543db
TI		 3862 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3863 &pci->dev, GFP_KERNEL, card,
3864 azx_firmware_cb);
4918cdab
TI		 3865 if (err < 0)
3866 goto out_free;
aad730d0 3867 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3868 }
3869#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3870
aad730d0
TI		 3871#ifndef CONFIG_SND_HDA_I915
3872 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d
WX		 3873 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3874#endif
99a2008d 3875
aad730d0
TI		 3876 if (schedule_probe)
3877 schedule_work(&chip->probe_work);
a82d51ed 3878
a82d51ed 3879 dev++;
88d071fc
TI		 3880 if (chip->disabled)
3881 complete_all(&chip->probe_wait);
a82d51ed
TI		 3882 return 0;
3883
3884out_free:
3885 snd_card_free(card);
3886 return err;
3887}
3888
48c8b0eb 3889static int azx_probe_continue(struct azx *chip)
a82d51ed 3890{
c67e2228 3891 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3892 int dev = chip->dev_index;
3893 int err;
3894
99a2008d
WX		 3895 /* Request power well for Haswell HDA controller and codec */
3896 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 3897#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 3898 err = hda_i915_init();
3899 if (err < 0) {
3900 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3901 goto out_free;
3902 }
c841ad2a 3903#endif
99a2008d
WX		 3904 hda_display_power(true);
3905 }
3906
5c90680e
TI		 3907 err = azx_first_init(chip);
3908 if (err < 0)
3909 goto out_free;
3910
2dca0bba
JK		 3911#ifdef CONFIG_SND_HDA_INPUT_BEEP
3912 chip->beep_mode = beep_mode[dev];
3913#endif
3914
1da177e4 3915 /* create codec instances */
a1e21c90 3916 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3917 if (err < 0)
3918 goto out_free;
4ea6fbc8 3919#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3920 if (chip->fw) {
3921 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3922 chip->fw->data);
4ea6fbc8
TI		 3923 if (err < 0)
3924 goto out_free;
e39ae856 3925#ifndef CONFIG_PM
4918cdab
TI		 3926 release_firmware(chip->fw); /* no longer needed */
3927 chip->fw = NULL;
e39ae856 3928#endif
4ea6fbc8
TI		 3929 }
3930#endif
10e77dda 3931 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3932 err = azx_codec_configure(chip);
3933 if (err < 0)
3934 goto out_free;
3935 }
1da177e4
LT		 3936
3937 /* create PCM streams */
176d5335 3938 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3939 if (err < 0)
3940 goto out_free;
1da177e4
LT		 3941
3942 /* create mixer controls */
d01ce99f 3943 err = azx_mixer_create(chip);
41dda0fd
WF		 3944 if (err < 0)
3945 goto out_free;
1da177e4 3946
a82d51ed 3947 err = snd_card_register(chip->card);
41dda0fd
WF		 3948 if (err < 0)
3949 goto out_free;
1da177e4 3950
cb53c626
TI		 3951 chip->running = 1;
3952 power_down_all_codecs(chip);
0cbf0098 3953 azx_notifier_register(chip);
65fcd41d 3954 azx_add_card_list(chip);
246efa4a 3955 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 3956 pm_runtime_put_noidle(&pci->dev);
1da177e4 3957
41dda0fd 3958out_free:
88d071fc
TI		 3959 if (err < 0)
3960 chip->init_failed = 1;
3961 complete_all(&chip->probe_wait);
41dda0fd 3962 return err;
1da177e4
LT		 3963}
3964
e23e7a14 3965static void azx_remove(struct pci_dev *pci)
1da177e4 3966{
9121947d 3967 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3968
9121947d
TI		 3969 if (card)
3970 snd_card_free(card);
1da177e4
LT		 3971}
3972
3973/* PCI IDs */
cebe41d4 3974static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3975 /* CPT */
9477c58e 3976 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3977 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3978 /* PBG */
9477c58e 3979 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3980 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3981 /* Panther Point */
9477c58e 3982 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 3983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3984 /* Lynx Point */
3985 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3987 /* Wellsburg */
3988 { PCI_DEVICE(0x8086, 0x8d20),
3989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3990 { PCI_DEVICE(0x8086, 0x8d21),
3991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3992 /* Lynx Point-LP */
3993 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3995 /* Lynx Point-LP */
3996 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3997 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 3998 /* Wildcat Point-LP */
3999 { PCI_DEVICE(0x8086, 0x9ca0),
4000 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 4001 /* Haswell */
4a7c516b 4002 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 4003 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 4004 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 4005 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 4006 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 4007 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 4008 /* Broadwell */
4009 { PCI_DEVICE(0x8086, 0x160c),
4010 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 4011 /* 5 Series/3400 */
4012 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 4013 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 4014 /* Poulsbo */
9477c58e 4015 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 4016 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4017 /* Oaktrail */
09904b95 4018 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 4019 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 4020 /* BayTrail */
4021 { PCI_DEVICE(0x8086, 0x0f04),
4022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 4023 /* ICH */
8b0bd226 4024 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 4025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4026 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 4027 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 4028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4029 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 4030 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 4031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4032 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 4033 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 4034 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4035 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 4036 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 4037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4038 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4039 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 4040 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4041 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4042 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 4043 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4044 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 4045 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 4046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4047 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 4048 /* Generic Intel */
4049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4050 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4051 .class_mask = 0xffffff,
2ae66c26 4052 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 4053 /* ATI SB 450/600/700/800/900 */
4054 { PCI_DEVICE(0x1002, 0x437b),
4055 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4056 { PCI_DEVICE(0x1002, 0x4383),
4057 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4058 /* AMD Hudson */
4059 { PCI_DEVICE(0x1022, 0x780d),
4060 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 4061 /* ATI HDMI */
9477c58e
TI		 4062 { PCI_DEVICE(0x1002, 0x793b),
4063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4064 { PCI_DEVICE(0x1002, 0x7919),
4065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4066 { PCI_DEVICE(0x1002, 0x960f),
4067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4068 { PCI_DEVICE(0x1002, 0x970f),
4069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4070 { PCI_DEVICE(0x1002, 0xaa00),
4071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4072 { PCI_DEVICE(0x1002, 0xaa08),
4073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4074 { PCI_DEVICE(0x1002, 0xaa10),
4075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4076 { PCI_DEVICE(0x1002, 0xaa18),
4077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4078 { PCI_DEVICE(0x1002, 0xaa20),
4079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4080 { PCI_DEVICE(0x1002, 0xaa28),
4081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4082 { PCI_DEVICE(0x1002, 0xaa30),
4083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4084 { PCI_DEVICE(0x1002, 0xaa38),
4085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4086 { PCI_DEVICE(0x1002, 0xaa40),
4087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4088 { PCI_DEVICE(0x1002, 0xaa48),
4089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 4090 { PCI_DEVICE(0x1002, 0xaa50),
4091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4092 { PCI_DEVICE(0x1002, 0xaa58),
4093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4094 { PCI_DEVICE(0x1002, 0xaa60),
4095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4096 { PCI_DEVICE(0x1002, 0xaa68),
4097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4098 { PCI_DEVICE(0x1002, 0xaa80),
4099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4100 { PCI_DEVICE(0x1002, 0xaa88),
4101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4102 { PCI_DEVICE(0x1002, 0xaa90),
4103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4104 { PCI_DEVICE(0x1002, 0xaa98),
4105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 4106 { PCI_DEVICE(0x1002, 0x9902),
4107 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4108 { PCI_DEVICE(0x1002, 0xaaa0),
4109 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4110 { PCI_DEVICE(0x1002, 0xaaa8),
4111 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4112 { PCI_DEVICE(0x1002, 0xaab0),
4113 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 4114 /* VIA VT8251/VT8237A */
9477c58e
TI		 4115 { PCI_DEVICE(0x1106, 0x3288),
4116 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 4117 /* VIA GFX VT7122/VX900 */
4118 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4119 /* VIA GFX VT6122/VX11 */
4120 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 4121 /* SIS966 */
4122 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4123 /* ULI M5461 */
4124 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4125 /* NVIDIA MCP */
0c2fd1bf
TI		 4126 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4127 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4128 .class_mask = 0xffffff,
9477c58e 4129 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 4130 /* Teradici */
9477c58e
TI		 4131 { PCI_DEVICE(0x6549, 0x1200),
4132 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 4133 { PCI_DEVICE(0x6549, 0x2200),
4134 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 4135 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 4136 /* CTHDA chips */
4137 { PCI_DEVICE(0x1102, 0x0010),
4138 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4139 { PCI_DEVICE(0x1102, 0x0012),
4140 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 4141#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 4142 /* the following entry conflicts with snd-ctxfi driver,
4143 * as ctxfi driver mutates from HD-audio to native mode with
4144 * a special command sequence.
4145 */
4e01f54b
TI		 4146 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4147 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4148 .class_mask = 0xffffff,
9477c58e 4149 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4150 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4151#else
4152 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4153 { PCI_DEVICE(0x1102, 0x0009),
4154 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4155 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4156#endif
e35d4b11
OS		 4157 /* Vortex86MX */
4158 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4159 /* VMware HDAudio */
4160 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4161 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4162 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4163 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4164 .class_mask = 0xffffff,
9477c58e 4165 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4166 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4167 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4168 .class_mask = 0xffffff,
9477c58e 4169 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4170 { 0, }
4171};
4172MODULE_DEVICE_TABLE(pci, azx_ids);
4173
4174/* pci_driver definition */
e9f66d9b 4175static struct pci_driver azx_driver = {
3733e424 4176 .name = KBUILD_MODNAME,
1da177e4
LT		 4177 .id_table = azx_ids,
4178 .probe = azx_probe,
e23e7a14 4179 .remove = azx_remove,
68cb2b55
TI		 4180 .driver = {
4181 .pm = AZX_PM_OPS,
4182 },
1da177e4
LT		 4183};
4184
e9f66d9b 4185module_pci_driver(azx_driver);
Linux kernel - Deliverables
This page took 0.986101 seconds and 5 git commands to generate.