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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 93#define INTEL_HDA_CGCTL 0x48
94#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 95#define INTEL_SCH_HDA_DEVC 0x78
96#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98/* Define IN stream 0 FIFO size offset in VIA controller */
99#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100/* Define VIA HD Audio Device ID*/
101#define VIA_HDAC_DEVICE_ID 0x3288
102
33124929
TI		 103/* max number of SDs */
104/* ICH, ATI and VIA have 4 playback and 4 capture */
105#define ICH6_NUM_CAPTURE 4
106#define ICH6_NUM_PLAYBACK 4
107
108/* ULI has 6 playback and 5 capture */
109#define ULI_NUM_CAPTURE 5
110#define ULI_NUM_PLAYBACK 6
111
112/* ATI HDMI may have up to 8 playbacks and 0 capture */
113#define ATIHDMI_NUM_CAPTURE 0
114#define ATIHDMI_NUM_PLAYBACK 8
115
116/* TERA has 4 playback and 3 capture */
117#define TERA_NUM_CAPTURE 3
118#define TERA_NUM_PLAYBACK 4
119
1da177e4 120
5aba4f8e
TI		 121static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 123static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 124static char *model[SNDRV_CARDS];
1dac6695 125static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 126static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 127static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 128static int probe_only[SNDRV_CARDS];
26a6cb6c 129static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 130static bool single_cmd;
71623855 131static int enable_msi = -1;
4ea6fbc8
TI		 132#ifdef CONFIG_SND_HDA_PATCH_LOADER
133static char *patch[SNDRV_CARDS];
134#endif
2dca0bba 135#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 136static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138#endif
1da177e4 139
5aba4f8e 140module_param_array(index, int, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 142module_param_array(id, charp, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 144module_param_array(enable, bool, NULL, 0444);
145MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146module_param_array(model, charp, NULL, 0444);
1da177e4 147MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 148module_param_array(position_fix, int, NULL, 0444);
4cb36310 149MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 151module_param_array(bdl_pos_adj, int, NULL, 0644);
152MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 153module_param_array(probe_mask, int, NULL, 0444);
606ad75f 154MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 155module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 156MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 157module_param_array(jackpoll_ms, int, NULL, 0444);
158MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 159module_param(single_cmd, bool, 0444);
d01ce99f
TI		 160MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
ac9ef6cf 162module_param(enable_msi, bint, 0444);
134a11f0 163MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 164#ifdef CONFIG_SND_HDA_PATCH_LOADER
165module_param_array(patch, charp, NULL, 0444);
166MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167#endif
2dca0bba 168#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 169module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 170MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 171 "(0=off, 1=on) (default=1).");
2dca0bba 172#endif
606ad75f 173
83012a7c 174#ifdef CONFIG_PM
65fcd41d 175static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 176static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 177 .set = param_set_xint,
178 .get = param_get_int,
179};
180#define param_check_xint param_check_int
181
fee2fba3 182static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 183module_param(power_save, xint, 0644);
fee2fba3
TI		 184MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
1da177e4 186
dee1b66c
TI		 187/* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
8fc24426
TI		 191static bool power_save_controller = 1;
192module_param(power_save_controller, bool, 0644);
dee1b66c 193MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 194#else
bb573928 195#define power_save 0
83012a7c 196#endif /* CONFIG_PM */
dee1b66c 197
7bfe059e
TI		 198static int align_buffer_size = -1;
199module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 200MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
27fe48d9 203#ifdef CONFIG_X86
7c732015
TI		 204static int hda_snoop = -1;
205module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 206MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 207#else
208#define hda_snoop true
27fe48d9
TI		 209#endif
210
211
1da177e4
LT		 212MODULE_LICENSE("GPL");
213MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
2f1b3818 215 "{Intel, ICH7},"
f5d40b30 216 "{Intel, ESB2},"
d2981393 217 "{Intel, ICH8},"
f9cc8a8b 218 "{Intel, ICH9},"
c34f5a04 219 "{Intel, ICH10},"
b29c2360 220 "{Intel, PCH},"
d2f2fcd2 221 "{Intel, CPT},"
d2edeb7c 222 "{Intel, PPT},"
8bc039a1 223 "{Intel, LPT},"
144dad99 224 "{Intel, LPT_LP},"
4eeca499 225 "{Intel, WPT_LP},"
c8b00fd2 226 "{Intel, SPT},"
b4565913 227 "{Intel, SPT_LP},"
e926f2c8 228 "{Intel, HPT},"
cea310e8 229 "{Intel, PBG},"
4979bca9 230 "{Intel, SCH},"
fc20a562 231 "{ATI, SB450},"
89be83f8 232 "{ATI, SB600},"
778b6e1b 233 "{ATI, RS600},"
5b15c95f 234 "{ATI, RS690},"
e6db1119
WL		 235 "{ATI, RS780},"
236 "{ATI, R600},"
2797f724
HRK		 237 "{ATI, RV630},"
238 "{ATI, RV610},"
27da1834
WL		 239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
fc20a562 243 "{VIA, VT8251},"
47672310 244 "{VIA, VT8237A},"
07e4ca50
TI		 245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
1da177e4
LT		 247MODULE_DESCRIPTION("Intel HDA driver");
248
a82d51ed 249#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 250#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 251#define SUPPORT_VGA_SWITCHEROO
252#endif
253#endif
254
255
1da177e4 256/*
1da177e4 257 */
1da177e4 258
07e4ca50
TI		 259/* driver types */
260enum {
261 AZX_DRIVER_ICH,
32679f95 262 AZX_DRIVER_PCH,
4979bca9 263 AZX_DRIVER_SCH,
fab1285a 264 AZX_DRIVER_HDMI,
07e4ca50 265 AZX_DRIVER_ATI,
778b6e1b 266 AZX_DRIVER_ATIHDMI,
1815b34a 267 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
da3fca21 271 AZX_DRIVER_NVIDIA,
f269002e 272 AZX_DRIVER_TERA,
14d34f16 273 AZX_DRIVER_CTX,
5ae763b1 274 AZX_DRIVER_CTHDA,
c563f473 275 AZX_DRIVER_CMEDIA,
c4da29ca 276 AZX_DRIVER_GENERIC,
2f5983f2 277 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 278};
279
37e661ee
TI		 280#define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
b42b4afb
TI		 284/* quirks for old Intel chipsets */
285#define AZX_DCAPS_INTEL_ICH \
103884a3 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 287
2ea3c6a2 288/* quirks for Intel PCH */
6603249d 289#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 291 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 292
55913110 293/* PCH up to IVB; no runtime PM */
6603249d 294#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 295 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 296
55913110 297/* PCH for HSW/BDW; with runtime PM */
d7dab4db 298#define AZX_DCAPS_INTEL_PCH \
6603249d 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 300
6603249d 301/* HSW HDMI */
33499a15 302#define AZX_DCAPS_INTEL_HASWELL \
103884a3 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 306
54a0405d
LY		 307/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
308#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
311 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 312
40cc2392
ML		 313#define AZX_DCAPS_INTEL_BAYTRAIL \
314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
315
2d846c74
LY		 316#define AZX_DCAPS_INTEL_BRASWELL \
317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
318
d6795827 319#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
321 AZX_DCAPS_I915_POWERWELL)
d6795827 322
c87693da
LH		 323#define AZX_DCAPS_INTEL_BROXTON \
324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
325 AZX_DCAPS_I915_POWERWELL)
326
9477c58e
TI		 327/* quirks for ATI SB / AMD Hudson */
328#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 331
332/* quirks for ATI/AMD HDMI */
333#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
9477c58e 336
37e661ee
TI		 337/* quirks for ATI HDMI with snoop off */
338#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
9477c58e
TI		 341/* quirks for Nvidia */
342#define AZX_DCAPS_PRESET_NVIDIA \
7d9a1808 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
345 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 346
5ae763b1 347#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 349 AZX_DCAPS_NO_64BIT |\
37e661ee 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 351
a82d51ed 352/*
2b760d88 353 * vga_switcheroo support
a82d51ed
TI		 354 */
355#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 356#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
357#else
358#define use_vga_switcheroo(chip) 0
359#endif
360
03b135ce
LY		 361#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
362 ((pci)->device == 0x0c0c) || \
363 ((pci)->device == 0x0d0c) || \
364 ((pci)->device == 0x160c))
365
7e31a015
TI		 366#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
367#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
368#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
369#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
7c23b7c1 370
48c8b0eb 371static char *driver_short_names[] = {
07e4ca50 372 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 373 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 374 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 375 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 376 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 377 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 378 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 379 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
380 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 381 [AZX_DRIVER_ULI] = "HDA ULI M5461",
382 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 383 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 384 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 385 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 386 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 387 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 388};
389
27fe48d9 390#ifdef CONFIG_X86
9ddf1aeb 391static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 392{
9ddf1aeb
TI		 393 int pages;
394
27fe48d9
TI		 395 if (azx_snoop(chip))
396 return;
9ddf1aeb
TI		 397 if (!dmab || !dmab->area || !dmab->bytes)
398 return;
399
400#ifdef CONFIG_SND_DMA_SGBUF
401 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
402 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 403 if (chip->driver_type == AZX_DRIVER_CMEDIA)
404 return; /* deal with only CORB/RIRB buffers */
27fe48d9 405 if (on)
9ddf1aeb 406 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 407 else
9ddf1aeb
TI		 408 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
409 return;
27fe48d9 410 }
9ddf1aeb
TI		 411#endif
412
413 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
414 if (on)
415 set_memory_wc((unsigned long)dmab->area, pages);
416 else
417 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 418}
419
420static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 bool on)
422{
9ddf1aeb 423 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 424}
425static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 426 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 427{
428 if (azx_dev->wc_marked != on) {
9ddf1aeb 429 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 430 azx_dev->wc_marked = on;
431 }
432}
433#else
434/* NOP for other archs */
435static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
436 bool on)
437{
438}
439static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 440 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 441{
442}
443#endif
444
68e7fffc 445static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 446
cb53c626
TI		 447/*
448 * initialize the PCI registers
449 */
450/* update bits in a PCI register byte */
451static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
452 unsigned char mask, unsigned char val)
453{
454 unsigned char data;
455
456 pci_read_config_byte(pci, reg, &data);
457 data &= ~mask;
458 data |= (val & mask);
459 pci_write_config_byte(pci, reg, data);
460}
461
462static void azx_init_pci(struct azx *chip)
463{
37e661ee
TI		 464 int snoop_type = azx_get_snoop_type(chip);
465
cb53c626
TI		 466 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
467 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
468 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 469 * codecs.
470 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 471 */
46f2cc80 472 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 473 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 474 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 475 }
cb53c626 476
9477c58e
TI		 477 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
478 * we need to enable snoop.
479 */
37e661ee 480 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 481 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
482 azx_snoop(chip));
cb53c626 483 update_pci_byte(chip->pci,
27fe48d9
TI		 484 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
485 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 486 }
487
488 /* For NVIDIA HDA, enable snoop */
37e661ee 489 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 490 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
491 azx_snoop(chip));
cb53c626
TI		 492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_TRANSREG_ADDR,
494 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_ISTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 update_pci_byte(chip->pci,
499 NVIDIA_HDA_OSTRM_COH,
500 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 501 }
502
503 /* Enable SCH/PCH snoop if needed */
37e661ee 504 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 505 unsigned short snoop;
90a5ad52 506 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 507 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
508 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
509 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
510 if (!azx_snoop(chip))
511 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
512 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 513 pci_read_config_word(chip->pci,
514 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 515 }
4e76a883
TI		 516 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
517 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
518 "Disabled" : "Enabled");
da3fca21 519 }
1da177e4
LT		 520}
521
7c23b7c1
LH		 522/*
523 * In BXT-P A0, HD-Audio DMA requests is later than expected,
524 * and makes an audio stream sensitive to system latencies when
525 * 24/32 bits are playing.
526 * Adjusting threshold of DMA fifo to force the DMA request
527 * sooner to improve latency tolerance at the expense of power.
528 */
529static void bxt_reduce_dma_latency(struct azx *chip)
530{
531 u32 val;
532
533 val = azx_readl(chip, SKL_EM4L);
534 val &= (0x3 << 20);
535 azx_writel(chip, SKL_EM4L, val);
536}
537
0a673521
LH		 538static void hda_intel_init_chip(struct azx *chip, bool full_reset)
539{
98d8fc6c 540 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 541 struct pci_dev *pci = chip->pci;
6639484d 542 u32 val;
0a673521
LH		 543
544 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 545 snd_hdac_set_codec_wakeup(bus, true);
7e31a015 546 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 547 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
548 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
549 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
550 }
0a673521 551 azx_init_chip(chip, full_reset);
7e31a015 552 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
554 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
556 }
0a673521 557 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 558 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 559
560 /* reduce dma latency to avoid noise */
7e31a015 561 if (IS_BXT(pci))
7c23b7c1 562 bxt_reduce_dma_latency(chip);
0a673521
LH		 563}
564
b6050ef6
TI		 565/* calculate runtime delay from LPIB */
566static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
567 unsigned int pos)
568{
7833c3f8 569 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 570 int stream = substream->stream;
571 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
572 int delay;
573
574 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
575 delay = pos - lpib_pos;
576 else
577 delay = lpib_pos - pos;
578 if (delay < 0) {
7833c3f8 579 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 580 delay = 0;
581 else
7833c3f8 582 delay += azx_dev->core.bufsize;
b6050ef6
TI		 583 }
584
7833c3f8 585 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 586 dev_info(chip->card->dev,
587 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 588 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 589 delay = 0;
590 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
591 chip->get_delay[stream] = NULL;
592 }
593
594 return bytes_to_frames(substream->runtime, delay);
595}
596
9ad593f6
TI		 597static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
598
7ca954a8
DR		 599/* called from IRQ */
600static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
601{
9a34af4a 602 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 603 int ok;
604
605 ok = azx_position_ok(chip, azx_dev);
606 if (ok == 1) {
607 azx_dev->irq_pending = 0;
608 return ok;
2f35c630 609 } else if (ok == 0) {
7ca954a8
DR		 610 /* bogus IRQ, process it later */
611 azx_dev->irq_pending = 1;
2f35c630 612 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 613 }
614 return 0;
615}
616
17eccb27
ML		 617/* Enable/disable i915 display power for the link */
618static int azx_intel_link_power(struct azx *chip, bool enable)
619{
98d8fc6c 620 struct hdac_bus *bus = azx_bus(chip);
17eccb27 621
98d8fc6c 622 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 623}
624
9ad593f6
TI		 625/*
626 * Check whether the current DMA position is acceptable for updating
627 * periods. Returns non-zero if it's OK.
628 *
629 * Many HD-audio controllers appear pretty inaccurate about
630 * the update-IRQ timing. The IRQ is issued before actually the
631 * data is processed. So, we need to process it afterwords in a
632 * workqueue.
633 */
634static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
635{
7833c3f8 636 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 637 int stream = substream->stream;
e5463720 638 u32 wallclk;
9ad593f6
TI		 639 unsigned int pos;
640
7833c3f8
TI		 641 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
642 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 643 return -1; /* bogus (too early) interrupt */
fa00e046 644
b6050ef6
TI		 645 if (chip->get_position[stream])
646 pos = chip->get_position[stream](chip, azx_dev);
647 else { /* use the position buffer as default */
648 pos = azx_get_pos_posbuf(chip, azx_dev);
649 if (!pos || pos == (u32)-1) {
650 dev_info(chip->card->dev,
651 "Invalid position buffer, using LPIB read method instead.\n");
652 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 653 if (chip->get_position[0] == azx_get_pos_lpib &&
654 chip->get_position[1] == azx_get_pos_lpib)
655 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 656 pos = azx_get_pos_lpib(chip, azx_dev);
657 chip->get_delay[stream] = NULL;
658 } else {
659 chip->get_position[stream] = azx_get_pos_posbuf;
660 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
661 chip->get_delay[stream] = azx_get_delay_from_lpib;
662 }
663 }
664
7833c3f8 665 if (pos >= azx_dev->core.bufsize)
b6050ef6 666 pos = 0;
9ad593f6 667
7833c3f8 668 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 669 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 670 return -1; /* this shouldn't happen! */
7833c3f8
TI		 671 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
672 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 673 /* NG - it's below the first next period boundary */
4f0189be 674 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 675 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 676 return 1; /* OK, it's fine */
677}
678
679/*
680 * The work for pending PCM period updates.
681 */
682static void azx_irq_pending_work(struct work_struct *work)
683{
9a34af4a
TI		 684 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
685 struct azx *chip = &hda->chip;
7833c3f8
TI		 686 struct hdac_bus *bus = azx_bus(chip);
687 struct hdac_stream *s;
688 int pending, ok;
9ad593f6 689
9a34af4a 690 if (!hda->irq_pending_warned) {
4e76a883
TI		 691 dev_info(chip->card->dev,
692 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
693 chip->card->number);
9a34af4a 694 hda->irq_pending_warned = 1;
a6a950a8
TI		 695 }
696
9ad593f6
TI		 697 for (;;) {
698 pending = 0;
a41d1224 699 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 700 list_for_each_entry(s, &bus->stream_list, list) {
701 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 702 if (!azx_dev->irq_pending ||
7833c3f8
TI		 703 !s->substream ||
704 !s->running)
9ad593f6 705 continue;
e5463720
JK		 706 ok = azx_position_ok(chip, azx_dev);
707 if (ok > 0) {
9ad593f6 708 azx_dev->irq_pending = 0;
a41d1224 709 spin_unlock(&bus->reg_lock);
7833c3f8 710 snd_pcm_period_elapsed(s->substream);
a41d1224 711 spin_lock(&bus->reg_lock);
e5463720
JK		 712 } else if (ok < 0) {
713 pending = 0; /* too early */
9ad593f6
TI		 714 } else
715 pending++;
716 }
a41d1224 717 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 718 if (!pending)
719 return;
08af495f 720 msleep(1);
9ad593f6
TI		 721 }
722}
723
724/* clear irq_pending flags and assure no on-going workq */
725static void azx_clear_irq_pending(struct azx *chip)
726{
7833c3f8
TI		 727 struct hdac_bus *bus = azx_bus(chip);
728 struct hdac_stream *s;
9ad593f6 729
a41d1224 730 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
733 azx_dev->irq_pending = 0;
734 }
a41d1224 735 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 736}
737
68e7fffc
TI		 738static int azx_acquire_irq(struct azx *chip, int do_disconnect)
739{
a41d1224
TI		 740 struct hdac_bus *bus = azx_bus(chip);
741
437a5a46
TI		 742 if (request_irq(chip->pci->irq, azx_interrupt,
743 chip->msi ? 0 : IRQF_SHARED,
de65360b 744 chip->card->irq_descr, chip)) {
4e76a883
TI		 745 dev_err(chip->card->dev,
746 "unable to grab IRQ %d, disabling device\n",
747 chip->pci->irq);
68e7fffc
TI		 748 if (do_disconnect)
749 snd_card_disconnect(chip->card);
750 return -1;
751 }
a41d1224 752 bus->irq = chip->pci->irq;
69e13418 753 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 754 return 0;
755}
756
b6050ef6
TI		 757/* get the current DMA position with correction on VIA chips */
758static unsigned int azx_via_get_position(struct azx *chip,
759 struct azx_dev *azx_dev)
760{
761 unsigned int link_pos, mini_pos, bound_pos;
762 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
763 unsigned int fifo_size;
764
1604eeee 765 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 766 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 767 /* Playback, no problem using link position */
768 return link_pos;
769 }
770
771 /* Capture */
772 /* For new chipset,
773 * use mod to get the DMA position just like old chipset
774 */
7833c3f8
TI		 775 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
776 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 777
778 /* azx_dev->fifo_size can't get FIFO size of in stream.
779 * Get from base address + offset.
780 */
a41d1224
TI		 781 fifo_size = readw(azx_bus(chip)->remap_addr +
782 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 783
784 if (azx_dev->insufficient) {
785 /* Link position never gather than FIFO size */
786 if (link_pos <= fifo_size)
787 return 0;
788
789 azx_dev->insufficient = 0;
790 }
791
792 if (link_pos <= fifo_size)
7833c3f8 793 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 794 else
795 mini_pos = link_pos - fifo_size;
796
797 /* Find nearest previous boudary */
7833c3f8
TI		 798 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
799 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 800 if (mod_link_pos >= fifo_size)
801 bound_pos = link_pos - mod_link_pos;
802 else if (mod_dma_pos >= mod_mini_pos)
803 bound_pos = mini_pos - mod_mini_pos;
804 else {
7833c3f8
TI		 805 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
806 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 807 bound_pos = 0;
808 }
809
810 /* Calculate real DMA position we want */
811 return bound_pos + mod_dma_pos;
812}
813
83012a7c 814#ifdef CONFIG_PM
65fcd41d
TI		 815static DEFINE_MUTEX(card_list_lock);
816static LIST_HEAD(card_list);
817
818static void azx_add_card_list(struct azx *chip)
819{
9a34af4a 820 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 821 mutex_lock(&card_list_lock);
9a34af4a 822 list_add(&hda->list, &card_list);
65fcd41d
TI		 823 mutex_unlock(&card_list_lock);
824}
825
826static void azx_del_card_list(struct azx *chip)
827{
9a34af4a 828 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 829 mutex_lock(&card_list_lock);
9a34af4a 830 list_del_init(&hda->list);
65fcd41d
TI		 831 mutex_unlock(&card_list_lock);
832}
833
834/* trigger power-save check at writing parameter */
835static int param_set_xint(const char *val, const struct kernel_param *kp)
836{
9a34af4a 837 struct hda_intel *hda;
65fcd41d 838 struct azx *chip;
65fcd41d
TI		 839 int prev = power_save;
840 int ret = param_set_int(val, kp);
841
842 if (ret || prev == power_save)
843 return ret;
844
845 mutex_lock(&card_list_lock);
9a34af4a
TI		 846 list_for_each_entry(hda, &card_list, list) {
847 chip = &hda->chip;
a41d1224 848 if (!hda->probe_continued || chip->disabled)
65fcd41d 849 continue;
a41d1224 850 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 851 }
852 mutex_unlock(&card_list_lock);
853 return 0;
854}
855#else
856#define azx_add_card_list(chip) /* NOP */
857#define azx_del_card_list(chip) /* NOP */
83012a7c 858#endif /* CONFIG_PM */
5c0b9bec 859
7ccbde57 860#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 861/*
862 * power management
863 */
68cb2b55 864static int azx_suspend(struct device *dev)
1da177e4 865{
68cb2b55 866 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 867 struct azx *chip;
868 struct hda_intel *hda;
a41d1224 869 struct hdac_bus *bus;
1da177e4 870
2d9772ef
TI		 871 if (!card)
872 return 0;
873
874 chip = card->private_data;
875 hda = container_of(chip, struct hda_intel, chip);
342e8449 876 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 877 return 0;
878
a41d1224 879 bus = azx_bus(chip);
421a1252 880 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 881 azx_clear_irq_pending(chip);
cb53c626 882 azx_stop_chip(chip);
7295b264 883 azx_enter_link_reset(chip);
a41d1224
TI		 884 if (bus->irq >= 0) {
885 free_irq(bus->irq, chip);
886 bus->irq = -1;
30b35399 887 }
a07187c9 888
68e7fffc 889 if (chip->msi)
43001c95 890 pci_disable_msi(chip->pci);
795614dd
ML		 891 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
892 && hda->need_i915_power)
98d8fc6c 893 snd_hdac_display_power(bus, false);
785d8c4b
LY		 894
895 trace_azx_suspend(chip);
1da177e4
LT		 896 return 0;
897}
898
68cb2b55 899static int azx_resume(struct device *dev)
1da177e4 900{
68cb2b55
TI		 901 struct pci_dev *pci = to_pci_dev(dev);
902 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 903 struct azx *chip;
904 struct hda_intel *hda;
905
906 if (!card)
907 return 0;
1da177e4 908
2d9772ef
TI		 909 chip = card->private_data;
910 hda = container_of(chip, struct hda_intel, chip);
342e8449 911 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 912 return 0;
913
795614dd
ML		 914 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
915 && hda->need_i915_power) {
98d8fc6c 916 snd_hdac_display_power(azx_bus(chip), true);
bb03ed21 917 snd_hdac_i915_set_bclk(azx_bus(chip));
a07187c9 918 }
68e7fffc
TI		 919 if (chip->msi)
920 if (pci_enable_msi(pci) < 0)
921 chip->msi = 0;
922 if (azx_acquire_irq(chip, 1) < 0)
30b35399 923 return -EIO;
cb53c626 924 azx_init_pci(chip);
d804ad92 925
0a673521 926 hda_intel_init_chip(chip, true);
d804ad92 927
421a1252 928 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 929
930 trace_azx_resume(chip);
1da177e4
LT		 931 return 0;
932}
b8dfc462
ML		 933#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
934
3e6db33a
XZ		 935#ifdef CONFIG_PM_SLEEP
936/* put codec down to D3 at hibernation for Intel SKL+;
937 * otherwise BIOS may still access the codec and screw up the driver
938 */
3e6db33a
XZ		 939static int azx_freeze_noirq(struct device *dev)
940{
941 struct pci_dev *pci = to_pci_dev(dev);
942
943 if (IS_SKL_PLUS(pci))
944 pci_set_power_state(pci, PCI_D3hot);
945
946 return 0;
947}
948
949static int azx_thaw_noirq(struct device *dev)
950{
951 struct pci_dev *pci = to_pci_dev(dev);
952
953 if (IS_SKL_PLUS(pci))
954 pci_set_power_state(pci, PCI_D0);
955
956 return 0;
957}
958#endif /* CONFIG_PM_SLEEP */
959
641d334b 960#ifdef CONFIG_PM
b8dfc462
ML		 961static int azx_runtime_suspend(struct device *dev)
962{
963 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 964 struct azx *chip;
965 struct hda_intel *hda;
b8dfc462 966
2d9772ef
TI		 967 if (!card)
968 return 0;
969
970 chip = card->private_data;
971 hda = container_of(chip, struct hda_intel, chip);
1618e84a 972 if (chip->disabled || hda->init_failed)
246efa4a
DA		 973 return 0;
974
364aa716 975 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 976 return 0;
977
7d4f606c
WX		 978 /* enable controller wake up event */
979 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
980 STATESTS_INT_MASK);
981
b8dfc462 982 azx_stop_chip(chip);
873ce8ad 983 azx_enter_link_reset(chip);
b8dfc462 984 azx_clear_irq_pending(chip);
795614dd
ML		 985 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
986 && hda->need_i915_power)
98d8fc6c 987 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 988
785d8c4b 989 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 990 return 0;
991}
992
993static int azx_runtime_resume(struct device *dev)
994{
995 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 996 struct azx *chip;
997 struct hda_intel *hda;
98d8fc6c 998 struct hdac_bus *bus;
7d4f606c
WX		 999 struct hda_codec *codec;
1000 int status;
b8dfc462 1001
2d9772ef
TI		 1002 if (!card)
1003 return 0;
1004
1005 chip = card->private_data;
1006 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1007 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1008 return 0;
1009
364aa716 1010 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1011 return 0;
1012
033ea349
DH		 1013 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1014 bus = azx_bus(chip);
1015 if (hda->need_i915_power) {
1016 snd_hdac_display_power(bus, true);
bb03ed21 1017 snd_hdac_i915_set_bclk(bus);
033ea349
DH		 1018 } else {
1019 /* toggle codec wakeup bit for STATESTS read */
1020 snd_hdac_set_codec_wakeup(bus, true);
1021 snd_hdac_set_codec_wakeup(bus, false);
1022 }
a07187c9 1023 }
7d4f606c
WX		 1024
1025 /* Read STATESTS before controller reset */
1026 status = azx_readw(chip, STATESTS);
1027
b8dfc462 1028 azx_init_pci(chip);
0a673521 1029 hda_intel_init_chip(chip, true);
7d4f606c 1030
a41d1224
TI		 1031 if (status) {
1032 list_for_each_codec(codec, &chip->bus)
7d4f606c 1033 if (status & (1 << codec->addr))
2f35c630
TI		 1034 schedule_delayed_work(&codec->jackpoll_work,
1035 codec->jackpoll_interval);
7d4f606c
WX		 1036 }
1037
1038 /* disable controller Wake Up event*/
1039 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1040 ~STATESTS_INT_MASK);
1041
785d8c4b 1042 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1043 return 0;
1044}
6eb827d2
TI		 1045
1046static int azx_runtime_idle(struct device *dev)
1047{
1048 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1049 struct azx *chip;
1050 struct hda_intel *hda;
1051
1052 if (!card)
1053 return 0;
6eb827d2 1054
2d9772ef
TI		 1055 chip = card->private_data;
1056 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1057 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1058 return 0;
1059
55ed9cd1 1060 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1061 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1062 return -EBUSY;
1063
1064 return 0;
1065}
1066
b8dfc462
ML		 1067static const struct dev_pm_ops azx_pm = {
1068 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1069#ifdef CONFIG_PM_SLEEP
1070 .freeze_noirq = azx_freeze_noirq,
1071 .thaw_noirq = azx_thaw_noirq,
1072#endif
6eb827d2 1073 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1074};
1075
68cb2b55
TI		 1076#define AZX_PM_OPS &azx_pm
1077#else
68cb2b55 1078#define AZX_PM_OPS NULL
b8dfc462 1079#endif /* CONFIG_PM */
1da177e4
LT		 1080
1081
48c8b0eb 1082static int azx_probe_continue(struct azx *chip);
a82d51ed 1083
8393ec4a 1084#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1085static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1086
a82d51ed
TI		 1087static void azx_vs_set_state(struct pci_dev *pci,
1088 enum vga_switcheroo_state state)
1089{
1090 struct snd_card *card = pci_get_drvdata(pci);
1091 struct azx *chip = card->private_data;
9a34af4a 1092 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1093 bool disabled;
1094
9a34af4a
TI		 1095 wait_for_completion(&hda->probe_wait);
1096 if (hda->init_failed)
a82d51ed
TI		 1097 return;
1098
1099 disabled = (state == VGA_SWITCHEROO_OFF);
1100 if (chip->disabled == disabled)
1101 return;
1102
a41d1224 1103 if (!hda->probe_continued) {
a82d51ed
TI		 1104 chip->disabled = disabled;
1105 if (!disabled) {
4e76a883
TI		 1106 dev_info(chip->card->dev,
1107 "Start delayed initialization\n");
5c90680e 1108 if (azx_probe_continue(chip) < 0) {
4e76a883 1109 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1110 hda->init_failed = true;
a82d51ed
TI		 1111 }
1112 }
1113 } else {
2b760d88 1114 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1115 disabled ? "Disabling" : "Enabling");
a82d51ed 1116 if (disabled) {
8928756d
DR		 1117 pm_runtime_put_sync_suspend(card->dev);
1118 azx_suspend(card->dev);
2b760d88 1119 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1120 * however we have no ACPI handle, so pci/acpi can't put us there,
1121 * put ourselves there */
1122 pci->current_state = PCI_D3cold;
a82d51ed 1123 chip->disabled = true;
a41d1224 1124 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1125 dev_warn(chip->card->dev,
1126 "Cannot lock devices!\n");
a82d51ed 1127 } else {
a41d1224 1128 snd_hda_unlock_devices(&chip->bus);
8928756d 1129 pm_runtime_get_noresume(card->dev);
a82d51ed 1130 chip->disabled = false;
8928756d 1131 azx_resume(card->dev);
a82d51ed
TI		 1132 }
1133 }
1134}
1135
1136static bool azx_vs_can_switch(struct pci_dev *pci)
1137{
1138 struct snd_card *card = pci_get_drvdata(pci);
1139 struct azx *chip = card->private_data;
9a34af4a 1140 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1141
9a34af4a
TI		 1142 wait_for_completion(&hda->probe_wait);
1143 if (hda->init_failed)
a82d51ed 1144 return false;
a41d1224 1145 if (chip->disabled || !hda->probe_continued)
a82d51ed 1146 return true;
a41d1224 1147 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1148 return false;
a41d1224 1149 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1150 return true;
1151}
1152
e23e7a14 1153static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1154{
9a34af4a 1155 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1156 struct pci_dev *p = get_bound_vga(chip->pci);
1157 if (p) {
4e76a883 1158 dev_info(chip->card->dev,
2b760d88 1159 "Handle vga_switcheroo audio client\n");
9a34af4a 1160 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1161 pci_dev_put(p);
1162 }
1163}
1164
1165static const struct vga_switcheroo_client_ops azx_vs_ops = {
1166 .set_gpu_state = azx_vs_set_state,
1167 .can_switch = azx_vs_can_switch,
1168};
1169
e23e7a14 1170static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1171{
9a34af4a 1172 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1173 int err;
1174
9a34af4a 1175 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1176 return 0;
1177 /* FIXME: currently only handling DIS controller
1178 * is there any machine with two switchable HDMI audio controllers?
1179 */
128960a9 1180 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1181 VGA_SWITCHEROO_DIS);
128960a9
TI		 1182 if (err < 0)
1183 return err;
9a34af4a 1184 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1185
1186 /* register as an optimus hdmi audio power domain */
8928756d 1187 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1188 &hda->hdmi_pm_domain);
128960a9 1189 return 0;
a82d51ed
TI		 1190}
1191#else
1192#define init_vga_switcheroo(chip) /* NOP */
1193#define register_vga_switcheroo(chip) 0
8393ec4a 1194#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1195#endif /* SUPPORT_VGA_SWITCHER */
1196
1da177e4
LT		 1197/*
1198 * destructor
1199 */
a98f90fd 1200static int azx_free(struct azx *chip)
1da177e4 1201{
c67e2228 1202 struct pci_dev *pci = chip->pci;
a07187c9 1203 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1204 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1205
364aa716 1206 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1207 pm_runtime_get_noresume(&pci->dev);
1208
65fcd41d
TI		 1209 azx_del_card_list(chip);
1210
9a34af4a
TI		 1211 hda->init_failed = 1; /* to be sure */
1212 complete_all(&hda->probe_wait);
f4c482a4 1213
9a34af4a 1214 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1215 if (chip->disabled && hda->probe_continued)
1216 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1217 if (hda->vga_switcheroo_registered)
128960a9 1218 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1219 }
1220
a41d1224 1221 if (bus->chip_init) {
9ad593f6 1222 azx_clear_irq_pending(chip);
7833c3f8 1223 azx_stop_all_streams(chip);
cb53c626 1224 azx_stop_chip(chip);
1da177e4
LT		 1225 }
1226
a41d1224
TI		 1227 if (bus->irq >= 0)
1228 free_irq(bus->irq, (void*)chip);
68e7fffc 1229 if (chip->msi)
30b35399 1230 pci_disable_msi(chip->pci);
a41d1224 1231 iounmap(bus->remap_addr);
1da177e4 1232
67908994 1233 azx_free_stream_pages(chip);
a41d1224
TI		 1234 azx_free_streams(chip);
1235 snd_hdac_bus_exit(bus);
1236
a82d51ed
TI		 1237 if (chip->region_requested)
1238 pci_release_regions(chip->pci);
a41d1224 1239
1da177e4 1240 pci_disable_device(chip->pci);
4918cdab 1241#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1242 release_firmware(chip->fw);
4918cdab 1243#endif
98d8fc6c 1244
99a2008d 1245 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1246 if (hda->need_i915_power)
98d8fc6c
ML		 1247 snd_hdac_display_power(bus, false);
1248 snd_hdac_i915_exit(bus);
99a2008d 1249 }
a07187c9 1250 kfree(hda);
1da177e4
LT		 1251
1252 return 0;
1253}
1254
a41d1224
TI		 1255static int azx_dev_disconnect(struct snd_device *device)
1256{
1257 struct azx *chip = device->device_data;
1258
1259 chip->bus.shutdown = 1;
1260 return 0;
1261}
1262
a98f90fd 1263static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1264{
1265 return azx_free(device->device_data);
1266}
1267
8393ec4a 1268#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1269/*
2b760d88 1270 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1271 */
e23e7a14 1272static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1273{
1274 struct pci_dev *p;
1275
1276 /* check only discrete GPU */
1277 switch (pci->vendor) {
1278 case PCI_VENDOR_ID_ATI:
1279 case PCI_VENDOR_ID_AMD:
1280 case PCI_VENDOR_ID_NVIDIA:
1281 if (pci->devfn == 1) {
1282 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1283 pci->bus->number, 0);
1284 if (p) {
1285 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1286 return p;
1287 pci_dev_put(p);
1288 }
1289 }
1290 break;
1291 }
1292 return NULL;
1293}
1294
e23e7a14 1295static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1296{
1297 bool vga_inactive = false;
1298 struct pci_dev *p = get_bound_vga(pci);
1299
1300 if (p) {
12b78a7f 1301 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1302 vga_inactive = true;
1303 pci_dev_put(p);
1304 }
1305 return vga_inactive;
1306}
8393ec4a 1307#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1308
3372a153
TI		 1309/*
1310 * white/black-listing for position_fix
1311 */
e23e7a14 1312static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1313 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1314 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1315 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1316 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1317 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1318 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1319 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1320 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1321 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1322 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1323 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1324 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1325 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1326 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1327 {}
1328};
1329
e23e7a14 1330static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1331{
1332 const struct snd_pci_quirk *q;
1333
c673ba1c 1334 switch (fix) {
1dac6695 1335 case POS_FIX_AUTO:
c673ba1c
TI		 1336 case POS_FIX_LPIB:
1337 case POS_FIX_POSBUF:
4cb36310 1338 case POS_FIX_VIACOMBO:
a6f2fd55 1339 case POS_FIX_COMBO:
c673ba1c
TI		 1340 return fix;
1341 }
1342
c673ba1c
TI		 1343 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1344 if (q) {
4e76a883
TI		 1345 dev_info(chip->card->dev,
1346 "position_fix set to %d for device %04x:%04x\n",
1347 q->value, q->subvendor, q->subdevice);
c673ba1c 1348 return q->value;
3372a153 1349 }
bdd9ef24
DH		 1350
1351 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1352 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1353 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1354 return POS_FIX_VIACOMBO;
9477c58e
TI		 1355 }
1356 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1357 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1358 return POS_FIX_LPIB;
bdd9ef24 1359 }
c673ba1c 1360 return POS_FIX_AUTO;
3372a153
TI		 1361}
1362
b6050ef6
TI		 1363static void assign_position_fix(struct azx *chip, int fix)
1364{
1365 static azx_get_pos_callback_t callbacks[] = {
1366 [POS_FIX_AUTO] = NULL,
1367 [POS_FIX_LPIB] = azx_get_pos_lpib,
1368 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1369 [POS_FIX_VIACOMBO] = azx_via_get_position,
1370 [POS_FIX_COMBO] = azx_get_pos_lpib,
1371 };
1372
1373 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1374
1375 /* combo mode uses LPIB only for playback */
1376 if (fix == POS_FIX_COMBO)
1377 chip->get_position[1] = NULL;
1378
1379 if (fix == POS_FIX_POSBUF &&
1380 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1381 chip->get_delay[0] = chip->get_delay[1] =
1382 azx_get_delay_from_lpib;
1383 }
1384
1385}
1386
669ba27a
TI		 1387/*
1388 * black-lists for probe_mask
1389 */
e23e7a14 1390static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1391 /* Thinkpad often breaks the controller communication when accessing
1392 * to the non-working (or non-existing) modem codec slot.
1393 */
1394 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1395 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1396 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1397 /* broken BIOS */
1398 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1399 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1400 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1401 /* forced codec slots */
93574844 1402 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1403 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1404 /* WinFast VP200 H (Teradici) user reported broken communication */
1405 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1406 {}
1407};
1408
f1eaaeec
TI		 1409#define AZX_FORCE_CODEC_MASK 0x100
1410
e23e7a14 1411static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1412{
1413 const struct snd_pci_quirk *q;
1414
f1eaaeec
TI		 1415 chip->codec_probe_mask = probe_mask[dev];
1416 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1417 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1418 if (q) {
4e76a883
TI		 1419 dev_info(chip->card->dev,
1420 "probe_mask set to 0x%x for device %04x:%04x\n",
1421 q->value, q->subvendor, q->subdevice);
f1eaaeec 1422 chip->codec_probe_mask = q->value;
669ba27a
TI		 1423 }
1424 }
f1eaaeec
TI		 1425
1426 /* check forced option */
1427 if (chip->codec_probe_mask != -1 &&
1428 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1429 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1430 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1431 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1432 }
669ba27a
TI		 1433}
1434
4d8e22e0 1435/*
71623855 1436 * white/black-list for enable_msi
4d8e22e0 1437 */
e23e7a14 1438static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1439 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1440 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1441 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1442 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1443 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1444 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1445 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1446 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1447 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1448 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1449 {}
1450};
1451
e23e7a14 1452static void check_msi(struct azx *chip)
4d8e22e0
TI		 1453{
1454 const struct snd_pci_quirk *q;
1455
71623855
TI		 1456 if (enable_msi >= 0) {
1457 chip->msi = !!enable_msi;
4d8e22e0 1458 return;
71623855
TI		 1459 }
1460 chip->msi = 1; /* enable MSI as default */
1461 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1462 if (q) {
4e76a883
TI		 1463 dev_info(chip->card->dev,
1464 "msi for device %04x:%04x set to %d\n",
1465 q->subvendor, q->subdevice, q->value);
4d8e22e0 1466 chip->msi = q->value;
80c43ed7
TI		 1467 return;
1468 }
1469
1470 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1471 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1472 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1473 chip->msi = 0;
4d8e22e0
TI		 1474 }
1475}
1476
a1585d76 1477/* check the snoop mode availability */
e23e7a14 1478static void azx_check_snoop_available(struct azx *chip)
a1585d76 1479{
7c732015 1480 int snoop = hda_snoop;
a1585d76 1481
7c732015
TI		 1482 if (snoop >= 0) {
1483 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1484 snoop ? "snoop" : "non-snoop");
1485 chip->snoop = snoop;
1486 return;
1487 }
1488
1489 snoop = true;
37e661ee
TI		 1490 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1491 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1492 /* force to non-snoop mode for a new VIA controller
1493 * when BIOS is set
1494 */
7c732015
TI		 1495 u8 val;
1496 pci_read_config_byte(chip->pci, 0x42, &val);
1497 if (!(val & 0x80) && chip->pci->revision == 0x30)
1498 snoop = false;
a1585d76
TI		 1499 }
1500
37e661ee
TI		 1501 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1502 snoop = false;
1503
7c732015
TI		 1504 chip->snoop = snoop;
1505 if (!snoop)
1506 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1507}
669ba27a 1508
99a2008d
WX		 1509static void azx_probe_work(struct work_struct *work)
1510{
9a34af4a
TI		 1511 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1512 azx_probe_continue(&hda->chip);
99a2008d 1513}
99a2008d 1514
4f0189be
TI		 1515static int default_bdl_pos_adj(struct azx *chip)
1516{
2cf721db
TI		 1517 /* some exceptions: Atoms seem problematic with value 1 */
1518 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1519 switch (chip->pci->device) {
1520 case 0x0f04: /* Baytrail */
1521 case 0x2284: /* Braswell */
1522 return 32;
1523 }
1524 }
1525
4f0189be
TI		 1526 switch (chip->driver_type) {
1527 case AZX_DRIVER_ICH:
1528 case AZX_DRIVER_PCH:
1529 return 1;
1530 default:
1531 return 32;
1532 }
1533}
1534
1da177e4
LT		 1535/*
1536 * constructor
1537 */
a43ff5ba
TI		 1538static const struct hdac_io_ops pci_hda_io_ops;
1539static const struct hda_controller_ops pci_hda_ops;
1540
e23e7a14
BP		 1541static int azx_create(struct snd_card *card, struct pci_dev *pci,
1542 int dev, unsigned int driver_caps,
1543 struct azx **rchip)
1da177e4 1544{
a98f90fd 1545 static struct snd_device_ops ops = {
a41d1224 1546 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1547 .dev_free = azx_dev_free,
1548 };
a07187c9 1549 struct hda_intel *hda;
a82d51ed
TI		 1550 struct azx *chip;
1551 int err;
1da177e4
LT		 1552
1553 *rchip = NULL;
bcd72003 1554
927fc866
PM		 1555 err = pci_enable_device(pci);
1556 if (err < 0)
1da177e4
LT		 1557 return err;
1558
a07187c9
ML		 1559 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1560 if (!hda) {
1da177e4
LT		 1561 pci_disable_device(pci);
1562 return -ENOMEM;
1563 }
1564
a07187c9 1565 chip = &hda->chip;
62932df8 1566 mutex_init(&chip->open_mutex);
1da177e4
LT		 1567 chip->card = card;
1568 chip->pci = pci;
a43ff5ba 1569 chip->ops = &pci_hda_ops;
9477c58e
TI		 1570 chip->driver_caps = driver_caps;
1571 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1572 check_msi(chip);
555e219f 1573 chip->dev_index = dev;
749ee287 1574 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1575 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1576 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1577 INIT_LIST_HEAD(&hda->list);
a82d51ed 1578 init_vga_switcheroo(chip);
9a34af4a 1579 init_completion(&hda->probe_wait);
1da177e4 1580
b6050ef6 1581 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1582
5aba4f8e 1583 check_probe_mask(chip, dev);
3372a153 1584
27346166 1585 chip->single_cmd = single_cmd;
a1585d76 1586 azx_check_snoop_available(chip);
c74db86b 1587
4f0189be
TI		 1588 if (bdl_pos_adj[dev] < 0)
1589 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1590 else
1591 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1592
a41d1224
TI		 1593 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1594 if (err < 0) {
1595 kfree(hda);
1596 pci_disable_device(pci);
1597 return err;
1598 }
1599
7d9a1808
TI		 1600 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1601 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1602 chip->bus.needs_damn_long_delay = 1;
1603 }
1604
a82d51ed
TI		 1605 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1606 if (err < 0) {
4e76a883 1607 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1608 azx_free(chip);
1609 return err;
1610 }
1611
99a2008d 1612 /* continue probing in work context as may trigger request module */
9a34af4a 1613 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1614
a82d51ed 1615 *rchip = chip;
99a2008d 1616
a82d51ed
TI		 1617 return 0;
1618}
1619
48c8b0eb 1620static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1621{
1622 int dev = chip->dev_index;
1623 struct pci_dev *pci = chip->pci;
1624 struct snd_card *card = chip->card;
a41d1224 1625 struct hdac_bus *bus = azx_bus(chip);
67908994 1626 int err;
a82d51ed 1627 unsigned short gcap;
413cbf46 1628 unsigned int dma_bits = 64;
a82d51ed 1629
07e4ca50
TI		 1630#if BITS_PER_LONG != 64
1631 /* Fix up base address on ULI M5461 */
1632 if (chip->driver_type == AZX_DRIVER_ULI) {
1633 u16 tmp3;
1634 pci_read_config_word(pci, 0x40, &tmp3);
1635 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1636 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1637 }
1638#endif
1639
927fc866 1640 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1641 if (err < 0)
1da177e4 1642 return err;
a82d51ed 1643 chip->region_requested = 1;
1da177e4 1644
a41d1224
TI		 1645 bus->addr = pci_resource_start(pci, 0);
1646 bus->remap_addr = pci_ioremap_bar(pci, 0);
1647 if (bus->remap_addr == NULL) {
4e76a883 1648 dev_err(card->dev, "ioremap error\n");
a82d51ed 1649 return -ENXIO;
1da177e4
LT		 1650 }
1651
db79afa1
BH		 1652 if (chip->msi) {
1653 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1654 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1655 pci->no_64bit_msi = true;
1656 }
68e7fffc
TI		 1657 if (pci_enable_msi(pci) < 0)
1658 chip->msi = 0;
db79afa1 1659 }
7376d013 1660
a82d51ed
TI		 1661 if (azx_acquire_irq(chip, 0) < 0)
1662 return -EBUSY;
1da177e4
LT		 1663
1664 pci_set_master(pci);
a41d1224 1665 synchronize_irq(bus->irq);
1da177e4 1666
bcd72003 1667 gcap = azx_readw(chip, GCAP);
4e76a883 1668 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1669
413cbf46
TI		 1670 /* AMD devices support 40 or 48bit DMA, take the safe one */
1671 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1672 dma_bits = 40;
1673
dc4c2e6b 1674 /* disable SB600 64bit support for safety */
9477c58e 1675 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1676 struct pci_dev *p_smbus;
413cbf46 1677 dma_bits = 40;
dc4c2e6b
AB		 1678 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1679 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1680 NULL);
1681 if (p_smbus) {
1682 if (p_smbus->revision < 0x30)
fb1d8ac2 1683 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1684 pci_dev_put(p_smbus);
1685 }
1686 }
09240cf4 1687
9477c58e
TI		 1688 /* disable 64bit DMA address on some devices */
1689 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1690 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1691 gcap &= ~AZX_GCAP_64OK;
9477c58e 1692 }
396087ea 1693
2ae66c26 1694 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1695 if (align_buffer_size >= 0)
1696 chip->align_buffer_size = !!align_buffer_size;
1697 else {
103884a3 1698 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1699 chip->align_buffer_size = 0;
7bfe059e
TI		 1700 else
1701 chip->align_buffer_size = 1;
1702 }
2ae66c26 1703
cf7aaca8 1704 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1705 if (!(gcap & AZX_GCAP_64OK))
1706 dma_bits = 32;
412b979c
QL		 1707 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1708 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1709 } else {
412b979c
QL		 1710 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1711 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1712 }
cf7aaca8 1713
8b6ed8e7
TI		 1714 /* read number of streams from GCAP register instead of using
1715 * hardcoded value
1716 */
1717 chip->capture_streams = (gcap >> 8) & 0x0f;
1718 chip->playback_streams = (gcap >> 12) & 0x0f;
1719 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1720 /* gcap didn't give any info, switching to old method */
1721
1722 switch (chip->driver_type) {
1723 case AZX_DRIVER_ULI:
1724 chip->playback_streams = ULI_NUM_PLAYBACK;
1725 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1726 break;
1727 case AZX_DRIVER_ATIHDMI:
1815b34a 1728 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1729 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1730 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1731 break;
c4da29ca 1732 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1733 default:
1734 chip->playback_streams = ICH6_NUM_PLAYBACK;
1735 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1736 break;
1737 }
07e4ca50 1738 }
8b6ed8e7
TI		 1739 chip->capture_index_offset = 0;
1740 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1741 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1742
a41d1224
TI		 1743 /* initialize streams */
1744 err = azx_init_streams(chip);
81740861 1745 if (err < 0)
a82d51ed 1746 return err;
1da177e4 1747
a41d1224
TI		 1748 err = azx_alloc_stream_pages(chip);
1749 if (err < 0)
1750 return err;
1da177e4
LT		 1751
1752 /* initialize chip */
cb53c626 1753 azx_init_pci(chip);
e4d9e513 1754
bb03ed21
TI		 1755 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1756 snd_hdac_i915_set_bclk(bus);
e4d9e513 1757
0a673521 1758 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1759
1760 /* codec detection */
a41d1224 1761 if (!azx_bus(chip)->codec_mask) {
4e76a883 1762 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1763 return -ENODEV;
1da177e4
LT		 1764 }
1765
07e4ca50 1766 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1767 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1768 sizeof(card->shortname));
1769 snprintf(card->longname, sizeof(card->longname),
1770 "%s at 0x%lx irq %i",
a41d1224 1771 card->shortname, bus->addr, bus->irq);
07e4ca50 1772
1da177e4 1773 return 0;
1da177e4
LT		 1774}
1775
97c6a3d1 1776#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1777/* callback from request_firmware_nowait() */
1778static void azx_firmware_cb(const struct firmware *fw, void *context)
1779{
1780 struct snd_card *card = context;
1781 struct azx *chip = card->private_data;
1782 struct pci_dev *pci = chip->pci;
1783
1784 if (!fw) {
4e76a883 1785 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1786 goto error;
1787 }
1788
1789 chip->fw = fw;
1790 if (!chip->disabled) {
1791 /* continue probing */
1792 if (azx_probe_continue(chip))
1793 goto error;
1794 }
1795 return; /* OK */
1796
1797 error:
1798 snd_card_free(card);
1799 pci_set_drvdata(pci, NULL);
1800}
97c6a3d1 1801#endif
5cb543db 1802
40830813
DR		 1803/*
1804 * HDA controller ops.
1805 */
1806
1807/* PCI register access. */
db291e36 1808static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1809{
1810 writel(value, addr);
1811}
1812
db291e36 1813static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1814{
1815 return readl(addr);
1816}
1817
db291e36 1818static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1819{
1820 writew(value, addr);
1821}
1822
db291e36 1823static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1824{
1825 return readw(addr);
1826}
1827
db291e36 1828static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1829{
1830 writeb(value, addr);
1831}
1832
db291e36 1833static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1834{
1835 return readb(addr);
1836}
1837
f46ea609
DR		 1838static int disable_msi_reset_irq(struct azx *chip)
1839{
a41d1224 1840 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1841 int err;
1842
a41d1224
TI		 1843 free_irq(bus->irq, chip);
1844 bus->irq = -1;
f46ea609
DR		 1845 pci_disable_msi(chip->pci);
1846 chip->msi = 0;
1847 err = azx_acquire_irq(chip, 1);
1848 if (err < 0)
1849 return err;
1850
1851 return 0;
1852}
1853
b419b35b 1854/* DMA page allocation helpers. */
a43ff5ba 1855static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1856 int type,
1857 size_t size,
1858 struct snd_dma_buffer *buf)
1859{
a41d1224 1860 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1861 int err;
1862
1863 err = snd_dma_alloc_pages(type,
a43ff5ba 1864 bus->dev,
b419b35b
DR		 1865 size, buf);
1866 if (err < 0)
1867 return err;
1868 mark_pages_wc(chip, buf, true);
1869 return 0;
1870}
1871
a43ff5ba 1872static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1873{
a41d1224 1874 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1875
b419b35b
DR		 1876 mark_pages_wc(chip, buf, false);
1877 snd_dma_free_pages(buf);
1878}
1879
1880static int substream_alloc_pages(struct azx *chip,
1881 struct snd_pcm_substream *substream,
1882 size_t size)
1883{
1884 struct azx_dev *azx_dev = get_azx_dev(substream);
1885 int ret;
1886
1887 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1888 ret = snd_pcm_lib_malloc_pages(substream, size);
1889 if (ret < 0)
1890 return ret;
1891 mark_runtime_wc(chip, azx_dev, substream, true);
1892 return 0;
1893}
1894
1895static int substream_free_pages(struct azx *chip,
1896 struct snd_pcm_substream *substream)
1897{
1898 struct azx_dev *azx_dev = get_azx_dev(substream);
1899 mark_runtime_wc(chip, azx_dev, substream, false);
1900 return snd_pcm_lib_free_pages(substream);
1901}
1902
8769b278
DR		 1903static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1904 struct vm_area_struct *area)
1905{
1906#ifdef CONFIG_X86
1907 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1908 struct azx *chip = apcm->chip;
3b70bdba 1909 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1910 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1911#endif
1912}
1913
a43ff5ba 1914static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1915 .reg_writel = pci_azx_writel,
1916 .reg_readl = pci_azx_readl,
1917 .reg_writew = pci_azx_writew,
1918 .reg_readw = pci_azx_readw,
1919 .reg_writeb = pci_azx_writeb,
1920 .reg_readb = pci_azx_readb,
b419b35b
DR		 1921 .dma_alloc_pages = dma_alloc_pages,
1922 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1923};
1924
1925static const struct hda_controller_ops pci_hda_ops = {
1926 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1927 .substream_alloc_pages = substream_alloc_pages,
1928 .substream_free_pages = substream_free_pages,
8769b278 1929 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1930 .position_check = azx_position_check,
17eccb27 1931 .link_power = azx_intel_link_power,
40830813
DR		 1932};
1933
e23e7a14
BP		 1934static int azx_probe(struct pci_dev *pci,
1935 const struct pci_device_id *pci_id)
1da177e4 1936{
5aba4f8e 1937 static int dev;
a98f90fd 1938 struct snd_card *card;
9a34af4a 1939 struct hda_intel *hda;
a98f90fd 1940 struct azx *chip;
aad730d0 1941 bool schedule_probe;
927fc866 1942 int err;
1da177e4 1943
5aba4f8e
TI		 1944 if (dev >= SNDRV_CARDS)
1945 return -ENODEV;
1946 if (!enable[dev]) {
1947 dev++;
1948 return -ENOENT;
1949 }
1950
60c5772b
TI		 1951 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1952 0, &card);
e58de7ba 1953 if (err < 0) {
4e76a883 1954 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1955 return err;
1da177e4
LT		 1956 }
1957
a43ff5ba 1958 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1959 if (err < 0)
1960 goto out_free;
421a1252 1961 card->private_data = chip;
9a34af4a 1962 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1963
1964 pci_set_drvdata(pci, card);
1965
1966 err = register_vga_switcheroo(chip);
1967 if (err < 0) {
2b760d88 1968 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 1969 goto out_free;
1970 }
1971
1972 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1973 dev_info(card->dev, "VGA controller is disabled\n");
1974 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1975 chip->disabled = true;
1976 }
1977
aad730d0 1978 schedule_probe = !chip->disabled;
1da177e4 1979
4918cdab
TI		 1980#ifdef CONFIG_SND_HDA_PATCH_LOADER
1981 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1982 dev_info(card->dev, "Applying patch firmware '%s'\n",
1983 patch[dev]);
5cb543db
TI		 1984 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1985 &pci->dev, GFP_KERNEL, card,
1986 azx_firmware_cb);
4918cdab
TI		 1987 if (err < 0)
1988 goto out_free;
aad730d0 1989 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1990 }
1991#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1992
aad730d0 1993#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 1994 if (CONTROLLER_IN_GPU(pci))
1995 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 1996#endif
99a2008d 1997
aad730d0 1998 if (schedule_probe)
9a34af4a 1999 schedule_work(&hda->probe_work);
a82d51ed 2000
a82d51ed 2001 dev++;
88d071fc 2002 if (chip->disabled)
9a34af4a 2003 complete_all(&hda->probe_wait);
a82d51ed
TI		 2004 return 0;
2005
2006out_free:
2007 snd_card_free(card);
2008 return err;
2009}
2010
e62a42ae
DR		 2011/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2012static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2013 [AZX_DRIVER_NVIDIA] = 8,
2014 [AZX_DRIVER_TERA] = 1,
2015};
2016
48c8b0eb 2017static int azx_probe_continue(struct azx *chip)
a82d51ed 2018{
9a34af4a 2019 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2020 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2021 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2022 int dev = chip->dev_index;
2023 int err;
2024
a41d1224 2025 hda->probe_continued = 1;
795614dd
ML		 2026
2027 /* Request display power well for the HDA controller or codec. For
2028 * Haswell/Broadwell, both the display HDA controller and codec need
2029 * this power. For other platforms, like Baytrail/Braswell, only the
2030 * display codec needs the power and it can be released after probe.
2031 */
99a2008d 2032 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2033 /* HSW/BDW controllers need this power */
2034 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2035 hda->need_i915_power = 1;
2036
98d8fc6c 2037 err = snd_hdac_i915_init(bus);
535115b5
TI		 2038 if (err < 0) {
2039 /* if the controller is bound only with HDMI/DP
2040 * (for HSW and BDW), we need to abort the probe;
2041 * for other chips, still continue probing as other
2042 * codecs can be on the same link.
2043 */
bed2e98e
TI		 2044 if (CONTROLLER_IN_GPU(pci)) {
2045 dev_err(chip->card->dev,
2046 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2047 goto out_free;
bed2e98e 2048 } else
535115b5
TI		 2049 goto skip_i915;
2050 }
795614dd 2051
98d8fc6c 2052 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2053 if (err < 0) {
2054 dev_err(chip->card->dev,
2055 "Cannot turn on display power on i915\n");
795614dd 2056 goto i915_power_fail;
74b0c2d7 2057 }
99a2008d
WX		 2058 }
2059
bf06848b 2060 skip_i915:
5c90680e
TI		 2061 err = azx_first_init(chip);
2062 if (err < 0)
2063 goto out_free;
2064
2dca0bba
JK		 2065#ifdef CONFIG_SND_HDA_INPUT_BEEP
2066 chip->beep_mode = beep_mode[dev];
2067#endif
2068
1da177e4 2069 /* create codec instances */
96d2bd6e 2070 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2071 if (err < 0)
2072 goto out_free;
96d2bd6e 2073
4ea6fbc8 2074#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2075 if (chip->fw) {
a41d1224 2076 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2077 chip->fw->data);
4ea6fbc8
TI		 2078 if (err < 0)
2079 goto out_free;
e39ae856 2080#ifndef CONFIG_PM
4918cdab
TI		 2081 release_firmware(chip->fw); /* no longer needed */
2082 chip->fw = NULL;
e39ae856 2083#endif
4ea6fbc8
TI		 2084 }
2085#endif
10e77dda 2086 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2087 err = azx_codec_configure(chip);
2088 if (err < 0)
2089 goto out_free;
2090 }
1da177e4 2091
a82d51ed 2092 err = snd_card_register(chip->card);
41dda0fd
WF		 2093 if (err < 0)
2094 goto out_free;
1da177e4 2095
cb53c626 2096 chip->running = 1;
65fcd41d 2097 azx_add_card_list(chip);
a41d1224 2098 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2099 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2100 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2101
41dda0fd 2102out_free:
795614dd
ML		 2103 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2104 && !hda->need_i915_power)
98d8fc6c 2105 snd_hdac_display_power(bus, false);
795614dd
ML		 2106
2107i915_power_fail:
88d071fc 2108 if (err < 0)
9a34af4a
TI		 2109 hda->init_failed = 1;
2110 complete_all(&hda->probe_wait);
41dda0fd 2111 return err;
1da177e4
LT		 2112}
2113
e23e7a14 2114static void azx_remove(struct pci_dev *pci)
1da177e4 2115{
9121947d 2116 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2117 struct azx *chip;
2118 struct hda_intel *hda;
2119
2120 if (card) {
0b8c8219 2121 /* cancel the pending probing work */
991f86d7
TI		 2122 chip = card->private_data;
2123 hda = container_of(chip, struct hda_intel, chip);
0b8c8219 2124 cancel_work_sync(&hda->probe_work);
b8dfc462 2125
9121947d 2126 snd_card_free(card);
991f86d7 2127 }
1da177e4
LT		 2128}
2129
b2a0bafa
TI		 2130static void azx_shutdown(struct pci_dev *pci)
2131{
2132 struct snd_card *card = pci_get_drvdata(pci);
2133 struct azx *chip;
2134
2135 if (!card)
2136 return;
2137 chip = card->private_data;
2138 if (chip && chip->running)
2139 azx_stop_chip(chip);
2140}
2141
1da177e4 2142/* PCI IDs */
6f51f6cf 2143static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2144 /* CPT */
9477c58e 2145 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2146 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2147 /* PBG */
9477c58e 2148 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2149 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2150 /* Panther Point */
9477c58e 2151 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2152 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2153 /* Lynx Point */
2154 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2155 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2156 /* 9 Series */
2157 { PCI_DEVICE(0x8086, 0x8ca0),
2158 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2159 /* Wellsburg */
2160 { PCI_DEVICE(0x8086, 0x8d20),
2161 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2162 { PCI_DEVICE(0x8086, 0x8d21),
2163 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2164 /* Lewisburg */
2165 { PCI_DEVICE(0x8086, 0xa1f0),
2166 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2167 { PCI_DEVICE(0x8086, 0xa270),
2168 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2169 /* Lynx Point-LP */
2170 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2171 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2172 /* Lynx Point-LP */
2173 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2174 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2175 /* Wildcat Point-LP */
2176 { PCI_DEVICE(0x8086, 0x9ca0),
2177 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2178 /* Sunrise Point */
2179 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2180 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2181 /* Sunrise Point-LP */
2182 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2183 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2184 /* Broxton-P(Apollolake) */
2185 { PCI_DEVICE(0x8086, 0x5a98),
2186 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2187 /* Broxton-T */
2188 { PCI_DEVICE(0x8086, 0x1a98),
2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2190 /* Haswell */
4a7c516b 2191 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2192 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2193 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2194 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2195 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2196 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2197 /* Broadwell */
2198 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2199 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2200 /* 5 Series/3400 */
2201 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2202 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2203 /* Poulsbo */
9477c58e 2204 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2205 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2206 /* Oaktrail */
09904b95 2207 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2208 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2209 /* BayTrail */
2210 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2212 /* Braswell */
2213 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2214 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2215 /* ICH6 */
8b0bd226 2216 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2217 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2218 /* ICH7 */
8b0bd226 2219 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2220 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2221 /* ESB2 */
8b0bd226 2222 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2223 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2224 /* ICH8 */
8b0bd226 2225 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2226 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2227 /* ICH9 */
8b0bd226 2228 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2229 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2230 /* ICH9 */
8b0bd226 2231 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2232 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2233 /* ICH10 */
8b0bd226 2234 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2235 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2236 /* ICH10 */
8b0bd226 2237 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2238 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2239 /* Generic Intel */
2240 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2241 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2242 .class_mask = 0xffffff,
103884a3 2243 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2244 /* ATI SB 450/600/700/800/900 */
2245 { PCI_DEVICE(0x1002, 0x437b),
2246 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2247 { PCI_DEVICE(0x1002, 0x4383),
2248 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2249 /* AMD Hudson */
2250 { PCI_DEVICE(0x1022, 0x780d),
2251 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2252 /* ATI HDMI */
650474fb
AD		 2253 { PCI_DEVICE(0x1002, 0x1308),
2254 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2255 { PCI_DEVICE(0x1002, 0x157a),
2256 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2257 { PCI_DEVICE(0x1002, 0x793b),
2258 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2259 { PCI_DEVICE(0x1002, 0x7919),
2260 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2261 { PCI_DEVICE(0x1002, 0x960f),
2262 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2263 { PCI_DEVICE(0x1002, 0x970f),
2264 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2265 { PCI_DEVICE(0x1002, 0x9840),
2266 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2267 { PCI_DEVICE(0x1002, 0xaa00),
2268 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2269 { PCI_DEVICE(0x1002, 0xaa08),
2270 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2271 { PCI_DEVICE(0x1002, 0xaa10),
2272 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2273 { PCI_DEVICE(0x1002, 0xaa18),
2274 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2275 { PCI_DEVICE(0x1002, 0xaa20),
2276 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2277 { PCI_DEVICE(0x1002, 0xaa28),
2278 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2279 { PCI_DEVICE(0x1002, 0xaa30),
2280 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2281 { PCI_DEVICE(0x1002, 0xaa38),
2282 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2283 { PCI_DEVICE(0x1002, 0xaa40),
2284 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2285 { PCI_DEVICE(0x1002, 0xaa48),
2286 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2287 { PCI_DEVICE(0x1002, 0xaa50),
2288 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2289 { PCI_DEVICE(0x1002, 0xaa58),
2290 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2291 { PCI_DEVICE(0x1002, 0xaa60),
2292 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2293 { PCI_DEVICE(0x1002, 0xaa68),
2294 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2295 { PCI_DEVICE(0x1002, 0xaa80),
2296 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2297 { PCI_DEVICE(0x1002, 0xaa88),
2298 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2299 { PCI_DEVICE(0x1002, 0xaa90),
2300 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2301 { PCI_DEVICE(0x1002, 0xaa98),
2302 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2303 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2304 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2305 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2306 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2307 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2308 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2309 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2310 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2311 { PCI_DEVICE(0x1002, 0xaac0),
2312 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2313 { PCI_DEVICE(0x1002, 0xaac8),
2314 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2315 { PCI_DEVICE(0x1002, 0xaad8),
2316 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2317 { PCI_DEVICE(0x1002, 0xaae8),
2318 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2319 { PCI_DEVICE(0x1002, 0xaae0),
2320 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2321 { PCI_DEVICE(0x1002, 0xaaf0),
2322 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2323 /* VIA VT8251/VT8237A */
26f05717 2324 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2325 /* VIA GFX VT7122/VX900 */
2326 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2327 /* VIA GFX VT6122/VX11 */
2328 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2329 /* SIS966 */
2330 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2331 /* ULI M5461 */
2332 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2333 /* NVIDIA MCP */
0c2fd1bf
TI		 2334 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2335 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2336 .class_mask = 0xffffff,
9477c58e 2337 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2338 /* Teradici */
9477c58e
TI		 2339 { PCI_DEVICE(0x6549, 0x1200),
2340 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2341 { PCI_DEVICE(0x6549, 0x2200),
2342 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2343 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2344 /* CTHDA chips */
2345 { PCI_DEVICE(0x1102, 0x0010),
2346 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2347 { PCI_DEVICE(0x1102, 0x0012),
2348 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2349#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2350 /* the following entry conflicts with snd-ctxfi driver,
2351 * as ctxfi driver mutates from HD-audio to native mode with
2352 * a special command sequence.
2353 */
4e01f54b
TI		 2354 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2355 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2356 .class_mask = 0xffffff,
9477c58e 2357 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2358 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2359#else
2360 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2361 { PCI_DEVICE(0x1102, 0x0009),
2362 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2363 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2364#endif
c563f473
TI		 2365 /* CM8888 */
2366 { PCI_DEVICE(0x13f6, 0x5011),
2367 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2368 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2369 /* Vortex86MX */
2370 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2371 /* VMware HDAudio */
2372 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2373 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2374 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2375 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2376 .class_mask = 0xffffff,
9477c58e 2377 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2378 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2379 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2380 .class_mask = 0xffffff,
9477c58e 2381 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2382 { 0, }
2383};
2384MODULE_DEVICE_TABLE(pci, azx_ids);
2385
2386/* pci_driver definition */
e9f66d9b 2387static struct pci_driver azx_driver = {
3733e424 2388 .name = KBUILD_MODNAME,
1da177e4
LT		 2389 .id_table = azx_ids,
2390 .probe = azx_probe,
e23e7a14 2391 .remove = azx_remove,
b2a0bafa 2392 .shutdown = azx_shutdown,
68cb2b55
TI		 2393 .driver = {
2394 .pm = AZX_PM_OPS,
2395 },
1da177e4
LT		 2396};
2397
e9f66d9b 2398module_pci_driver(azx_driver);
Linux kernel - Deliverables
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