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ALSA: hda - Remove obsoleted SFX definitions
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
99a2008d 64#include "hda_i915.h"
05e84878 65#include "hda_controller.h"
2538a4f5 66#include "hda_priv.h"
1da177e4 67
b6050ef6
TI		 68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
9a34af4a
TI		 77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
33124929
TI		 97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
1da177e4 114
5aba4f8e
TI		 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 118static char *model[SNDRV_CARDS];
1dac6695 119static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 120static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 121static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 122static int probe_only[SNDRV_CARDS];
26a6cb6c 123static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 124static bool single_cmd;
71623855 125static int enable_msi = -1;
4ea6fbc8
TI		 126#ifdef CONFIG_SND_HDA_PATCH_LOADER
127static char *patch[SNDRV_CARDS];
128#endif
2dca0bba 129#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 130static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132#endif
1da177e4 133
5aba4f8e 134module_param_array(index, int, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 136module_param_array(id, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 138module_param_array(enable, bool, NULL, 0444);
139MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140module_param_array(model, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 142module_param_array(position_fix, int, NULL, 0444);
4cb36310 143MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 145module_param_array(bdl_pos_adj, int, NULL, 0644);
146MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 147module_param_array(probe_mask, int, NULL, 0444);
606ad75f 148MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 149module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 150MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 151module_param_array(jackpoll_ms, int, NULL, 0444);
152MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 153module_param(single_cmd, bool, 0444);
d01ce99f
TI		 154MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
ac9ef6cf 156module_param(enable_msi, bint, 0444);
134a11f0 157MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 158#ifdef CONFIG_SND_HDA_PATCH_LOADER
159module_param_array(patch, charp, NULL, 0444);
160MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161#endif
2dca0bba 162#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 163module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 164MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 165 "(0=off, 1=on) (default=1).");
2dca0bba 166#endif
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d
TI		 169static int param_set_xint(const char *val, const struct kernel_param *kp);
170static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 177static int *power_save_addr = &power_save;
65fcd41d 178module_param(power_save, xint, 0644);
fee2fba3
TI		 179MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
1da177e4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 189#else
190static int *power_save_addr;
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9
TI		 198#ifdef CONFIG_X86
199static bool hda_snoop = true;
200module_param_named(snoop, hda_snoop, bool, 0444);
201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
e926f2c8 221 "{Intel, HPT},"
cea310e8 222 "{Intel, PBG},"
4979bca9 223 "{Intel, SCH},"
fc20a562 224 "{ATI, SB450},"
89be83f8 225 "{ATI, SB600},"
778b6e1b 226 "{ATI, RS600},"
5b15c95f 227 "{ATI, RS690},"
e6db1119
WL		 228 "{ATI, RS780},"
229 "{ATI, R600},"
2797f724
HRK		 230 "{ATI, RV630},"
231 "{ATI, RV610},"
27da1834
WL		 232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
fc20a562 236 "{VIA, VT8251},"
47672310 237 "{VIA, VT8237A},"
07e4ca50
TI		 238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
1da177e4
LT		 240MODULE_DESCRIPTION("Intel HDA driver");
241
a82d51ed 242#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 243#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 244#define SUPPORT_VGA_SWITCHEROO
245#endif
246#endif
247
248
1da177e4 249/*
1da177e4 250 */
1da177e4 251
07e4ca50
TI		 252/* driver types */
253enum {
254 AZX_DRIVER_ICH,
32679f95 255 AZX_DRIVER_PCH,
4979bca9 256 AZX_DRIVER_SCH,
fab1285a 257 AZX_DRIVER_HDMI,
07e4ca50 258 AZX_DRIVER_ATI,
778b6e1b 259 AZX_DRIVER_ATIHDMI,
1815b34a 260 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
da3fca21 264 AZX_DRIVER_NVIDIA,
f269002e 265 AZX_DRIVER_TERA,
14d34f16 266 AZX_DRIVER_CTX,
5ae763b1 267 AZX_DRIVER_CTHDA,
c4da29ca 268 AZX_DRIVER_GENERIC,
2f5983f2 269 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 270};
271
2ea3c6a2 272/* quirks for Intel PCH */
d7dab4db 273#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 274 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 275 AZX_DCAPS_COUNT_LPIB_DELAY)
276
277#define AZX_DCAPS_INTEL_PCH \
278 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 279
33499a15
TI		 280#define AZX_DCAPS_INTEL_HASWELL \
281 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
282 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
283 AZX_DCAPS_I915_POWERWELL)
284
54a0405d
LY		 285/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
286#define AZX_DCAPS_INTEL_BROADWELL \
287 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
288 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
289 AZX_DCAPS_I915_POWERWELL)
290
9477c58e
TI		 291/* quirks for ATI SB / AMD Hudson */
292#define AZX_DCAPS_PRESET_ATI_SB \
293 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
294 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
295
296/* quirks for ATI/AMD HDMI */
297#define AZX_DCAPS_PRESET_ATI_HDMI \
298 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
299
300/* quirks for Nvidia */
301#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 302 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 303 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
304 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 305
5ae763b1
TI		 306#define AZX_DCAPS_PRESET_CTHDA \
307 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
308
a82d51ed
TI		 309/*
310 * VGA-switcher support
311 */
312#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 313#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
314#else
315#define use_vga_switcheroo(chip) 0
316#endif
317
48c8b0eb 318static char *driver_short_names[] = {
07e4ca50 319 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 320 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 321 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 322 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 323 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 324 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 325 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 326 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
327 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 328 [AZX_DRIVER_ULI] = "HDA ULI M5461",
329 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 330 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 331 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 332 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 333 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 334};
335
a07187c9
ML		 336
337/* Intel HSW/BDW display HDA controller Extended Mode registers.
338 * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
339 * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
340 * The values will be lost when the display power well is disabled.
341 */
342#define ICH6_REG_EM4 0x100c
343#define ICH6_REG_EM5 0x1010
344
345struct hda_intel {
346 struct azx chip;
347
348 /* HSW/BDW display HDA controller to restore BCLK from CDCLK */
349 unsigned int bclk_m;
350 unsigned int bclk_n;
a07187c9 351
9a34af4a
TI		 352 /* for pending irqs */
353 struct work_struct irq_pending_work;
354
355 /* sync probing */
356 struct completion probe_wait;
357 struct work_struct probe_work;
358
359 /* card list (for power_save trigger) */
360 struct list_head list;
361
362 /* extra flags */
363 unsigned int irq_pending_warned:1;
364
365 /* VGA-switcheroo setup */
366 unsigned int use_vga_switcheroo:1;
367 unsigned int vga_switcheroo_registered:1;
368 unsigned int init_failed:1; /* delayed init failed */
369
370 /* secondary power domain for hdmi audio under vga device */
371 struct dev_pm_domain hdmi_pm_domain;
372};
a07187c9 373
27fe48d9 374#ifdef CONFIG_X86
9ddf1aeb 375static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 376{
9ddf1aeb
TI		 377 int pages;
378
27fe48d9
TI		 379 if (azx_snoop(chip))
380 return;
9ddf1aeb
TI		 381 if (!dmab || !dmab->area || !dmab->bytes)
382 return;
383
384#ifdef CONFIG_SND_DMA_SGBUF
385 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
386 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 387 if (on)
9ddf1aeb 388 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 389 else
9ddf1aeb
TI		 390 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
391 return;
27fe48d9 392 }
9ddf1aeb
TI		 393#endif
394
395 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
396 if (on)
397 set_memory_wc((unsigned long)dmab->area, pages);
398 else
399 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 400}
401
402static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403 bool on)
404{
9ddf1aeb 405 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 406}
407static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 408 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 409{
410 if (azx_dev->wc_marked != on) {
9ddf1aeb 411 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 412 azx_dev->wc_marked = on;
413 }
414}
415#else
416/* NOP for other archs */
417static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419{
420}
421static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 422 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 423{
424}
425#endif
426
68e7fffc 427static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 428
cb53c626
TI		 429/*
430 * initialize the PCI registers
431 */
432/* update bits in a PCI register byte */
433static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
434 unsigned char mask, unsigned char val)
435{
436 unsigned char data;
437
438 pci_read_config_byte(pci, reg, &data);
439 data &= ~mask;
440 data |= (val & mask);
441 pci_write_config_byte(pci, reg, data);
442}
443
444static void azx_init_pci(struct azx *chip)
445{
446 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
447 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
448 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 449 * codecs.
450 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 451 */
46f2cc80 452 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 453 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 454 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 455 }
cb53c626 456
9477c58e
TI		 457 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
458 * we need to enable snoop.
459 */
460 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 461 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
462 azx_snoop(chip));
cb53c626 463 update_pci_byte(chip->pci,
27fe48d9
TI		 464 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
465 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 466 }
467
468 /* For NVIDIA HDA, enable snoop */
469 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 470 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
471 azx_snoop(chip));
cb53c626
TI		 472 update_pci_byte(chip->pci,
473 NVIDIA_HDA_TRANSREG_ADDR,
474 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 475 update_pci_byte(chip->pci,
476 NVIDIA_HDA_ISTRM_COH,
477 0x01, NVIDIA_HDA_ENABLE_COHBIT);
478 update_pci_byte(chip->pci,
479 NVIDIA_HDA_OSTRM_COH,
480 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 481 }
482
483 /* Enable SCH/PCH snoop if needed */
484 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 485 unsigned short snoop;
90a5ad52 486 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 487 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
488 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
489 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
490 if (!azx_snoop(chip))
491 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
492 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 493 pci_read_config_word(chip->pci,
494 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 495 }
4e76a883
TI		 496 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
497 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
498 "Disabled" : "Enabled");
da3fca21 499 }
1da177e4
LT		 500}
501
b6050ef6
TI		 502/* calculate runtime delay from LPIB */
503static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
504 unsigned int pos)
505{
506 struct snd_pcm_substream *substream = azx_dev->substream;
507 int stream = substream->stream;
508 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
509 int delay;
510
511 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
512 delay = pos - lpib_pos;
513 else
514 delay = lpib_pos - pos;
515 if (delay < 0) {
516 if (delay >= azx_dev->delay_negative_threshold)
517 delay = 0;
518 else
519 delay += azx_dev->bufsize;
520 }
521
522 if (delay >= azx_dev->period_bytes) {
523 dev_info(chip->card->dev,
524 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
525 delay, azx_dev->period_bytes);
526 delay = 0;
527 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
528 chip->get_delay[stream] = NULL;
529 }
530
531 return bytes_to_frames(substream->runtime, delay);
532}
533
9ad593f6
TI		 534static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
535
7ca954a8
DR		 536/* called from IRQ */
537static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
538{
9a34af4a 539 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 540 int ok;
541
542 ok = azx_position_ok(chip, azx_dev);
543 if (ok == 1) {
544 azx_dev->irq_pending = 0;
545 return ok;
546 } else if (ok == 0 && chip->bus && chip->bus->workq) {
547 /* bogus IRQ, process it later */
548 azx_dev->irq_pending = 1;
9a34af4a 549 queue_work(chip->bus->workq, &hda->irq_pending_work);
7ca954a8
DR		 550 }
551 return 0;
552}
553
9ad593f6
TI		 554/*
555 * Check whether the current DMA position is acceptable for updating
556 * periods. Returns non-zero if it's OK.
557 *
558 * Many HD-audio controllers appear pretty inaccurate about
559 * the update-IRQ timing. The IRQ is issued before actually the
560 * data is processed. So, we need to process it afterwords in a
561 * workqueue.
562 */
563static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
564{
b6050ef6
TI		 565 struct snd_pcm_substream *substream = azx_dev->substream;
566 int stream = substream->stream;
e5463720 567 u32 wallclk;
9ad593f6
TI		 568 unsigned int pos;
569
f48f606d
JK		 570 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
571 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 572 return -1; /* bogus (too early) interrupt */
fa00e046 573
b6050ef6
TI		 574 if (chip->get_position[stream])
575 pos = chip->get_position[stream](chip, azx_dev);
576 else { /* use the position buffer as default */
577 pos = azx_get_pos_posbuf(chip, azx_dev);
578 if (!pos || pos == (u32)-1) {
579 dev_info(chip->card->dev,
580 "Invalid position buffer, using LPIB read method instead.\n");
581 chip->get_position[stream] = azx_get_pos_lpib;
582 pos = azx_get_pos_lpib(chip, azx_dev);
583 chip->get_delay[stream] = NULL;
584 } else {
585 chip->get_position[stream] = azx_get_pos_posbuf;
586 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
587 chip->get_delay[stream] = azx_get_delay_from_lpib;
588 }
589 }
590
591 if (pos >= azx_dev->bufsize)
592 pos = 0;
9ad593f6 593
d6d8bf54
TI		 594 if (WARN_ONCE(!azx_dev->period_bytes,
595 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 596 return -1; /* this shouldn't happen! */
edb39935 597 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 598 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
599 /* NG - it's below the first next period boundary */
9cdc0115 600 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 601 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 602 return 1; /* OK, it's fine */
603}
604
605/*
606 * The work for pending PCM period updates.
607 */
608static void azx_irq_pending_work(struct work_struct *work)
609{
9a34af4a
TI		 610 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
611 struct azx *chip = &hda->chip;
e5463720 612 int i, pending, ok;
9ad593f6 613
9a34af4a 614 if (!hda->irq_pending_warned) {
4e76a883
TI		 615 dev_info(chip->card->dev,
616 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
617 chip->card->number);
9a34af4a 618 hda->irq_pending_warned = 1;
a6a950a8
TI		 619 }
620
9ad593f6
TI		 621 for (;;) {
622 pending = 0;
623 spin_lock_irq(&chip->reg_lock);
624 for (i = 0; i < chip->num_streams; i++) {
625 struct azx_dev *azx_dev = &chip->azx_dev[i];
626 if (!azx_dev->irq_pending ||
627 !azx_dev->substream ||
628 !azx_dev->running)
629 continue;
e5463720
JK		 630 ok = azx_position_ok(chip, azx_dev);
631 if (ok > 0) {
9ad593f6
TI		 632 azx_dev->irq_pending = 0;
633 spin_unlock(&chip->reg_lock);
634 snd_pcm_period_elapsed(azx_dev->substream);
635 spin_lock(&chip->reg_lock);
e5463720
JK		 636 } else if (ok < 0) {
637 pending = 0; /* too early */
9ad593f6
TI		 638 } else
639 pending++;
640 }
641 spin_unlock_irq(&chip->reg_lock);
642 if (!pending)
643 return;
08af495f 644 msleep(1);
9ad593f6
TI		 645 }
646}
647
648/* clear irq_pending flags and assure no on-going workq */
649static void azx_clear_irq_pending(struct azx *chip)
650{
651 int i;
652
653 spin_lock_irq(&chip->reg_lock);
654 for (i = 0; i < chip->num_streams; i++)
655 chip->azx_dev[i].irq_pending = 0;
656 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 657}
658
68e7fffc
TI		 659static int azx_acquire_irq(struct azx *chip, int do_disconnect)
660{
437a5a46
TI		 661 if (request_irq(chip->pci->irq, azx_interrupt,
662 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 663 KBUILD_MODNAME, chip)) {
4e76a883
TI		 664 dev_err(chip->card->dev,
665 "unable to grab IRQ %d, disabling device\n",
666 chip->pci->irq);
68e7fffc
TI		 667 if (do_disconnect)
668 snd_card_disconnect(chip->card);
669 return -1;
670 }
671 chip->irq = chip->pci->irq;
69e13418 672 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 673 return 0;
674}
675
b6050ef6
TI		 676/* get the current DMA position with correction on VIA chips */
677static unsigned int azx_via_get_position(struct azx *chip,
678 struct azx_dev *azx_dev)
679{
680 unsigned int link_pos, mini_pos, bound_pos;
681 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
682 unsigned int fifo_size;
683
684 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
685 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
686 /* Playback, no problem using link position */
687 return link_pos;
688 }
689
690 /* Capture */
691 /* For new chipset,
692 * use mod to get the DMA position just like old chipset
693 */
694 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
695 mod_dma_pos %= azx_dev->period_bytes;
696
697 /* azx_dev->fifo_size can't get FIFO size of in stream.
698 * Get from base address + offset.
699 */
700 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
701
702 if (azx_dev->insufficient) {
703 /* Link position never gather than FIFO size */
704 if (link_pos <= fifo_size)
705 return 0;
706
707 azx_dev->insufficient = 0;
708 }
709
710 if (link_pos <= fifo_size)
711 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
712 else
713 mini_pos = link_pos - fifo_size;
714
715 /* Find nearest previous boudary */
716 mod_mini_pos = mini_pos % azx_dev->period_bytes;
717 mod_link_pos = link_pos % azx_dev->period_bytes;
718 if (mod_link_pos >= fifo_size)
719 bound_pos = link_pos - mod_link_pos;
720 else if (mod_dma_pos >= mod_mini_pos)
721 bound_pos = mini_pos - mod_mini_pos;
722 else {
723 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
724 if (bound_pos >= azx_dev->bufsize)
725 bound_pos = 0;
726 }
727
728 /* Calculate real DMA position we want */
729 return bound_pos + mod_dma_pos;
730}
731
83012a7c 732#ifdef CONFIG_PM
65fcd41d
TI		 733static DEFINE_MUTEX(card_list_lock);
734static LIST_HEAD(card_list);
735
736static void azx_add_card_list(struct azx *chip)
737{
9a34af4a 738 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 739 mutex_lock(&card_list_lock);
9a34af4a 740 list_add(&hda->list, &card_list);
65fcd41d
TI		 741 mutex_unlock(&card_list_lock);
742}
743
744static void azx_del_card_list(struct azx *chip)
745{
9a34af4a 746 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 747 mutex_lock(&card_list_lock);
9a34af4a 748 list_del_init(&hda->list);
65fcd41d
TI		 749 mutex_unlock(&card_list_lock);
750}
751
752/* trigger power-save check at writing parameter */
753static int param_set_xint(const char *val, const struct kernel_param *kp)
754{
9a34af4a 755 struct hda_intel *hda;
65fcd41d
TI		 756 struct azx *chip;
757 struct hda_codec *c;
758 int prev = power_save;
759 int ret = param_set_int(val, kp);
760
761 if (ret || prev == power_save)
762 return ret;
763
764 mutex_lock(&card_list_lock);
9a34af4a
TI		 765 list_for_each_entry(hda, &card_list, list) {
766 chip = &hda->chip;
65fcd41d
TI		 767 if (!chip->bus || chip->disabled)
768 continue;
769 list_for_each_entry(c, &chip->bus->codec_list, list)
770 snd_hda_power_sync(c);
771 }
772 mutex_unlock(&card_list_lock);
773 return 0;
774}
775#else
776#define azx_add_card_list(chip) /* NOP */
777#define azx_del_card_list(chip) /* NOP */
83012a7c 778#endif /* CONFIG_PM */
5c0b9bec 779
a07187c9
ML		 780static void haswell_save_bclk(struct azx *chip)
781{
782 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
783
784 hda->bclk_m = azx_readw(chip, EM4);
785 hda->bclk_n = azx_readw(chip, EM5);
786}
787
788static void haswell_restore_bclk(struct azx *chip)
789{
790 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
791
792 azx_writew(chip, EM4, hda->bclk_m);
793 azx_writew(chip, EM5, hda->bclk_n);
794}
795
7ccbde57 796#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 797/*
798 * power management
799 */
68cb2b55 800static int azx_suspend(struct device *dev)
1da177e4 801{
68cb2b55
TI		 802 struct pci_dev *pci = to_pci_dev(dev);
803 struct snd_card *card = dev_get_drvdata(dev);
421a1252 804 struct azx *chip = card->private_data;
01b65bfb 805 struct azx_pcm *p;
1da177e4 806
c5c21523
TI		 807 if (chip->disabled)
808 return 0;
809
421a1252 810 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 811 azx_clear_irq_pending(chip);
01b65bfb
TI		 812 list_for_each_entry(p, &chip->pcm_list, list)
813 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 814 if (chip->initialized)
8dd78330 815 snd_hda_suspend(chip->bus);
cb53c626 816 azx_stop_chip(chip);
7295b264 817 azx_enter_link_reset(chip);
30b35399 818 if (chip->irq >= 0) {
43001c95 819 free_irq(chip->irq, chip);
30b35399
TI		 820 chip->irq = -1;
821 }
a07187c9
ML		 822
823 /* Save BCLK M/N values before they become invalid in D3.
824 * Will test if display power well can be released now.
825 */
826 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
827 haswell_save_bclk(chip);
828
68e7fffc 829 if (chip->msi)
43001c95 830 pci_disable_msi(chip->pci);
421a1252
TI		 831 pci_disable_device(pci);
832 pci_save_state(pci);
68cb2b55 833 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 834 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
835 hda_display_power(false);
1da177e4
LT		 836 return 0;
837}
838
68cb2b55 839static int azx_resume(struct device *dev)
1da177e4 840{
68cb2b55
TI		 841 struct pci_dev *pci = to_pci_dev(dev);
842 struct snd_card *card = dev_get_drvdata(dev);
421a1252 843 struct azx *chip = card->private_data;
1da177e4 844
c5c21523
TI		 845 if (chip->disabled)
846 return 0;
847
a07187c9 848 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 849 hda_display_power(true);
a07187c9
ML		 850 haswell_restore_bclk(chip);
851 }
d14a7e0b
TI		 852 pci_set_power_state(pci, PCI_D0);
853 pci_restore_state(pci);
30b35399 854 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 855 dev_err(chip->card->dev,
856 "pci_enable_device failed, disabling device\n");
30b35399
TI		 857 snd_card_disconnect(card);
858 return -EIO;
859 }
860 pci_set_master(pci);
68e7fffc
TI		 861 if (chip->msi)
862 if (pci_enable_msi(pci) < 0)
863 chip->msi = 0;
864 if (azx_acquire_irq(chip, 1) < 0)
30b35399 865 return -EIO;
cb53c626 866 azx_init_pci(chip);
d804ad92 867
17c3ad03 868 azx_init_chip(chip, true);
d804ad92 869
1da177e4 870 snd_hda_resume(chip->bus);
421a1252 871 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 872 return 0;
873}
b8dfc462
ML		 874#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
875
876#ifdef CONFIG_PM_RUNTIME
877static int azx_runtime_suspend(struct device *dev)
878{
879 struct snd_card *card = dev_get_drvdata(dev);
880 struct azx *chip = card->private_data;
881
246efa4a
DA		 882 if (chip->disabled)
883 return 0;
884
885 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
886 return 0;
887
7d4f606c
WX		 888 /* enable controller wake up event */
889 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
890 STATESTS_INT_MASK);
891
b8dfc462 892 azx_stop_chip(chip);
873ce8ad 893 azx_enter_link_reset(chip);
b8dfc462 894 azx_clear_irq_pending(chip);
a07187c9
ML		 895 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
896 haswell_save_bclk(chip);
99a2008d 897 hda_display_power(false);
a07187c9 898 }
b8dfc462
ML		 899 return 0;
900}
901
902static int azx_runtime_resume(struct device *dev)
903{
904 struct snd_card *card = dev_get_drvdata(dev);
905 struct azx *chip = card->private_data;
7d4f606c
WX		 906 struct hda_bus *bus;
907 struct hda_codec *codec;
908 int status;
b8dfc462 909
246efa4a
DA		 910 if (chip->disabled)
911 return 0;
912
913 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
914 return 0;
915
a07187c9 916 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 917 hda_display_power(true);
a07187c9
ML		 918 haswell_restore_bclk(chip);
919 }
7d4f606c
WX		 920
921 /* Read STATESTS before controller reset */
922 status = azx_readw(chip, STATESTS);
923
b8dfc462 924 azx_init_pci(chip);
17c3ad03 925 azx_init_chip(chip, true);
7d4f606c
WX		 926
927 bus = chip->bus;
928 if (status && bus) {
929 list_for_each_entry(codec, &bus->codec_list, list)
930 if (status & (1 << codec->addr))
931 queue_delayed_work(codec->bus->workq,
932 &codec->jackpoll_work, codec->jackpoll_interval);
933 }
934
935 /* disable controller Wake Up event*/
936 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
937 ~STATESTS_INT_MASK);
938
b8dfc462
ML		 939 return 0;
940}
6eb827d2
TI		 941
942static int azx_runtime_idle(struct device *dev)
943{
944 struct snd_card *card = dev_get_drvdata(dev);
945 struct azx *chip = card->private_data;
946
246efa4a
DA		 947 if (chip->disabled)
948 return 0;
949
6eb827d2
TI		 950 if (!power_save_controller ||
951 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
952 return -EBUSY;
953
954 return 0;
955}
956
b8dfc462
ML		 957#endif /* CONFIG_PM_RUNTIME */
958
959#ifdef CONFIG_PM
960static const struct dev_pm_ops azx_pm = {
961 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 962 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 963};
964
68cb2b55
TI		 965#define AZX_PM_OPS &azx_pm
966#else
68cb2b55 967#define AZX_PM_OPS NULL
b8dfc462 968#endif /* CONFIG_PM */
1da177e4
LT		 969
970
48c8b0eb 971static int azx_probe_continue(struct azx *chip);
a82d51ed 972
8393ec4a 973#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 974static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 975
a82d51ed
TI		 976static void azx_vs_set_state(struct pci_dev *pci,
977 enum vga_switcheroo_state state)
978{
979 struct snd_card *card = pci_get_drvdata(pci);
980 struct azx *chip = card->private_data;
9a34af4a 981 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 982 bool disabled;
983
9a34af4a
TI		 984 wait_for_completion(&hda->probe_wait);
985 if (hda->init_failed)
a82d51ed
TI		 986 return;
987
988 disabled = (state == VGA_SWITCHEROO_OFF);
989 if (chip->disabled == disabled)
990 return;
991
992 if (!chip->bus) {
993 chip->disabled = disabled;
994 if (!disabled) {
4e76a883
TI		 995 dev_info(chip->card->dev,
996 "Start delayed initialization\n");
5c90680e 997 if (azx_probe_continue(chip) < 0) {
4e76a883 998 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 999 hda->init_failed = true;
a82d51ed
TI		 1000 }
1001 }
1002 } else {
4e76a883
TI		 1003 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1004 disabled ? "Disabling" : "Enabling");
a82d51ed 1005 if (disabled) {
8928756d
DR		 1006 pm_runtime_put_sync_suspend(card->dev);
1007 azx_suspend(card->dev);
246efa4a
DA		 1008 /* when we get suspended by vga switcheroo we end up in D3cold,
1009 * however we have no ACPI handle, so pci/acpi can't put us there,
1010 * put ourselves there */
1011 pci->current_state = PCI_D3cold;
a82d51ed 1012 chip->disabled = true;
128960a9 1013 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1014 dev_warn(chip->card->dev,
1015 "Cannot lock devices!\n");
a82d51ed
TI		 1016 } else {
1017 snd_hda_unlock_devices(chip->bus);
8928756d 1018 pm_runtime_get_noresume(card->dev);
a82d51ed 1019 chip->disabled = false;
8928756d 1020 azx_resume(card->dev);
a82d51ed
TI		 1021 }
1022 }
1023}
1024
1025static bool azx_vs_can_switch(struct pci_dev *pci)
1026{
1027 struct snd_card *card = pci_get_drvdata(pci);
1028 struct azx *chip = card->private_data;
9a34af4a 1029 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1030
9a34af4a
TI		 1031 wait_for_completion(&hda->probe_wait);
1032 if (hda->init_failed)
a82d51ed
TI		 1033 return false;
1034 if (chip->disabled || !chip->bus)
1035 return true;
1036 if (snd_hda_lock_devices(chip->bus))
1037 return false;
1038 snd_hda_unlock_devices(chip->bus);
1039 return true;
1040}
1041
e23e7a14 1042static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1043{
9a34af4a 1044 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1045 struct pci_dev *p = get_bound_vga(chip->pci);
1046 if (p) {
4e76a883
TI		 1047 dev_info(chip->card->dev,
1048 "Handle VGA-switcheroo audio client\n");
9a34af4a 1049 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1050 pci_dev_put(p);
1051 }
1052}
1053
1054static const struct vga_switcheroo_client_ops azx_vs_ops = {
1055 .set_gpu_state = azx_vs_set_state,
1056 .can_switch = azx_vs_can_switch,
1057};
1058
e23e7a14 1059static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1060{
9a34af4a 1061 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1062 int err;
1063
9a34af4a 1064 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1065 return 0;
1066 /* FIXME: currently only handling DIS controller
1067 * is there any machine with two switchable HDMI audio controllers?
1068 */
128960a9 1069 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1070 VGA_SWITCHEROO_DIS,
1071 chip->bus != NULL);
128960a9
TI		 1072 if (err < 0)
1073 return err;
9a34af4a 1074 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1075
1076 /* register as an optimus hdmi audio power domain */
8928756d 1077 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1078 &hda->hdmi_pm_domain);
128960a9 1079 return 0;
a82d51ed
TI		 1080}
1081#else
1082#define init_vga_switcheroo(chip) /* NOP */
1083#define register_vga_switcheroo(chip) 0
8393ec4a 1084#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1085#endif /* SUPPORT_VGA_SWITCHER */
1086
1da177e4
LT		 1087/*
1088 * destructor
1089 */
a98f90fd 1090static int azx_free(struct azx *chip)
1da177e4 1091{
c67e2228 1092 struct pci_dev *pci = chip->pci;
a07187c9 1093 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1094 int i;
1095
c67e2228
WX		 1096 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1097 && chip->running)
1098 pm_runtime_get_noresume(&pci->dev);
1099
65fcd41d
TI		 1100 azx_del_card_list(chip);
1101
0cbf0098
TI		 1102 azx_notifier_unregister(chip);
1103
9a34af4a
TI		 1104 hda->init_failed = 1; /* to be sure */
1105 complete_all(&hda->probe_wait);
f4c482a4 1106
9a34af4a 1107 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1108 if (chip->disabled && chip->bus)
1109 snd_hda_unlock_devices(chip->bus);
9a34af4a 1110 if (hda->vga_switcheroo_registered)
128960a9 1111 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1112 }
1113
ce43fbae 1114 if (chip->initialized) {
9ad593f6 1115 azx_clear_irq_pending(chip);
07e4ca50 1116 for (i = 0; i < chip->num_streams; i++)
1da177e4 1117 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1118 azx_stop_chip(chip);
1da177e4
LT		 1119 }
1120
f000fd80 1121 if (chip->irq >= 0)
1da177e4 1122 free_irq(chip->irq, (void*)chip);
68e7fffc 1123 if (chip->msi)
30b35399 1124 pci_disable_msi(chip->pci);
f079c25a
TI		 1125 if (chip->remap_addr)
1126 iounmap(chip->remap_addr);
1da177e4 1127
67908994 1128 azx_free_stream_pages(chip);
a82d51ed
TI		 1129 if (chip->region_requested)
1130 pci_release_regions(chip->pci);
1da177e4 1131 pci_disable_device(chip->pci);
07e4ca50 1132 kfree(chip->azx_dev);
4918cdab
TI		 1133#ifdef CONFIG_SND_HDA_PATCH_LOADER
1134 if (chip->fw)
1135 release_firmware(chip->fw);
1136#endif
99a2008d
WX		 1137 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1138 hda_display_power(false);
1139 hda_i915_exit();
1140 }
a07187c9 1141 kfree(hda);
1da177e4
LT		 1142
1143 return 0;
1144}
1145
a98f90fd 1146static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1147{
1148 return azx_free(device->device_data);
1149}
1150
8393ec4a 1151#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1152/*
1153 * Check of disabled HDMI controller by vga-switcheroo
1154 */
e23e7a14 1155static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1156{
1157 struct pci_dev *p;
1158
1159 /* check only discrete GPU */
1160 switch (pci->vendor) {
1161 case PCI_VENDOR_ID_ATI:
1162 case PCI_VENDOR_ID_AMD:
1163 case PCI_VENDOR_ID_NVIDIA:
1164 if (pci->devfn == 1) {
1165 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1166 pci->bus->number, 0);
1167 if (p) {
1168 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1169 return p;
1170 pci_dev_put(p);
1171 }
1172 }
1173 break;
1174 }
1175 return NULL;
1176}
1177
e23e7a14 1178static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1179{
1180 bool vga_inactive = false;
1181 struct pci_dev *p = get_bound_vga(pci);
1182
1183 if (p) {
12b78a7f 1184 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1185 vga_inactive = true;
1186 pci_dev_put(p);
1187 }
1188 return vga_inactive;
1189}
8393ec4a 1190#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1191
3372a153
TI		 1192/*
1193 * white/black-listing for position_fix
1194 */
e23e7a14 1195static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1196 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1197 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1198 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1199 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1200 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1201 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1202 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1203 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1204 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1205 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1206 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1207 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1208 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1209 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1210 {}
1211};
1212
e23e7a14 1213static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1214{
1215 const struct snd_pci_quirk *q;
1216
c673ba1c 1217 switch (fix) {
1dac6695 1218 case POS_FIX_AUTO:
c673ba1c
TI		 1219 case POS_FIX_LPIB:
1220 case POS_FIX_POSBUF:
4cb36310 1221 case POS_FIX_VIACOMBO:
a6f2fd55 1222 case POS_FIX_COMBO:
c673ba1c
TI		 1223 return fix;
1224 }
1225
c673ba1c
TI		 1226 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1227 if (q) {
4e76a883
TI		 1228 dev_info(chip->card->dev,
1229 "position_fix set to %d for device %04x:%04x\n",
1230 q->value, q->subvendor, q->subdevice);
c673ba1c 1231 return q->value;
3372a153 1232 }
bdd9ef24
DH		 1233
1234 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1235 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1236 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1237 return POS_FIX_VIACOMBO;
9477c58e
TI		 1238 }
1239 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1240 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1241 return POS_FIX_LPIB;
bdd9ef24 1242 }
c673ba1c 1243 return POS_FIX_AUTO;
3372a153
TI		 1244}
1245
b6050ef6
TI		 1246static void assign_position_fix(struct azx *chip, int fix)
1247{
1248 static azx_get_pos_callback_t callbacks[] = {
1249 [POS_FIX_AUTO] = NULL,
1250 [POS_FIX_LPIB] = azx_get_pos_lpib,
1251 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1252 [POS_FIX_VIACOMBO] = azx_via_get_position,
1253 [POS_FIX_COMBO] = azx_get_pos_lpib,
1254 };
1255
1256 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1257
1258 /* combo mode uses LPIB only for playback */
1259 if (fix == POS_FIX_COMBO)
1260 chip->get_position[1] = NULL;
1261
1262 if (fix == POS_FIX_POSBUF &&
1263 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1264 chip->get_delay[0] = chip->get_delay[1] =
1265 azx_get_delay_from_lpib;
1266 }
1267
1268}
1269
669ba27a
TI		 1270/*
1271 * black-lists for probe_mask
1272 */
e23e7a14 1273static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1274 /* Thinkpad often breaks the controller communication when accessing
1275 * to the non-working (or non-existing) modem codec slot.
1276 */
1277 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1278 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1279 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1280 /* broken BIOS */
1281 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1282 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1283 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1284 /* forced codec slots */
93574844 1285 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1286 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1287 /* WinFast VP200 H (Teradici) user reported broken communication */
1288 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1289 {}
1290};
1291
f1eaaeec
TI		 1292#define AZX_FORCE_CODEC_MASK 0x100
1293
e23e7a14 1294static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1295{
1296 const struct snd_pci_quirk *q;
1297
f1eaaeec
TI		 1298 chip->codec_probe_mask = probe_mask[dev];
1299 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1300 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1301 if (q) {
4e76a883
TI		 1302 dev_info(chip->card->dev,
1303 "probe_mask set to 0x%x for device %04x:%04x\n",
1304 q->value, q->subvendor, q->subdevice);
f1eaaeec 1305 chip->codec_probe_mask = q->value;
669ba27a
TI		 1306 }
1307 }
f1eaaeec
TI		 1308
1309 /* check forced option */
1310 if (chip->codec_probe_mask != -1 &&
1311 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1312 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1313 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1314 chip->codec_mask);
f1eaaeec 1315 }
669ba27a
TI		 1316}
1317
4d8e22e0 1318/*
71623855 1319 * white/black-list for enable_msi
4d8e22e0 1320 */
e23e7a14 1321static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1322 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1323 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1324 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1325 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1326 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1327 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1328 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1329 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1330 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1331 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1332 {}
1333};
1334
e23e7a14 1335static void check_msi(struct azx *chip)
4d8e22e0
TI		 1336{
1337 const struct snd_pci_quirk *q;
1338
71623855
TI		 1339 if (enable_msi >= 0) {
1340 chip->msi = !!enable_msi;
4d8e22e0 1341 return;
71623855
TI		 1342 }
1343 chip->msi = 1; /* enable MSI as default */
1344 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1345 if (q) {
4e76a883
TI		 1346 dev_info(chip->card->dev,
1347 "msi for device %04x:%04x set to %d\n",
1348 q->subvendor, q->subdevice, q->value);
4d8e22e0 1349 chip->msi = q->value;
80c43ed7
TI		 1350 return;
1351 }
1352
1353 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1354 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1355 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1356 chip->msi = 0;
4d8e22e0
TI		 1357 }
1358}
1359
a1585d76 1360/* check the snoop mode availability */
e23e7a14 1361static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1362{
1363 bool snoop = chip->snoop;
1364
1365 switch (chip->driver_type) {
1366 case AZX_DRIVER_VIA:
1367 /* force to non-snoop mode for a new VIA controller
1368 * when BIOS is set
1369 */
1370 if (snoop) {
1371 u8 val;
1372 pci_read_config_byte(chip->pci, 0x42, &val);
1373 if (!(val & 0x80) && chip->pci->revision == 0x30)
1374 snoop = false;
1375 }
1376 break;
1377 case AZX_DRIVER_ATIHDMI_NS:
1378 /* new ATI HDMI requires non-snoop */
1379 snoop = false;
1380 break;
c1279f87
TI		 1381 case AZX_DRIVER_CTHDA:
1382 snoop = false;
1383 break;
a1585d76
TI		 1384 }
1385
1386 if (snoop != chip->snoop) {
4e76a883
TI		 1387 dev_info(chip->card->dev, "Force to %s mode\n",
1388 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1389 chip->snoop = snoop;
1390 }
1391}
669ba27a 1392
99a2008d
WX		 1393static void azx_probe_work(struct work_struct *work)
1394{
9a34af4a
TI		 1395 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1396 azx_probe_continue(&hda->chip);
99a2008d 1397}
99a2008d 1398
1da177e4
LT		 1399/*
1400 * constructor
1401 */
e23e7a14
BP		 1402static int azx_create(struct snd_card *card, struct pci_dev *pci,
1403 int dev, unsigned int driver_caps,
40830813 1404 const struct hda_controller_ops *hda_ops,
e23e7a14 1405 struct azx **rchip)
1da177e4 1406{
a98f90fd 1407 static struct snd_device_ops ops = {
1da177e4
LT		 1408 .dev_free = azx_dev_free,
1409 };
a07187c9 1410 struct hda_intel *hda;
a82d51ed
TI		 1411 struct azx *chip;
1412 int err;
1da177e4
LT		 1413
1414 *rchip = NULL;
bcd72003 1415
927fc866
PM		 1416 err = pci_enable_device(pci);
1417 if (err < 0)
1da177e4
LT		 1418 return err;
1419
a07187c9
ML		 1420 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1421 if (!hda) {
1422 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1423 pci_disable_device(pci);
1424 return -ENOMEM;
1425 }
1426
a07187c9 1427 chip = &hda->chip;
1da177e4 1428 spin_lock_init(&chip->reg_lock);
62932df8 1429 mutex_init(&chip->open_mutex);
1da177e4
LT		 1430 chip->card = card;
1431 chip->pci = pci;
40830813 1432 chip->ops = hda_ops;
1da177e4 1433 chip->irq = -1;
9477c58e
TI		 1434 chip->driver_caps = driver_caps;
1435 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1436 check_msi(chip);
555e219f 1437 chip->dev_index = dev;
749ee287 1438 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1439 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1440 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1441 INIT_LIST_HEAD(&hda->list);
a82d51ed 1442 init_vga_switcheroo(chip);
9a34af4a 1443 init_completion(&hda->probe_wait);
1da177e4 1444
b6050ef6 1445 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1446
5aba4f8e 1447 check_probe_mask(chip, dev);
3372a153 1448
27346166 1449 chip->single_cmd = single_cmd;
27fe48d9 1450 chip->snoop = hda_snoop;
a1585d76 1451 azx_check_snoop_available(chip);
c74db86b 1452
5c0d7bc1
TI		 1453 if (bdl_pos_adj[dev] < 0) {
1454 switch (chip->driver_type) {
0c6341ac 1455 case AZX_DRIVER_ICH:
32679f95 1456 case AZX_DRIVER_PCH:
0c6341ac 1457 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1458 break;
1459 default:
0c6341ac 1460 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1461 break;
1462 }
1463 }
9cdc0115 1464 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1465
a82d51ed
TI		 1466 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1467 if (err < 0) {
4e76a883 1468 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1469 azx_free(chip);
1470 return err;
1471 }
1472
99a2008d 1473 /* continue probing in work context as may trigger request module */
9a34af4a 1474 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1475
a82d51ed 1476 *rchip = chip;
99a2008d 1477
a82d51ed
TI		 1478 return 0;
1479}
1480
48c8b0eb 1481static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1482{
1483 int dev = chip->dev_index;
1484 struct pci_dev *pci = chip->pci;
1485 struct snd_card *card = chip->card;
67908994 1486 int err;
a82d51ed
TI		 1487 unsigned short gcap;
1488
07e4ca50
TI		 1489#if BITS_PER_LONG != 64
1490 /* Fix up base address on ULI M5461 */
1491 if (chip->driver_type == AZX_DRIVER_ULI) {
1492 u16 tmp3;
1493 pci_read_config_word(pci, 0x40, &tmp3);
1494 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1495 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1496 }
1497#endif
1498
927fc866 1499 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1500 if (err < 0)
1da177e4 1501 return err;
a82d51ed 1502 chip->region_requested = 1;
1da177e4 1503
927fc866 1504 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1505 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1506 if (chip->remap_addr == NULL) {
4e76a883 1507 dev_err(card->dev, "ioremap error\n");
a82d51ed 1508 return -ENXIO;
1da177e4
LT		 1509 }
1510
68e7fffc
TI		 1511 if (chip->msi)
1512 if (pci_enable_msi(pci) < 0)
1513 chip->msi = 0;
7376d013 1514
a82d51ed
TI		 1515 if (azx_acquire_irq(chip, 0) < 0)
1516 return -EBUSY;
1da177e4
LT		 1517
1518 pci_set_master(pci);
1519 synchronize_irq(chip->irq);
1520
bcd72003 1521 gcap = azx_readw(chip, GCAP);
4e76a883 1522 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1523
dc4c2e6b 1524 /* disable SB600 64bit support for safety */
9477c58e 1525 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1526 struct pci_dev *p_smbus;
1527 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1528 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1529 NULL);
1530 if (p_smbus) {
1531 if (p_smbus->revision < 0x30)
1532 gcap &= ~ICH6_GCAP_64OK;
1533 pci_dev_put(p_smbus);
1534 }
1535 }
09240cf4 1536
9477c58e
TI		 1537 /* disable 64bit DMA address on some devices */
1538 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1539 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1540 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1541 }
396087ea 1542
2ae66c26 1543 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1544 if (align_buffer_size >= 0)
1545 chip->align_buffer_size = !!align_buffer_size;
1546 else {
1547 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1548 chip->align_buffer_size = 0;
1549 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1550 chip->align_buffer_size = 1;
1551 else
1552 chip->align_buffer_size = 1;
1553 }
2ae66c26 1554
cf7aaca8 1555 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1556 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1558 else {
e930438c
YH		 1559 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1560 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1561 }
cf7aaca8 1562
8b6ed8e7
TI		 1563 /* read number of streams from GCAP register instead of using
1564 * hardcoded value
1565 */
1566 chip->capture_streams = (gcap >> 8) & 0x0f;
1567 chip->playback_streams = (gcap >> 12) & 0x0f;
1568 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1569 /* gcap didn't give any info, switching to old method */
1570
1571 switch (chip->driver_type) {
1572 case AZX_DRIVER_ULI:
1573 chip->playback_streams = ULI_NUM_PLAYBACK;
1574 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1575 break;
1576 case AZX_DRIVER_ATIHDMI:
1815b34a 1577 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1578 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1579 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1580 break;
c4da29ca 1581 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1582 default:
1583 chip->playback_streams = ICH6_NUM_PLAYBACK;
1584 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1585 break;
1586 }
07e4ca50 1587 }
8b6ed8e7
TI		 1588 chip->capture_index_offset = 0;
1589 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1590 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1591 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1592 GFP_KERNEL);
927fc866 1593 if (!chip->azx_dev) {
4e76a883 1594 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1595 return -ENOMEM;
07e4ca50
TI		 1596 }
1597
67908994 1598 err = azx_alloc_stream_pages(chip);
81740861 1599 if (err < 0)
a82d51ed 1600 return err;
1da177e4
LT		 1601
1602 /* initialize streams */
1603 azx_init_stream(chip);
1604
1605 /* initialize chip */
cb53c626 1606 azx_init_pci(chip);
10e77dda 1607 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1608
1609 /* codec detection */
927fc866 1610 if (!chip->codec_mask) {
4e76a883 1611 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1612 return -ENODEV;
1da177e4
LT		 1613 }
1614
07e4ca50 1615 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1616 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1617 sizeof(card->shortname));
1618 snprintf(card->longname, sizeof(card->longname),
1619 "%s at 0x%lx irq %i",
1620 card->shortname, chip->addr, chip->irq);
07e4ca50 1621
1da177e4 1622 return 0;
1da177e4
LT		 1623}
1624
cb53c626
TI		 1625static void power_down_all_codecs(struct azx *chip)
1626{
83012a7c 1627#ifdef CONFIG_PM
cb53c626
TI		 1628 /* The codecs were powered up in snd_hda_codec_new().
1629 * Now all initialization done, so turn them down if possible
1630 */
1631 struct hda_codec *codec;
1632 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1633 snd_hda_power_down(codec);
1634 }
1635#endif
1636}
1637
97c6a3d1 1638#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1639/* callback from request_firmware_nowait() */
1640static void azx_firmware_cb(const struct firmware *fw, void *context)
1641{
1642 struct snd_card *card = context;
1643 struct azx *chip = card->private_data;
1644 struct pci_dev *pci = chip->pci;
1645
1646 if (!fw) {
4e76a883 1647 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1648 goto error;
1649 }
1650
1651 chip->fw = fw;
1652 if (!chip->disabled) {
1653 /* continue probing */
1654 if (azx_probe_continue(chip))
1655 goto error;
1656 }
1657 return; /* OK */
1658
1659 error:
1660 snd_card_free(card);
1661 pci_set_drvdata(pci, NULL);
1662}
97c6a3d1 1663#endif
5cb543db 1664
40830813
DR		 1665/*
1666 * HDA controller ops.
1667 */
1668
1669/* PCI register access. */
db291e36 1670static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1671{
1672 writel(value, addr);
1673}
1674
db291e36 1675static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1676{
1677 return readl(addr);
1678}
1679
db291e36 1680static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1681{
1682 writew(value, addr);
1683}
1684
db291e36 1685static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1686{
1687 return readw(addr);
1688}
1689
db291e36 1690static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1691{
1692 writeb(value, addr);
1693}
1694
db291e36 1695static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1696{
1697 return readb(addr);
1698}
1699
f46ea609
DR		 1700static int disable_msi_reset_irq(struct azx *chip)
1701{
1702 int err;
1703
1704 free_irq(chip->irq, chip);
1705 chip->irq = -1;
1706 pci_disable_msi(chip->pci);
1707 chip->msi = 0;
1708 err = azx_acquire_irq(chip, 1);
1709 if (err < 0)
1710 return err;
1711
1712 return 0;
1713}
1714
b419b35b
DR		 1715/* DMA page allocation helpers. */
1716static int dma_alloc_pages(struct azx *chip,
1717 int type,
1718 size_t size,
1719 struct snd_dma_buffer *buf)
1720{
1721 int err;
1722
1723 err = snd_dma_alloc_pages(type,
1724 chip->card->dev,
1725 size, buf);
1726 if (err < 0)
1727 return err;
1728 mark_pages_wc(chip, buf, true);
1729 return 0;
1730}
1731
1732static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1733{
1734 mark_pages_wc(chip, buf, false);
1735 snd_dma_free_pages(buf);
1736}
1737
1738static int substream_alloc_pages(struct azx *chip,
1739 struct snd_pcm_substream *substream,
1740 size_t size)
1741{
1742 struct azx_dev *azx_dev = get_azx_dev(substream);
1743 int ret;
1744
1745 mark_runtime_wc(chip, azx_dev, substream, false);
1746 azx_dev->bufsize = 0;
1747 azx_dev->period_bytes = 0;
1748 azx_dev->format_val = 0;
1749 ret = snd_pcm_lib_malloc_pages(substream, size);
1750 if (ret < 0)
1751 return ret;
1752 mark_runtime_wc(chip, azx_dev, substream, true);
1753 return 0;
1754}
1755
1756static int substream_free_pages(struct azx *chip,
1757 struct snd_pcm_substream *substream)
1758{
1759 struct azx_dev *azx_dev = get_azx_dev(substream);
1760 mark_runtime_wc(chip, azx_dev, substream, false);
1761 return snd_pcm_lib_free_pages(substream);
1762}
1763
8769b278
DR		 1764static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1765 struct vm_area_struct *area)
1766{
1767#ifdef CONFIG_X86
1768 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1769 struct azx *chip = apcm->chip;
1770 if (!azx_snoop(chip))
1771 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1772#endif
1773}
1774
40830813 1775static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1776 .reg_writel = pci_azx_writel,
1777 .reg_readl = pci_azx_readl,
1778 .reg_writew = pci_azx_writew,
1779 .reg_readw = pci_azx_readw,
1780 .reg_writeb = pci_azx_writeb,
1781 .reg_readb = pci_azx_readb,
f46ea609 1782 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1783 .dma_alloc_pages = dma_alloc_pages,
1784 .dma_free_pages = dma_free_pages,
1785 .substream_alloc_pages = substream_alloc_pages,
1786 .substream_free_pages = substream_free_pages,
8769b278 1787 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1788 .position_check = azx_position_check,
40830813
DR		 1789};
1790
e23e7a14
BP		 1791static int azx_probe(struct pci_dev *pci,
1792 const struct pci_device_id *pci_id)
1da177e4 1793{
5aba4f8e 1794 static int dev;
a98f90fd 1795 struct snd_card *card;
9a34af4a 1796 struct hda_intel *hda;
a98f90fd 1797 struct azx *chip;
aad730d0 1798 bool schedule_probe;
927fc866 1799 int err;
1da177e4 1800
5aba4f8e
TI		 1801 if (dev >= SNDRV_CARDS)
1802 return -ENODEV;
1803 if (!enable[dev]) {
1804 dev++;
1805 return -ENOENT;
1806 }
1807
60c5772b
TI		 1808 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1809 0, &card);
e58de7ba 1810 if (err < 0) {
4e76a883 1811 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1812 return err;
1da177e4
LT		 1813 }
1814
40830813
DR		 1815 err = azx_create(card, pci, dev, pci_id->driver_data,
1816 &pci_hda_ops, &chip);
41dda0fd
WF		 1817 if (err < 0)
1818 goto out_free;
421a1252 1819 card->private_data = chip;
9a34af4a 1820 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1821
1822 pci_set_drvdata(pci, card);
1823
1824 err = register_vga_switcheroo(chip);
1825 if (err < 0) {
4e76a883 1826 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1827 goto out_free;
1828 }
1829
1830 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1831 dev_info(card->dev, "VGA controller is disabled\n");
1832 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1833 chip->disabled = true;
1834 }
1835
aad730d0 1836 schedule_probe = !chip->disabled;
1da177e4 1837
4918cdab
TI		 1838#ifdef CONFIG_SND_HDA_PATCH_LOADER
1839 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1840 dev_info(card->dev, "Applying patch firmware '%s'\n",
1841 patch[dev]);
5cb543db
TI		 1842 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1843 &pci->dev, GFP_KERNEL, card,
1844 azx_firmware_cb);
4918cdab
TI		 1845 if (err < 0)
1846 goto out_free;
aad730d0 1847 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1848 }
1849#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1850
aad730d0
TI		 1851#ifndef CONFIG_SND_HDA_I915
1852 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1853 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1854#endif
99a2008d 1855
aad730d0 1856 if (schedule_probe)
9a34af4a 1857 schedule_work(&hda->probe_work);
a82d51ed 1858
a82d51ed 1859 dev++;
88d071fc 1860 if (chip->disabled)
9a34af4a 1861 complete_all(&hda->probe_wait);
a82d51ed
TI		 1862 return 0;
1863
1864out_free:
1865 snd_card_free(card);
1866 return err;
1867}
1868
e62a42ae
DR		 1869/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1870static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1871 [AZX_DRIVER_NVIDIA] = 8,
1872 [AZX_DRIVER_TERA] = 1,
1873};
1874
48c8b0eb 1875static int azx_probe_continue(struct azx *chip)
a82d51ed 1876{
9a34af4a 1877 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1878 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1879 int dev = chip->dev_index;
1880 int err;
1881
99a2008d
WX		 1882 /* Request power well for Haswell HDA controller and codec */
1883 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1884#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1885 err = hda_i915_init();
1886 if (err < 0) {
4e76a883
TI		 1887 dev_err(chip->card->dev,
1888 "Error request power-well from i915\n");
99a2008d
WX		 1889 goto out_free;
1890 }
74b0c2d7
TI		 1891 err = hda_display_power(true);
1892 if (err < 0) {
1893 dev_err(chip->card->dev,
1894 "Cannot turn on display power on i915\n");
1895 goto out_free;
1896 }
c841ad2a 1897#endif
99a2008d
WX		 1898 }
1899
5c90680e
TI		 1900 err = azx_first_init(chip);
1901 if (err < 0)
1902 goto out_free;
1903
2dca0bba
JK		 1904#ifdef CONFIG_SND_HDA_INPUT_BEEP
1905 chip->beep_mode = beep_mode[dev];
1906#endif
1907
1da177e4 1908 /* create codec instances */
e62a42ae
DR		 1909 err = azx_codec_create(chip, model[dev],
1910 azx_max_codecs[chip->driver_type],
1911 power_save_addr);
1912
41dda0fd
WF		 1913 if (err < 0)
1914 goto out_free;
4ea6fbc8 1915#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1916 if (chip->fw) {
1917 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1918 chip->fw->data);
4ea6fbc8
TI		 1919 if (err < 0)
1920 goto out_free;
e39ae856 1921#ifndef CONFIG_PM
4918cdab
TI		 1922 release_firmware(chip->fw); /* no longer needed */
1923 chip->fw = NULL;
e39ae856 1924#endif
4ea6fbc8
TI		 1925 }
1926#endif
10e77dda 1927 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1928 err = azx_codec_configure(chip);
1929 if (err < 0)
1930 goto out_free;
1931 }
1da177e4
LT		 1932
1933 /* create PCM streams */
176d5335 1934 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1935 if (err < 0)
1936 goto out_free;
1da177e4
LT		 1937
1938 /* create mixer controls */
d01ce99f 1939 err = azx_mixer_create(chip);
41dda0fd
WF		 1940 if (err < 0)
1941 goto out_free;
1da177e4 1942
a82d51ed 1943 err = snd_card_register(chip->card);
41dda0fd
WF		 1944 if (err < 0)
1945 goto out_free;
1da177e4 1946
cb53c626
TI		 1947 chip->running = 1;
1948 power_down_all_codecs(chip);
0cbf0098 1949 azx_notifier_register(chip);
65fcd41d 1950 azx_add_card_list(chip);
9a34af4a 1951 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
c67e2228 1952 pm_runtime_put_noidle(&pci->dev);
1da177e4 1953
41dda0fd 1954out_free:
88d071fc 1955 if (err < 0)
9a34af4a
TI		 1956 hda->init_failed = 1;
1957 complete_all(&hda->probe_wait);
41dda0fd 1958 return err;
1da177e4
LT		 1959}
1960
e23e7a14 1961static void azx_remove(struct pci_dev *pci)
1da177e4 1962{
9121947d 1963 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1964
9121947d
TI		 1965 if (card)
1966 snd_card_free(card);
1da177e4
LT		 1967}
1968
1969/* PCI IDs */
6f51f6cf 1970static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1971 /* CPT */
9477c58e 1972 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1973 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1974 /* PBG */
9477c58e 1975 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1976 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1977 /* Panther Point */
9477c58e 1978 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1979 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1980 /* Lynx Point */
1981 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1982 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1983 /* 9 Series */
1984 { PCI_DEVICE(0x8086, 0x8ca0),
1985 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1986 /* Wellsburg */
1987 { PCI_DEVICE(0x8086, 0x8d20),
1988 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1989 { PCI_DEVICE(0x8086, 0x8d21),
1990 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1991 /* Lynx Point-LP */
1992 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1993 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1994 /* Lynx Point-LP */
1995 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1996 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1997 /* Wildcat Point-LP */
1998 { PCI_DEVICE(0x8086, 0x9ca0),
1999 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 2000 /* Haswell */
4a7c516b 2001 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2002 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2003 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2004 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2005 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2006 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2007 /* Broadwell */
2008 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2009 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2010 /* 5 Series/3400 */
2011 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2012 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2013 /* Poulsbo */
9477c58e 2014 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2015 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2016 /* Oaktrail */
09904b95 2017 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2018 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2019 /* BayTrail */
2020 { PCI_DEVICE(0x8086, 0x0f04),
2021 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 2022 /* ICH */
8b0bd226 2023 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 2024 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2025 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 2026 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 2027 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2028 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 2029 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 2030 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2031 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 2032 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 2033 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2034 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 2035 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 2036 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2037 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2038 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 2039 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2040 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2041 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 2042 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2043 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 2044 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 2045 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2046 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 2047 /* Generic Intel */
2048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2049 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2050 .class_mask = 0xffffff,
2ae66c26 2051 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 2052 /* ATI SB 450/600/700/800/900 */
2053 { PCI_DEVICE(0x1002, 0x437b),
2054 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2055 { PCI_DEVICE(0x1002, 0x4383),
2056 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2057 /* AMD Hudson */
2058 { PCI_DEVICE(0x1022, 0x780d),
2059 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2060 /* ATI HDMI */
9477c58e
TI		 2061 { PCI_DEVICE(0x1002, 0x793b),
2062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2063 { PCI_DEVICE(0x1002, 0x7919),
2064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2065 { PCI_DEVICE(0x1002, 0x960f),
2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2067 { PCI_DEVICE(0x1002, 0x970f),
2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2069 { PCI_DEVICE(0x1002, 0xaa00),
2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2071 { PCI_DEVICE(0x1002, 0xaa08),
2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2073 { PCI_DEVICE(0x1002, 0xaa10),
2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2075 { PCI_DEVICE(0x1002, 0xaa18),
2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2077 { PCI_DEVICE(0x1002, 0xaa20),
2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2079 { PCI_DEVICE(0x1002, 0xaa28),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0xaa30),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0xaa38),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0xaa40),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0xaa48),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2089 { PCI_DEVICE(0x1002, 0xaa50),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0xaa58),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2093 { PCI_DEVICE(0x1002, 0xaa60),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa68),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa80),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa88),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa90),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0xaa98),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 2105 { PCI_DEVICE(0x1002, 0x9902),
2106 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaaa0),
2108 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaaa8),
2110 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaab0),
2112 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 2113 /* VIA VT8251/VT8237A */
9477c58e
TI		 2114 { PCI_DEVICE(0x1106, 0x3288),
2115 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2116 /* VIA GFX VT7122/VX900 */
2117 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2118 /* VIA GFX VT6122/VX11 */
2119 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2120 /* SIS966 */
2121 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2122 /* ULI M5461 */
2123 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2124 /* NVIDIA MCP */
0c2fd1bf
TI		 2125 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2126 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2127 .class_mask = 0xffffff,
9477c58e 2128 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2129 /* Teradici */
9477c58e
TI		 2130 { PCI_DEVICE(0x6549, 0x1200),
2131 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2132 { PCI_DEVICE(0x6549, 0x2200),
2133 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2134 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2135 /* CTHDA chips */
2136 { PCI_DEVICE(0x1102, 0x0010),
2137 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2138 { PCI_DEVICE(0x1102, 0x0012),
2139 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2140#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2141 /* the following entry conflicts with snd-ctxfi driver,
2142 * as ctxfi driver mutates from HD-audio to native mode with
2143 * a special command sequence.
2144 */
4e01f54b
TI		 2145 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2146 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2147 .class_mask = 0xffffff,
9477c58e 2148 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2149 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2150#else
2151 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2152 { PCI_DEVICE(0x1102, 0x0009),
2153 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2154 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2155#endif
e35d4b11
OS		 2156 /* Vortex86MX */
2157 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2158 /* VMware HDAudio */
2159 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2160 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2161 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2162 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2163 .class_mask = 0xffffff,
9477c58e 2164 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2165 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2166 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2167 .class_mask = 0xffffff,
9477c58e 2168 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2169 { 0, }
2170};
2171MODULE_DEVICE_TABLE(pci, azx_ids);
2172
2173/* pci_driver definition */
e9f66d9b 2174static struct pci_driver azx_driver = {
3733e424 2175 .name = KBUILD_MODNAME,
1da177e4
LT		 2176 .id_table = azx_ids,
2177 .probe = azx_probe,
e23e7a14 2178 .remove = azx_remove,
68cb2b55
TI		 2179 .driver = {
2180 .pm = AZX_PM_OPS,
2181 },
1da177e4
LT		 2182};
2183
e9f66d9b 2184module_pci_driver(azx_driver);
Linux kernel - Deliverables
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