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ALSA: hda - add PCI IDs for Intel Broxton
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
93#define INTEL_SCH_HDA_DEVC 0x78
94#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96/* Define IN stream 0 FIFO size offset in VIA controller */
97#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98/* Define VIA HD Audio Device ID*/
99#define VIA_HDAC_DEVICE_ID 0x3288
100
33124929
TI		 101/* max number of SDs */
102/* ICH, ATI and VIA have 4 playback and 4 capture */
103#define ICH6_NUM_CAPTURE 4
104#define ICH6_NUM_PLAYBACK 4
105
106/* ULI has 6 playback and 5 capture */
107#define ULI_NUM_CAPTURE 5
108#define ULI_NUM_PLAYBACK 6
109
110/* ATI HDMI may have up to 8 playbacks and 0 capture */
111#define ATIHDMI_NUM_CAPTURE 0
112#define ATIHDMI_NUM_PLAYBACK 8
113
114/* TERA has 4 playback and 3 capture */
115#define TERA_NUM_CAPTURE 3
116#define TERA_NUM_PLAYBACK 4
117
1da177e4 118
5aba4f8e
TI		 119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 122static char *model[SNDRV_CARDS];
1dac6695 123static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 124static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 125static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 126static int probe_only[SNDRV_CARDS];
26a6cb6c 127static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 128static bool single_cmd;
71623855 129static int enable_msi = -1;
4ea6fbc8
TI		 130#ifdef CONFIG_SND_HDA_PATCH_LOADER
131static char *patch[SNDRV_CARDS];
132#endif
2dca0bba 133#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 134static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136#endif
1da177e4 137
5aba4f8e 138module_param_array(index, int, NULL, 0444);
1da177e4 139MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 140module_param_array(id, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 142module_param_array(enable, bool, NULL, 0444);
143MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144module_param_array(model, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 146module_param_array(position_fix, int, NULL, 0444);
4cb36310 147MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 149module_param_array(bdl_pos_adj, int, NULL, 0644);
150MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 151module_param_array(probe_mask, int, NULL, 0444);
606ad75f 152MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 153module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 154MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 155module_param_array(jackpoll_ms, int, NULL, 0444);
156MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 157module_param(single_cmd, bool, 0444);
d01ce99f
TI		 158MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
ac9ef6cf 160module_param(enable_msi, bint, 0444);
134a11f0 161MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 162#ifdef CONFIG_SND_HDA_PATCH_LOADER
163module_param_array(patch, charp, NULL, 0444);
164MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165#endif
2dca0bba 166#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 167module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 168MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 169 "(0=off, 1=on) (default=1).");
2dca0bba 170#endif
606ad75f 171
83012a7c 172#ifdef CONFIG_PM
65fcd41d 173static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 174static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 175 .set = param_set_xint,
176 .get = param_get_int,
177};
178#define param_check_xint param_check_int
179
fee2fba3 180static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 181module_param(power_save, xint, 0644);
fee2fba3
TI		 182MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
1da177e4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
fab1285a 262 AZX_DRIVER_HDMI,
07e4ca50 263 AZX_DRIVER_ATI,
778b6e1b 264 AZX_DRIVER_ATIHDMI,
1815b34a 265 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
da3fca21 269 AZX_DRIVER_NVIDIA,
f269002e 270 AZX_DRIVER_TERA,
14d34f16 271 AZX_DRIVER_CTX,
5ae763b1 272 AZX_DRIVER_CTHDA,
c563f473 273 AZX_DRIVER_CMEDIA,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
d7dab4db 287#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 290
291#define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 293
33499a15 294#define AZX_DCAPS_INTEL_HASWELL \
103884a3 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 298
54a0405d
LY		 299/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 304
40cc2392
ML		 305#define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
2d846c74
LY		 308#define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
d6795827 311#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
d6795827 314
c87693da
LH		 315#define AZX_DCAPS_INTEL_BROXTON \
316 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
317 AZX_DCAPS_I915_POWERWELL)
318
9477c58e
TI		 319/* quirks for ATI SB / AMD Hudson */
320#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 321 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
322 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 323
324/* quirks for ATI/AMD HDMI */
325#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 326 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
327 AZX_DCAPS_NO_MSI64)
9477c58e 328
37e661ee
TI		 329/* quirks for ATI HDMI with snoop off */
330#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
331 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
332
9477c58e
TI		 333/* quirks for Nvidia */
334#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 335 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 336 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
337 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 338
5ae763b1 339#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 340 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 341 AZX_DCAPS_NO_64BIT |\
37e661ee 342 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 343
a82d51ed
TI		 344/*
345 * VGA-switcher support
346 */
347#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 348#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
349#else
350#define use_vga_switcheroo(chip) 0
351#endif
352
03b135ce
LY		 353#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
354 ((pci)->device == 0x0c0c) || \
355 ((pci)->device == 0x0d0c) || \
356 ((pci)->device == 0x160c))
357
48c8b0eb 358static char *driver_short_names[] = {
07e4ca50 359 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 360 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 361 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 362 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 363 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 364 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 365 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 366 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
367 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 368 [AZX_DRIVER_ULI] = "HDA ULI M5461",
369 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 370 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 371 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 372 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 373 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 374 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 375};
376
27fe48d9 377#ifdef CONFIG_X86
9ddf1aeb 378static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 379{
9ddf1aeb
TI		 380 int pages;
381
27fe48d9
TI		 382 if (azx_snoop(chip))
383 return;
9ddf1aeb
TI		 384 if (!dmab || !dmab->area || !dmab->bytes)
385 return;
386
387#ifdef CONFIG_SND_DMA_SGBUF
388 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
389 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 390 if (chip->driver_type == AZX_DRIVER_CMEDIA)
391 return; /* deal with only CORB/RIRB buffers */
27fe48d9 392 if (on)
9ddf1aeb 393 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 394 else
9ddf1aeb
TI		 395 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
396 return;
27fe48d9 397 }
9ddf1aeb
TI		 398#endif
399
400 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
401 if (on)
402 set_memory_wc((unsigned long)dmab->area, pages);
403 else
404 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 405}
406
407static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
408 bool on)
409{
9ddf1aeb 410 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 411}
412static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 413 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 414{
415 if (azx_dev->wc_marked != on) {
9ddf1aeb 416 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 417 azx_dev->wc_marked = on;
418 }
419}
420#else
421/* NOP for other archs */
422static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
423 bool on)
424{
425}
426static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 427 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 428{
429}
430#endif
431
68e7fffc 432static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 433
cb53c626
TI		 434/*
435 * initialize the PCI registers
436 */
437/* update bits in a PCI register byte */
438static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
439 unsigned char mask, unsigned char val)
440{
441 unsigned char data;
442
443 pci_read_config_byte(pci, reg, &data);
444 data &= ~mask;
445 data |= (val & mask);
446 pci_write_config_byte(pci, reg, data);
447}
448
449static void azx_init_pci(struct azx *chip)
450{
37e661ee
TI		 451 int snoop_type = azx_get_snoop_type(chip);
452
cb53c626
TI		 453 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
454 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
455 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 456 * codecs.
457 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 458 */
46f2cc80 459 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 460 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 461 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 462 }
cb53c626 463
9477c58e
TI		 464 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
465 * we need to enable snoop.
466 */
37e661ee 467 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 468 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
469 azx_snoop(chip));
cb53c626 470 update_pci_byte(chip->pci,
27fe48d9
TI		 471 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
472 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 473 }
474
475 /* For NVIDIA HDA, enable snoop */
37e661ee 476 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 477 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
478 azx_snoop(chip));
cb53c626
TI		 479 update_pci_byte(chip->pci,
480 NVIDIA_HDA_TRANSREG_ADDR,
481 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 482 update_pci_byte(chip->pci,
483 NVIDIA_HDA_ISTRM_COH,
484 0x01, NVIDIA_HDA_ENABLE_COHBIT);
485 update_pci_byte(chip->pci,
486 NVIDIA_HDA_OSTRM_COH,
487 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 488 }
489
490 /* Enable SCH/PCH snoop if needed */
37e661ee 491 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 492 unsigned short snoop;
90a5ad52 493 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 494 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
495 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
496 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
497 if (!azx_snoop(chip))
498 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
499 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 500 pci_read_config_word(chip->pci,
501 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 502 }
4e76a883
TI		 503 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
504 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
505 "Disabled" : "Enabled");
da3fca21 506 }
1da177e4
LT		 507}
508
0a673521
LH		 509static void hda_intel_init_chip(struct azx *chip, bool full_reset)
510{
98d8fc6c 511 struct hdac_bus *bus = azx_bus(chip);
0a673521
LH		 512
513 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 514 snd_hdac_set_codec_wakeup(bus, true);
0a673521
LH		 515 azx_init_chip(chip, full_reset);
516 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 517 snd_hdac_set_codec_wakeup(bus, false);
0a673521
LH		 518}
519
b6050ef6
TI		 520/* calculate runtime delay from LPIB */
521static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
522 unsigned int pos)
523{
7833c3f8 524 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 525 int stream = substream->stream;
526 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
527 int delay;
528
529 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
530 delay = pos - lpib_pos;
531 else
532 delay = lpib_pos - pos;
533 if (delay < 0) {
7833c3f8 534 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 535 delay = 0;
536 else
7833c3f8 537 delay += azx_dev->core.bufsize;
b6050ef6
TI		 538 }
539
7833c3f8 540 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 541 dev_info(chip->card->dev,
542 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 543 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 544 delay = 0;
545 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
546 chip->get_delay[stream] = NULL;
547 }
548
549 return bytes_to_frames(substream->runtime, delay);
550}
551
9ad593f6
TI		 552static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
553
7ca954a8
DR		 554/* called from IRQ */
555static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
556{
9a34af4a 557 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 558 int ok;
559
560 ok = azx_position_ok(chip, azx_dev);
561 if (ok == 1) {
562 azx_dev->irq_pending = 0;
563 return ok;
2f35c630 564 } else if (ok == 0) {
7ca954a8
DR		 565 /* bogus IRQ, process it later */
566 azx_dev->irq_pending = 1;
2f35c630 567 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 568 }
569 return 0;
570}
571
17eccb27
ML		 572/* Enable/disable i915 display power for the link */
573static int azx_intel_link_power(struct azx *chip, bool enable)
574{
98d8fc6c 575 struct hdac_bus *bus = azx_bus(chip);
17eccb27 576
98d8fc6c 577 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 578}
579
9ad593f6
TI		 580/*
581 * Check whether the current DMA position is acceptable for updating
582 * periods. Returns non-zero if it's OK.
583 *
584 * Many HD-audio controllers appear pretty inaccurate about
585 * the update-IRQ timing. The IRQ is issued before actually the
586 * data is processed. So, we need to process it afterwords in a
587 * workqueue.
588 */
589static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
590{
7833c3f8 591 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 592 int stream = substream->stream;
e5463720 593 u32 wallclk;
9ad593f6
TI		 594 unsigned int pos;
595
7833c3f8
TI		 596 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
597 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 598 return -1; /* bogus (too early) interrupt */
fa00e046 599
b6050ef6
TI		 600 if (chip->get_position[stream])
601 pos = chip->get_position[stream](chip, azx_dev);
602 else { /* use the position buffer as default */
603 pos = azx_get_pos_posbuf(chip, azx_dev);
604 if (!pos || pos == (u32)-1) {
605 dev_info(chip->card->dev,
606 "Invalid position buffer, using LPIB read method instead.\n");
607 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 608 if (chip->get_position[0] == azx_get_pos_lpib &&
609 chip->get_position[1] == azx_get_pos_lpib)
610 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 611 pos = azx_get_pos_lpib(chip, azx_dev);
612 chip->get_delay[stream] = NULL;
613 } else {
614 chip->get_position[stream] = azx_get_pos_posbuf;
615 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
616 chip->get_delay[stream] = azx_get_delay_from_lpib;
617 }
618 }
619
7833c3f8 620 if (pos >= azx_dev->core.bufsize)
b6050ef6 621 pos = 0;
9ad593f6 622
7833c3f8 623 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 624 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 625 return -1; /* this shouldn't happen! */
7833c3f8
TI		 626 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
627 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 628 /* NG - it's below the first next period boundary */
9cdc0115 629 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
7833c3f8 630 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 631 return 1; /* OK, it's fine */
632}
633
634/*
635 * The work for pending PCM period updates.
636 */
637static void azx_irq_pending_work(struct work_struct *work)
638{
9a34af4a
TI		 639 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
640 struct azx *chip = &hda->chip;
7833c3f8
TI		 641 struct hdac_bus *bus = azx_bus(chip);
642 struct hdac_stream *s;
643 int pending, ok;
9ad593f6 644
9a34af4a 645 if (!hda->irq_pending_warned) {
4e76a883
TI		 646 dev_info(chip->card->dev,
647 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
648 chip->card->number);
9a34af4a 649 hda->irq_pending_warned = 1;
a6a950a8
TI		 650 }
651
9ad593f6
TI		 652 for (;;) {
653 pending = 0;
a41d1224 654 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 655 list_for_each_entry(s, &bus->stream_list, list) {
656 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 657 if (!azx_dev->irq_pending ||
7833c3f8
TI		 658 !s->substream ||
659 !s->running)
9ad593f6 660 continue;
e5463720
JK		 661 ok = azx_position_ok(chip, azx_dev);
662 if (ok > 0) {
9ad593f6 663 azx_dev->irq_pending = 0;
a41d1224 664 spin_unlock(&bus->reg_lock);
7833c3f8 665 snd_pcm_period_elapsed(s->substream);
a41d1224 666 spin_lock(&bus->reg_lock);
e5463720
JK		 667 } else if (ok < 0) {
668 pending = 0; /* too early */
9ad593f6
TI		 669 } else
670 pending++;
671 }
a41d1224 672 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 673 if (!pending)
674 return;
08af495f 675 msleep(1);
9ad593f6
TI		 676 }
677}
678
679/* clear irq_pending flags and assure no on-going workq */
680static void azx_clear_irq_pending(struct azx *chip)
681{
7833c3f8
TI		 682 struct hdac_bus *bus = azx_bus(chip);
683 struct hdac_stream *s;
9ad593f6 684
a41d1224 685 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 686 list_for_each_entry(s, &bus->stream_list, list) {
687 struct azx_dev *azx_dev = stream_to_azx_dev(s);
688 azx_dev->irq_pending = 0;
689 }
a41d1224 690 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 691}
692
68e7fffc
TI		 693static int azx_acquire_irq(struct azx *chip, int do_disconnect)
694{
a41d1224
TI		 695 struct hdac_bus *bus = azx_bus(chip);
696
437a5a46
TI		 697 if (request_irq(chip->pci->irq, azx_interrupt,
698 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 699 KBUILD_MODNAME, chip)) {
4e76a883
TI		 700 dev_err(chip->card->dev,
701 "unable to grab IRQ %d, disabling device\n",
702 chip->pci->irq);
68e7fffc
TI		 703 if (do_disconnect)
704 snd_card_disconnect(chip->card);
705 return -1;
706 }
a41d1224 707 bus->irq = chip->pci->irq;
69e13418 708 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 709 return 0;
710}
711
b6050ef6
TI		 712/* get the current DMA position with correction on VIA chips */
713static unsigned int azx_via_get_position(struct azx *chip,
714 struct azx_dev *azx_dev)
715{
716 unsigned int link_pos, mini_pos, bound_pos;
717 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
718 unsigned int fifo_size;
719
1604eeee 720 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 721 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 722 /* Playback, no problem using link position */
723 return link_pos;
724 }
725
726 /* Capture */
727 /* For new chipset,
728 * use mod to get the DMA position just like old chipset
729 */
7833c3f8
TI		 730 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
731 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 732
733 /* azx_dev->fifo_size can't get FIFO size of in stream.
734 * Get from base address + offset.
735 */
a41d1224
TI		 736 fifo_size = readw(azx_bus(chip)->remap_addr +
737 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 738
739 if (azx_dev->insufficient) {
740 /* Link position never gather than FIFO size */
741 if (link_pos <= fifo_size)
742 return 0;
743
744 azx_dev->insufficient = 0;
745 }
746
747 if (link_pos <= fifo_size)
7833c3f8 748 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 749 else
750 mini_pos = link_pos - fifo_size;
751
752 /* Find nearest previous boudary */
7833c3f8
TI		 753 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
754 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 755 if (mod_link_pos >= fifo_size)
756 bound_pos = link_pos - mod_link_pos;
757 else if (mod_dma_pos >= mod_mini_pos)
758 bound_pos = mini_pos - mod_mini_pos;
759 else {
7833c3f8
TI		 760 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
761 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 762 bound_pos = 0;
763 }
764
765 /* Calculate real DMA position we want */
766 return bound_pos + mod_dma_pos;
767}
768
83012a7c 769#ifdef CONFIG_PM
65fcd41d
TI		 770static DEFINE_MUTEX(card_list_lock);
771static LIST_HEAD(card_list);
772
773static void azx_add_card_list(struct azx *chip)
774{
9a34af4a 775 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 776 mutex_lock(&card_list_lock);
9a34af4a 777 list_add(&hda->list, &card_list);
65fcd41d
TI		 778 mutex_unlock(&card_list_lock);
779}
780
781static void azx_del_card_list(struct azx *chip)
782{
9a34af4a 783 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 784 mutex_lock(&card_list_lock);
9a34af4a 785 list_del_init(&hda->list);
65fcd41d
TI		 786 mutex_unlock(&card_list_lock);
787}
788
789/* trigger power-save check at writing parameter */
790static int param_set_xint(const char *val, const struct kernel_param *kp)
791{
9a34af4a 792 struct hda_intel *hda;
65fcd41d 793 struct azx *chip;
65fcd41d
TI		 794 int prev = power_save;
795 int ret = param_set_int(val, kp);
796
797 if (ret || prev == power_save)
798 return ret;
799
800 mutex_lock(&card_list_lock);
9a34af4a
TI		 801 list_for_each_entry(hda, &card_list, list) {
802 chip = &hda->chip;
a41d1224 803 if (!hda->probe_continued || chip->disabled)
65fcd41d 804 continue;
a41d1224 805 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 806 }
807 mutex_unlock(&card_list_lock);
808 return 0;
809}
810#else
811#define azx_add_card_list(chip) /* NOP */
812#define azx_del_card_list(chip) /* NOP */
83012a7c 813#endif /* CONFIG_PM */
5c0b9bec 814
98d8fc6c
ML		 815/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
816 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
817 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
818 * BCLK = CDCLK * M / N
819 * The values will be lost when the display power well is disabled and need to
820 * be restored to avoid abnormal playback speed.
821 */
822static void haswell_set_bclk(struct hda_intel *hda)
823{
824 struct azx *chip = &hda->chip;
825 int cdclk_freq;
826 unsigned int bclk_m, bclk_n;
827
828 if (!hda->need_i915_power)
829 return;
830
831 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
832 switch (cdclk_freq) {
833 case 337500:
834 bclk_m = 16;
835 bclk_n = 225;
836 break;
837
838 case 450000:
839 default: /* default CDCLK 450MHz */
840 bclk_m = 4;
841 bclk_n = 75;
842 break;
843
844 case 540000:
845 bclk_m = 4;
846 bclk_n = 90;
847 break;
848
849 case 675000:
850 bclk_m = 8;
851 bclk_n = 225;
852 break;
853 }
854
855 azx_writew(chip, HSW_EM4, bclk_m);
856 azx_writew(chip, HSW_EM5, bclk_n);
857}
858
7ccbde57 859#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 860/*
861 * power management
862 */
68cb2b55 863static int azx_suspend(struct device *dev)
1da177e4 864{
68cb2b55 865 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 866 struct azx *chip;
867 struct hda_intel *hda;
a41d1224 868 struct hdac_bus *bus;
1da177e4 869
2d9772ef
TI		 870 if (!card)
871 return 0;
872
873 chip = card->private_data;
874 hda = container_of(chip, struct hda_intel, chip);
342e8449 875 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 876 return 0;
877
a41d1224 878 bus = azx_bus(chip);
421a1252 879 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 880 azx_clear_irq_pending(chip);
cb53c626 881 azx_stop_chip(chip);
7295b264 882 azx_enter_link_reset(chip);
a41d1224
TI		 883 if (bus->irq >= 0) {
884 free_irq(bus->irq, chip);
885 bus->irq = -1;
30b35399 886 }
a07187c9 887
68e7fffc 888 if (chip->msi)
43001c95 889 pci_disable_msi(chip->pci);
795614dd
ML		 890 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
891 && hda->need_i915_power)
98d8fc6c 892 snd_hdac_display_power(bus, false);
785d8c4b
LY		 893
894 trace_azx_suspend(chip);
1da177e4
LT		 895 return 0;
896}
897
68cb2b55 898static int azx_resume(struct device *dev)
1da177e4 899{
68cb2b55
TI		 900 struct pci_dev *pci = to_pci_dev(dev);
901 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 902 struct azx *chip;
903 struct hda_intel *hda;
904
905 if (!card)
906 return 0;
1da177e4 907
2d9772ef
TI		 908 chip = card->private_data;
909 hda = container_of(chip, struct hda_intel, chip);
342e8449 910 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 911 return 0;
912
795614dd
ML		 913 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
914 && hda->need_i915_power) {
98d8fc6c 915 snd_hdac_display_power(azx_bus(chip), true);
926981ae 916 haswell_set_bclk(hda);
a07187c9 917 }
68e7fffc
TI		 918 if (chip->msi)
919 if (pci_enable_msi(pci) < 0)
920 chip->msi = 0;
921 if (azx_acquire_irq(chip, 1) < 0)
30b35399 922 return -EIO;
cb53c626 923 azx_init_pci(chip);
d804ad92 924
0a673521 925 hda_intel_init_chip(chip, true);
d804ad92 926
421a1252 927 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 928
929 trace_azx_resume(chip);
1da177e4
LT		 930 return 0;
931}
b8dfc462
ML		 932#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
933
641d334b 934#ifdef CONFIG_PM
b8dfc462
ML		 935static int azx_runtime_suspend(struct device *dev)
936{
937 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 938 struct azx *chip;
939 struct hda_intel *hda;
b8dfc462 940
2d9772ef
TI		 941 if (!card)
942 return 0;
943
944 chip = card->private_data;
945 hda = container_of(chip, struct hda_intel, chip);
1618e84a 946 if (chip->disabled || hda->init_failed)
246efa4a
DA		 947 return 0;
948
364aa716 949 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 950 return 0;
951
7d4f606c
WX		 952 /* enable controller wake up event */
953 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
954 STATESTS_INT_MASK);
955
b8dfc462 956 azx_stop_chip(chip);
873ce8ad 957 azx_enter_link_reset(chip);
b8dfc462 958 azx_clear_irq_pending(chip);
795614dd
ML		 959 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
960 && hda->need_i915_power)
98d8fc6c 961 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 962
785d8c4b 963 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 964 return 0;
965}
966
967static int azx_runtime_resume(struct device *dev)
968{
969 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 970 struct azx *chip;
971 struct hda_intel *hda;
98d8fc6c 972 struct hdac_bus *bus;
7d4f606c
WX		 973 struct hda_codec *codec;
974 int status;
b8dfc462 975
2d9772ef
TI		 976 if (!card)
977 return 0;
978
979 chip = card->private_data;
980 hda = container_of(chip, struct hda_intel, chip);
1618e84a 981 if (chip->disabled || hda->init_failed)
246efa4a
DA		 982 return 0;
983
364aa716 984 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 985 return 0;
986
033ea349
DH		 987 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
988 bus = azx_bus(chip);
989 if (hda->need_i915_power) {
990 snd_hdac_display_power(bus, true);
991 haswell_set_bclk(hda);
992 } else {
993 /* toggle codec wakeup bit for STATESTS read */
994 snd_hdac_set_codec_wakeup(bus, true);
995 snd_hdac_set_codec_wakeup(bus, false);
996 }
a07187c9 997 }
7d4f606c
WX		 998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
b8dfc462 1002 azx_init_pci(chip);
0a673521 1003 hda_intel_init_chip(chip, true);
7d4f606c 1004
a41d1224
TI		 1005 if (status) {
1006 list_for_each_codec(codec, &chip->bus)
7d4f606c 1007 if (status & (1 << codec->addr))
2f35c630
TI		 1008 schedule_delayed_work(&codec->jackpoll_work,
1009 codec->jackpoll_interval);
7d4f606c
WX		 1010 }
1011
1012 /* disable controller Wake Up event*/
1013 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1014 ~STATESTS_INT_MASK);
1015
785d8c4b 1016 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1017 return 0;
1018}
6eb827d2
TI		 1019
1020static int azx_runtime_idle(struct device *dev)
1021{
1022 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1023 struct azx *chip;
1024 struct hda_intel *hda;
1025
1026 if (!card)
1027 return 0;
6eb827d2 1028
2d9772ef
TI		 1029 chip = card->private_data;
1030 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1031 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1032 return 0;
1033
55ed9cd1 1034 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1035 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1036 return -EBUSY;
1037
1038 return 0;
1039}
1040
b8dfc462
ML		 1041static const struct dev_pm_ops azx_pm = {
1042 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1043 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1044};
1045
68cb2b55
TI		 1046#define AZX_PM_OPS &azx_pm
1047#else
68cb2b55 1048#define AZX_PM_OPS NULL
b8dfc462 1049#endif /* CONFIG_PM */
1da177e4
LT		 1050
1051
48c8b0eb 1052static int azx_probe_continue(struct azx *chip);
a82d51ed 1053
8393ec4a 1054#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1055static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1056
a82d51ed
TI		 1057static void azx_vs_set_state(struct pci_dev *pci,
1058 enum vga_switcheroo_state state)
1059{
1060 struct snd_card *card = pci_get_drvdata(pci);
1061 struct azx *chip = card->private_data;
9a34af4a 1062 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1063 bool disabled;
1064
9a34af4a
TI		 1065 wait_for_completion(&hda->probe_wait);
1066 if (hda->init_failed)
a82d51ed
TI		 1067 return;
1068
1069 disabled = (state == VGA_SWITCHEROO_OFF);
1070 if (chip->disabled == disabled)
1071 return;
1072
a41d1224 1073 if (!hda->probe_continued) {
a82d51ed
TI		 1074 chip->disabled = disabled;
1075 if (!disabled) {
4e76a883
TI		 1076 dev_info(chip->card->dev,
1077 "Start delayed initialization\n");
5c90680e 1078 if (azx_probe_continue(chip) < 0) {
4e76a883 1079 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1080 hda->init_failed = true;
a82d51ed
TI		 1081 }
1082 }
1083 } else {
4e76a883
TI		 1084 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1085 disabled ? "Disabling" : "Enabling");
a82d51ed 1086 if (disabled) {
8928756d
DR		 1087 pm_runtime_put_sync_suspend(card->dev);
1088 azx_suspend(card->dev);
246efa4a
DA		 1089 /* when we get suspended by vga switcheroo we end up in D3cold,
1090 * however we have no ACPI handle, so pci/acpi can't put us there,
1091 * put ourselves there */
1092 pci->current_state = PCI_D3cold;
a82d51ed 1093 chip->disabled = true;
a41d1224 1094 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1095 dev_warn(chip->card->dev,
1096 "Cannot lock devices!\n");
a82d51ed 1097 } else {
a41d1224 1098 snd_hda_unlock_devices(&chip->bus);
8928756d 1099 pm_runtime_get_noresume(card->dev);
a82d51ed 1100 chip->disabled = false;
8928756d 1101 azx_resume(card->dev);
a82d51ed
TI		 1102 }
1103 }
1104}
1105
1106static bool azx_vs_can_switch(struct pci_dev *pci)
1107{
1108 struct snd_card *card = pci_get_drvdata(pci);
1109 struct azx *chip = card->private_data;
9a34af4a 1110 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1111
9a34af4a
TI		 1112 wait_for_completion(&hda->probe_wait);
1113 if (hda->init_failed)
a82d51ed 1114 return false;
a41d1224 1115 if (chip->disabled || !hda->probe_continued)
a82d51ed 1116 return true;
a41d1224 1117 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1118 return false;
a41d1224 1119 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1120 return true;
1121}
1122
e23e7a14 1123static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1124{
9a34af4a 1125 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1126 struct pci_dev *p = get_bound_vga(chip->pci);
1127 if (p) {
4e76a883
TI		 1128 dev_info(chip->card->dev,
1129 "Handle VGA-switcheroo audio client\n");
9a34af4a 1130 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1131 pci_dev_put(p);
1132 }
1133}
1134
1135static const struct vga_switcheroo_client_ops azx_vs_ops = {
1136 .set_gpu_state = azx_vs_set_state,
1137 .can_switch = azx_vs_can_switch,
1138};
1139
e23e7a14 1140static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1141{
9a34af4a 1142 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1143 int err;
1144
9a34af4a 1145 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1146 return 0;
1147 /* FIXME: currently only handling DIS controller
1148 * is there any machine with two switchable HDMI audio controllers?
1149 */
128960a9 1150 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed 1151 VGA_SWITCHEROO_DIS,
a41d1224 1152 hda->probe_continued);
128960a9
TI		 1153 if (err < 0)
1154 return err;
9a34af4a 1155 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1156
1157 /* register as an optimus hdmi audio power domain */
8928756d 1158 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1159 &hda->hdmi_pm_domain);
128960a9 1160 return 0;
a82d51ed
TI		 1161}
1162#else
1163#define init_vga_switcheroo(chip) /* NOP */
1164#define register_vga_switcheroo(chip) 0
8393ec4a 1165#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1166#endif /* SUPPORT_VGA_SWITCHER */
1167
1da177e4
LT		 1168/*
1169 * destructor
1170 */
a98f90fd 1171static int azx_free(struct azx *chip)
1da177e4 1172{
c67e2228 1173 struct pci_dev *pci = chip->pci;
a07187c9 1174 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1175 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1176
364aa716 1177 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1178 pm_runtime_get_noresume(&pci->dev);
1179
65fcd41d
TI		 1180 azx_del_card_list(chip);
1181
9a34af4a
TI		 1182 hda->init_failed = 1; /* to be sure */
1183 complete_all(&hda->probe_wait);
f4c482a4 1184
9a34af4a 1185 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1186 if (chip->disabled && hda->probe_continued)
1187 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1188 if (hda->vga_switcheroo_registered)
128960a9 1189 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1190 }
1191
a41d1224 1192 if (bus->chip_init) {
9ad593f6 1193 azx_clear_irq_pending(chip);
7833c3f8 1194 azx_stop_all_streams(chip);
cb53c626 1195 azx_stop_chip(chip);
1da177e4
LT		 1196 }
1197
a41d1224
TI		 1198 if (bus->irq >= 0)
1199 free_irq(bus->irq, (void*)chip);
68e7fffc 1200 if (chip->msi)
30b35399 1201 pci_disable_msi(chip->pci);
a41d1224 1202 iounmap(bus->remap_addr);
1da177e4 1203
67908994 1204 azx_free_stream_pages(chip);
a41d1224
TI		 1205 azx_free_streams(chip);
1206 snd_hdac_bus_exit(bus);
1207
a82d51ed
TI		 1208 if (chip->region_requested)
1209 pci_release_regions(chip->pci);
a41d1224 1210
1da177e4 1211 pci_disable_device(chip->pci);
4918cdab 1212#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1213 release_firmware(chip->fw);
4918cdab 1214#endif
98d8fc6c 1215
99a2008d 1216 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1217 if (hda->need_i915_power)
98d8fc6c
ML		 1218 snd_hdac_display_power(bus, false);
1219 snd_hdac_i915_exit(bus);
99a2008d 1220 }
a07187c9 1221 kfree(hda);
1da177e4
LT		 1222
1223 return 0;
1224}
1225
a41d1224
TI		 1226static int azx_dev_disconnect(struct snd_device *device)
1227{
1228 struct azx *chip = device->device_data;
1229
1230 chip->bus.shutdown = 1;
1231 return 0;
1232}
1233
a98f90fd 1234static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1235{
1236 return azx_free(device->device_data);
1237}
1238
8393ec4a 1239#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1240/*
1241 * Check of disabled HDMI controller by vga-switcheroo
1242 */
e23e7a14 1243static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1244{
1245 struct pci_dev *p;
1246
1247 /* check only discrete GPU */
1248 switch (pci->vendor) {
1249 case PCI_VENDOR_ID_ATI:
1250 case PCI_VENDOR_ID_AMD:
1251 case PCI_VENDOR_ID_NVIDIA:
1252 if (pci->devfn == 1) {
1253 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1254 pci->bus->number, 0);
1255 if (p) {
1256 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1257 return p;
1258 pci_dev_put(p);
1259 }
1260 }
1261 break;
1262 }
1263 return NULL;
1264}
1265
e23e7a14 1266static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1267{
1268 bool vga_inactive = false;
1269 struct pci_dev *p = get_bound_vga(pci);
1270
1271 if (p) {
12b78a7f 1272 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1273 vga_inactive = true;
1274 pci_dev_put(p);
1275 }
1276 return vga_inactive;
1277}
8393ec4a 1278#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1279
3372a153
TI		 1280/*
1281 * white/black-listing for position_fix
1282 */
e23e7a14 1283static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1284 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1285 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1286 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1287 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1288 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1289 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1290 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1291 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1292 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1293 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1294 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1295 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1296 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1297 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1298 {}
1299};
1300
e23e7a14 1301static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1302{
1303 const struct snd_pci_quirk *q;
1304
c673ba1c 1305 switch (fix) {
1dac6695 1306 case POS_FIX_AUTO:
c673ba1c
TI		 1307 case POS_FIX_LPIB:
1308 case POS_FIX_POSBUF:
4cb36310 1309 case POS_FIX_VIACOMBO:
a6f2fd55 1310 case POS_FIX_COMBO:
c673ba1c
TI		 1311 return fix;
1312 }
1313
c673ba1c
TI		 1314 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1315 if (q) {
4e76a883
TI		 1316 dev_info(chip->card->dev,
1317 "position_fix set to %d for device %04x:%04x\n",
1318 q->value, q->subvendor, q->subdevice);
c673ba1c 1319 return q->value;
3372a153 1320 }
bdd9ef24
DH		 1321
1322 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1323 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1324 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1325 return POS_FIX_VIACOMBO;
9477c58e
TI		 1326 }
1327 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1328 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1329 return POS_FIX_LPIB;
bdd9ef24 1330 }
c673ba1c 1331 return POS_FIX_AUTO;
3372a153
TI		 1332}
1333
b6050ef6
TI		 1334static void assign_position_fix(struct azx *chip, int fix)
1335{
1336 static azx_get_pos_callback_t callbacks[] = {
1337 [POS_FIX_AUTO] = NULL,
1338 [POS_FIX_LPIB] = azx_get_pos_lpib,
1339 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1340 [POS_FIX_VIACOMBO] = azx_via_get_position,
1341 [POS_FIX_COMBO] = azx_get_pos_lpib,
1342 };
1343
1344 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1345
1346 /* combo mode uses LPIB only for playback */
1347 if (fix == POS_FIX_COMBO)
1348 chip->get_position[1] = NULL;
1349
1350 if (fix == POS_FIX_POSBUF &&
1351 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1352 chip->get_delay[0] = chip->get_delay[1] =
1353 azx_get_delay_from_lpib;
1354 }
1355
1356}
1357
669ba27a
TI		 1358/*
1359 * black-lists for probe_mask
1360 */
e23e7a14 1361static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1362 /* Thinkpad often breaks the controller communication when accessing
1363 * to the non-working (or non-existing) modem codec slot.
1364 */
1365 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1366 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1367 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1368 /* broken BIOS */
1369 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1370 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1371 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1372 /* forced codec slots */
93574844 1373 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1374 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1375 /* WinFast VP200 H (Teradici) user reported broken communication */
1376 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1377 {}
1378};
1379
f1eaaeec
TI		 1380#define AZX_FORCE_CODEC_MASK 0x100
1381
e23e7a14 1382static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1383{
1384 const struct snd_pci_quirk *q;
1385
f1eaaeec
TI		 1386 chip->codec_probe_mask = probe_mask[dev];
1387 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1388 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1389 if (q) {
4e76a883
TI		 1390 dev_info(chip->card->dev,
1391 "probe_mask set to 0x%x for device %04x:%04x\n",
1392 q->value, q->subvendor, q->subdevice);
f1eaaeec 1393 chip->codec_probe_mask = q->value;
669ba27a
TI		 1394 }
1395 }
f1eaaeec
TI		 1396
1397 /* check forced option */
1398 if (chip->codec_probe_mask != -1 &&
1399 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1400 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1401 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1402 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1403 }
669ba27a
TI		 1404}
1405
4d8e22e0 1406/*
71623855 1407 * white/black-list for enable_msi
4d8e22e0 1408 */
e23e7a14 1409static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1410 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1411 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1412 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1413 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1414 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1415 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1416 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1417 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1418 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1419 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1420 {}
1421};
1422
e23e7a14 1423static void check_msi(struct azx *chip)
4d8e22e0
TI		 1424{
1425 const struct snd_pci_quirk *q;
1426
71623855
TI		 1427 if (enable_msi >= 0) {
1428 chip->msi = !!enable_msi;
4d8e22e0 1429 return;
71623855
TI		 1430 }
1431 chip->msi = 1; /* enable MSI as default */
1432 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1433 if (q) {
4e76a883
TI		 1434 dev_info(chip->card->dev,
1435 "msi for device %04x:%04x set to %d\n",
1436 q->subvendor, q->subdevice, q->value);
4d8e22e0 1437 chip->msi = q->value;
80c43ed7
TI		 1438 return;
1439 }
1440
1441 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1442 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1443 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1444 chip->msi = 0;
4d8e22e0
TI		 1445 }
1446}
1447
a1585d76 1448/* check the snoop mode availability */
e23e7a14 1449static void azx_check_snoop_available(struct azx *chip)
a1585d76 1450{
7c732015 1451 int snoop = hda_snoop;
a1585d76 1452
7c732015
TI		 1453 if (snoop >= 0) {
1454 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1455 snoop ? "snoop" : "non-snoop");
1456 chip->snoop = snoop;
1457 return;
1458 }
1459
1460 snoop = true;
37e661ee
TI		 1461 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1462 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1463 /* force to non-snoop mode for a new VIA controller
1464 * when BIOS is set
1465 */
7c732015
TI		 1466 u8 val;
1467 pci_read_config_byte(chip->pci, 0x42, &val);
1468 if (!(val & 0x80) && chip->pci->revision == 0x30)
1469 snoop = false;
a1585d76
TI		 1470 }
1471
37e661ee
TI		 1472 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1473 snoop = false;
1474
7c732015
TI		 1475 chip->snoop = snoop;
1476 if (!snoop)
1477 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1478}
669ba27a 1479
99a2008d
WX		 1480static void azx_probe_work(struct work_struct *work)
1481{
9a34af4a
TI		 1482 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1483 azx_probe_continue(&hda->chip);
99a2008d 1484}
99a2008d 1485
1da177e4
LT		 1486/*
1487 * constructor
1488 */
a43ff5ba
TI		 1489static const struct hdac_io_ops pci_hda_io_ops;
1490static const struct hda_controller_ops pci_hda_ops;
1491
e23e7a14
BP		 1492static int azx_create(struct snd_card *card, struct pci_dev *pci,
1493 int dev, unsigned int driver_caps,
1494 struct azx **rchip)
1da177e4 1495{
a98f90fd 1496 static struct snd_device_ops ops = {
a41d1224 1497 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1498 .dev_free = azx_dev_free,
1499 };
a07187c9 1500 struct hda_intel *hda;
a82d51ed
TI		 1501 struct azx *chip;
1502 int err;
1da177e4
LT		 1503
1504 *rchip = NULL;
bcd72003 1505
927fc866
PM		 1506 err = pci_enable_device(pci);
1507 if (err < 0)
1da177e4
LT		 1508 return err;
1509
a07187c9
ML		 1510 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1511 if (!hda) {
1da177e4
LT		 1512 pci_disable_device(pci);
1513 return -ENOMEM;
1514 }
1515
a07187c9 1516 chip = &hda->chip;
62932df8 1517 mutex_init(&chip->open_mutex);
1da177e4
LT		 1518 chip->card = card;
1519 chip->pci = pci;
a43ff5ba 1520 chip->ops = &pci_hda_ops;
9477c58e
TI		 1521 chip->driver_caps = driver_caps;
1522 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1523 check_msi(chip);
555e219f 1524 chip->dev_index = dev;
749ee287 1525 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1526 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1527 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1528 INIT_LIST_HEAD(&hda->list);
a82d51ed 1529 init_vga_switcheroo(chip);
9a34af4a 1530 init_completion(&hda->probe_wait);
1da177e4 1531
b6050ef6 1532 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1533
5aba4f8e 1534 check_probe_mask(chip, dev);
3372a153 1535
27346166 1536 chip->single_cmd = single_cmd;
a1585d76 1537 azx_check_snoop_available(chip);
c74db86b 1538
5c0d7bc1
TI		 1539 if (bdl_pos_adj[dev] < 0) {
1540 switch (chip->driver_type) {
0c6341ac 1541 case AZX_DRIVER_ICH:
32679f95 1542 case AZX_DRIVER_PCH:
0c6341ac 1543 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1544 break;
1545 default:
0c6341ac 1546 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1547 break;
1548 }
1549 }
9cdc0115 1550 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1551
a41d1224
TI		 1552 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1553 if (err < 0) {
1554 kfree(hda);
1555 pci_disable_device(pci);
1556 return err;
1557 }
1558
a82d51ed
TI		 1559 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1560 if (err < 0) {
4e76a883 1561 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1562 azx_free(chip);
1563 return err;
1564 }
1565
99a2008d 1566 /* continue probing in work context as may trigger request module */
9a34af4a 1567 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1568
a82d51ed 1569 *rchip = chip;
99a2008d 1570
a82d51ed
TI		 1571 return 0;
1572}
1573
48c8b0eb 1574static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1575{
1576 int dev = chip->dev_index;
1577 struct pci_dev *pci = chip->pci;
1578 struct snd_card *card = chip->card;
a41d1224 1579 struct hdac_bus *bus = azx_bus(chip);
67908994 1580 int err;
a82d51ed 1581 unsigned short gcap;
413cbf46 1582 unsigned int dma_bits = 64;
a82d51ed 1583
07e4ca50
TI		 1584#if BITS_PER_LONG != 64
1585 /* Fix up base address on ULI M5461 */
1586 if (chip->driver_type == AZX_DRIVER_ULI) {
1587 u16 tmp3;
1588 pci_read_config_word(pci, 0x40, &tmp3);
1589 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1590 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1591 }
1592#endif
1593
927fc866 1594 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1595 if (err < 0)
1da177e4 1596 return err;
a82d51ed 1597 chip->region_requested = 1;
1da177e4 1598
a41d1224
TI		 1599 bus->addr = pci_resource_start(pci, 0);
1600 bus->remap_addr = pci_ioremap_bar(pci, 0);
1601 if (bus->remap_addr == NULL) {
4e76a883 1602 dev_err(card->dev, "ioremap error\n");
a82d51ed 1603 return -ENXIO;
1da177e4
LT		 1604 }
1605
db79afa1
BH		 1606 if (chip->msi) {
1607 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1608 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1609 pci->no_64bit_msi = true;
1610 }
68e7fffc
TI		 1611 if (pci_enable_msi(pci) < 0)
1612 chip->msi = 0;
db79afa1 1613 }
7376d013 1614
a82d51ed
TI		 1615 if (azx_acquire_irq(chip, 0) < 0)
1616 return -EBUSY;
1da177e4
LT		 1617
1618 pci_set_master(pci);
a41d1224 1619 synchronize_irq(bus->irq);
1da177e4 1620
bcd72003 1621 gcap = azx_readw(chip, GCAP);
4e76a883 1622 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1623
413cbf46
TI		 1624 /* AMD devices support 40 or 48bit DMA, take the safe one */
1625 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1626 dma_bits = 40;
1627
dc4c2e6b 1628 /* disable SB600 64bit support for safety */
9477c58e 1629 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1630 struct pci_dev *p_smbus;
413cbf46 1631 dma_bits = 40;
dc4c2e6b
AB		 1632 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1633 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1634 NULL);
1635 if (p_smbus) {
1636 if (p_smbus->revision < 0x30)
fb1d8ac2 1637 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1638 pci_dev_put(p_smbus);
1639 }
1640 }
09240cf4 1641
9477c58e
TI		 1642 /* disable 64bit DMA address on some devices */
1643 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1644 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1645 gcap &= ~AZX_GCAP_64OK;
9477c58e 1646 }
396087ea 1647
2ae66c26 1648 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1649 if (align_buffer_size >= 0)
1650 chip->align_buffer_size = !!align_buffer_size;
1651 else {
103884a3 1652 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1653 chip->align_buffer_size = 0;
7bfe059e
TI		 1654 else
1655 chip->align_buffer_size = 1;
1656 }
2ae66c26 1657
cf7aaca8 1658 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1659 if (!(gcap & AZX_GCAP_64OK))
1660 dma_bits = 32;
412b979c
QL		 1661 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1662 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1663 } else {
412b979c
QL		 1664 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1665 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1666 }
cf7aaca8 1667
8b6ed8e7
TI		 1668 /* read number of streams from GCAP register instead of using
1669 * hardcoded value
1670 */
1671 chip->capture_streams = (gcap >> 8) & 0x0f;
1672 chip->playback_streams = (gcap >> 12) & 0x0f;
1673 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1674 /* gcap didn't give any info, switching to old method */
1675
1676 switch (chip->driver_type) {
1677 case AZX_DRIVER_ULI:
1678 chip->playback_streams = ULI_NUM_PLAYBACK;
1679 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1680 break;
1681 case AZX_DRIVER_ATIHDMI:
1815b34a 1682 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1683 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1684 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1685 break;
c4da29ca 1686 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1687 default:
1688 chip->playback_streams = ICH6_NUM_PLAYBACK;
1689 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1690 break;
1691 }
07e4ca50 1692 }
8b6ed8e7
TI		 1693 chip->capture_index_offset = 0;
1694 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1695 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1696
a41d1224
TI		 1697 /* initialize streams */
1698 err = azx_init_streams(chip);
81740861 1699 if (err < 0)
a82d51ed 1700 return err;
1da177e4 1701
a41d1224
TI		 1702 err = azx_alloc_stream_pages(chip);
1703 if (err < 0)
1704 return err;
1da177e4
LT		 1705
1706 /* initialize chip */
cb53c626 1707 azx_init_pci(chip);
e4d9e513 1708
926981ae
ID		 1709 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1710 struct hda_intel *hda;
1711
1712 hda = container_of(chip, struct hda_intel, chip);
1713 haswell_set_bclk(hda);
1714 }
e4d9e513 1715
0a673521 1716 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1717
1718 /* codec detection */
a41d1224 1719 if (!azx_bus(chip)->codec_mask) {
4e76a883 1720 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1721 return -ENODEV;
1da177e4
LT		 1722 }
1723
07e4ca50 1724 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1725 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1726 sizeof(card->shortname));
1727 snprintf(card->longname, sizeof(card->longname),
1728 "%s at 0x%lx irq %i",
a41d1224 1729 card->shortname, bus->addr, bus->irq);
07e4ca50 1730
1da177e4 1731 return 0;
1da177e4
LT		 1732}
1733
97c6a3d1 1734#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1735/* callback from request_firmware_nowait() */
1736static void azx_firmware_cb(const struct firmware *fw, void *context)
1737{
1738 struct snd_card *card = context;
1739 struct azx *chip = card->private_data;
1740 struct pci_dev *pci = chip->pci;
1741
1742 if (!fw) {
4e76a883 1743 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1744 goto error;
1745 }
1746
1747 chip->fw = fw;
1748 if (!chip->disabled) {
1749 /* continue probing */
1750 if (azx_probe_continue(chip))
1751 goto error;
1752 }
1753 return; /* OK */
1754
1755 error:
1756 snd_card_free(card);
1757 pci_set_drvdata(pci, NULL);
1758}
97c6a3d1 1759#endif
5cb543db 1760
40830813
DR		 1761/*
1762 * HDA controller ops.
1763 */
1764
1765/* PCI register access. */
db291e36 1766static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1767{
1768 writel(value, addr);
1769}
1770
db291e36 1771static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1772{
1773 return readl(addr);
1774}
1775
db291e36 1776static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1777{
1778 writew(value, addr);
1779}
1780
db291e36 1781static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1782{
1783 return readw(addr);
1784}
1785
db291e36 1786static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1787{
1788 writeb(value, addr);
1789}
1790
db291e36 1791static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1792{
1793 return readb(addr);
1794}
1795
f46ea609
DR		 1796static int disable_msi_reset_irq(struct azx *chip)
1797{
a41d1224 1798 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1799 int err;
1800
a41d1224
TI		 1801 free_irq(bus->irq, chip);
1802 bus->irq = -1;
f46ea609
DR		 1803 pci_disable_msi(chip->pci);
1804 chip->msi = 0;
1805 err = azx_acquire_irq(chip, 1);
1806 if (err < 0)
1807 return err;
1808
1809 return 0;
1810}
1811
b419b35b 1812/* DMA page allocation helpers. */
a43ff5ba 1813static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1814 int type,
1815 size_t size,
1816 struct snd_dma_buffer *buf)
1817{
a41d1224 1818 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1819 int err;
1820
1821 err = snd_dma_alloc_pages(type,
a43ff5ba 1822 bus->dev,
b419b35b
DR		 1823 size, buf);
1824 if (err < 0)
1825 return err;
1826 mark_pages_wc(chip, buf, true);
1827 return 0;
1828}
1829
a43ff5ba 1830static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1831{
a41d1224 1832 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1833
b419b35b
DR		 1834 mark_pages_wc(chip, buf, false);
1835 snd_dma_free_pages(buf);
1836}
1837
1838static int substream_alloc_pages(struct azx *chip,
1839 struct snd_pcm_substream *substream,
1840 size_t size)
1841{
1842 struct azx_dev *azx_dev = get_azx_dev(substream);
1843 int ret;
1844
1845 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1846 ret = snd_pcm_lib_malloc_pages(substream, size);
1847 if (ret < 0)
1848 return ret;
1849 mark_runtime_wc(chip, azx_dev, substream, true);
1850 return 0;
1851}
1852
1853static int substream_free_pages(struct azx *chip,
1854 struct snd_pcm_substream *substream)
1855{
1856 struct azx_dev *azx_dev = get_azx_dev(substream);
1857 mark_runtime_wc(chip, azx_dev, substream, false);
1858 return snd_pcm_lib_free_pages(substream);
1859}
1860
8769b278
DR		 1861static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1862 struct vm_area_struct *area)
1863{
1864#ifdef CONFIG_X86
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1866 struct azx *chip = apcm->chip;
3b70bdba 1867 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1868 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1869#endif
1870}
1871
a43ff5ba 1872static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1873 .reg_writel = pci_azx_writel,
1874 .reg_readl = pci_azx_readl,
1875 .reg_writew = pci_azx_writew,
1876 .reg_readw = pci_azx_readw,
1877 .reg_writeb = pci_azx_writeb,
1878 .reg_readb = pci_azx_readb,
b419b35b
DR		 1879 .dma_alloc_pages = dma_alloc_pages,
1880 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1881};
1882
1883static const struct hda_controller_ops pci_hda_ops = {
1884 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1885 .substream_alloc_pages = substream_alloc_pages,
1886 .substream_free_pages = substream_free_pages,
8769b278 1887 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1888 .position_check = azx_position_check,
17eccb27 1889 .link_power = azx_intel_link_power,
40830813
DR		 1890};
1891
e23e7a14
BP		 1892static int azx_probe(struct pci_dev *pci,
1893 const struct pci_device_id *pci_id)
1da177e4 1894{
5aba4f8e 1895 static int dev;
a98f90fd 1896 struct snd_card *card;
9a34af4a 1897 struct hda_intel *hda;
a98f90fd 1898 struct azx *chip;
aad730d0 1899 bool schedule_probe;
927fc866 1900 int err;
1da177e4 1901
5aba4f8e
TI		 1902 if (dev >= SNDRV_CARDS)
1903 return -ENODEV;
1904 if (!enable[dev]) {
1905 dev++;
1906 return -ENOENT;
1907 }
1908
60c5772b
TI		 1909 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1910 0, &card);
e58de7ba 1911 if (err < 0) {
4e76a883 1912 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1913 return err;
1da177e4
LT		 1914 }
1915
a43ff5ba 1916 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1917 if (err < 0)
1918 goto out_free;
421a1252 1919 card->private_data = chip;
9a34af4a 1920 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1921
1922 pci_set_drvdata(pci, card);
1923
1924 err = register_vga_switcheroo(chip);
1925 if (err < 0) {
4e76a883 1926 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1927 goto out_free;
1928 }
1929
1930 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1931 dev_info(card->dev, "VGA controller is disabled\n");
1932 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1933 chip->disabled = true;
1934 }
1935
aad730d0 1936 schedule_probe = !chip->disabled;
1da177e4 1937
4918cdab
TI		 1938#ifdef CONFIG_SND_HDA_PATCH_LOADER
1939 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1940 dev_info(card->dev, "Applying patch firmware '%s'\n",
1941 patch[dev]);
5cb543db
TI		 1942 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1943 &pci->dev, GFP_KERNEL, card,
1944 azx_firmware_cb);
4918cdab
TI		 1945 if (err < 0)
1946 goto out_free;
aad730d0 1947 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1948 }
1949#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1950
aad730d0
TI		 1951#ifndef CONFIG_SND_HDA_I915
1952 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1953 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1954#endif
99a2008d 1955
aad730d0 1956 if (schedule_probe)
9a34af4a 1957 schedule_work(&hda->probe_work);
a82d51ed 1958
a82d51ed 1959 dev++;
88d071fc 1960 if (chip->disabled)
9a34af4a 1961 complete_all(&hda->probe_wait);
a82d51ed
TI		 1962 return 0;
1963
1964out_free:
1965 snd_card_free(card);
1966 return err;
1967}
1968
e62a42ae
DR		 1969/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1970static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1971 [AZX_DRIVER_NVIDIA] = 8,
1972 [AZX_DRIVER_TERA] = 1,
1973};
1974
48c8b0eb 1975static int azx_probe_continue(struct azx *chip)
a82d51ed 1976{
9a34af4a 1977 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 1978 struct hdac_bus *bus = azx_bus(chip);
c67e2228 1979 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1980 int dev = chip->dev_index;
1981 int err;
1982
a41d1224 1983 hda->probe_continued = 1;
795614dd
ML		 1984
1985 /* Request display power well for the HDA controller or codec. For
1986 * Haswell/Broadwell, both the display HDA controller and codec need
1987 * this power. For other platforms, like Baytrail/Braswell, only the
1988 * display codec needs the power and it can be released after probe.
1989 */
99a2008d 1990 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 1991 /* HSW/BDW controllers need this power */
1992 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 1993 hda->need_i915_power = 1;
1994
98d8fc6c 1995 err = snd_hdac_i915_init(bus);
535115b5
TI		 1996 if (err < 0) {
1997 /* if the controller is bound only with HDMI/DP
1998 * (for HSW and BDW), we need to abort the probe;
1999 * for other chips, still continue probing as other
2000 * codecs can be on the same link.
2001 */
2002 if (CONTROLLER_IN_GPU(pci))
2003 goto out_free;
2004 else
2005 goto skip_i915;
2006 }
795614dd 2007
98d8fc6c 2008 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2009 if (err < 0) {
2010 dev_err(chip->card->dev,
2011 "Cannot turn on display power on i915\n");
795614dd 2012 goto i915_power_fail;
74b0c2d7 2013 }
99a2008d
WX		 2014 }
2015
bf06848b 2016 skip_i915:
5c90680e
TI		 2017 err = azx_first_init(chip);
2018 if (err < 0)
2019 goto out_free;
2020
2dca0bba
JK		 2021#ifdef CONFIG_SND_HDA_INPUT_BEEP
2022 chip->beep_mode = beep_mode[dev];
2023#endif
2024
1da177e4 2025 /* create codec instances */
96d2bd6e 2026 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2027 if (err < 0)
2028 goto out_free;
96d2bd6e 2029
4ea6fbc8 2030#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2031 if (chip->fw) {
a41d1224 2032 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2033 chip->fw->data);
4ea6fbc8
TI		 2034 if (err < 0)
2035 goto out_free;
e39ae856 2036#ifndef CONFIG_PM
4918cdab
TI		 2037 release_firmware(chip->fw); /* no longer needed */
2038 chip->fw = NULL;
e39ae856 2039#endif
4ea6fbc8
TI		 2040 }
2041#endif
10e77dda 2042 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2043 err = azx_codec_configure(chip);
2044 if (err < 0)
2045 goto out_free;
2046 }
1da177e4 2047
a82d51ed 2048 err = snd_card_register(chip->card);
41dda0fd
WF		 2049 if (err < 0)
2050 goto out_free;
1da177e4 2051
cb53c626 2052 chip->running = 1;
65fcd41d 2053 azx_add_card_list(chip);
a41d1224 2054 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2055 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 2056 pm_runtime_put_noidle(&pci->dev);
1da177e4 2057
41dda0fd 2058out_free:
795614dd
ML		 2059 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2060 && !hda->need_i915_power)
98d8fc6c 2061 snd_hdac_display_power(bus, false);
795614dd
ML		 2062
2063i915_power_fail:
88d071fc 2064 if (err < 0)
9a34af4a
TI		 2065 hda->init_failed = 1;
2066 complete_all(&hda->probe_wait);
41dda0fd 2067 return err;
1da177e4
LT		 2068}
2069
e23e7a14 2070static void azx_remove(struct pci_dev *pci)
1da177e4 2071{
9121947d 2072 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 2073
9121947d
TI		 2074 if (card)
2075 snd_card_free(card);
1da177e4
LT		 2076}
2077
b2a0bafa
TI		 2078static void azx_shutdown(struct pci_dev *pci)
2079{
2080 struct snd_card *card = pci_get_drvdata(pci);
2081 struct azx *chip;
2082
2083 if (!card)
2084 return;
2085 chip = card->private_data;
2086 if (chip && chip->running)
2087 azx_stop_chip(chip);
2088}
2089
1da177e4 2090/* PCI IDs */
6f51f6cf 2091static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2092 /* CPT */
9477c58e 2093 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2094 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2095 /* PBG */
9477c58e 2096 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2097 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2098 /* Panther Point */
9477c58e 2099 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2100 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2101 /* Lynx Point */
2102 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2103 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2104 /* 9 Series */
2105 { PCI_DEVICE(0x8086, 0x8ca0),
2106 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2107 /* Wellsburg */
2108 { PCI_DEVICE(0x8086, 0x8d20),
2109 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2110 { PCI_DEVICE(0x8086, 0x8d21),
2111 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2112 /* Lewisburg */
2113 { PCI_DEVICE(0x8086, 0xa1f0),
2114 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2115 { PCI_DEVICE(0x8086, 0xa270),
2116 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2117 /* Lynx Point-LP */
2118 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2119 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2120 /* Lynx Point-LP */
2121 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2122 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2123 /* Wildcat Point-LP */
2124 { PCI_DEVICE(0x8086, 0x9ca0),
2125 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2126 /* Sunrise Point */
2127 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2128 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2129 /* Sunrise Point-LP */
2130 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2131 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2132 /* Broxton-P(Apollolake) */
2133 { PCI_DEVICE(0x8086, 0x5a98),
2134 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2135 /* Haswell */
4a7c516b 2136 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2137 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2138 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2139 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2140 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2141 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2142 /* Broadwell */
2143 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2144 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2145 /* 5 Series/3400 */
2146 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2147 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2148 /* Poulsbo */
9477c58e 2149 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2150 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2151 /* Oaktrail */
09904b95 2152 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2153 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2154 /* BayTrail */
2155 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2156 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2157 /* Braswell */
2158 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2159 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2160 /* ICH6 */
8b0bd226 2161 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2162 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2163 /* ICH7 */
8b0bd226 2164 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2165 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2166 /* ESB2 */
8b0bd226 2167 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2168 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2169 /* ICH8 */
8b0bd226 2170 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2171 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2172 /* ICH9 */
8b0bd226 2173 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2174 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2175 /* ICH9 */
8b0bd226 2176 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2177 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2178 /* ICH10 */
8b0bd226 2179 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2180 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2181 /* ICH10 */
8b0bd226 2182 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2183 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2184 /* Generic Intel */
2185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2186 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2187 .class_mask = 0xffffff,
103884a3 2188 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2189 /* ATI SB 450/600/700/800/900 */
2190 { PCI_DEVICE(0x1002, 0x437b),
2191 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2192 { PCI_DEVICE(0x1002, 0x4383),
2193 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2194 /* AMD Hudson */
2195 { PCI_DEVICE(0x1022, 0x780d),
2196 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2197 /* ATI HDMI */
650474fb
AD		 2198 { PCI_DEVICE(0x1002, 0x1308),
2199 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2200 { PCI_DEVICE(0x1002, 0x157a),
2201 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2202 { PCI_DEVICE(0x1002, 0x793b),
2203 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2204 { PCI_DEVICE(0x1002, 0x7919),
2205 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2206 { PCI_DEVICE(0x1002, 0x960f),
2207 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2208 { PCI_DEVICE(0x1002, 0x970f),
2209 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2210 { PCI_DEVICE(0x1002, 0x9840),
2211 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2212 { PCI_DEVICE(0x1002, 0xaa00),
2213 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2214 { PCI_DEVICE(0x1002, 0xaa08),
2215 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2216 { PCI_DEVICE(0x1002, 0xaa10),
2217 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2218 { PCI_DEVICE(0x1002, 0xaa18),
2219 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2220 { PCI_DEVICE(0x1002, 0xaa20),
2221 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2222 { PCI_DEVICE(0x1002, 0xaa28),
2223 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2224 { PCI_DEVICE(0x1002, 0xaa30),
2225 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2226 { PCI_DEVICE(0x1002, 0xaa38),
2227 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2228 { PCI_DEVICE(0x1002, 0xaa40),
2229 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2230 { PCI_DEVICE(0x1002, 0xaa48),
2231 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2232 { PCI_DEVICE(0x1002, 0xaa50),
2233 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2234 { PCI_DEVICE(0x1002, 0xaa58),
2235 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2236 { PCI_DEVICE(0x1002, 0xaa60),
2237 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2238 { PCI_DEVICE(0x1002, 0xaa68),
2239 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2240 { PCI_DEVICE(0x1002, 0xaa80),
2241 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2242 { PCI_DEVICE(0x1002, 0xaa88),
2243 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2244 { PCI_DEVICE(0x1002, 0xaa90),
2245 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2246 { PCI_DEVICE(0x1002, 0xaa98),
2247 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2248 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2249 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2250 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2251 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2252 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2253 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2254 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2255 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2256 { PCI_DEVICE(0x1002, 0xaac0),
2257 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2258 { PCI_DEVICE(0x1002, 0xaac8),
2259 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2260 { PCI_DEVICE(0x1002, 0xaad8),
2261 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2262 { PCI_DEVICE(0x1002, 0xaae8),
2263 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2264 /* VIA VT8251/VT8237A */
9477c58e
TI		 2265 { PCI_DEVICE(0x1106, 0x3288),
2266 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2267 /* VIA GFX VT7122/VX900 */
2268 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2269 /* VIA GFX VT6122/VX11 */
2270 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2271 /* SIS966 */
2272 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2273 /* ULI M5461 */
2274 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2275 /* NVIDIA MCP */
0c2fd1bf
TI		 2276 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2277 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2278 .class_mask = 0xffffff,
9477c58e 2279 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2280 /* Teradici */
9477c58e
TI		 2281 { PCI_DEVICE(0x6549, 0x1200),
2282 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2283 { PCI_DEVICE(0x6549, 0x2200),
2284 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2285 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2286 /* CTHDA chips */
2287 { PCI_DEVICE(0x1102, 0x0010),
2288 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2289 { PCI_DEVICE(0x1102, 0x0012),
2290 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2291#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2292 /* the following entry conflicts with snd-ctxfi driver,
2293 * as ctxfi driver mutates from HD-audio to native mode with
2294 * a special command sequence.
2295 */
4e01f54b
TI		 2296 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2297 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2298 .class_mask = 0xffffff,
9477c58e 2299 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
cadd16ea 2300 AZX_DCAPS_NO_64BIT |
69f9ba9b 2301 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2302#else
2303 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2304 { PCI_DEVICE(0x1102, 0x0009),
2305 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
cadd16ea 2306 AZX_DCAPS_NO_64BIT |
69f9ba9b 2307 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2308#endif
c563f473
TI		 2309 /* CM8888 */
2310 { PCI_DEVICE(0x13f6, 0x5011),
2311 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2312 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2313 /* Vortex86MX */
2314 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2315 /* VMware HDAudio */
2316 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2317 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2318 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2319 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2320 .class_mask = 0xffffff,
9477c58e 2321 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2322 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2323 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2324 .class_mask = 0xffffff,
9477c58e 2325 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2326 { 0, }
2327};
2328MODULE_DEVICE_TABLE(pci, azx_ids);
2329
2330/* pci_driver definition */
e9f66d9b 2331static struct pci_driver azx_driver = {
3733e424 2332 .name = KBUILD_MODNAME,
1da177e4
LT		 2333 .id_table = azx_ids,
2334 .probe = azx_probe,
e23e7a14 2335 .remove = azx_remove,
b2a0bafa 2336 .shutdown = azx_shutdown,
68cb2b55
TI		 2337 .driver = {
2338 .pm = AZX_PM_OPS,
2339 },
1da177e4
LT		 2340};
2341
e9f66d9b 2342module_pci_driver(azx_driver);
Linux kernel - Deliverables
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