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Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
2538a4f5 65#include "hda_priv.h"
e4d9e513 66#include "hda_i915.h"
1da177e4 67
b6050ef6
TI		 68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
9a34af4a
TI		 77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
33124929
TI		 97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
1da177e4 114
5aba4f8e
TI		 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 118static char *model[SNDRV_CARDS];
1dac6695 119static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 120static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 121static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 122static int probe_only[SNDRV_CARDS];
26a6cb6c 123static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 124static bool single_cmd;
71623855 125static int enable_msi = -1;
4ea6fbc8
TI		 126#ifdef CONFIG_SND_HDA_PATCH_LOADER
127static char *patch[SNDRV_CARDS];
128#endif
2dca0bba 129#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 130static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132#endif
1da177e4 133
5aba4f8e 134module_param_array(index, int, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 136module_param_array(id, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 138module_param_array(enable, bool, NULL, 0444);
139MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140module_param_array(model, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 142module_param_array(position_fix, int, NULL, 0444);
4cb36310 143MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 145module_param_array(bdl_pos_adj, int, NULL, 0644);
146MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 147module_param_array(probe_mask, int, NULL, 0444);
606ad75f 148MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 149module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 150MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 151module_param_array(jackpoll_ms, int, NULL, 0444);
152MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 153module_param(single_cmd, bool, 0444);
d01ce99f
TI		 154MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
ac9ef6cf 156module_param(enable_msi, bint, 0444);
134a11f0 157MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 158#ifdef CONFIG_SND_HDA_PATCH_LOADER
159module_param_array(patch, charp, NULL, 0444);
160MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161#endif
2dca0bba 162#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 163module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 164MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 165 "(0=off, 1=on) (default=1).");
2dca0bba 166#endif
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d
TI		 169static int param_set_xint(const char *val, const struct kernel_param *kp);
170static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 177static int *power_save_addr = &power_save;
65fcd41d 178module_param(power_save, xint, 0644);
fee2fba3
TI		 179MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
1da177e4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 189#else
190static int *power_save_addr;
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9
TI		 198#ifdef CONFIG_X86
199static bool hda_snoop = true;
200module_param_named(snoop, hda_snoop, bool, 0444);
201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
c8b00fd2 221 "{Intel, SPT},"
b4565913 222 "{Intel, SPT_LP},"
e926f2c8 223 "{Intel, HPT},"
cea310e8 224 "{Intel, PBG},"
4979bca9 225 "{Intel, SCH},"
fc20a562 226 "{ATI, SB450},"
89be83f8 227 "{ATI, SB600},"
778b6e1b 228 "{ATI, RS600},"
5b15c95f 229 "{ATI, RS690},"
e6db1119
WL		 230 "{ATI, RS780},"
231 "{ATI, R600},"
2797f724
HRK		 232 "{ATI, RV630},"
233 "{ATI, RV610},"
27da1834
WL		 234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
fc20a562 238 "{VIA, VT8251},"
47672310 239 "{VIA, VT8237A},"
07e4ca50
TI		 240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
1da177e4
LT		 242MODULE_DESCRIPTION("Intel HDA driver");
243
a82d51ed 244#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 245#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 246#define SUPPORT_VGA_SWITCHEROO
247#endif
248#endif
249
250
1da177e4 251/*
1da177e4 252 */
1da177e4 253
07e4ca50
TI		 254/* driver types */
255enum {
256 AZX_DRIVER_ICH,
32679f95 257 AZX_DRIVER_PCH,
4979bca9 258 AZX_DRIVER_SCH,
fab1285a 259 AZX_DRIVER_HDMI,
07e4ca50 260 AZX_DRIVER_ATI,
778b6e1b 261 AZX_DRIVER_ATIHDMI,
1815b34a 262 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
da3fca21 266 AZX_DRIVER_NVIDIA,
f269002e 267 AZX_DRIVER_TERA,
14d34f16 268 AZX_DRIVER_CTX,
5ae763b1 269 AZX_DRIVER_CTHDA,
c563f473 270 AZX_DRIVER_CMEDIA,
c4da29ca 271 AZX_DRIVER_GENERIC,
2f5983f2 272 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 273};
274
2ea3c6a2 275/* quirks for Intel PCH */
d7dab4db 276#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 277 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
cd50065b 278 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN)
d7dab4db
TI		 279
280#define AZX_DCAPS_INTEL_PCH \
281 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 282
33499a15
TI		 283#define AZX_DCAPS_INTEL_HASWELL \
284 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
285 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
286 AZX_DCAPS_I915_POWERWELL)
287
54a0405d
LY		 288/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
289#define AZX_DCAPS_INTEL_BROADWELL \
290 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
291 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
292 AZX_DCAPS_I915_POWERWELL)
293
9477c58e
TI		 294/* quirks for ATI SB / AMD Hudson */
295#define AZX_DCAPS_PRESET_ATI_SB \
296 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
297 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
298
299/* quirks for ATI/AMD HDMI */
300#define AZX_DCAPS_PRESET_ATI_HDMI \
301 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
302
303/* quirks for Nvidia */
304#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 305 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 306 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
307 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 308
5ae763b1
TI		 309#define AZX_DCAPS_PRESET_CTHDA \
310 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
311
a82d51ed
TI		 312/*
313 * VGA-switcher support
314 */
315#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 316#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
317#else
318#define use_vga_switcheroo(chip) 0
319#endif
320
48c8b0eb 321static char *driver_short_names[] = {
07e4ca50 322 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 323 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 324 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 325 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 326 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 327 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 328 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 329 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
330 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 331 [AZX_DRIVER_ULI] = "HDA ULI M5461",
332 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 333 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 334 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 335 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 336 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 337 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 338};
339
a07187c9
ML		 340struct hda_intel {
341 struct azx chip;
342
9a34af4a
TI		 343 /* for pending irqs */
344 struct work_struct irq_pending_work;
345
346 /* sync probing */
347 struct completion probe_wait;
348 struct work_struct probe_work;
349
350 /* card list (for power_save trigger) */
351 struct list_head list;
352
353 /* extra flags */
354 unsigned int irq_pending_warned:1;
355
356 /* VGA-switcheroo setup */
357 unsigned int use_vga_switcheroo:1;
358 unsigned int vga_switcheroo_registered:1;
359 unsigned int init_failed:1; /* delayed init failed */
360
361 /* secondary power domain for hdmi audio under vga device */
362 struct dev_pm_domain hdmi_pm_domain;
363};
a07187c9 364
27fe48d9 365#ifdef CONFIG_X86
9ddf1aeb 366static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 367{
9ddf1aeb
TI		 368 int pages;
369
27fe48d9
TI		 370 if (azx_snoop(chip))
371 return;
9ddf1aeb
TI		 372 if (!dmab || !dmab->area || !dmab->bytes)
373 return;
374
375#ifdef CONFIG_SND_DMA_SGBUF
376 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
377 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 378 if (chip->driver_type == AZX_DRIVER_CMEDIA)
379 return; /* deal with only CORB/RIRB buffers */
27fe48d9 380 if (on)
9ddf1aeb 381 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 382 else
9ddf1aeb
TI		 383 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
384 return;
27fe48d9 385 }
9ddf1aeb
TI		 386#endif
387
388 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
389 if (on)
390 set_memory_wc((unsigned long)dmab->area, pages);
391 else
392 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 393}
394
395static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
396 bool on)
397{
9ddf1aeb 398 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 399}
400static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 401 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 402{
403 if (azx_dev->wc_marked != on) {
9ddf1aeb 404 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 405 azx_dev->wc_marked = on;
406 }
407}
408#else
409/* NOP for other archs */
410static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
411 bool on)
412{
413}
414static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 415 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 416{
417}
418#endif
419
68e7fffc 420static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 421
cb53c626
TI		 422/*
423 * initialize the PCI registers
424 */
425/* update bits in a PCI register byte */
426static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
427 unsigned char mask, unsigned char val)
428{
429 unsigned char data;
430
431 pci_read_config_byte(pci, reg, &data);
432 data &= ~mask;
433 data |= (val & mask);
434 pci_write_config_byte(pci, reg, data);
435}
436
437static void azx_init_pci(struct azx *chip)
438{
439 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
440 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
441 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 442 * codecs.
443 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 444 */
46f2cc80 445 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 446 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 447 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 448 }
cb53c626 449
9477c58e
TI		 450 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
451 * we need to enable snoop.
452 */
453 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 454 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
455 azx_snoop(chip));
cb53c626 456 update_pci_byte(chip->pci,
27fe48d9
TI		 457 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
458 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 459 }
460
461 /* For NVIDIA HDA, enable snoop */
462 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 463 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
464 azx_snoop(chip));
cb53c626
TI		 465 update_pci_byte(chip->pci,
466 NVIDIA_HDA_TRANSREG_ADDR,
467 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 468 update_pci_byte(chip->pci,
469 NVIDIA_HDA_ISTRM_COH,
470 0x01, NVIDIA_HDA_ENABLE_COHBIT);
471 update_pci_byte(chip->pci,
472 NVIDIA_HDA_OSTRM_COH,
473 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 474 }
475
476 /* Enable SCH/PCH snoop if needed */
477 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 478 unsigned short snoop;
90a5ad52 479 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 480 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
481 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
482 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
483 if (!azx_snoop(chip))
484 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
485 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 486 pci_read_config_word(chip->pci,
487 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 488 }
4e76a883
TI		 489 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
490 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
491 "Disabled" : "Enabled");
da3fca21 492 }
1da177e4
LT		 493}
494
b6050ef6
TI		 495/* calculate runtime delay from LPIB */
496static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
497 unsigned int pos)
498{
499 struct snd_pcm_substream *substream = azx_dev->substream;
500 int stream = substream->stream;
501 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
502 int delay;
503
504 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
505 delay = pos - lpib_pos;
506 else
507 delay = lpib_pos - pos;
508 if (delay < 0) {
509 if (delay >= azx_dev->delay_negative_threshold)
510 delay = 0;
511 else
512 delay += azx_dev->bufsize;
513 }
514
515 if (delay >= azx_dev->period_bytes) {
516 dev_info(chip->card->dev,
517 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
518 delay, azx_dev->period_bytes);
519 delay = 0;
520 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
521 chip->get_delay[stream] = NULL;
522 }
523
524 return bytes_to_frames(substream->runtime, delay);
525}
526
9ad593f6
TI		 527static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
528
7ca954a8
DR		 529/* called from IRQ */
530static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
531{
9a34af4a 532 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 533 int ok;
534
535 ok = azx_position_ok(chip, azx_dev);
536 if (ok == 1) {
537 azx_dev->irq_pending = 0;
538 return ok;
539 } else if (ok == 0 && chip->bus && chip->bus->workq) {
540 /* bogus IRQ, process it later */
541 azx_dev->irq_pending = 1;
9a34af4a 542 queue_work(chip->bus->workq, &hda->irq_pending_work);
7ca954a8
DR		 543 }
544 return 0;
545}
546
9ad593f6
TI		 547/*
548 * Check whether the current DMA position is acceptable for updating
549 * periods. Returns non-zero if it's OK.
550 *
551 * Many HD-audio controllers appear pretty inaccurate about
552 * the update-IRQ timing. The IRQ is issued before actually the
553 * data is processed. So, we need to process it afterwords in a
554 * workqueue.
555 */
556static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
557{
b6050ef6
TI		 558 struct snd_pcm_substream *substream = azx_dev->substream;
559 int stream = substream->stream;
e5463720 560 u32 wallclk;
9ad593f6
TI		 561 unsigned int pos;
562
f48f606d
JK		 563 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
564 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 565 return -1; /* bogus (too early) interrupt */
fa00e046 566
b6050ef6
TI		 567 if (chip->get_position[stream])
568 pos = chip->get_position[stream](chip, azx_dev);
569 else { /* use the position buffer as default */
570 pos = azx_get_pos_posbuf(chip, azx_dev);
571 if (!pos || pos == (u32)-1) {
572 dev_info(chip->card->dev,
573 "Invalid position buffer, using LPIB read method instead.\n");
574 chip->get_position[stream] = azx_get_pos_lpib;
575 pos = azx_get_pos_lpib(chip, azx_dev);
576 chip->get_delay[stream] = NULL;
577 } else {
578 chip->get_position[stream] = azx_get_pos_posbuf;
579 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
580 chip->get_delay[stream] = azx_get_delay_from_lpib;
581 }
582 }
583
584 if (pos >= azx_dev->bufsize)
585 pos = 0;
9ad593f6 586
d6d8bf54
TI		 587 if (WARN_ONCE(!azx_dev->period_bytes,
588 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 589 return -1; /* this shouldn't happen! */
edb39935 590 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 591 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
592 /* NG - it's below the first next period boundary */
9cdc0115 593 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 594 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 595 return 1; /* OK, it's fine */
596}
597
598/*
599 * The work for pending PCM period updates.
600 */
601static void azx_irq_pending_work(struct work_struct *work)
602{
9a34af4a
TI		 603 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
604 struct azx *chip = &hda->chip;
e5463720 605 int i, pending, ok;
9ad593f6 606
9a34af4a 607 if (!hda->irq_pending_warned) {
4e76a883
TI		 608 dev_info(chip->card->dev,
609 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
610 chip->card->number);
9a34af4a 611 hda->irq_pending_warned = 1;
a6a950a8
TI		 612 }
613
9ad593f6
TI		 614 for (;;) {
615 pending = 0;
616 spin_lock_irq(&chip->reg_lock);
617 for (i = 0; i < chip->num_streams; i++) {
618 struct azx_dev *azx_dev = &chip->azx_dev[i];
619 if (!azx_dev->irq_pending ||
620 !azx_dev->substream ||
621 !azx_dev->running)
622 continue;
e5463720
JK		 623 ok = azx_position_ok(chip, azx_dev);
624 if (ok > 0) {
9ad593f6
TI		 625 azx_dev->irq_pending = 0;
626 spin_unlock(&chip->reg_lock);
627 snd_pcm_period_elapsed(azx_dev->substream);
628 spin_lock(&chip->reg_lock);
e5463720
JK		 629 } else if (ok < 0) {
630 pending = 0; /* too early */
9ad593f6
TI		 631 } else
632 pending++;
633 }
634 spin_unlock_irq(&chip->reg_lock);
635 if (!pending)
636 return;
08af495f 637 msleep(1);
9ad593f6
TI		 638 }
639}
640
641/* clear irq_pending flags and assure no on-going workq */
642static void azx_clear_irq_pending(struct azx *chip)
643{
644 int i;
645
646 spin_lock_irq(&chip->reg_lock);
647 for (i = 0; i < chip->num_streams; i++)
648 chip->azx_dev[i].irq_pending = 0;
649 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 650}
651
68e7fffc
TI		 652static int azx_acquire_irq(struct azx *chip, int do_disconnect)
653{
437a5a46
TI		 654 if (request_irq(chip->pci->irq, azx_interrupt,
655 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 656 KBUILD_MODNAME, chip)) {
4e76a883
TI		 657 dev_err(chip->card->dev,
658 "unable to grab IRQ %d, disabling device\n",
659 chip->pci->irq);
68e7fffc
TI		 660 if (do_disconnect)
661 snd_card_disconnect(chip->card);
662 return -1;
663 }
664 chip->irq = chip->pci->irq;
69e13418 665 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 666 return 0;
667}
668
b6050ef6
TI		 669/* get the current DMA position with correction on VIA chips */
670static unsigned int azx_via_get_position(struct azx *chip,
671 struct azx_dev *azx_dev)
672{
673 unsigned int link_pos, mini_pos, bound_pos;
674 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
675 unsigned int fifo_size;
676
677 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
678 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
679 /* Playback, no problem using link position */
680 return link_pos;
681 }
682
683 /* Capture */
684 /* For new chipset,
685 * use mod to get the DMA position just like old chipset
686 */
687 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
688 mod_dma_pos %= azx_dev->period_bytes;
689
690 /* azx_dev->fifo_size can't get FIFO size of in stream.
691 * Get from base address + offset.
692 */
693 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
694
695 if (azx_dev->insufficient) {
696 /* Link position never gather than FIFO size */
697 if (link_pos <= fifo_size)
698 return 0;
699
700 azx_dev->insufficient = 0;
701 }
702
703 if (link_pos <= fifo_size)
704 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
705 else
706 mini_pos = link_pos - fifo_size;
707
708 /* Find nearest previous boudary */
709 mod_mini_pos = mini_pos % azx_dev->period_bytes;
710 mod_link_pos = link_pos % azx_dev->period_bytes;
711 if (mod_link_pos >= fifo_size)
712 bound_pos = link_pos - mod_link_pos;
713 else if (mod_dma_pos >= mod_mini_pos)
714 bound_pos = mini_pos - mod_mini_pos;
715 else {
716 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
717 if (bound_pos >= azx_dev->bufsize)
718 bound_pos = 0;
719 }
720
721 /* Calculate real DMA position we want */
722 return bound_pos + mod_dma_pos;
723}
724
83012a7c 725#ifdef CONFIG_PM
65fcd41d
TI		 726static DEFINE_MUTEX(card_list_lock);
727static LIST_HEAD(card_list);
728
729static void azx_add_card_list(struct azx *chip)
730{
9a34af4a 731 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 732 mutex_lock(&card_list_lock);
9a34af4a 733 list_add(&hda->list, &card_list);
65fcd41d
TI		 734 mutex_unlock(&card_list_lock);
735}
736
737static void azx_del_card_list(struct azx *chip)
738{
9a34af4a 739 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 740 mutex_lock(&card_list_lock);
9a34af4a 741 list_del_init(&hda->list);
65fcd41d
TI		 742 mutex_unlock(&card_list_lock);
743}
744
745/* trigger power-save check at writing parameter */
746static int param_set_xint(const char *val, const struct kernel_param *kp)
747{
9a34af4a 748 struct hda_intel *hda;
65fcd41d
TI		 749 struct azx *chip;
750 struct hda_codec *c;
751 int prev = power_save;
752 int ret = param_set_int(val, kp);
753
754 if (ret || prev == power_save)
755 return ret;
756
757 mutex_lock(&card_list_lock);
9a34af4a
TI		 758 list_for_each_entry(hda, &card_list, list) {
759 chip = &hda->chip;
65fcd41d
TI		 760 if (!chip->bus || chip->disabled)
761 continue;
762 list_for_each_entry(c, &chip->bus->codec_list, list)
763 snd_hda_power_sync(c);
764 }
765 mutex_unlock(&card_list_lock);
766 return 0;
767}
768#else
769#define azx_add_card_list(chip) /* NOP */
770#define azx_del_card_list(chip) /* NOP */
83012a7c 771#endif /* CONFIG_PM */
5c0b9bec 772
7ccbde57 773#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 774/*
775 * power management
776 */
68cb2b55 777static int azx_suspend(struct device *dev)
1da177e4 778{
68cb2b55
TI		 779 struct pci_dev *pci = to_pci_dev(dev);
780 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 781 struct azx *chip;
782 struct hda_intel *hda;
01b65bfb 783 struct azx_pcm *p;
1da177e4 784
2d9772ef
TI		 785 if (!card)
786 return 0;
787
788 chip = card->private_data;
789 hda = container_of(chip, struct hda_intel, chip);
1618e84a 790 if (chip->disabled || hda->init_failed)
c5c21523
TI		 791 return 0;
792
421a1252 793 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 794 azx_clear_irq_pending(chip);
01b65bfb
TI		 795 list_for_each_entry(p, &chip->pcm_list, list)
796 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 797 if (chip->initialized)
8dd78330 798 snd_hda_suspend(chip->bus);
cb53c626 799 azx_stop_chip(chip);
7295b264 800 azx_enter_link_reset(chip);
30b35399 801 if (chip->irq >= 0) {
43001c95 802 free_irq(chip->irq, chip);
30b35399
TI		 803 chip->irq = -1;
804 }
a07187c9 805
68e7fffc 806 if (chip->msi)
43001c95 807 pci_disable_msi(chip->pci);
421a1252
TI		 808 pci_disable_device(pci);
809 pci_save_state(pci);
68cb2b55 810 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 811 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
812 hda_display_power(false);
1da177e4
LT		 813 return 0;
814}
815
68cb2b55 816static int azx_resume(struct device *dev)
1da177e4 817{
68cb2b55
TI		 818 struct pci_dev *pci = to_pci_dev(dev);
819 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 820 struct azx *chip;
821 struct hda_intel *hda;
822
823 if (!card)
824 return 0;
1da177e4 825
2d9772ef
TI		 826 chip = card->private_data;
827 hda = container_of(chip, struct hda_intel, chip);
1618e84a 828 if (chip->disabled || hda->init_failed)
c5c21523
TI		 829 return 0;
830
a07187c9 831 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 832 hda_display_power(true);
e4d9e513 833 haswell_set_bclk(chip);
a07187c9 834 }
d14a7e0b
TI		 835 pci_set_power_state(pci, PCI_D0);
836 pci_restore_state(pci);
30b35399 837 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 838 dev_err(chip->card->dev,
839 "pci_enable_device failed, disabling device\n");
30b35399
TI		 840 snd_card_disconnect(card);
841 return -EIO;
842 }
843 pci_set_master(pci);
68e7fffc
TI		 844 if (chip->msi)
845 if (pci_enable_msi(pci) < 0)
846 chip->msi = 0;
847 if (azx_acquire_irq(chip, 1) < 0)
30b35399 848 return -EIO;
cb53c626 849 azx_init_pci(chip);
d804ad92 850
17c3ad03 851 azx_init_chip(chip, true);
d804ad92 852
1da177e4 853 snd_hda_resume(chip->bus);
421a1252 854 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 855 return 0;
856}
b8dfc462
ML		 857#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
858
859#ifdef CONFIG_PM_RUNTIME
860static int azx_runtime_suspend(struct device *dev)
861{
862 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 863 struct azx *chip;
864 struct hda_intel *hda;
b8dfc462 865
2d9772ef
TI		 866 if (!card)
867 return 0;
868
869 chip = card->private_data;
870 hda = container_of(chip, struct hda_intel, chip);
1618e84a 871 if (chip->disabled || hda->init_failed)
246efa4a
DA		 872 return 0;
873
874 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
875 return 0;
876
7d4f606c
WX		 877 /* enable controller wake up event */
878 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
879 STATESTS_INT_MASK);
880
b8dfc462 881 azx_stop_chip(chip);
873ce8ad 882 azx_enter_link_reset(chip);
b8dfc462 883 azx_clear_irq_pending(chip);
e4d9e513 884 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d 885 hda_display_power(false);
e4d9e513 886
b8dfc462
ML		 887 return 0;
888}
889
890static int azx_runtime_resume(struct device *dev)
891{
892 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 893 struct azx *chip;
894 struct hda_intel *hda;
7d4f606c
WX		 895 struct hda_bus *bus;
896 struct hda_codec *codec;
897 int status;
b8dfc462 898
2d9772ef
TI		 899 if (!card)
900 return 0;
901
902 chip = card->private_data;
903 hda = container_of(chip, struct hda_intel, chip);
1618e84a 904 if (chip->disabled || hda->init_failed)
246efa4a
DA		 905 return 0;
906
907 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
908 return 0;
909
a07187c9 910 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 911 hda_display_power(true);
e4d9e513 912 haswell_set_bclk(chip);
a07187c9 913 }
7d4f606c
WX		 914
915 /* Read STATESTS before controller reset */
916 status = azx_readw(chip, STATESTS);
917
b8dfc462 918 azx_init_pci(chip);
17c3ad03 919 azx_init_chip(chip, true);
7d4f606c
WX		 920
921 bus = chip->bus;
922 if (status && bus) {
923 list_for_each_entry(codec, &bus->codec_list, list)
924 if (status & (1 << codec->addr))
925 queue_delayed_work(codec->bus->workq,
926 &codec->jackpoll_work, codec->jackpoll_interval);
927 }
928
929 /* disable controller Wake Up event*/
930 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
931 ~STATESTS_INT_MASK);
932
b8dfc462
ML		 933 return 0;
934}
6eb827d2
TI		 935
936static int azx_runtime_idle(struct device *dev)
937{
938 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 939 struct azx *chip;
940 struct hda_intel *hda;
941
942 if (!card)
943 return 0;
6eb827d2 944
2d9772ef
TI		 945 chip = card->private_data;
946 hda = container_of(chip, struct hda_intel, chip);
1618e84a 947 if (chip->disabled || hda->init_failed)
246efa4a
DA		 948 return 0;
949
6eb827d2
TI		 950 if (!power_save_controller ||
951 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
952 return -EBUSY;
953
954 return 0;
955}
956
b8dfc462
ML		 957#endif /* CONFIG_PM_RUNTIME */
958
959#ifdef CONFIG_PM
960static const struct dev_pm_ops azx_pm = {
961 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 962 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 963};
964
68cb2b55
TI		 965#define AZX_PM_OPS &azx_pm
966#else
68cb2b55 967#define AZX_PM_OPS NULL
b8dfc462 968#endif /* CONFIG_PM */
1da177e4
LT		 969
970
48c8b0eb 971static int azx_probe_continue(struct azx *chip);
a82d51ed 972
8393ec4a 973#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 974static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 975
a82d51ed
TI		 976static void azx_vs_set_state(struct pci_dev *pci,
977 enum vga_switcheroo_state state)
978{
979 struct snd_card *card = pci_get_drvdata(pci);
980 struct azx *chip = card->private_data;
9a34af4a 981 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 982 bool disabled;
983
9a34af4a
TI		 984 wait_for_completion(&hda->probe_wait);
985 if (hda->init_failed)
a82d51ed
TI		 986 return;
987
988 disabled = (state == VGA_SWITCHEROO_OFF);
989 if (chip->disabled == disabled)
990 return;
991
992 if (!chip->bus) {
993 chip->disabled = disabled;
994 if (!disabled) {
4e76a883
TI		 995 dev_info(chip->card->dev,
996 "Start delayed initialization\n");
5c90680e 997 if (azx_probe_continue(chip) < 0) {
4e76a883 998 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 999 hda->init_failed = true;
a82d51ed
TI		 1000 }
1001 }
1002 } else {
4e76a883
TI		 1003 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1004 disabled ? "Disabling" : "Enabling");
a82d51ed 1005 if (disabled) {
8928756d
DR		 1006 pm_runtime_put_sync_suspend(card->dev);
1007 azx_suspend(card->dev);
246efa4a
DA		 1008 /* when we get suspended by vga switcheroo we end up in D3cold,
1009 * however we have no ACPI handle, so pci/acpi can't put us there,
1010 * put ourselves there */
1011 pci->current_state = PCI_D3cold;
a82d51ed 1012 chip->disabled = true;
128960a9 1013 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1014 dev_warn(chip->card->dev,
1015 "Cannot lock devices!\n");
a82d51ed
TI		 1016 } else {
1017 snd_hda_unlock_devices(chip->bus);
8928756d 1018 pm_runtime_get_noresume(card->dev);
a82d51ed 1019 chip->disabled = false;
8928756d 1020 azx_resume(card->dev);
a82d51ed
TI		 1021 }
1022 }
1023}
1024
1025static bool azx_vs_can_switch(struct pci_dev *pci)
1026{
1027 struct snd_card *card = pci_get_drvdata(pci);
1028 struct azx *chip = card->private_data;
9a34af4a 1029 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1030
9a34af4a
TI		 1031 wait_for_completion(&hda->probe_wait);
1032 if (hda->init_failed)
a82d51ed
TI		 1033 return false;
1034 if (chip->disabled || !chip->bus)
1035 return true;
1036 if (snd_hda_lock_devices(chip->bus))
1037 return false;
1038 snd_hda_unlock_devices(chip->bus);
1039 return true;
1040}
1041
e23e7a14 1042static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1043{
9a34af4a 1044 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1045 struct pci_dev *p = get_bound_vga(chip->pci);
1046 if (p) {
4e76a883
TI		 1047 dev_info(chip->card->dev,
1048 "Handle VGA-switcheroo audio client\n");
9a34af4a 1049 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1050 pci_dev_put(p);
1051 }
1052}
1053
1054static const struct vga_switcheroo_client_ops azx_vs_ops = {
1055 .set_gpu_state = azx_vs_set_state,
1056 .can_switch = azx_vs_can_switch,
1057};
1058
e23e7a14 1059static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1060{
9a34af4a 1061 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1062 int err;
1063
9a34af4a 1064 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1065 return 0;
1066 /* FIXME: currently only handling DIS controller
1067 * is there any machine with two switchable HDMI audio controllers?
1068 */
128960a9 1069 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1070 VGA_SWITCHEROO_DIS,
1071 chip->bus != NULL);
128960a9
TI		 1072 if (err < 0)
1073 return err;
9a34af4a 1074 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1075
1076 /* register as an optimus hdmi audio power domain */
8928756d 1077 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1078 &hda->hdmi_pm_domain);
128960a9 1079 return 0;
a82d51ed
TI		 1080}
1081#else
1082#define init_vga_switcheroo(chip) /* NOP */
1083#define register_vga_switcheroo(chip) 0
8393ec4a 1084#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1085#endif /* SUPPORT_VGA_SWITCHER */
1086
1da177e4
LT		 1087/*
1088 * destructor
1089 */
a98f90fd 1090static int azx_free(struct azx *chip)
1da177e4 1091{
c67e2228 1092 struct pci_dev *pci = chip->pci;
a07187c9 1093 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1094 int i;
1095
c67e2228
WX		 1096 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1097 && chip->running)
1098 pm_runtime_get_noresume(&pci->dev);
1099
65fcd41d
TI		 1100 azx_del_card_list(chip);
1101
0cbf0098
TI		 1102 azx_notifier_unregister(chip);
1103
9a34af4a
TI		 1104 hda->init_failed = 1; /* to be sure */
1105 complete_all(&hda->probe_wait);
f4c482a4 1106
9a34af4a 1107 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1108 if (chip->disabled && chip->bus)
1109 snd_hda_unlock_devices(chip->bus);
9a34af4a 1110 if (hda->vga_switcheroo_registered)
128960a9 1111 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1112 }
1113
ce43fbae 1114 if (chip->initialized) {
9ad593f6 1115 azx_clear_irq_pending(chip);
07e4ca50 1116 for (i = 0; i < chip->num_streams; i++)
1da177e4 1117 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1118 azx_stop_chip(chip);
1da177e4
LT		 1119 }
1120
f000fd80 1121 if (chip->irq >= 0)
1da177e4 1122 free_irq(chip->irq, (void*)chip);
68e7fffc 1123 if (chip->msi)
30b35399 1124 pci_disable_msi(chip->pci);
f079c25a
TI		 1125 if (chip->remap_addr)
1126 iounmap(chip->remap_addr);
1da177e4 1127
67908994 1128 azx_free_stream_pages(chip);
a82d51ed
TI		 1129 if (chip->region_requested)
1130 pci_release_regions(chip->pci);
1da177e4 1131 pci_disable_device(chip->pci);
07e4ca50 1132 kfree(chip->azx_dev);
4918cdab
TI		 1133#ifdef CONFIG_SND_HDA_PATCH_LOADER
1134 if (chip->fw)
1135 release_firmware(chip->fw);
1136#endif
99a2008d
WX		 1137 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1138 hda_display_power(false);
1139 hda_i915_exit();
1140 }
a07187c9 1141 kfree(hda);
1da177e4
LT		 1142
1143 return 0;
1144}
1145
a98f90fd 1146static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1147{
1148 return azx_free(device->device_data);
1149}
1150
8393ec4a 1151#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1152/*
1153 * Check of disabled HDMI controller by vga-switcheroo
1154 */
e23e7a14 1155static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1156{
1157 struct pci_dev *p;
1158
1159 /* check only discrete GPU */
1160 switch (pci->vendor) {
1161 case PCI_VENDOR_ID_ATI:
1162 case PCI_VENDOR_ID_AMD:
1163 case PCI_VENDOR_ID_NVIDIA:
1164 if (pci->devfn == 1) {
1165 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1166 pci->bus->number, 0);
1167 if (p) {
1168 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1169 return p;
1170 pci_dev_put(p);
1171 }
1172 }
1173 break;
1174 }
1175 return NULL;
1176}
1177
e23e7a14 1178static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1179{
1180 bool vga_inactive = false;
1181 struct pci_dev *p = get_bound_vga(pci);
1182
1183 if (p) {
12b78a7f 1184 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1185 vga_inactive = true;
1186 pci_dev_put(p);
1187 }
1188 return vga_inactive;
1189}
8393ec4a 1190#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1191
3372a153
TI		 1192/*
1193 * white/black-listing for position_fix
1194 */
e23e7a14 1195static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1196 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1197 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1198 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1199 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1200 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1201 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1202 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1203 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1204 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1205 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1206 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1207 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1208 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1209 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1210 {}
1211};
1212
e23e7a14 1213static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1214{
1215 const struct snd_pci_quirk *q;
1216
c673ba1c 1217 switch (fix) {
1dac6695 1218 case POS_FIX_AUTO:
c673ba1c
TI		 1219 case POS_FIX_LPIB:
1220 case POS_FIX_POSBUF:
4cb36310 1221 case POS_FIX_VIACOMBO:
a6f2fd55 1222 case POS_FIX_COMBO:
c673ba1c
TI		 1223 return fix;
1224 }
1225
c673ba1c
TI		 1226 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1227 if (q) {
4e76a883
TI		 1228 dev_info(chip->card->dev,
1229 "position_fix set to %d for device %04x:%04x\n",
1230 q->value, q->subvendor, q->subdevice);
c673ba1c 1231 return q->value;
3372a153 1232 }
bdd9ef24
DH		 1233
1234 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1235 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1236 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1237 return POS_FIX_VIACOMBO;
9477c58e
TI		 1238 }
1239 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1240 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1241 return POS_FIX_LPIB;
bdd9ef24 1242 }
c673ba1c 1243 return POS_FIX_AUTO;
3372a153
TI		 1244}
1245
b6050ef6
TI		 1246static void assign_position_fix(struct azx *chip, int fix)
1247{
1248 static azx_get_pos_callback_t callbacks[] = {
1249 [POS_FIX_AUTO] = NULL,
1250 [POS_FIX_LPIB] = azx_get_pos_lpib,
1251 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1252 [POS_FIX_VIACOMBO] = azx_via_get_position,
1253 [POS_FIX_COMBO] = azx_get_pos_lpib,
1254 };
1255
1256 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1257
1258 /* combo mode uses LPIB only for playback */
1259 if (fix == POS_FIX_COMBO)
1260 chip->get_position[1] = NULL;
1261
1262 if (fix == POS_FIX_POSBUF &&
1263 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1264 chip->get_delay[0] = chip->get_delay[1] =
1265 azx_get_delay_from_lpib;
1266 }
1267
1268}
1269
669ba27a
TI		 1270/*
1271 * black-lists for probe_mask
1272 */
e23e7a14 1273static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1274 /* Thinkpad often breaks the controller communication when accessing
1275 * to the non-working (or non-existing) modem codec slot.
1276 */
1277 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1278 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1279 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1280 /* broken BIOS */
1281 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1282 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1283 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1284 /* forced codec slots */
93574844 1285 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1286 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1287 /* WinFast VP200 H (Teradici) user reported broken communication */
1288 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1289 {}
1290};
1291
f1eaaeec
TI		 1292#define AZX_FORCE_CODEC_MASK 0x100
1293
e23e7a14 1294static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1295{
1296 const struct snd_pci_quirk *q;
1297
f1eaaeec
TI		 1298 chip->codec_probe_mask = probe_mask[dev];
1299 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1300 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1301 if (q) {
4e76a883
TI		 1302 dev_info(chip->card->dev,
1303 "probe_mask set to 0x%x for device %04x:%04x\n",
1304 q->value, q->subvendor, q->subdevice);
f1eaaeec 1305 chip->codec_probe_mask = q->value;
669ba27a
TI		 1306 }
1307 }
f1eaaeec
TI		 1308
1309 /* check forced option */
1310 if (chip->codec_probe_mask != -1 &&
1311 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1312 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1313 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1314 chip->codec_mask);
f1eaaeec 1315 }
669ba27a
TI		 1316}
1317
4d8e22e0 1318/*
71623855 1319 * white/black-list for enable_msi
4d8e22e0 1320 */
e23e7a14 1321static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1322 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1323 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1324 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1325 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1326 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1327 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1328 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1329 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1330 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1331 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1332 {}
1333};
1334
e23e7a14 1335static void check_msi(struct azx *chip)
4d8e22e0
TI		 1336{
1337 const struct snd_pci_quirk *q;
1338
71623855
TI		 1339 if (enable_msi >= 0) {
1340 chip->msi = !!enable_msi;
4d8e22e0 1341 return;
71623855
TI		 1342 }
1343 chip->msi = 1; /* enable MSI as default */
1344 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1345 if (q) {
4e76a883
TI		 1346 dev_info(chip->card->dev,
1347 "msi for device %04x:%04x set to %d\n",
1348 q->subvendor, q->subdevice, q->value);
4d8e22e0 1349 chip->msi = q->value;
80c43ed7
TI		 1350 return;
1351 }
1352
1353 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1354 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1355 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1356 chip->msi = 0;
4d8e22e0
TI		 1357 }
1358}
1359
a1585d76 1360/* check the snoop mode availability */
e23e7a14 1361static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1362{
1363 bool snoop = chip->snoop;
1364
1365 switch (chip->driver_type) {
1366 case AZX_DRIVER_VIA:
1367 /* force to non-snoop mode for a new VIA controller
1368 * when BIOS is set
1369 */
1370 if (snoop) {
1371 u8 val;
1372 pci_read_config_byte(chip->pci, 0x42, &val);
1373 if (!(val & 0x80) && chip->pci->revision == 0x30)
1374 snoop = false;
1375 }
1376 break;
1377 case AZX_DRIVER_ATIHDMI_NS:
1378 /* new ATI HDMI requires non-snoop */
1379 snoop = false;
1380 break;
c1279f87 1381 case AZX_DRIVER_CTHDA:
c563f473 1382 case AZX_DRIVER_CMEDIA:
c1279f87
TI		 1383 snoop = false;
1384 break;
a1585d76
TI		 1385 }
1386
1387 if (snoop != chip->snoop) {
4e76a883
TI		 1388 dev_info(chip->card->dev, "Force to %s mode\n",
1389 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1390 chip->snoop = snoop;
1391 }
1392}
669ba27a 1393
99a2008d
WX		 1394static void azx_probe_work(struct work_struct *work)
1395{
9a34af4a
TI		 1396 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1397 azx_probe_continue(&hda->chip);
99a2008d 1398}
99a2008d 1399
1da177e4
LT		 1400/*
1401 * constructor
1402 */
e23e7a14
BP		 1403static int azx_create(struct snd_card *card, struct pci_dev *pci,
1404 int dev, unsigned int driver_caps,
40830813 1405 const struct hda_controller_ops *hda_ops,
e23e7a14 1406 struct azx **rchip)
1da177e4 1407{
a98f90fd 1408 static struct snd_device_ops ops = {
1da177e4
LT		 1409 .dev_free = azx_dev_free,
1410 };
a07187c9 1411 struct hda_intel *hda;
a82d51ed
TI		 1412 struct azx *chip;
1413 int err;
1da177e4
LT		 1414
1415 *rchip = NULL;
bcd72003 1416
927fc866
PM		 1417 err = pci_enable_device(pci);
1418 if (err < 0)
1da177e4
LT		 1419 return err;
1420
a07187c9
ML		 1421 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1422 if (!hda) {
1423 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1424 pci_disable_device(pci);
1425 return -ENOMEM;
1426 }
1427
a07187c9 1428 chip = &hda->chip;
1da177e4 1429 spin_lock_init(&chip->reg_lock);
62932df8 1430 mutex_init(&chip->open_mutex);
1da177e4
LT		 1431 chip->card = card;
1432 chip->pci = pci;
40830813 1433 chip->ops = hda_ops;
1da177e4 1434 chip->irq = -1;
9477c58e
TI		 1435 chip->driver_caps = driver_caps;
1436 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1437 check_msi(chip);
555e219f 1438 chip->dev_index = dev;
749ee287 1439 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1440 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1441 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1442 INIT_LIST_HEAD(&hda->list);
a82d51ed 1443 init_vga_switcheroo(chip);
9a34af4a 1444 init_completion(&hda->probe_wait);
1da177e4 1445
b6050ef6 1446 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1447
5aba4f8e 1448 check_probe_mask(chip, dev);
3372a153 1449
27346166 1450 chip->single_cmd = single_cmd;
27fe48d9 1451 chip->snoop = hda_snoop;
a1585d76 1452 azx_check_snoop_available(chip);
c74db86b 1453
5c0d7bc1
TI		 1454 if (bdl_pos_adj[dev] < 0) {
1455 switch (chip->driver_type) {
0c6341ac 1456 case AZX_DRIVER_ICH:
32679f95 1457 case AZX_DRIVER_PCH:
0c6341ac 1458 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1459 break;
1460 default:
0c6341ac 1461 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1462 break;
1463 }
1464 }
9cdc0115 1465 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1466
a82d51ed
TI		 1467 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1468 if (err < 0) {
4e76a883 1469 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1470 azx_free(chip);
1471 return err;
1472 }
1473
99a2008d 1474 /* continue probing in work context as may trigger request module */
9a34af4a 1475 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1476
a82d51ed 1477 *rchip = chip;
99a2008d 1478
a82d51ed
TI		 1479 return 0;
1480}
1481
48c8b0eb 1482static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1483{
1484 int dev = chip->dev_index;
1485 struct pci_dev *pci = chip->pci;
1486 struct snd_card *card = chip->card;
67908994 1487 int err;
a82d51ed
TI		 1488 unsigned short gcap;
1489
07e4ca50
TI		 1490#if BITS_PER_LONG != 64
1491 /* Fix up base address on ULI M5461 */
1492 if (chip->driver_type == AZX_DRIVER_ULI) {
1493 u16 tmp3;
1494 pci_read_config_word(pci, 0x40, &tmp3);
1495 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1496 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1497 }
1498#endif
1499
927fc866 1500 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1501 if (err < 0)
1da177e4 1502 return err;
a82d51ed 1503 chip->region_requested = 1;
1da177e4 1504
927fc866 1505 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1506 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1507 if (chip->remap_addr == NULL) {
4e76a883 1508 dev_err(card->dev, "ioremap error\n");
a82d51ed 1509 return -ENXIO;
1da177e4
LT		 1510 }
1511
68e7fffc
TI		 1512 if (chip->msi)
1513 if (pci_enable_msi(pci) < 0)
1514 chip->msi = 0;
7376d013 1515
a82d51ed
TI		 1516 if (azx_acquire_irq(chip, 0) < 0)
1517 return -EBUSY;
1da177e4
LT		 1518
1519 pci_set_master(pci);
1520 synchronize_irq(chip->irq);
1521
bcd72003 1522 gcap = azx_readw(chip, GCAP);
4e76a883 1523 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1524
dc4c2e6b 1525 /* disable SB600 64bit support for safety */
9477c58e 1526 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1527 struct pci_dev *p_smbus;
1528 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1529 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1530 NULL);
1531 if (p_smbus) {
1532 if (p_smbus->revision < 0x30)
fb1d8ac2 1533 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1534 pci_dev_put(p_smbus);
1535 }
1536 }
09240cf4 1537
9477c58e
TI		 1538 /* disable 64bit DMA address on some devices */
1539 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1540 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1541 gcap &= ~AZX_GCAP_64OK;
9477c58e 1542 }
396087ea 1543
2ae66c26 1544 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1545 if (align_buffer_size >= 0)
1546 chip->align_buffer_size = !!align_buffer_size;
1547 else {
1548 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1549 chip->align_buffer_size = 0;
1550 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1551 chip->align_buffer_size = 1;
1552 else
1553 chip->align_buffer_size = 1;
1554 }
2ae66c26 1555
cf7aaca8 1556 /* allow 64bit DMA address if supported by H/W */
fb1d8ac2 1557 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1558 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1559 else {
e930438c
YH		 1560 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1561 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1562 }
cf7aaca8 1563
8b6ed8e7
TI		 1564 /* read number of streams from GCAP register instead of using
1565 * hardcoded value
1566 */
1567 chip->capture_streams = (gcap >> 8) & 0x0f;
1568 chip->playback_streams = (gcap >> 12) & 0x0f;
1569 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1570 /* gcap didn't give any info, switching to old method */
1571
1572 switch (chip->driver_type) {
1573 case AZX_DRIVER_ULI:
1574 chip->playback_streams = ULI_NUM_PLAYBACK;
1575 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1576 break;
1577 case AZX_DRIVER_ATIHDMI:
1815b34a 1578 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1579 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1580 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1581 break;
c4da29ca 1582 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1583 default:
1584 chip->playback_streams = ICH6_NUM_PLAYBACK;
1585 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1586 break;
1587 }
07e4ca50 1588 }
8b6ed8e7
TI		 1589 chip->capture_index_offset = 0;
1590 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1591 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1592 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1593 GFP_KERNEL);
927fc866 1594 if (!chip->azx_dev) {
4e76a883 1595 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1596 return -ENOMEM;
07e4ca50
TI		 1597 }
1598
67908994 1599 err = azx_alloc_stream_pages(chip);
81740861 1600 if (err < 0)
a82d51ed 1601 return err;
1da177e4
LT		 1602
1603 /* initialize streams */
1604 azx_init_stream(chip);
1605
1606 /* initialize chip */
cb53c626 1607 azx_init_pci(chip);
e4d9e513
ML		 1608
1609 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1610 haswell_set_bclk(chip);
1611
10e77dda 1612 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1613
1614 /* codec detection */
927fc866 1615 if (!chip->codec_mask) {
4e76a883 1616 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1617 return -ENODEV;
1da177e4
LT		 1618 }
1619
07e4ca50 1620 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1621 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1622 sizeof(card->shortname));
1623 snprintf(card->longname, sizeof(card->longname),
1624 "%s at 0x%lx irq %i",
1625 card->shortname, chip->addr, chip->irq);
07e4ca50 1626
1da177e4 1627 return 0;
1da177e4
LT		 1628}
1629
cb53c626
TI		 1630static void power_down_all_codecs(struct azx *chip)
1631{
83012a7c 1632#ifdef CONFIG_PM
cb53c626
TI		 1633 /* The codecs were powered up in snd_hda_codec_new().
1634 * Now all initialization done, so turn them down if possible
1635 */
1636 struct hda_codec *codec;
1637 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1638 snd_hda_power_down(codec);
1639 }
1640#endif
1641}
1642
97c6a3d1 1643#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1644/* callback from request_firmware_nowait() */
1645static void azx_firmware_cb(const struct firmware *fw, void *context)
1646{
1647 struct snd_card *card = context;
1648 struct azx *chip = card->private_data;
1649 struct pci_dev *pci = chip->pci;
1650
1651 if (!fw) {
4e76a883 1652 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1653 goto error;
1654 }
1655
1656 chip->fw = fw;
1657 if (!chip->disabled) {
1658 /* continue probing */
1659 if (azx_probe_continue(chip))
1660 goto error;
1661 }
1662 return; /* OK */
1663
1664 error:
1665 snd_card_free(card);
1666 pci_set_drvdata(pci, NULL);
1667}
97c6a3d1 1668#endif
5cb543db 1669
40830813
DR		 1670/*
1671 * HDA controller ops.
1672 */
1673
1674/* PCI register access. */
db291e36 1675static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1676{
1677 writel(value, addr);
1678}
1679
db291e36 1680static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1681{
1682 return readl(addr);
1683}
1684
db291e36 1685static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1686{
1687 writew(value, addr);
1688}
1689
db291e36 1690static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1691{
1692 return readw(addr);
1693}
1694
db291e36 1695static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1696{
1697 writeb(value, addr);
1698}
1699
db291e36 1700static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1701{
1702 return readb(addr);
1703}
1704
f46ea609
DR		 1705static int disable_msi_reset_irq(struct azx *chip)
1706{
1707 int err;
1708
1709 free_irq(chip->irq, chip);
1710 chip->irq = -1;
1711 pci_disable_msi(chip->pci);
1712 chip->msi = 0;
1713 err = azx_acquire_irq(chip, 1);
1714 if (err < 0)
1715 return err;
1716
1717 return 0;
1718}
1719
b419b35b
DR		 1720/* DMA page allocation helpers. */
1721static int dma_alloc_pages(struct azx *chip,
1722 int type,
1723 size_t size,
1724 struct snd_dma_buffer *buf)
1725{
1726 int err;
1727
1728 err = snd_dma_alloc_pages(type,
1729 chip->card->dev,
1730 size, buf);
1731 if (err < 0)
1732 return err;
1733 mark_pages_wc(chip, buf, true);
1734 return 0;
1735}
1736
1737static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1738{
1739 mark_pages_wc(chip, buf, false);
1740 snd_dma_free_pages(buf);
1741}
1742
1743static int substream_alloc_pages(struct azx *chip,
1744 struct snd_pcm_substream *substream,
1745 size_t size)
1746{
1747 struct azx_dev *azx_dev = get_azx_dev(substream);
1748 int ret;
1749
1750 mark_runtime_wc(chip, azx_dev, substream, false);
1751 azx_dev->bufsize = 0;
1752 azx_dev->period_bytes = 0;
1753 azx_dev->format_val = 0;
1754 ret = snd_pcm_lib_malloc_pages(substream, size);
1755 if (ret < 0)
1756 return ret;
1757 mark_runtime_wc(chip, azx_dev, substream, true);
1758 return 0;
1759}
1760
1761static int substream_free_pages(struct azx *chip,
1762 struct snd_pcm_substream *substream)
1763{
1764 struct azx_dev *azx_dev = get_azx_dev(substream);
1765 mark_runtime_wc(chip, azx_dev, substream, false);
1766 return snd_pcm_lib_free_pages(substream);
1767}
1768
8769b278
DR		 1769static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1770 struct vm_area_struct *area)
1771{
1772#ifdef CONFIG_X86
1773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774 struct azx *chip = apcm->chip;
3b70bdba 1775 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1776 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1777#endif
1778}
1779
40830813 1780static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1781 .reg_writel = pci_azx_writel,
1782 .reg_readl = pci_azx_readl,
1783 .reg_writew = pci_azx_writew,
1784 .reg_readw = pci_azx_readw,
1785 .reg_writeb = pci_azx_writeb,
1786 .reg_readb = pci_azx_readb,
f46ea609 1787 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1788 .dma_alloc_pages = dma_alloc_pages,
1789 .dma_free_pages = dma_free_pages,
1790 .substream_alloc_pages = substream_alloc_pages,
1791 .substream_free_pages = substream_free_pages,
8769b278 1792 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1793 .position_check = azx_position_check,
40830813
DR		 1794};
1795
e23e7a14
BP		 1796static int azx_probe(struct pci_dev *pci,
1797 const struct pci_device_id *pci_id)
1da177e4 1798{
5aba4f8e 1799 static int dev;
a98f90fd 1800 struct snd_card *card;
9a34af4a 1801 struct hda_intel *hda;
a98f90fd 1802 struct azx *chip;
aad730d0 1803 bool schedule_probe;
927fc866 1804 int err;
1da177e4 1805
5aba4f8e
TI		 1806 if (dev >= SNDRV_CARDS)
1807 return -ENODEV;
1808 if (!enable[dev]) {
1809 dev++;
1810 return -ENOENT;
1811 }
1812
60c5772b
TI		 1813 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1814 0, &card);
e58de7ba 1815 if (err < 0) {
4e76a883 1816 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1817 return err;
1da177e4
LT		 1818 }
1819
40830813
DR		 1820 err = azx_create(card, pci, dev, pci_id->driver_data,
1821 &pci_hda_ops, &chip);
41dda0fd
WF		 1822 if (err < 0)
1823 goto out_free;
421a1252 1824 card->private_data = chip;
9a34af4a 1825 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1826
1827 pci_set_drvdata(pci, card);
1828
1829 err = register_vga_switcheroo(chip);
1830 if (err < 0) {
4e76a883 1831 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1832 goto out_free;
1833 }
1834
1835 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1836 dev_info(card->dev, "VGA controller is disabled\n");
1837 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1838 chip->disabled = true;
1839 }
1840
aad730d0 1841 schedule_probe = !chip->disabled;
1da177e4 1842
4918cdab
TI		 1843#ifdef CONFIG_SND_HDA_PATCH_LOADER
1844 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1845 dev_info(card->dev, "Applying patch firmware '%s'\n",
1846 patch[dev]);
5cb543db
TI		 1847 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1848 &pci->dev, GFP_KERNEL, card,
1849 azx_firmware_cb);
4918cdab
TI		 1850 if (err < 0)
1851 goto out_free;
aad730d0 1852 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1853 }
1854#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1855
aad730d0
TI		 1856#ifndef CONFIG_SND_HDA_I915
1857 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1858 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1859#endif
99a2008d 1860
aad730d0 1861 if (schedule_probe)
9a34af4a 1862 schedule_work(&hda->probe_work);
a82d51ed 1863
a82d51ed 1864 dev++;
88d071fc 1865 if (chip->disabled)
9a34af4a 1866 complete_all(&hda->probe_wait);
a82d51ed
TI		 1867 return 0;
1868
1869out_free:
1870 snd_card_free(card);
1871 return err;
1872}
1873
e62a42ae
DR		 1874/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1875static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1876 [AZX_DRIVER_NVIDIA] = 8,
1877 [AZX_DRIVER_TERA] = 1,
1878};
1879
48c8b0eb 1880static int azx_probe_continue(struct azx *chip)
a82d51ed 1881{
9a34af4a 1882 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1883 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1884 int dev = chip->dev_index;
1885 int err;
1886
99a2008d
WX		 1887 /* Request power well for Haswell HDA controller and codec */
1888 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1889#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1890 err = hda_i915_init();
1891 if (err < 0) {
4e76a883
TI		 1892 dev_err(chip->card->dev,
1893 "Error request power-well from i915\n");
99a2008d
WX		 1894 goto out_free;
1895 }
74b0c2d7
TI		 1896 err = hda_display_power(true);
1897 if (err < 0) {
1898 dev_err(chip->card->dev,
1899 "Cannot turn on display power on i915\n");
1900 goto out_free;
1901 }
c841ad2a 1902#endif
99a2008d
WX		 1903 }
1904
5c90680e
TI		 1905 err = azx_first_init(chip);
1906 if (err < 0)
1907 goto out_free;
1908
2dca0bba
JK		 1909#ifdef CONFIG_SND_HDA_INPUT_BEEP
1910 chip->beep_mode = beep_mode[dev];
1911#endif
1912
1da177e4 1913 /* create codec instances */
e62a42ae
DR		 1914 err = azx_codec_create(chip, model[dev],
1915 azx_max_codecs[chip->driver_type],
1916 power_save_addr);
1917
41dda0fd
WF		 1918 if (err < 0)
1919 goto out_free;
4ea6fbc8 1920#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1921 if (chip->fw) {
1922 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1923 chip->fw->data);
4ea6fbc8
TI		 1924 if (err < 0)
1925 goto out_free;
e39ae856 1926#ifndef CONFIG_PM
4918cdab
TI		 1927 release_firmware(chip->fw); /* no longer needed */
1928 chip->fw = NULL;
e39ae856 1929#endif
4ea6fbc8
TI		 1930 }
1931#endif
10e77dda 1932 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1933 err = azx_codec_configure(chip);
1934 if (err < 0)
1935 goto out_free;
1936 }
1da177e4
LT		 1937
1938 /* create PCM streams */
176d5335 1939 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1940 if (err < 0)
1941 goto out_free;
1da177e4
LT		 1942
1943 /* create mixer controls */
d01ce99f 1944 err = azx_mixer_create(chip);
41dda0fd
WF		 1945 if (err < 0)
1946 goto out_free;
1da177e4 1947
a82d51ed 1948 err = snd_card_register(chip->card);
41dda0fd
WF		 1949 if (err < 0)
1950 goto out_free;
1da177e4 1951
cb53c626
TI		 1952 chip->running = 1;
1953 power_down_all_codecs(chip);
0cbf0098 1954 azx_notifier_register(chip);
65fcd41d 1955 azx_add_card_list(chip);
9a34af4a 1956 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
c67e2228 1957 pm_runtime_put_noidle(&pci->dev);
1da177e4 1958
41dda0fd 1959out_free:
88d071fc 1960 if (err < 0)
9a34af4a
TI		 1961 hda->init_failed = 1;
1962 complete_all(&hda->probe_wait);
41dda0fd 1963 return err;
1da177e4
LT		 1964}
1965
e23e7a14 1966static void azx_remove(struct pci_dev *pci)
1da177e4 1967{
9121947d 1968 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1969
9121947d
TI		 1970 if (card)
1971 snd_card_free(card);
1da177e4
LT		 1972}
1973
1974/* PCI IDs */
6f51f6cf 1975static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1976 /* CPT */
9477c58e 1977 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1979 /* PBG */
9477c58e 1980 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1982 /* Panther Point */
9477c58e 1983 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1985 /* Lynx Point */
1986 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1988 /* 9 Series */
1989 { PCI_DEVICE(0x8086, 0x8ca0),
1990 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1991 /* Wellsburg */
1992 { PCI_DEVICE(0x8086, 0x8d20),
1993 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1994 { PCI_DEVICE(0x8086, 0x8d21),
1995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1996 /* Lynx Point-LP */
1997 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1999 /* Lynx Point-LP */
2000 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2002 /* Wildcat Point-LP */
2003 { PCI_DEVICE(0x8086, 0x9ca0),
2004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2005 /* Sunrise Point */
2006 { PCI_DEVICE(0x8086, 0xa170),
2007 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b4565913
DR		 2008 /* Sunrise Point-LP */
2009 { PCI_DEVICE(0x8086, 0x9d70),
2010 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 2011 /* Haswell */
4a7c516b 2012 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2013 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2014 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2015 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2016 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2017 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2018 /* Broadwell */
2019 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2020 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2021 /* 5 Series/3400 */
2022 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2023 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2024 /* Poulsbo */
9477c58e 2025 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2026 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2027 /* Oaktrail */
09904b95 2028 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2029 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2030 /* BayTrail */
2031 { PCI_DEVICE(0x8086, 0x0f04),
2032 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
f31b2ffc
LY		 2033 /* Braswell */
2034 { PCI_DEVICE(0x8086, 0x2284),
2035 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
645e9035 2036 /* ICH */
8b0bd226 2037 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 2038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2039 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 2040 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 2041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2042 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 2043 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 2044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2045 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 2046 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 2047 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2048 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 2049 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 2050 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2051 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2052 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 2053 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2054 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2055 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 2056 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2057 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 2058 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 2059 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2060 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 2061 /* Generic Intel */
2062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2063 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2064 .class_mask = 0xffffff,
2ae66c26 2065 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 2066 /* ATI SB 450/600/700/800/900 */
2067 { PCI_DEVICE(0x1002, 0x437b),
2068 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2069 { PCI_DEVICE(0x1002, 0x4383),
2070 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2071 /* AMD Hudson */
2072 { PCI_DEVICE(0x1022, 0x780d),
2073 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2074 /* ATI HDMI */
9477c58e
TI		 2075 { PCI_DEVICE(0x1002, 0x793b),
2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2077 { PCI_DEVICE(0x1002, 0x7919),
2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2079 { PCI_DEVICE(0x1002, 0x960f),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0x970f),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0xaa00),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0xaa08),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0xaa10),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0xaa18),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0xaa20),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2093 { PCI_DEVICE(0x1002, 0xaa28),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa30),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa38),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa40),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa48),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2103 { PCI_DEVICE(0x1002, 0xaa50),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa58),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa60),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaa68),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaa80),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2113 { PCI_DEVICE(0x1002, 0xaa88),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0xaa90),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa98),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 2119 { PCI_DEVICE(0x1002, 0x9902),
2120 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaaa0),
2122 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0xaaa8),
2124 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2125 { PCI_DEVICE(0x1002, 0xaab0),
2126 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 2127 /* VIA VT8251/VT8237A */
9477c58e
TI		 2128 { PCI_DEVICE(0x1106, 0x3288),
2129 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2130 /* VIA GFX VT7122/VX900 */
2131 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2132 /* VIA GFX VT6122/VX11 */
2133 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2134 /* SIS966 */
2135 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2136 /* ULI M5461 */
2137 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2138 /* NVIDIA MCP */
0c2fd1bf
TI		 2139 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2140 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2141 .class_mask = 0xffffff,
9477c58e 2142 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2143 /* Teradici */
9477c58e
TI		 2144 { PCI_DEVICE(0x6549, 0x1200),
2145 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2146 { PCI_DEVICE(0x6549, 0x2200),
2147 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2148 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2149 /* CTHDA chips */
2150 { PCI_DEVICE(0x1102, 0x0010),
2151 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2152 { PCI_DEVICE(0x1102, 0x0012),
2153 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2154#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2155 /* the following entry conflicts with snd-ctxfi driver,
2156 * as ctxfi driver mutates from HD-audio to native mode with
2157 * a special command sequence.
2158 */
4e01f54b
TI		 2159 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2160 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2161 .class_mask = 0xffffff,
9477c58e 2162 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2163 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2164#else
2165 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2166 { PCI_DEVICE(0x1102, 0x0009),
2167 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2168 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2169#endif
c563f473
TI		 2170 /* CM8888 */
2171 { PCI_DEVICE(0x13f6, 0x5011),
2172 .driver_data = AZX_DRIVER_CMEDIA |
2173 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB },
e35d4b11
OS		 2174 /* Vortex86MX */
2175 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2176 /* VMware HDAudio */
2177 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2178 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2179 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2180 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2181 .class_mask = 0xffffff,
9477c58e 2182 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2183 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2184 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2185 .class_mask = 0xffffff,
9477c58e 2186 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2187 { 0, }
2188};
2189MODULE_DEVICE_TABLE(pci, azx_ids);
2190
2191/* pci_driver definition */
e9f66d9b 2192static struct pci_driver azx_driver = {
3733e424 2193 .name = KBUILD_MODNAME,
1da177e4
LT		 2194 .id_table = azx_ids,
2195 .probe = azx_probe,
e23e7a14 2196 .remove = azx_remove,
68cb2b55
TI		 2197 .driver = {
2198 .pm = AZX_PM_OPS,
2199 },
1da177e4
LT		 2200};
2201
e9f66d9b 2202module_pci_driver(azx_driver);
Linux kernel - Deliverables
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