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ALSA: hda - remove position_fix=3
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
1da177e4
LT		 48#include <sound/core.h>
49#include <sound/initval.h>
50#include "hda_codec.h"
51
52
5aba4f8e
TI		 53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56static char *model[SNDRV_CARDS];
57static int position_fix[SNDRV_CARDS];
58static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
27346166 59static int single_cmd;
134a11f0 60static int enable_msi;
675f25d4 61static int bdl_pos_adj = 1;
1da177e4 62
5aba4f8e 63module_param_array(index, int, NULL, 0444);
1da177e4 64MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 65module_param_array(id, charp, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 67module_param_array(enable, bool, NULL, 0444);
68MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69module_param_array(model, charp, NULL, 0444);
1da177e4 70MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 71module_param_array(position_fix, int, NULL, 0444);
d01ce99f 72MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 73 "(0 = auto, 1 = none, 2 = POSBUF).");
5aba4f8e 74module_param_array(probe_mask, int, NULL, 0444);
606ad75f 75MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
27346166 76module_param(single_cmd, bool, 0444);
d01ce99f
TI		 77MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
78 "(for debugging only).");
5aba4f8e 79module_param(enable_msi, int, 0444);
134a11f0 80MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
675f25d4
TI		 81module_param(bdl_pos_adj, int, 0644);
82MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset");
606ad75f 83
dee1b66c 84#ifdef CONFIG_SND_HDA_POWER_SAVE
cb53c626 85/* power_save option is defined in hda_codec.c */
1da177e4 86
dee1b66c
TI		 87/* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
89 * wake up.
90 */
91static int power_save_controller = 1;
92module_param(power_save_controller, bool, 0644);
93MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
94#endif
95
1da177e4
LT		 96MODULE_LICENSE("GPL");
97MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
98 "{Intel, ICH6M},"
2f1b3818 99 "{Intel, ICH7},"
f5d40b30 100 "{Intel, ESB2},"
d2981393 101 "{Intel, ICH8},"
f9cc8a8b 102 "{Intel, ICH9},"
c34f5a04 103 "{Intel, ICH10},"
4979bca9 104 "{Intel, SCH},"
fc20a562 105 "{ATI, SB450},"
89be83f8 106 "{ATI, SB600},"
778b6e1b 107 "{ATI, RS600},"
5b15c95f 108 "{ATI, RS690},"
e6db1119
WL		 109 "{ATI, RS780},"
110 "{ATI, R600},"
2797f724
HRK		 111 "{ATI, RV630},"
112 "{ATI, RV610},"
27da1834
WL		 113 "{ATI, RV670},"
114 "{ATI, RV635},"
115 "{ATI, RV620},"
116 "{ATI, RV770},"
fc20a562 117 "{VIA, VT8251},"
47672310 118 "{VIA, VT8237A},"
07e4ca50
TI		 119 "{SiS, SIS966},"
120 "{ULI, M5461}}");
1da177e4
LT		 121MODULE_DESCRIPTION("Intel HDA driver");
122
123#define SFX "hda-intel: "
124
cb53c626 125
1da177e4
LT		 126/*
127 * registers
128 */
129#define ICH6_REG_GCAP 0x00
130#define ICH6_REG_VMIN 0x02
131#define ICH6_REG_VMAJ 0x03
132#define ICH6_REG_OUTPAY 0x04
133#define ICH6_REG_INPAY 0x06
134#define ICH6_REG_GCTL 0x08
135#define ICH6_REG_WAKEEN 0x0c
136#define ICH6_REG_STATESTS 0x0e
137#define ICH6_REG_GSTS 0x10
138#define ICH6_REG_INTCTL 0x20
139#define ICH6_REG_INTSTS 0x24
140#define ICH6_REG_WALCLK 0x30
141#define ICH6_REG_SYNC 0x34
142#define ICH6_REG_CORBLBASE 0x40
143#define ICH6_REG_CORBUBASE 0x44
144#define ICH6_REG_CORBWP 0x48
145#define ICH6_REG_CORBRP 0x4A
146#define ICH6_REG_CORBCTL 0x4c
147#define ICH6_REG_CORBSTS 0x4d
148#define ICH6_REG_CORBSIZE 0x4e
149
150#define ICH6_REG_RIRBLBASE 0x50
151#define ICH6_REG_RIRBUBASE 0x54
152#define ICH6_REG_RIRBWP 0x58
153#define ICH6_REG_RINTCNT 0x5a
154#define ICH6_REG_RIRBCTL 0x5c
155#define ICH6_REG_RIRBSTS 0x5d
156#define ICH6_REG_RIRBSIZE 0x5e
157
158#define ICH6_REG_IC 0x60
159#define ICH6_REG_IR 0x64
160#define ICH6_REG_IRS 0x68
161#define ICH6_IRS_VALID (1<<1)
162#define ICH6_IRS_BUSY (1<<0)
163
164#define ICH6_REG_DPLBASE 0x70
165#define ICH6_REG_DPUBASE 0x74
166#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
167
168/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
169enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
170
171/* stream register offsets from stream base */
172#define ICH6_REG_SD_CTL 0x00
173#define ICH6_REG_SD_STS 0x03
174#define ICH6_REG_SD_LPIB 0x04
175#define ICH6_REG_SD_CBL 0x08
176#define ICH6_REG_SD_LVI 0x0c
177#define ICH6_REG_SD_FIFOW 0x0e
178#define ICH6_REG_SD_FIFOSIZE 0x10
179#define ICH6_REG_SD_FORMAT 0x12
180#define ICH6_REG_SD_BDLPL 0x18
181#define ICH6_REG_SD_BDLPU 0x1c
182
183/* PCI space */
184#define ICH6_PCIREG_TCSEL 0x44
185
186/*
187 * other constants
188 */
189
190/* max number of SDs */
07e4ca50 191/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 192#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 193#define ICH6_NUM_PLAYBACK 4
194
195/* ULI has 6 playback and 5 capture */
07e4ca50 196#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 197#define ULI_NUM_PLAYBACK 6
198
778b6e1b 199/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 200#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 201#define ATIHDMI_NUM_PLAYBACK 1
202
f269002e
KY		 203/* TERA has 4 playback and 3 capture */
204#define TERA_NUM_CAPTURE 3
205#define TERA_NUM_PLAYBACK 4
206
07e4ca50
TI		 207/* this number is statically defined for simplicity */
208#define MAX_AZX_DEV 16
209
1da177e4 210/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 211#define BDL_SIZE 4096
212#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
213#define AZX_MAX_FRAG 32
1da177e4
LT		 214/* max buffer size - no h/w limit, you can increase as you like */
215#define AZX_MAX_BUF_SIZE (1024*1024*1024)
216/* max number of PCM devics per card */
7ba72ba1 217#define AZX_MAX_PCMS 8
1da177e4
LT		 218
219/* RIRB int mask: overrun[2], response[0] */
220#define RIRB_INT_RESPONSE 0x01
221#define RIRB_INT_OVERRUN 0x04
222#define RIRB_INT_MASK 0x05
223
224/* STATESTS int mask: SD2,SD1,SD0 */
19a982b6 225#define AZX_MAX_CODECS 3
1da177e4 226#define STATESTS_INT_MASK 0x07
1da177e4
LT		 227
228/* SD_CTL bits */
229#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
230#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 231#define SD_CTL_STRIPE (3 << 16) /* stripe control */
232#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
233#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 234#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
235#define SD_CTL_STREAM_TAG_SHIFT 20
236
237/* SD_CTL and SD_STS */
238#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
239#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
240#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 241#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
242 SD_INT_COMPLETE)
1da177e4
LT		 243
244/* SD_STS */
245#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
246
247/* INTCTL and INTSTS */
d01ce99f
TI		 248#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
249#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
250#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 251
41e2fce4
M		 252/* GCTL unsolicited response enable bit */
253#define ICH6_GCTL_UREN (1<<8)
254
1da177e4
LT		 255/* GCTL reset bit */
256#define ICH6_GCTL_RESET (1<<0)
257
258/* CORB/RIRB control, read/write pointer */
259#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
260#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
261#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
262/* below are so far hardcoded - should read registers in future */
263#define ICH6_MAX_CORB_ENTRIES 256
264#define ICH6_MAX_RIRB_ENTRIES 256
265
c74db86b
TI		 266/* position fix mode */
267enum {
0be3b5d3 268 POS_FIX_AUTO,
d2e1c973 269 POS_FIX_LPIB,
0be3b5d3 270 POS_FIX_POSBUF,
c74db86b 271};
1da177e4 272
f5d40b30 273/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 274#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
275#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
276
da3fca21
V		 277/* Defines for Nvidia HDA support */
278#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
279#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 280
90a5ad52
TI		 281/* Defines for Intel SCH HDA snoop control */
282#define INTEL_SCH_HDA_DEVC 0x78
283#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
284
285
1da177e4
LT		 286/*
287 */
288
a98f90fd 289struct azx_dev {
4ce107b9 290 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 291 u32 *posbuf; /* position buffer pointer */
1da177e4 292
d01ce99f 293 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 294 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 295 unsigned int frags; /* number for period in the play buffer */
296 unsigned int fifo_size; /* FIFO size */
1da177e4 297
d01ce99f 298 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 299
d01ce99f 300 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 301
302 /* pcm support */
d01ce99f
TI		 303 struct snd_pcm_substream *substream; /* assigned substream,
304 * set in PCM open
305 */
306 unsigned int format_val; /* format value to be set in the
307 * controller and the codec
308 */
1da177e4
LT		 309 unsigned char stream_tag; /* assigned stream */
310 unsigned char index; /* stream index */
311
927fc866
PM		 312 unsigned int opened :1;
313 unsigned int running :1;
675f25d4
TI		 314 unsigned int irq_pending :1;
315 unsigned int irq_ignore :1;
1da177e4
LT		 316};
317
318/* CORB/RIRB */
a98f90fd 319struct azx_rb {
1da177e4
LT		 320 u32 *buf; /* CORB/RIRB buffer
321 * Each CORB entry is 4byte, RIRB is 8byte
322 */
323 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
324 /* for RIRB */
325 unsigned short rp, wp; /* read/write pointers */
326 int cmds; /* number of pending requests */
327 u32 res; /* last read value */
328};
329
a98f90fd
TI		 330struct azx {
331 struct snd_card *card;
1da177e4
LT		 332 struct pci_dev *pci;
333
07e4ca50
TI		 334 /* chip type specific */
335 int driver_type;
336 int playback_streams;
337 int playback_index_offset;
338 int capture_streams;
339 int capture_index_offset;
340 int num_streams;
341
1da177e4
LT		 342 /* pci resources */
343 unsigned long addr;
344 void __iomem *remap_addr;
345 int irq;
346
347 /* locks */
348 spinlock_t reg_lock;
62932df8 349 struct mutex open_mutex;
1da177e4 350
07e4ca50 351 /* streams (x num_streams) */
a98f90fd 352 struct azx_dev *azx_dev;
1da177e4
LT		 353
354 /* PCM */
a98f90fd 355 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 356
357 /* HD codec */
358 unsigned short codec_mask;
359 struct hda_bus *bus;
360
361 /* CORB/RIRB */
a98f90fd
TI		 362 struct azx_rb corb;
363 struct azx_rb rirb;
1da177e4 364
4ce107b9 365 /* CORB/RIRB and position buffers */
1da177e4
LT		 366 struct snd_dma_buffer rb;
367 struct snd_dma_buffer posbuf;
c74db86b
TI		 368
369 /* flags */
370 int position_fix;
cb53c626 371 unsigned int running :1;
927fc866
PM		 372 unsigned int initialized :1;
373 unsigned int single_cmd :1;
374 unsigned int polling_mode :1;
68e7fffc 375 unsigned int msi :1;
43bbb6cc
TI		 376
377 /* for debugging */
378 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 379
380 /* for pending irqs */
381 struct work_struct irq_pending_work;
1da177e4
LT		 382};
383
07e4ca50
TI		 384/* driver types */
385enum {
386 AZX_DRIVER_ICH,
4979bca9 387 AZX_DRIVER_SCH,
07e4ca50 388 AZX_DRIVER_ATI,
778b6e1b 389 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 390 AZX_DRIVER_VIA,
391 AZX_DRIVER_SIS,
392 AZX_DRIVER_ULI,
da3fca21 393 AZX_DRIVER_NVIDIA,
f269002e 394 AZX_DRIVER_TERA,
07e4ca50
TI		 395};
396
397static char *driver_short_names[] __devinitdata = {
398 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 399 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 400 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 401 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 402 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
403 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 404 [AZX_DRIVER_ULI] = "HDA ULI M5461",
405 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 406 [AZX_DRIVER_TERA] = "HDA Teradici",
07e4ca50
TI		 407};
408
1da177e4
LT		 409/*
410 * macros for easy use
411 */
412#define azx_writel(chip,reg,value) \
413 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
414#define azx_readl(chip,reg) \
415 readl((chip)->remap_addr + ICH6_REG_##reg)
416#define azx_writew(chip,reg,value) \
417 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
418#define azx_readw(chip,reg) \
419 readw((chip)->remap_addr + ICH6_REG_##reg)
420#define azx_writeb(chip,reg,value) \
421 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
422#define azx_readb(chip,reg) \
423 readb((chip)->remap_addr + ICH6_REG_##reg)
424
425#define azx_sd_writel(dev,reg,value) \
426 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
427#define azx_sd_readl(dev,reg) \
428 readl((dev)->sd_addr + ICH6_REG_##reg)
429#define azx_sd_writew(dev,reg,value) \
430 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
431#define azx_sd_readw(dev,reg) \
432 readw((dev)->sd_addr + ICH6_REG_##reg)
433#define azx_sd_writeb(dev,reg,value) \
434 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
435#define azx_sd_readb(dev,reg) \
436 readb((dev)->sd_addr + ICH6_REG_##reg)
437
438/* for pcm support */
a98f90fd 439#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4
LT		 440
441/* Get the upper 32bit of the given dma_addr_t
442 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
443 */
444#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
445
68e7fffc 446static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 447
448/*
449 * Interface for HD codec
450 */
451
1da177e4
LT		 452/*
453 * CORB / RIRB interface
454 */
a98f90fd 455static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 456{
457 int err;
458
459 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 460 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
461 snd_dma_pci_data(chip->pci),
1da177e4
LT		 462 PAGE_SIZE, &chip->rb);
463 if (err < 0) {
464 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
465 return err;
466 }
467 return 0;
468}
469
a98f90fd 470static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 471{
472 /* CORB set up */
473 chip->corb.addr = chip->rb.addr;
474 chip->corb.buf = (u32 *)chip->rb.area;
475 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
476 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
477
07e4ca50
TI		 478 /* set the corb size to 256 entries (ULI requires explicitly) */
479 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 480 /* set the corb write pointer to 0 */
481 azx_writew(chip, CORBWP, 0);
482 /* reset the corb hw read pointer */
483 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
484 /* enable corb dma */
485 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
486
487 /* RIRB set up */
488 chip->rirb.addr = chip->rb.addr + 2048;
489 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
490 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
491 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
492
07e4ca50
TI		 493 /* set the rirb size to 256 entries (ULI requires explicitly) */
494 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 495 /* reset the rirb hw write pointer */
496 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
497 /* set N=1, get RIRB response interrupt for new entry */
498 azx_writew(chip, RINTCNT, 1);
499 /* enable rirb dma and response irq */
1da177e4 500 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 501 chip->rirb.rp = chip->rirb.cmds = 0;
502}
503
a98f90fd 504static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 505{
506 /* disable ringbuffer DMAs */
507 azx_writeb(chip, RIRBCTL, 0);
508 azx_writeb(chip, CORBCTL, 0);
509}
510
511/* send a command */
43bbb6cc 512static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 513{
a98f90fd 514 struct azx *chip = codec->bus->private_data;
1da177e4 515 unsigned int wp;
1da177e4
LT		 516
517 /* add command to corb */
518 wp = azx_readb(chip, CORBWP);
519 wp++;
520 wp %= ICH6_MAX_CORB_ENTRIES;
521
522 spin_lock_irq(&chip->reg_lock);
523 chip->rirb.cmds++;
524 chip->corb.buf[wp] = cpu_to_le32(val);
525 azx_writel(chip, CORBWP, wp);
526 spin_unlock_irq(&chip->reg_lock);
527
528 return 0;
529}
530
531#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
532
533/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 534static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 535{
536 unsigned int rp, wp;
537 u32 res, res_ex;
538
539 wp = azx_readb(chip, RIRBWP);
540 if (wp == chip->rirb.wp)
541 return;
542 chip->rirb.wp = wp;
543
544 while (chip->rirb.rp != wp) {
545 chip->rirb.rp++;
546 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
547
548 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
549 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
550 res = le32_to_cpu(chip->rirb.buf[rp]);
551 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
552 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
553 else if (chip->rirb.cmds) {
1da177e4 554 chip->rirb.res = res;
2add9b92
TI		 555 smp_wmb();
556 chip->rirb.cmds--;
1da177e4
LT		 557 }
558 }
559}
560
561/* receive a response */
111d3af5 562static unsigned int azx_rirb_get_response(struct hda_codec *codec)
1da177e4 563{
a98f90fd 564 struct azx *chip = codec->bus->private_data;
5c79b1f8 565 unsigned long timeout;
1da177e4 566
5c79b1f8
TI		 567 again:
568 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 569 for (;;) {
e96224ae
TI		 570 if (chip->polling_mode) {
571 spin_lock_irq(&chip->reg_lock);
572 azx_update_rirb(chip);
573 spin_unlock_irq(&chip->reg_lock);
574 }
2add9b92
TI		 575 if (!chip->rirb.cmds) {
576 smp_rmb();
5c79b1f8 577 return chip->rirb.res; /* the last value */
2add9b92 578 }
28a0d9df
TI		 579 if (time_after(jiffies, timeout))
580 break;
52987656
TI		 581 if (codec->bus->needs_damn_long_delay)
582 msleep(2); /* temporary workaround */
583 else {
584 udelay(10);
585 cond_resched();
586 }
28a0d9df 587 }
5c79b1f8 588
68e7fffc
TI		 589 if (chip->msi) {
590 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
43bbb6cc 591 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 592 free_irq(chip->irq, chip);
593 chip->irq = -1;
594 pci_disable_msi(chip->pci);
595 chip->msi = 0;
596 if (azx_acquire_irq(chip, 1) < 0)
597 return -1;
598 goto again;
599 }
600
5c79b1f8
TI		 601 if (!chip->polling_mode) {
602 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 603 "switching to polling mode: last cmd=0x%08x\n",
604 chip->last_cmd);
5c79b1f8
TI		 605 chip->polling_mode = 1;
606 goto again;
1da177e4 607 }
5c79b1f8
TI		 608
609 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 610 "switching to single_cmd mode: last cmd=0x%08x\n",
611 chip->last_cmd);
5c79b1f8
TI		 612 chip->rirb.rp = azx_readb(chip, RIRBWP);
613 chip->rirb.cmds = 0;
614 /* switch to single_cmd mode */
615 chip->single_cmd = 1;
616 azx_free_cmd_io(chip);
617 return -1;
1da177e4
LT		 618}
619
1da177e4
LT		 620/*
621 * Use the single immediate command instead of CORB/RIRB for simplicity
622 *
623 * Note: according to Intel, this is not preferred use. The command was
624 * intended for the BIOS only, and may get confused with unsolicited
625 * responses. So, we shouldn't use it for normal operation from the
626 * driver.
627 * I left the codes, however, for debugging/testing purposes.
628 */
629
1da177e4 630/* send a command */
43bbb6cc 631static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 632{
a98f90fd 633 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 634 int timeout = 50;
635
1da177e4
LT		 636 while (timeout--) {
637 /* check ICB busy bit */
d01ce99f 638 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 639 /* Clear IRV valid bit */
d01ce99f
TI		 640 azx_writew(chip, IRS, azx_readw(chip, IRS) |
641 ICH6_IRS_VALID);
1da177e4 642 azx_writel(chip, IC, val);
d01ce99f
TI		 643 azx_writew(chip, IRS, azx_readw(chip, IRS) |
644 ICH6_IRS_BUSY);
1da177e4
LT		 645 return 0;
646 }
647 udelay(1);
648 }
1cfd52bc
MB		 649 if (printk_ratelimit())
650 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
651 azx_readw(chip, IRS), val);
1da177e4
LT		 652 return -EIO;
653}
654
655/* receive a response */
27346166 656static unsigned int azx_single_get_response(struct hda_codec *codec)
1da177e4 657{
a98f90fd 658 struct azx *chip = codec->bus->private_data;
1da177e4
LT		 659 int timeout = 50;
660
661 while (timeout--) {
662 /* check IRV busy bit */
663 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
664 return azx_readl(chip, IR);
665 udelay(1);
666 }
1cfd52bc
MB		 667 if (printk_ratelimit())
668 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
669 azx_readw(chip, IRS));
1da177e4
LT		 670 return (unsigned int)-1;
671}
672
111d3af5
TI		 673/*
674 * The below are the main callbacks from hda_codec.
675 *
676 * They are just the skeleton to call sub-callbacks according to the
677 * current setting of chip->single_cmd.
678 */
679
680/* send a command */
681static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
682 int direct, unsigned int verb,
683 unsigned int para)
684{
685 struct azx *chip = codec->bus->private_data;
43bbb6cc
TI		 686 u32 val;
687
688 val = (u32)(codec->addr & 0x0f) << 28;
689 val |= (u32)direct << 27;
690 val |= (u32)nid << 20;
691 val |= verb << 8;
692 val |= para;
693 chip->last_cmd = val;
694
111d3af5 695 if (chip->single_cmd)
43bbb6cc 696 return azx_single_send_cmd(codec, val);
111d3af5 697 else
43bbb6cc 698 return azx_corb_send_cmd(codec, val);
111d3af5
TI		 699}
700
701/* get a response */
702static unsigned int azx_get_response(struct hda_codec *codec)
703{
704 struct azx *chip = codec->bus->private_data;
705 if (chip->single_cmd)
706 return azx_single_get_response(codec);
707 else
708 return azx_rirb_get_response(codec);
709}
710
cb53c626
TI		 711#ifdef CONFIG_SND_HDA_POWER_SAVE
712static void azx_power_notify(struct hda_codec *codec);
713#endif
111d3af5 714
1da177e4 715/* reset codec link */
a98f90fd 716static int azx_reset(struct azx *chip)
1da177e4
LT		 717{
718 int count;
719
e8a7f136
DT		 720 /* clear STATESTS */
721 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
722
1da177e4
LT		 723 /* reset controller */
724 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
725
726 count = 50;
727 while (azx_readb(chip, GCTL) && --count)
728 msleep(1);
729
730 /* delay for >= 100us for codec PLL to settle per spec
731 * Rev 0.9 section 5.5.1
732 */
733 msleep(1);
734
735 /* Bring controller out of reset */
736 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
737
738 count = 50;
927fc866 739 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 740 msleep(1);
741
927fc866 742 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 743 msleep(1);
744
745 /* check to see if controller is ready */
927fc866 746 if (!azx_readb(chip, GCTL)) {
1da177e4
LT		 747 snd_printd("azx_reset: controller not ready!\n");
748 return -EBUSY;
749 }
750
41e2fce4
M		 751 /* Accept unsolicited responses */
752 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
753
1da177e4 754 /* detect codecs */
927fc866 755 if (!chip->codec_mask) {
1da177e4
LT		 756 chip->codec_mask = azx_readw(chip, STATESTS);
757 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
758 }
759
760 return 0;
761}
762
763
764/*
765 * Lowlevel interface
766 */
767
768/* enable interrupts */
a98f90fd 769static void azx_int_enable(struct azx *chip)
1da177e4
LT		 770{
771 /* enable controller CIE and GIE */
772 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
773 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
774}
775
776/* disable interrupts */
a98f90fd 777static void azx_int_disable(struct azx *chip)
1da177e4
LT		 778{
779 int i;
780
781 /* disable interrupts in stream descriptor */
07e4ca50 782 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 783 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 784 azx_sd_writeb(azx_dev, SD_CTL,
785 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
786 }
787
788 /* disable SIE for all streams */
789 azx_writeb(chip, INTCTL, 0);
790
791 /* disable controller CIE and GIE */
792 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
793 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
794}
795
796/* clear interrupts */
a98f90fd 797static void azx_int_clear(struct azx *chip)
1da177e4
LT		 798{
799 int i;
800
801 /* clear stream status */
07e4ca50 802 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 803 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 804 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
805 }
806
807 /* clear STATESTS */
808 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
809
810 /* clear rirb status */
811 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
812
813 /* clear int status */
814 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
815}
816
817/* start a stream */
a98f90fd 818static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 819{
820 /* enable SIE */
821 azx_writeb(chip, INTCTL,
822 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
823 /* set DMA start and interrupt mask */
824 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
825 SD_CTL_DMA_START | SD_INT_MASK);
826}
827
828/* stop a stream */
a98f90fd 829static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 830{
831 /* stop DMA */
832 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
833 ~(SD_CTL_DMA_START | SD_INT_MASK));
834 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
835 /* disable SIE */
836 azx_writeb(chip, INTCTL,
837 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
838}
839
840
841/*
cb53c626 842 * reset and start the controller registers
1da177e4 843 */
a98f90fd 844static void azx_init_chip(struct azx *chip)
1da177e4 845{
cb53c626
TI		 846 if (chip->initialized)
847 return;
1da177e4
LT		 848
849 /* reset controller */
850 azx_reset(chip);
851
852 /* initialize interrupts */
853 azx_int_clear(chip);
854 azx_int_enable(chip);
855
856 /* initialize the codec command I/O */
927fc866 857 if (!chip->single_cmd)
27346166 858 azx_init_cmd_io(chip);
1da177e4 859
0be3b5d3
TI		 860 /* program the position buffer */
861 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
862 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 863
cb53c626
TI		 864 chip->initialized = 1;
865}
866
867/*
868 * initialize the PCI registers
869 */
870/* update bits in a PCI register byte */
871static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
872 unsigned char mask, unsigned char val)
873{
874 unsigned char data;
875
876 pci_read_config_byte(pci, reg, &data);
877 data &= ~mask;
878 data |= (val & mask);
879 pci_write_config_byte(pci, reg, data);
880}
881
882static void azx_init_pci(struct azx *chip)
883{
90a5ad52
TI		 884 unsigned short snoop;
885
cb53c626
TI		 886 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
887 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
888 * Ensuring these bits are 0 clears playback static on some HD Audio
889 * codecs
890 */
891 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
892
da3fca21
V		 893 switch (chip->driver_type) {
894 case AZX_DRIVER_ATI:
895 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 896 update_pci_byte(chip->pci,
897 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
898 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 899 break;
900 case AZX_DRIVER_NVIDIA:
901 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 902 update_pci_byte(chip->pci,
903 NVIDIA_HDA_TRANSREG_ADDR,
904 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
da3fca21 905 break;
90a5ad52
TI		 906 case AZX_DRIVER_SCH:
907 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
908 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
909 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
910 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
911 pci_read_config_word(chip->pci,
912 INTEL_SCH_HDA_DEVC, &snoop);
913 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
914 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
915 ? "Failed" : "OK");
916 }
917 break;
918
da3fca21 919 }
1da177e4
LT		 920}
921
922
9ad593f6
TI		 923static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
924
1da177e4
LT		 925/*
926 * interrupt handler
927 */
7d12e780 928static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 929{
a98f90fd
TI		 930 struct azx *chip = dev_id;
931 struct azx_dev *azx_dev;
1da177e4
LT		 932 u32 status;
933 int i;
934
935 spin_lock(&chip->reg_lock);
936
937 status = azx_readl(chip, INTSTS);
938 if (status == 0) {
939 spin_unlock(&chip->reg_lock);
940 return IRQ_NONE;
941 }
942
07e4ca50 943 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 944 azx_dev = &chip->azx_dev[i];
945 if (status & azx_dev->sd_int_sta_mask) {
946 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 947 if (!azx_dev->substream || !azx_dev->running)
948 continue;
675f25d4
TI		 949 /* ignore the first dummy IRQ (due to pos_adj) */
950 if (azx_dev->irq_ignore) {
951 azx_dev->irq_ignore = 0;
952 continue;
953 }
9ad593f6
TI		 954 /* check whether this IRQ is really acceptable */
955 if (azx_position_ok(chip, azx_dev)) {
956 azx_dev->irq_pending = 0;
1da177e4
LT		 957 spin_unlock(&chip->reg_lock);
958 snd_pcm_period_elapsed(azx_dev->substream);
959 spin_lock(&chip->reg_lock);
9ad593f6
TI		 960 } else {
961 /* bogus IRQ, process it later */
962 azx_dev->irq_pending = 1;
963 schedule_work(&chip->irq_pending_work);
1da177e4
LT		 964 }
965 }
966 }
967
968 /* clear rirb int */
969 status = azx_readb(chip, RIRBSTS);
970 if (status & RIRB_INT_MASK) {
d01ce99f 971 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 972 azx_update_rirb(chip);
973 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
974 }
975
976#if 0
977 /* clear state status int */
978 if (azx_readb(chip, STATESTS) & 0x04)
979 azx_writeb(chip, STATESTS, 0x04);
980#endif
981 spin_unlock(&chip->reg_lock);
982
983 return IRQ_HANDLED;
984}
985
986
675f25d4
TI		 987/*
988 * set up a BDL entry
989 */
990static int setup_bdle(struct snd_pcm_substream *substream,
991 struct azx_dev *azx_dev, u32 **bdlp,
992 int ofs, int size, int with_ioc)
993{
994 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
995 u32 *bdl = *bdlp;
996
997 while (size > 0) {
998 dma_addr_t addr;
999 int chunk;
1000
1001 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1002 return -EINVAL;
1003
1004 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1005 /* program the address field of the BDL entry */
1006 bdl[0] = cpu_to_le32((u32)addr);
1007 bdl[1] = cpu_to_le32(upper_32bit(addr));
1008 /* program the size field of the BDL entry */
1009 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1010 if (size < chunk)
1011 chunk = size;
1012 bdl[2] = cpu_to_le32(chunk);
1013 /* program the IOC to enable interrupt
1014 * only when the whole fragment is processed
1015 */
1016 size -= chunk;
1017 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1018 bdl += 4;
1019 azx_dev->frags++;
1020 ofs += chunk;
1021 }
1022 *bdlp = bdl;
1023 return ofs;
1024}
1025
1da177e4
LT		 1026/*
1027 * set up BDL entries
1028 */
4ce107b9
TI		 1029static int azx_setup_periods(struct snd_pcm_substream *substream,
1030 struct azx_dev *azx_dev)
1da177e4 1031{
4ce107b9
TI		 1032 u32 *bdl;
1033 int i, ofs, periods, period_bytes;
675f25d4 1034 int pos_adj = 0;
1da177e4
LT		 1035
1036 /* reset BDL address */
1037 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1038 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1039
4ce107b9 1040 period_bytes = snd_pcm_lib_period_bytes(substream);
9ad593f6 1041 azx_dev->period_bytes = period_bytes;
4ce107b9
TI		 1042 periods = azx_dev->bufsize / period_bytes;
1043
1da177e4 1044 /* program the initial BDL entries */
4ce107b9
TI		 1045 bdl = (u32 *)azx_dev->bdl.area;
1046 ofs = 0;
1047 azx_dev->frags = 0;
675f25d4
TI		 1048 azx_dev->irq_ignore = 0;
1049 if (bdl_pos_adj > 0) {
1050 struct snd_pcm_runtime *runtime = substream->runtime;
1051 pos_adj = (bdl_pos_adj * runtime->rate + 47999) / 48000;
1052 if (!pos_adj)
1053 pos_adj = 1;
1054 pos_adj = frames_to_bytes(runtime, pos_adj);
1055 if (pos_adj >= period_bytes) {
1056 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1057 bdl_pos_adj);
1058 pos_adj = 0;
1059 } else {
1060 ofs = setup_bdle(substream, azx_dev,
1061 &bdl, ofs, pos_adj, 1);
1062 if (ofs < 0)
1063 goto error;
1064 azx_dev->irq_ignore = 1;
4ce107b9 1065 }
675f25d4
TI		 1066 }
1067 for (i = 0; i < periods; i++) {
1068 if (i == periods - 1 && pos_adj)
1069 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1070 period_bytes - pos_adj, 0);
1071 else
1072 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1073 period_bytes, 1);
1074 if (ofs < 0)
1075 goto error;
1da177e4 1076 }
4ce107b9 1077 return 0;
675f25d4
TI		 1078
1079 error:
1080 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1081 azx_dev->bufsize, period_bytes);
1082 /* reset */
1083 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1084 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1085 return -EINVAL;
1da177e4
LT		 1086}
1087
1088/*
1089 * set up the SD for streaming
1090 */
a98f90fd 1091static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1092{
1093 unsigned char val;
1094 int timeout;
1095
1096 /* make sure the run bit is zero for SD */
d01ce99f
TI		 1097 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1098 ~SD_CTL_DMA_START);
1da177e4 1099 /* reset stream */
d01ce99f
TI		 1100 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1101 SD_CTL_STREAM_RESET);
1da177e4
LT		 1102 udelay(3);
1103 timeout = 300;
1104 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1105 --timeout)
1106 ;
1107 val &= ~SD_CTL_STREAM_RESET;
1108 azx_sd_writeb(azx_dev, SD_CTL, val);
1109 udelay(3);
1110
1111 timeout = 300;
1112 /* waiting for hardware to report that the stream is out of reset */
1113 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1114 --timeout)
1115 ;
1116
1117 /* program the stream_tag */
1118 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1119 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1120 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1121
1122 /* program the length of samples in cyclic buffer */
1123 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1124
1125 /* program the stream format */
1126 /* this value needs to be the same as the one programmed */
1127 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1128
1129 /* program the stream LVI (last valid index) of the BDL */
1130 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1131
1132 /* program the BDL address */
1133 /* lower BDL address */
4ce107b9 1134 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1135 /* upper BDL address */
4ce107b9 1136 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1da177e4 1137
0be3b5d3 1138 /* enable the position buffer */
ee9d6b9a
TI		 1139 if (chip->position_fix == POS_FIX_POSBUF ||
1140 chip->position_fix == POS_FIX_AUTO) {
1141 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1142 azx_writel(chip, DPLBASE,
1143 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1144 }
c74db86b 1145
1da177e4 1146 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1147 azx_sd_writel(azx_dev, SD_CTL,
1148 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1149
1150 return 0;
1151}
1152
1153
1154/*
1155 * Codec initialization
1156 */
1157
a9995a35 1158static unsigned int azx_max_codecs[] __devinitdata = {
607d982b 1159 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
90a5ad52 1160 [AZX_DRIVER_SCH] = 3,
a9995a35
TI		 1161 [AZX_DRIVER_ATI] = 4,
1162 [AZX_DRIVER_ATIHDMI] = 4,
1163 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1164 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1165 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1166 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
f269002e 1167 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1168};
1169
5aba4f8e
TI		 1170static int __devinit azx_codec_create(struct azx *chip, const char *model,
1171 unsigned int codec_probe_mask)
1da177e4
LT		 1172{
1173 struct hda_bus_template bus_temp;
bccad14e 1174 int c, codecs, audio_codecs, err;
1da177e4
LT		 1175
1176 memset(&bus_temp, 0, sizeof(bus_temp));
1177 bus_temp.private_data = chip;
1178 bus_temp.modelname = model;
1179 bus_temp.pci = chip->pci;
111d3af5
TI		 1180 bus_temp.ops.command = azx_send_cmd;
1181 bus_temp.ops.get_response = azx_get_response;
cb53c626
TI		 1182#ifdef CONFIG_SND_HDA_POWER_SAVE
1183 bus_temp.ops.pm_notify = azx_power_notify;
1184#endif
1da177e4 1185
d01ce99f
TI		 1186 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1187 if (err < 0)
1da177e4
LT		 1188 return err;
1189
bccad14e 1190 codecs = audio_codecs = 0;
19a982b6 1191 for (c = 0; c < AZX_MAX_CODECS; c++) {
5aba4f8e 1192 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
bccad14e
TI		 1193 struct hda_codec *codec;
1194 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1195 if (err < 0)
1196 continue;
1197 codecs++;
bccad14e
TI		 1198 if (codec->afg)
1199 audio_codecs++;
1da177e4
LT		 1200 }
1201 }
bccad14e 1202 if (!audio_codecs) {
19a982b6
TI		 1203 /* probe additional slots if no codec is found */
1204 for (; c < azx_max_codecs[chip->driver_type]; c++) {
5aba4f8e 1205 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
19a982b6
TI		 1206 err = snd_hda_codec_new(chip->bus, c, NULL);
1207 if (err < 0)
1208 continue;
1209 codecs++;
1210 }
1211 }
1212 }
1213 if (!codecs) {
1da177e4
LT		 1214 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1215 return -ENXIO;
1216 }
1217
1218 return 0;
1219}
1220
1221
1222/*
1223 * PCM support
1224 */
1225
1226/* assign a stream for the PCM */
a98f90fd 1227static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1228{
07e4ca50
TI		 1229 int dev, i, nums;
1230 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1231 dev = chip->playback_index_offset;
1232 nums = chip->playback_streams;
1233 } else {
1234 dev = chip->capture_index_offset;
1235 nums = chip->capture_streams;
1236 }
1237 for (i = 0; i < nums; i++, dev++)
d01ce99f 1238 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1239 chip->azx_dev[dev].opened = 1;
1240 return &chip->azx_dev[dev];
1241 }
1242 return NULL;
1243}
1244
1245/* release the assigned stream */
a98f90fd 1246static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1247{
1248 azx_dev->opened = 0;
1249}
1250
a98f90fd 1251static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1252 .info = (SNDRV_PCM_INFO_MMAP |
1253 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1254 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1255 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1256 /* No full-resume yet implemented */
1257 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1258 SNDRV_PCM_INFO_PAUSE |
1259 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1260 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1261 .rates = SNDRV_PCM_RATE_48000,
1262 .rate_min = 48000,
1263 .rate_max = 48000,
1264 .channels_min = 2,
1265 .channels_max = 2,
1266 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1267 .period_bytes_min = 128,
1268 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1269 .periods_min = 2,
1270 .periods_max = AZX_MAX_FRAG,
1271 .fifo_size = 0,
1272};
1273
1274struct azx_pcm {
a98f90fd 1275 struct azx *chip;
1da177e4
LT		 1276 struct hda_codec *codec;
1277 struct hda_pcm_stream *hinfo[2];
1278};
1279
a98f90fd 1280static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1281{
1282 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1283 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1284 struct azx *chip = apcm->chip;
1285 struct azx_dev *azx_dev;
1286 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1287 unsigned long flags;
1288 int err;
1289
62932df8 1290 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1291 azx_dev = azx_assign_device(chip, substream->stream);
1292 if (azx_dev == NULL) {
62932df8 1293 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1294 return -EBUSY;
1295 }
1296 runtime->hw = azx_pcm_hw;
1297 runtime->hw.channels_min = hinfo->channels_min;
1298 runtime->hw.channels_max = hinfo->channels_max;
1299 runtime->hw.formats = hinfo->formats;
1300 runtime->hw.rates = hinfo->rates;
1301 snd_pcm_limit_hw_rates(runtime);
1302 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1303 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1304 128);
1305 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1306 128);
cb53c626 1307 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1308 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1309 if (err < 0) {
1da177e4 1310 azx_release_device(azx_dev);
cb53c626 1311 snd_hda_power_down(apcm->codec);
62932df8 1312 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1313 return err;
1314 }
1315 spin_lock_irqsave(&chip->reg_lock, flags);
1316 azx_dev->substream = substream;
1317 azx_dev->running = 0;
1318 spin_unlock_irqrestore(&chip->reg_lock, flags);
1319
1320 runtime->private_data = azx_dev;
850f0e52 1321 snd_pcm_set_sync(substream);
62932df8 1322 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1323 return 0;
1324}
1325
a98f90fd 1326static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1327{
1328 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1329 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1330 struct azx *chip = apcm->chip;
1331 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1332 unsigned long flags;
1333
62932df8 1334 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1335 spin_lock_irqsave(&chip->reg_lock, flags);
1336 azx_dev->substream = NULL;
1337 azx_dev->running = 0;
1338 spin_unlock_irqrestore(&chip->reg_lock, flags);
1339 azx_release_device(azx_dev);
1340 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1341 snd_hda_power_down(apcm->codec);
62932df8 1342 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1343 return 0;
1344}
1345
d01ce99f
TI		 1346static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1347 struct snd_pcm_hw_params *hw_params)
1da177e4 1348{
d01ce99f
TI		 1349 return snd_pcm_lib_malloc_pages(substream,
1350 params_buffer_bytes(hw_params));
1da177e4
LT		 1351}
1352
a98f90fd 1353static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1354{
1355 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1356 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1357 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1358
1359 /* reset BDL address */
1360 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1361 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1362 azx_sd_writel(azx_dev, SD_CTL, 0);
1363
1364 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1365
1366 return snd_pcm_lib_free_pages(substream);
1367}
1368
a98f90fd 1369static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1370{
1371 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1372 struct azx *chip = apcm->chip;
1373 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1374 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1375 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1376
1377 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1da177e4
LT		 1378 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1379 runtime->channels,
1380 runtime->format,
1381 hinfo->maxbps);
d01ce99f
TI		 1382 if (!azx_dev->format_val) {
1383 snd_printk(KERN_ERR SFX
1384 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1385 runtime->rate, runtime->channels, runtime->format);
1386 return -EINVAL;
1387 }
1388
21c7b081
TI		 1389 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1390 azx_dev->bufsize, azx_dev->format_val);
4ce107b9
TI		 1391 if (azx_setup_periods(substream, azx_dev) < 0)
1392 return -EINVAL;
1da177e4
LT		 1393 azx_setup_controller(chip, azx_dev);
1394 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1395 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1396 else
1397 azx_dev->fifo_size = 0;
1398
1399 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1400 azx_dev->format_val, substream);
1401}
1402
a98f90fd 1403static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1404{
1405 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1406 struct azx *chip = apcm->chip;
850f0e52
TI		 1407 struct azx_dev *azx_dev;
1408 struct snd_pcm_substream *s;
1409 int start, nsync = 0, sbits = 0;
1410 int nwait, timeout;
1da177e4 1411
1da177e4
LT		 1412 switch (cmd) {
1413 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1414 case SNDRV_PCM_TRIGGER_RESUME:
1415 case SNDRV_PCM_TRIGGER_START:
850f0e52 1416 start = 1;
1da177e4
LT		 1417 break;
1418 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1419 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1420 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1421 start = 0;
1da177e4
LT		 1422 break;
1423 default:
850f0e52
TI		 1424 return -EINVAL;
1425 }
1426
1427 snd_pcm_group_for_each_entry(s, substream) {
1428 if (s->pcm->card != substream->pcm->card)
1429 continue;
1430 azx_dev = get_azx_dev(s);
1431 sbits |= 1 << azx_dev->index;
1432 nsync++;
1433 snd_pcm_trigger_done(s, substream);
1434 }
1435
1436 spin_lock(&chip->reg_lock);
1437 if (nsync > 1) {
1438 /* first, set SYNC bits of corresponding streams */
1439 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1440 }
1441 snd_pcm_group_for_each_entry(s, substream) {
1442 if (s->pcm->card != substream->pcm->card)
1443 continue;
1444 azx_dev = get_azx_dev(s);
1445 if (start)
1446 azx_stream_start(chip, azx_dev);
1447 else
1448 azx_stream_stop(chip, azx_dev);
1449 azx_dev->running = start;
1da177e4
LT		 1450 }
1451 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1452 if (start) {
1453 if (nsync == 1)
1454 return 0;
1455 /* wait until all FIFOs get ready */
1456 for (timeout = 5000; timeout; timeout--) {
1457 nwait = 0;
1458 snd_pcm_group_for_each_entry(s, substream) {
1459 if (s->pcm->card != substream->pcm->card)
1460 continue;
1461 azx_dev = get_azx_dev(s);
1462 if (!(azx_sd_readb(azx_dev, SD_STS) &
1463 SD_STS_FIFO_READY))
1464 nwait++;
1465 }
1466 if (!nwait)
1467 break;
1468 cpu_relax();
1469 }
1470 } else {
1471 /* wait until all RUN bits are cleared */
1472 for (timeout = 5000; timeout; timeout--) {
1473 nwait = 0;
1474 snd_pcm_group_for_each_entry(s, substream) {
1475 if (s->pcm->card != substream->pcm->card)
1476 continue;
1477 azx_dev = get_azx_dev(s);
1478 if (azx_sd_readb(azx_dev, SD_CTL) &
1479 SD_CTL_DMA_START)
1480 nwait++;
1481 }
1482 if (!nwait)
1483 break;
1484 cpu_relax();
1485 }
1da177e4 1486 }
850f0e52
TI		 1487 if (nsync > 1) {
1488 spin_lock(&chip->reg_lock);
1489 /* reset SYNC bits */
1490 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1491 spin_unlock(&chip->reg_lock);
1492 }
1493 return 0;
1da177e4
LT		 1494}
1495
9ad593f6
TI		 1496static unsigned int azx_get_position(struct azx *chip,
1497 struct azx_dev *azx_dev)
1da177e4 1498{
1da177e4
LT		 1499 unsigned int pos;
1500
1a56f8d6
TI		 1501 if (chip->position_fix == POS_FIX_POSBUF ||
1502 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1503 /* use the position buffer */
929861c6 1504 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1505 } else {
1506 /* read LPIB */
1507 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1508 }
1da177e4
LT		 1509 if (pos >= azx_dev->bufsize)
1510 pos = 0;
9ad593f6
TI		 1511 return pos;
1512}
1513
1514static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1515{
1516 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1517 struct azx *chip = apcm->chip;
1518 struct azx_dev *azx_dev = get_azx_dev(substream);
1519 return bytes_to_frames(substream->runtime,
1520 azx_get_position(chip, azx_dev));
1521}
1522
1523/*
1524 * Check whether the current DMA position is acceptable for updating
1525 * periods. Returns non-zero if it's OK.
1526 *
1527 * Many HD-audio controllers appear pretty inaccurate about
1528 * the update-IRQ timing. The IRQ is issued before actually the
1529 * data is processed. So, we need to process it afterwords in a
1530 * workqueue.
1531 */
1532static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1533{
1534 unsigned int pos;
1535
1536 pos = azx_get_position(chip, azx_dev);
1537 if (chip->position_fix == POS_FIX_AUTO) {
1538 if (!pos) {
1539 printk(KERN_WARNING
1540 "hda-intel: Invalid position buffer, "
1541 "using LPIB read method instead.\n");
d2e1c973 1542 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1543 pos = azx_get_position(chip, azx_dev);
1544 } else
1545 chip->position_fix = POS_FIX_POSBUF;
1546 }
1547
1548 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1549 return 0; /* NG - it's below the period boundary */
1550 return 1; /* OK, it's fine */
1551}
1552
1553/*
1554 * The work for pending PCM period updates.
1555 */
1556static void azx_irq_pending_work(struct work_struct *work)
1557{
1558 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1559 int i, pending;
1560
1561 for (;;) {
1562 pending = 0;
1563 spin_lock_irq(&chip->reg_lock);
1564 for (i = 0; i < chip->num_streams; i++) {
1565 struct azx_dev *azx_dev = &chip->azx_dev[i];
1566 if (!azx_dev->irq_pending ||
1567 !azx_dev->substream ||
1568 !azx_dev->running)
1569 continue;
1570 if (azx_position_ok(chip, azx_dev)) {
1571 azx_dev->irq_pending = 0;
1572 spin_unlock(&chip->reg_lock);
1573 snd_pcm_period_elapsed(azx_dev->substream);
1574 spin_lock(&chip->reg_lock);
1575 } else
1576 pending++;
1577 }
1578 spin_unlock_irq(&chip->reg_lock);
1579 if (!pending)
1580 return;
1581 cond_resched();
1582 }
1583}
1584
1585/* clear irq_pending flags and assure no on-going workq */
1586static void azx_clear_irq_pending(struct azx *chip)
1587{
1588 int i;
1589
1590 spin_lock_irq(&chip->reg_lock);
1591 for (i = 0; i < chip->num_streams; i++)
1592 chip->azx_dev[i].irq_pending = 0;
1593 spin_unlock_irq(&chip->reg_lock);
1594 flush_scheduled_work();
1da177e4
LT		 1595}
1596
a98f90fd 1597static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1598 .open = azx_pcm_open,
1599 .close = azx_pcm_close,
1600 .ioctl = snd_pcm_lib_ioctl,
1601 .hw_params = azx_pcm_hw_params,
1602 .hw_free = azx_pcm_hw_free,
1603 .prepare = azx_pcm_prepare,
1604 .trigger = azx_pcm_trigger,
1605 .pointer = azx_pcm_pointer,
4ce107b9 1606 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1607};
1608
a98f90fd 1609static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4
LT		 1610{
1611 kfree(pcm->private_data);
1612}
1613
a98f90fd 1614static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
7ba72ba1 1615 struct hda_pcm *cpcm)
1da177e4
LT		 1616{
1617 int err;
a98f90fd 1618 struct snd_pcm *pcm;
1da177e4
LT		 1619 struct azx_pcm *apcm;
1620
e08a007d
TI		 1621 /* if no substreams are defined for both playback and capture,
1622 * it's just a placeholder. ignore it.
1623 */
1624 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1625 return 0;
1626
1da177e4
LT		 1627 snd_assert(cpcm->name, return -EINVAL);
1628
7ba72ba1 1629 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
d01ce99f
TI		 1630 cpcm->stream[0].substreams,
1631 cpcm->stream[1].substreams,
1da177e4
LT		 1632 &pcm);
1633 if (err < 0)
1634 return err;
1635 strcpy(pcm->name, cpcm->name);
1636 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1637 if (apcm == NULL)
1638 return -ENOMEM;
1639 apcm->chip = chip;
1640 apcm->codec = codec;
1641 apcm->hinfo[0] = &cpcm->stream[0];
1642 apcm->hinfo[1] = &cpcm->stream[1];
1643 pcm->private_data = apcm;
1644 pcm->private_free = azx_pcm_free;
1645 if (cpcm->stream[0].substreams)
1646 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1647 if (cpcm->stream[1].substreams)
1648 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
4ce107b9 1649 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1650 snd_dma_pci_data(chip->pci),
b66b3cfe 1651 1024 * 64, 1024 * 1024);
7ba72ba1 1652 chip->pcm[cpcm->device] = pcm;
1da177e4
LT		 1653 return 0;
1654}
1655
a98f90fd 1656static int __devinit azx_pcm_create(struct azx *chip)
1da177e4 1657{
7ba72ba1
TI		 1658 static const char *dev_name[HDA_PCM_NTYPES] = {
1659 "Audio", "SPDIF", "HDMI", "Modem"
1660 };
1661 /* starting device index for each PCM type */
1662 static int dev_idx[HDA_PCM_NTYPES] = {
1663 [HDA_PCM_TYPE_AUDIO] = 0,
1664 [HDA_PCM_TYPE_SPDIF] = 1,
1665 [HDA_PCM_TYPE_HDMI] = 3,
1666 [HDA_PCM_TYPE_MODEM] = 6
1667 };
1668 /* normal audio device indices; not linear to keep compatibility */
1669 static int audio_idx[4] = { 0, 2, 4, 5 };
1da177e4
LT		 1670 struct hda_codec *codec;
1671 int c, err;
7ba72ba1 1672 int num_devs[HDA_PCM_NTYPES];
1da177e4 1673
d01ce99f
TI		 1674 err = snd_hda_build_pcms(chip->bus);
1675 if (err < 0)
1da177e4
LT		 1676 return err;
1677
ec9e1c5c 1678 /* create audio PCMs */
7ba72ba1 1679 memset(num_devs, 0, sizeof(num_devs));
33206e86 1680 list_for_each_entry(codec, &chip->bus->codec_list, list) {
ec9e1c5c 1681 for (c = 0; c < codec->num_pcms; c++) {
7ba72ba1
TI		 1682 struct hda_pcm *cpcm = &codec->pcm_info[c];
1683 int type = cpcm->pcm_type;
1684 switch (type) {
1685 case HDA_PCM_TYPE_AUDIO:
1686 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1687 snd_printk(KERN_WARNING
1688 "Too many audio devices\n");
1689 continue;
1690 }
1691 cpcm->device = audio_idx[num_devs[type]];
1692 break;
1693 case HDA_PCM_TYPE_SPDIF:
1694 case HDA_PCM_TYPE_HDMI:
1695 case HDA_PCM_TYPE_MODEM:
1696 if (num_devs[type]) {
1697 snd_printk(KERN_WARNING
1698 "%s already defined\n",
1699 dev_name[type]);
1700 continue;
1701 }
1702 cpcm->device = dev_idx[type];
1703 break;
1704 default:
1705 snd_printk(KERN_WARNING
1706 "Invalid PCM type %d\n", type);
1707 continue;
1da177e4 1708 }
7ba72ba1
TI		 1709 num_devs[type]++;
1710 err = create_codec_pcm(chip, codec, cpcm);
1da177e4
LT		 1711 if (err < 0)
1712 return err;
1da177e4
LT		 1713 }
1714 }
1715 return 0;
1716}
1717
1718/*
1719 * mixer creation - all stuff is implemented in hda module
1720 */
a98f90fd 1721static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1722{
1723 return snd_hda_build_controls(chip->bus);
1724}
1725
1726
1727/*
1728 * initialize SD streams
1729 */
a98f90fd 1730static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1731{
1732 int i;
1733
1734 /* initialize each stream (aka device)
d01ce99f
TI		 1735 * assign the starting bdl address to each stream (device)
1736 * and initialize
1da177e4 1737 */
07e4ca50 1738 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1739 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1740 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1741 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1742 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1743 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1744 azx_dev->sd_int_sta_mask = 1 << i;
1745 /* stream tag: must be non-zero and unique */
1746 azx_dev->index = i;
1747 azx_dev->stream_tag = i + 1;
1748 }
1749
1750 return 0;
1751}
1752
68e7fffc
TI		 1753static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1754{
437a5a46
TI		 1755 if (request_irq(chip->pci->irq, azx_interrupt,
1756 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1757 "HDA Intel", chip)) {
1758 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1759 "disabling device\n", chip->pci->irq);
1760 if (do_disconnect)
1761 snd_card_disconnect(chip->card);
1762 return -1;
1763 }
1764 chip->irq = chip->pci->irq;
69e13418 1765 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1766 return 0;
1767}
1768
1da177e4 1769
cb53c626
TI		 1770static void azx_stop_chip(struct azx *chip)
1771{
95e99fda 1772 if (!chip->initialized)
cb53c626
TI		 1773 return;
1774
1775 /* disable interrupts */
1776 azx_int_disable(chip);
1777 azx_int_clear(chip);
1778
1779 /* disable CORB/RIRB */
1780 azx_free_cmd_io(chip);
1781
1782 /* disable position buffer */
1783 azx_writel(chip, DPLBASE, 0);
1784 azx_writel(chip, DPUBASE, 0);
1785
1786 chip->initialized = 0;
1787}
1788
1789#ifdef CONFIG_SND_HDA_POWER_SAVE
1790/* power-up/down the controller */
1791static void azx_power_notify(struct hda_codec *codec)
1792{
1793 struct azx *chip = codec->bus->private_data;
1794 struct hda_codec *c;
1795 int power_on = 0;
1796
1797 list_for_each_entry(c, &codec->bus->codec_list, list) {
1798 if (c->power_on) {
1799 power_on = 1;
1800 break;
1801 }
1802 }
1803 if (power_on)
1804 azx_init_chip(chip);
dee1b66c 1805 else if (chip->running && power_save_controller)
cb53c626 1806 azx_stop_chip(chip);
cb53c626
TI		 1807}
1808#endif /* CONFIG_SND_HDA_POWER_SAVE */
1809
1da177e4
LT		 1810#ifdef CONFIG_PM
1811/*
1812 * power management
1813 */
421a1252 1814static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1815{
421a1252
TI		 1816 struct snd_card *card = pci_get_drvdata(pci);
1817 struct azx *chip = card->private_data;
1da177e4
LT		 1818 int i;
1819
421a1252 1820 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1821 azx_clear_irq_pending(chip);
7ba72ba1 1822 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 1823 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI		 1824 if (chip->initialized)
1825 snd_hda_suspend(chip->bus, state);
cb53c626 1826 azx_stop_chip(chip);
30b35399 1827 if (chip->irq >= 0) {
43001c95 1828 free_irq(chip->irq, chip);
30b35399
TI		 1829 chip->irq = -1;
1830 }
68e7fffc 1831 if (chip->msi)
43001c95 1832 pci_disable_msi(chip->pci);
421a1252
TI		 1833 pci_disable_device(pci);
1834 pci_save_state(pci);
30b35399 1835 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1836 return 0;
1837}
1838
421a1252 1839static int azx_resume(struct pci_dev *pci)
1da177e4 1840{
421a1252
TI		 1841 struct snd_card *card = pci_get_drvdata(pci);
1842 struct azx *chip = card->private_data;
1da177e4 1843
30b35399 1844 pci_set_power_state(pci, PCI_D0);
421a1252 1845 pci_restore_state(pci);
30b35399
TI		 1846 if (pci_enable_device(pci) < 0) {
1847 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1848 "disabling device\n");
1849 snd_card_disconnect(card);
1850 return -EIO;
1851 }
1852 pci_set_master(pci);
68e7fffc
TI		 1853 if (chip->msi)
1854 if (pci_enable_msi(pci) < 0)
1855 chip->msi = 0;
1856 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1857 return -EIO;
cb53c626 1858 azx_init_pci(chip);
d804ad92
ML		 1859
1860 if (snd_hda_codecs_inuse(chip->bus))
1861 azx_init_chip(chip);
1862
1da177e4 1863 snd_hda_resume(chip->bus);
421a1252 1864 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1865 return 0;
1866}
1867#endif /* CONFIG_PM */
1868
1869
1870/*
1871 * destructor
1872 */
a98f90fd 1873static int azx_free(struct azx *chip)
1da177e4 1874{
4ce107b9
TI		 1875 int i;
1876
ce43fbae 1877 if (chip->initialized) {
9ad593f6 1878 azx_clear_irq_pending(chip);
07e4ca50 1879 for (i = 0; i < chip->num_streams; i++)
1da177e4 1880 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1881 azx_stop_chip(chip);
1da177e4
LT		 1882 }
1883
f000fd80 1884 if (chip->irq >= 0)
1da177e4 1885 free_irq(chip->irq, (void*)chip);
68e7fffc 1886 if (chip->msi)
30b35399 1887 pci_disable_msi(chip->pci);
f079c25a
TI		 1888 if (chip->remap_addr)
1889 iounmap(chip->remap_addr);
1da177e4 1890
4ce107b9
TI		 1891 if (chip->azx_dev) {
1892 for (i = 0; i < chip->num_streams; i++)
1893 if (chip->azx_dev[i].bdl.area)
1894 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1895 }
1da177e4
LT		 1896 if (chip->rb.area)
1897 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 1898 if (chip->posbuf.area)
1899 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 1900 pci_release_regions(chip->pci);
1901 pci_disable_device(chip->pci);
07e4ca50 1902 kfree(chip->azx_dev);
1da177e4
LT		 1903 kfree(chip);
1904
1905 return 0;
1906}
1907
a98f90fd 1908static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1909{
1910 return azx_free(device->device_data);
1911}
1912
3372a153
TI		 1913/*
1914 * white/black-listing for position_fix
1915 */
623ec047 1916static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 1917 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1918 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1919 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 1920 {}
1921};
1922
1923static int __devinit check_position_fix(struct azx *chip, int fix)
1924{
1925 const struct snd_pci_quirk *q;
1926
1927 if (fix == POS_FIX_AUTO) {
1928 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1929 if (q) {
669ba27a 1930 printk(KERN_INFO
3372a153
TI		 1931 "hda_intel: position_fix set to %d "
1932 "for device %04x:%04x\n",
1933 q->value, q->subvendor, q->subdevice);
1934 return q->value;
1935 }
1936 }
1937 return fix;
1938}
1939
669ba27a
TI		 1940/*
1941 * black-lists for probe_mask
1942 */
1943static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1944 /* Thinkpad often breaks the controller communication when accessing
1945 * to the non-working (or non-existing) modem codec slot.
1946 */
1947 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1948 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1949 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1950 {}
1951};
1952
5aba4f8e 1953static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1954{
1955 const struct snd_pci_quirk *q;
1956
5aba4f8e 1957 if (probe_mask[dev] == -1) {
669ba27a
TI		 1958 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1959 if (q) {
1960 printk(KERN_INFO
1961 "hda_intel: probe_mask set to 0x%x "
1962 "for device %04x:%04x\n",
1963 q->value, q->subvendor, q->subdevice);
5aba4f8e 1964 probe_mask[dev] = q->value;
669ba27a
TI		 1965 }
1966 }
1967}
1968
1969
1da177e4
LT		 1970/*
1971 * constructor
1972 */
a98f90fd 1973static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 1974 int dev, int driver_type,
a98f90fd 1975 struct azx **rchip)
1da177e4 1976{
a98f90fd 1977 struct azx *chip;
4ce107b9 1978 int i, err;
bcd72003 1979 unsigned short gcap;
a98f90fd 1980 static struct snd_device_ops ops = {
1da177e4
LT		 1981 .dev_free = azx_dev_free,
1982 };
1983
1984 *rchip = NULL;
bcd72003 1985
927fc866
PM		 1986 err = pci_enable_device(pci);
1987 if (err < 0)
1da177e4
LT		 1988 return err;
1989
e560d8d8 1990 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1991 if (!chip) {
1da177e4
LT		 1992 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1993 pci_disable_device(pci);
1994 return -ENOMEM;
1995 }
1996
1997 spin_lock_init(&chip->reg_lock);
62932df8 1998 mutex_init(&chip->open_mutex);
1da177e4
LT		 1999 chip->card = card;
2000 chip->pci = pci;
2001 chip->irq = -1;
07e4ca50 2002 chip->driver_type = driver_type;
134a11f0 2003 chip->msi = enable_msi;
9ad593f6 2004 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2005
5aba4f8e
TI		 2006 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2007 check_probe_mask(chip, dev);
3372a153 2008
27346166 2009 chip->single_cmd = single_cmd;
c74db86b 2010
07e4ca50
TI		 2011#if BITS_PER_LONG != 64
2012 /* Fix up base address on ULI M5461 */
2013 if (chip->driver_type == AZX_DRIVER_ULI) {
2014 u16 tmp3;
2015 pci_read_config_word(pci, 0x40, &tmp3);
2016 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2017 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2018 }
2019#endif
2020
927fc866
PM		 2021 err = pci_request_regions(pci, "ICH HD audio");
2022 if (err < 0) {
1da177e4
LT		 2023 kfree(chip);
2024 pci_disable_device(pci);
2025 return err;
2026 }
2027
927fc866 2028 chip->addr = pci_resource_start(pci, 0);
1da177e4
LT		 2029 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2030 if (chip->remap_addr == NULL) {
2031 snd_printk(KERN_ERR SFX "ioremap error\n");
2032 err = -ENXIO;
2033 goto errout;
2034 }
2035
68e7fffc
TI		 2036 if (chip->msi)
2037 if (pci_enable_msi(pci) < 0)
2038 chip->msi = 0;
7376d013 2039
68e7fffc 2040 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2041 err = -EBUSY;
2042 goto errout;
2043 }
1da177e4
LT		 2044
2045 pci_set_master(pci);
2046 synchronize_irq(chip->irq);
2047
bcd72003
TD		 2048 gcap = azx_readw(chip, GCAP);
2049 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2050
cf7aaca8
TI		 2051 /* allow 64bit DMA address if supported by H/W */
2052 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2053 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2054
8b6ed8e7
TI		 2055 /* read number of streams from GCAP register instead of using
2056 * hardcoded value
2057 */
2058 chip->capture_streams = (gcap >> 8) & 0x0f;
2059 chip->playback_streams = (gcap >> 12) & 0x0f;
2060 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2061 /* gcap didn't give any info, switching to old method */
2062
2063 switch (chip->driver_type) {
2064 case AZX_DRIVER_ULI:
2065 chip->playback_streams = ULI_NUM_PLAYBACK;
2066 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2067 break;
2068 case AZX_DRIVER_ATIHDMI:
2069 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2070 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003
TD		 2071 break;
2072 default:
2073 chip->playback_streams = ICH6_NUM_PLAYBACK;
2074 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2075 break;
2076 }
07e4ca50 2077 }
8b6ed8e7
TI		 2078 chip->capture_index_offset = 0;
2079 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2080 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2081 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2082 GFP_KERNEL);
927fc866 2083 if (!chip->azx_dev) {
07e4ca50
TI		 2084 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2085 goto errout;
2086 }
2087
4ce107b9
TI		 2088 for (i = 0; i < chip->num_streams; i++) {
2089 /* allocate memory for the BDL for each stream */
2090 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2091 snd_dma_pci_data(chip->pci),
2092 BDL_SIZE, &chip->azx_dev[i].bdl);
2093 if (err < 0) {
2094 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2095 goto errout;
2096 }
1da177e4 2097 }
0be3b5d3 2098 /* allocate memory for the position buffer */
d01ce99f
TI		 2099 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2100 snd_dma_pci_data(chip->pci),
2101 chip->num_streams * 8, &chip->posbuf);
2102 if (err < 0) {
0be3b5d3
TI		 2103 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2104 goto errout;
1da177e4 2105 }
1da177e4 2106 /* allocate CORB/RIRB */
d01ce99f
TI		 2107 if (!chip->single_cmd) {
2108 err = azx_alloc_cmd_io(chip);
2109 if (err < 0)
27346166 2110 goto errout;
d01ce99f 2111 }
1da177e4
LT		 2112
2113 /* initialize streams */
2114 azx_init_stream(chip);
2115
2116 /* initialize chip */
cb53c626 2117 azx_init_pci(chip);
1da177e4
LT		 2118 azx_init_chip(chip);
2119
2120 /* codec detection */
927fc866 2121 if (!chip->codec_mask) {
1da177e4
LT		 2122 snd_printk(KERN_ERR SFX "no codecs found!\n");
2123 err = -ENODEV;
2124 goto errout;
2125 }
2126
d01ce99f
TI		 2127 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2128 if (err <0) {
1da177e4
LT		 2129 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2130 goto errout;
2131 }
2132
07e4ca50
TI		 2133 strcpy(card->driver, "HDA-Intel");
2134 strcpy(card->shortname, driver_short_names[chip->driver_type]);
d01ce99f
TI		 2135 sprintf(card->longname, "%s at 0x%lx irq %i",
2136 card->shortname, chip->addr, chip->irq);
07e4ca50 2137
1da177e4
LT		 2138 *rchip = chip;
2139 return 0;
2140
2141 errout:
2142 azx_free(chip);
2143 return err;
2144}
2145
cb53c626
TI		 2146static void power_down_all_codecs(struct azx *chip)
2147{
2148#ifdef CONFIG_SND_HDA_POWER_SAVE
2149 /* The codecs were powered up in snd_hda_codec_new().
2150 * Now all initialization done, so turn them down if possible
2151 */
2152 struct hda_codec *codec;
2153 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2154 snd_hda_power_down(codec);
2155 }
2156#endif
2157}
2158
d01ce99f
TI		 2159static int __devinit azx_probe(struct pci_dev *pci,
2160 const struct pci_device_id *pci_id)
1da177e4 2161{
5aba4f8e 2162 static int dev;
a98f90fd
TI		 2163 struct snd_card *card;
2164 struct azx *chip;
927fc866 2165 int err;
1da177e4 2166
5aba4f8e
TI		 2167 if (dev >= SNDRV_CARDS)
2168 return -ENODEV;
2169 if (!enable[dev]) {
2170 dev++;
2171 return -ENOENT;
2172 }
2173
2174 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
927fc866 2175 if (!card) {
1da177e4
LT		 2176 snd_printk(KERN_ERR SFX "Error creating card!\n");
2177 return -ENOMEM;
2178 }
2179
5aba4f8e 2180 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
927fc866 2181 if (err < 0) {
1da177e4
LT		 2182 snd_card_free(card);
2183 return err;
2184 }
421a1252 2185 card->private_data = chip;
1da177e4 2186
1da177e4 2187 /* create codec instances */
5aba4f8e 2188 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
d01ce99f 2189 if (err < 0) {
1da177e4
LT		 2190 snd_card_free(card);
2191 return err;
2192 }
2193
2194 /* create PCM streams */
d01ce99f
TI		 2195 err = azx_pcm_create(chip);
2196 if (err < 0) {
1da177e4
LT		 2197 snd_card_free(card);
2198 return err;
2199 }
2200
2201 /* create mixer controls */
d01ce99f
TI		 2202 err = azx_mixer_create(chip);
2203 if (err < 0) {
1da177e4
LT		 2204 snd_card_free(card);
2205 return err;
2206 }
2207
1da177e4
LT		 2208 snd_card_set_dev(card, &pci->dev);
2209
d01ce99f
TI		 2210 err = snd_card_register(card);
2211 if (err < 0) {
1da177e4
LT		 2212 snd_card_free(card);
2213 return err;
2214 }
2215
2216 pci_set_drvdata(pci, card);
cb53c626
TI		 2217 chip->running = 1;
2218 power_down_all_codecs(chip);
1da177e4 2219
e25bcdba 2220 dev++;
1da177e4
LT		 2221 return err;
2222}
2223
2224static void __devexit azx_remove(struct pci_dev *pci)
2225{
2226 snd_card_free(pci_get_drvdata(pci));
2227 pci_set_drvdata(pci, NULL);
2228}
2229
2230/* PCI IDs */
f40b6890 2231static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2232 /* ICH 6..10 */
2233 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2234 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2235 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2236 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2237 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2238 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2239 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2240 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2241 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2242 /* SCH */
2243 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2244 /* ATI SB 450/600 */
2245 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2246 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2247 /* ATI HDMI */
2248 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2249 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2250 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2251 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2252 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2253 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2254 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2255 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2256 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2257 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2258 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2259 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2260 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2261 /* VIA VT8251/VT8237A */
2262 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2263 /* SIS966 */
2264 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2265 /* ULI M5461 */
2266 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2267 /* NVIDIA MCP */
2268 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2269 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2270 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2271 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2272 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2273 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2274 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2275 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2276 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2277 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2278 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2279 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2280 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2281 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2282 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2283 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2284 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2285 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
487145a1
PC		 2286 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2287 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2288 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2289 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2290 /* Teradici */
2291 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
1da177e4
LT		 2292 { 0, }
2293};
2294MODULE_DEVICE_TABLE(pci, azx_ids);
2295
2296/* pci_driver definition */
2297static struct pci_driver driver = {
2298 .name = "HDA Intel",
2299 .id_table = azx_ids,
2300 .probe = azx_probe,
2301 .remove = __devexit_p(azx_remove),
421a1252
TI		 2302#ifdef CONFIG_PM
2303 .suspend = azx_suspend,
2304 .resume = azx_resume,
2305#endif
1da177e4
LT		 2306};
2307
2308static int __init alsa_card_azx_init(void)
2309{
01d25d46 2310 return pci_register_driver(&driver);
1da177e4
LT		 2311}
2312
2313static void __exit alsa_card_azx_exit(void)
2314{
2315 pci_unregister_driver(&driver);
2316}
2317
2318module_init(alsa_card_azx_init)
2319module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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