projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'topic/hda' into topic/hda-switcheroo
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9
TI		 48#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
1da177e4
LT		 54#include <sound/core.h>
55#include <sound/initval.h>
56#include "hda_codec.h"
57
58
5aba4f8e
TI		 59static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 61static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 62static char *model[SNDRV_CARDS];
63static int position_fix[SNDRV_CARDS];
5c0d7bc1 64static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 65static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 66static int probe_only[SNDRV_CARDS];
a67ff6a5 67static bool single_cmd;
71623855 68static int enable_msi = -1;
4ea6fbc8
TI		 69#ifdef CONFIG_SND_HDA_PATCH_LOADER
70static char *patch[SNDRV_CARDS];
71#endif
2dca0bba
JK		 72#ifdef CONFIG_SND_HDA_INPUT_BEEP
73static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75#endif
1da177e4 76
5aba4f8e 77module_param_array(index, int, NULL, 0444);
1da177e4 78MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 79module_param_array(id, charp, NULL, 0444);
1da177e4 80MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 81module_param_array(enable, bool, NULL, 0444);
82MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83module_param_array(model, charp, NULL, 0444);
1da177e4 84MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 85module_param_array(position_fix, int, NULL, 0444);
4cb36310 86MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 88module_param_array(bdl_pos_adj, int, NULL, 0644);
89MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 90module_param_array(probe_mask, int, NULL, 0444);
606ad75f 91MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 92module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 93MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 94module_param(single_cmd, bool, 0444);
d01ce99f
TI		 95MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
ac9ef6cf 97module_param(enable_msi, bint, 0444);
134a11f0 98MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 99#ifdef CONFIG_SND_HDA_PATCH_LOADER
100module_param_array(patch, charp, NULL, 0444);
101MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102#endif
2dca0bba
JK		 103#ifdef CONFIG_SND_HDA_INPUT_BEEP
104module_param_array(beep_mode, int, NULL, 0444);
105MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107#endif
606ad75f 108
dee1b66c 109#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 110static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111module_param(power_save, int, 0644);
112MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
1da177e4 114
dee1b66c
TI		 115/* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
a67ff6a5 119static bool power_save_controller = 1;
dee1b66c
TI		 120module_param(power_save_controller, bool, 0644);
121MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122#endif
123
7bfe059e
TI		 124static int align_buffer_size = -1;
125module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 126MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
27fe48d9
TI		 129#ifdef CONFIG_X86
130static bool hda_snoop = true;
131module_param_named(snoop, hda_snoop, bool, 0444);
132MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133#define azx_snoop(chip) (chip)->snoop
134#else
135#define hda_snoop true
136#define azx_snoop(chip) true
137#endif
138
139
1da177e4
LT		 140MODULE_LICENSE("GPL");
141MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
2f1b3818 143 "{Intel, ICH7},"
f5d40b30 144 "{Intel, ESB2},"
d2981393 145 "{Intel, ICH8},"
f9cc8a8b 146 "{Intel, ICH9},"
c34f5a04 147 "{Intel, ICH10},"
b29c2360 148 "{Intel, PCH},"
d2f2fcd2 149 "{Intel, CPT},"
d2edeb7c 150 "{Intel, PPT},"
8bc039a1 151 "{Intel, LPT},"
cea310e8 152 "{Intel, PBG},"
4979bca9 153 "{Intel, SCH},"
fc20a562 154 "{ATI, SB450},"
89be83f8 155 "{ATI, SB600},"
778b6e1b 156 "{ATI, RS600},"
5b15c95f 157 "{ATI, RS690},"
e6db1119
WL		 158 "{ATI, RS780},"
159 "{ATI, R600},"
2797f724
HRK		 160 "{ATI, RV630},"
161 "{ATI, RV610},"
27da1834
WL		 162 "{ATI, RV670},"
163 "{ATI, RV635},"
164 "{ATI, RV620},"
165 "{ATI, RV770},"
fc20a562 166 "{VIA, VT8251},"
47672310 167 "{VIA, VT8237A},"
07e4ca50
TI		 168 "{SiS, SIS966},"
169 "{ULI, M5461}}");
1da177e4
LT		 170MODULE_DESCRIPTION("Intel HDA driver");
171
4abc1cc2
TI		 172#ifdef CONFIG_SND_VERBOSE_PRINTK
173#define SFX /* nop */
174#else
1da177e4 175#define SFX "hda-intel: "
4abc1cc2 176#endif
cb53c626 177
1da177e4
LT		 178/*
179 * registers
180 */
181#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 182#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
183#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
184#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
185#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
186#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 187#define ICH6_REG_VMIN 0x02
188#define ICH6_REG_VMAJ 0x03
189#define ICH6_REG_OUTPAY 0x04
190#define ICH6_REG_INPAY 0x06
191#define ICH6_REG_GCTL 0x08
8a933ece 192#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 193#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
194#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 195#define ICH6_REG_WAKEEN 0x0c
196#define ICH6_REG_STATESTS 0x0e
197#define ICH6_REG_GSTS 0x10
b21fadb9 198#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 199#define ICH6_REG_INTCTL 0x20
200#define ICH6_REG_INTSTS 0x24
e5463720 201#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 202#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
203#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 204#define ICH6_REG_CORBLBASE 0x40
205#define ICH6_REG_CORBUBASE 0x44
206#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 207#define ICH6_REG_CORBRP 0x4a
208#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 209#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 210#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
211#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 212#define ICH6_REG_CORBSTS 0x4d
b21fadb9 213#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 214#define ICH6_REG_CORBSIZE 0x4e
215
216#define ICH6_REG_RIRBLBASE 0x50
217#define ICH6_REG_RIRBUBASE 0x54
218#define ICH6_REG_RIRBWP 0x58
b21fadb9 219#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 220#define ICH6_REG_RINTCNT 0x5a
221#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 222#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
223#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
224#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 225#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 226#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
227#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 228#define ICH6_REG_RIRBSIZE 0x5e
229
230#define ICH6_REG_IC 0x60
231#define ICH6_REG_IR 0x64
232#define ICH6_REG_IRS 0x68
233#define ICH6_IRS_VALID (1<<1)
234#define ICH6_IRS_BUSY (1<<0)
235
236#define ICH6_REG_DPLBASE 0x70
237#define ICH6_REG_DPUBASE 0x74
238#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
239
240/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
241enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
242
243/* stream register offsets from stream base */
244#define ICH6_REG_SD_CTL 0x00
245#define ICH6_REG_SD_STS 0x03
246#define ICH6_REG_SD_LPIB 0x04
247#define ICH6_REG_SD_CBL 0x08
248#define ICH6_REG_SD_LVI 0x0c
249#define ICH6_REG_SD_FIFOW 0x0e
250#define ICH6_REG_SD_FIFOSIZE 0x10
251#define ICH6_REG_SD_FORMAT 0x12
252#define ICH6_REG_SD_BDLPL 0x18
253#define ICH6_REG_SD_BDLPU 0x1c
254
255/* PCI space */
256#define ICH6_PCIREG_TCSEL 0x44
257
258/*
259 * other constants
260 */
261
262/* max number of SDs */
07e4ca50 263/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 264#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 265#define ICH6_NUM_PLAYBACK 4
266
267/* ULI has 6 playback and 5 capture */
07e4ca50 268#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 269#define ULI_NUM_PLAYBACK 6
270
778b6e1b 271/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 272#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 273#define ATIHDMI_NUM_PLAYBACK 1
274
f269002e
KY		 275/* TERA has 4 playback and 3 capture */
276#define TERA_NUM_CAPTURE 3
277#define TERA_NUM_PLAYBACK 4
278
07e4ca50
TI		 279/* this number is statically defined for simplicity */
280#define MAX_AZX_DEV 16
281
1da177e4 282/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 283#define BDL_SIZE 4096
284#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
285#define AZX_MAX_FRAG 32
1da177e4
LT		 286/* max buffer size - no h/w limit, you can increase as you like */
287#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 288
289/* RIRB int mask: overrun[2], response[0] */
290#define RIRB_INT_RESPONSE 0x01
291#define RIRB_INT_OVERRUN 0x04
292#define RIRB_INT_MASK 0x05
293
2f5983f2 294/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 295#define AZX_MAX_CODECS 8
296#define AZX_DEFAULT_CODECS 4
deadff16 297#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 298
299/* SD_CTL bits */
300#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
301#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 302#define SD_CTL_STRIPE (3 << 16) /* stripe control */
303#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
304#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 305#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
306#define SD_CTL_STREAM_TAG_SHIFT 20
307
308/* SD_CTL and SD_STS */
309#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
310#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
311#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 312#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
313 SD_INT_COMPLETE)
1da177e4
LT		 314
315/* SD_STS */
316#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
317
318/* INTCTL and INTSTS */
d01ce99f
TI		 319#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
320#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
321#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 322
1da177e4
LT		 323/* below are so far hardcoded - should read registers in future */
324#define ICH6_MAX_CORB_ENTRIES 256
325#define ICH6_MAX_RIRB_ENTRIES 256
326
c74db86b
TI		 327/* position fix mode */
328enum {
0be3b5d3 329 POS_FIX_AUTO,
d2e1c973 330 POS_FIX_LPIB,
0be3b5d3 331 POS_FIX_POSBUF,
4cb36310 332 POS_FIX_VIACOMBO,
a6f2fd55 333 POS_FIX_COMBO,
c74db86b 334};
1da177e4 335
f5d40b30 336/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 337#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
338#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
339
da3fca21
V		 340/* Defines for Nvidia HDA support */
341#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
342#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 343#define NVIDIA_HDA_ISTRM_COH 0x4d
344#define NVIDIA_HDA_OSTRM_COH 0x4c
345#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 346
90a5ad52
TI		 347/* Defines for Intel SCH HDA snoop control */
348#define INTEL_SCH_HDA_DEVC 0x78
349#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
350
0e153474
JC		 351/* Define IN stream 0 FIFO size offset in VIA controller */
352#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
353/* Define VIA HD Audio Device ID*/
354#define VIA_HDAC_DEVICE_ID 0x3288
355
c4da29ca
YL		 356/* HD Audio class code */
357#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 358
1da177e4
LT		 359/*
360 */
361
a98f90fd 362struct azx_dev {
4ce107b9 363 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 364 u32 *posbuf; /* position buffer pointer */
1da177e4 365
d01ce99f 366 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 367 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 368 unsigned int frags; /* number for period in the play buffer */
369 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 370 unsigned long start_wallclk; /* start + minimum wallclk */
371 unsigned long period_wallclk; /* wallclk for period */
1da177e4 372
d01ce99f 373 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 374
d01ce99f 375 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 376
377 /* pcm support */
d01ce99f
TI		 378 struct snd_pcm_substream *substream; /* assigned substream,
379 * set in PCM open
380 */
381 unsigned int format_val; /* format value to be set in the
382 * controller and the codec
383 */
1da177e4
LT		 384 unsigned char stream_tag; /* assigned stream */
385 unsigned char index; /* stream index */
d5cf9911 386 int assigned_key; /* last device# key assigned to */
1da177e4 387
927fc866
PM		 388 unsigned int opened :1;
389 unsigned int running :1;
675f25d4 390 unsigned int irq_pending :1;
0e153474
JC		 391 /*
392 * For VIA:
393 * A flag to ensure DMA position is 0
394 * when link position is not greater than FIFO size
395 */
396 unsigned int insufficient :1;
27fe48d9 397 unsigned int wc_marked:1;
1da177e4
LT		 398};
399
400/* CORB/RIRB */
a98f90fd 401struct azx_rb {
1da177e4
LT		 402 u32 *buf; /* CORB/RIRB buffer
403 * Each CORB entry is 4byte, RIRB is 8byte
404 */
405 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
406 /* for RIRB */
407 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 408 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
409 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 410};
411
01b65bfb
TI		 412struct azx_pcm {
413 struct azx *chip;
414 struct snd_pcm *pcm;
415 struct hda_codec *codec;
416 struct hda_pcm_stream *hinfo[2];
417 struct list_head list;
418};
419
a98f90fd
TI		 420struct azx {
421 struct snd_card *card;
1da177e4 422 struct pci_dev *pci;
555e219f 423 int dev_index;
1da177e4 424
07e4ca50
TI		 425 /* chip type specific */
426 int driver_type;
9477c58e 427 unsigned int driver_caps;
07e4ca50
TI		 428 int playback_streams;
429 int playback_index_offset;
430 int capture_streams;
431 int capture_index_offset;
432 int num_streams;
433
1da177e4
LT		 434 /* pci resources */
435 unsigned long addr;
436 void __iomem *remap_addr;
437 int irq;
438
439 /* locks */
440 spinlock_t reg_lock;
62932df8 441 struct mutex open_mutex;
1da177e4 442
07e4ca50 443 /* streams (x num_streams) */
a98f90fd 444 struct azx_dev *azx_dev;
1da177e4
LT		 445
446 /* PCM */
01b65bfb 447 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 448
449 /* HD codec */
450 unsigned short codec_mask;
f1eaaeec 451 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 452 struct hda_bus *bus;
2dca0bba 453 unsigned int beep_mode;
1da177e4
LT		 454
455 /* CORB/RIRB */
a98f90fd
TI		 456 struct azx_rb corb;
457 struct azx_rb rirb;
1da177e4 458
4ce107b9 459 /* CORB/RIRB and position buffers */
1da177e4
LT		 460 struct snd_dma_buffer rb;
461 struct snd_dma_buffer posbuf;
c74db86b
TI		 462
463 /* flags */
beaffc39 464 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 465 int poll_count;
cb53c626 466 unsigned int running :1;
927fc866
PM		 467 unsigned int initialized :1;
468 unsigned int single_cmd :1;
469 unsigned int polling_mode :1;
68e7fffc 470 unsigned int msi :1;
a6a950a8 471 unsigned int irq_pending_warned :1;
6ce4a3bc 472 unsigned int probing :1; /* codec probing phase */
27fe48d9 473 unsigned int snoop:1;
52409aa6 474 unsigned int align_buffer_size:1;
43bbb6cc
TI		 475
476 /* for debugging */
feb27340 477 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 478
479 /* for pending irqs */
480 struct work_struct irq_pending_work;
0cbf0098
TI		 481
482 /* reboot notifier (for mysterious hangup problem at power-down) */
483 struct notifier_block reboot_notifier;
1da177e4
LT		 484};
485
07e4ca50
TI		 486/* driver types */
487enum {
488 AZX_DRIVER_ICH,
32679f95 489 AZX_DRIVER_PCH,
4979bca9 490 AZX_DRIVER_SCH,
07e4ca50 491 AZX_DRIVER_ATI,
778b6e1b 492 AZX_DRIVER_ATIHDMI,
1815b34a 493 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 494 AZX_DRIVER_VIA,
495 AZX_DRIVER_SIS,
496 AZX_DRIVER_ULI,
da3fca21 497 AZX_DRIVER_NVIDIA,
f269002e 498 AZX_DRIVER_TERA,
14d34f16 499 AZX_DRIVER_CTX,
5ae763b1 500 AZX_DRIVER_CTHDA,
c4da29ca 501 AZX_DRIVER_GENERIC,
2f5983f2 502 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 503};
504
9477c58e
TI		 505/* driver quirks (capabilities) */
506/* bits 0-7 are used for indicating driver type */
507#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
508#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
509#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
510#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
511#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
512#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
513#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
514#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
515#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
516#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
517#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
518#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 519#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 520#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 521#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 522#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
9477c58e
TI		 523
524/* quirks for ATI SB / AMD Hudson */
525#define AZX_DCAPS_PRESET_ATI_SB \
526 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
527 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
528
529/* quirks for ATI/AMD HDMI */
530#define AZX_DCAPS_PRESET_ATI_HDMI \
531 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
532
533/* quirks for Nvidia */
534#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 535 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
536 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 537
5ae763b1
TI		 538#define AZX_DCAPS_PRESET_CTHDA \
539 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
540
07e4ca50
TI		 541static char *driver_short_names[] __devinitdata = {
542 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 543 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 544 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 545 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 546 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 547 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 548 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
549 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 550 [AZX_DRIVER_ULI] = "HDA ULI M5461",
551 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 552 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 553 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 554 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 555 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 556};
557
1da177e4
LT		 558/*
559 * macros for easy use
560 */
561#define azx_writel(chip,reg,value) \
562 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
563#define azx_readl(chip,reg) \
564 readl((chip)->remap_addr + ICH6_REG_##reg)
565#define azx_writew(chip,reg,value) \
566 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
567#define azx_readw(chip,reg) \
568 readw((chip)->remap_addr + ICH6_REG_##reg)
569#define azx_writeb(chip,reg,value) \
570 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
571#define azx_readb(chip,reg) \
572 readb((chip)->remap_addr + ICH6_REG_##reg)
573
574#define azx_sd_writel(dev,reg,value) \
575 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
576#define azx_sd_readl(dev,reg) \
577 readl((dev)->sd_addr + ICH6_REG_##reg)
578#define azx_sd_writew(dev,reg,value) \
579 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
580#define azx_sd_readw(dev,reg) \
581 readw((dev)->sd_addr + ICH6_REG_##reg)
582#define azx_sd_writeb(dev,reg,value) \
583 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
584#define azx_sd_readb(dev,reg) \
585 readb((dev)->sd_addr + ICH6_REG_##reg)
586
587/* for pcm support */
a98f90fd 588#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 589
27fe48d9
TI		 590#ifdef CONFIG_X86
591static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
592{
593 if (azx_snoop(chip))
594 return;
595 if (addr && size) {
596 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
597 if (on)
598 set_memory_wc((unsigned long)addr, pages);
599 else
600 set_memory_wb((unsigned long)addr, pages);
601 }
602}
603
604static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
605 bool on)
606{
607 __mark_pages_wc(chip, buf->area, buf->bytes, on);
608}
609static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
610 struct snd_pcm_runtime *runtime, bool on)
611{
612 if (azx_dev->wc_marked != on) {
613 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
614 azx_dev->wc_marked = on;
615 }
616}
617#else
618/* NOP for other archs */
619static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
620 bool on)
621{
622}
623static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
624 struct snd_pcm_runtime *runtime, bool on)
625{
626}
627#endif
628
68e7fffc 629static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 630static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 631/*
632 * Interface for HD codec
633 */
634
1da177e4
LT		 635/*
636 * CORB / RIRB interface
637 */
a98f90fd 638static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 639{
640 int err;
641
642 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 643 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
644 snd_dma_pci_data(chip->pci),
1da177e4
LT		 645 PAGE_SIZE, &chip->rb);
646 if (err < 0) {
647 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
648 return err;
649 }
27fe48d9 650 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 651 return 0;
652}
653
a98f90fd 654static void azx_init_cmd_io(struct azx *chip)
1da177e4 655{
cdb1fbf2 656 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 657 /* CORB set up */
658 chip->corb.addr = chip->rb.addr;
659 chip->corb.buf = (u32 *)chip->rb.area;
660 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 661 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 662
07e4ca50
TI		 663 /* set the corb size to 256 entries (ULI requires explicitly) */
664 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 665 /* set the corb write pointer to 0 */
666 azx_writew(chip, CORBWP, 0);
667 /* reset the corb hw read pointer */
b21fadb9 668 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 669 /* enable corb dma */
b21fadb9 670 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 671
672 /* RIRB set up */
673 chip->rirb.addr = chip->rb.addr + 2048;
674 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 675 chip->rirb.wp = chip->rirb.rp = 0;
676 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 677 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 678 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 679
07e4ca50
TI		 680 /* set the rirb size to 256 entries (ULI requires explicitly) */
681 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 682 /* reset the rirb hw write pointer */
b21fadb9 683 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 684 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 685 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 686 azx_writew(chip, RINTCNT, 0xc0);
687 else
688 azx_writew(chip, RINTCNT, 1);
1da177e4 689 /* enable rirb dma and response irq */
1da177e4 690 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 691 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 692}
693
a98f90fd 694static void azx_free_cmd_io(struct azx *chip)
1da177e4 695{
cdb1fbf2 696 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 697 /* disable ringbuffer DMAs */
698 azx_writeb(chip, RIRBCTL, 0);
699 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 700 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 701}
702
deadff16
WF		 703static unsigned int azx_command_addr(u32 cmd)
704{
705 unsigned int addr = cmd >> 28;
706
707 if (addr >= AZX_MAX_CODECS) {
708 snd_BUG();
709 addr = 0;
710 }
711
712 return addr;
713}
714
715static unsigned int azx_response_addr(u32 res)
716{
717 unsigned int addr = res & 0xf;
718
719 if (addr >= AZX_MAX_CODECS) {
720 snd_BUG();
721 addr = 0;
722 }
723
724 return addr;
1da177e4
LT		 725}
726
727/* send a command */
33fa35ed 728static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 729{
33fa35ed 730 struct azx *chip = bus->private_data;
deadff16 731 unsigned int addr = azx_command_addr(val);
1da177e4 732 unsigned int wp;
1da177e4 733
c32649fe
WF		 734 spin_lock_irq(&chip->reg_lock);
735
1da177e4
LT		 736 /* add command to corb */
737 wp = azx_readb(chip, CORBWP);
738 wp++;
739 wp %= ICH6_MAX_CORB_ENTRIES;
740
deadff16 741 chip->rirb.cmds[addr]++;
1da177e4
LT		 742 chip->corb.buf[wp] = cpu_to_le32(val);
743 azx_writel(chip, CORBWP, wp);
c32649fe 744
1da177e4
LT		 745 spin_unlock_irq(&chip->reg_lock);
746
747 return 0;
748}
749
750#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
751
752/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 753static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 754{
755 unsigned int rp, wp;
deadff16 756 unsigned int addr;
1da177e4
LT		 757 u32 res, res_ex;
758
759 wp = azx_readb(chip, RIRBWP);
760 if (wp == chip->rirb.wp)
761 return;
762 chip->rirb.wp = wp;
deadff16 763
1da177e4
LT		 764 while (chip->rirb.rp != wp) {
765 chip->rirb.rp++;
766 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
767
768 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
769 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
770 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 771 addr = azx_response_addr(res_ex);
1da177e4
LT		 772 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
773 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 774 else if (chip->rirb.cmds[addr]) {
775 chip->rirb.res[addr] = res;
2add9b92 776 smp_wmb();
deadff16 777 chip->rirb.cmds[addr]--;
e310bb06
WF		 778 } else
779 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
780 "last cmd=%#08x\n",
781 res, res_ex,
782 chip->last_cmd[addr]);
1da177e4
LT		 783 }
784}
785
786/* receive a response */
deadff16
WF		 787static unsigned int azx_rirb_get_response(struct hda_bus *bus,
788 unsigned int addr)
1da177e4 789{
33fa35ed 790 struct azx *chip = bus->private_data;
5c79b1f8 791 unsigned long timeout;
1eb6dc7d 792 int do_poll = 0;
1da177e4 793
5c79b1f8
TI		 794 again:
795 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 796 for (;;) {
1eb6dc7d 797 if (chip->polling_mode || do_poll) {
e96224ae
TI		 798 spin_lock_irq(&chip->reg_lock);
799 azx_update_rirb(chip);
800 spin_unlock_irq(&chip->reg_lock);
801 }
deadff16 802 if (!chip->rirb.cmds[addr]) {
2add9b92 803 smp_rmb();
b613291f 804 bus->rirb_error = 0;
1eb6dc7d
ML		 805
806 if (!do_poll)
807 chip->poll_count = 0;
deadff16 808 return chip->rirb.res[addr]; /* the last value */
2add9b92 809 }
28a0d9df
TI		 810 if (time_after(jiffies, timeout))
811 break;
33fa35ed 812 if (bus->needs_damn_long_delay)
52987656
TI		 813 msleep(2); /* temporary workaround */
814 else {
815 udelay(10);
816 cond_resched();
817 }
28a0d9df 818 }
5c79b1f8 819
1eb6dc7d
ML		 820 if (!chip->polling_mode && chip->poll_count < 2) {
821 snd_printdd(SFX "azx_get_response timeout, "
822 "polling the codec once: last cmd=0x%08x\n",
823 chip->last_cmd[addr]);
824 do_poll = 1;
825 chip->poll_count++;
826 goto again;
827 }
828
829
23c4a881
TI		 830 if (!chip->polling_mode) {
831 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
832 "switching to polling mode: last cmd=0x%08x\n",
833 chip->last_cmd[addr]);
834 chip->polling_mode = 1;
835 goto again;
836 }
837
68e7fffc 838 if (chip->msi) {
4abc1cc2 839 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 840 "disabling MSI: last cmd=0x%08x\n",
841 chip->last_cmd[addr]);
68e7fffc
TI		 842 free_irq(chip->irq, chip);
843 chip->irq = -1;
844 pci_disable_msi(chip->pci);
845 chip->msi = 0;
b613291f
TI		 846 if (azx_acquire_irq(chip, 1) < 0) {
847 bus->rirb_error = 1;
68e7fffc 848 return -1;
b613291f 849 }
68e7fffc
TI		 850 goto again;
851 }
852
6ce4a3bc
TI		 853 if (chip->probing) {
854 /* If this critical timeout happens during the codec probing
855 * phase, this is likely an access to a non-existing codec
856 * slot. Better to return an error and reset the system.
857 */
858 return -1;
859 }
860
8dd78330
TI		 861 /* a fatal communication error; need either to reset or to fallback
862 * to the single_cmd mode
863 */
b613291f 864 bus->rirb_error = 1;
b20f3b83 865 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 866 bus->response_reset = 1;
867 return -1; /* give a chance to retry */
868 }
869
870 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
871 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 872 chip->last_cmd[addr]);
8dd78330
TI		 873 chip->single_cmd = 1;
874 bus->response_reset = 0;
1a696978 875 /* release CORB/RIRB */
4fcd3920 876 azx_free_cmd_io(chip);
1a696978
TI		 877 /* disable unsolicited responses */
878 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 879 return -1;
1da177e4
LT		 880}
881
1da177e4
LT		 882/*
883 * Use the single immediate command instead of CORB/RIRB for simplicity
884 *
885 * Note: according to Intel, this is not preferred use. The command was
886 * intended for the BIOS only, and may get confused with unsolicited
887 * responses. So, we shouldn't use it for normal operation from the
888 * driver.
889 * I left the codes, however, for debugging/testing purposes.
890 */
891
b05a7d4f 892/* receive a response */
deadff16 893static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 894{
895 int timeout = 50;
896
897 while (timeout--) {
898 /* check IRV busy bit */
899 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
900 /* reuse rirb.res as the response return value */
deadff16 901 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 902 return 0;
903 }
904 udelay(1);
905 }
906 if (printk_ratelimit())
907 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
908 azx_readw(chip, IRS));
deadff16 909 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 910 return -EIO;
911}
912
1da177e4 913/* send a command */
33fa35ed 914static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 915{
33fa35ed 916 struct azx *chip = bus->private_data;
deadff16 917 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 918 int timeout = 50;
919
8dd78330 920 bus->rirb_error = 0;
1da177e4
LT		 921 while (timeout--) {
922 /* check ICB busy bit */
d01ce99f 923 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 924 /* Clear IRV valid bit */
d01ce99f
TI		 925 azx_writew(chip, IRS, azx_readw(chip, IRS) |
926 ICH6_IRS_VALID);
1da177e4 927 azx_writel(chip, IC, val);
d01ce99f
TI		 928 azx_writew(chip, IRS, azx_readw(chip, IRS) |
929 ICH6_IRS_BUSY);
deadff16 930 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 931 }
932 udelay(1);
933 }
1cfd52bc
MB		 934 if (printk_ratelimit())
935 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
936 azx_readw(chip, IRS), val);
1da177e4
LT		 937 return -EIO;
938}
939
940/* receive a response */
deadff16
WF		 941static unsigned int azx_single_get_response(struct hda_bus *bus,
942 unsigned int addr)
1da177e4 943{
33fa35ed 944 struct azx *chip = bus->private_data;
deadff16 945 return chip->rirb.res[addr];
1da177e4
LT		 946}
947
111d3af5
TI		 948/*
949 * The below are the main callbacks from hda_codec.
950 *
951 * They are just the skeleton to call sub-callbacks according to the
952 * current setting of chip->single_cmd.
953 */
954
955/* send a command */
33fa35ed 956static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 957{
33fa35ed 958 struct azx *chip = bus->private_data;
43bbb6cc 959
feb27340 960 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 961 if (chip->single_cmd)
33fa35ed 962 return azx_single_send_cmd(bus, val);
111d3af5 963 else
33fa35ed 964 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 965}
966
967/* get a response */
deadff16
WF		 968static unsigned int azx_get_response(struct hda_bus *bus,
969 unsigned int addr)
111d3af5 970{
33fa35ed 971 struct azx *chip = bus->private_data;
111d3af5 972 if (chip->single_cmd)
deadff16 973 return azx_single_get_response(bus, addr);
111d3af5 974 else
deadff16 975 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 976}
977
cb53c626 978#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 979static void azx_power_notify(struct hda_bus *bus);
cb53c626 980#endif
111d3af5 981
1da177e4 982/* reset codec link */
cd508fe5 983static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 984{
985 int count;
986
cd508fe5
JK		 987 if (!full_reset)
988 goto __skip;
989
e8a7f136
DT		 990 /* clear STATESTS */
991 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
992
1da177e4
LT		 993 /* reset controller */
994 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
995
996 count = 50;
997 while (azx_readb(chip, GCTL) && --count)
998 msleep(1);
999
1000 /* delay for >= 100us for codec PLL to settle per spec
1001 * Rev 0.9 section 5.5.1
1002 */
1003 msleep(1);
1004
1005 /* Bring controller out of reset */
1006 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1007
1008 count = 50;
927fc866 1009 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1010 msleep(1);
1011
927fc866 1012 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1013 msleep(1);
1014
cd508fe5 1015 __skip:
1da177e4 1016 /* check to see if controller is ready */
927fc866 1017 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1018 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1019 return -EBUSY;
1020 }
1021
41e2fce4 1022 /* Accept unsolicited responses */
1a696978
TI		 1023 if (!chip->single_cmd)
1024 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1025 ICH6_GCTL_UNSOL);
41e2fce4 1026
1da177e4 1027 /* detect codecs */
927fc866 1028 if (!chip->codec_mask) {
1da177e4 1029 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1030 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1031 }
1032
1033 return 0;
1034}
1035
1036
1037/*
1038 * Lowlevel interface
1039 */
1040
1041/* enable interrupts */
a98f90fd 1042static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1043{
1044 /* enable controller CIE and GIE */
1045 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1046 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1047}
1048
1049/* disable interrupts */
a98f90fd 1050static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1051{
1052 int i;
1053
1054 /* disable interrupts in stream descriptor */
07e4ca50 1055 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1056 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1057 azx_sd_writeb(azx_dev, SD_CTL,
1058 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1059 }
1060
1061 /* disable SIE for all streams */
1062 azx_writeb(chip, INTCTL, 0);
1063
1064 /* disable controller CIE and GIE */
1065 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1066 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1067}
1068
1069/* clear interrupts */
a98f90fd 1070static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1071{
1072 int i;
1073
1074 /* clear stream status */
07e4ca50 1075 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1076 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1077 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1078 }
1079
1080 /* clear STATESTS */
1081 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1082
1083 /* clear rirb status */
1084 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1085
1086 /* clear int status */
1087 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1088}
1089
1090/* start a stream */
a98f90fd 1091static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1092{
0e153474
JC		 1093 /*
1094 * Before stream start, initialize parameter
1095 */
1096 azx_dev->insufficient = 1;
1097
1da177e4 1098 /* enable SIE */
ccc5df05
WN		 1099 azx_writel(chip, INTCTL,
1100 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1101 /* set DMA start and interrupt mask */
1102 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1103 SD_CTL_DMA_START | SD_INT_MASK);
1104}
1105
1dddab40
TI		 1106/* stop DMA */
1107static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1108{
1da177e4
LT		 1109 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1110 ~(SD_CTL_DMA_START | SD_INT_MASK));
1111 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1112}
1113
1114/* stop a stream */
1115static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1116{
1117 azx_stream_clear(chip, azx_dev);
1da177e4 1118 /* disable SIE */
ccc5df05
WN		 1119 azx_writel(chip, INTCTL,
1120 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1121}
1122
1123
1124/*
cb53c626 1125 * reset and start the controller registers
1da177e4 1126 */
cd508fe5 1127static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1128{
cb53c626
TI		 1129 if (chip->initialized)
1130 return;
1da177e4
LT		 1131
1132 /* reset controller */
cd508fe5 1133 azx_reset(chip, full_reset);
1da177e4
LT		 1134
1135 /* initialize interrupts */
1136 azx_int_clear(chip);
1137 azx_int_enable(chip);
1138
1139 /* initialize the codec command I/O */
1a696978
TI		 1140 if (!chip->single_cmd)
1141 azx_init_cmd_io(chip);
1da177e4 1142
0be3b5d3
TI		 1143 /* program the position buffer */
1144 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1145 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1146
cb53c626
TI		 1147 chip->initialized = 1;
1148}
1149
1150/*
1151 * initialize the PCI registers
1152 */
1153/* update bits in a PCI register byte */
1154static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1155 unsigned char mask, unsigned char val)
1156{
1157 unsigned char data;
1158
1159 pci_read_config_byte(pci, reg, &data);
1160 data &= ~mask;
1161 data |= (val & mask);
1162 pci_write_config_byte(pci, reg, data);
1163}
1164
1165static void azx_init_pci(struct azx *chip)
1166{
1167 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1168 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1169 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1170 * codecs.
1171 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1172 */
46f2cc80 1173 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1174 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1175 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1176 }
cb53c626 1177
9477c58e
TI		 1178 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1179 * we need to enable snoop.
1180 */
1181 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1182 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1183 update_pci_byte(chip->pci,
27fe48d9
TI		 1184 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1185 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1186 }
1187
1188 /* For NVIDIA HDA, enable snoop */
1189 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1190 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1191 update_pci_byte(chip->pci,
1192 NVIDIA_HDA_TRANSREG_ADDR,
1193 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1194 update_pci_byte(chip->pci,
1195 NVIDIA_HDA_ISTRM_COH,
1196 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1197 update_pci_byte(chip->pci,
1198 NVIDIA_HDA_OSTRM_COH,
1199 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1200 }
1201
1202 /* Enable SCH/PCH snoop if needed */
1203 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1204 unsigned short snoop;
90a5ad52 1205 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1206 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1207 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1208 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1209 if (!azx_snoop(chip))
1210 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1211 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1212 pci_read_config_word(chip->pci,
1213 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1214 }
27fe48d9
TI		 1215 snd_printdd(SFX "SCH snoop: %s\n",
1216 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1217 ? "Disabled" : "Enabled");
da3fca21 1218 }
1da177e4
LT		 1219}
1220
1221
9ad593f6
TI		 1222static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1223
1da177e4
LT		 1224/*
1225 * interrupt handler
1226 */
7d12e780 1227static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1228{
a98f90fd
TI		 1229 struct azx *chip = dev_id;
1230 struct azx_dev *azx_dev;
1da177e4 1231 u32 status;
9ef04066 1232 u8 sd_status;
fa00e046 1233 int i, ok;
1da177e4
LT		 1234
1235 spin_lock(&chip->reg_lock);
1236
1237 status = azx_readl(chip, INTSTS);
1238 if (status == 0) {
1239 spin_unlock(&chip->reg_lock);
1240 return IRQ_NONE;
1241 }
1242
07e4ca50 1243 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1244 azx_dev = &chip->azx_dev[i];
1245 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1246 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1247 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1248 if (!azx_dev->substream || !azx_dev->running ||
1249 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1250 continue;
1251 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1252 ok = azx_position_ok(chip, azx_dev);
1253 if (ok == 1) {
9ad593f6 1254 azx_dev->irq_pending = 0;
1da177e4
LT		 1255 spin_unlock(&chip->reg_lock);
1256 snd_pcm_period_elapsed(azx_dev->substream);
1257 spin_lock(&chip->reg_lock);
fa00e046 1258 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1259 /* bogus IRQ, process it later */
1260 azx_dev->irq_pending = 1;
6acaed38
TI		 1261 queue_work(chip->bus->workq,
1262 &chip->irq_pending_work);
1da177e4
LT		 1263 }
1264 }
1265 }
1266
1267 /* clear rirb int */
1268 status = azx_readb(chip, RIRBSTS);
1269 if (status & RIRB_INT_MASK) {
14d34f16 1270 if (status & RIRB_INT_RESPONSE) {
9477c58e 1271 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1272 udelay(80);
1da177e4 1273 azx_update_rirb(chip);
14d34f16 1274 }
1da177e4
LT		 1275 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1276 }
1277
1278#if 0
1279 /* clear state status int */
1280 if (azx_readb(chip, STATESTS) & 0x04)
1281 azx_writeb(chip, STATESTS, 0x04);
1282#endif
1283 spin_unlock(&chip->reg_lock);
1284
1285 return IRQ_HANDLED;
1286}
1287
1288
675f25d4
TI		 1289/*
1290 * set up a BDL entry
1291 */
5ae763b1
TI		 1292static int setup_bdle(struct azx *chip,
1293 struct snd_pcm_substream *substream,
675f25d4
TI		 1294 struct azx_dev *azx_dev, u32 **bdlp,
1295 int ofs, int size, int with_ioc)
1296{
675f25d4
TI		 1297 u32 *bdl = *bdlp;
1298
1299 while (size > 0) {
1300 dma_addr_t addr;
1301 int chunk;
1302
1303 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1304 return -EINVAL;
1305
77a23f26 1306 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1307 /* program the address field of the BDL entry */
1308 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1309 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1310 /* program the size field of the BDL entry */
fc4abee8 1311 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1312 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1313 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1314 u32 remain = 0x1000 - (ofs & 0xfff);
1315 if (chunk > remain)
1316 chunk = remain;
1317 }
675f25d4
TI		 1318 bdl[2] = cpu_to_le32(chunk);
1319 /* program the IOC to enable interrupt
1320 * only when the whole fragment is processed
1321 */
1322 size -= chunk;
1323 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1324 bdl += 4;
1325 azx_dev->frags++;
1326 ofs += chunk;
1327 }
1328 *bdlp = bdl;
1329 return ofs;
1330}
1331
1da177e4
LT		 1332/*
1333 * set up BDL entries
1334 */
555e219f
TI		 1335static int azx_setup_periods(struct azx *chip,
1336 struct snd_pcm_substream *substream,
4ce107b9 1337 struct azx_dev *azx_dev)
1da177e4 1338{
4ce107b9
TI		 1339 u32 *bdl;
1340 int i, ofs, periods, period_bytes;
555e219f 1341 int pos_adj;
1da177e4
LT		 1342
1343 /* reset BDL address */
1344 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1345 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1346
97b71c94 1347 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1348 periods = azx_dev->bufsize / period_bytes;
1349
1da177e4 1350 /* program the initial BDL entries */
4ce107b9
TI		 1351 bdl = (u32 *)azx_dev->bdl.area;
1352 ofs = 0;
1353 azx_dev->frags = 0;
555e219f
TI		 1354 pos_adj = bdl_pos_adj[chip->dev_index];
1355 if (pos_adj > 0) {
675f25d4 1356 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1357 int pos_align = pos_adj;
555e219f 1358 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1359 if (!pos_adj)
e785d3d8
TI		 1360 pos_adj = pos_align;
1361 else
1362 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1363 pos_align;
675f25d4
TI		 1364 pos_adj = frames_to_bytes(runtime, pos_adj);
1365 if (pos_adj >= period_bytes) {
4abc1cc2 1366 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1367 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1368 pos_adj = 0;
1369 } else {
5ae763b1 1370 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1371 &bdl, ofs, pos_adj,
1372 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1373 if (ofs < 0)
1374 goto error;
4ce107b9 1375 }
555e219f
TI		 1376 } else
1377 pos_adj = 0;
675f25d4
TI		 1378 for (i = 0; i < periods; i++) {
1379 if (i == periods - 1 && pos_adj)
5ae763b1 1380 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1381 period_bytes - pos_adj, 0);
1382 else
5ae763b1 1383 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1384 period_bytes,
1385 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1386 if (ofs < 0)
1387 goto error;
1da177e4 1388 }
4ce107b9 1389 return 0;
675f25d4
TI		 1390
1391 error:
4abc1cc2 1392 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1393 azx_dev->bufsize, period_bytes);
675f25d4 1394 return -EINVAL;
1da177e4
LT		 1395}
1396
1dddab40
TI		 1397/* reset stream */
1398static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1399{
1400 unsigned char val;
1401 int timeout;
1402
1dddab40
TI		 1403 azx_stream_clear(chip, azx_dev);
1404
d01ce99f
TI		 1405 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1406 SD_CTL_STREAM_RESET);
1da177e4
LT		 1407 udelay(3);
1408 timeout = 300;
1409 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1410 --timeout)
1411 ;
1412 val &= ~SD_CTL_STREAM_RESET;
1413 azx_sd_writeb(azx_dev, SD_CTL, val);
1414 udelay(3);
1415
1416 timeout = 300;
1417 /* waiting for hardware to report that the stream is out of reset */
1418 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1419 --timeout)
1420 ;
fa00e046
JK		 1421
1422 /* reset first position - may not be synced with hw at this time */
1423 *azx_dev->posbuf = 0;
1dddab40 1424}
1da177e4 1425
1dddab40
TI		 1426/*
1427 * set up the SD for streaming
1428 */
1429static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1430{
27fe48d9 1431 unsigned int val;
1dddab40
TI		 1432 /* make sure the run bit is zero for SD */
1433 azx_stream_clear(chip, azx_dev);
1da177e4 1434 /* program the stream_tag */
27fe48d9
TI		 1435 val = azx_sd_readl(azx_dev, SD_CTL);
1436 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1437 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1438 if (!azx_snoop(chip))
1439 val |= SD_CTL_TRAFFIC_PRIO;
1440 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1441
1442 /* program the length of samples in cyclic buffer */
1443 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1444
1445 /* program the stream format */
1446 /* this value needs to be the same as the one programmed */
1447 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1448
1449 /* program the stream LVI (last valid index) of the BDL */
1450 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1451
1452 /* program the BDL address */
1453 /* lower BDL address */
4ce107b9 1454 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1455 /* upper BDL address */
766979e0 1456 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1457
0be3b5d3 1458 /* enable the position buffer */
4cb36310
DH		 1459 if (chip->position_fix[0] != POS_FIX_LPIB ||
1460 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1461 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1462 azx_writel(chip, DPLBASE,
1463 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1464 }
c74db86b 1465
1da177e4 1466 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1467 azx_sd_writel(azx_dev, SD_CTL,
1468 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1469
1470 return 0;
1471}
1472
6ce4a3bc
TI		 1473/*
1474 * Probe the given codec address
1475 */
1476static int probe_codec(struct azx *chip, int addr)
1477{
1478 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1479 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1480 unsigned int res;
1481
a678cdee 1482 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1483 chip->probing = 1;
1484 azx_send_cmd(chip->bus, cmd);
deadff16 1485 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1486 chip->probing = 0;
a678cdee 1487 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1488 if (res == -1)
1489 return -EIO;
4abc1cc2 1490 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1491 return 0;
1492}
1493
33fa35ed
TI		 1494static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1495 struct hda_pcm *cpcm);
6ce4a3bc 1496static void azx_stop_chip(struct azx *chip);
1da177e4 1497
8dd78330
TI		 1498static void azx_bus_reset(struct hda_bus *bus)
1499{
1500 struct azx *chip = bus->private_data;
8dd78330
TI		 1501
1502 bus->in_reset = 1;
1503 azx_stop_chip(chip);
cd508fe5 1504 azx_init_chip(chip, 1);
65f75983 1505#ifdef CONFIG_PM
8dd78330 1506 if (chip->initialized) {
01b65bfb
TI		 1507 struct azx_pcm *p;
1508 list_for_each_entry(p, &chip->pcm_list, list)
1509 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1510 snd_hda_suspend(chip->bus);
1511 snd_hda_resume(chip->bus);
1512 }
65f75983 1513#endif
8dd78330
TI		 1514 bus->in_reset = 0;
1515}
1516
1da177e4
LT		 1517/*
1518 * Codec initialization
1519 */
1520
2f5983f2
TI		 1521/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1522static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
7445dfc1 1523 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1524 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1525};
1526
a1e21c90 1527static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1528{
1529 struct hda_bus_template bus_temp;
34c25350
TI		 1530 int c, codecs, err;
1531 int max_slots;
1da177e4
LT		 1532
1533 memset(&bus_temp, 0, sizeof(bus_temp));
1534 bus_temp.private_data = chip;
1535 bus_temp.modelname = model;
1536 bus_temp.pci = chip->pci;
111d3af5
TI		 1537 bus_temp.ops.command = azx_send_cmd;
1538 bus_temp.ops.get_response = azx_get_response;
176d5335 1539 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1540 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1541#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1542 bus_temp.power_save = &power_save;
cb53c626
TI		 1543 bus_temp.ops.pm_notify = azx_power_notify;
1544#endif
1da177e4 1545
d01ce99f
TI		 1546 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1547 if (err < 0)
1da177e4
LT		 1548 return err;
1549
9477c58e
TI		 1550 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1551 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1552 chip->bus->needs_damn_long_delay = 1;
9477c58e 1553 }
dc9c8e21 1554
34c25350 1555 codecs = 0;
2f5983f2
TI		 1556 max_slots = azx_max_codecs[chip->driver_type];
1557 if (!max_slots)
7445dfc1 1558 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1559
1560 /* First try to probe all given codec slots */
1561 for (c = 0; c < max_slots; c++) {
f1eaaeec 1562 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1563 if (probe_codec(chip, c) < 0) {
1564 /* Some BIOSen give you wrong codec addresses
1565 * that don't exist
1566 */
4abc1cc2
TI		 1567 snd_printk(KERN_WARNING SFX
1568 "Codec #%d probe error; "
6ce4a3bc
TI		 1569 "disabling it...\n", c);
1570 chip->codec_mask &= ~(1 << c);
1571 /* More badly, accessing to a non-existing
1572 * codec often screws up the controller chip,
2448158e 1573 * and disturbs the further communications.
6ce4a3bc
TI		 1574 * Thus if an error occurs during probing,
1575 * better to reset the controller chip to
1576 * get back to the sanity state.
1577 */
1578 azx_stop_chip(chip);
cd508fe5 1579 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1580 }
1581 }
1582 }
1583
d507cd66
TI		 1584 /* AMD chipsets often cause the communication stalls upon certain
1585 * sequence like the pin-detection. It seems that forcing the synced
1586 * access works around the stall. Grrr...
1587 */
9477c58e
TI		 1588 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1589 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1590 chip->bus->sync_write = 1;
1591 chip->bus->allow_bus_reset = 1;
1592 }
1593
6ce4a3bc 1594 /* Then create codec instances */
34c25350 1595 for (c = 0; c < max_slots; c++) {
f1eaaeec 1596 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1597 struct hda_codec *codec;
a1e21c90 1598 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1599 if (err < 0)
1600 continue;
2dca0bba 1601 codec->beep_mode = chip->beep_mode;
1da177e4 1602 codecs++;
19a982b6
TI		 1603 }
1604 }
1605 if (!codecs) {
1da177e4
LT		 1606 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1607 return -ENXIO;
1608 }
a1e21c90
TI		 1609 return 0;
1610}
1da177e4 1611
a1e21c90
TI		 1612/* configure each codec instance */
1613static int __devinit azx_codec_configure(struct azx *chip)
1614{
1615 struct hda_codec *codec;
1616 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1617 snd_hda_codec_configure(codec);
1618 }
1da177e4
LT		 1619 return 0;
1620}
1621
1622
1623/*
1624 * PCM support
1625 */
1626
1627/* assign a stream for the PCM */
ef18bede
WF		 1628static inline struct azx_dev *
1629azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1630{
07e4ca50 1631 int dev, i, nums;
ef18bede 1632 struct azx_dev *res = NULL;
d5cf9911
TI		 1633 /* make a non-zero unique key for the substream */
1634 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1635 (substream->stream + 1);
ef18bede
WF		 1636
1637 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1638 dev = chip->playback_index_offset;
1639 nums = chip->playback_streams;
1640 } else {
1641 dev = chip->capture_index_offset;
1642 nums = chip->capture_streams;
1643 }
1644 for (i = 0; i < nums; i++, dev++)
d01ce99f 1645 if (!chip->azx_dev[dev].opened) {
ef18bede 1646 res = &chip->azx_dev[dev];
d5cf9911 1647 if (res->assigned_key == key)
ef18bede 1648 break;
1da177e4 1649 }
ef18bede
WF		 1650 if (res) {
1651 res->opened = 1;
d5cf9911 1652 res->assigned_key = key;
ef18bede
WF		 1653 }
1654 return res;
1da177e4
LT		 1655}
1656
1657/* release the assigned stream */
a98f90fd 1658static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1659{
1660 azx_dev->opened = 0;
1661}
1662
a98f90fd 1663static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1664 .info = (SNDRV_PCM_INFO_MMAP |
1665 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1666 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1667 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1668 /* No full-resume yet implemented */
1669 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1670 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1671 SNDRV_PCM_INFO_SYNC_START |
1672 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1673 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1674 .rates = SNDRV_PCM_RATE_48000,
1675 .rate_min = 48000,
1676 .rate_max = 48000,
1677 .channels_min = 2,
1678 .channels_max = 2,
1679 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1680 .period_bytes_min = 128,
1681 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1682 .periods_min = 2,
1683 .periods_max = AZX_MAX_FRAG,
1684 .fifo_size = 0,
1685};
1686
a98f90fd 1687static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1688{
1689 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1690 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1691 struct azx *chip = apcm->chip;
1692 struct azx_dev *azx_dev;
1693 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1694 unsigned long flags;
1695 int err;
2ae66c26 1696 int buff_step;
1da177e4 1697
62932df8 1698 mutex_lock(&chip->open_mutex);
ef18bede 1699 azx_dev = azx_assign_device(chip, substream);
1da177e4 1700 if (azx_dev == NULL) {
62932df8 1701 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1702 return -EBUSY;
1703 }
1704 runtime->hw = azx_pcm_hw;
1705 runtime->hw.channels_min = hinfo->channels_min;
1706 runtime->hw.channels_max = hinfo->channels_max;
1707 runtime->hw.formats = hinfo->formats;
1708 runtime->hw.rates = hinfo->rates;
1709 snd_pcm_limit_hw_rates(runtime);
1710 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1711 if (chip->align_buffer_size)
2ae66c26
PLB		 1712 /* constrain buffer sizes to be multiple of 128
1713 bytes. This is more efficient in terms of memory
1714 access but isn't required by the HDA spec and
1715 prevents users from specifying exact period/buffer
1716 sizes. For example for 44.1kHz, a period size set
1717 to 20ms will be rounded to 19.59ms. */
1718 buff_step = 128;
1719 else
1720 /* Don't enforce steps on buffer sizes, still need to
1721 be multiple of 4 bytes (HDA spec). Tested on Intel
1722 HDA controllers, may not work on all devices where
1723 option needs to be disabled */
1724 buff_step = 4;
1725
5f1545bc 1726 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1727 buff_step);
5f1545bc 1728 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1729 buff_step);
cb53c626 1730 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1731 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1732 if (err < 0) {
1da177e4 1733 azx_release_device(azx_dev);
cb53c626 1734 snd_hda_power_down(apcm->codec);
62932df8 1735 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1736 return err;
1737 }
70d321e6 1738 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1739 /* sanity check */
1740 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1741 snd_BUG_ON(!runtime->hw.channels_max) ||
1742 snd_BUG_ON(!runtime->hw.formats) ||
1743 snd_BUG_ON(!runtime->hw.rates)) {
1744 azx_release_device(azx_dev);
1745 hinfo->ops.close(hinfo, apcm->codec, substream);
1746 snd_hda_power_down(apcm->codec);
1747 mutex_unlock(&chip->open_mutex);
1748 return -EINVAL;
1749 }
1da177e4
LT		 1750 spin_lock_irqsave(&chip->reg_lock, flags);
1751 azx_dev->substream = substream;
1752 azx_dev->running = 0;
1753 spin_unlock_irqrestore(&chip->reg_lock, flags);
1754
1755 runtime->private_data = azx_dev;
850f0e52 1756 snd_pcm_set_sync(substream);
62932df8 1757 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1758 return 0;
1759}
1760
a98f90fd 1761static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1762{
1763 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1764 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1765 struct azx *chip = apcm->chip;
1766 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1767 unsigned long flags;
1768
62932df8 1769 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1770 spin_lock_irqsave(&chip->reg_lock, flags);
1771 azx_dev->substream = NULL;
1772 azx_dev->running = 0;
1773 spin_unlock_irqrestore(&chip->reg_lock, flags);
1774 azx_release_device(azx_dev);
1775 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1776 snd_hda_power_down(apcm->codec);
62932df8 1777 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1778 return 0;
1779}
1780
d01ce99f
TI		 1781static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1782 struct snd_pcm_hw_params *hw_params)
1da177e4 1783{
27fe48d9
TI		 1784 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1785 struct azx *chip = apcm->chip;
1786 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1787 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1788 int ret;
97b71c94 1789
27fe48d9 1790 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1791 azx_dev->bufsize = 0;
1792 azx_dev->period_bytes = 0;
1793 azx_dev->format_val = 0;
27fe48d9 1794 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1795 params_buffer_bytes(hw_params));
27fe48d9
TI		 1796 if (ret < 0)
1797 return ret;
1798 mark_runtime_wc(chip, azx_dev, runtime, true);
1799 return ret;
1da177e4
LT		 1800}
1801
a98f90fd 1802static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1803{
1804 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1805 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1806 struct azx *chip = apcm->chip;
1807 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1808 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1809
1810 /* reset BDL address */
1811 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1812 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1813 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1814 azx_dev->bufsize = 0;
1815 azx_dev->period_bytes = 0;
1816 azx_dev->format_val = 0;
1da177e4 1817
eb541337 1818 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1819
27fe48d9 1820 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1821 return snd_pcm_lib_free_pages(substream);
1822}
1823
a98f90fd 1824static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1825{
1826 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1827 struct azx *chip = apcm->chip;
1828 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1829 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1830 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1831 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1832 int err;
7c935976
SW		 1833 struct hda_spdif_out *spdif =
1834 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1835 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1836
fa00e046 1837 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1838 format_val = snd_hda_calc_stream_format(runtime->rate,
1839 runtime->channels,
1840 runtime->format,
32c168c8 1841 hinfo->maxbps,
7c935976 1842 ctls);
97b71c94 1843 if (!format_val) {
d01ce99f
TI		 1844 snd_printk(KERN_ERR SFX
1845 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1846 runtime->rate, runtime->channels, runtime->format);
1847 return -EINVAL;
1848 }
1849
97b71c94
TI		 1850 bufsize = snd_pcm_lib_buffer_bytes(substream);
1851 period_bytes = snd_pcm_lib_period_bytes(substream);
1852
4abc1cc2 1853 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1854 bufsize, format_val);
1855
1856 if (bufsize != azx_dev->bufsize ||
1857 period_bytes != azx_dev->period_bytes ||
1858 format_val != azx_dev->format_val) {
1859 azx_dev->bufsize = bufsize;
1860 azx_dev->period_bytes = period_bytes;
1861 azx_dev->format_val = format_val;
1862 err = azx_setup_periods(chip, substream, azx_dev);
1863 if (err < 0)
1864 return err;
1865 }
1866
e5463720
JK		 1867 /* wallclk has 24Mhz clock source */
1868 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1869 runtime->rate) * 1000);
1da177e4
LT		 1870 azx_setup_controller(chip, azx_dev);
1871 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1872 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1873 else
1874 azx_dev->fifo_size = 0;
1875
62b7e5e0
TI		 1876 stream_tag = azx_dev->stream_tag;
1877 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1878 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1879 stream_tag > chip->capture_streams)
1880 stream_tag -= chip->capture_streams;
1881 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1882 azx_dev->format_val, substream);
1da177e4
LT		 1883}
1884
a98f90fd 1885static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1886{
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1888 struct azx *chip = apcm->chip;
850f0e52
TI		 1889 struct azx_dev *azx_dev;
1890 struct snd_pcm_substream *s;
fa00e046 1891 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1892 int nwait, timeout;
1da177e4 1893
1da177e4 1894 switch (cmd) {
fa00e046
JK		 1895 case SNDRV_PCM_TRIGGER_START:
1896 rstart = 1;
1da177e4
LT		 1897 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1898 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1899 start = 1;
1da177e4
LT		 1900 break;
1901 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1902 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1903 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1904 start = 0;
1da177e4
LT		 1905 break;
1906 default:
850f0e52
TI		 1907 return -EINVAL;
1908 }
1909
1910 snd_pcm_group_for_each_entry(s, substream) {
1911 if (s->pcm->card != substream->pcm->card)
1912 continue;
1913 azx_dev = get_azx_dev(s);
1914 sbits |= 1 << azx_dev->index;
1915 nsync++;
1916 snd_pcm_trigger_done(s, substream);
1917 }
1918
1919 spin_lock(&chip->reg_lock);
1920 if (nsync > 1) {
1921 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1922 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1923 azx_writel(chip, OLD_SSYNC,
1924 azx_readl(chip, OLD_SSYNC) | sbits);
1925 else
1926 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1927 }
1928 snd_pcm_group_for_each_entry(s, substream) {
1929 if (s->pcm->card != substream->pcm->card)
1930 continue;
1931 azx_dev = get_azx_dev(s);
e5463720
JK		 1932 if (start) {
1933 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1934 if (!rstart)
1935 azx_dev->start_wallclk -=
1936 azx_dev->period_wallclk;
850f0e52 1937 azx_stream_start(chip, azx_dev);
e5463720 1938 } else {
850f0e52 1939 azx_stream_stop(chip, azx_dev);
e5463720 1940 }
850f0e52 1941 azx_dev->running = start;
1da177e4
LT		 1942 }
1943 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1944 if (start) {
1945 if (nsync == 1)
1946 return 0;
1947 /* wait until all FIFOs get ready */
1948 for (timeout = 5000; timeout; timeout--) {
1949 nwait = 0;
1950 snd_pcm_group_for_each_entry(s, substream) {
1951 if (s->pcm->card != substream->pcm->card)
1952 continue;
1953 azx_dev = get_azx_dev(s);
1954 if (!(azx_sd_readb(azx_dev, SD_STS) &
1955 SD_STS_FIFO_READY))
1956 nwait++;
1957 }
1958 if (!nwait)
1959 break;
1960 cpu_relax();
1961 }
1962 } else {
1963 /* wait until all RUN bits are cleared */
1964 for (timeout = 5000; timeout; timeout--) {
1965 nwait = 0;
1966 snd_pcm_group_for_each_entry(s, substream) {
1967 if (s->pcm->card != substream->pcm->card)
1968 continue;
1969 azx_dev = get_azx_dev(s);
1970 if (azx_sd_readb(azx_dev, SD_CTL) &
1971 SD_CTL_DMA_START)
1972 nwait++;
1973 }
1974 if (!nwait)
1975 break;
1976 cpu_relax();
1977 }
1da177e4 1978 }
850f0e52
TI		 1979 if (nsync > 1) {
1980 spin_lock(&chip->reg_lock);
1981 /* reset SYNC bits */
8b0bd226
TI		 1982 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1983 azx_writel(chip, OLD_SSYNC,
1984 azx_readl(chip, OLD_SSYNC) & ~sbits);
1985 else
1986 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 1987 spin_unlock(&chip->reg_lock);
1988 }
1989 return 0;
1da177e4
LT		 1990}
1991
0e153474
JC		 1992/* get the current DMA position with correction on VIA chips */
1993static unsigned int azx_via_get_position(struct azx *chip,
1994 struct azx_dev *azx_dev)
1995{
1996 unsigned int link_pos, mini_pos, bound_pos;
1997 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1998 unsigned int fifo_size;
1999
2000 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2001 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2002 /* Playback, no problem using link position */
2003 return link_pos;
2004 }
2005
2006 /* Capture */
2007 /* For new chipset,
2008 * use mod to get the DMA position just like old chipset
2009 */
2010 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2011 mod_dma_pos %= azx_dev->period_bytes;
2012
2013 /* azx_dev->fifo_size can't get FIFO size of in stream.
2014 * Get from base address + offset.
2015 */
2016 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2017
2018 if (azx_dev->insufficient) {
2019 /* Link position never gather than FIFO size */
2020 if (link_pos <= fifo_size)
2021 return 0;
2022
2023 azx_dev->insufficient = 0;
2024 }
2025
2026 if (link_pos <= fifo_size)
2027 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2028 else
2029 mini_pos = link_pos - fifo_size;
2030
2031 /* Find nearest previous boudary */
2032 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2033 mod_link_pos = link_pos % azx_dev->period_bytes;
2034 if (mod_link_pos >= fifo_size)
2035 bound_pos = link_pos - mod_link_pos;
2036 else if (mod_dma_pos >= mod_mini_pos)
2037 bound_pos = mini_pos - mod_mini_pos;
2038 else {
2039 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2040 if (bound_pos >= azx_dev->bufsize)
2041 bound_pos = 0;
2042 }
2043
2044 /* Calculate real DMA position we want */
2045 return bound_pos + mod_dma_pos;
2046}
2047
9ad593f6 2048static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2049 struct azx_dev *azx_dev,
2050 bool with_check)
1da177e4 2051{
1da177e4 2052 unsigned int pos;
4cb36310 2053 int stream = azx_dev->substream->stream;
1da177e4 2054
4cb36310
DH		 2055 switch (chip->position_fix[stream]) {
2056 case POS_FIX_LPIB:
2057 /* read LPIB */
2058 pos = azx_sd_readl(azx_dev, SD_LPIB);
2059 break;
2060 case POS_FIX_VIACOMBO:
0e153474 2061 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2062 break;
2063 default:
2064 /* use the position buffer */
2065 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2066 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2067 if (!pos || pos == (u32)-1) {
2068 printk(KERN_WARNING
2069 "hda-intel: Invalid position buffer, "
2070 "using LPIB read method instead.\n");
2071 chip->position_fix[stream] = POS_FIX_LPIB;
2072 pos = azx_sd_readl(azx_dev, SD_LPIB);
2073 } else
2074 chip->position_fix[stream] = POS_FIX_POSBUF;
2075 }
2076 break;
c74db86b 2077 }
4cb36310 2078
1da177e4
LT		 2079 if (pos >= azx_dev->bufsize)
2080 pos = 0;
9ad593f6
TI		 2081 return pos;
2082}
2083
2084static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2085{
2086 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2087 struct azx *chip = apcm->chip;
2088 struct azx_dev *azx_dev = get_azx_dev(substream);
2089 return bytes_to_frames(substream->runtime,
798cb7e8 2090 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2091}
2092
2093/*
2094 * Check whether the current DMA position is acceptable for updating
2095 * periods. Returns non-zero if it's OK.
2096 *
2097 * Many HD-audio controllers appear pretty inaccurate about
2098 * the update-IRQ timing. The IRQ is issued before actually the
2099 * data is processed. So, we need to process it afterwords in a
2100 * workqueue.
2101 */
2102static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2103{
e5463720 2104 u32 wallclk;
9ad593f6 2105 unsigned int pos;
beaffc39 2106 int stream;
9ad593f6 2107
f48f606d
JK		 2108 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2109 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2110 return -1; /* bogus (too early) interrupt */
fa00e046 2111
beaffc39 2112 stream = azx_dev->substream->stream;
798cb7e8 2113 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2114
d6d8bf54
TI		 2115 if (WARN_ONCE(!azx_dev->period_bytes,
2116 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2117 return -1; /* this shouldn't happen! */
edb39935 2118 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2119 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2120 /* NG - it's below the first next period boundary */
2121 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2122 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2123 return 1; /* OK, it's fine */
2124}
2125
2126/*
2127 * The work for pending PCM period updates.
2128 */
2129static void azx_irq_pending_work(struct work_struct *work)
2130{
2131 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2132 int i, pending, ok;
9ad593f6 2133
a6a950a8
TI		 2134 if (!chip->irq_pending_warned) {
2135 printk(KERN_WARNING
2136 "hda-intel: IRQ timing workaround is activated "
2137 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2138 chip->card->number);
2139 chip->irq_pending_warned = 1;
2140 }
2141
9ad593f6
TI		 2142 for (;;) {
2143 pending = 0;
2144 spin_lock_irq(&chip->reg_lock);
2145 for (i = 0; i < chip->num_streams; i++) {
2146 struct azx_dev *azx_dev = &chip->azx_dev[i];
2147 if (!azx_dev->irq_pending ||
2148 !azx_dev->substream ||
2149 !azx_dev->running)
2150 continue;
e5463720
JK		 2151 ok = azx_position_ok(chip, azx_dev);
2152 if (ok > 0) {
9ad593f6
TI		 2153 azx_dev->irq_pending = 0;
2154 spin_unlock(&chip->reg_lock);
2155 snd_pcm_period_elapsed(azx_dev->substream);
2156 spin_lock(&chip->reg_lock);
e5463720
JK		 2157 } else if (ok < 0) {
2158 pending = 0; /* too early */
9ad593f6
TI		 2159 } else
2160 pending++;
2161 }
2162 spin_unlock_irq(&chip->reg_lock);
2163 if (!pending)
2164 return;
08af495f 2165 msleep(1);
9ad593f6
TI		 2166 }
2167}
2168
2169/* clear irq_pending flags and assure no on-going workq */
2170static void azx_clear_irq_pending(struct azx *chip)
2171{
2172 int i;
2173
2174 spin_lock_irq(&chip->reg_lock);
2175 for (i = 0; i < chip->num_streams; i++)
2176 chip->azx_dev[i].irq_pending = 0;
2177 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2178}
2179
27fe48d9
TI		 2180#ifdef CONFIG_X86
2181static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2182 struct vm_area_struct *area)
2183{
2184 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2185 struct azx *chip = apcm->chip;
2186 if (!azx_snoop(chip))
2187 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2188 return snd_pcm_lib_default_mmap(substream, area);
2189}
2190#else
2191#define azx_pcm_mmap NULL
2192#endif
2193
a98f90fd 2194static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2195 .open = azx_pcm_open,
2196 .close = azx_pcm_close,
2197 .ioctl = snd_pcm_lib_ioctl,
2198 .hw_params = azx_pcm_hw_params,
2199 .hw_free = azx_pcm_hw_free,
2200 .prepare = azx_pcm_prepare,
2201 .trigger = azx_pcm_trigger,
2202 .pointer = azx_pcm_pointer,
27fe48d9 2203 .mmap = azx_pcm_mmap,
4ce107b9 2204 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2205};
2206
a98f90fd 2207static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2208{
176d5335
TI		 2209 struct azx_pcm *apcm = pcm->private_data;
2210 if (apcm) {
01b65bfb 2211 list_del(&apcm->list);
176d5335
TI		 2212 kfree(apcm);
2213 }
1da177e4
LT		 2214}
2215
acfa634f
TI		 2216#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2217
176d5335 2218static int
33fa35ed
TI		 2219azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2220 struct hda_pcm *cpcm)
1da177e4 2221{
33fa35ed 2222 struct azx *chip = bus->private_data;
a98f90fd 2223 struct snd_pcm *pcm;
1da177e4 2224 struct azx_pcm *apcm;
176d5335 2225 int pcm_dev = cpcm->device;
acfa634f 2226 unsigned int size;
176d5335 2227 int s, err;
1da177e4 2228
01b65bfb
TI		 2229 list_for_each_entry(apcm, &chip->pcm_list, list) {
2230 if (apcm->pcm->device == pcm_dev) {
2231 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2232 return -EBUSY;
2233 }
176d5335
TI		 2234 }
2235 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2236 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2237 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2238 &pcm);
2239 if (err < 0)
2240 return err;
18cb7109 2241 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2242 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2243 if (apcm == NULL)
2244 return -ENOMEM;
2245 apcm->chip = chip;
01b65bfb 2246 apcm->pcm = pcm;
1da177e4 2247 apcm->codec = codec;
1da177e4
LT		 2248 pcm->private_data = apcm;
2249 pcm->private_free = azx_pcm_free;
176d5335
TI		 2250 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2251 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2252 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2253 cpcm->pcm = pcm;
2254 for (s = 0; s < 2; s++) {
2255 apcm->hinfo[s] = &cpcm->stream[s];
2256 if (cpcm->stream[s].substreams)
2257 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2258 }
2259 /* buffer pre-allocation */
acfa634f
TI		 2260 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2261 if (size > MAX_PREALLOC_SIZE)
2262 size = MAX_PREALLOC_SIZE;
4ce107b9 2263 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2264 snd_dma_pci_data(chip->pci),
acfa634f 2265 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2266 return 0;
2267}
2268
2269/*
2270 * mixer creation - all stuff is implemented in hda module
2271 */
a98f90fd 2272static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2273{
2274 return snd_hda_build_controls(chip->bus);
2275}
2276
2277
2278/*
2279 * initialize SD streams
2280 */
a98f90fd 2281static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2282{
2283 int i;
2284
2285 /* initialize each stream (aka device)
d01ce99f
TI		 2286 * assign the starting bdl address to each stream (device)
2287 * and initialize
1da177e4 2288 */
07e4ca50 2289 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2290 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2291 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2292 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2293 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2294 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2295 azx_dev->sd_int_sta_mask = 1 << i;
2296 /* stream tag: must be non-zero and unique */
2297 azx_dev->index = i;
2298 azx_dev->stream_tag = i + 1;
2299 }
2300
2301 return 0;
2302}
2303
68e7fffc
TI		 2304static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2305{
437a5a46
TI		 2306 if (request_irq(chip->pci->irq, azx_interrupt,
2307 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2308 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2309 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2310 "disabling device\n", chip->pci->irq);
2311 if (do_disconnect)
2312 snd_card_disconnect(chip->card);
2313 return -1;
2314 }
2315 chip->irq = chip->pci->irq;
69e13418 2316 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2317 return 0;
2318}
2319
1da177e4 2320
cb53c626
TI		 2321static void azx_stop_chip(struct azx *chip)
2322{
95e99fda 2323 if (!chip->initialized)
cb53c626
TI		 2324 return;
2325
2326 /* disable interrupts */
2327 azx_int_disable(chip);
2328 azx_int_clear(chip);
2329
2330 /* disable CORB/RIRB */
2331 azx_free_cmd_io(chip);
2332
2333 /* disable position buffer */
2334 azx_writel(chip, DPLBASE, 0);
2335 azx_writel(chip, DPUBASE, 0);
2336
2337 chip->initialized = 0;
2338}
2339
2340#ifdef CONFIG_SND_HDA_POWER_SAVE
2341/* power-up/down the controller */
33fa35ed 2342static void azx_power_notify(struct hda_bus *bus)
cb53c626 2343{
33fa35ed 2344 struct azx *chip = bus->private_data;
cb53c626
TI		 2345 struct hda_codec *c;
2346 int power_on = 0;
2347
33fa35ed 2348 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2349 if (c->power_on) {
2350 power_on = 1;
2351 break;
2352 }
2353 }
2354 if (power_on)
cd508fe5 2355 azx_init_chip(chip, 1);
0287d970
WF		 2356 else if (chip->running && power_save_controller &&
2357 !bus->power_keep_link_on)
cb53c626 2358 azx_stop_chip(chip);
cb53c626 2359}
5c0b9bec
TI		 2360#endif /* CONFIG_SND_HDA_POWER_SAVE */
2361
2362#ifdef CONFIG_PM
2363/*
2364 * power management
2365 */
986862bd 2366
421a1252 2367static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2368{
421a1252
TI		 2369 struct snd_card *card = pci_get_drvdata(pci);
2370 struct azx *chip = card->private_data;
01b65bfb 2371 struct azx_pcm *p;
1da177e4 2372
421a1252 2373 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2374 azx_clear_irq_pending(chip);
01b65bfb
TI		 2375 list_for_each_entry(p, &chip->pcm_list, list)
2376 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2377 if (chip->initialized)
8dd78330 2378 snd_hda_suspend(chip->bus);
cb53c626 2379 azx_stop_chip(chip);
30b35399 2380 if (chip->irq >= 0) {
43001c95 2381 free_irq(chip->irq, chip);
30b35399
TI		 2382 chip->irq = -1;
2383 }
68e7fffc 2384 if (chip->msi)
43001c95 2385 pci_disable_msi(chip->pci);
421a1252
TI		 2386 pci_disable_device(pci);
2387 pci_save_state(pci);
30b35399 2388 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2389 return 0;
2390}
2391
421a1252 2392static int azx_resume(struct pci_dev *pci)
1da177e4 2393{
421a1252
TI		 2394 struct snd_card *card = pci_get_drvdata(pci);
2395 struct azx *chip = card->private_data;
1da177e4 2396
d14a7e0b
TI		 2397 pci_set_power_state(pci, PCI_D0);
2398 pci_restore_state(pci);
30b35399
TI		 2399 if (pci_enable_device(pci) < 0) {
2400 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2401 "disabling device\n");
2402 snd_card_disconnect(card);
2403 return -EIO;
2404 }
2405 pci_set_master(pci);
68e7fffc
TI		 2406 if (chip->msi)
2407 if (pci_enable_msi(pci) < 0)
2408 chip->msi = 0;
2409 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2410 return -EIO;
cb53c626 2411 azx_init_pci(chip);
d804ad92 2412
7f30830b 2413 azx_init_chip(chip, 1);
d804ad92 2414
1da177e4 2415 snd_hda_resume(chip->bus);
421a1252 2416 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2417 return 0;
2418}
2419#endif /* CONFIG_PM */
2420
2421
0cbf0098
TI		 2422/*
2423 * reboot notifier for hang-up problem at power-down
2424 */
2425static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2426{
2427 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2428 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2429 azx_stop_chip(chip);
2430 return NOTIFY_OK;
2431}
2432
2433static void azx_notifier_register(struct azx *chip)
2434{
2435 chip->reboot_notifier.notifier_call = azx_halt;
2436 register_reboot_notifier(&chip->reboot_notifier);
2437}
2438
2439static void azx_notifier_unregister(struct azx *chip)
2440{
2441 if (chip->reboot_notifier.notifier_call)
2442 unregister_reboot_notifier(&chip->reboot_notifier);
2443}
2444
1da177e4
LT		 2445/*
2446 * destructor
2447 */
a98f90fd 2448static int azx_free(struct azx *chip)
1da177e4 2449{
4ce107b9
TI		 2450 int i;
2451
0cbf0098
TI		 2452 azx_notifier_unregister(chip);
2453
ce43fbae 2454 if (chip->initialized) {
9ad593f6 2455 azx_clear_irq_pending(chip);
07e4ca50 2456 for (i = 0; i < chip->num_streams; i++)
1da177e4 2457 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2458 azx_stop_chip(chip);
1da177e4
LT		 2459 }
2460
f000fd80 2461 if (chip->irq >= 0)
1da177e4 2462 free_irq(chip->irq, (void*)chip);
68e7fffc 2463 if (chip->msi)
30b35399 2464 pci_disable_msi(chip->pci);
f079c25a
TI		 2465 if (chip->remap_addr)
2466 iounmap(chip->remap_addr);
1da177e4 2467
4ce107b9
TI		 2468 if (chip->azx_dev) {
2469 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2470 if (chip->azx_dev[i].bdl.area) {
2471 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2472 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2473 }
4ce107b9 2474 }
27fe48d9
TI		 2475 if (chip->rb.area) {
2476 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2477 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2478 }
2479 if (chip->posbuf.area) {
2480 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2481 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2482 }
1da177e4
LT		 2483 pci_release_regions(chip->pci);
2484 pci_disable_device(chip->pci);
07e4ca50 2485 kfree(chip->azx_dev);
1da177e4
LT		 2486 kfree(chip);
2487
2488 return 0;
2489}
2490
a98f90fd 2491static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2492{
2493 return azx_free(device->device_data);
2494}
2495
3372a153
TI		 2496/*
2497 * white/black-listing for position_fix
2498 */
623ec047 2499static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2500 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2501 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2502 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2503 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2504 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2505 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2506 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2507 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2508 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2509 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2510 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2511 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2512 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2513 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2514 {}
2515};
2516
2517static int __devinit check_position_fix(struct azx *chip, int fix)
2518{
2519 const struct snd_pci_quirk *q;
2520
c673ba1c
TI		 2521 switch (fix) {
2522 case POS_FIX_LPIB:
2523 case POS_FIX_POSBUF:
4cb36310 2524 case POS_FIX_VIACOMBO:
a6f2fd55 2525 case POS_FIX_COMBO:
c673ba1c
TI		 2526 return fix;
2527 }
2528
c673ba1c
TI		 2529 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2530 if (q) {
2531 printk(KERN_INFO
2532 "hda_intel: position_fix set to %d "
2533 "for device %04x:%04x\n",
2534 q->value, q->subvendor, q->subdevice);
2535 return q->value;
3372a153 2536 }
bdd9ef24
DH		 2537
2538 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2539 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2540 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2541 return POS_FIX_VIACOMBO;
9477c58e
TI		 2542 }
2543 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2544 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2545 return POS_FIX_LPIB;
bdd9ef24 2546 }
c673ba1c 2547 return POS_FIX_AUTO;
3372a153
TI		 2548}
2549
669ba27a
TI		 2550/*
2551 * black-lists for probe_mask
2552 */
2553static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2554 /* Thinkpad often breaks the controller communication when accessing
2555 * to the non-working (or non-existing) modem codec slot.
2556 */
2557 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2558 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2559 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2560 /* broken BIOS */
2561 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2562 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2563 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2564 /* forced codec slots */
93574844 2565 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2566 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2567 {}
2568};
2569
f1eaaeec
TI		 2570#define AZX_FORCE_CODEC_MASK 0x100
2571
5aba4f8e 2572static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2573{
2574 const struct snd_pci_quirk *q;
2575
f1eaaeec
TI		 2576 chip->codec_probe_mask = probe_mask[dev];
2577 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2578 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2579 if (q) {
2580 printk(KERN_INFO
2581 "hda_intel: probe_mask set to 0x%x "
2582 "for device %04x:%04x\n",
2583 q->value, q->subvendor, q->subdevice);
f1eaaeec 2584 chip->codec_probe_mask = q->value;
669ba27a
TI		 2585 }
2586 }
f1eaaeec
TI		 2587
2588 /* check forced option */
2589 if (chip->codec_probe_mask != -1 &&
2590 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2591 chip->codec_mask = chip->codec_probe_mask & 0xff;
2592 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2593 chip->codec_mask);
2594 }
669ba27a
TI		 2595}
2596
4d8e22e0 2597/*
71623855 2598 * white/black-list for enable_msi
4d8e22e0 2599 */
71623855 2600static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2601 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2602 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2603 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2604 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2605 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2606 {}
2607};
2608
2609static void __devinit check_msi(struct azx *chip)
2610{
2611 const struct snd_pci_quirk *q;
2612
71623855
TI		 2613 if (enable_msi >= 0) {
2614 chip->msi = !!enable_msi;
4d8e22e0 2615 return;
71623855
TI		 2616 }
2617 chip->msi = 1; /* enable MSI as default */
2618 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2619 if (q) {
2620 printk(KERN_INFO
2621 "hda_intel: msi for device %04x:%04x set to %d\n",
2622 q->subvendor, q->subdevice, q->value);
2623 chip->msi = q->value;
80c43ed7
TI		 2624 return;
2625 }
2626
2627 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2628 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2629 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2630 chip->msi = 0;
4d8e22e0
TI		 2631 }
2632}
2633
a1585d76
TI		 2634/* check the snoop mode availability */
2635static void __devinit azx_check_snoop_available(struct azx *chip)
2636{
2637 bool snoop = chip->snoop;
2638
2639 switch (chip->driver_type) {
2640 case AZX_DRIVER_VIA:
2641 /* force to non-snoop mode for a new VIA controller
2642 * when BIOS is set
2643 */
2644 if (snoop) {
2645 u8 val;
2646 pci_read_config_byte(chip->pci, 0x42, &val);
2647 if (!(val & 0x80) && chip->pci->revision == 0x30)
2648 snoop = false;
2649 }
2650 break;
2651 case AZX_DRIVER_ATIHDMI_NS:
2652 /* new ATI HDMI requires non-snoop */
2653 snoop = false;
2654 break;
2655 }
2656
2657 if (snoop != chip->snoop) {
2658 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2659 snoop ? "snoop" : "non-snoop");
2660 chip->snoop = snoop;
2661 }
2662}
669ba27a 2663
1da177e4
LT		 2664/*
2665 * constructor
2666 */
a98f90fd 2667static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2668 int dev, unsigned int driver_caps,
a98f90fd 2669 struct azx **rchip)
1da177e4 2670{
a98f90fd 2671 struct azx *chip;
4ce107b9 2672 int i, err;
bcd72003 2673 unsigned short gcap;
a98f90fd 2674 static struct snd_device_ops ops = {
1da177e4
LT		 2675 .dev_free = azx_dev_free,
2676 };
2677
2678 *rchip = NULL;
bcd72003 2679
927fc866
PM		 2680 err = pci_enable_device(pci);
2681 if (err < 0)
1da177e4
LT		 2682 return err;
2683
e560d8d8 2684 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2685 if (!chip) {
1da177e4
LT		 2686 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2687 pci_disable_device(pci);
2688 return -ENOMEM;
2689 }
2690
2691 spin_lock_init(&chip->reg_lock);
62932df8 2692 mutex_init(&chip->open_mutex);
1da177e4
LT		 2693 chip->card = card;
2694 chip->pci = pci;
2695 chip->irq = -1;
9477c58e
TI		 2696 chip->driver_caps = driver_caps;
2697 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2698 check_msi(chip);
555e219f 2699 chip->dev_index = dev;
9ad593f6 2700 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2701 INIT_LIST_HEAD(&chip->pcm_list);
1da177e4 2702
beaffc39
SG		 2703 chip->position_fix[0] = chip->position_fix[1] =
2704 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 2705 /* combo mode uses LPIB for playback */
2706 if (chip->position_fix[0] == POS_FIX_COMBO) {
2707 chip->position_fix[0] = POS_FIX_LPIB;
2708 chip->position_fix[1] = POS_FIX_AUTO;
2709 }
2710
5aba4f8e 2711 check_probe_mask(chip, dev);
3372a153 2712
27346166 2713 chip->single_cmd = single_cmd;
27fe48d9 2714 chip->snoop = hda_snoop;
a1585d76 2715 azx_check_snoop_available(chip);
c74db86b 2716
5c0d7bc1
TI		 2717 if (bdl_pos_adj[dev] < 0) {
2718 switch (chip->driver_type) {
0c6341ac 2719 case AZX_DRIVER_ICH:
32679f95 2720 case AZX_DRIVER_PCH:
0c6341ac 2721 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2722 break;
2723 default:
0c6341ac 2724 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2725 break;
2726 }
2727 }
2728
07e4ca50
TI		 2729#if BITS_PER_LONG != 64
2730 /* Fix up base address on ULI M5461 */
2731 if (chip->driver_type == AZX_DRIVER_ULI) {
2732 u16 tmp3;
2733 pci_read_config_word(pci, 0x40, &tmp3);
2734 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2735 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2736 }
2737#endif
2738
927fc866
PM		 2739 err = pci_request_regions(pci, "ICH HD audio");
2740 if (err < 0) {
1da177e4
LT		 2741 kfree(chip);
2742 pci_disable_device(pci);
2743 return err;
2744 }
2745
927fc866 2746 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2747 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2748 if (chip->remap_addr == NULL) {
2749 snd_printk(KERN_ERR SFX "ioremap error\n");
2750 err = -ENXIO;
2751 goto errout;
2752 }
2753
68e7fffc
TI		 2754 if (chip->msi)
2755 if (pci_enable_msi(pci) < 0)
2756 chip->msi = 0;
7376d013 2757
68e7fffc 2758 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2759 err = -EBUSY;
2760 goto errout;
2761 }
1da177e4
LT		 2762
2763 pci_set_master(pci);
2764 synchronize_irq(chip->irq);
2765
bcd72003 2766 gcap = azx_readw(chip, GCAP);
4abc1cc2 2767 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2768
dc4c2e6b 2769 /* disable SB600 64bit support for safety */
9477c58e 2770 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 2771 struct pci_dev *p_smbus;
2772 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2773 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2774 NULL);
2775 if (p_smbus) {
2776 if (p_smbus->revision < 0x30)
2777 gcap &= ~ICH6_GCAP_64OK;
2778 pci_dev_put(p_smbus);
2779 }
2780 }
09240cf4 2781
9477c58e
TI		 2782 /* disable 64bit DMA address on some devices */
2783 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2784 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 2785 gcap &= ~ICH6_GCAP_64OK;
9477c58e 2786 }
396087ea 2787
2ae66c26 2788 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 2789 if (align_buffer_size >= 0)
2790 chip->align_buffer_size = !!align_buffer_size;
2791 else {
2792 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2793 chip->align_buffer_size = 0;
2794 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2795 chip->align_buffer_size = 1;
2796 else
2797 chip->align_buffer_size = 1;
2798 }
2ae66c26 2799
cf7aaca8 2800 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2801 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2802 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2803 else {
e930438c
YH		 2804 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2805 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2806 }
cf7aaca8 2807
8b6ed8e7
TI		 2808 /* read number of streams from GCAP register instead of using
2809 * hardcoded value
2810 */
2811 chip->capture_streams = (gcap >> 8) & 0x0f;
2812 chip->playback_streams = (gcap >> 12) & 0x0f;
2813 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2814 /* gcap didn't give any info, switching to old method */
2815
2816 switch (chip->driver_type) {
2817 case AZX_DRIVER_ULI:
2818 chip->playback_streams = ULI_NUM_PLAYBACK;
2819 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2820 break;
2821 case AZX_DRIVER_ATIHDMI:
1815b34a 2822 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 2823 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2824 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2825 break;
c4da29ca 2826 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2827 default:
2828 chip->playback_streams = ICH6_NUM_PLAYBACK;
2829 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2830 break;
2831 }
07e4ca50 2832 }
8b6ed8e7
TI		 2833 chip->capture_index_offset = 0;
2834 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2835 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2836 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2837 GFP_KERNEL);
927fc866 2838 if (!chip->azx_dev) {
4abc1cc2 2839 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2840 goto errout;
2841 }
2842
4ce107b9
TI		 2843 for (i = 0; i < chip->num_streams; i++) {
2844 /* allocate memory for the BDL for each stream */
2845 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2846 snd_dma_pci_data(chip->pci),
2847 BDL_SIZE, &chip->azx_dev[i].bdl);
2848 if (err < 0) {
2849 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2850 goto errout;
2851 }
27fe48d9 2852 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 2853 }
0be3b5d3 2854 /* allocate memory for the position buffer */
d01ce99f
TI		 2855 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2856 snd_dma_pci_data(chip->pci),
2857 chip->num_streams * 8, &chip->posbuf);
2858 if (err < 0) {
0be3b5d3
TI		 2859 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2860 goto errout;
1da177e4 2861 }
27fe48d9 2862 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 2863 /* allocate CORB/RIRB */
81740861
TI		 2864 err = azx_alloc_cmd_io(chip);
2865 if (err < 0)
2866 goto errout;
1da177e4
LT		 2867
2868 /* initialize streams */
2869 azx_init_stream(chip);
2870
2871 /* initialize chip */
cb53c626 2872 azx_init_pci(chip);
10e77dda 2873 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2874
2875 /* codec detection */
927fc866 2876 if (!chip->codec_mask) {
1da177e4
LT		 2877 snd_printk(KERN_ERR SFX "no codecs found!\n");
2878 err = -ENODEV;
2879 goto errout;
2880 }
2881
d01ce99f
TI		 2882 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2883 if (err <0) {
1da177e4
LT		 2884 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2885 goto errout;
2886 }
2887
07e4ca50 2888 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2889 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2890 sizeof(card->shortname));
2891 snprintf(card->longname, sizeof(card->longname),
2892 "%s at 0x%lx irq %i",
2893 card->shortname, chip->addr, chip->irq);
07e4ca50 2894
1da177e4
LT		 2895 *rchip = chip;
2896 return 0;
2897
2898 errout:
2899 azx_free(chip);
2900 return err;
2901}
2902
cb53c626
TI		 2903static void power_down_all_codecs(struct azx *chip)
2904{
2905#ifdef CONFIG_SND_HDA_POWER_SAVE
2906 /* The codecs were powered up in snd_hda_codec_new().
2907 * Now all initialization done, so turn them down if possible
2908 */
2909 struct hda_codec *codec;
2910 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2911 snd_hda_power_down(codec);
2912 }
2913#endif
2914}
2915
d01ce99f
TI		 2916static int __devinit azx_probe(struct pci_dev *pci,
2917 const struct pci_device_id *pci_id)
1da177e4 2918{
5aba4f8e 2919 static int dev;
a98f90fd
TI		 2920 struct snd_card *card;
2921 struct azx *chip;
927fc866 2922 int err;
1da177e4 2923
5aba4f8e
TI		 2924 if (dev >= SNDRV_CARDS)
2925 return -ENODEV;
2926 if (!enable[dev]) {
2927 dev++;
2928 return -ENOENT;
2929 }
2930
e58de7ba
TI		 2931 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2932 if (err < 0) {
1da177e4 2933 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2934 return err;
1da177e4
LT		 2935 }
2936
4ea6fbc8
TI		 2937 /* set this here since it's referred in snd_hda_load_patch() */
2938 snd_card_set_dev(card, &pci->dev);
2939
5aba4f8e 2940 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2941 if (err < 0)
2942 goto out_free;
421a1252 2943 card->private_data = chip;
1da177e4 2944
2dca0bba
JK		 2945#ifdef CONFIG_SND_HDA_INPUT_BEEP
2946 chip->beep_mode = beep_mode[dev];
2947#endif
2948
1da177e4 2949 /* create codec instances */
a1e21c90 2950 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2951 if (err < 0)
2952 goto out_free;
4ea6fbc8 2953#ifdef CONFIG_SND_HDA_PATCH_LOADER
41a63f18 2954 if (patch[dev] && *patch[dev]) {
4ea6fbc8
TI		 2955 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2956 patch[dev]);
2957 err = snd_hda_load_patch(chip->bus, patch[dev]);
2958 if (err < 0)
2959 goto out_free;
2960 }
2961#endif
10e77dda 2962 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2963 err = azx_codec_configure(chip);
2964 if (err < 0)
2965 goto out_free;
2966 }
1da177e4
LT		 2967
2968 /* create PCM streams */
176d5335 2969 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2970 if (err < 0)
2971 goto out_free;
1da177e4
LT		 2972
2973 /* create mixer controls */
d01ce99f 2974 err = azx_mixer_create(chip);
41dda0fd
WF		 2975 if (err < 0)
2976 goto out_free;
1da177e4 2977
d01ce99f 2978 err = snd_card_register(card);
41dda0fd
WF		 2979 if (err < 0)
2980 goto out_free;
1da177e4
LT		 2981
2982 pci_set_drvdata(pci, card);
cb53c626
TI		 2983 chip->running = 1;
2984 power_down_all_codecs(chip);
0cbf0098 2985 azx_notifier_register(chip);
1da177e4 2986
e25bcdba 2987 dev++;
1da177e4 2988 return err;
41dda0fd
WF		 2989out_free:
2990 snd_card_free(card);
2991 return err;
1da177e4
LT		 2992}
2993
2994static void __devexit azx_remove(struct pci_dev *pci)
2995{
2996 snd_card_free(pci_get_drvdata(pci));
2997 pci_set_drvdata(pci, NULL);
2998}
2999
3000/* PCI IDs */
cebe41d4 3001static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3002 /* CPT */
9477c58e 3003 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26
PLB		 3004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3005 AZX_DCAPS_BUFSIZE },
cea310e8 3006 /* PBG */
9477c58e 3007 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3009 AZX_DCAPS_BUFSIZE},
d2edeb7c 3010 /* Panther Point */
9477c58e 3011 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3012 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
8bc039a1
SH		 3013 AZX_DCAPS_BUFSIZE},
3014 /* Lynx Point */
3015 { PCI_DEVICE(0x8086, 0x8c20),
3016 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2ae66c26 3017 AZX_DCAPS_BUFSIZE},
87218e9c 3018 /* SCH */
9477c58e 3019 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3020 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3021 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3022 { PCI_DEVICE(0x8086, 0x080a),
3023 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3024 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3025 /* ICH */
8b0bd226 3026 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3027 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3028 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3029 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3030 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3031 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3032 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3033 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3034 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3035 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3036 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3037 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3038 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3039 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3040 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3041 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3042 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3043 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3044 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3045 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3046 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3047 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3048 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3049 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3050 /* Generic Intel */
3051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3052 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3053 .class_mask = 0xffffff,
2ae66c26 3054 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3055 /* ATI SB 450/600/700/800/900 */
3056 { PCI_DEVICE(0x1002, 0x437b),
3057 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3058 { PCI_DEVICE(0x1002, 0x4383),
3059 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3060 /* AMD Hudson */
3061 { PCI_DEVICE(0x1022, 0x780d),
3062 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3063 /* ATI HDMI */
9477c58e
TI		 3064 { PCI_DEVICE(0x1002, 0x793b),
3065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3066 { PCI_DEVICE(0x1002, 0x7919),
3067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3068 { PCI_DEVICE(0x1002, 0x960f),
3069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3070 { PCI_DEVICE(0x1002, 0x970f),
3071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3072 { PCI_DEVICE(0x1002, 0xaa00),
3073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3074 { PCI_DEVICE(0x1002, 0xaa08),
3075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3076 { PCI_DEVICE(0x1002, 0xaa10),
3077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3078 { PCI_DEVICE(0x1002, 0xaa18),
3079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3080 { PCI_DEVICE(0x1002, 0xaa20),
3081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3082 { PCI_DEVICE(0x1002, 0xaa28),
3083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3084 { PCI_DEVICE(0x1002, 0xaa30),
3085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3086 { PCI_DEVICE(0x1002, 0xaa38),
3087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3088 { PCI_DEVICE(0x1002, 0xaa40),
3089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3090 { PCI_DEVICE(0x1002, 0xaa48),
3091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3092 { PCI_DEVICE(0x1002, 0x9902),
3093 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3094 { PCI_DEVICE(0x1002, 0xaaa0),
3095 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3096 { PCI_DEVICE(0x1002, 0xaaa8),
3097 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3098 { PCI_DEVICE(0x1002, 0xaab0),
3099 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3100 /* VIA VT8251/VT8237A */
9477c58e
TI		 3101 { PCI_DEVICE(0x1106, 0x3288),
3102 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
87218e9c
TI		 3103 /* SIS966 */
3104 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3105 /* ULI M5461 */
3106 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3107 /* NVIDIA MCP */
0c2fd1bf
TI		 3108 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3109 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3110 .class_mask = 0xffffff,
9477c58e 3111 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3112 /* Teradici */
9477c58e
TI		 3113 { PCI_DEVICE(0x6549, 0x1200),
3114 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3115 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 3116#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3117 /* the following entry conflicts with snd-ctxfi driver,
3118 * as ctxfi driver mutates from HD-audio to native mode with
3119 * a special command sequence.
3120 */
4e01f54b
TI		 3121 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3122 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3123 .class_mask = 0xffffff,
9477c58e 3124 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3125 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3126#else
3127 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3128 { PCI_DEVICE(0x1102, 0x0009),
3129 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3130 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3131#endif
5ae763b1
TI		 3132 /* CTHDA chips */
3133 { PCI_DEVICE(0x1102, 0x0010),
3134 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3135 { PCI_DEVICE(0x1102, 0x0012),
3136 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e35d4b11
OS		 3137 /* Vortex86MX */
3138 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3139 /* VMware HDAudio */
3140 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3141 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3142 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3143 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3144 .class_mask = 0xffffff,
9477c58e 3145 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3146 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3147 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3148 .class_mask = 0xffffff,
9477c58e 3149 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3150 { 0, }
3151};
3152MODULE_DEVICE_TABLE(pci, azx_ids);
3153
3154/* pci_driver definition */
3155static struct pci_driver driver = {
3733e424 3156 .name = KBUILD_MODNAME,
1da177e4
LT		 3157 .id_table = azx_ids,
3158 .probe = azx_probe,
3159 .remove = __devexit_p(azx_remove),
421a1252
TI		 3160#ifdef CONFIG_PM
3161 .suspend = azx_suspend,
3162 .resume = azx_resume,
3163#endif
1da177e4
LT		 3164};
3165
3166static int __init alsa_card_azx_init(void)
3167{
01d25d46 3168 return pci_register_driver(&driver);
1da177e4
LT		 3169}
3170
3171static void __exit alsa_card_azx_exit(void)
3172{
3173 pci_unregister_driver(&driver);
3174}
3175
3176module_init(alsa_card_azx_init)
3177module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
This page took 0.804876 seconds and 5 git commands to generate.