projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - Move low level functions to hda_controller
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
05e84878 66#include "hda_controller.h"
2538a4f5 67#include "hda_priv.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
9477c58e
TI		 240/* quirks for ATI SB / AMD Hudson */
241#define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245/* quirks for ATI/AMD HDMI */
246#define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249/* quirks for Nvidia */
250#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 253
5ae763b1
TI		 254#define AZX_DCAPS_PRESET_CTHDA \
255 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
256
a82d51ed
TI		 257/*
258 * VGA-switcher support
259 */
260#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 261#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
262#else
263#define use_vga_switcheroo(chip) 0
264#endif
265
48c8b0eb 266static char *driver_short_names[] = {
07e4ca50 267 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 268 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 269 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 270 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 271 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 272 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 273 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 274 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
275 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 276 [AZX_DRIVER_ULI] = "HDA ULI M5461",
277 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 278 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 279 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 280 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 282};
283
27fe48d9 284#ifdef CONFIG_X86
9ddf1aeb 285static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 286{
9ddf1aeb
TI		 287 int pages;
288
27fe48d9
TI		 289 if (azx_snoop(chip))
290 return;
9ddf1aeb
TI		 291 if (!dmab || !dmab->area || !dmab->bytes)
292 return;
293
294#ifdef CONFIG_SND_DMA_SGBUF
295 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
296 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 297 if (on)
9ddf1aeb 298 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 299 else
9ddf1aeb
TI		 300 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
301 return;
27fe48d9 302 }
9ddf1aeb
TI		 303#endif
304
305 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
306 if (on)
307 set_memory_wc((unsigned long)dmab->area, pages);
308 else
309 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 310}
311
312static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
313 bool on)
314{
9ddf1aeb 315 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 316}
317static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 318 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 319{
320 if (azx_dev->wc_marked != on) {
9ddf1aeb 321 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 322 azx_dev->wc_marked = on;
323 }
324}
325#else
326/* NOP for other archs */
327static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329{
330}
331static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 332 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 333{
334}
335#endif
336
68e7fffc 337static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 338
83012a7c 339#ifdef CONFIG_PM
68467f51 340static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 341#endif
111d3af5 342
cb53c626
TI		 343/*
344 * initialize the PCI registers
345 */
346/* update bits in a PCI register byte */
347static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
348 unsigned char mask, unsigned char val)
349{
350 unsigned char data;
351
352 pci_read_config_byte(pci, reg, &data);
353 data &= ~mask;
354 data |= (val & mask);
355 pci_write_config_byte(pci, reg, data);
356}
357
358static void azx_init_pci(struct azx *chip)
359{
360 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
361 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
362 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 363 * codecs.
364 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 365 */
46f2cc80 366 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 367 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 368 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 369 }
cb53c626 370
9477c58e
TI		 371 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
372 * we need to enable snoop.
373 */
374 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 375 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
376 azx_snoop(chip));
cb53c626 377 update_pci_byte(chip->pci,
27fe48d9
TI		 378 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
379 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 380 }
381
382 /* For NVIDIA HDA, enable snoop */
383 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 384 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
385 azx_snoop(chip));
cb53c626
TI		 386 update_pci_byte(chip->pci,
387 NVIDIA_HDA_TRANSREG_ADDR,
388 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 389 update_pci_byte(chip->pci,
390 NVIDIA_HDA_ISTRM_COH,
391 0x01, NVIDIA_HDA_ENABLE_COHBIT);
392 update_pci_byte(chip->pci,
393 NVIDIA_HDA_OSTRM_COH,
394 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 395 }
396
397 /* Enable SCH/PCH snoop if needed */
398 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 399 unsigned short snoop;
90a5ad52 400 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 401 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
402 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
403 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
404 if (!azx_snoop(chip))
405 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
406 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 407 pci_read_config_word(chip->pci,
408 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 409 }
4e76a883
TI		 410 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
411 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
412 "Disabled" : "Enabled");
da3fca21 413 }
1da177e4
LT		 414}
415
416
9ad593f6
TI		 417static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
418
1da177e4
LT		 419/*
420 * interrupt handler
421 */
7d12e780 422static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 423{
a98f90fd
TI		 424 struct azx *chip = dev_id;
425 struct azx_dev *azx_dev;
1da177e4 426 u32 status;
9ef04066 427 u8 sd_status;
fa00e046 428 int i, ok;
1da177e4 429
b8dfc462 430#ifdef CONFIG_PM_RUNTIME
246efa4a 431 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
8928756d 432 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
246efa4a 433 return IRQ_NONE;
b8dfc462
ML		 434#endif
435
1da177e4
LT		 436 spin_lock(&chip->reg_lock);
437
60911062
DC		 438 if (chip->disabled) {
439 spin_unlock(&chip->reg_lock);
a82d51ed 440 return IRQ_NONE;
60911062 441 }
a82d51ed 442
1da177e4 443 status = azx_readl(chip, INTSTS);
246efa4a 444 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 445 spin_unlock(&chip->reg_lock);
446 return IRQ_NONE;
447 }
448
07e4ca50 449 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 450 azx_dev = &chip->azx_dev[i];
451 if (status & azx_dev->sd_int_sta_mask) {
40830813
DR		 452 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
453 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 454 if (!azx_dev->substream || !azx_dev->running ||
455 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 456 continue;
457 /* check whether this IRQ is really acceptable */
fa00e046
JK		 458 ok = azx_position_ok(chip, azx_dev);
459 if (ok == 1) {
9ad593f6 460 azx_dev->irq_pending = 0;
1da177e4
LT		 461 spin_unlock(&chip->reg_lock);
462 snd_pcm_period_elapsed(azx_dev->substream);
463 spin_lock(&chip->reg_lock);
fa00e046 464 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 465 /* bogus IRQ, process it later */
466 azx_dev->irq_pending = 1;
6acaed38
TI		 467 queue_work(chip->bus->workq,
468 &chip->irq_pending_work);
1da177e4
LT		 469 }
470 }
471 }
472
473 /* clear rirb int */
474 status = azx_readb(chip, RIRBSTS);
475 if (status & RIRB_INT_MASK) {
14d34f16 476 if (status & RIRB_INT_RESPONSE) {
9477c58e 477 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 478 udelay(80);
1da177e4 479 azx_update_rirb(chip);
14d34f16 480 }
1da177e4
LT		 481 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
482 }
483
1da177e4
LT		 484 spin_unlock(&chip->reg_lock);
485
486 return IRQ_HANDLED;
487}
488
6ce4a3bc
TI		 489/*
490 * Probe the given codec address
491 */
492static int probe_codec(struct azx *chip, int addr)
493{
494 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
495 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
496 unsigned int res;
497
a678cdee 498 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 499 chip->probing = 1;
500 azx_send_cmd(chip->bus, cmd);
deadff16 501 res = azx_get_response(chip->bus, addr);
6ce4a3bc 502 chip->probing = 0;
a678cdee 503 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 504 if (res == -1)
505 return -EIO;
4e76a883 506 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 507 return 0;
508}
509
8dd78330
TI		 510static void azx_bus_reset(struct hda_bus *bus)
511{
512 struct azx *chip = bus->private_data;
8dd78330
TI		 513
514 bus->in_reset = 1;
515 azx_stop_chip(chip);
cd508fe5 516 azx_init_chip(chip, 1);
65f75983 517#ifdef CONFIG_PM
8dd78330 518 if (chip->initialized) {
01b65bfb
TI		 519 struct azx_pcm *p;
520 list_for_each_entry(p, &chip->pcm_list, list)
521 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 522 snd_hda_suspend(chip->bus);
523 snd_hda_resume(chip->bus);
524 }
65f75983 525#endif
8dd78330
TI		 526 bus->in_reset = 0;
527}
528
26a6cb6c
DH		 529static int get_jackpoll_interval(struct azx *chip)
530{
749ee287 531 int i;
26a6cb6c 532 unsigned int j;
749ee287
DR		 533
534 if (!chip->jackpoll_ms)
535 return 0;
536
537 i = chip->jackpoll_ms[chip->dev_index];
26a6cb6c
DH		 538 if (i == 0)
539 return 0;
540 if (i < 50 || i > 60000)
541 j = 0;
542 else
543 j = msecs_to_jiffies(i);
544 if (j == 0)
4e76a883
TI		 545 dev_warn(chip->card->dev,
546 "jackpoll_ms value out of range: %d\n", i);
26a6cb6c
DH		 547 return j;
548}
549
1da177e4
LT		 550/*
551 * Codec initialization
552 */
553
e62a42ae
DR		 554static int azx_codec_create(struct azx *chip, const char *model,
555 unsigned int max_slots,
556 int *power_save_to)
1da177e4
LT		 557{
558 struct hda_bus_template bus_temp;
34c25350 559 int c, codecs, err;
1da177e4
LT		 560
561 memset(&bus_temp, 0, sizeof(bus_temp));
562 bus_temp.private_data = chip;
563 bus_temp.modelname = model;
564 bus_temp.pci = chip->pci;
111d3af5
TI		 565 bus_temp.ops.command = azx_send_cmd;
566 bus_temp.ops.get_response = azx_get_response;
176d5335 567 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 568 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 569#ifdef CONFIG_PM
e62a42ae 570 bus_temp.power_save = power_save_to;
cb53c626
TI		 571 bus_temp.ops.pm_notify = azx_power_notify;
572#endif
1d1a4564
TI		 573#ifdef CONFIG_SND_HDA_DSP_LOADER
574 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
575 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
576 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
577#endif
1da177e4 578
d01ce99f
TI		 579 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
580 if (err < 0)
1da177e4
LT		 581 return err;
582
9477c58e 583 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
4e76a883 584 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
dc9c8e21 585 chip->bus->needs_damn_long_delay = 1;
9477c58e 586 }
dc9c8e21 587
34c25350 588 codecs = 0;
2f5983f2 589 if (!max_slots)
7445dfc1 590 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 591
592 /* First try to probe all given codec slots */
593 for (c = 0; c < max_slots; c++) {
f1eaaeec 594 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 595 if (probe_codec(chip, c) < 0) {
596 /* Some BIOSen give you wrong codec addresses
597 * that don't exist
598 */
4e76a883
TI		 599 dev_warn(chip->card->dev,
600 "Codec #%d probe error; disabling it...\n", c);
6ce4a3bc
TI		 601 chip->codec_mask &= ~(1 << c);
602 /* More badly, accessing to a non-existing
603 * codec often screws up the controller chip,
2448158e 604 * and disturbs the further communications.
6ce4a3bc
TI		 605 * Thus if an error occurs during probing,
606 * better to reset the controller chip to
607 * get back to the sanity state.
608 */
609 azx_stop_chip(chip);
cd508fe5 610 azx_init_chip(chip, 1);
6ce4a3bc
TI		 611 }
612 }
613 }
614
d507cd66
TI		 615 /* AMD chipsets often cause the communication stalls upon certain
616 * sequence like the pin-detection. It seems that forcing the synced
617 * access works around the stall. Grrr...
618 */
9477c58e 619 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
4e76a883 620 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
d507cd66
TI		 621 chip->bus->sync_write = 1;
622 chip->bus->allow_bus_reset = 1;
623 }
624
6ce4a3bc 625 /* Then create codec instances */
34c25350 626 for (c = 0; c < max_slots; c++) {
f1eaaeec 627 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 628 struct hda_codec *codec;
a1e21c90 629 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 630 if (err < 0)
631 continue;
26a6cb6c 632 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 633 codec->beep_mode = chip->beep_mode;
1da177e4 634 codecs++;
19a982b6
TI		 635 }
636 }
637 if (!codecs) {
4e76a883 638 dev_err(chip->card->dev, "no codecs initialized\n");
1da177e4
LT		 639 return -ENXIO;
640 }
a1e21c90
TI		 641 return 0;
642}
1da177e4 643
a1e21c90 644/* configure each codec instance */
e23e7a14 645static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 646{
647 struct hda_codec *codec;
648 list_for_each_entry(codec, &chip->bus->codec_list, list) {
649 snd_hda_codec_configure(codec);
650 }
1da177e4
LT		 651 return 0;
652}
653
9ad593f6
TI		 654/*
655 * Check whether the current DMA position is acceptable for updating
656 * periods. Returns non-zero if it's OK.
657 *
658 * Many HD-audio controllers appear pretty inaccurate about
659 * the update-IRQ timing. The IRQ is issued before actually the
660 * data is processed. So, we need to process it afterwords in a
661 * workqueue.
662 */
663static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
664{
e5463720 665 u32 wallclk;
9ad593f6
TI		 666 unsigned int pos;
667
f48f606d
JK		 668 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
669 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 670 return -1; /* bogus (too early) interrupt */
fa00e046 671
798cb7e8 672 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 673
d6d8bf54
TI		 674 if (WARN_ONCE(!azx_dev->period_bytes,
675 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 676 return -1; /* this shouldn't happen! */
edb39935 677 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 678 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
679 /* NG - it's below the first next period boundary */
9cdc0115 680 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 681 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 682 return 1; /* OK, it's fine */
683}
684
685/*
686 * The work for pending PCM period updates.
687 */
688static void azx_irq_pending_work(struct work_struct *work)
689{
690 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 691 int i, pending, ok;
9ad593f6 692
a6a950a8 693 if (!chip->irq_pending_warned) {
4e76a883
TI		 694 dev_info(chip->card->dev,
695 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
696 chip->card->number);
a6a950a8
TI		 697 chip->irq_pending_warned = 1;
698 }
699
9ad593f6
TI		 700 for (;;) {
701 pending = 0;
702 spin_lock_irq(&chip->reg_lock);
703 for (i = 0; i < chip->num_streams; i++) {
704 struct azx_dev *azx_dev = &chip->azx_dev[i];
705 if (!azx_dev->irq_pending ||
706 !azx_dev->substream ||
707 !azx_dev->running)
708 continue;
e5463720
JK		 709 ok = azx_position_ok(chip, azx_dev);
710 if (ok > 0) {
9ad593f6
TI		 711 azx_dev->irq_pending = 0;
712 spin_unlock(&chip->reg_lock);
713 snd_pcm_period_elapsed(azx_dev->substream);
714 spin_lock(&chip->reg_lock);
e5463720
JK		 715 } else if (ok < 0) {
716 pending = 0; /* too early */
9ad593f6
TI		 717 } else
718 pending++;
719 }
720 spin_unlock_irq(&chip->reg_lock);
721 if (!pending)
722 return;
08af495f 723 msleep(1);
9ad593f6
TI		 724 }
725}
726
727/* clear irq_pending flags and assure no on-going workq */
728static void azx_clear_irq_pending(struct azx *chip)
729{
730 int i;
731
732 spin_lock_irq(&chip->reg_lock);
733 for (i = 0; i < chip->num_streams; i++)
734 chip->azx_dev[i].irq_pending = 0;
735 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 736}
737
1da177e4
LT		 738/*
739 * mixer creation - all stuff is implemented in hda module
740 */
e23e7a14 741static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 742{
743 return snd_hda_build_controls(chip->bus);
744}
745
746
747/*
748 * initialize SD streams
749 */
e23e7a14 750static int azx_init_stream(struct azx *chip)
1da177e4
LT		 751{
752 int i;
753
754 /* initialize each stream (aka device)
d01ce99f
TI		 755 * assign the starting bdl address to each stream (device)
756 * and initialize
1da177e4 757 */
07e4ca50 758 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 759 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 760 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 761 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
762 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
763 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
764 azx_dev->sd_int_sta_mask = 1 << i;
765 /* stream tag: must be non-zero and unique */
766 azx_dev->index = i;
767 azx_dev->stream_tag = i + 1;
768 }
769
770 return 0;
771}
772
68e7fffc
TI		 773static int azx_acquire_irq(struct azx *chip, int do_disconnect)
774{
437a5a46
TI		 775 if (request_irq(chip->pci->irq, azx_interrupt,
776 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 777 KBUILD_MODNAME, chip)) {
4e76a883
TI		 778 dev_err(chip->card->dev,
779 "unable to grab IRQ %d, disabling device\n",
780 chip->pci->irq);
68e7fffc
TI		 781 if (do_disconnect)
782 snd_card_disconnect(chip->card);
783 return -1;
784 }
785 chip->irq = chip->pci->irq;
69e13418 786 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 787 return 0;
788}
789
83012a7c 790#ifdef CONFIG_PM
cb53c626 791/* power-up/down the controller */
68467f51 792static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 793{
33fa35ed 794 struct azx *chip = bus->private_data;
cb53c626 795
2ea3c6a2
TI		 796 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
797 return;
798
68467f51 799 if (power_up)
8928756d 800 pm_runtime_get_sync(chip->card->dev);
b8dfc462 801 else
8928756d 802 pm_runtime_put_sync(chip->card->dev);
cb53c626 803}
65fcd41d
TI		 804
805static DEFINE_MUTEX(card_list_lock);
806static LIST_HEAD(card_list);
807
808static void azx_add_card_list(struct azx *chip)
809{
810 mutex_lock(&card_list_lock);
811 list_add(&chip->list, &card_list);
812 mutex_unlock(&card_list_lock);
813}
814
815static void azx_del_card_list(struct azx *chip)
816{
817 mutex_lock(&card_list_lock);
818 list_del_init(&chip->list);
819 mutex_unlock(&card_list_lock);
820}
821
822/* trigger power-save check at writing parameter */
823static int param_set_xint(const char *val, const struct kernel_param *kp)
824{
825 struct azx *chip;
826 struct hda_codec *c;
827 int prev = power_save;
828 int ret = param_set_int(val, kp);
829
830 if (ret || prev == power_save)
831 return ret;
832
833 mutex_lock(&card_list_lock);
834 list_for_each_entry(chip, &card_list, list) {
835 if (!chip->bus || chip->disabled)
836 continue;
837 list_for_each_entry(c, &chip->bus->codec_list, list)
838 snd_hda_power_sync(c);
839 }
840 mutex_unlock(&card_list_lock);
841 return 0;
842}
843#else
844#define azx_add_card_list(chip) /* NOP */
845#define azx_del_card_list(chip) /* NOP */
83012a7c 846#endif /* CONFIG_PM */
5c0b9bec 847
7ccbde57 848#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 849/*
850 * power management
851 */
68cb2b55 852static int azx_suspend(struct device *dev)
1da177e4 853{
68cb2b55
TI		 854 struct pci_dev *pci = to_pci_dev(dev);
855 struct snd_card *card = dev_get_drvdata(dev);
421a1252 856 struct azx *chip = card->private_data;
01b65bfb 857 struct azx_pcm *p;
1da177e4 858
c5c21523
TI		 859 if (chip->disabled)
860 return 0;
861
421a1252 862 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 863 azx_clear_irq_pending(chip);
01b65bfb
TI		 864 list_for_each_entry(p, &chip->pcm_list, list)
865 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 866 if (chip->initialized)
8dd78330 867 snd_hda_suspend(chip->bus);
cb53c626 868 azx_stop_chip(chip);
7295b264 869 azx_enter_link_reset(chip);
30b35399 870 if (chip->irq >= 0) {
43001c95 871 free_irq(chip->irq, chip);
30b35399
TI		 872 chip->irq = -1;
873 }
68e7fffc 874 if (chip->msi)
43001c95 875 pci_disable_msi(chip->pci);
421a1252
TI		 876 pci_disable_device(pci);
877 pci_save_state(pci);
68cb2b55 878 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 879 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
880 hda_display_power(false);
1da177e4
LT		 881 return 0;
882}
883
68cb2b55 884static int azx_resume(struct device *dev)
1da177e4 885{
68cb2b55
TI		 886 struct pci_dev *pci = to_pci_dev(dev);
887 struct snd_card *card = dev_get_drvdata(dev);
421a1252 888 struct azx *chip = card->private_data;
1da177e4 889
c5c21523
TI		 890 if (chip->disabled)
891 return 0;
892
99a2008d
WX		 893 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
894 hda_display_power(true);
d14a7e0b
TI		 895 pci_set_power_state(pci, PCI_D0);
896 pci_restore_state(pci);
30b35399 897 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 898 dev_err(chip->card->dev,
899 "pci_enable_device failed, disabling device\n");
30b35399
TI		 900 snd_card_disconnect(card);
901 return -EIO;
902 }
903 pci_set_master(pci);
68e7fffc
TI		 904 if (chip->msi)
905 if (pci_enable_msi(pci) < 0)
906 chip->msi = 0;
907 if (azx_acquire_irq(chip, 1) < 0)
30b35399 908 return -EIO;
cb53c626 909 azx_init_pci(chip);
d804ad92 910
7f30830b 911 azx_init_chip(chip, 1);
d804ad92 912
1da177e4 913 snd_hda_resume(chip->bus);
421a1252 914 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 915 return 0;
916}
b8dfc462
ML		 917#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
918
919#ifdef CONFIG_PM_RUNTIME
920static int azx_runtime_suspend(struct device *dev)
921{
922 struct snd_card *card = dev_get_drvdata(dev);
923 struct azx *chip = card->private_data;
924
246efa4a
DA		 925 if (chip->disabled)
926 return 0;
927
928 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
929 return 0;
930
7d4f606c
WX		 931 /* enable controller wake up event */
932 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
933 STATESTS_INT_MASK);
934
b8dfc462 935 azx_stop_chip(chip);
873ce8ad 936 azx_enter_link_reset(chip);
b8dfc462 937 azx_clear_irq_pending(chip);
99a2008d
WX		 938 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
939 hda_display_power(false);
b8dfc462
ML		 940 return 0;
941}
942
943static int azx_runtime_resume(struct device *dev)
944{
945 struct snd_card *card = dev_get_drvdata(dev);
946 struct azx *chip = card->private_data;
7d4f606c
WX		 947 struct hda_bus *bus;
948 struct hda_codec *codec;
949 int status;
b8dfc462 950
246efa4a
DA		 951 if (chip->disabled)
952 return 0;
953
954 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
955 return 0;
956
99a2008d
WX		 957 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
958 hda_display_power(true);
7d4f606c
WX		 959
960 /* Read STATESTS before controller reset */
961 status = azx_readw(chip, STATESTS);
962
b8dfc462
ML		 963 azx_init_pci(chip);
964 azx_init_chip(chip, 1);
7d4f606c
WX		 965
966 bus = chip->bus;
967 if (status && bus) {
968 list_for_each_entry(codec, &bus->codec_list, list)
969 if (status & (1 << codec->addr))
970 queue_delayed_work(codec->bus->workq,
971 &codec->jackpoll_work, codec->jackpoll_interval);
972 }
973
974 /* disable controller Wake Up event*/
975 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
976 ~STATESTS_INT_MASK);
977
b8dfc462
ML		 978 return 0;
979}
6eb827d2
TI		 980
981static int azx_runtime_idle(struct device *dev)
982{
983 struct snd_card *card = dev_get_drvdata(dev);
984 struct azx *chip = card->private_data;
985
246efa4a
DA		 986 if (chip->disabled)
987 return 0;
988
6eb827d2
TI		 989 if (!power_save_controller ||
990 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
991 return -EBUSY;
992
993 return 0;
994}
995
b8dfc462
ML		 996#endif /* CONFIG_PM_RUNTIME */
997
998#ifdef CONFIG_PM
999static const struct dev_pm_ops azx_pm = {
1000 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1001 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1002};
1003
68cb2b55
TI		 1004#define AZX_PM_OPS &azx_pm
1005#else
68cb2b55 1006#define AZX_PM_OPS NULL
b8dfc462 1007#endif /* CONFIG_PM */
1da177e4
LT		 1008
1009
0cbf0098
TI		 1010/*
1011 * reboot notifier for hang-up problem at power-down
1012 */
1013static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1014{
1015 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 1016 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 1017 azx_stop_chip(chip);
1018 return NOTIFY_OK;
1019}
1020
1021static void azx_notifier_register(struct azx *chip)
1022{
1023 chip->reboot_notifier.notifier_call = azx_halt;
1024 register_reboot_notifier(&chip->reboot_notifier);
1025}
1026
1027static void azx_notifier_unregister(struct azx *chip)
1028{
1029 if (chip->reboot_notifier.notifier_call)
1030 unregister_reboot_notifier(&chip->reboot_notifier);
1031}
1032
48c8b0eb 1033static int azx_probe_continue(struct azx *chip);
a82d51ed 1034
8393ec4a 1035#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1036static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1037
a82d51ed
TI		 1038static void azx_vs_set_state(struct pci_dev *pci,
1039 enum vga_switcheroo_state state)
1040{
1041 struct snd_card *card = pci_get_drvdata(pci);
1042 struct azx *chip = card->private_data;
1043 bool disabled;
1044
f4c482a4 1045 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 1046 if (chip->init_failed)
1047 return;
1048
1049 disabled = (state == VGA_SWITCHEROO_OFF);
1050 if (chip->disabled == disabled)
1051 return;
1052
1053 if (!chip->bus) {
1054 chip->disabled = disabled;
1055 if (!disabled) {
4e76a883
TI		 1056 dev_info(chip->card->dev,
1057 "Start delayed initialization\n");
5c90680e 1058 if (azx_probe_continue(chip) < 0) {
4e76a883 1059 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1060 chip->init_failed = true;
1061 }
1062 }
1063 } else {
4e76a883
TI		 1064 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1065 disabled ? "Disabling" : "Enabling");
a82d51ed 1066 if (disabled) {
8928756d
DR		 1067 pm_runtime_put_sync_suspend(card->dev);
1068 azx_suspend(card->dev);
246efa4a
DA		 1069 /* when we get suspended by vga switcheroo we end up in D3cold,
1070 * however we have no ACPI handle, so pci/acpi can't put us there,
1071 * put ourselves there */
1072 pci->current_state = PCI_D3cold;
a82d51ed 1073 chip->disabled = true;
128960a9 1074 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1075 dev_warn(chip->card->dev,
1076 "Cannot lock devices!\n");
a82d51ed
TI		 1077 } else {
1078 snd_hda_unlock_devices(chip->bus);
8928756d 1079 pm_runtime_get_noresume(card->dev);
a82d51ed 1080 chip->disabled = false;
8928756d 1081 azx_resume(card->dev);
a82d51ed
TI		 1082 }
1083 }
1084}
1085
1086static bool azx_vs_can_switch(struct pci_dev *pci)
1087{
1088 struct snd_card *card = pci_get_drvdata(pci);
1089 struct azx *chip = card->private_data;
1090
f4c482a4 1091 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 1092 if (chip->init_failed)
1093 return false;
1094 if (chip->disabled || !chip->bus)
1095 return true;
1096 if (snd_hda_lock_devices(chip->bus))
1097 return false;
1098 snd_hda_unlock_devices(chip->bus);
1099 return true;
1100}
1101
e23e7a14 1102static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 1103{
1104 struct pci_dev *p = get_bound_vga(chip->pci);
1105 if (p) {
4e76a883
TI		 1106 dev_info(chip->card->dev,
1107 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 1108 chip->use_vga_switcheroo = 1;
1109 pci_dev_put(p);
1110 }
1111}
1112
1113static const struct vga_switcheroo_client_ops azx_vs_ops = {
1114 .set_gpu_state = azx_vs_set_state,
1115 .can_switch = azx_vs_can_switch,
1116};
1117
e23e7a14 1118static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1119{
128960a9
TI		 1120 int err;
1121
a82d51ed
TI		 1122 if (!chip->use_vga_switcheroo)
1123 return 0;
1124 /* FIXME: currently only handling DIS controller
1125 * is there any machine with two switchable HDMI audio controllers?
1126 */
128960a9 1127 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1128 VGA_SWITCHEROO_DIS,
1129 chip->bus != NULL);
128960a9
TI		 1130 if (err < 0)
1131 return err;
1132 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 1133
1134 /* register as an optimus hdmi audio power domain */
8928756d
DR		 1135 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1136 &chip->hdmi_pm_domain);
128960a9 1137 return 0;
a82d51ed
TI		 1138}
1139#else
1140#define init_vga_switcheroo(chip) /* NOP */
1141#define register_vga_switcheroo(chip) 0
8393ec4a 1142#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1143#endif /* SUPPORT_VGA_SWITCHER */
1144
1da177e4
LT		 1145/*
1146 * destructor
1147 */
a98f90fd 1148static int azx_free(struct azx *chip)
1da177e4 1149{
c67e2228 1150 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 1151 int i;
1152
c67e2228
WX		 1153 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1154 && chip->running)
1155 pm_runtime_get_noresume(&pci->dev);
1156
65fcd41d
TI		 1157 azx_del_card_list(chip);
1158
0cbf0098
TI		 1159 azx_notifier_unregister(chip);
1160
f4c482a4 1161 chip->init_failed = 1; /* to be sure */
44728e97 1162 complete_all(&chip->probe_wait);
f4c482a4 1163
a82d51ed
TI		 1164 if (use_vga_switcheroo(chip)) {
1165 if (chip->disabled && chip->bus)
1166 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 1167 if (chip->vga_switcheroo_registered)
1168 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1169 }
1170
ce43fbae 1171 if (chip->initialized) {
9ad593f6 1172 azx_clear_irq_pending(chip);
07e4ca50 1173 for (i = 0; i < chip->num_streams; i++)
1da177e4 1174 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1175 azx_stop_chip(chip);
1da177e4
LT		 1176 }
1177
f000fd80 1178 if (chip->irq >= 0)
1da177e4 1179 free_irq(chip->irq, (void*)chip);
68e7fffc 1180 if (chip->msi)
30b35399 1181 pci_disable_msi(chip->pci);
f079c25a
TI		 1182 if (chip->remap_addr)
1183 iounmap(chip->remap_addr);
1da177e4 1184
67908994 1185 azx_free_stream_pages(chip);
a82d51ed
TI		 1186 if (chip->region_requested)
1187 pci_release_regions(chip->pci);
1da177e4 1188 pci_disable_device(chip->pci);
07e4ca50 1189 kfree(chip->azx_dev);
4918cdab
TI		 1190#ifdef CONFIG_SND_HDA_PATCH_LOADER
1191 if (chip->fw)
1192 release_firmware(chip->fw);
1193#endif
99a2008d
WX		 1194 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1195 hda_display_power(false);
1196 hda_i915_exit();
1197 }
1da177e4
LT		 1198 kfree(chip);
1199
1200 return 0;
1201}
1202
a98f90fd 1203static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1204{
1205 return azx_free(device->device_data);
1206}
1207
8393ec4a 1208#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1209/*
1210 * Check of disabled HDMI controller by vga-switcheroo
1211 */
e23e7a14 1212static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1213{
1214 struct pci_dev *p;
1215
1216 /* check only discrete GPU */
1217 switch (pci->vendor) {
1218 case PCI_VENDOR_ID_ATI:
1219 case PCI_VENDOR_ID_AMD:
1220 case PCI_VENDOR_ID_NVIDIA:
1221 if (pci->devfn == 1) {
1222 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1223 pci->bus->number, 0);
1224 if (p) {
1225 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1226 return p;
1227 pci_dev_put(p);
1228 }
1229 }
1230 break;
1231 }
1232 return NULL;
1233}
1234
e23e7a14 1235static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1236{
1237 bool vga_inactive = false;
1238 struct pci_dev *p = get_bound_vga(pci);
1239
1240 if (p) {
12b78a7f 1241 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1242 vga_inactive = true;
1243 pci_dev_put(p);
1244 }
1245 return vga_inactive;
1246}
8393ec4a 1247#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1248
3372a153
TI		 1249/*
1250 * white/black-listing for position_fix
1251 */
e23e7a14 1252static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1253 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1254 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1255 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1256 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1257 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1258 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1259 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1260 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1261 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1262 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1263 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1264 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1265 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1266 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1267 {}
1268};
1269
e23e7a14 1270static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1271{
1272 const struct snd_pci_quirk *q;
1273
c673ba1c 1274 switch (fix) {
1dac6695 1275 case POS_FIX_AUTO:
c673ba1c
TI		 1276 case POS_FIX_LPIB:
1277 case POS_FIX_POSBUF:
4cb36310 1278 case POS_FIX_VIACOMBO:
a6f2fd55 1279 case POS_FIX_COMBO:
c673ba1c
TI		 1280 return fix;
1281 }
1282
c673ba1c
TI		 1283 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1284 if (q) {
4e76a883
TI		 1285 dev_info(chip->card->dev,
1286 "position_fix set to %d for device %04x:%04x\n",
1287 q->value, q->subvendor, q->subdevice);
c673ba1c 1288 return q->value;
3372a153 1289 }
bdd9ef24
DH		 1290
1291 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1292 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1293 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1294 return POS_FIX_VIACOMBO;
9477c58e
TI		 1295 }
1296 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1297 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1298 return POS_FIX_LPIB;
bdd9ef24 1299 }
c673ba1c 1300 return POS_FIX_AUTO;
3372a153
TI		 1301}
1302
669ba27a
TI		 1303/*
1304 * black-lists for probe_mask
1305 */
e23e7a14 1306static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1307 /* Thinkpad often breaks the controller communication when accessing
1308 * to the non-working (or non-existing) modem codec slot.
1309 */
1310 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1311 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1312 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1313 /* broken BIOS */
1314 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1315 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1316 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1317 /* forced codec slots */
93574844 1318 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1319 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1320 /* WinFast VP200 H (Teradici) user reported broken communication */
1321 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1322 {}
1323};
1324
f1eaaeec
TI		 1325#define AZX_FORCE_CODEC_MASK 0x100
1326
e23e7a14 1327static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1328{
1329 const struct snd_pci_quirk *q;
1330
f1eaaeec
TI		 1331 chip->codec_probe_mask = probe_mask[dev];
1332 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1333 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1334 if (q) {
4e76a883
TI		 1335 dev_info(chip->card->dev,
1336 "probe_mask set to 0x%x for device %04x:%04x\n",
1337 q->value, q->subvendor, q->subdevice);
f1eaaeec 1338 chip->codec_probe_mask = q->value;
669ba27a
TI		 1339 }
1340 }
f1eaaeec
TI		 1341
1342 /* check forced option */
1343 if (chip->codec_probe_mask != -1 &&
1344 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1345 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1346 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1347 chip->codec_mask);
f1eaaeec 1348 }
669ba27a
TI		 1349}
1350
4d8e22e0 1351/*
71623855 1352 * white/black-list for enable_msi
4d8e22e0 1353 */
e23e7a14 1354static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1355 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1356 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1357 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1358 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1359 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1360 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1361 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1362 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1363 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1364 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1365 {}
1366};
1367
e23e7a14 1368static void check_msi(struct azx *chip)
4d8e22e0
TI		 1369{
1370 const struct snd_pci_quirk *q;
1371
71623855
TI		 1372 if (enable_msi >= 0) {
1373 chip->msi = !!enable_msi;
4d8e22e0 1374 return;
71623855
TI		 1375 }
1376 chip->msi = 1; /* enable MSI as default */
1377 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1378 if (q) {
4e76a883
TI		 1379 dev_info(chip->card->dev,
1380 "msi for device %04x:%04x set to %d\n",
1381 q->subvendor, q->subdevice, q->value);
4d8e22e0 1382 chip->msi = q->value;
80c43ed7
TI		 1383 return;
1384 }
1385
1386 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1387 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1388 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1389 chip->msi = 0;
4d8e22e0
TI		 1390 }
1391}
1392
a1585d76 1393/* check the snoop mode availability */
e23e7a14 1394static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1395{
1396 bool snoop = chip->snoop;
1397
1398 switch (chip->driver_type) {
1399 case AZX_DRIVER_VIA:
1400 /* force to non-snoop mode for a new VIA controller
1401 * when BIOS is set
1402 */
1403 if (snoop) {
1404 u8 val;
1405 pci_read_config_byte(chip->pci, 0x42, &val);
1406 if (!(val & 0x80) && chip->pci->revision == 0x30)
1407 snoop = false;
1408 }
1409 break;
1410 case AZX_DRIVER_ATIHDMI_NS:
1411 /* new ATI HDMI requires non-snoop */
1412 snoop = false;
1413 break;
c1279f87
TI		 1414 case AZX_DRIVER_CTHDA:
1415 snoop = false;
1416 break;
a1585d76
TI		 1417 }
1418
1419 if (snoop != chip->snoop) {
4e76a883
TI		 1420 dev_info(chip->card->dev, "Force to %s mode\n",
1421 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1422 chip->snoop = snoop;
1423 }
1424}
669ba27a 1425
99a2008d
WX		 1426static void azx_probe_work(struct work_struct *work)
1427{
1428 azx_probe_continue(container_of(work, struct azx, probe_work));
1429}
99a2008d 1430
1da177e4
LT		 1431/*
1432 * constructor
1433 */
e23e7a14
BP		 1434static int azx_create(struct snd_card *card, struct pci_dev *pci,
1435 int dev, unsigned int driver_caps,
40830813 1436 const struct hda_controller_ops *hda_ops,
e23e7a14 1437 struct azx **rchip)
1da177e4 1438{
a98f90fd 1439 static struct snd_device_ops ops = {
1da177e4
LT		 1440 .dev_free = azx_dev_free,
1441 };
a82d51ed
TI		 1442 struct azx *chip;
1443 int err;
1da177e4
LT		 1444
1445 *rchip = NULL;
bcd72003 1446
927fc866
PM		 1447 err = pci_enable_device(pci);
1448 if (err < 0)
1da177e4
LT		 1449 return err;
1450
e560d8d8 1451 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1452 if (!chip) {
4e76a883 1453 dev_err(card->dev, "Cannot allocate chip\n");
1da177e4
LT		 1454 pci_disable_device(pci);
1455 return -ENOMEM;
1456 }
1457
1458 spin_lock_init(&chip->reg_lock);
62932df8 1459 mutex_init(&chip->open_mutex);
1da177e4
LT		 1460 chip->card = card;
1461 chip->pci = pci;
40830813 1462 chip->ops = hda_ops;
1da177e4 1463 chip->irq = -1;
9477c58e
TI		 1464 chip->driver_caps = driver_caps;
1465 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1466 check_msi(chip);
555e219f 1467 chip->dev_index = dev;
749ee287 1468 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1469 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1470 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1471 INIT_LIST_HEAD(&chip->list);
a82d51ed 1472 init_vga_switcheroo(chip);
f4c482a4 1473 init_completion(&chip->probe_wait);
1da177e4 1474
beaffc39
SG		 1475 chip->position_fix[0] = chip->position_fix[1] =
1476 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1477 /* combo mode uses LPIB for playback */
1478 if (chip->position_fix[0] == POS_FIX_COMBO) {
1479 chip->position_fix[0] = POS_FIX_LPIB;
1480 chip->position_fix[1] = POS_FIX_AUTO;
1481 }
1482
5aba4f8e 1483 check_probe_mask(chip, dev);
3372a153 1484
27346166 1485 chip->single_cmd = single_cmd;
27fe48d9 1486 chip->snoop = hda_snoop;
a1585d76 1487 azx_check_snoop_available(chip);
c74db86b 1488
5c0d7bc1
TI		 1489 if (bdl_pos_adj[dev] < 0) {
1490 switch (chip->driver_type) {
0c6341ac 1491 case AZX_DRIVER_ICH:
32679f95 1492 case AZX_DRIVER_PCH:
0c6341ac 1493 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1494 break;
1495 default:
0c6341ac 1496 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1497 break;
1498 }
1499 }
9cdc0115 1500 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1501
a82d51ed
TI		 1502 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1503 if (err < 0) {
4e76a883 1504 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1505 azx_free(chip);
1506 return err;
1507 }
1508
99a2008d
WX		 1509 /* continue probing in work context as may trigger request module */
1510 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1511
a82d51ed 1512 *rchip = chip;
99a2008d 1513
a82d51ed
TI		 1514 return 0;
1515}
1516
48c8b0eb 1517static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1518{
1519 int dev = chip->dev_index;
1520 struct pci_dev *pci = chip->pci;
1521 struct snd_card *card = chip->card;
67908994 1522 int err;
a82d51ed
TI		 1523 unsigned short gcap;
1524
07e4ca50
TI		 1525#if BITS_PER_LONG != 64
1526 /* Fix up base address on ULI M5461 */
1527 if (chip->driver_type == AZX_DRIVER_ULI) {
1528 u16 tmp3;
1529 pci_read_config_word(pci, 0x40, &tmp3);
1530 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1531 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1532 }
1533#endif
1534
927fc866 1535 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1536 if (err < 0)
1da177e4 1537 return err;
a82d51ed 1538 chip->region_requested = 1;
1da177e4 1539
927fc866 1540 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1541 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1542 if (chip->remap_addr == NULL) {
4e76a883 1543 dev_err(card->dev, "ioremap error\n");
a82d51ed 1544 return -ENXIO;
1da177e4
LT		 1545 }
1546
68e7fffc
TI		 1547 if (chip->msi)
1548 if (pci_enable_msi(pci) < 0)
1549 chip->msi = 0;
7376d013 1550
a82d51ed
TI		 1551 if (azx_acquire_irq(chip, 0) < 0)
1552 return -EBUSY;
1da177e4
LT		 1553
1554 pci_set_master(pci);
1555 synchronize_irq(chip->irq);
1556
bcd72003 1557 gcap = azx_readw(chip, GCAP);
4e76a883 1558 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1559
dc4c2e6b 1560 /* disable SB600 64bit support for safety */
9477c58e 1561 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1562 struct pci_dev *p_smbus;
1563 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1564 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1565 NULL);
1566 if (p_smbus) {
1567 if (p_smbus->revision < 0x30)
1568 gcap &= ~ICH6_GCAP_64OK;
1569 pci_dev_put(p_smbus);
1570 }
1571 }
09240cf4 1572
9477c58e
TI		 1573 /* disable 64bit DMA address on some devices */
1574 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1575 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1576 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1577 }
396087ea 1578
2ae66c26 1579 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1580 if (align_buffer_size >= 0)
1581 chip->align_buffer_size = !!align_buffer_size;
1582 else {
1583 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1584 chip->align_buffer_size = 0;
1585 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1586 chip->align_buffer_size = 1;
1587 else
1588 chip->align_buffer_size = 1;
1589 }
2ae66c26 1590
cf7aaca8 1591 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1592 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1593 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1594 else {
e930438c
YH		 1595 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1596 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1597 }
cf7aaca8 1598
8b6ed8e7
TI		 1599 /* read number of streams from GCAP register instead of using
1600 * hardcoded value
1601 */
1602 chip->capture_streams = (gcap >> 8) & 0x0f;
1603 chip->playback_streams = (gcap >> 12) & 0x0f;
1604 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1605 /* gcap didn't give any info, switching to old method */
1606
1607 switch (chip->driver_type) {
1608 case AZX_DRIVER_ULI:
1609 chip->playback_streams = ULI_NUM_PLAYBACK;
1610 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1611 break;
1612 case AZX_DRIVER_ATIHDMI:
1815b34a 1613 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1614 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1615 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1616 break;
c4da29ca 1617 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1618 default:
1619 chip->playback_streams = ICH6_NUM_PLAYBACK;
1620 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1621 break;
1622 }
07e4ca50 1623 }
8b6ed8e7
TI		 1624 chip->capture_index_offset = 0;
1625 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1626 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1627 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1628 GFP_KERNEL);
927fc866 1629 if (!chip->azx_dev) {
4e76a883 1630 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1631 return -ENOMEM;
07e4ca50
TI		 1632 }
1633
67908994 1634 err = azx_alloc_stream_pages(chip);
81740861 1635 if (err < 0)
a82d51ed 1636 return err;
1da177e4
LT		 1637
1638 /* initialize streams */
1639 azx_init_stream(chip);
1640
1641 /* initialize chip */
cb53c626 1642 azx_init_pci(chip);
10e77dda 1643 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1644
1645 /* codec detection */
927fc866 1646 if (!chip->codec_mask) {
4e76a883 1647 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1648 return -ENODEV;
1da177e4
LT		 1649 }
1650
07e4ca50 1651 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1652 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1653 sizeof(card->shortname));
1654 snprintf(card->longname, sizeof(card->longname),
1655 "%s at 0x%lx irq %i",
1656 card->shortname, chip->addr, chip->irq);
07e4ca50 1657
1da177e4 1658 return 0;
1da177e4
LT		 1659}
1660
cb53c626
TI		 1661static void power_down_all_codecs(struct azx *chip)
1662{
83012a7c 1663#ifdef CONFIG_PM
cb53c626
TI		 1664 /* The codecs were powered up in snd_hda_codec_new().
1665 * Now all initialization done, so turn them down if possible
1666 */
1667 struct hda_codec *codec;
1668 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1669 snd_hda_power_down(codec);
1670 }
1671#endif
1672}
1673
97c6a3d1 1674#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1675/* callback from request_firmware_nowait() */
1676static void azx_firmware_cb(const struct firmware *fw, void *context)
1677{
1678 struct snd_card *card = context;
1679 struct azx *chip = card->private_data;
1680 struct pci_dev *pci = chip->pci;
1681
1682 if (!fw) {
4e76a883 1683 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1684 goto error;
1685 }
1686
1687 chip->fw = fw;
1688 if (!chip->disabled) {
1689 /* continue probing */
1690 if (azx_probe_continue(chip))
1691 goto error;
1692 }
1693 return; /* OK */
1694
1695 error:
1696 snd_card_free(card);
1697 pci_set_drvdata(pci, NULL);
1698}
97c6a3d1 1699#endif
5cb543db 1700
40830813
DR		 1701/*
1702 * HDA controller ops.
1703 */
1704
1705/* PCI register access. */
1706static void pci_azx_writel(u32 value, u32 *addr)
1707{
1708 writel(value, addr);
1709}
1710
1711static u32 pci_azx_readl(u32 *addr)
1712{
1713 return readl(addr);
1714}
1715
1716static void pci_azx_writew(u16 value, u16 *addr)
1717{
1718 writew(value, addr);
1719}
1720
1721static u16 pci_azx_readw(u16 *addr)
1722{
1723 return readw(addr);
1724}
1725
1726static void pci_azx_writeb(u8 value, u8 *addr)
1727{
1728 writeb(value, addr);
1729}
1730
1731static u8 pci_azx_readb(u8 *addr)
1732{
1733 return readb(addr);
1734}
1735
f46ea609
DR		 1736static int disable_msi_reset_irq(struct azx *chip)
1737{
1738 int err;
1739
1740 free_irq(chip->irq, chip);
1741 chip->irq = -1;
1742 pci_disable_msi(chip->pci);
1743 chip->msi = 0;
1744 err = azx_acquire_irq(chip, 1);
1745 if (err < 0)
1746 return err;
1747
1748 return 0;
1749}
1750
b419b35b
DR		 1751/* DMA page allocation helpers. */
1752static int dma_alloc_pages(struct azx *chip,
1753 int type,
1754 size_t size,
1755 struct snd_dma_buffer *buf)
1756{
1757 int err;
1758
1759 err = snd_dma_alloc_pages(type,
1760 chip->card->dev,
1761 size, buf);
1762 if (err < 0)
1763 return err;
1764 mark_pages_wc(chip, buf, true);
1765 return 0;
1766}
1767
1768static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1769{
1770 mark_pages_wc(chip, buf, false);
1771 snd_dma_free_pages(buf);
1772}
1773
1774static int substream_alloc_pages(struct azx *chip,
1775 struct snd_pcm_substream *substream,
1776 size_t size)
1777{
1778 struct azx_dev *azx_dev = get_azx_dev(substream);
1779 int ret;
1780
1781 mark_runtime_wc(chip, azx_dev, substream, false);
1782 azx_dev->bufsize = 0;
1783 azx_dev->period_bytes = 0;
1784 azx_dev->format_val = 0;
1785 ret = snd_pcm_lib_malloc_pages(substream, size);
1786 if (ret < 0)
1787 return ret;
1788 mark_runtime_wc(chip, azx_dev, substream, true);
1789 return 0;
1790}
1791
1792static int substream_free_pages(struct azx *chip,
1793 struct snd_pcm_substream *substream)
1794{
1795 struct azx_dev *azx_dev = get_azx_dev(substream);
1796 mark_runtime_wc(chip, azx_dev, substream, false);
1797 return snd_pcm_lib_free_pages(substream);
1798}
1799
8769b278
DR		 1800static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1801 struct vm_area_struct *area)
1802{
1803#ifdef CONFIG_X86
1804 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1805 struct azx *chip = apcm->chip;
1806 if (!azx_snoop(chip))
1807 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1808#endif
1809}
1810
40830813
DR		 1811static const struct hda_controller_ops pci_hda_ops = {
1812 .writel = pci_azx_writel,
1813 .readl = pci_azx_readl,
1814 .writew = pci_azx_writew,
1815 .readw = pci_azx_readw,
1816 .writeb = pci_azx_writeb,
1817 .readb = pci_azx_readb,
f46ea609 1818 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1819 .dma_alloc_pages = dma_alloc_pages,
1820 .dma_free_pages = dma_free_pages,
1821 .substream_alloc_pages = substream_alloc_pages,
1822 .substream_free_pages = substream_free_pages,
8769b278 1823 .pcm_mmap_prepare = pcm_mmap_prepare,
40830813
DR		 1824};
1825
e23e7a14
BP		 1826static int azx_probe(struct pci_dev *pci,
1827 const struct pci_device_id *pci_id)
1da177e4 1828{
5aba4f8e 1829 static int dev;
a98f90fd
TI		 1830 struct snd_card *card;
1831 struct azx *chip;
aad730d0 1832 bool schedule_probe;
927fc866 1833 int err;
1da177e4 1834
5aba4f8e
TI		 1835 if (dev >= SNDRV_CARDS)
1836 return -ENODEV;
1837 if (!enable[dev]) {
1838 dev++;
1839 return -ENOENT;
1840 }
1841
60c5772b
TI		 1842 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1843 0, &card);
e58de7ba 1844 if (err < 0) {
4e76a883 1845 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1846 return err;
1da177e4
LT		 1847 }
1848
40830813
DR		 1849 err = azx_create(card, pci, dev, pci_id->driver_data,
1850 &pci_hda_ops, &chip);
41dda0fd
WF		 1851 if (err < 0)
1852 goto out_free;
421a1252 1853 card->private_data = chip;
f4c482a4
TI		 1854
1855 pci_set_drvdata(pci, card);
1856
1857 err = register_vga_switcheroo(chip);
1858 if (err < 0) {
4e76a883 1859 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1860 goto out_free;
1861 }
1862
1863 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1864 dev_info(card->dev, "VGA controller is disabled\n");
1865 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1866 chip->disabled = true;
1867 }
1868
aad730d0 1869 schedule_probe = !chip->disabled;
1da177e4 1870
4918cdab
TI		 1871#ifdef CONFIG_SND_HDA_PATCH_LOADER
1872 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1873 dev_info(card->dev, "Applying patch firmware '%s'\n",
1874 patch[dev]);
5cb543db
TI		 1875 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1876 &pci->dev, GFP_KERNEL, card,
1877 azx_firmware_cb);
4918cdab
TI		 1878 if (err < 0)
1879 goto out_free;
aad730d0 1880 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1881 }
1882#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1883
aad730d0
TI		 1884#ifndef CONFIG_SND_HDA_I915
1885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1886 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1887#endif
99a2008d 1888
aad730d0
TI		 1889 if (schedule_probe)
1890 schedule_work(&chip->probe_work);
a82d51ed 1891
a82d51ed 1892 dev++;
88d071fc
TI		 1893 if (chip->disabled)
1894 complete_all(&chip->probe_wait);
a82d51ed
TI		 1895 return 0;
1896
1897out_free:
1898 snd_card_free(card);
1899 return err;
1900}
1901
e62a42ae
DR		 1902/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1903static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1904 [AZX_DRIVER_NVIDIA] = 8,
1905 [AZX_DRIVER_TERA] = 1,
1906};
1907
48c8b0eb 1908static int azx_probe_continue(struct azx *chip)
a82d51ed 1909{
c67e2228 1910 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1911 int dev = chip->dev_index;
1912 int err;
1913
99a2008d
WX		 1914 /* Request power well for Haswell HDA controller and codec */
1915 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1916#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1917 err = hda_i915_init();
1918 if (err < 0) {
4e76a883
TI		 1919 dev_err(chip->card->dev,
1920 "Error request power-well from i915\n");
99a2008d
WX		 1921 goto out_free;
1922 }
c841ad2a 1923#endif
99a2008d
WX		 1924 hda_display_power(true);
1925 }
1926
5c90680e
TI		 1927 err = azx_first_init(chip);
1928 if (err < 0)
1929 goto out_free;
1930
2dca0bba
JK		 1931#ifdef CONFIG_SND_HDA_INPUT_BEEP
1932 chip->beep_mode = beep_mode[dev];
1933#endif
1934
1da177e4 1935 /* create codec instances */
e62a42ae
DR		 1936 err = azx_codec_create(chip, model[dev],
1937 azx_max_codecs[chip->driver_type],
1938 power_save_addr);
1939
41dda0fd
WF		 1940 if (err < 0)
1941 goto out_free;
4ea6fbc8 1942#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1943 if (chip->fw) {
1944 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1945 chip->fw->data);
4ea6fbc8
TI		 1946 if (err < 0)
1947 goto out_free;
e39ae856 1948#ifndef CONFIG_PM
4918cdab
TI		 1949 release_firmware(chip->fw); /* no longer needed */
1950 chip->fw = NULL;
e39ae856 1951#endif
4ea6fbc8
TI		 1952 }
1953#endif
10e77dda 1954 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1955 err = azx_codec_configure(chip);
1956 if (err < 0)
1957 goto out_free;
1958 }
1da177e4
LT		 1959
1960 /* create PCM streams */
176d5335 1961 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1962 if (err < 0)
1963 goto out_free;
1da177e4
LT		 1964
1965 /* create mixer controls */
d01ce99f 1966 err = azx_mixer_create(chip);
41dda0fd
WF		 1967 if (err < 0)
1968 goto out_free;
1da177e4 1969
a82d51ed 1970 err = snd_card_register(chip->card);
41dda0fd
WF		 1971 if (err < 0)
1972 goto out_free;
1da177e4 1973
cb53c626
TI		 1974 chip->running = 1;
1975 power_down_all_codecs(chip);
0cbf0098 1976 azx_notifier_register(chip);
65fcd41d 1977 azx_add_card_list(chip);
246efa4a 1978 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1979 pm_runtime_put_noidle(&pci->dev);
1da177e4 1980
41dda0fd 1981out_free:
88d071fc
TI		 1982 if (err < 0)
1983 chip->init_failed = 1;
1984 complete_all(&chip->probe_wait);
41dda0fd 1985 return err;
1da177e4
LT		 1986}
1987
e23e7a14 1988static void azx_remove(struct pci_dev *pci)
1da177e4 1989{
9121947d 1990 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1991
9121947d
TI		 1992 if (card)
1993 snd_card_free(card);
1da177e4
LT		 1994}
1995
1996/* PCI IDs */
cebe41d4 1997static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 1998 /* CPT */
9477c58e 1999 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2000 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2001 /* PBG */
9477c58e 2002 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2003 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2004 /* Panther Point */
9477c58e 2005 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 2006 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 2007 /* Lynx Point */
2008 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2009 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2010 /* Wellsburg */
2011 { PCI_DEVICE(0x8086, 0x8d20),
2012 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2013 { PCI_DEVICE(0x8086, 0x8d21),
2014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2015 /* Lynx Point-LP */
2016 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2017 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2018 /* Lynx Point-LP */
2019 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2020 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2021 /* Wildcat Point-LP */
2022 { PCI_DEVICE(0x8086, 0x9ca0),
2023 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 2024 /* Haswell */
4a7c516b 2025 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2026 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2027 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2028 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2029 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2030 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2031 /* Broadwell */
2032 { PCI_DEVICE(0x8086, 0x160c),
2033 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 2034 /* 5 Series/3400 */
2035 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2036 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2037 /* Poulsbo */
9477c58e 2038 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2039 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2040 /* Oaktrail */
09904b95 2041 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2042 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2043 /* BayTrail */
2044 { PCI_DEVICE(0x8086, 0x0f04),
2045 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 2046 /* ICH */
8b0bd226 2047 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 2048 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2049 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 2050 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 2051 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2052 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 2053 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 2054 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2055 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 2056 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 2057 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2058 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 2059 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 2060 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2061 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2062 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 2063 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2064 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2065 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 2066 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2067 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 2068 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 2069 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2070 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 2071 /* Generic Intel */
2072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2073 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2074 .class_mask = 0xffffff,
2ae66c26 2075 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 2076 /* ATI SB 450/600/700/800/900 */
2077 { PCI_DEVICE(0x1002, 0x437b),
2078 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2079 { PCI_DEVICE(0x1002, 0x4383),
2080 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2081 /* AMD Hudson */
2082 { PCI_DEVICE(0x1022, 0x780d),
2083 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2084 /* ATI HDMI */
9477c58e
TI		 2085 { PCI_DEVICE(0x1002, 0x793b),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0x7919),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0x960f),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0x970f),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2093 { PCI_DEVICE(0x1002, 0xaa00),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa08),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa10),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa18),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa20),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0xaa28),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa30),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa38),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaa40),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaa48),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2113 { PCI_DEVICE(0x1002, 0xaa50),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0xaa58),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa60),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2119 { PCI_DEVICE(0x1002, 0xaa68),
2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaa80),
2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0xaa88),
2124 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2125 { PCI_DEVICE(0x1002, 0xaa90),
2126 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2127 { PCI_DEVICE(0x1002, 0xaa98),
2128 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 2129 { PCI_DEVICE(0x1002, 0x9902),
2130 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2131 { PCI_DEVICE(0x1002, 0xaaa0),
2132 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2133 { PCI_DEVICE(0x1002, 0xaaa8),
2134 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2135 { PCI_DEVICE(0x1002, 0xaab0),
2136 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 2137 /* VIA VT8251/VT8237A */
9477c58e
TI		 2138 { PCI_DEVICE(0x1106, 0x3288),
2139 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2140 /* VIA GFX VT7122/VX900 */
2141 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2142 /* VIA GFX VT6122/VX11 */
2143 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2144 /* SIS966 */
2145 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2146 /* ULI M5461 */
2147 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2148 /* NVIDIA MCP */
0c2fd1bf
TI		 2149 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2150 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2151 .class_mask = 0xffffff,
9477c58e 2152 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2153 /* Teradici */
9477c58e
TI		 2154 { PCI_DEVICE(0x6549, 0x1200),
2155 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2156 { PCI_DEVICE(0x6549, 0x2200),
2157 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2158 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2159 /* CTHDA chips */
2160 { PCI_DEVICE(0x1102, 0x0010),
2161 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2162 { PCI_DEVICE(0x1102, 0x0012),
2163 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2164#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2165 /* the following entry conflicts with snd-ctxfi driver,
2166 * as ctxfi driver mutates from HD-audio to native mode with
2167 * a special command sequence.
2168 */
4e01f54b
TI		 2169 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2170 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2171 .class_mask = 0xffffff,
9477c58e 2172 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2173 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2174#else
2175 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2176 { PCI_DEVICE(0x1102, 0x0009),
2177 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2178 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2179#endif
e35d4b11
OS		 2180 /* Vortex86MX */
2181 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2182 /* VMware HDAudio */
2183 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2184 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2185 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2186 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2187 .class_mask = 0xffffff,
9477c58e 2188 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2189 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2190 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2191 .class_mask = 0xffffff,
9477c58e 2192 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2193 { 0, }
2194};
2195MODULE_DEVICE_TABLE(pci, azx_ids);
2196
2197/* pci_driver definition */
e9f66d9b 2198static struct pci_driver azx_driver = {
3733e424 2199 .name = KBUILD_MODNAME,
1da177e4
LT		 2200 .id_table = azx_ids,
2201 .probe = azx_probe,
e23e7a14 2202 .remove = azx_remove,
68cb2b55
TI		 2203 .driver = {
2204 .pm = AZX_PM_OPS,
2205 },
1da177e4
LT		 2206};
2207
e9f66d9b 2208module_pci_driver(azx_driver);
Linux kernel - Deliverables
This page took 0.778199 seconds and 5 git commands to generate.