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ALSA: hda - move eld->spk_alloc fixup to hdmi_update_eld()
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
84eb01be
TI		 37#include "hda_codec.h"
38#include "hda_local.h"
39
0ebaa24c
TI		 40static bool static_hdmi_pcm;
41module_param(static_hdmi_pcm, bool, 0644);
42MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
43
84eb01be
TI		 44/*
45 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 46 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 47 * more ports (DVI, HDMI or DisplayPort).
48 *
49 * The HDA correspondence of pipes/ports are converter/pin nodes.
50 */
73926656
SW		 51#define MAX_HDMI_CVTS 4
52#define MAX_HDMI_PINS 4
079d88cc 53
384a48d7
SW		 54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
079d88cc 63
384a48d7
SW		 64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 68
69 struct hda_codec *codec;
384a48d7 70 struct hdmi_eld sink_eld;
744626da 71 struct delayed_work work;
384a48d7 72};
079d88cc 73
384a48d7
SW		 74struct hdmi_spec {
75 int num_cvts;
76 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 77
384a48d7
SW		 78 int num_pins;
79 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
80 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
079d88cc
WF		 81
82 /*
384a48d7 83 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 84 */
85 struct hda_multi_out multiout;
fb79e1e0 86 const struct hda_pcm_stream *pcm_playback;
079d88cc
WF		 87};
88
89
90struct hdmi_audio_infoframe {
91 u8 type; /* 0x84 */
92 u8 ver; /* 0x01 */
93 u8 len; /* 0x0a */
94
53d7d69d
WF		 95 u8 checksum;
96
079d88cc
WF		 97 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
98 u8 SS01_SF24;
99 u8 CXT04;
100 u8 CA;
101 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 102};
103
104struct dp_audio_infoframe {
105 u8 type; /* 0x84 */
106 u8 len; /* 0x1b */
107 u8 ver; /* 0x11 << 2 */
108
109 u8 CC02_CT47; /* match with HDMI infoframe from this on */
110 u8 SS01_SF24;
111 u8 CXT04;
112 u8 CA;
113 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 114};
115
2b203dbb
TI		 116union audio_infoframe {
117 struct hdmi_audio_infoframe hdmi;
118 struct dp_audio_infoframe dp;
119 u8 bytes[0];
120};
121
079d88cc
WF		 122/*
123 * CEA speaker placement:
124 *
125 * FLH FCH FRH
126 * FLW FL FLC FC FRC FR FRW
127 *
128 * LFE
129 * TC
130 *
131 * RL RLC RC RRC RR
132 *
133 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
134 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
135 */
136enum cea_speaker_placement {
137 FL = (1 << 0), /* Front Left */
138 FC = (1 << 1), /* Front Center */
139 FR = (1 << 2), /* Front Right */
140 FLC = (1 << 3), /* Front Left Center */
141 FRC = (1 << 4), /* Front Right Center */
142 RL = (1 << 5), /* Rear Left */
143 RC = (1 << 6), /* Rear Center */
144 RR = (1 << 7), /* Rear Right */
145 RLC = (1 << 8), /* Rear Left Center */
146 RRC = (1 << 9), /* Rear Right Center */
147 LFE = (1 << 10), /* Low Frequency Effect */
148 FLW = (1 << 11), /* Front Left Wide */
149 FRW = (1 << 12), /* Front Right Wide */
150 FLH = (1 << 13), /* Front Left High */
151 FCH = (1 << 14), /* Front Center High */
152 FRH = (1 << 15), /* Front Right High */
153 TC = (1 << 16), /* Top Center */
154};
155
156/*
157 * ELD SA bits in the CEA Speaker Allocation data block
158 */
159static int eld_speaker_allocation_bits[] = {
160 [0] = FL | FR,
161 [1] = LFE,
162 [2] = FC,
163 [3] = RL | RR,
164 [4] = RC,
165 [5] = FLC | FRC,
166 [6] = RLC | RRC,
167 /* the following are not defined in ELD yet */
168 [7] = FLW | FRW,
169 [8] = FLH | FRH,
170 [9] = TC,
171 [10] = FCH,
172};
173
174struct cea_channel_speaker_allocation {
175 int ca_index;
176 int speakers[8];
177
178 /* derived values, just for convenience */
179 int channels;
180 int spk_mask;
181};
182
183/*
184 * ALSA sequence is:
185 *
186 * surround40 surround41 surround50 surround51 surround71
187 * ch0 front left = = = =
188 * ch1 front right = = = =
189 * ch2 rear left = = = =
190 * ch3 rear right = = = =
191 * ch4 LFE center center center
192 * ch5 LFE LFE
193 * ch6 side left
194 * ch7 side right
195 *
196 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
197 */
198static int hdmi_channel_mapping[0x32][8] = {
199 /* stereo */
200 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
201 /* 2.1 */
202 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
203 /* Dolby Surround */
204 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
205 /* surround40 */
206 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
207 /* 4ch */
208 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
209 /* surround41 */
9396d317 210 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 211 /* surround50 */
212 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
213 /* surround51 */
214 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
215 /* 7.1 */
216 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
217};
218
219/*
220 * This is an ordered list!
221 *
222 * The preceding ones have better chances to be selected by
53d7d69d 223 * hdmi_channel_allocation().
079d88cc
WF		 224 */
225static struct cea_channel_speaker_allocation channel_allocations[] = {
226/* channel: 7 6 5 4 3 2 1 0 */
227{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
228 /* 2.1 */
229{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
230 /* Dolby Surround */
231{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
232 /* surround40 */
233{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
234 /* surround41 */
235{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
236 /* surround50 */
237{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
238 /* surround51 */
239{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
240 /* 6.1 */
241{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
242 /* surround71 */
243{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
244
245{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
246{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
247{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
248{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
249{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
250{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
251{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
252{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
253{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
254{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
255{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
256{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
257{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
258{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
259{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
260{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
261{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
262{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
263{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
264{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
265{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
266{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
267{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
268{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
269{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
270{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
271{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
272{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
273{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
274{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
275{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
276{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
283{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
284{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
285{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
286};
287
288
289/*
290 * HDMI routines
291 */
292
384a48d7 293static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 294{
384a48d7 295 int pin_idx;
079d88cc 296
384a48d7
SW		 297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
298 if (spec->pins[pin_idx].pin_nid == pin_nid)
299 return pin_idx;
079d88cc 300
384a48d7
SW		 301 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
302 return -EINVAL;
303}
304
305static int hinfo_to_pin_index(struct hdmi_spec *spec,
306 struct hda_pcm_stream *hinfo)
307{
308 int pin_idx;
309
310 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
311 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
312 return pin_idx;
313
314 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
315 return -EINVAL;
316}
317
318static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
319{
320 int cvt_idx;
321
322 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
323 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
324 return cvt_idx;
325
326 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 327 return -EINVAL;
328}
329
14bc52b8
PLB		 330static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
331 struct snd_ctl_elem_info *uinfo)
332{
333 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
334 struct hdmi_spec *spec;
335 int pin_idx;
336
337 spec = codec->spec;
338 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
339
340 pin_idx = kcontrol->private_value;
341 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
342
343 return 0;
344}
345
346static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
350 struct hdmi_spec *spec;
351 int pin_idx;
352
353 spec = codec->spec;
354 pin_idx = kcontrol->private_value;
355
356 memcpy(ucontrol->value.bytes.data,
357 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
358
359 return 0;
360}
361
362static struct snd_kcontrol_new eld_bytes_ctl = {
363 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
364 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
365 .name = "ELD",
366 .info = hdmi_eld_ctl_info,
367 .get = hdmi_eld_ctl_get,
368};
369
370static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
371 int device)
372{
373 struct snd_kcontrol *kctl;
374 struct hdmi_spec *spec = codec->spec;
375 int err;
376
377 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
378 if (!kctl)
379 return -ENOMEM;
380 kctl->private_value = pin_idx;
381 kctl->id.device = device;
382
383 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
384 if (err < 0)
385 return err;
386
387 return 0;
388}
389
079d88cc
WF		 390#ifdef BE_PARANOID
391static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
392 int *packet_index, int *byte_index)
393{
394 int val;
395
396 val = snd_hda_codec_read(codec, pin_nid, 0,
397 AC_VERB_GET_HDMI_DIP_INDEX, 0);
398
399 *packet_index = val >> 5;
400 *byte_index = val & 0x1f;
401}
402#endif
403
404static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
405 int packet_index, int byte_index)
406{
407 int val;
408
409 val = (packet_index << 5) | (byte_index & 0x1f);
410
411 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
412}
413
414static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
415 unsigned char val)
416{
417 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
418}
419
384a48d7 420static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 421{
422 /* Unmute */
423 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
424 snd_hda_codec_write(codec, pin_nid, 0,
425 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
384a48d7 426 /* Disable pin out until stream is active*/
079d88cc 427 snd_hda_codec_write(codec, pin_nid, 0,
384a48d7 428 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
079d88cc
WF		 429}
430
384a48d7 431static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 432{
384a48d7 433 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 434 AC_VERB_GET_CVT_CHAN_COUNT, 0);
435}
436
437static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 438 hda_nid_t cvt_nid, int chs)
079d88cc 439{
384a48d7
SW		 440 if (chs != hdmi_get_channel_count(codec, cvt_nid))
441 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 442 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
443}
444
445
446/*
447 * Channel mapping routines
448 */
449
450/*
451 * Compute derived values in channel_allocations[].
452 */
453static void init_channel_allocations(void)
454{
455 int i, j;
456 struct cea_channel_speaker_allocation *p;
457
458 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
459 p = channel_allocations + i;
460 p->channels = 0;
461 p->spk_mask = 0;
462 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
463 if (p->speakers[j]) {
464 p->channels++;
465 p->spk_mask |= p->speakers[j];
466 }
467 }
468}
469
470/*
471 * The transformation takes two steps:
472 *
473 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
474 * spk_mask => (channel_allocations[]) => ai->CA
475 *
476 * TODO: it could select the wrong CA from multiple candidates.
477*/
384a48d7 478static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 479{
079d88cc 480 int i;
53d7d69d 481 int ca = 0;
079d88cc 482 int spk_mask = 0;
079d88cc
WF		 483 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
484
485 /*
486 * CA defaults to 0 for basic stereo audio
487 */
488 if (channels <= 2)
489 return 0;
490
079d88cc
WF		 491 /*
492 * expand ELD's speaker allocation mask
493 *
494 * ELD tells the speaker mask in a compact(paired) form,
495 * expand ELD's notions to match the ones used by Audio InfoFrame.
496 */
497 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
498 if (eld->spk_alloc & (1 << i))
499 spk_mask |= eld_speaker_allocation_bits[i];
500 }
501
502 /* search for the first working match in the CA table */
503 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
504 if (channels == channel_allocations[i].channels &&
505 (spk_mask & channel_allocations[i].spk_mask) ==
506 channel_allocations[i].spk_mask) {
53d7d69d 507 ca = channel_allocations[i].ca_index;
079d88cc
WF		 508 break;
509 }
510 }
511
512 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 513 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 514 ca, channels, buf);
079d88cc 515
53d7d69d 516 return ca;
079d88cc
WF		 517}
518
519static void hdmi_debug_channel_mapping(struct hda_codec *codec,
520 hda_nid_t pin_nid)
521{
522#ifdef CONFIG_SND_DEBUG_VERBOSE
523 int i;
524 int slot;
525
526 for (i = 0; i < 8; i++) {
527 slot = snd_hda_codec_read(codec, pin_nid, 0,
528 AC_VERB_GET_HDMI_CHAN_SLOT, i);
529 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
530 slot >> 4, slot & 0xf);
531 }
532#endif
533}
534
535
536static void hdmi_setup_channel_mapping(struct hda_codec *codec,
537 hda_nid_t pin_nid,
53d7d69d 538 int ca)
079d88cc
WF		 539{
540 int i;
079d88cc
WF		 541 int err;
542
543 if (hdmi_channel_mapping[ca][1] == 0) {
544 for (i = 0; i < channel_allocations[ca].channels; i++)
545 hdmi_channel_mapping[ca][i] = i | (i << 4);
546 for (; i < 8; i++)
547 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
548 }
549
550 for (i = 0; i < 8; i++) {
551 err = snd_hda_codec_write(codec, pin_nid, 0,
552 AC_VERB_SET_HDMI_CHAN_SLOT,
553 hdmi_channel_mapping[ca][i]);
554 if (err) {
2abbf439
WF		 555 snd_printdd(KERN_NOTICE
556 "HDMI: channel mapping failed\n");
079d88cc
WF		 557 break;
558 }
559 }
560
561 hdmi_debug_channel_mapping(codec, pin_nid);
562}
563
564
565/*
566 * Audio InfoFrame routines
567 */
568
569/*
570 * Enable Audio InfoFrame Transmission
571 */
572static void hdmi_start_infoframe_trans(struct hda_codec *codec,
573 hda_nid_t pin_nid)
574{
575 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
576 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
577 AC_DIPXMIT_BEST);
578}
579
580/*
581 * Disable Audio InfoFrame Transmission
582 */
583static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
584 hda_nid_t pin_nid)
585{
586 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
587 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
588 AC_DIPXMIT_DISABLE);
589}
590
591static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
592{
593#ifdef CONFIG_SND_DEBUG_VERBOSE
594 int i;
595 int size;
596
597 size = snd_hdmi_get_eld_size(codec, pin_nid);
598 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
599
600 for (i = 0; i < 8; i++) {
601 size = snd_hda_codec_read(codec, pin_nid, 0,
602 AC_VERB_GET_HDMI_DIP_SIZE, i);
603 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
604 }
605#endif
606}
607
608static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
609{
610#ifdef BE_PARANOID
611 int i, j;
612 int size;
613 int pi, bi;
614 for (i = 0; i < 8; i++) {
615 size = snd_hda_codec_read(codec, pin_nid, 0,
616 AC_VERB_GET_HDMI_DIP_SIZE, i);
617 if (size == 0)
618 continue;
619
620 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
621 for (j = 1; j < 1000; j++) {
622 hdmi_write_dip_byte(codec, pin_nid, 0x0);
623 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
624 if (pi != i)
625 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
626 bi, pi, i);
627 if (bi == 0) /* byte index wrapped around */
628 break;
629 }
630 snd_printd(KERN_INFO
631 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
632 i, size, j);
633 }
634#endif
635}
636
53d7d69d 637static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 638{
53d7d69d 639 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 640 u8 sum = 0;
641 int i;
642
53d7d69d 643 hdmi_ai->checksum = 0;
079d88cc 644
53d7d69d 645 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 646 sum += bytes[i];
647
53d7d69d 648 hdmi_ai->checksum = -sum;
079d88cc
WF		 649}
650
651static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
652 hda_nid_t pin_nid,
53d7d69d 653 u8 *dip, int size)
079d88cc 654{
079d88cc
WF		 655 int i;
656
657 hdmi_debug_dip_size(codec, pin_nid);
658 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
659
079d88cc 660 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 661 for (i = 0; i < size; i++)
662 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 663}
664
665static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 666 u8 *dip, int size)
079d88cc 667{
079d88cc
WF		 668 u8 val;
669 int i;
670
671 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
672 != AC_DIPXMIT_BEST)
673 return false;
674
675 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 676 for (i = 0; i < size; i++) {
079d88cc
WF		 677 val = snd_hda_codec_read(codec, pin_nid, 0,
678 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 679 if (val != dip[i])
079d88cc
WF		 680 return false;
681 }
682
683 return true;
684}
685
384a48d7 686static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
079d88cc
WF		 687 struct snd_pcm_substream *substream)
688{
689 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 690 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
691 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 692 int channels = substream->runtime->channels;
384a48d7 693 struct hdmi_eld *eld;
53d7d69d 694 int ca;
2b203dbb 695 union audio_infoframe ai;
079d88cc 696
384a48d7
SW		 697 eld = &spec->pins[pin_idx].sink_eld;
698 if (!eld->monitor_present)
699 return;
079d88cc 700
384a48d7
SW		 701 ca = hdmi_channel_allocation(eld, channels);
702
703 memset(&ai, 0, sizeof(ai));
704 if (eld->conn_type == 0) { /* HDMI */
705 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
706
707 hdmi_ai->type = 0x84;
708 hdmi_ai->ver = 0x01;
709 hdmi_ai->len = 0x0a;
710 hdmi_ai->CC02_CT47 = channels - 1;
711 hdmi_ai->CA = ca;
712 hdmi_checksum_audio_infoframe(hdmi_ai);
713 } else if (eld->conn_type == 1) { /* DisplayPort */
714 struct dp_audio_infoframe *dp_ai = &ai.dp;
715
716 dp_ai->type = 0x84;
717 dp_ai->len = 0x1b;
718 dp_ai->ver = 0x11 << 2;
719 dp_ai->CC02_CT47 = channels - 1;
720 dp_ai->CA = ca;
721 } else {
722 snd_printd("HDMI: unknown connection type at pin %d\n",
723 pin_nid);
724 return;
725 }
53d7d69d 726
384a48d7
SW		 727 /*
728 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
729 * sizeof(*dp_ai) to avoid partial match/update problems when
730 * the user switches between HDMI/DP monitors.
731 */
732 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
733 sizeof(ai))) {
734 snd_printdd("hdmi_setup_audio_infoframe: "
735 "pin=%d channels=%d\n",
736 pin_nid,
737 channels);
738 hdmi_setup_channel_mapping(codec, pin_nid, ca);
739 hdmi_stop_infoframe_trans(codec, pin_nid);
740 hdmi_fill_audio_infoframe(codec, pin_nid,
741 ai.bytes, sizeof(ai));
742 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc
WF		 743 }
744}
745
746
747/*
748 * Unsolicited events
749 */
750
744626da 751static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, bool retry);
38faddb1 752
079d88cc
WF		 753static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
754{
755 struct hdmi_spec *spec = codec->spec;
5d44f927
SW		 756 int pin_nid = res >> AC_UNSOL_RES_TAG_SHIFT;
757 int pd = !!(res & AC_UNSOL_RES_PD);
079d88cc 758 int eldv = !!(res & AC_UNSOL_RES_ELDV);
384a48d7 759 int pin_idx;
079d88cc
WF		 760
761 printk(KERN_INFO
384a48d7
SW		 762 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
763 codec->addr, pin_nid, pd, eldv);
079d88cc 764
384a48d7
SW		 765 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
766 if (pin_idx < 0)
079d88cc
WF		 767 return;
768
744626da 769 hdmi_present_sense(&spec->pins[pin_idx], true);
079d88cc
WF		 770}
771
772static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
773{
774 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
775 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
776 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
777 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
778
779 printk(KERN_INFO
384a48d7
SW		 780 "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
781 codec->addr,
079d88cc
WF		 782 tag,
783 subtag,
784 cp_state,
785 cp_ready);
786
787 /* TODO */
788 if (cp_state)
789 ;
790 if (cp_ready)
791 ;
792}
793
794
795static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
796{
797 struct hdmi_spec *spec = codec->spec;
798 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
799 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
800
384a48d7 801 if (pin_nid_to_pin_index(spec, tag) < 0) {
079d88cc
WF		 802 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
803 return;
804 }
805
806 if (subtag == 0)
807 hdmi_intrinsic_event(codec, res);
808 else
809 hdmi_non_intrinsic_event(codec, res);
810}
811
812/*
813 * Callbacks
814 */
815
92f10b3f
TI		 816/* HBR should be Non-PCM, 8 channels */
817#define is_hbr_format(format) \
818 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
819
384a48d7
SW		 820static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
821 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 822{
ea87d1c4
AH		 823 int pinctl;
824 int new_pinctl = 0;
ea87d1c4 825
384a48d7
SW		 826 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
827 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 828 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
829
830 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 831 if (is_hbr_format(format))
ea87d1c4
AH		 832 new_pinctl |= AC_PINCTL_EPT_HBR;
833 else
834 new_pinctl |= AC_PINCTL_EPT_NATIVE;
835
836 snd_printdd("hdmi_setup_stream: "
837 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 838 pin_nid,
ea87d1c4
AH		 839 pinctl == new_pinctl ? "" : "new-",
840 new_pinctl);
841
842 if (pinctl != new_pinctl)
384a48d7 843 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 844 AC_VERB_SET_PIN_WIDGET_CONTROL,
845 new_pinctl);
ea87d1c4 846
384a48d7 847 }
92f10b3f 848 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 849 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
850 return -EINVAL;
851 }
079d88cc 852
384a48d7 853 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 854 return 0;
079d88cc
WF		 855}
856
bbbe3390
TI		 857/*
858 * HDA PCM callbacks
859 */
860static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
861 struct hda_codec *codec,
862 struct snd_pcm_substream *substream)
863{
864 struct hdmi_spec *spec = codec->spec;
639cef0e 865 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 866 int pin_idx, cvt_idx, mux_idx = 0;
867 struct hdmi_spec_per_pin *per_pin;
868 struct hdmi_eld *eld;
869 struct hdmi_spec_per_cvt *per_cvt = NULL;
870 int pinctl;
bbbe3390 871
384a48d7
SW		 872 /* Validate hinfo */
873 pin_idx = hinfo_to_pin_index(spec, hinfo);
874 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 875 return -EINVAL;
384a48d7
SW		 876 per_pin = &spec->pins[pin_idx];
877 eld = &per_pin->sink_eld;
878
879 /* Dynamically assign converter to stream */
880 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
881 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 882
384a48d7
SW		 883 /* Must not already be assigned */
884 if (per_cvt->assigned)
885 continue;
886 /* Must be in pin's mux's list of converters */
887 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
888 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
889 break;
890 /* Not in mux list */
891 if (mux_idx == per_pin->num_mux_nids)
892 continue;
893 break;
894 }
895 /* No free converters */
896 if (cvt_idx == spec->num_cvts)
897 return -ENODEV;
898
899 /* Claim converter */
900 per_cvt->assigned = 1;
901 hinfo->nid = per_cvt->cvt_nid;
902
903 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
904 AC_VERB_SET_CONNECT_SEL,
905 mux_idx);
906 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
907 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
908 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
909 AC_VERB_SET_PIN_WIDGET_CONTROL,
910 pinctl | PIN_OUT);
911 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 912
2def8172 913 /* Initially set the converter's capabilities */
384a48d7
SW		 914 hinfo->channels_min = per_cvt->channels_min;
915 hinfo->channels_max = per_cvt->channels_max;
916 hinfo->rates = per_cvt->rates;
917 hinfo->formats = per_cvt->formats;
918 hinfo->maxbps = per_cvt->maxbps;
2def8172 919
384a48d7 920 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 921 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 922 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390
TI		 923 if (hinfo->channels_min > hinfo->channels_max ||
924 !hinfo->rates || !hinfo->formats)
925 return -ENODEV;
bbbe3390 926 }
2def8172
SW		 927
928 /* Store the updated parameters */
639cef0e
TI		 929 runtime->hw.channels_min = hinfo->channels_min;
930 runtime->hw.channels_max = hinfo->channels_max;
931 runtime->hw.formats = hinfo->formats;
932 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 933
934 snd_pcm_hw_constraint_step(substream->runtime, 0,
935 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 936 return 0;
937}
938
079d88cc
WF		 939/*
940 * HDA/HDMI auto parsing
941 */
384a48d7 942static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 943{
944 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 945 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
946 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 947
948 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
949 snd_printk(KERN_WARNING
950 "HDMI: pin %d wcaps %#x "
951 "does not support connection list\n",
952 pin_nid, get_wcaps(codec, pin_nid));
953 return -EINVAL;
954 }
955
384a48d7
SW		 956 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
957 per_pin->mux_nids,
958 HDA_MAX_CONNECTIONS);
079d88cc
WF		 959
960 return 0;
961}
962
744626da 963static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, bool retry)
079d88cc 964{
744626da
WF		 965 struct hda_codec *codec = per_pin->codec;
966 struct hdmi_eld *eld = &per_pin->sink_eld;
967 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 968 /*
969 * Always execute a GetPinSense verb here, even when called from
970 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
971 * response's PD bit is not the real PD value, but indicates that
972 * the real PD value changed. An older version of the HD-audio
973 * specification worked this way. Hence, we just ignore the data in
974 * the unsolicited response to avoid custom WARs.
975 */
079d88cc 976 int present = snd_hda_pin_sense(codec, pin_nid);
b95d68b8 977 bool eld_valid = false;
079d88cc 978
b95d68b8 979 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
5d44f927 980
079d88cc 981 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927 982 if (eld->monitor_present)
b95d68b8 983 eld_valid = !!(present & AC_PINSENSE_ELDV);
079d88cc 984
5d44f927 985 printk(KERN_INFO
384a48d7 986 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
b95d68b8 987 codec->addr, pin_nid, eld->monitor_present, eld_valid);
5d44f927 988
744626da 989 if (eld_valid) {
5d44f927
SW		 990 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
991 snd_hdmi_show_eld(eld);
744626da
WF		 992 else if (retry) {
993 queue_delayed_work(codec->bus->workq,
994 &per_pin->work,
995 msecs_to_jiffies(300));
996 }
997 }
5d44f927
SW		 998
999 snd_hda_input_jack_report(codec, pin_nid);
079d88cc
WF		 1000}
1001
744626da
WF		 1002static void hdmi_repoll_eld(struct work_struct *work)
1003{
1004 struct hdmi_spec_per_pin *per_pin =
1005 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1006
1007 hdmi_present_sense(per_pin, false);
1008}
1009
079d88cc
WF		 1010static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1011{
1012 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1013 unsigned int caps, config;
1014 int pin_idx;
1015 struct hdmi_spec_per_pin *per_pin;
07acecc1 1016 int err;
079d88cc 1017
384a48d7
SW		 1018 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
1019 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1020 return 0;
1021
1022 config = snd_hda_codec_read(codec, pin_nid, 0,
1023 AC_VERB_GET_CONFIG_DEFAULT, 0);
1024 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1025 return 0;
1026
1027 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1028 return -E2BIG;
384a48d7
SW		 1029
1030 pin_idx = spec->num_pins;
1031 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1032
1033 per_pin->pin_nid = pin_nid;
079d88cc 1034
384a48d7
SW		 1035 err = hdmi_read_pin_conn(codec, pin_idx);
1036 if (err < 0)
1037 return err;
079d88cc 1038
079d88cc
WF		 1039 spec->num_pins++;
1040
384a48d7 1041 return 0;
079d88cc
WF		 1042}
1043
384a48d7 1044static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1045{
1046 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1047 int cvt_idx;
1048 struct hdmi_spec_per_cvt *per_cvt;
1049 unsigned int chans;
1050 int err;
079d88cc 1051
116dcde6
DH		 1052 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1053 return -E2BIG;
1054
384a48d7
SW		 1055 chans = get_wcaps(codec, cvt_nid);
1056 chans = get_wcaps_channels(chans);
1057
1058 cvt_idx = spec->num_cvts;
1059 per_cvt = &spec->cvts[cvt_idx];
1060
1061 per_cvt->cvt_nid = cvt_nid;
1062 per_cvt->channels_min = 2;
1063 if (chans <= 16)
1064 per_cvt->channels_max = chans;
1065
1066 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1067 &per_cvt->rates,
1068 &per_cvt->formats,
1069 &per_cvt->maxbps);
1070 if (err < 0)
1071 return err;
1072
079d88cc
WF		 1073 spec->num_cvts++;
1074
1075 return 0;
1076}
1077
1078static int hdmi_parse_codec(struct hda_codec *codec)
1079{
1080 hda_nid_t nid;
1081 int i, nodes;
1082
1083 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1084 if (!nid || nodes < 0) {
1085 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1086 return -EINVAL;
1087 }
1088
1089 for (i = 0; i < nodes; i++, nid++) {
1090 unsigned int caps;
1091 unsigned int type;
1092
1093 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1094 type = get_wcaps_type(caps);
1095
1096 if (!(caps & AC_WCAP_DIGITAL))
1097 continue;
1098
1099 switch (type) {
1100 case AC_WID_AUD_OUT:
384a48d7 1101 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1102 break;
1103 case AC_WID_PIN:
3eaead57 1104 hdmi_add_pin(codec, nid);
079d88cc
WF		 1105 break;
1106 }
1107 }
1108
1109 /*
1110 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1111 * can be lost and presence sense verb will become inaccurate if the
1112 * HDA link is powered off at hot plug or hw initialization time.
1113 */
1114#ifdef CONFIG_SND_HDA_POWER_SAVE
1115 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1116 AC_PWRST_EPSS))
1117 codec->bus->power_keep_link_on = 1;
1118#endif
1119
1120 return 0;
1121}
1122
84eb01be
TI		 1123/*
1124 */
384a48d7 1125static char *generic_hdmi_pcm_names[MAX_HDMI_PINS] = {
84eb01be
TI		 1126 "HDMI 0",
1127 "HDMI 1",
1128 "HDMI 2",
73926656 1129 "HDMI 3",
84eb01be
TI		 1130};
1131
1132/*
1133 * HDMI callbacks
1134 */
1135
1136static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1137 struct hda_codec *codec,
1138 unsigned int stream_tag,
1139 unsigned int format,
1140 struct snd_pcm_substream *substream)
1141{
384a48d7
SW		 1142 hda_nid_t cvt_nid = hinfo->nid;
1143 struct hdmi_spec *spec = codec->spec;
1144 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1145 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1146
1147 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1148
384a48d7 1149 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
84eb01be 1150
384a48d7 1151 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1152}
1153
384a48d7
SW		 1154static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1155 struct hda_codec *codec,
1156 struct snd_pcm_substream *substream)
1157{
1158 struct hdmi_spec *spec = codec->spec;
1159 int cvt_idx, pin_idx;
1160 struct hdmi_spec_per_cvt *per_cvt;
1161 struct hdmi_spec_per_pin *per_pin;
1162 int pinctl;
1163
1164 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1165
1166 if (hinfo->nid) {
1167 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1168 if (snd_BUG_ON(cvt_idx < 0))
1169 return -EINVAL;
1170 per_cvt = &spec->cvts[cvt_idx];
1171
1172 snd_BUG_ON(!per_cvt->assigned);
1173 per_cvt->assigned = 0;
1174 hinfo->nid = 0;
1175
1176 pin_idx = hinfo_to_pin_index(spec, hinfo);
1177 if (snd_BUG_ON(pin_idx < 0))
1178 return -EINVAL;
1179 per_pin = &spec->pins[pin_idx];
1180
1181 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1182 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1183 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1184 AC_VERB_SET_PIN_WIDGET_CONTROL,
1185 pinctl & ~PIN_OUT);
1186 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1187 }
1188
1189 return 0;
1190}
1191
1192static const struct hda_pcm_ops generic_ops = {
1193 .open = hdmi_pcm_open,
1194 .prepare = generic_hdmi_playback_pcm_prepare,
1195 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1196};
1197
1198static int generic_hdmi_build_pcms(struct hda_codec *codec)
1199{
1200 struct hdmi_spec *spec = codec->spec;
384a48d7 1201 int pin_idx;
84eb01be 1202
384a48d7
SW		 1203 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1204 struct hda_pcm *info;
84eb01be
TI		 1205 struct hda_pcm_stream *pstr;
1206
384a48d7
SW		 1207 info = &spec->pcm_rec[pin_idx];
1208 info->name = generic_hdmi_pcm_names[pin_idx];
84eb01be 1209 info->pcm_type = HDA_PCM_TYPE_HDMI;
384a48d7 1210
84eb01be 1211 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1212 pstr->substreams = 1;
1213 pstr->ops = generic_ops;
1214 /* other pstr fields are set in open */
84eb01be
TI		 1215 }
1216
384a48d7
SW		 1217 codec->num_pcms = spec->num_pins;
1218 codec->pcm_info = spec->pcm_rec;
1219
84eb01be
TI		 1220 return 0;
1221}
1222
0b6c49b5
DH		 1223static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1224{
1225 int err;
1226 char hdmi_str[32];
1227 struct hdmi_spec *spec = codec->spec;
1228 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1229 int pcmdev = spec->pcm_rec[pin_idx].device;
1230
1231 snprintf(hdmi_str, sizeof(hdmi_str), "HDMI/DP,pcm=%d", pcmdev);
1232
1233 err = snd_hda_input_jack_add(codec, per_pin->pin_nid,
1234 SND_JACK_VIDEOOUT, pcmdev > 0 ? hdmi_str : NULL);
1235 if (err < 0)
1236 return err;
1237
744626da 1238 hdmi_present_sense(per_pin, false);
0b6c49b5
DH		 1239 return 0;
1240}
1241
84eb01be
TI		 1242static int generic_hdmi_build_controls(struct hda_codec *codec)
1243{
1244 struct hdmi_spec *spec = codec->spec;
1245 int err;
384a48d7 1246 int pin_idx;
84eb01be 1247
384a48d7
SW		 1248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1249 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1250
1251 err = generic_hdmi_build_jack(codec, pin_idx);
1252 if (err < 0)
1253 return err;
1254
384a48d7
SW		 1255 err = snd_hda_create_spdif_out_ctls(codec,
1256 per_pin->pin_nid,
1257 per_pin->mux_nids[0]);
84eb01be
TI		 1258 if (err < 0)
1259 return err;
384a48d7 1260 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1261
1262 /* add control for ELD Bytes */
1263 err = hdmi_create_eld_ctl(codec,
1264 pin_idx,
1265 spec->pcm_rec[pin_idx].device);
1266
1267 if (err < 0)
1268 return err;
84eb01be
TI		 1269 }
1270
1271 return 0;
1272}
1273
1274static int generic_hdmi_init(struct hda_codec *codec)
1275{
1276 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1277 int pin_idx;
1278
1279 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1280 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1281 hda_nid_t pin_nid = per_pin->pin_nid;
1282 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1283
384a48d7
SW		 1284 hdmi_init_pin(codec, pin_nid);
1285 snd_hda_codec_write(codec, pin_nid, 0,
84eb01be 1286 AC_VERB_SET_UNSOLICITED_ENABLE,
384a48d7
SW		 1287 AC_USRSP_EN | pin_nid);
1288
744626da
WF		 1289 per_pin->codec = codec;
1290 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1291 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be
TI		 1292 }
1293 return 0;
1294}
1295
1296static void generic_hdmi_free(struct hda_codec *codec)
1297{
1298 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1299 int pin_idx;
1300
1301 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1302 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1303 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1304
744626da 1305 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1306 snd_hda_eld_proc_free(codec, eld);
1307 }
07acecc1 1308 snd_hda_input_jack_free(codec);
84eb01be 1309
744626da 1310 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1311 kfree(spec);
1312}
1313
fb79e1e0 1314static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1315 .init = generic_hdmi_init,
1316 .free = generic_hdmi_free,
1317 .build_pcms = generic_hdmi_build_pcms,
1318 .build_controls = generic_hdmi_build_controls,
1319 .unsol_event = hdmi_unsol_event,
1320};
1321
1322static int patch_generic_hdmi(struct hda_codec *codec)
1323{
1324 struct hdmi_spec *spec;
84eb01be
TI		 1325
1326 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1327 if (spec == NULL)
1328 return -ENOMEM;
1329
1330 codec->spec = spec;
1331 if (hdmi_parse_codec(codec) < 0) {
1332 codec->spec = NULL;
1333 kfree(spec);
1334 return -EINVAL;
1335 }
1336 codec->patch_ops = generic_hdmi_patch_ops;
1337
84eb01be
TI		 1338 init_channel_allocations();
1339
1340 return 0;
1341}
1342
3aaf8980
SW		 1343/*
1344 * Shared non-generic implementations
1345 */
1346
1347static int simple_playback_build_pcms(struct hda_codec *codec)
1348{
1349 struct hdmi_spec *spec = codec->spec;
1350 struct hda_pcm *info = spec->pcm_rec;
1351 int i;
1352
1353 codec->num_pcms = spec->num_cvts;
1354 codec->pcm_info = info;
1355
1356 for (i = 0; i < codec->num_pcms; i++, info++) {
1357 unsigned int chans;
1358 struct hda_pcm_stream *pstr;
1359
384a48d7 1360 chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
3aaf8980
SW		 1361 chans = get_wcaps_channels(chans);
1362
1363 info->name = generic_hdmi_pcm_names[i];
1364 info->pcm_type = HDA_PCM_TYPE_HDMI;
1365 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1366 snd_BUG_ON(!spec->pcm_playback);
1367 *pstr = *spec->pcm_playback;
384a48d7 1368 pstr->nid = spec->cvts[i].cvt_nid;
3aaf8980
SW		 1369 if (pstr->channels_max <= 2 && chans && chans <= 16)
1370 pstr->channels_max = chans;
1371 }
1372
1373 return 0;
1374}
1375
1376static int simple_playback_build_controls(struct hda_codec *codec)
1377{
1378 struct hdmi_spec *spec = codec->spec;
1379 int err;
1380 int i;
1381
1382 for (i = 0; i < codec->num_pcms; i++) {
1383 err = snd_hda_create_spdif_out_ctls(codec,
384a48d7
SW		 1384 spec->cvts[i].cvt_nid,
1385 spec->cvts[i].cvt_nid);
3aaf8980
SW		 1386 if (err < 0)
1387 return err;
1388 }
1389
1390 return 0;
1391}
1392
1393static void simple_playback_free(struct hda_codec *codec)
1394{
1395 struct hdmi_spec *spec = codec->spec;
1396
1397 kfree(spec);
1398}
1399
84eb01be
TI		 1400/*
1401 * Nvidia specific implementations
1402 */
1403
1404#define Nv_VERB_SET_Channel_Allocation 0xF79
1405#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1406#define Nv_VERB_SET_Audio_Protection_On 0xF98
1407#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1408
1409#define nvhdmi_master_con_nid_7x 0x04
1410#define nvhdmi_master_pin_nid_7x 0x05
1411
fb79e1e0 1412static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1413 /*front, rear, clfe, rear_surr */
1414 0x6, 0x8, 0xa, 0xc,
1415};
1416
fb79e1e0 1417static const struct hda_verb nvhdmi_basic_init_7x[] = {
84eb01be
TI		 1418 /* set audio protect on */
1419 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1420 /* enable digital output on pin widget */
1421 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1422 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1423 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1424 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1425 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1426 {} /* terminator */
1427};
1428
1429#ifdef LIMITED_RATE_FMT_SUPPORT
1430/* support only the safe format and rate */
1431#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1432#define SUPPORTED_MAXBPS 16
1433#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1434#else
1435/* support all rates and formats */
1436#define SUPPORTED_RATES \
1437 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1438 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1439 SNDRV_PCM_RATE_192000)
1440#define SUPPORTED_MAXBPS 24
1441#define SUPPORTED_FORMATS \
1442 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1443#endif
1444
1445static int nvhdmi_7x_init(struct hda_codec *codec)
1446{
1447 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1448 return 0;
1449}
1450
393004b2
ND		 1451static unsigned int channels_2_6_8[] = {
1452 2, 6, 8
1453};
1454
1455static unsigned int channels_2_8[] = {
1456 2, 8
1457};
1458
1459static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1460 .count = ARRAY_SIZE(channels_2_6_8),
1461 .list = channels_2_6_8,
1462 .mask = 0,
1463};
1464
1465static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1466 .count = ARRAY_SIZE(channels_2_8),
1467 .list = channels_2_8,
1468 .mask = 0,
1469};
1470
84eb01be
TI		 1471static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1472 struct hda_codec *codec,
1473 struct snd_pcm_substream *substream)
1474{
1475 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1476 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1477
1478 switch (codec->preset->id) {
1479 case 0x10de0002:
1480 case 0x10de0003:
1481 case 0x10de0005:
1482 case 0x10de0006:
1483 hw_constraints_channels = &hw_constraints_2_8_channels;
1484 break;
1485 case 0x10de0007:
1486 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1487 break;
1488 default:
1489 break;
1490 }
1491
1492 if (hw_constraints_channels != NULL) {
1493 snd_pcm_hw_constraint_list(substream->runtime, 0,
1494 SNDRV_PCM_HW_PARAM_CHANNELS,
1495 hw_constraints_channels);
ad09fc9d
TI		 1496 } else {
1497 snd_pcm_hw_constraint_step(substream->runtime, 0,
1498 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1499 }
1500
84eb01be
TI		 1501 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1502}
1503
1504static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1505 struct hda_codec *codec,
1506 struct snd_pcm_substream *substream)
1507{
1508 struct hdmi_spec *spec = codec->spec;
1509 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1510}
1511
1512static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1513 struct hda_codec *codec,
1514 unsigned int stream_tag,
1515 unsigned int format,
1516 struct snd_pcm_substream *substream)
1517{
1518 struct hdmi_spec *spec = codec->spec;
1519 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1520 stream_tag, format, substream);
1521}
1522
1f348522
AP		 1523static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1524 int channels)
1525{
1526 unsigned int chanmask;
1527 int chan = channels ? (channels - 1) : 1;
1528
1529 switch (channels) {
1530 default:
1531 case 0:
1532 case 2:
1533 chanmask = 0x00;
1534 break;
1535 case 4:
1536 chanmask = 0x08;
1537 break;
1538 case 6:
1539 chanmask = 0x0b;
1540 break;
1541 case 8:
1542 chanmask = 0x13;
1543 break;
1544 }
1545
1546 /* Set the audio infoframe channel allocation and checksum fields. The
1547 * channel count is computed implicitly by the hardware. */
1548 snd_hda_codec_write(codec, 0x1, 0,
1549 Nv_VERB_SET_Channel_Allocation, chanmask);
1550
1551 snd_hda_codec_write(codec, 0x1, 0,
1552 Nv_VERB_SET_Info_Frame_Checksum,
1553 (0x71 - chan - chanmask));
1554}
1555
84eb01be
TI		 1556static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1557 struct hda_codec *codec,
1558 struct snd_pcm_substream *substream)
1559{
1560 struct hdmi_spec *spec = codec->spec;
1561 int i;
1562
1563 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1564 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1565 for (i = 0; i < 4; i++) {
1566 /* set the stream id */
1567 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1568 AC_VERB_SET_CHANNEL_STREAMID, 0);
1569 /* set the stream format */
1570 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1571 AC_VERB_SET_STREAM_FORMAT, 0);
1572 }
1573
1f348522
AP		 1574 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1575 * streams are disabled. */
1576 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1577
84eb01be
TI		 1578 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1579}
1580
1581static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1582 struct hda_codec *codec,
1583 unsigned int stream_tag,
1584 unsigned int format,
1585 struct snd_pcm_substream *substream)
1586{
1587 int chs;
112daa7a 1588 unsigned int dataDCC2, channel_id;
84eb01be 1589 int i;
7c935976
SW		 1590 struct hdmi_spec *spec = codec->spec;
1591 struct hda_spdif_out *spdif =
384a48d7 1592 snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 1593
1594 mutex_lock(&codec->spdif_mutex);
1595
1596 chs = substream->runtime->channels;
84eb01be 1597
84eb01be
TI		 1598 dataDCC2 = 0x2;
1599
84eb01be 1600 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 1601 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1602 snd_hda_codec_write(codec,
1603 nvhdmi_master_con_nid_7x,
1604 0,
1605 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1606 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1607
1608 /* set the stream id */
1609 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1610 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1611
1612 /* set the stream format */
1613 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1614 AC_VERB_SET_STREAM_FORMAT, format);
1615
1616 /* turn on again (if needed) */
1617 /* enable and set the channel status audio/data flag */
7c935976 1618 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1619 snd_hda_codec_write(codec,
1620 nvhdmi_master_con_nid_7x,
1621 0,
1622 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1623 spdif->ctls & 0xff);
84eb01be
TI		 1624 snd_hda_codec_write(codec,
1625 nvhdmi_master_con_nid_7x,
1626 0,
1627 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1628 }
1629
1630 for (i = 0; i < 4; i++) {
1631 if (chs == 2)
1632 channel_id = 0;
1633 else
1634 channel_id = i * 2;
1635
1636 /* turn off SPDIF once;
1637 *otherwise the IEC958 bits won't be updated
1638 */
1639 if (codec->spdif_status_reset &&
7c935976 1640 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1641 snd_hda_codec_write(codec,
1642 nvhdmi_con_nids_7x[i],
1643 0,
1644 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1645 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1646 /* set the stream id */
1647 snd_hda_codec_write(codec,
1648 nvhdmi_con_nids_7x[i],
1649 0,
1650 AC_VERB_SET_CHANNEL_STREAMID,
1651 (stream_tag << 4) | channel_id);
1652 /* set the stream format */
1653 snd_hda_codec_write(codec,
1654 nvhdmi_con_nids_7x[i],
1655 0,
1656 AC_VERB_SET_STREAM_FORMAT,
1657 format);
1658 /* turn on again (if needed) */
1659 /* enable and set the channel status audio/data flag */
1660 if (codec->spdif_status_reset &&
7c935976 1661 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1662 snd_hda_codec_write(codec,
1663 nvhdmi_con_nids_7x[i],
1664 0,
1665 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1666 spdif->ctls & 0xff);
84eb01be
TI		 1667 snd_hda_codec_write(codec,
1668 nvhdmi_con_nids_7x[i],
1669 0,
1670 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1671 }
1672 }
1673
1f348522 1674 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 1675
1676 mutex_unlock(&codec->spdif_mutex);
1677 return 0;
1678}
1679
fb79e1e0 1680static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 1681 .substreams = 1,
1682 .channels_min = 2,
1683 .channels_max = 8,
1684 .nid = nvhdmi_master_con_nid_7x,
1685 .rates = SUPPORTED_RATES,
1686 .maxbps = SUPPORTED_MAXBPS,
1687 .formats = SUPPORTED_FORMATS,
1688 .ops = {
1689 .open = simple_playback_pcm_open,
1690 .close = nvhdmi_8ch_7x_pcm_close,
1691 .prepare = nvhdmi_8ch_7x_pcm_prepare
1692 },
1693};
1694
fb79e1e0 1695static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
84eb01be
TI		 1696 .substreams = 1,
1697 .channels_min = 2,
1698 .channels_max = 2,
1699 .nid = nvhdmi_master_con_nid_7x,
1700 .rates = SUPPORTED_RATES,
1701 .maxbps = SUPPORTED_MAXBPS,
1702 .formats = SUPPORTED_FORMATS,
1703 .ops = {
1704 .open = simple_playback_pcm_open,
1705 .close = simple_playback_pcm_close,
1706 .prepare = simple_playback_pcm_prepare
1707 },
1708};
1709
fb79e1e0 1710static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
3aaf8980
SW		 1711 .build_controls = simple_playback_build_controls,
1712 .build_pcms = simple_playback_build_pcms,
84eb01be 1713 .init = nvhdmi_7x_init,
3aaf8980 1714 .free = simple_playback_free,
84eb01be
TI		 1715};
1716
fb79e1e0 1717static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
3aaf8980
SW		 1718 .build_controls = simple_playback_build_controls,
1719 .build_pcms = simple_playback_build_pcms,
84eb01be 1720 .init = nvhdmi_7x_init,
3aaf8980 1721 .free = simple_playback_free,
84eb01be
TI		 1722};
1723
84eb01be
TI		 1724static int patch_nvhdmi_2ch(struct hda_codec *codec)
1725{
1726 struct hdmi_spec *spec;
1727
1728 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1729 if (spec == NULL)
1730 return -ENOMEM;
1731
1732 codec->spec = spec;
1733
1734 spec->multiout.num_dacs = 0; /* no analog */
1735 spec->multiout.max_channels = 2;
1736 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
84eb01be 1737 spec->num_cvts = 1;
384a48d7 1738 spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
84eb01be
TI		 1739 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1740
1741 codec->patch_ops = nvhdmi_patch_ops_2ch;
1742
1743 return 0;
1744}
1745
1746static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1747{
1748 struct hdmi_spec *spec;
1749 int err = patch_nvhdmi_2ch(codec);
1750
1751 if (err < 0)
1752 return err;
1753 spec = codec->spec;
1754 spec->multiout.max_channels = 8;
1755 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1756 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1f348522
AP		 1757
1758 /* Initialize the audio infoframe channel mask and checksum to something
1759 * valid */
1760 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1761
84eb01be
TI		 1762 return 0;
1763}
1764
1765/*
1766 * ATI-specific implementations
1767 *
1768 * FIXME: we may omit the whole this and use the generic code once after
1769 * it's confirmed to work.
1770 */
1771
1772#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1773#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1774
1775static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1776 struct hda_codec *codec,
1777 unsigned int stream_tag,
1778 unsigned int format,
1779 struct snd_pcm_substream *substream)
1780{
1781 struct hdmi_spec *spec = codec->spec;
1782 int chans = substream->runtime->channels;
1783 int i, err;
1784
1785 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1786 substream);
1787 if (err < 0)
1788 return err;
384a48d7
SW		 1789 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1790 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 1791 /* FIXME: XXX */
1792 for (i = 0; i < chans; i++) {
384a48d7 1793 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 1794 AC_VERB_SET_HDMI_CHAN_SLOT,
1795 (i << 4) | i);
1796 }
1797 return 0;
1798}
1799
fb79e1e0 1800static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
84eb01be
TI		 1801 .substreams = 1,
1802 .channels_min = 2,
1803 .channels_max = 2,
1804 .nid = ATIHDMI_CVT_NID,
1805 .ops = {
1806 .open = simple_playback_pcm_open,
1807 .close = simple_playback_pcm_close,
1808 .prepare = atihdmi_playback_pcm_prepare
1809 },
1810};
1811
fb79e1e0 1812static const struct hda_verb atihdmi_basic_init[] = {
84eb01be
TI		 1813 /* enable digital output on pin widget */
1814 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1815 {} /* terminator */
1816};
1817
1818static int atihdmi_init(struct hda_codec *codec)
1819{
1820 struct hdmi_spec *spec = codec->spec;
1821
1822 snd_hda_sequence_write(codec, atihdmi_basic_init);
1823 /* SI codec requires to unmute the pin */
384a48d7
SW		 1824 if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
1825 snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
84eb01be
TI		 1826 AC_VERB_SET_AMP_GAIN_MUTE,
1827 AMP_OUT_UNMUTE);
1828 return 0;
1829}
1830
fb79e1e0 1831static const struct hda_codec_ops atihdmi_patch_ops = {
3aaf8980
SW		 1832 .build_controls = simple_playback_build_controls,
1833 .build_pcms = simple_playback_build_pcms,
84eb01be 1834 .init = atihdmi_init,
3aaf8980 1835 .free = simple_playback_free,
84eb01be
TI		 1836};
1837
1838
1839static int patch_atihdmi(struct hda_codec *codec)
1840{
1841 struct hdmi_spec *spec;
1842
1843 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1844 if (spec == NULL)
1845 return -ENOMEM;
1846
1847 codec->spec = spec;
1848
1849 spec->multiout.num_dacs = 0; /* no analog */
1850 spec->multiout.max_channels = 2;
1851 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1852 spec->num_cvts = 1;
384a48d7
SW		 1853 spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
1854 spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
84eb01be
TI		 1855 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1856
1857 codec->patch_ops = atihdmi_patch_ops;
1858
1859 return 0;
1860}
1861
1862
1863/*
1864 * patch entries
1865 */
fb79e1e0 1866static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 1867{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1868{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1869{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1870{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1871{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1872{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1873{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1874{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1875{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1876{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1877{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1878{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 1879{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1880{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1881{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1882{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1883{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1884{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1885{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1886{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1887{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1888{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1889{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 1890/* 17 is known to be absent */
5d44f927
SW		 1891{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1892{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1893{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1894{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1895{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1896{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1897{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1898{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1899{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1900{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1901{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1902{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1903{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1904{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1905{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1906{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1907{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1908{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 1909{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1910{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1911{} /* terminator */
1912};
1913
1914MODULE_ALIAS("snd-hda-codec-id:1002793c");
1915MODULE_ALIAS("snd-hda-codec-id:10027919");
1916MODULE_ALIAS("snd-hda-codec-id:1002791a");
1917MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1918MODULE_ALIAS("snd-hda-codec-id:10951390");
1919MODULE_ALIAS("snd-hda-codec-id:10951392");
1920MODULE_ALIAS("snd-hda-codec-id:10de0002");
1921MODULE_ALIAS("snd-hda-codec-id:10de0003");
1922MODULE_ALIAS("snd-hda-codec-id:10de0005");
1923MODULE_ALIAS("snd-hda-codec-id:10de0006");
1924MODULE_ALIAS("snd-hda-codec-id:10de0007");
1925MODULE_ALIAS("snd-hda-codec-id:10de000a");
1926MODULE_ALIAS("snd-hda-codec-id:10de000b");
1927MODULE_ALIAS("snd-hda-codec-id:10de000c");
1928MODULE_ALIAS("snd-hda-codec-id:10de000d");
1929MODULE_ALIAS("snd-hda-codec-id:10de0010");
1930MODULE_ALIAS("snd-hda-codec-id:10de0011");
1931MODULE_ALIAS("snd-hda-codec-id:10de0012");
1932MODULE_ALIAS("snd-hda-codec-id:10de0013");
1933MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 1934MODULE_ALIAS("snd-hda-codec-id:10de0015");
1935MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 1936MODULE_ALIAS("snd-hda-codec-id:10de0018");
1937MODULE_ALIAS("snd-hda-codec-id:10de0019");
1938MODULE_ALIAS("snd-hda-codec-id:10de001a");
1939MODULE_ALIAS("snd-hda-codec-id:10de001b");
1940MODULE_ALIAS("snd-hda-codec-id:10de001c");
1941MODULE_ALIAS("snd-hda-codec-id:10de0040");
1942MODULE_ALIAS("snd-hda-codec-id:10de0041");
1943MODULE_ALIAS("snd-hda-codec-id:10de0042");
1944MODULE_ALIAS("snd-hda-codec-id:10de0043");
1945MODULE_ALIAS("snd-hda-codec-id:10de0044");
1946MODULE_ALIAS("snd-hda-codec-id:10de0067");
1947MODULE_ALIAS("snd-hda-codec-id:10de8001");
1948MODULE_ALIAS("snd-hda-codec-id:17e80047");
1949MODULE_ALIAS("snd-hda-codec-id:80860054");
1950MODULE_ALIAS("snd-hda-codec-id:80862801");
1951MODULE_ALIAS("snd-hda-codec-id:80862802");
1952MODULE_ALIAS("snd-hda-codec-id:80862803");
1953MODULE_ALIAS("snd-hda-codec-id:80862804");
1954MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 1955MODULE_ALIAS("snd-hda-codec-id:80862806");
84eb01be
TI		 1956MODULE_ALIAS("snd-hda-codec-id:808629fb");
1957
1958MODULE_LICENSE("GPL");
1959MODULE_DESCRIPTION("HDMI HD-audio codec");
1960MODULE_ALIAS("snd-hda-codec-intelhdmi");
1961MODULE_ALIAS("snd-hda-codec-nvhdmi");
1962MODULE_ALIAS("snd-hda-codec-atihdmi");
1963
1964static struct hda_codec_preset_list intel_list = {
1965 .preset = snd_hda_preset_hdmi,
1966 .owner = THIS_MODULE,
1967};
1968
1969static int __init patch_hdmi_init(void)
1970{
1971 return snd_hda_add_codec_preset(&intel_list);
1972}
1973
1974static void __exit patch_hdmi_exit(void)
1975{
1976 snd_hda_delete_codec_preset(&intel_list);
1977}
1978
1979module_init(patch_hdmi_init)
1980module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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