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Merge branch 'topic/hda-ca0132-dsp' into for-next
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
84eb01be
TI		 47/*
48 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 49 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 50 * more ports (DVI, HDMI or DisplayPort).
51 *
52 * The HDA correspondence of pipes/ports are converter/pin nodes.
53 */
a4567cb3
TI		 54#define MAX_HDMI_CVTS 8
55#define MAX_HDMI_PINS 8
079d88cc 56
384a48d7
SW		 57struct hdmi_spec_per_cvt {
58 hda_nid_t cvt_nid;
59 int assigned;
60 unsigned int channels_min;
61 unsigned int channels_max;
62 u32 rates;
63 u64 formats;
64 unsigned int maxbps;
65};
079d88cc 66
384a48d7
SW		 67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 71
72 struct hda_codec *codec;
384a48d7 73 struct hdmi_eld sink_eld;
744626da 74 struct delayed_work work;
c6e8453e 75 int repoll_count;
1a6003b5 76 bool non_pcm;
d45e6889
TI		 77 bool chmap_set; /* channel-map override by ALSA API? */
78 unsigned char chmap[8]; /* ALSA API channel-map */
384a48d7 79};
079d88cc 80
384a48d7
SW		 81struct hdmi_spec {
82 int num_cvts;
83 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 84
384a48d7
SW		 85 int num_pins;
86 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
87 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
d45e6889 88 unsigned int channels_max; /* max over all cvts */
079d88cc
WF		 89
90 /*
384a48d7 91 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 92 */
93 struct hda_multi_out multiout;
d0b1252d 94 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 95};
96
97
98struct hdmi_audio_infoframe {
99 u8 type; /* 0x84 */
100 u8 ver; /* 0x01 */
101 u8 len; /* 0x0a */
102
53d7d69d
WF		 103 u8 checksum;
104
079d88cc
WF		 105 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
106 u8 SS01_SF24;
107 u8 CXT04;
108 u8 CA;
109 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 110};
111
112struct dp_audio_infoframe {
113 u8 type; /* 0x84 */
114 u8 len; /* 0x1b */
115 u8 ver; /* 0x11 << 2 */
116
117 u8 CC02_CT47; /* match with HDMI infoframe from this on */
118 u8 SS01_SF24;
119 u8 CXT04;
120 u8 CA;
121 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 122};
123
2b203dbb
TI		 124union audio_infoframe {
125 struct hdmi_audio_infoframe hdmi;
126 struct dp_audio_infoframe dp;
127 u8 bytes[0];
128};
129
079d88cc
WF		 130/*
131 * CEA speaker placement:
132 *
133 * FLH FCH FRH
134 * FLW FL FLC FC FRC FR FRW
135 *
136 * LFE
137 * TC
138 *
139 * RL RLC RC RRC RR
140 *
141 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
142 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
143 */
144enum cea_speaker_placement {
145 FL = (1 << 0), /* Front Left */
146 FC = (1 << 1), /* Front Center */
147 FR = (1 << 2), /* Front Right */
148 FLC = (1 << 3), /* Front Left Center */
149 FRC = (1 << 4), /* Front Right Center */
150 RL = (1 << 5), /* Rear Left */
151 RC = (1 << 6), /* Rear Center */
152 RR = (1 << 7), /* Rear Right */
153 RLC = (1 << 8), /* Rear Left Center */
154 RRC = (1 << 9), /* Rear Right Center */
155 LFE = (1 << 10), /* Low Frequency Effect */
156 FLW = (1 << 11), /* Front Left Wide */
157 FRW = (1 << 12), /* Front Right Wide */
158 FLH = (1 << 13), /* Front Left High */
159 FCH = (1 << 14), /* Front Center High */
160 FRH = (1 << 15), /* Front Right High */
161 TC = (1 << 16), /* Top Center */
162};
163
164/*
165 * ELD SA bits in the CEA Speaker Allocation data block
166 */
167static int eld_speaker_allocation_bits[] = {
168 [0] = FL | FR,
169 [1] = LFE,
170 [2] = FC,
171 [3] = RL | RR,
172 [4] = RC,
173 [5] = FLC | FRC,
174 [6] = RLC | RRC,
175 /* the following are not defined in ELD yet */
176 [7] = FLW | FRW,
177 [8] = FLH | FRH,
178 [9] = TC,
179 [10] = FCH,
180};
181
182struct cea_channel_speaker_allocation {
183 int ca_index;
184 int speakers[8];
185
186 /* derived values, just for convenience */
187 int channels;
188 int spk_mask;
189};
190
191/*
192 * ALSA sequence is:
193 *
194 * surround40 surround41 surround50 surround51 surround71
195 * ch0 front left = = = =
196 * ch1 front right = = = =
197 * ch2 rear left = = = =
198 * ch3 rear right = = = =
199 * ch4 LFE center center center
200 * ch5 LFE LFE
201 * ch6 side left
202 * ch7 side right
203 *
204 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
205 */
206static int hdmi_channel_mapping[0x32][8] = {
207 /* stereo */
208 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
209 /* 2.1 */
210 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
211 /* Dolby Surround */
212 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
213 /* surround40 */
214 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
215 /* 4ch */
216 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
217 /* surround41 */
9396d317 218 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 219 /* surround50 */
220 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
221 /* surround51 */
222 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
223 /* 7.1 */
224 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
225};
226
227/*
228 * This is an ordered list!
229 *
230 * The preceding ones have better chances to be selected by
53d7d69d 231 * hdmi_channel_allocation().
079d88cc
WF		 232 */
233static struct cea_channel_speaker_allocation channel_allocations[] = {
234/* channel: 7 6 5 4 3 2 1 0 */
235{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
236 /* 2.1 */
237{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
238 /* Dolby Surround */
239{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
240 /* surround40 */
241{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
242 /* surround41 */
243{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
244 /* surround50 */
245{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
246 /* surround51 */
247{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
248 /* 6.1 */
249{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
250 /* surround71 */
251{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
252
253{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
254{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
255{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
256{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
257{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
258{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
262{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
263{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
264{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
265{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
266{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
267{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
268{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
269{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
270{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
271{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
272{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
273{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
274{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
275{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
276{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
281{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
282{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
283{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
284{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
285{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
286{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
288{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
289{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
290{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
294};
295
296
297/*
298 * HDMI routines
299 */
300
384a48d7 301static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 302{
384a48d7 303 int pin_idx;
079d88cc 304
384a48d7
SW		 305 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
306 if (spec->pins[pin_idx].pin_nid == pin_nid)
307 return pin_idx;
079d88cc 308
384a48d7
SW		 309 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
310 return -EINVAL;
311}
312
313static int hinfo_to_pin_index(struct hdmi_spec *spec,
314 struct hda_pcm_stream *hinfo)
315{
316 int pin_idx;
317
318 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
319 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
320 return pin_idx;
321
322 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
323 return -EINVAL;
324}
325
326static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
327{
328 int cvt_idx;
329
330 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
331 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
332 return cvt_idx;
333
334 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 335 return -EINVAL;
336}
337
14bc52b8
PLB		 338static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
339 struct snd_ctl_elem_info *uinfo)
340{
341 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
342 struct hdmi_spec *spec;
343 int pin_idx;
344
345 spec = codec->spec;
346 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
347
348 pin_idx = kcontrol->private_value;
349 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
350
351 return 0;
352}
353
354static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356{
357 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct hdmi_spec *spec;
359 int pin_idx;
360
361 spec = codec->spec;
362 pin_idx = kcontrol->private_value;
363
364 memcpy(ucontrol->value.bytes.data,
365 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
366
367 return 0;
368}
369
370static struct snd_kcontrol_new eld_bytes_ctl = {
371 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
372 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
373 .name = "ELD",
374 .info = hdmi_eld_ctl_info,
375 .get = hdmi_eld_ctl_get,
376};
377
378static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
379 int device)
380{
381 struct snd_kcontrol *kctl;
382 struct hdmi_spec *spec = codec->spec;
383 int err;
384
385 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
386 if (!kctl)
387 return -ENOMEM;
388 kctl->private_value = pin_idx;
389 kctl->id.device = device;
390
391 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
392 if (err < 0)
393 return err;
394
395 return 0;
396}
397
079d88cc
WF		 398#ifdef BE_PARANOID
399static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
400 int *packet_index, int *byte_index)
401{
402 int val;
403
404 val = snd_hda_codec_read(codec, pin_nid, 0,
405 AC_VERB_GET_HDMI_DIP_INDEX, 0);
406
407 *packet_index = val >> 5;
408 *byte_index = val & 0x1f;
409}
410#endif
411
412static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
413 int packet_index, int byte_index)
414{
415 int val;
416
417 val = (packet_index << 5) | (byte_index & 0x1f);
418
419 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
420}
421
422static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
423 unsigned char val)
424{
425 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
426}
427
384a48d7 428static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 429{
430 /* Unmute */
431 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
432 snd_hda_codec_write(codec, pin_nid, 0,
433 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 434 /* Enable pin out: some machines with GM965 gets broken output when
435 * the pin is disabled or changed while using with HDMI
436 */
079d88cc 437 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 438 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 439}
440
384a48d7 441static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 442{
384a48d7 443 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 444 AC_VERB_GET_CVT_CHAN_COUNT, 0);
445}
446
447static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 448 hda_nid_t cvt_nid, int chs)
079d88cc 449{
384a48d7
SW		 450 if (chs != hdmi_get_channel_count(codec, cvt_nid))
451 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 452 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
453}
454
455
456/*
457 * Channel mapping routines
458 */
459
460/*
461 * Compute derived values in channel_allocations[].
462 */
463static void init_channel_allocations(void)
464{
465 int i, j;
466 struct cea_channel_speaker_allocation *p;
467
468 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
469 p = channel_allocations + i;
470 p->channels = 0;
471 p->spk_mask = 0;
472 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
473 if (p->speakers[j]) {
474 p->channels++;
475 p->spk_mask |= p->speakers[j];
476 }
477 }
478}
479
72357c78
WX		 480static int get_channel_allocation_order(int ca)
481{
482 int i;
483
484 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
485 if (channel_allocations[i].ca_index == ca)
486 break;
487 }
488 return i;
489}
490
079d88cc
WF		 491/*
492 * The transformation takes two steps:
493 *
494 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
495 * spk_mask => (channel_allocations[]) => ai->CA
496 *
497 * TODO: it could select the wrong CA from multiple candidates.
498*/
384a48d7 499static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 500{
079d88cc 501 int i;
53d7d69d 502 int ca = 0;
079d88cc 503 int spk_mask = 0;
079d88cc
WF		 504 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
505
506 /*
507 * CA defaults to 0 for basic stereo audio
508 */
509 if (channels <= 2)
510 return 0;
511
079d88cc
WF		 512 /*
513 * expand ELD's speaker allocation mask
514 *
515 * ELD tells the speaker mask in a compact(paired) form,
516 * expand ELD's notions to match the ones used by Audio InfoFrame.
517 */
518 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
519 if (eld->spk_alloc & (1 << i))
520 spk_mask |= eld_speaker_allocation_bits[i];
521 }
522
523 /* search for the first working match in the CA table */
524 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
525 if (channels == channel_allocations[i].channels &&
526 (spk_mask & channel_allocations[i].spk_mask) ==
527 channel_allocations[i].spk_mask) {
53d7d69d 528 ca = channel_allocations[i].ca_index;
079d88cc
WF		 529 break;
530 }
531 }
532
533 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 534 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 535 ca, channels, buf);
079d88cc 536
53d7d69d 537 return ca;
079d88cc
WF		 538}
539
540static void hdmi_debug_channel_mapping(struct hda_codec *codec,
541 hda_nid_t pin_nid)
542{
543#ifdef CONFIG_SND_DEBUG_VERBOSE
544 int i;
545 int slot;
546
547 for (i = 0; i < 8; i++) {
548 slot = snd_hda_codec_read(codec, pin_nid, 0,
549 AC_VERB_GET_HDMI_CHAN_SLOT, i);
550 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
551 slot >> 4, slot & 0xf);
552 }
553#endif
554}
555
556
d45e6889 557static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 558 hda_nid_t pin_nid,
433968da 559 bool non_pcm,
53d7d69d 560 int ca)
079d88cc
WF		 561{
562 int i;
079d88cc 563 int err;
72357c78 564 int order;
433968da 565 int non_pcm_mapping[8];
079d88cc 566
72357c78 567 order = get_channel_allocation_order(ca);
433968da 568
079d88cc 569 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 570 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 571 hdmi_channel_mapping[ca][i] = i | (i << 4);
572 for (; i < 8; i++)
573 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
574 }
575
433968da
WX		 576 if (non_pcm) {
577 for (i = 0; i < channel_allocations[order].channels; i++)
578 non_pcm_mapping[i] = i | (i << 4);
579 for (; i < 8; i++)
580 non_pcm_mapping[i] = 0xf | (i << 4);
581 }
582
079d88cc
WF		 583 for (i = 0; i < 8; i++) {
584 err = snd_hda_codec_write(codec, pin_nid, 0,
585 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 586 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 587 if (err) {
2abbf439
WF		 588 snd_printdd(KERN_NOTICE
589 "HDMI: channel mapping failed\n");
079d88cc
WF		 590 break;
591 }
592 }
593
594 hdmi_debug_channel_mapping(codec, pin_nid);
595}
596
d45e6889
TI		 597struct channel_map_table {
598 unsigned char map; /* ALSA API channel map position */
599 unsigned char cea_slot; /* CEA slot value */
600 int spk_mask; /* speaker position bit mask */
601};
602
603static struct channel_map_table map_tables[] = {
604 { SNDRV_CHMAP_FL, 0x00, FL },
605 { SNDRV_CHMAP_FR, 0x01, FR },
606 { SNDRV_CHMAP_RL, 0x04, RL },
607 { SNDRV_CHMAP_RR, 0x05, RR },
608 { SNDRV_CHMAP_LFE, 0x02, LFE },
609 { SNDRV_CHMAP_FC, 0x03, FC },
610 { SNDRV_CHMAP_RLC, 0x06, RLC },
611 { SNDRV_CHMAP_RRC, 0x07, RRC },
612 {} /* terminator */
613};
614
615/* from ALSA API channel position to speaker bit mask */
616static int to_spk_mask(unsigned char c)
617{
618 struct channel_map_table *t = map_tables;
619 for (; t->map; t++) {
620 if (t->map == c)
621 return t->spk_mask;
622 }
623 return 0;
624}
625
626/* from ALSA API channel position to CEA slot */
627static int to_cea_slot(unsigned char c)
628{
629 struct channel_map_table *t = map_tables;
630 for (; t->map; t++) {
631 if (t->map == c)
632 return t->cea_slot;
633 }
634 return 0x0f;
635}
636
637/* from CEA slot to ALSA API channel position */
638static int from_cea_slot(unsigned char c)
639{
640 struct channel_map_table *t = map_tables;
641 for (; t->map; t++) {
642 if (t->cea_slot == c)
643 return t->map;
644 }
645 return 0;
646}
647
648/* from speaker bit mask to ALSA API channel position */
649static int spk_to_chmap(int spk)
650{
651 struct channel_map_table *t = map_tables;
652 for (; t->map; t++) {
653 if (t->spk_mask == spk)
654 return t->map;
655 }
656 return 0;
657}
658
659/* get the CA index corresponding to the given ALSA API channel map */
660static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
661{
662 int i, spks = 0, spk_mask = 0;
663
664 for (i = 0; i < chs; i++) {
665 int mask = to_spk_mask(map[i]);
666 if (mask) {
667 spk_mask |= mask;
668 spks++;
669 }
670 }
671
672 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
673 if ((chs == channel_allocations[i].channels ||
674 spks == channel_allocations[i].channels) &&
675 (spk_mask & channel_allocations[i].spk_mask) ==
676 channel_allocations[i].spk_mask)
677 return channel_allocations[i].ca_index;
678 }
679 return -1;
680}
681
682/* set up the channel slots for the given ALSA API channel map */
683static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
684 hda_nid_t pin_nid,
685 int chs, unsigned char *map)
686{
687 int i;
688 for (i = 0; i < 8; i++) {
689 int val, err;
690 if (i < chs)
691 val = to_cea_slot(map[i]);
692 else
693 val = 0xf;
694 val |= (i << 4);
695 err = snd_hda_codec_write(codec, pin_nid, 0,
696 AC_VERB_SET_HDMI_CHAN_SLOT, val);
697 if (err)
698 return -EINVAL;
699 }
700 return 0;
701}
702
703/* store ALSA API channel map from the current default map */
704static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
705{
706 int i;
707 for (i = 0; i < 8; i++) {
708 if (i < channel_allocations[ca].channels)
709 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
710 else
711 map[i] = 0;
712 }
713}
714
715static void hdmi_setup_channel_mapping(struct hda_codec *codec,
716 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 717 int channels, unsigned char *map,
718 bool chmap_set)
d45e6889 719{
20608731 720 if (!non_pcm && chmap_set) {
d45e6889
TI		 721 hdmi_manual_setup_channel_mapping(codec, pin_nid,
722 channels, map);
723 } else {
724 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
725 hdmi_setup_fake_chmap(map, ca);
726 }
727}
079d88cc
WF		 728
729/*
730 * Audio InfoFrame routines
731 */
732
733/*
734 * Enable Audio InfoFrame Transmission
735 */
736static void hdmi_start_infoframe_trans(struct hda_codec *codec,
737 hda_nid_t pin_nid)
738{
739 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
740 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
741 AC_DIPXMIT_BEST);
742}
743
744/*
745 * Disable Audio InfoFrame Transmission
746 */
747static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
748 hda_nid_t pin_nid)
749{
750 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
751 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
752 AC_DIPXMIT_DISABLE);
753}
754
755static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
756{
757#ifdef CONFIG_SND_DEBUG_VERBOSE
758 int i;
759 int size;
760
761 size = snd_hdmi_get_eld_size(codec, pin_nid);
762 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
763
764 for (i = 0; i < 8; i++) {
765 size = snd_hda_codec_read(codec, pin_nid, 0,
766 AC_VERB_GET_HDMI_DIP_SIZE, i);
767 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
768 }
769#endif
770}
771
772static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
773{
774#ifdef BE_PARANOID
775 int i, j;
776 int size;
777 int pi, bi;
778 for (i = 0; i < 8; i++) {
779 size = snd_hda_codec_read(codec, pin_nid, 0,
780 AC_VERB_GET_HDMI_DIP_SIZE, i);
781 if (size == 0)
782 continue;
783
784 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
785 for (j = 1; j < 1000; j++) {
786 hdmi_write_dip_byte(codec, pin_nid, 0x0);
787 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
788 if (pi != i)
789 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
790 bi, pi, i);
791 if (bi == 0) /* byte index wrapped around */
792 break;
793 }
794 snd_printd(KERN_INFO
795 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
796 i, size, j);
797 }
798#endif
799}
800
53d7d69d 801static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 802{
53d7d69d 803 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 804 u8 sum = 0;
805 int i;
806
53d7d69d 807 hdmi_ai->checksum = 0;
079d88cc 808
53d7d69d 809 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 810 sum += bytes[i];
811
53d7d69d 812 hdmi_ai->checksum = -sum;
079d88cc
WF		 813}
814
815static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
816 hda_nid_t pin_nid,
53d7d69d 817 u8 *dip, int size)
079d88cc 818{
079d88cc
WF		 819 int i;
820
821 hdmi_debug_dip_size(codec, pin_nid);
822 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
823
079d88cc 824 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 825 for (i = 0; i < size; i++)
826 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 827}
828
829static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 830 u8 *dip, int size)
079d88cc 831{
079d88cc
WF		 832 u8 val;
833 int i;
834
835 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
836 != AC_DIPXMIT_BEST)
837 return false;
838
839 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 840 for (i = 0; i < size; i++) {
079d88cc
WF		 841 val = snd_hda_codec_read(codec, pin_nid, 0,
842 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 843 if (val != dip[i])
079d88cc
WF		 844 return false;
845 }
846
847 return true;
848}
849
384a48d7 850static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 851 bool non_pcm,
852 struct snd_pcm_substream *substream)
079d88cc
WF		 853{
854 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 855 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
856 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 857 int channels = substream->runtime->channels;
384a48d7 858 struct hdmi_eld *eld;
53d7d69d 859 int ca;
2b203dbb 860 union audio_infoframe ai;
079d88cc 861
384a48d7
SW		 862 eld = &spec->pins[pin_idx].sink_eld;
863 if (!eld->monitor_present)
864 return;
079d88cc 865
d45e6889
TI		 866 if (!non_pcm && per_pin->chmap_set)
867 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
868 else
869 ca = hdmi_channel_allocation(eld, channels);
870 if (ca < 0)
871 ca = 0;
384a48d7
SW		 872
873 memset(&ai, 0, sizeof(ai));
874 if (eld->conn_type == 0) { /* HDMI */
875 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
876
877 hdmi_ai->type = 0x84;
878 hdmi_ai->ver = 0x01;
879 hdmi_ai->len = 0x0a;
880 hdmi_ai->CC02_CT47 = channels - 1;
881 hdmi_ai->CA = ca;
882 hdmi_checksum_audio_infoframe(hdmi_ai);
883 } else if (eld->conn_type == 1) { /* DisplayPort */
884 struct dp_audio_infoframe *dp_ai = &ai.dp;
885
886 dp_ai->type = 0x84;
887 dp_ai->len = 0x1b;
888 dp_ai->ver = 0x11 << 2;
889 dp_ai->CC02_CT47 = channels - 1;
890 dp_ai->CA = ca;
891 } else {
892 snd_printd("HDMI: unknown connection type at pin %d\n",
893 pin_nid);
894 return;
895 }
53d7d69d 896
384a48d7
SW		 897 /*
898 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
899 * sizeof(*dp_ai) to avoid partial match/update problems when
900 * the user switches between HDMI/DP monitors.
901 */
902 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
903 sizeof(ai))) {
904 snd_printdd("hdmi_setup_audio_infoframe: "
905 "pin=%d channels=%d\n",
906 pin_nid,
907 channels);
d45e6889 908 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 909 channels, per_pin->chmap,
910 per_pin->chmap_set);
384a48d7
SW		 911 hdmi_stop_infoframe_trans(codec, pin_nid);
912 hdmi_fill_audio_infoframe(codec, pin_nid,
913 ai.bytes, sizeof(ai));
914 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 915 } else {
916 /* For non-pcm audio switch, setup new channel mapping
917 * accordingly */
1a6003b5 918 if (per_pin->non_pcm != non_pcm)
d45e6889 919 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 920 channels, per_pin->chmap,
921 per_pin->chmap_set);
079d88cc 922 }
433968da 923
1a6003b5 924 per_pin->non_pcm = non_pcm;
079d88cc
WF		 925}
926
927
928/*
929 * Unsolicited events
930 */
931
c6e8453e 932static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 933
079d88cc
WF		 934static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
935{
936 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 937 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
938 int pin_nid;
384a48d7 939 int pin_idx;
3a93897e
TI		 940 struct hda_jack_tbl *jack;
941
942 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
943 if (!jack)
944 return;
945 pin_nid = jack->nid;
946 jack->jack_dirty = 1;
079d88cc 947
fae3d88a 948 _snd_printd(SND_PR_VERBOSE,
384a48d7 949 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 950 codec->addr, pin_nid,
951 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 952
384a48d7
SW		 953 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
954 if (pin_idx < 0)
079d88cc
WF		 955 return;
956
c6e8453e 957 hdmi_present_sense(&spec->pins[pin_idx], 1);
01a61e12 958 snd_hda_jack_report_sync(codec);
079d88cc
WF		 959}
960
961static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
962{
963 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
964 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
965 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
966 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
967
968 printk(KERN_INFO
e9ea8e8f 969 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 970 codec->addr,
079d88cc
WF		 971 tag,
972 subtag,
973 cp_state,
974 cp_ready);
975
976 /* TODO */
977 if (cp_state)
978 ;
979 if (cp_ready)
980 ;
981}
982
983
984static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
985{
079d88cc
WF		 986 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
987 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
988
3a93897e 989 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 990 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
991 return;
992 }
993
994 if (subtag == 0)
995 hdmi_intrinsic_event(codec, res);
996 else
997 hdmi_non_intrinsic_event(codec, res);
998}
999
1000/*
1001 * Callbacks
1002 */
1003
92f10b3f
TI		 1004/* HBR should be Non-PCM, 8 channels */
1005#define is_hbr_format(format) \
1006 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1007
384a48d7
SW		 1008static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1009 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1010{
ea87d1c4
AH		 1011 int pinctl;
1012 int new_pinctl = 0;
ea87d1c4 1013
384a48d7
SW		 1014 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1015 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1016 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1017
1018 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1019 if (is_hbr_format(format))
ea87d1c4
AH		 1020 new_pinctl |= AC_PINCTL_EPT_HBR;
1021 else
1022 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1023
1024 snd_printdd("hdmi_setup_stream: "
1025 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1026 pin_nid,
ea87d1c4
AH		 1027 pinctl == new_pinctl ? "" : "new-",
1028 new_pinctl);
1029
1030 if (pinctl != new_pinctl)
384a48d7 1031 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1032 AC_VERB_SET_PIN_WIDGET_CONTROL,
1033 new_pinctl);
ea87d1c4 1034
384a48d7 1035 }
92f10b3f 1036 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1037 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1038 return -EINVAL;
1039 }
079d88cc 1040
384a48d7 1041 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1042 return 0;
079d88cc
WF		 1043}
1044
bbbe3390
TI		 1045/*
1046 * HDA PCM callbacks
1047 */
1048static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1049 struct hda_codec *codec,
1050 struct snd_pcm_substream *substream)
1051{
1052 struct hdmi_spec *spec = codec->spec;
639cef0e 1053 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 1054 int pin_idx, cvt_idx, mux_idx = 0;
1055 struct hdmi_spec_per_pin *per_pin;
1056 struct hdmi_eld *eld;
1057 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 1058
384a48d7
SW		 1059 /* Validate hinfo */
1060 pin_idx = hinfo_to_pin_index(spec, hinfo);
1061 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 1062 return -EINVAL;
384a48d7
SW		 1063 per_pin = &spec->pins[pin_idx];
1064 eld = &per_pin->sink_eld;
1065
1066 /* Dynamically assign converter to stream */
1067 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1068 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 1069
384a48d7
SW		 1070 /* Must not already be assigned */
1071 if (per_cvt->assigned)
1072 continue;
1073 /* Must be in pin's mux's list of converters */
1074 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1075 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1076 break;
1077 /* Not in mux list */
1078 if (mux_idx == per_pin->num_mux_nids)
1079 continue;
1080 break;
1081 }
1082 /* No free converters */
1083 if (cvt_idx == spec->num_cvts)
1084 return -ENODEV;
1085
1086 /* Claim converter */
1087 per_cvt->assigned = 1;
1088 hinfo->nid = per_cvt->cvt_nid;
1089
1090 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1091 AC_VERB_SET_CONNECT_SEL,
1092 mux_idx);
384a48d7 1093 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1094
2def8172 1095 /* Initially set the converter's capabilities */
384a48d7
SW		 1096 hinfo->channels_min = per_cvt->channels_min;
1097 hinfo->channels_max = per_cvt->channels_max;
1098 hinfo->rates = per_cvt->rates;
1099 hinfo->formats = per_cvt->formats;
1100 hinfo->maxbps = per_cvt->maxbps;
2def8172 1101
384a48d7 1102 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1103 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 1104 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390 1105 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1106 !hinfo->rates || !hinfo->formats) {
1107 per_cvt->assigned = 0;
1108 hinfo->nid = 0;
1109 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1110 return -ENODEV;
2ad779b7 1111 }
bbbe3390 1112 }
2def8172
SW		 1113
1114 /* Store the updated parameters */
639cef0e
TI		 1115 runtime->hw.channels_min = hinfo->channels_min;
1116 runtime->hw.channels_max = hinfo->channels_max;
1117 runtime->hw.formats = hinfo->formats;
1118 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1119
1120 snd_pcm_hw_constraint_step(substream->runtime, 0,
1121 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1122 return 0;
1123}
1124
079d88cc
WF		 1125/*
1126 * HDA/HDMI auto parsing
1127 */
384a48d7 1128static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1129{
1130 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1131 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1132 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1133
1134 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1135 snd_printk(KERN_WARNING
1136 "HDMI: pin %d wcaps %#x "
1137 "does not support connection list\n",
1138 pin_nid, get_wcaps(codec, pin_nid));
1139 return -EINVAL;
1140 }
1141
384a48d7
SW		 1142 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1143 per_pin->mux_nids,
1144 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1145
1146 return 0;
1147}
1148
c6e8453e 1149static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1150{
744626da
WF		 1151 struct hda_codec *codec = per_pin->codec;
1152 struct hdmi_eld *eld = &per_pin->sink_eld;
1153 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1154 /*
1155 * Always execute a GetPinSense verb here, even when called from
1156 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1157 * response's PD bit is not the real PD value, but indicates that
1158 * the real PD value changed. An older version of the HD-audio
1159 * specification worked this way. Hence, we just ignore the data in
1160 * the unsolicited response to avoid custom WARs.
1161 */
079d88cc 1162 int present = snd_hda_pin_sense(codec, pin_nid);
b95d68b8 1163 bool eld_valid = false;
079d88cc 1164
b95d68b8 1165 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
5d44f927 1166
079d88cc 1167 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927 1168 if (eld->monitor_present)
b95d68b8 1169 eld_valid = !!(present & AC_PINSENSE_ELDV);
079d88cc 1170
fae3d88a 1171 _snd_printd(SND_PR_VERBOSE,
384a48d7 1172 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
b95d68b8 1173 codec->addr, pin_nid, eld->monitor_present, eld_valid);
5d44f927 1174
744626da 1175 if (eld_valid) {
5d44f927
SW		 1176 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
1177 snd_hdmi_show_eld(eld);
c6e8453e 1178 else if (repoll) {
744626da
WF		 1179 queue_delayed_work(codec->bus->workq,
1180 &per_pin->work,
1181 msecs_to_jiffies(300));
1182 }
1183 }
079d88cc
WF		 1184}
1185
744626da
WF		 1186static void hdmi_repoll_eld(struct work_struct *work)
1187{
1188 struct hdmi_spec_per_pin *per_pin =
1189 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1190
c6e8453e
WF		 1191 if (per_pin->repoll_count++ > 6)
1192 per_pin->repoll_count = 0;
1193
1194 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1195}
1196
079d88cc
WF		 1197static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1198{
1199 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1200 unsigned int caps, config;
1201 int pin_idx;
1202 struct hdmi_spec_per_pin *per_pin;
07acecc1 1203 int err;
079d88cc 1204
efc2f8de 1205 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1206 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1207 return 0;
1208
efc2f8de 1209 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1210 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1211 return 0;
1212
1213 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1214 return -E2BIG;
384a48d7
SW		 1215
1216 pin_idx = spec->num_pins;
1217 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1218
1219 per_pin->pin_nid = pin_nid;
1a6003b5 1220 per_pin->non_pcm = false;
079d88cc 1221
384a48d7
SW		 1222 err = hdmi_read_pin_conn(codec, pin_idx);
1223 if (err < 0)
1224 return err;
079d88cc 1225
079d88cc
WF		 1226 spec->num_pins++;
1227
384a48d7 1228 return 0;
079d88cc
WF		 1229}
1230
384a48d7 1231static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1232{
1233 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1234 int cvt_idx;
1235 struct hdmi_spec_per_cvt *per_cvt;
1236 unsigned int chans;
1237 int err;
079d88cc 1238
116dcde6
DH		 1239 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1240 return -E2BIG;
1241
384a48d7
SW		 1242 chans = get_wcaps(codec, cvt_nid);
1243 chans = get_wcaps_channels(chans);
1244
1245 cvt_idx = spec->num_cvts;
1246 per_cvt = &spec->cvts[cvt_idx];
1247
1248 per_cvt->cvt_nid = cvt_nid;
1249 per_cvt->channels_min = 2;
d45e6889 1250 if (chans <= 16) {
384a48d7 1251 per_cvt->channels_max = chans;
d45e6889
TI		 1252 if (chans > spec->channels_max)
1253 spec->channels_max = chans;
1254 }
384a48d7
SW		 1255
1256 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1257 &per_cvt->rates,
1258 &per_cvt->formats,
1259 &per_cvt->maxbps);
1260 if (err < 0)
1261 return err;
1262
079d88cc
WF		 1263 spec->num_cvts++;
1264
1265 return 0;
1266}
1267
1268static int hdmi_parse_codec(struct hda_codec *codec)
1269{
1270 hda_nid_t nid;
1271 int i, nodes;
1272
1273 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1274 if (!nid || nodes < 0) {
1275 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1276 return -EINVAL;
1277 }
1278
1279 for (i = 0; i < nodes; i++, nid++) {
1280 unsigned int caps;
1281 unsigned int type;
1282
efc2f8de 1283 caps = get_wcaps(codec, nid);
079d88cc
WF		 1284 type = get_wcaps_type(caps);
1285
1286 if (!(caps & AC_WCAP_DIGITAL))
1287 continue;
1288
1289 switch (type) {
1290 case AC_WID_AUD_OUT:
384a48d7 1291 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1292 break;
1293 case AC_WID_PIN:
3eaead57 1294 hdmi_add_pin(codec, nid);
079d88cc
WF		 1295 break;
1296 }
1297 }
1298
c9adeefd
DH		 1299#ifdef CONFIG_PM
1300 /* We're seeing some problems with unsolicited hot plug events on
1301 * PantherPoint after S3, if this is not enabled */
1302 if (codec->vendor_id == 0x80862806)
1303 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1304 /*
1305 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1306 * can be lost and presence sense verb will become inaccurate if the
1307 * HDA link is powered off at hot plug or hw initialization time.
1308 */
c9adeefd 1309 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1310 AC_PWRST_EPSS))
1311 codec->bus->power_keep_link_on = 1;
1312#endif
1313
1314 return 0;
1315}
1316
84eb01be
TI		 1317/*
1318 */
a4567cb3
TI		 1319static char *get_hdmi_pcm_name(int idx)
1320{
1321 static char names[MAX_HDMI_PINS][8];
1322 sprintf(&names[idx][0], "HDMI %d", idx);
1323 return &names[idx][0];
1324}
84eb01be 1325
1a6003b5
TI		 1326static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1327{
1328 struct hda_spdif_out *spdif;
1329 bool non_pcm;
1330
1331 mutex_lock(&codec->spdif_mutex);
1332 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1333 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1334 mutex_unlock(&codec->spdif_mutex);
1335 return non_pcm;
1336}
1337
1338
84eb01be
TI		 1339/*
1340 * HDMI callbacks
1341 */
1342
1343static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1344 struct hda_codec *codec,
1345 unsigned int stream_tag,
1346 unsigned int format,
1347 struct snd_pcm_substream *substream)
1348{
384a48d7
SW		 1349 hda_nid_t cvt_nid = hinfo->nid;
1350 struct hdmi_spec *spec = codec->spec;
1351 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1352 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1a6003b5
TI		 1353 bool non_pcm;
1354
1355 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1356
1357 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1358
1a6003b5 1359 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1360
384a48d7 1361 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1362}
1363
8dfaa573
TI		 1364static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1365 struct hda_codec *codec,
1366 struct snd_pcm_substream *substream)
1367{
1368 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1369 return 0;
1370}
1371
f2ad24fa
TI		 1372static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1373 struct hda_codec *codec,
1374 struct snd_pcm_substream *substream)
384a48d7
SW		 1375{
1376 struct hdmi_spec *spec = codec->spec;
1377 int cvt_idx, pin_idx;
1378 struct hdmi_spec_per_cvt *per_cvt;
1379 struct hdmi_spec_per_pin *per_pin;
384a48d7 1380
384a48d7
SW		 1381 if (hinfo->nid) {
1382 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1383 if (snd_BUG_ON(cvt_idx < 0))
1384 return -EINVAL;
1385 per_cvt = &spec->cvts[cvt_idx];
1386
1387 snd_BUG_ON(!per_cvt->assigned);
1388 per_cvt->assigned = 0;
1389 hinfo->nid = 0;
1390
1391 pin_idx = hinfo_to_pin_index(spec, hinfo);
1392 if (snd_BUG_ON(pin_idx < 0))
1393 return -EINVAL;
1394 per_pin = &spec->pins[pin_idx];
1395
384a48d7 1396 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1397 per_pin->chmap_set = false;
1398 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1399 }
d45e6889 1400
384a48d7
SW		 1401 return 0;
1402}
1403
1404static const struct hda_pcm_ops generic_ops = {
1405 .open = hdmi_pcm_open,
f2ad24fa 1406 .close = hdmi_pcm_close,
384a48d7 1407 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1408 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1409};
1410
d45e6889
TI		 1411/*
1412 * ALSA API channel-map control callbacks
1413 */
1414static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1415 struct snd_ctl_elem_info *uinfo)
1416{
1417 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1418 struct hda_codec *codec = info->private_data;
1419 struct hdmi_spec *spec = codec->spec;
1420 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1421 uinfo->count = spec->channels_max;
1422 uinfo->value.integer.min = 0;
1423 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1424 return 0;
1425}
1426
1427static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1428 unsigned int size, unsigned int __user *tlv)
1429{
1430 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1431 struct hda_codec *codec = info->private_data;
1432 struct hdmi_spec *spec = codec->spec;
1433 const unsigned int valid_mask =
1434 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1435 unsigned int __user *dst;
1436 int chs, count = 0;
1437
1438 if (size < 8)
1439 return -ENOMEM;
1440 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1441 return -EFAULT;
1442 size -= 8;
1443 dst = tlv + 2;
498dab3a 1444 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1445 int i, c;
1446 struct cea_channel_speaker_allocation *cap;
1447 cap = channel_allocations;
1448 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1449 int chs_bytes = chs * 4;
1450 if (cap->channels != chs)
1451 continue;
1452 if (cap->spk_mask & ~valid_mask)
1453 continue;
1454 if (size < 8)
1455 return -ENOMEM;
1456 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1457 put_user(chs_bytes, dst + 1))
1458 return -EFAULT;
1459 dst += 2;
1460 size -= 8;
1461 count += 8;
1462 if (size < chs_bytes)
1463 return -ENOMEM;
1464 size -= chs_bytes;
1465 count += chs_bytes;
1466 for (c = 7; c >= 0; c--) {
1467 int spk = cap->speakers[c];
1468 if (!spk)
1469 continue;
1470 if (put_user(spk_to_chmap(spk), dst))
1471 return -EFAULT;
1472 dst++;
1473 }
1474 }
1475 }
1476 if (put_user(count, tlv + 1))
1477 return -EFAULT;
1478 return 0;
1479}
1480
1481static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1482 struct snd_ctl_elem_value *ucontrol)
1483{
1484 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1485 struct hda_codec *codec = info->private_data;
1486 struct hdmi_spec *spec = codec->spec;
1487 int pin_idx = kcontrol->private_value;
1488 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1489 int i;
1490
1491 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1492 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1493 return 0;
1494}
1495
1496static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1497 struct snd_ctl_elem_value *ucontrol)
1498{
1499 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1500 struct hda_codec *codec = info->private_data;
1501 struct hdmi_spec *spec = codec->spec;
1502 int pin_idx = kcontrol->private_value;
1503 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1504 unsigned int ctl_idx;
1505 struct snd_pcm_substream *substream;
1506 unsigned char chmap[8];
1507 int i, ca, prepared = 0;
1508
1509 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1510 substream = snd_pcm_chmap_substream(info, ctl_idx);
1511 if (!substream || !substream->runtime)
6f54c361 1512 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1513 switch (substream->runtime->status->state) {
1514 case SNDRV_PCM_STATE_OPEN:
1515 case SNDRV_PCM_STATE_SETUP:
1516 break;
1517 case SNDRV_PCM_STATE_PREPARED:
1518 prepared = 1;
1519 break;
1520 default:
1521 return -EBUSY;
1522 }
1523 memset(chmap, 0, sizeof(chmap));
1524 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1525 chmap[i] = ucontrol->value.integer.value[i];
1526 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1527 return 0;
1528 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1529 if (ca < 0)
1530 return -EINVAL;
1531 per_pin->chmap_set = true;
1532 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1533 if (prepared)
1534 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1535 substream);
1536
1537 return 0;
1538}
1539
84eb01be
TI		 1540static int generic_hdmi_build_pcms(struct hda_codec *codec)
1541{
1542 struct hdmi_spec *spec = codec->spec;
384a48d7 1543 int pin_idx;
84eb01be 1544
384a48d7
SW		 1545 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1546 struct hda_pcm *info;
84eb01be
TI		 1547 struct hda_pcm_stream *pstr;
1548
384a48d7 1549 info = &spec->pcm_rec[pin_idx];
a4567cb3 1550 info->name = get_hdmi_pcm_name(pin_idx);
84eb01be 1551 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1552 info->own_chmap = true;
384a48d7 1553
84eb01be 1554 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1555 pstr->substreams = 1;
1556 pstr->ops = generic_ops;
1557 /* other pstr fields are set in open */
84eb01be
TI		 1558 }
1559
384a48d7
SW		 1560 codec->num_pcms = spec->num_pins;
1561 codec->pcm_info = spec->pcm_rec;
1562
84eb01be
TI		 1563 return 0;
1564}
1565
0b6c49b5
DH		 1566static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1567{
31ef2257 1568 char hdmi_str[32] = "HDMI/DP";
0b6c49b5
DH		 1569 struct hdmi_spec *spec = codec->spec;
1570 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1571 int pcmdev = spec->pcm_rec[pin_idx].device;
1572
31ef2257
TI		 1573 if (pcmdev > 0)
1574 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
0b6c49b5 1575
31ef2257 1576 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1577}
1578
84eb01be
TI		 1579static int generic_hdmi_build_controls(struct hda_codec *codec)
1580{
1581 struct hdmi_spec *spec = codec->spec;
1582 int err;
384a48d7 1583 int pin_idx;
84eb01be 1584
384a48d7
SW		 1585 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1586 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1587
1588 err = generic_hdmi_build_jack(codec, pin_idx);
1589 if (err < 0)
1590 return err;
1591
dcda5806
TI		 1592 err = snd_hda_create_dig_out_ctls(codec,
1593 per_pin->pin_nid,
1594 per_pin->mux_nids[0],
1595 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1596 if (err < 0)
1597 return err;
384a48d7 1598 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1599
1600 /* add control for ELD Bytes */
1601 err = hdmi_create_eld_ctl(codec,
1602 pin_idx,
1603 spec->pcm_rec[pin_idx].device);
1604
1605 if (err < 0)
1606 return err;
31ef2257 1607
82b1d73f 1608 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1609 }
1610
d45e6889
TI		 1611 /* add channel maps */
1612 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1613 struct snd_pcm_chmap *chmap;
1614 struct snd_kcontrol *kctl;
1615 int i;
1616 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1617 SNDRV_PCM_STREAM_PLAYBACK,
1618 NULL, 0, pin_idx, &chmap);
1619 if (err < 0)
1620 return err;
1621 /* override handlers */
1622 chmap->private_data = codec;
1623 kctl = chmap->kctl;
1624 for (i = 0; i < kctl->count; i++)
1625 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1626 kctl->info = hdmi_chmap_ctl_info;
1627 kctl->get = hdmi_chmap_ctl_get;
1628 kctl->put = hdmi_chmap_ctl_put;
1629 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1630 }
1631
84eb01be
TI		 1632 return 0;
1633}
1634
8b8d654b 1635static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1636{
1637 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1638 int pin_idx;
1639
1640 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1641 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
384a48d7 1642 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1643
744626da
WF		 1644 per_pin->codec = codec;
1645 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1646 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1647 }
8b8d654b
TI		 1648 return 0;
1649}
1650
1651static int generic_hdmi_init(struct hda_codec *codec)
1652{
1653 struct hdmi_spec *spec = codec->spec;
1654 int pin_idx;
1655
1656 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1657 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1658 hda_nid_t pin_nid = per_pin->pin_nid;
1659
1660 hdmi_init_pin(codec, pin_nid);
1661 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1662 }
84eb01be
TI		 1663 return 0;
1664}
1665
1666static void generic_hdmi_free(struct hda_codec *codec)
1667{
1668 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1669 int pin_idx;
1670
1671 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1672 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1673 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1674
744626da 1675 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1676 snd_hda_eld_proc_free(codec, eld);
1677 }
84eb01be 1678
744626da 1679 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1680 kfree(spec);
1681}
1682
fb79e1e0 1683static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1684 .init = generic_hdmi_init,
1685 .free = generic_hdmi_free,
1686 .build_pcms = generic_hdmi_build_pcms,
1687 .build_controls = generic_hdmi_build_controls,
1688 .unsol_event = hdmi_unsol_event,
1689};
1690
6ffe168f
ML		 1691static void intel_haswell_fixup_connect_list(struct hda_codec *codec)
1692{
1693 unsigned int vendor_param;
1694 hda_nid_t list[3] = {0x2, 0x3, 0x4};
1695
1696 vendor_param = snd_hda_codec_read(codec, 0x08, 0, 0xf81, 0);
1697 if (vendor_param == -1 || vendor_param & 0x02)
1698 return;
1699
1700 /* enable DP1.2 mode */
1701 vendor_param |= 0x02;
1702 snd_hda_codec_read(codec, 0x08, 0, 0x781, vendor_param);
1703
1704 vendor_param = snd_hda_codec_read(codec, 0x08, 0, 0xf81, 0);
1705 if (vendor_param == -1 || !(vendor_param & 0x02))
1706 return;
1707
1708 /* override 3 pins connection list */
1709 snd_hda_override_conn_list(codec, 0x05, 3, list);
1710 snd_hda_override_conn_list(codec, 0x06, 3, list);
1711 snd_hda_override_conn_list(codec, 0x07, 3, list);
1712}
1713
1714
84eb01be
TI		 1715static int patch_generic_hdmi(struct hda_codec *codec)
1716{
1717 struct hdmi_spec *spec;
84eb01be
TI		 1718
1719 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1720 if (spec == NULL)
1721 return -ENOMEM;
1722
1723 codec->spec = spec;
6ffe168f
ML		 1724
1725 if (codec->vendor_id == 0x80862807)
1726 intel_haswell_fixup_connect_list(codec);
1727
84eb01be
TI		 1728 if (hdmi_parse_codec(codec) < 0) {
1729 codec->spec = NULL;
1730 kfree(spec);
1731 return -EINVAL;
1732 }
1733 codec->patch_ops = generic_hdmi_patch_ops;
8b8d654b 1734 generic_hdmi_init_per_pins(codec);
84eb01be 1735
84eb01be
TI		 1736 init_channel_allocations();
1737
1738 return 0;
1739}
1740
3aaf8980
SW		 1741/*
1742 * Shared non-generic implementations
1743 */
1744
1745static int simple_playback_build_pcms(struct hda_codec *codec)
1746{
1747 struct hdmi_spec *spec = codec->spec;
1748 struct hda_pcm *info = spec->pcm_rec;
8ceb332d
TI		 1749 unsigned int chans;
1750 struct hda_pcm_stream *pstr;
3aaf8980 1751
8ceb332d 1752 codec->num_pcms = 1;
3aaf8980
SW		 1753 codec->pcm_info = info;
1754
8ceb332d
TI		 1755 chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
1756 chans = get_wcaps_channels(chans);
3aaf8980 1757
8ceb332d
TI		 1758 info->name = get_hdmi_pcm_name(0);
1759 info->pcm_type = HDA_PCM_TYPE_HDMI;
1760 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1761 *pstr = spec->pcm_playback;
1762 pstr->nid = spec->cvts[0].cvt_nid;
1763 if (pstr->channels_max <= 2 && chans && chans <= 16)
1764 pstr->channels_max = chans;
3aaf8980
SW		 1765
1766 return 0;
1767}
1768
4b6ace9e
TI		 1769/* unsolicited event for jack sensing */
1770static void simple_hdmi_unsol_event(struct hda_codec *codec,
1771 unsigned int res)
1772{
9dd8cf12 1773 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 1774 snd_hda_jack_report_sync(codec);
1775}
1776
1777/* generic_hdmi_build_jack can be used for simple_hdmi, too,
1778 * as long as spec->pins[] is set correctly
1779 */
1780#define simple_hdmi_build_jack generic_hdmi_build_jack
1781
3aaf8980
SW		 1782static int simple_playback_build_controls(struct hda_codec *codec)
1783{
1784 struct hdmi_spec *spec = codec->spec;
1785 int err;
3aaf8980 1786
8ceb332d
TI		 1787 err = snd_hda_create_spdif_out_ctls(codec,
1788 spec->cvts[0].cvt_nid,
1789 spec->cvts[0].cvt_nid);
1790 if (err < 0)
1791 return err;
1792 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 1793}
1794
4f0110ce
TI		 1795static int simple_playback_init(struct hda_codec *codec)
1796{
1797 struct hdmi_spec *spec = codec->spec;
8ceb332d
TI		 1798 hda_nid_t pin = spec->pins[0].pin_nid;
1799
1800 snd_hda_codec_write(codec, pin, 0,
1801 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
1802 /* some codecs require to unmute the pin */
1803 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
1804 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1805 AMP_OUT_UNMUTE);
1806 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 1807 return 0;
1808}
1809
3aaf8980
SW		 1810static void simple_playback_free(struct hda_codec *codec)
1811{
1812 struct hdmi_spec *spec = codec->spec;
1813
1814 kfree(spec);
1815}
1816
84eb01be
TI		 1817/*
1818 * Nvidia specific implementations
1819 */
1820
1821#define Nv_VERB_SET_Channel_Allocation 0xF79
1822#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1823#define Nv_VERB_SET_Audio_Protection_On 0xF98
1824#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1825
1826#define nvhdmi_master_con_nid_7x 0x04
1827#define nvhdmi_master_pin_nid_7x 0x05
1828
fb79e1e0 1829static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1830 /*front, rear, clfe, rear_surr */
1831 0x6, 0x8, 0xa, 0xc,
1832};
1833
ceaa86ba
TI		 1834static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
1835 /* set audio protect on */
1836 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1837 /* enable digital output on pin widget */
1838 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1839 {} /* terminator */
1840};
1841
1842static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 1843 /* set audio protect on */
1844 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1845 /* enable digital output on pin widget */
1846 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1847 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1848 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1849 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1850 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1851 {} /* terminator */
1852};
1853
1854#ifdef LIMITED_RATE_FMT_SUPPORT
1855/* support only the safe format and rate */
1856#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1857#define SUPPORTED_MAXBPS 16
1858#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1859#else
1860/* support all rates and formats */
1861#define SUPPORTED_RATES \
1862 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1863 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1864 SNDRV_PCM_RATE_192000)
1865#define SUPPORTED_MAXBPS 24
1866#define SUPPORTED_FORMATS \
1867 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1868#endif
1869
ceaa86ba
TI		 1870static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
1871{
1872 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
1873 return 0;
1874}
1875
1876static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 1877{
ceaa86ba 1878 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 1879 return 0;
1880}
1881
393004b2
ND		 1882static unsigned int channels_2_6_8[] = {
1883 2, 6, 8
1884};
1885
1886static unsigned int channels_2_8[] = {
1887 2, 8
1888};
1889
1890static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1891 .count = ARRAY_SIZE(channels_2_6_8),
1892 .list = channels_2_6_8,
1893 .mask = 0,
1894};
1895
1896static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1897 .count = ARRAY_SIZE(channels_2_8),
1898 .list = channels_2_8,
1899 .mask = 0,
1900};
1901
84eb01be
TI		 1902static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1903 struct hda_codec *codec,
1904 struct snd_pcm_substream *substream)
1905{
1906 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1907 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1908
1909 switch (codec->preset->id) {
1910 case 0x10de0002:
1911 case 0x10de0003:
1912 case 0x10de0005:
1913 case 0x10de0006:
1914 hw_constraints_channels = &hw_constraints_2_8_channels;
1915 break;
1916 case 0x10de0007:
1917 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1918 break;
1919 default:
1920 break;
1921 }
1922
1923 if (hw_constraints_channels != NULL) {
1924 snd_pcm_hw_constraint_list(substream->runtime, 0,
1925 SNDRV_PCM_HW_PARAM_CHANNELS,
1926 hw_constraints_channels);
ad09fc9d
TI		 1927 } else {
1928 snd_pcm_hw_constraint_step(substream->runtime, 0,
1929 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1930 }
1931
84eb01be
TI		 1932 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1933}
1934
1935static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1936 struct hda_codec *codec,
1937 struct snd_pcm_substream *substream)
1938{
1939 struct hdmi_spec *spec = codec->spec;
1940 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1941}
1942
1943static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1944 struct hda_codec *codec,
1945 unsigned int stream_tag,
1946 unsigned int format,
1947 struct snd_pcm_substream *substream)
1948{
1949 struct hdmi_spec *spec = codec->spec;
1950 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1951 stream_tag, format, substream);
1952}
1953
d0b1252d
TI		 1954static const struct hda_pcm_stream simple_pcm_playback = {
1955 .substreams = 1,
1956 .channels_min = 2,
1957 .channels_max = 2,
1958 .ops = {
1959 .open = simple_playback_pcm_open,
1960 .close = simple_playback_pcm_close,
1961 .prepare = simple_playback_pcm_prepare
1962 },
1963};
1964
1965static const struct hda_codec_ops simple_hdmi_patch_ops = {
1966 .build_controls = simple_playback_build_controls,
1967 .build_pcms = simple_playback_build_pcms,
1968 .init = simple_playback_init,
1969 .free = simple_playback_free,
250e41ac 1970 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 1971};
1972
1973static int patch_simple_hdmi(struct hda_codec *codec,
1974 hda_nid_t cvt_nid, hda_nid_t pin_nid)
1975{
1976 struct hdmi_spec *spec;
1977
1978 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1979 if (!spec)
1980 return -ENOMEM;
1981
1982 codec->spec = spec;
1983
1984 spec->multiout.num_dacs = 0; /* no analog */
1985 spec->multiout.max_channels = 2;
1986 spec->multiout.dig_out_nid = cvt_nid;
1987 spec->num_cvts = 1;
1988 spec->num_pins = 1;
1989 spec->cvts[0].cvt_nid = cvt_nid;
21cd683d 1990 spec->pins[0].pin_nid = pin_nid;
d0b1252d
TI		 1991 spec->pcm_playback = simple_pcm_playback;
1992
1993 codec->patch_ops = simple_hdmi_patch_ops;
1994
1995 return 0;
1996}
1997
1f348522
AP		 1998static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1999 int channels)
2000{
2001 unsigned int chanmask;
2002 int chan = channels ? (channels - 1) : 1;
2003
2004 switch (channels) {
2005 default:
2006 case 0:
2007 case 2:
2008 chanmask = 0x00;
2009 break;
2010 case 4:
2011 chanmask = 0x08;
2012 break;
2013 case 6:
2014 chanmask = 0x0b;
2015 break;
2016 case 8:
2017 chanmask = 0x13;
2018 break;
2019 }
2020
2021 /* Set the audio infoframe channel allocation and checksum fields. The
2022 * channel count is computed implicitly by the hardware. */
2023 snd_hda_codec_write(codec, 0x1, 0,
2024 Nv_VERB_SET_Channel_Allocation, chanmask);
2025
2026 snd_hda_codec_write(codec, 0x1, 0,
2027 Nv_VERB_SET_Info_Frame_Checksum,
2028 (0x71 - chan - chanmask));
2029}
2030
84eb01be
TI		 2031static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2032 struct hda_codec *codec,
2033 struct snd_pcm_substream *substream)
2034{
2035 struct hdmi_spec *spec = codec->spec;
2036 int i;
2037
2038 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2039 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2040 for (i = 0; i < 4; i++) {
2041 /* set the stream id */
2042 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2043 AC_VERB_SET_CHANNEL_STREAMID, 0);
2044 /* set the stream format */
2045 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2046 AC_VERB_SET_STREAM_FORMAT, 0);
2047 }
2048
1f348522
AP		 2049 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2050 * streams are disabled. */
2051 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2052
84eb01be
TI		 2053 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2054}
2055
2056static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2057 struct hda_codec *codec,
2058 unsigned int stream_tag,
2059 unsigned int format,
2060 struct snd_pcm_substream *substream)
2061{
2062 int chs;
112daa7a 2063 unsigned int dataDCC2, channel_id;
84eb01be 2064 int i;
7c935976 2065 struct hdmi_spec *spec = codec->spec;
e3245cdd 2066 struct hda_spdif_out *spdif;
84eb01be
TI		 2067
2068 mutex_lock(&codec->spdif_mutex);
e3245cdd 2069 spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 2070
2071 chs = substream->runtime->channels;
84eb01be 2072
84eb01be
TI		 2073 dataDCC2 = 0x2;
2074
84eb01be 2075 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2076 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2077 snd_hda_codec_write(codec,
2078 nvhdmi_master_con_nid_7x,
2079 0,
2080 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2081 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2082
2083 /* set the stream id */
2084 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2085 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2086
2087 /* set the stream format */
2088 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2089 AC_VERB_SET_STREAM_FORMAT, format);
2090
2091 /* turn on again (if needed) */
2092 /* enable and set the channel status audio/data flag */
7c935976 2093 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2094 snd_hda_codec_write(codec,
2095 nvhdmi_master_con_nid_7x,
2096 0,
2097 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2098 spdif->ctls & 0xff);
84eb01be
TI		 2099 snd_hda_codec_write(codec,
2100 nvhdmi_master_con_nid_7x,
2101 0,
2102 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2103 }
2104
2105 for (i = 0; i < 4; i++) {
2106 if (chs == 2)
2107 channel_id = 0;
2108 else
2109 channel_id = i * 2;
2110
2111 /* turn off SPDIF once;
2112 *otherwise the IEC958 bits won't be updated
2113 */
2114 if (codec->spdif_status_reset &&
7c935976 2115 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2116 snd_hda_codec_write(codec,
2117 nvhdmi_con_nids_7x[i],
2118 0,
2119 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2120 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2121 /* set the stream id */
2122 snd_hda_codec_write(codec,
2123 nvhdmi_con_nids_7x[i],
2124 0,
2125 AC_VERB_SET_CHANNEL_STREAMID,
2126 (stream_tag << 4) | channel_id);
2127 /* set the stream format */
2128 snd_hda_codec_write(codec,
2129 nvhdmi_con_nids_7x[i],
2130 0,
2131 AC_VERB_SET_STREAM_FORMAT,
2132 format);
2133 /* turn on again (if needed) */
2134 /* enable and set the channel status audio/data flag */
2135 if (codec->spdif_status_reset &&
7c935976 2136 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2137 snd_hda_codec_write(codec,
2138 nvhdmi_con_nids_7x[i],
2139 0,
2140 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2141 spdif->ctls & 0xff);
84eb01be
TI		 2142 snd_hda_codec_write(codec,
2143 nvhdmi_con_nids_7x[i],
2144 0,
2145 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2146 }
2147 }
2148
1f348522 2149 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2150
2151 mutex_unlock(&codec->spdif_mutex);
2152 return 0;
2153}
2154
fb79e1e0 2155static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2156 .substreams = 1,
2157 .channels_min = 2,
2158 .channels_max = 8,
2159 .nid = nvhdmi_master_con_nid_7x,
2160 .rates = SUPPORTED_RATES,
2161 .maxbps = SUPPORTED_MAXBPS,
2162 .formats = SUPPORTED_FORMATS,
2163 .ops = {
2164 .open = simple_playback_pcm_open,
2165 .close = nvhdmi_8ch_7x_pcm_close,
2166 .prepare = nvhdmi_8ch_7x_pcm_prepare
2167 },
2168};
2169
84eb01be
TI		 2170static int patch_nvhdmi_2ch(struct hda_codec *codec)
2171{
2172 struct hdmi_spec *spec;
d0b1252d
TI		 2173 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2174 nvhdmi_master_pin_nid_7x);
2175 if (err < 0)
2176 return err;
84eb01be 2177
ceaa86ba 2178 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2179 /* override the PCM rates, etc, as the codec doesn't give full list */
2180 spec = codec->spec;
2181 spec->pcm_playback.rates = SUPPORTED_RATES;
2182 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2183 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2184 return 0;
2185}
2186
53775b0d
TI		 2187static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2188{
2189 struct hdmi_spec *spec = codec->spec;
2190 int err = simple_playback_build_pcms(codec);
2191 spec->pcm_rec[0].own_chmap = true;
2192 return err;
2193}
2194
2195static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2196{
2197 struct hdmi_spec *spec = codec->spec;
2198 struct snd_pcm_chmap *chmap;
2199 int err;
2200
2201 err = simple_playback_build_controls(codec);
2202 if (err < 0)
2203 return err;
2204
2205 /* add channel maps */
2206 err = snd_pcm_add_chmap_ctls(spec->pcm_rec[0].pcm,
2207 SNDRV_PCM_STREAM_PLAYBACK,
2208 snd_pcm_alt_chmaps, 8, 0, &chmap);
2209 if (err < 0)
2210 return err;
2211 switch (codec->preset->id) {
2212 case 0x10de0002:
2213 case 0x10de0003:
2214 case 0x10de0005:
2215 case 0x10de0006:
2216 chmap->channel_mask = (1U << 2) | (1U << 8);
2217 break;
2218 case 0x10de0007:
2219 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2220 }
2221 return 0;
2222}
2223
84eb01be
TI		 2224static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2225{
2226 struct hdmi_spec *spec;
2227 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2228 if (err < 0)
2229 return err;
2230 spec = codec->spec;
2231 spec->multiout.max_channels = 8;
d0b1252d 2232 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2233 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2234 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2235 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2236
2237 /* Initialize the audio infoframe channel mask and checksum to something
2238 * valid */
2239 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2240
84eb01be
TI		 2241 return 0;
2242}
2243
2244/*
2245 * ATI-specific implementations
2246 *
2247 * FIXME: we may omit the whole this and use the generic code once after
2248 * it's confirmed to work.
2249 */
2250
2251#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2252#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2253
2254static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2255 struct hda_codec *codec,
2256 unsigned int stream_tag,
2257 unsigned int format,
2258 struct snd_pcm_substream *substream)
2259{
2260 struct hdmi_spec *spec = codec->spec;
2261 int chans = substream->runtime->channels;
2262 int i, err;
2263
2264 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2265 substream);
2266 if (err < 0)
2267 return err;
384a48d7
SW		 2268 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
2269 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2270 /* FIXME: XXX */
2271 for (i = 0; i < chans; i++) {
384a48d7 2272 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 2273 AC_VERB_SET_HDMI_CHAN_SLOT,
2274 (i << 4) | i);
2275 }
2276 return 0;
2277}
2278
84eb01be
TI		 2279static int patch_atihdmi(struct hda_codec *codec)
2280{
2281 struct hdmi_spec *spec;
d0b1252d
TI		 2282 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2283 if (err < 0)
2284 return err;
2285 spec = codec->spec;
2286 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2287 return 0;
2288}
2289
3de5ff88
AL		 2290/* VIA HDMI Implementation */
2291#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2292#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2293
3de5ff88
AL		 2294static int patch_via_hdmi(struct hda_codec *codec)
2295{
250e41ac 2296 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2297}
84eb01be
TI		 2298
2299/*
2300 * patch entries
2301 */
fb79e1e0 2302static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2303{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2304{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2305{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2306{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2307{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2308{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2309{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2310{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2311{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2312{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2313{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2314{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2315{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2316{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2317{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2318{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2319{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2320{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2321{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2322{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2323{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2324{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2325{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2326/* 17 is known to be absent */
5d44f927
SW		 2327{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2328{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2329{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2330{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2331{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2332{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2333{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2334{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2335{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2336{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2337{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2338{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2339{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2340{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2341{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2342{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2343{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2344{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2345{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2346{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2347{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2348{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2349{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2350{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2351{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2352{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2353{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2354{} /* terminator */
2355};
2356
2357MODULE_ALIAS("snd-hda-codec-id:1002793c");
2358MODULE_ALIAS("snd-hda-codec-id:10027919");
2359MODULE_ALIAS("snd-hda-codec-id:1002791a");
2360MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2361MODULE_ALIAS("snd-hda-codec-id:10951390");
2362MODULE_ALIAS("snd-hda-codec-id:10951392");
2363MODULE_ALIAS("snd-hda-codec-id:10de0002");
2364MODULE_ALIAS("snd-hda-codec-id:10de0003");
2365MODULE_ALIAS("snd-hda-codec-id:10de0005");
2366MODULE_ALIAS("snd-hda-codec-id:10de0006");
2367MODULE_ALIAS("snd-hda-codec-id:10de0007");
2368MODULE_ALIAS("snd-hda-codec-id:10de000a");
2369MODULE_ALIAS("snd-hda-codec-id:10de000b");
2370MODULE_ALIAS("snd-hda-codec-id:10de000c");
2371MODULE_ALIAS("snd-hda-codec-id:10de000d");
2372MODULE_ALIAS("snd-hda-codec-id:10de0010");
2373MODULE_ALIAS("snd-hda-codec-id:10de0011");
2374MODULE_ALIAS("snd-hda-codec-id:10de0012");
2375MODULE_ALIAS("snd-hda-codec-id:10de0013");
2376MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2377MODULE_ALIAS("snd-hda-codec-id:10de0015");
2378MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2379MODULE_ALIAS("snd-hda-codec-id:10de0018");
2380MODULE_ALIAS("snd-hda-codec-id:10de0019");
2381MODULE_ALIAS("snd-hda-codec-id:10de001a");
2382MODULE_ALIAS("snd-hda-codec-id:10de001b");
2383MODULE_ALIAS("snd-hda-codec-id:10de001c");
2384MODULE_ALIAS("snd-hda-codec-id:10de0040");
2385MODULE_ALIAS("snd-hda-codec-id:10de0041");
2386MODULE_ALIAS("snd-hda-codec-id:10de0042");
2387MODULE_ALIAS("snd-hda-codec-id:10de0043");
2388MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2389MODULE_ALIAS("snd-hda-codec-id:10de0051");
84eb01be
TI		 2390MODULE_ALIAS("snd-hda-codec-id:10de0067");
2391MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2392MODULE_ALIAS("snd-hda-codec-id:11069f80");
2393MODULE_ALIAS("snd-hda-codec-id:11069f81");
2394MODULE_ALIAS("snd-hda-codec-id:11069f84");
2395MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2396MODULE_ALIAS("snd-hda-codec-id:17e80047");
2397MODULE_ALIAS("snd-hda-codec-id:80860054");
2398MODULE_ALIAS("snd-hda-codec-id:80862801");
2399MODULE_ALIAS("snd-hda-codec-id:80862802");
2400MODULE_ALIAS("snd-hda-codec-id:80862803");
2401MODULE_ALIAS("snd-hda-codec-id:80862804");
2402MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2403MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2404MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2405MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2406MODULE_ALIAS("snd-hda-codec-id:808629fb");
2407
2408MODULE_LICENSE("GPL");
2409MODULE_DESCRIPTION("HDMI HD-audio codec");
2410MODULE_ALIAS("snd-hda-codec-intelhdmi");
2411MODULE_ALIAS("snd-hda-codec-nvhdmi");
2412MODULE_ALIAS("snd-hda-codec-atihdmi");
2413
2414static struct hda_codec_preset_list intel_list = {
2415 .preset = snd_hda_preset_hdmi,
2416 .owner = THIS_MODULE,
2417};
2418
2419static int __init patch_hdmi_init(void)
2420{
2421 return snd_hda_add_codec_preset(&intel_list);
2422}
2423
2424static void __exit patch_hdmi_exit(void)
2425{
2426 snd_hda_delete_codec_preset(&intel_list);
2427}
2428
2429module_init(patch_hdmi_init)
2430module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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